Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33461

1

T1

22

T2

36

T3

18

auto[1]

316

1

T114

8

T115

9

T116

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33474	1			T1	22		T2	36		T3	18
auto[134217728:268435455]	6	1			T116	1		T201	1		T352	1
auto[268435456:402653183]	18	1			T114	1		T320	1		T150	1
auto[402653184:536870911]	9	1			T320	2		T415	1		T346	1
auto[536870912:671088639]	9	1			T114	1		T130	1		T272	1
auto[671088640:805306367]	7	1			T201	1		T377	1		T346	1
auto[805306368:939524095]	7	1			T155	1		T385	1		T377	1
auto[939524096:1073741823]	7	1			T114	1		T385	1		T377	1
auto[1073741824:1207959551]	3	1			T415	1		T416	1		T266	1
auto[1207959552:1342177279]	11	1			T115	1		T385	1		T257	1
auto[1342177280:1476395007]	16	1			T155	1		T130	1		T385	1
auto[1476395008:1610612735]	6	1			T385	1		T415	1		T288	1
auto[1610612736:1744830463]	10	1			T114	1		T385	1		T282	1
auto[1744830464:1879048191]	11	1			T115	1		T385	3		T272	2
auto[1879048192:2013265919]	11	1			T114	1		T130	1		T272	1
auto[2013265920:2147483647]	9	1			T115	1		T352	1		T346	1
auto[2147483648:2281701375]	13	1			T115	2		T147	1		T272	1
auto[2281701376:2415919103]	5	1			T288	1		T417	2		T392	1
auto[2415919104:2550136831]	8	1			T147	1		T385	1		T377	1
auto[2550136832:2684354559]	10	1			T115	2		T385	1		T257	1
auto[2684354560:2818572287]	14	1			T147	1		T206	1		T194	1
auto[2818572288:2952790015]	7	1			T385	1		T201	1		T418	1
auto[2952790016:3087007743]	8	1			T147	1		T257	1		T377	1
auto[3087007744:3221225471]	16	1			T147	1		T257	2		T272	1
auto[3221225472:3355443199]	11	1			T115	1		T150	1		T201	1
auto[3355443200:3489660927]	7	1			T114	1		T115	1		T206	1
auto[3489660928:3623878655]	8	1			T320	1		T206	2		T419	1
auto[3623878656:3758096383]	12	1			T147	1		T385	1		T257	1
auto[3758096384:3892314111]	10	1			T114	1		T155	1		T320	1
auto[3892314112:4026531839]	12	1			T114	1		T116	1		T155	1
auto[4026531840:4160749567]	11	1			T320	1		T149	1		T257	1
auto[4160749568:4294967295]	11	1			T206	2		T257	1		T377	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33461	1			T1	22		T2	36		T3	18
auto[0:134217727]	auto[1]	13	1			T149	1		T206	1		T257	1
auto[134217728:268435455]	auto[1]	6	1			T116	1		T201	1		T352	1
auto[268435456:402653183]	auto[1]	18	1			T114	1		T320	1		T150	1
auto[402653184:536870911]	auto[1]	9	1			T320	2		T415	1		T346	1
auto[536870912:671088639]	auto[1]	9	1			T114	1		T130	1		T272	1
auto[671088640:805306367]	auto[1]	7	1			T201	1		T377	1		T346	1
auto[805306368:939524095]	auto[1]	7	1			T155	1		T385	1		T377	1
auto[939524096:1073741823]	auto[1]	7	1			T114	1		T385	1		T377	1
auto[1073741824:1207959551]	auto[1]	3	1			T415	1		T416	1		T266	1
auto[1207959552:1342177279]	auto[1]	11	1			T115	1		T385	1		T257	1
auto[1342177280:1476395007]	auto[1]	16	1			T155	1		T130	1		T385	1
auto[1476395008:1610612735]	auto[1]	6	1			T385	1		T415	1		T288	1
auto[1610612736:1744830463]	auto[1]	10	1			T114	1		T385	1		T282	1
auto[1744830464:1879048191]	auto[1]	11	1			T115	1		T385	3		T272	2
auto[1879048192:2013265919]	auto[1]	11	1			T114	1		T130	1		T272	1
auto[2013265920:2147483647]	auto[1]	9	1			T115	1		T352	1		T346	1
auto[2147483648:2281701375]	auto[1]	13	1			T115	2		T147	1		T272	1
auto[2281701376:2415919103]	auto[1]	5	1			T288	1		T417	2		T392	1
auto[2415919104:2550136831]	auto[1]	8	1			T147	1		T385	1		T377	1
auto[2550136832:2684354559]	auto[1]	10	1			T115	2		T385	1		T257	1
auto[2684354560:2818572287]	auto[1]	14	1			T147	1		T206	1		T194	1
auto[2818572288:2952790015]	auto[1]	7	1			T385	1		T201	1		T418	1
auto[2952790016:3087007743]	auto[1]	8	1			T147	1		T257	1		T377	1
auto[3087007744:3221225471]	auto[1]	16	1			T147	1		T257	2		T272	1
auto[3221225472:3355443199]	auto[1]	11	1			T115	1		T150	1		T201	1
auto[3355443200:3489660927]	auto[1]	7	1			T114	1		T115	1		T206	1
auto[3489660928:3623878655]	auto[1]	8	1			T320	1		T206	2		T419	1
auto[3623878656:3758096383]	auto[1]	12	1			T147	1		T385	1		T257	1
auto[3758096384:3892314111]	auto[1]	10	1			T114	1		T155	1		T320	1
auto[3892314112:4026531839]	auto[1]	12	1			T114	1		T116	1		T155	1
auto[4026531840:4160749567]	auto[1]	11	1			T320	1		T149	1		T257	1
auto[4160749568:4294967295]	auto[1]	11	1			T206	2		T257	1		T377	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1566

1

T3

3

T26

3

T27

4

auto[1]

1773

1

T18

3

T26

3

T27

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T27	2		T42	2		T402	1
auto[134217728:268435455]	103	1			T3	1		T222	1		T233	1
auto[268435456:402653183]	112	1			T27	1		T222	1		T219	1
auto[402653184:536870911]	123	1			T42	1		T141	1		T54	1
auto[536870912:671088639]	104	1			T3	1		T99	1		T42	1
auto[671088640:805306367]	113	1			T42	2		T68	1		T143	1
auto[805306368:939524095]	97	1			T42	2		T37	1		T22	1
auto[939524096:1073741823]	126	1			T42	1		T114	1		T54	1
auto[1073741824:1207959551]	88	1			T42	2		T53	1		T61	1
auto[1207959552:1342177279]	95	1			T3	1		T99	1		T42	1
auto[1342177280:1476395007]	97	1			T27	1		T42	1		T46	2
auto[1476395008:1610612735]	82	1			T42	1		T68	1		T143	1
auto[1610612736:1744830463]	93	1			T18	2		T26	1		T42	3
auto[1744830464:1879048191]	109	1			T42	2		T68	1		T143	1
auto[1879048192:2013265919]	104	1			T26	1		T99	1		T42	4
auto[2013265920:2147483647]	105	1			T114	1		T222	1		T23	1
auto[2147483648:2281701375]	97	1			T18	1		T115	1		T47	1
auto[2281701376:2415919103]	95	1			T26	1		T42	5		T22	1
auto[2415919104:2550136831]	110	1			T26	1		T42	2		T141	1
auto[2550136832:2684354559]	107	1			T26	1		T54	1		T48	1
auto[2684354560:2818572287]	112	1			T402	1		T116	1		T47	1
auto[2818572288:2952790015]	99	1			T42	2		T233	1		T47	1
auto[2952790016:3087007743]	114	1			T42	1		T22	1		T47	1
auto[3087007744:3221225471]	116	1			T99	1		T42	1		T46	1
auto[3221225472:3355443199]	103	1			T42	3		T140	1		T115	1
auto[3355443200:3489660927]	110	1			T42	1		T68	1		T61	1
auto[3489660928:3623878655]	78	1			T26	1		T42	1		T46	1
auto[3623878656:3758096383]	117	1			T99	1		T42	2		T23	1
auto[3758096384:3892314111]	130	1			T27	1		T42	3		T53	1
auto[3892314112:4026531839]	83	1			T42	1		T143	1		T22	1
auto[4026531840:4160749567]	104	1			T99	1		T42	1		T155	1
auto[4160749568:4294967295]	111	1			T42	2		T37	1		T47	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T27	2		T42	1		T402	1
auto[0:134217727]	auto[1]	56	1			T42	1		T115	1		T420	1
auto[134217728:268435455]	auto[0]	46	1			T3	1		T47	1		T107	1
auto[134217728:268435455]	auto[1]	57	1			T222	1		T233	1		T47	1
auto[268435456:402653183]	auto[0]	45	1			T222	1		T224	1		T88	1
auto[268435456:402653183]	auto[1]	67	1			T27	1		T219	1		T47	1
auto[402653184:536870911]	auto[0]	58	1			T54	1		T155	1		T47	1
auto[402653184:536870911]	auto[1]	65	1			T42	1		T141	1		T233	1
auto[536870912:671088639]	auto[0]	57	1			T3	1		T42	1		T69	1
auto[536870912:671088639]	auto[1]	47	1			T99	1		T47	1		T101	1
auto[671088640:805306367]	auto[0]	45	1			T42	1		T402	1		T47	2
auto[671088640:805306367]	auto[1]	68	1			T42	1		T68	1		T143	1
auto[805306368:939524095]	auto[0]	44	1			T42	1		T54	1		T48	1
auto[805306368:939524095]	auto[1]	53	1			T42	1		T37	1		T22	1
auto[939524096:1073741823]	auto[0]	56	1			T42	1		T54	1		T155	1
auto[939524096:1073741823]	auto[1]	70	1			T114	1		T95	1		T67	2
auto[1073741824:1207959551]	auto[0]	40	1			T42	1		T53	1		T61	1
auto[1073741824:1207959551]	auto[1]	48	1			T42	1		T116	1		T48	1
auto[1207959552:1342177279]	auto[0]	44	1			T3	1		T99	1		T23	1
auto[1207959552:1342177279]	auto[1]	51	1			T42	1		T219	1		T47	1
auto[1342177280:1476395007]	auto[0]	61	1			T27	1		T42	1		T46	2
auto[1342177280:1476395007]	auto[1]	36	1			T133	1		T94	1		T63	1
auto[1476395008:1610612735]	auto[0]	39	1			T42	1		T23	1		T107	1
auto[1476395008:1610612735]	auto[1]	43	1			T68	1		T143	1		T48	1
auto[1610612736:1744830463]	auto[0]	47	1			T143	1		T402	1		T47	2
auto[1610612736:1744830463]	auto[1]	46	1			T18	2		T26	1		T42	3
auto[1744830464:1879048191]	auto[0]	48	1			T42	1		T68	1		T86	1
auto[1744830464:1879048191]	auto[1]	61	1			T42	1		T143	1		T370	1
auto[1879048192:2013265919]	auto[0]	56	1			T42	3		T47	1		T48	1
auto[1879048192:2013265919]	auto[1]	48	1			T26	1		T99	1		T42	1
auto[2013265920:2147483647]	auto[0]	59	1			T114	1		T23	1		T58	1
auto[2013265920:2147483647]	auto[1]	46	1			T222	1		T59	1		T60	1
auto[2147483648:2281701375]	auto[0]	49	1			T47	1		T48	1		T95	1
auto[2147483648:2281701375]	auto[1]	48	1			T18	1		T115	1		T48	3
auto[2281701376:2415919103]	auto[0]	35	1			T26	1		T42	3		T69	1
auto[2281701376:2415919103]	auto[1]	60	1			T42	2		T22	1		T47	1
auto[2415919104:2550136831]	auto[0]	48	1			T26	1		T42	2		T64	1
auto[2415919104:2550136831]	auto[1]	62	1			T141	1		T219	1		T116	1
auto[2550136832:2684354559]	auto[0]	46	1			T26	1		T54	1		T48	1
auto[2550136832:2684354559]	auto[1]	61	1			T104	1		T7	1		T62	1
auto[2684354560:2818572287]	auto[0]	47	1			T402	1		T24	1		T88	2
auto[2684354560:2818572287]	auto[1]	65	1			T116	1		T47	1		T234	1
auto[2818572288:2952790015]	auto[0]	50	1			T42	1		T233	1		T48	1
auto[2818572288:2952790015]	auto[1]	49	1			T42	1		T47	1		T69	1
auto[2952790016:3087007743]	auto[0]	54	1			T22	1		T318	1		T148	1
auto[2952790016:3087007743]	auto[1]	60	1			T42	1		T47	1		T58	1
auto[3087007744:3221225471]	auto[0]	53	1			T46	1		T143	1		T22	1
auto[3087007744:3221225471]	auto[1]	63	1			T99	1		T42	1		T233	1
auto[3221225472:3355443199]	auto[0]	38	1			T116	1		T47	2		T62	1
auto[3221225472:3355443199]	auto[1]	65	1			T42	3		T140	1		T115	1
auto[3355443200:3489660927]	auto[0]	53	1			T47	1		T420	1		T148	1
auto[3355443200:3489660927]	auto[1]	57	1			T42	1		T68	1		T61	1
auto[3489660928:3623878655]	auto[0]	34	1			T42	1		T48	1		T224	1
auto[3489660928:3623878655]	auto[1]	44	1			T26	1		T46	1		T53	1
auto[3623878656:3758096383]	auto[0]	62	1			T99	1		T42	1		T23	1
auto[3623878656:3758096383]	auto[1]	55	1			T42	1		T48	1		T234	1
auto[3758096384:3892314111]	auto[0]	65	1			T27	1		T42	2		T53	1
auto[3758096384:3892314111]	auto[1]	65	1			T42	1		T219	1		T48	4
auto[3892314112:4026531839]	auto[0]	42	1			T42	1		T22	1		T47	1
auto[3892314112:4026531839]	auto[1]	41	1			T143	1		T116	1		T130	2
auto[4026531840:4160749567]	auto[0]	50	1			T155	1		T47	1		T130	1
auto[4026531840:4160749567]	auto[1]	54	1			T99	1		T42	1		T47	2
auto[4160749568:4294967295]	auto[0]	49	1			T42	1		T47	2		T95	1
auto[4160749568:4294967295]	auto[1]	62	1			T42	1		T37	1		T48	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1547

1

T3

2

T26

2

T27

3

auto[1]

1792

1

T3

1

T18

3

T26

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T27	3		T42	2		T54	1
auto[134217728:268435455]	111	1			T42	1		T37	1		T46	1
auto[268435456:402653183]	101	1			T42	5		T68	1		T219	2
auto[402653184:536870911]	121	1			T99	1		T42	3		T402	2
auto[536870912:671088639]	116	1			T42	2		T68	1		T47	1
auto[671088640:805306367]	112	1			T3	1		T42	1		T37	1
auto[805306368:939524095]	119	1			T26	2		T99	1		T42	3
auto[939524096:1073741823]	95	1			T23	1		T69	1		T48	2
auto[1073741824:1207959551]	107	1			T42	1		T68	1		T143	1
auto[1207959552:1342177279]	100	1			T3	1		T18	1		T68	1
auto[1342177280:1476395007]	97	1			T42	1		T47	1		T59	1
auto[1476395008:1610612735]	99	1			T99	1		T42	1		T37	1
auto[1610612736:1744830463]	97	1			T42	1		T46	1		T143	1
auto[1744830464:1879048191]	92	1			T42	1		T141	1		T233	2
auto[1879048192:2013265919]	117	1			T42	2		T54	1		T116	1
auto[2013265920:2147483647]	99	1			T26	1		T42	2		T143	1
auto[2147483648:2281701375]	115	1			T99	1		T42	3		T115	1
auto[2281701376:2415919103]	102	1			T42	3		T46	1		T104	1
auto[2415919104:2550136831]	108	1			T99	1		T22	2		T47	1
auto[2550136832:2684354559]	102	1			T3	1		T42	2		T22	1
auto[2684354560:2818572287]	95	1			T26	1		T53	1		T233	1
auto[2818572288:2952790015]	88	1			T26	1		T141	1		T53	1
auto[2952790016:3087007743]	106	1			T18	1		T42	1		T143	1
auto[3087007744:3221225471]	91	1			T42	1		T22	1		T219	1
auto[3221225472:3355443199]	103	1			T114	1		T48	1		T74	1
auto[3355443200:3489660927]	112	1			T42	2		T23	1		T61	1
auto[3489660928:3623878655]	115	1			T18	1		T27	1		T42	4
auto[3623878656:3758096383]	108	1			T99	1		T53	1		T143	1
auto[3758096384:3892314111]	109	1			T42	2		T402	1		T115	1
auto[3892314112:4026531839]	102	1			T27	1		T42	2		T116	1
auto[4026531840:4160749567]	108	1			T26	1		T42	1		T47	1
auto[4160749568:4294967295]	92	1			T42	1		T39	1		T130	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T27	2		T42	2		T54	1
auto[0:134217727]	auto[1]	53	1			T27	1		T48	1		T130	1
auto[134217728:268435455]	auto[0]	57	1			T42	1		T46	1		T47	2
auto[134217728:268435455]	auto[1]	54	1			T37	1		T114	1		T61	1
auto[268435456:402653183]	auto[0]	49	1			T42	1		T68	1		T421	1
auto[268435456:402653183]	auto[1]	52	1			T42	4		T219	2		T115	1
auto[402653184:536870911]	auto[0]	59	1			T42	1		T402	2		T48	1
auto[402653184:536870911]	auto[1]	62	1			T99	1		T42	2		T47	1
auto[536870912:671088639]	auto[0]	58	1			T60	2		T86	1		T107	1
auto[536870912:671088639]	auto[1]	58	1			T42	2		T68	1		T47	1
auto[671088640:805306367]	auto[0]	50	1			T3	1		T46	1		T402	1
auto[671088640:805306367]	auto[1]	62	1			T42	1		T37	1		T140	1
auto[805306368:939524095]	auto[0]	59	1			T26	2		T42	1		T23	1
auto[805306368:939524095]	auto[1]	60	1			T99	1		T42	2		T133	1
auto[939524096:1073741823]	auto[0]	38	1			T23	1		T48	1		T60	1
auto[939524096:1073741823]	auto[1]	57	1			T69	1		T48	1		T134	1
auto[1073741824:1207959551]	auto[0]	51	1			T42	1		T143	1		T47	1
auto[1073741824:1207959551]	auto[1]	56	1			T68	1		T48	2		T133	1
auto[1207959552:1342177279]	auto[0]	40	1			T54	1		T47	2		T94	1
auto[1207959552:1342177279]	auto[1]	60	1			T3	1		T18	1		T68	1
auto[1342177280:1476395007]	auto[0]	44	1			T47	1		T60	2		T224	1
auto[1342177280:1476395007]	auto[1]	53	1			T42	1		T59	1		T224	1
auto[1476395008:1610612735]	auto[0]	39	1			T64	1		T222	1		T54	1
auto[1476395008:1610612735]	auto[1]	60	1			T99	1		T42	1		T37	1
auto[1610612736:1744830463]	auto[0]	39	1			T42	1		T46	1		T222	1
auto[1610612736:1744830463]	auto[1]	58	1			T143	1		T48	1		T60	1
auto[1744830464:1879048191]	auto[0]	46	1			T42	1		T23	1		T47	1
auto[1744830464:1879048191]	auto[1]	46	1			T141	1		T233	2		T47	1
auto[1879048192:2013265919]	auto[0]	64	1			T54	1		T47	1		T69	1
auto[1879048192:2013265919]	auto[1]	53	1			T42	2		T116	1		T60	1
auto[2013265920:2147483647]	auto[0]	42	1			T42	2		T143	1		T48	1
auto[2013265920:2147483647]	auto[1]	57	1			T26	1		T130	1		T56	1
auto[2147483648:2281701375]	auto[0]	49	1			T42	2		T47	2		T95	1
auto[2147483648:2281701375]	auto[1]	66	1			T99	1		T42	1		T115	1
auto[2281701376:2415919103]	auto[0]	53	1			T42	2		T46	1		T86	1
auto[2281701376:2415919103]	auto[1]	49	1			T42	1		T104	1		T8	1
auto[2415919104:2550136831]	auto[0]	49	1			T22	2		T47	1		T60	2
auto[2415919104:2550136831]	auto[1]	59	1			T99	1		T74	1		T101	1
auto[2550136832:2684354559]	auto[0]	52	1			T3	1		T42	1		T48	1
auto[2550136832:2684354559]	auto[1]	50	1			T42	1		T22	1		T233	1
auto[2684354560:2818572287]	auto[0]	41	1			T53	1		T69	1		T60	1
auto[2684354560:2818572287]	auto[1]	54	1			T26	1		T233	1		T116	1
auto[2818572288:2952790015]	auto[0]	43	1			T53	1		T155	1		T47	1
auto[2818572288:2952790015]	auto[1]	45	1			T26	1		T141	1		T318	1
auto[2952790016:3087007743]	auto[0]	42	1			T42	1		T47	2		T60	1
auto[2952790016:3087007743]	auto[1]	64	1			T18	1		T143	1		T222	2
auto[3087007744:3221225471]	auto[0]	43	1			T22	1		T47	4		T48	1
auto[3087007744:3221225471]	auto[1]	48	1			T42	1		T219	1		T48	2
auto[3221225472:3355443199]	auto[0]	42	1			T114	1		T60	1		T239	1
auto[3221225472:3355443199]	auto[1]	61	1			T48	1		T74	1		T58	2
auto[3355443200:3489660927]	auto[0]	52	1			T42	1		T23	1		T61	1
auto[3355443200:3489660927]	auto[1]	60	1			T42	1		T133	1		T234	1
auto[3489660928:3623878655]	auto[0]	52	1			T42	2		T402	1		T48	1
auto[3489660928:3623878655]	auto[1]	63	1			T18	1		T27	1		T42	2
auto[3623878656:3758096383]	auto[0]	51	1			T48	1		T263	1		T60	1
auto[3623878656:3758096383]	auto[1]	57	1			T99	1		T53	1		T143	1
auto[3758096384:3892314111]	auto[0]	53	1			T402	1		T40	1		T224	1
auto[3758096384:3892314111]	auto[1]	56	1			T42	2		T115	1		T47	1
auto[3892314112:4026531839]	auto[0]	54	1			T27	1		T155	2		T95	1
auto[3892314112:4026531839]	auto[1]	48	1			T42	2		T116	1		T48	1
auto[4026531840:4160749567]	auto[0]	45	1			T42	1		T47	1		T60	1
auto[4026531840:4160749567]	auto[1]	63	1			T26	1		T48	1		T318	1
auto[4160749568:4294967295]	auto[0]	44	1			T42	1		T318	1		T86	1
auto[4160749568:4294967295]	auto[1]	48	1			T39	1		T130	1		T133	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1552

1

T3

2

T26

4

T27

4

auto[1]

1786

1

T3

1

T18

3

T26

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T42	2		T64	1		T222	1
auto[134217728:268435455]	94	1			T99	1		T54	1		T402	1
auto[268435456:402653183]	104	1			T143	1		T23	1		T47	1
auto[402653184:536870911]	93	1			T42	1		T114	1		T47	1
auto[536870912:671088639]	115	1			T42	1		T141	1		T155	1
auto[671088640:805306367]	102	1			T27	2		T99	1		T42	1
auto[805306368:939524095]	99	1			T42	2		T402	1		T47	2
auto[939524096:1073741823]	115	1			T42	1		T53	1		T143	1
auto[1073741824:1207959551]	100	1			T27	1		T42	2		T222	1
auto[1207959552:1342177279]	90	1			T42	1		T141	1		T22	1
auto[1342177280:1476395007]	115	1			T26	1		T42	1		T37	1
auto[1476395008:1610612735]	109	1			T42	1		T68	1		T69	1
auto[1610612736:1744830463]	113	1			T18	1		T42	2		T46	1
auto[1744830464:1879048191]	94	1			T99	1		T42	3		T47	1
auto[1879048192:2013265919]	95	1			T42	1		T46	1		T53	1
auto[2013265920:2147483647]	109	1			T3	1		T42	4		T68	2
auto[2147483648:2281701375]	112	1			T42	1		T22	2		T233	1
auto[2281701376:2415919103]	114	1			T18	1		T42	1		T143	1
auto[2415919104:2550136831]	106	1			T140	1		T22	1		T23	1
auto[2550136832:2684354559]	109	1			T26	1		T222	1		T219	2
auto[2684354560:2818572287]	92	1			T26	1		T42	1		T47	2
auto[2818572288:2952790015]	103	1			T99	1		T42	4		T46	1
auto[2952790016:3087007743]	103	1			T27	1		T99	1		T42	2
auto[3087007744:3221225471]	98	1			T42	3		T141	1		T23	1
auto[3221225472:3355443199]	93	1			T46	1		T54	1		T155	1
auto[3355443200:3489660927]	121	1			T42	3		T68	1		T47	1
auto[3489660928:3623878655]	115	1			T27	1		T99	1		T42	1
auto[3623878656:3758096383]	103	1			T26	1		T42	3		T37	1
auto[3758096384:3892314111]	112	1			T42	1		T37	1		T47	1
auto[3892314112:4026531839]	97	1			T3	1		T18	1		T26	2
auto[4026531840:4160749567]	106	1			T42	2		T143	1		T222	1
auto[4160749568:4294967295]	104	1			T3	1		T42	2		T116	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T42	2		T64	1		T222	1
auto[0:134217727]	auto[1]	49	1			T219	1		T115	1		T47	1
auto[134217728:268435455]	auto[0]	55	1			T54	1		T402	1		T47	1
auto[134217728:268435455]	auto[1]	39	1			T99	1		T69	1		T130	1
auto[268435456:402653183]	auto[0]	50	1			T23	1		T69	1		T48	1
auto[268435456:402653183]	auto[1]	54	1			T143	1		T47	1		T48	1
auto[402653184:536870911]	auto[0]	42	1			T42	1		T48	1		T234	1
auto[402653184:536870911]	auto[1]	51	1			T114	1		T47	1		T277	1
auto[536870912:671088639]	auto[0]	47	1			T42	1		T59	1		T159	1
auto[536870912:671088639]	auto[1]	68	1			T141	1		T155	1		T130	1
auto[671088640:805306367]	auto[0]	46	1			T27	1		T155	1		T47	1
auto[671088640:805306367]	auto[1]	56	1			T27	1		T99	1		T42	1
auto[805306368:939524095]	auto[0]	47	1			T402	1		T24	1		T60	1
auto[805306368:939524095]	auto[1]	52	1			T42	2		T47	2		T74	1
auto[939524096:1073741823]	auto[0]	48	1			T53	1		T402	1		T48	2
auto[939524096:1073741823]	auto[1]	67	1			T42	1		T143	1		T47	1
auto[1073741824:1207959551]	auto[0]	47	1			T27	1		T42	1		T222	1
auto[1073741824:1207959551]	auto[1]	53	1			T42	1		T48	1		T25	1
auto[1207959552:1342177279]	auto[0]	42	1			T22	1		T54	1		T61	1
auto[1207959552:1342177279]	auto[1]	48	1			T42	1		T141	1		T219	1
auto[1342177280:1476395007]	auto[0]	45	1			T26	1		T402	1		T24	2
auto[1342177280:1476395007]	auto[1]	70	1			T42	1		T37	1		T143	1
auto[1476395008:1610612735]	auto[0]	52	1			T42	1		T69	1		T318	1
auto[1476395008:1610612735]	auto[1]	57	1			T68	1		T60	1		T224	4
auto[1610612736:1744830463]	auto[0]	53	1			T42	1		T46	1		T47	1
auto[1610612736:1744830463]	auto[1]	60	1			T18	1		T42	1		T48	1
auto[1744830464:1879048191]	auto[0]	40	1			T42	2		T47	1		T69	1
auto[1744830464:1879048191]	auto[1]	54	1			T99	1		T42	1		T48	1
auto[1879048192:2013265919]	auto[0]	41	1			T42	1		T53	1		T22	1
auto[1879048192:2013265919]	auto[1]	54	1			T46	1		T233	1		T61	1
auto[2013265920:2147483647]	auto[0]	47	1			T3	1		T42	3		T68	1
auto[2013265920:2147483647]	auto[1]	62	1			T42	1		T68	1		T47	1
auto[2147483648:2281701375]	auto[0]	44	1			T42	1		T22	1		T402	1
auto[2147483648:2281701375]	auto[1]	68	1			T22	1		T233	1		T116	1
auto[2281701376:2415919103]	auto[0]	53	1			T143	1		T116	1		T48	1
auto[2281701376:2415919103]	auto[1]	61	1			T18	1		T42	1		T47	1
auto[2415919104:2550136831]	auto[0]	49	1			T23	1		T47	1		T48	4
auto[2415919104:2550136831]	auto[1]	57	1			T140	1		T22	1		T130	1
auto[2550136832:2684354559]	auto[0]	55	1			T26	1		T60	2		T224	1
auto[2550136832:2684354559]	auto[1]	54	1			T222	1		T219	2		T48	1
auto[2684354560:2818572287]	auto[0]	41	1			T42	1		T47	1		T95	1
auto[2684354560:2818572287]	auto[1]	51	1			T26	1		T47	1		T133	1
auto[2818572288:2952790015]	auto[0]	50	1			T46	1		T54	1		T47	2
auto[2818572288:2952790015]	auto[1]	53	1			T99	1		T42	4		T53	1
auto[2952790016:3087007743]	auto[0]	47	1			T27	1		T42	2		T224	1
auto[2952790016:3087007743]	auto[1]	56	1			T99	1		T233	1		T56	1
auto[3087007744:3221225471]	auto[0]	38	1			T42	2		T23	1		T105	1
auto[3087007744:3221225471]	auto[1]	60	1			T42	1		T141	1		T47	1
auto[3221225472:3355443199]	auto[0]	45	1			T46	1		T54	1		T224	2
auto[3221225472:3355443199]	auto[1]	48	1			T155	1		T263	1		T60	1
auto[3355443200:3489660927]	auto[0]	57	1			T42	1		T47	1		T48	2
auto[3355443200:3489660927]	auto[1]	64	1			T42	2		T68	1		T48	1
auto[3489660928:3623878655]	auto[0]	65	1			T27	1		T47	3		T48	1
auto[3489660928:3623878655]	auto[1]	50	1			T99	1		T42	1		T143	1
auto[3623878656:3758096383]	auto[0]	42	1			T26	1		T42	1		T114	1
auto[3623878656:3758096383]	auto[1]	61	1			T42	2		T37	1		T115	1
auto[3758096384:3892314111]	auto[0]	54	1			T47	1		T130	1		T60	1
auto[3758096384:3892314111]	auto[1]	58	1			T42	1		T37	1		T234	1
auto[3892314112:4026531839]	auto[0]	47	1			T26	1		T42	1		T155	1
auto[3892314112:4026531839]	auto[1]	50	1			T3	1		T18	1		T26	1
auto[4026531840:4160749567]	auto[0]	52	1			T42	1		T155	1		T47	1
auto[4026531840:4160749567]	auto[1]	54	1			T42	1		T143	1		T222	1
auto[4160749568:4294967295]	auto[0]	57	1			T3	1		T42	2		T116	1
auto[4160749568:4294967295]	auto[1]	47	1			T130	1		T60	1		T94	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1536

1

T3

1

T26

2

T27

4

auto[1]

1803

1

T3

2

T18

3

T26

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T18	1		T141	1		T53	1
auto[134217728:268435455]	94	1			T42	2		T155	1		T69	1
auto[268435456:402653183]	105	1			T42	1		T46	1		T22	1
auto[402653184:536870911]	109	1			T42	3		T140	1		T53	1
auto[536870912:671088639]	104	1			T3	1		T42	2		T54	1
auto[671088640:805306367]	101	1			T42	3		T53	1		T23	1
auto[805306368:939524095]	111	1			T3	2		T26	2		T37	1
auto[939524096:1073741823]	106	1			T42	2		T37	1		T47	1
auto[1073741824:1207959551]	113	1			T26	1		T42	2		T114	1
auto[1207959552:1342177279]	110	1			T26	1		T99	1		T42	1
auto[1342177280:1476395007]	99	1			T27	1		T42	3		T64	1
auto[1476395008:1610612735]	111	1			T26	1		T42	1		T22	2
auto[1610612736:1744830463]	102	1			T99	1		T46	1		T402	1
auto[1744830464:1879048191]	104	1			T42	1		T22	1		T47	1
auto[1879048192:2013265919]	110	1			T18	2		T42	2		T143	1
auto[2013265920:2147483647]	89	1			T26	1		T27	1		T42	2
auto[2147483648:2281701375]	104	1			T42	4		T233	1		T23	1
auto[2281701376:2415919103]	112	1			T42	1		T54	1		T115	1
auto[2415919104:2550136831]	102	1			T99	2		T42	3		T46	1
auto[2550136832:2684354559]	120	1			T42	2		T222	1		T47	2
auto[2684354560:2818572287]	108	1			T27	1		T42	1		T222	1
auto[2818572288:2952790015]	109	1			T42	1		T54	1		T402	1
auto[2952790016:3087007743]	103	1			T99	1		T42	2		T54	1
auto[3087007744:3221225471]	118	1			T42	1		T47	1		T48	2
auto[3221225472:3355443199]	93	1			T68	1		T47	1		T130	1
auto[3355443200:3489660927]	105	1			T99	1		T42	2		T68	1
auto[3489660928:3623878655]	108	1			T27	1		T42	1		T233	1
auto[3623878656:3758096383]	96	1			T42	1		T402	1		T116	1
auto[3758096384:3892314111]	94	1			T141	1		T143	1		T22	1
auto[3892314112:4026531839]	98	1			T42	2		T37	1		T68	1
auto[4026531840:4160749567]	104	1			T23	1		T402	1		T116	1
auto[4160749568:4294967295]	104	1			T27	1		T42	2		T141	1