Unified Coverage Report :: Group Instance : attest_sw_binding_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1556

1

T3

3

T26

4

T27

4

auto[1]

1783

1

T18

3

T26

2

T27

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T27	1		T141	1		T115	1
auto[134217728:268435455]	113	1			T99	1		T42	3		T22	1
auto[268435456:402653183]	105	1			T26	1		T27	1		T402	2
auto[402653184:536870911]	128	1			T140	1		T53	1		T222	1
auto[536870912:671088639]	105	1			T42	1		T115	1		T47	1
auto[671088640:805306367]	91	1			T27	1		T42	3		T37	1
auto[805306368:939524095]	103	1			T42	2		T143	1		T47	2
auto[939524096:1073741823]	110	1			T42	1		T64	1		T23	1
auto[1073741824:1207959551]	104	1			T99	1		T143	1		T233	1
auto[1207959552:1342177279]	106	1			T18	1		T99	1		T42	2
auto[1342177280:1476395007]	115	1			T3	1		T27	1		T42	3
auto[1476395008:1610612735]	104	1			T3	1		T42	2		T233	1
auto[1610612736:1744830463]	101	1			T42	3		T141	1		T222	1
auto[1744830464:1879048191]	103	1			T26	1		T42	1		T37	2
auto[1879048192:2013265919]	118	1			T3	1		T42	3		T54	1
auto[2013265920:2147483647]	122	1			T42	1		T116	1		T155	1
auto[2147483648:2281701375]	106	1			T99	1		T42	4		T69	1
auto[2281701376:2415919103]	109	1			T99	1		T42	3		T68	1
auto[2415919104:2550136831]	102	1			T26	1		T42	1		T54	1
auto[2550136832:2684354559]	107	1			T61	1		T219	1		T115	1
auto[2684354560:2818572287]	90	1			T68	1		T143	1		T23	1
auto[2818572288:2952790015]	110	1			T18	1		T143	1		T222	1
auto[2952790016:3087007743]	106	1			T26	1		T42	1		T53	1
auto[3087007744:3221225471]	94	1			T42	2		T46	2		T222	1
auto[3221225472:3355443199]	91	1			T99	1		T54	1		T116	2
auto[3355443200:3489660927]	103	1			T18	1		T42	2		T141	1
auto[3489660928:3623878655]	107	1			T42	2		T22	1		T155	1
auto[3623878656:3758096383]	86	1			T42	1		T47	1		T156	1
auto[3758096384:3892314111]	102	1			T26	2		T27	1		T42	2
auto[3892314112:4026531839]	98	1			T42	1		T47	2		T48	2
auto[4026531840:4160749567]	105	1			T42	1		T114	1		T47	1
auto[4160749568:4294967295]	101	1			T42	3		T143	1		T47	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T27	1		T24	1		T60	1
auto[0:134217727]	auto[1]	41	1			T141	1		T115	1		T48	1
auto[134217728:268435455]	auto[0]	57	1			T42	2		T402	1		T47	1
auto[134217728:268435455]	auto[1]	56	1			T99	1		T42	1		T22	1
auto[268435456:402653183]	auto[0]	53	1			T26	1		T27	1		T402	2
auto[268435456:402653183]	auto[1]	52	1			T47	1		T70	1		T108	1
auto[402653184:536870911]	auto[0]	50	1			T53	1		T402	1		T116	1
auto[402653184:536870911]	auto[1]	78	1			T140	1		T222	1		T69	1
auto[536870912:671088639]	auto[0]	51	1			T42	1		T48	1		T60	1
auto[536870912:671088639]	auto[1]	54	1			T115	1		T47	1		T58	1
auto[671088640:805306367]	auto[0]	41	1			T42	1		T53	1		T133	1
auto[671088640:805306367]	auto[1]	50	1			T27	1		T42	2		T37	1
auto[805306368:939524095]	auto[0]	39	1			T42	1		T143	1		T48	1
auto[805306368:939524095]	auto[1]	64	1			T42	1		T47	2		T39	1
auto[939524096:1073741823]	auto[0]	50	1			T42	1		T23	1		T47	1
auto[939524096:1073741823]	auto[1]	60	1			T64	1		T219	1		T48	3
auto[1073741824:1207959551]	auto[0]	52	1			T99	1		T86	2		T94	1
auto[1073741824:1207959551]	auto[1]	52	1			T143	1		T233	1		T74	1
auto[1207959552:1342177279]	auto[0]	50	1			T114	1		T47	1		T318	1
auto[1207959552:1342177279]	auto[1]	56	1			T18	1		T99	1		T42	2
auto[1342177280:1476395007]	auto[0]	51	1			T3	1		T27	1		T42	2
auto[1342177280:1476395007]	auto[1]	64	1			T42	1		T48	1		T60	1
auto[1476395008:1610612735]	auto[0]	46	1			T3	1		T23	1		T48	1
auto[1476395008:1610612735]	auto[1]	58	1			T42	2		T233	1		T60	1
auto[1610612736:1744830463]	auto[0]	49	1			T42	1		T222	1		T22	1
auto[1610612736:1744830463]	auto[1]	52	1			T42	2		T141	1		T60	1
auto[1744830464:1879048191]	auto[0]	48	1			T26	1		T42	1		T47	1
auto[1744830464:1879048191]	auto[1]	55	1			T37	2		T143	1		T131	1
auto[1879048192:2013265919]	auto[0]	52	1			T3	1		T42	2		T54	1
auto[1879048192:2013265919]	auto[1]	66	1			T42	1		T219	1		T234	1
auto[2013265920:2147483647]	auto[0]	62	1			T42	1		T47	1		T95	1
auto[2013265920:2147483647]	auto[1]	60	1			T116	1		T155	1		T47	2
auto[2147483648:2281701375]	auto[0]	50	1			T42	1		T69	1		T48	1
auto[2147483648:2281701375]	auto[1]	56	1			T99	1		T42	3		T48	2
auto[2281701376:2415919103]	auto[0]	53	1			T42	2		T46	1		T54	1
auto[2281701376:2415919103]	auto[1]	56	1			T99	1		T42	1		T68	1
auto[2415919104:2550136831]	auto[0]	50	1			T54	1		T402	1		T48	1
auto[2415919104:2550136831]	auto[1]	52	1			T26	1		T42	1		T116	1
auto[2550136832:2684354559]	auto[0]	43	1			T223	1		T307	1		T73	1
auto[2550136832:2684354559]	auto[1]	64	1			T61	1		T219	1		T115	1
auto[2684354560:2818572287]	auto[0]	43	1			T68	1		T23	1		T47	1
auto[2684354560:2818572287]	auto[1]	47	1			T143	1		T56	1		T277	1
auto[2818572288:2952790015]	auto[0]	48	1			T143	1		T155	1		T47	1
auto[2818572288:2952790015]	auto[1]	62	1			T18	1		T222	1		T233	1
auto[2952790016:3087007743]	auto[0]	51	1			T26	1		T42	1		T155	1
auto[2952790016:3087007743]	auto[1]	55	1			T53	1		T130	1		T133	1
auto[3087007744:3221225471]	auto[0]	40	1			T42	2		T46	2		T47	1
auto[3087007744:3221225471]	auto[1]	54	1			T222	1		T233	1		T47	1
auto[3221225472:3355443199]	auto[0]	39	1			T54	1		T60	2		T107	1
auto[3221225472:3355443199]	auto[1]	52	1			T99	1		T116	2		T48	1
auto[3355443200:3489660927]	auto[0]	48	1			T42	2		T22	1		T47	1
auto[3355443200:3489660927]	auto[1]	55	1			T18	1		T141	1		T46	1
auto[3489660928:3623878655]	auto[0]	53	1			T42	1		T22	1		T48	1
auto[3489660928:3623878655]	auto[1]	54	1			T42	1		T155	1		T47	1
auto[3623878656:3758096383]	auto[0]	40	1			T47	1		T108	1		T149	1
auto[3623878656:3758096383]	auto[1]	46	1			T42	1		T156	1		T60	1
auto[3758096384:3892314111]	auto[0]	51	1			T26	1		T27	1		T42	1
auto[3758096384:3892314111]	auto[1]	51	1			T26	1		T42	1		T68	1
auto[3892314112:4026531839]	auto[0]	50	1			T47	1		T48	1		T24	2
auto[3892314112:4026531839]	auto[1]	48	1			T42	1		T47	1		T48	1
auto[4026531840:4160749567]	auto[0]	47	1			T42	1		T48	1		T224	1
auto[4026531840:4160749567]	auto[1]	58	1			T114	1		T47	1		T56	1
auto[4160749568:4294967295]	auto[0]	46	1			T42	2		T47	1		T48	1
auto[4160749568:4294967295]	auto[1]	55	1			T42	1		T143	1		T47	1