Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4491

1

T3

2

T18

4

T26

6

auto[1]

2186

1

T3

4

T18

2

T26

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	206	1			T143	2		T116	2		T47	6
auto[134217728:268435455]	248	1			T42	4		T22	2		T233	2
auto[268435456:402653183]	222	1			T42	4		T47	2		T48	4
auto[402653184:536870911]	222	1			T42	2		T37	2		T143	2
auto[536870912:671088639]	194	1			T53	2		T143	2		T402	2
auto[671088640:805306367]	224	1			T141	2		T53	2		T47	6
auto[805306368:939524095]	194	1			T99	2		T42	2		T68	2
auto[939524096:1073741823]	250	1			T26	4		T99	2		T42	4
auto[1073741824:1207959551]	202	1			T42	6		T46	2		T23	2
auto[1207959552:1342177279]	186	1			T42	2		T140	2		T114	2
auto[1342177280:1476395007]	208	1			T42	2		T143	2		T47	2
auto[1476395008:1610612735]	202	1			T3	2		T42	2		T155	2
auto[1610612736:1744830463]	200	1			T26	2		T222	2		T22	2
auto[1744830464:1879048191]	204	1			T42	2		T23	2		T47	4
auto[1879048192:2013265919]	210	1			T42	6		T114	2		T23	2
auto[2013265920:2147483647]	230	1			T42	6		T37	2		T64	2
auto[2147483648:2281701375]	172	1			T26	2		T42	2		T68	2
auto[2281701376:2415919103]	232	1			T18	2		T26	2		T27	2
auto[2415919104:2550136831]	192	1			T18	2		T99	2		T42	8
auto[2550136832:2684354559]	210	1			T99	2		T42	4		T54	2
auto[2684354560:2818572287]	214	1			T42	2		T222	2		T115	2
auto[2818572288:2952790015]	216	1			T42	2		T141	2		T22	2
auto[2952790016:3087007743]	214	1			T42	4		T141	2		T219	2
auto[3087007744:3221225471]	240	1			T27	2		T99	2		T42	2
auto[3221225472:3355443199]	206	1			T27	2		T42	8		T68	2
auto[3355443200:3489660927]	184	1			T143	4		T402	2		T47	2
auto[3489660928:3623878655]	222	1			T18	2		T26	2		T99	2
auto[3623878656:3758096383]	216	1			T27	2		T54	2		T74	2
auto[3758096384:3892314111]	204	1			T3	2		T42	4		T37	2
auto[3892314112:4026531839]	164	1			T42	2		T22	2		T115	2
auto[4026531840:4160749567]	190	1			T42	4		T155	2		T60	4
auto[4160749568:4294967295]	199	1			T3	2		T27	2		T42	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	132	1			T116	2		T47	6		T133	4
auto[0:134217727]	auto[1]	74	1			T143	2		T149	2		T91	2
auto[134217728:268435455]	auto[0]	172	1			T42	2		T22	2		T233	2
auto[134217728:268435455]	auto[1]	76	1			T42	2		T116	2		T60	4
auto[268435456:402653183]	auto[0]	146	1			T42	2		T47	2		T48	4
auto[268435456:402653183]	auto[1]	76	1			T42	2		T28	2		T147	2
auto[402653184:536870911]	auto[0]	144	1			T42	2		T402	2		T47	4
auto[402653184:536870911]	auto[1]	78	1			T37	2		T143	2		T48	2
auto[536870912:671088639]	auto[0]	112	1			T53	2		T402	2		T116	2
auto[536870912:671088639]	auto[1]	82	1			T143	2		T47	2		T107	2
auto[671088640:805306367]	auto[0]	142	1			T53	2		T47	4		T60	2
auto[671088640:805306367]	auto[1]	82	1			T141	2		T47	2		T48	2
auto[805306368:939524095]	auto[0]	136	1			T99	2		T42	2		T68	2
auto[805306368:939524095]	auto[1]	58	1			T46	2		T219	2		T47	2
auto[939524096:1073741823]	auto[0]	168	1			T26	4		T99	2		T42	4
auto[939524096:1073741823]	auto[1]	82	1			T115	2		T155	2		T47	2
auto[1073741824:1207959551]	auto[0]	128	1			T42	4		T46	2		T23	2
auto[1073741824:1207959551]	auto[1]	74	1			T42	2		T65	2		T149	2
auto[1207959552:1342177279]	auto[0]	118	1			T42	2		T116	2		T48	4
auto[1207959552:1342177279]	auto[1]	68	1			T140	2		T114	2		T47	2
auto[1342177280:1476395007]	auto[0]	152	1			T47	2		T263	2		T105	2
auto[1342177280:1476395007]	auto[1]	56	1			T42	2		T143	2		T130	2
auto[1476395008:1610612735]	auto[0]	132	1			T42	2		T155	2		T48	4
auto[1476395008:1610612735]	auto[1]	70	1			T3	2		T130	2		T385	2
auto[1610612736:1744830463]	auto[0]	128	1			T222	2		T22	2		T47	4
auto[1610612736:1744830463]	auto[1]	72	1			T26	2		T219	2		T67	2
auto[1744830464:1879048191]	auto[0]	134	1			T42	2		T23	2		T234	2
auto[1744830464:1879048191]	auto[1]	70	1			T47	4		T48	2		T60	2
auto[1879048192:2013265919]	auto[0]	128	1			T42	2		T114	2		T23	2
auto[1879048192:2013265919]	auto[1]	82	1			T42	4		T61	2		T130	2
auto[2013265920:2147483647]	auto[0]	144	1			T42	4		T47	2		T69	2
auto[2013265920:2147483647]	auto[1]	86	1			T42	2		T37	2		T64	2
auto[2147483648:2281701375]	auto[0]	120	1			T68	2		T46	2		T48	2
auto[2147483648:2281701375]	auto[1]	52	1			T26	2		T42	2		T108	2
auto[2281701376:2415919103]	auto[0]	158	1			T18	2		T26	2		T27	2
auto[2281701376:2415919103]	auto[1]	74	1			T42	4		T234	2		T60	2
auto[2415919104:2550136831]	auto[0]	126	1			T18	2		T42	4		T22	2
auto[2415919104:2550136831]	auto[1]	66	1			T99	2		T42	4		T108	2
auto[2550136832:2684354559]	auto[0]	144	1			T99	2		T42	4		T54	2
auto[2550136832:2684354559]	auto[1]	66	1			T219	2		T47	2		T48	2
auto[2684354560:2818572287]	auto[0]	146	1			T222	2		T47	4		T48	2
auto[2684354560:2818572287]	auto[1]	68	1			T42	2		T115	2		T47	2
auto[2818572288:2952790015]	auto[0]	144	1			T42	2		T22	2		T233	2
auto[2818572288:2952790015]	auto[1]	72	1			T141	2		T69	4		T60	2
auto[2952790016:3087007743]	auto[0]	166	1			T42	4		T48	2		T318	2
auto[2952790016:3087007743]	auto[1]	48	1			T141	2		T219	2		T239	2
auto[3087007744:3221225471]	auto[0]	168	1			T27	2		T99	2		T42	2
auto[3087007744:3221225471]	auto[1]	72	1			T233	2		T159	2		T94	4
auto[3221225472:3355443199]	auto[0]	142	1			T27	2		T42	6		T68	2
auto[3221225472:3355443199]	auto[1]	64	1			T42	2		T60	2		T73	4
auto[3355443200:3489660927]	auto[0]	134	1			T402	2		T47	2		T24	2
auto[3355443200:3489660927]	auto[1]	50	1			T143	4		T131	2		T421	2
auto[3489660928:3623878655]	auto[0]	160	1			T99	2		T54	2		T60	4
auto[3489660928:3623878655]	auto[1]	62	1			T18	2		T26	2		T134	2
auto[3623878656:3758096383]	auto[0]	144	1			T27	2		T54	2		T74	2
auto[3623878656:3758096383]	auto[1]	72	1			T49	2		T227	2		T307	2
auto[3758096384:3892314111]	auto[0]	138	1			T42	2		T54	2		T23	2
auto[3758096384:3892314111]	auto[1]	66	1			T3	2		T42	2		T37	2
auto[3892314112:4026531839]	auto[0]	114	1			T42	2		T22	2		T60	4
auto[3892314112:4026531839]	auto[1]	50	1			T115	2		T104	2		T147	2
auto[4026531840:4160749567]	auto[0]	128	1			T42	4		T155	2		T60	4
auto[4026531840:4160749567]	auto[1]	62	1			T86	2		T40	2		T108	2
auto[4160749568:4294967295]	auto[0]	143	1			T3	2		T27	2		T42	2
auto[4160749568:4294967295]	auto[1]	56	1			T42	2		T402	2		T94	2