Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.84 99.07 98.06 98.57 100.00 99.11 98.41 91.66


Total test records in report: 1074
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1004 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1684467381 Mar 28 12:35:22 PM PDT 24 Mar 28 12:35:23 PM PDT 24 17305888 ps
T1005 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4056519700 Mar 28 12:34:55 PM PDT 24 Mar 28 12:34:56 PM PDT 24 36234455 ps
T1006 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1048149105 Mar 28 12:35:06 PM PDT 24 Mar 28 12:35:15 PM PDT 24 229360784 ps
T1007 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1856538274 Mar 28 12:35:08 PM PDT 24 Mar 28 12:35:14 PM PDT 24 179840183 ps
T1008 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3504954553 Mar 28 12:35:00 PM PDT 24 Mar 28 12:35:10 PM PDT 24 534377923 ps
T1009 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2837304942 Mar 28 12:35:01 PM PDT 24 Mar 28 12:35:05 PM PDT 24 44973173 ps
T1010 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2688611514 Mar 28 12:35:08 PM PDT 24 Mar 28 12:35:10 PM PDT 24 21944050 ps
T1011 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2387419068 Mar 28 12:35:07 PM PDT 24 Mar 28 12:35:10 PM PDT 24 18652122 ps
T1012 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2844258386 Mar 28 12:35:26 PM PDT 24 Mar 28 12:35:28 PM PDT 24 196071763 ps
T1013 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2413300308 Mar 28 12:35:11 PM PDT 24 Mar 28 12:35:13 PM PDT 24 26041025 ps
T1014 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1551136207 Mar 28 12:35:00 PM PDT 24 Mar 28 12:35:04 PM PDT 24 59921702 ps
T1015 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.4288970112 Mar 28 12:35:22 PM PDT 24 Mar 28 12:35:24 PM PDT 24 34207922 ps
T1016 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2321190335 Mar 28 12:35:00 PM PDT 24 Mar 28 12:35:06 PM PDT 24 86264884 ps
T1017 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.728658735 Mar 28 12:34:54 PM PDT 24 Mar 28 12:34:55 PM PDT 24 22580827 ps
T1018 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2118381900 Mar 28 12:35:18 PM PDT 24 Mar 28 12:35:21 PM PDT 24 126416712 ps
T1019 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2909307614 Mar 28 12:35:15 PM PDT 24 Mar 28 12:35:18 PM PDT 24 37109251 ps
T1020 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2118163527 Mar 28 12:35:09 PM PDT 24 Mar 28 12:35:26 PM PDT 24 2313916489 ps
T1021 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4014808580 Mar 28 12:35:08 PM PDT 24 Mar 28 12:35:10 PM PDT 24 54302332 ps
T1022 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1633565096 Mar 28 12:35:11 PM PDT 24 Mar 28 12:35:14 PM PDT 24 130186068 ps
T1023 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2157501011 Mar 28 12:34:53 PM PDT 24 Mar 28 12:35:00 PM PDT 24 667548071 ps
T1024 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.251611622 Mar 28 12:35:14 PM PDT 24 Mar 28 12:35:17 PM PDT 24 280089164 ps
T1025 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.21829781 Mar 28 12:35:25 PM PDT 24 Mar 28 12:35:26 PM PDT 24 9963845 ps
T1026 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3588449645 Mar 28 12:35:24 PM PDT 24 Mar 28 12:35:25 PM PDT 24 33612407 ps
T1027 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1644703010 Mar 28 12:35:25 PM PDT 24 Mar 28 12:35:26 PM PDT 24 19357361 ps
T1028 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4111959749 Mar 28 12:35:20 PM PDT 24 Mar 28 12:35:21 PM PDT 24 13166116 ps
T1029 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.170204845 Mar 28 12:35:16 PM PDT 24 Mar 28 12:35:19 PM PDT 24 146837174 ps
T168 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3360028662 Mar 28 12:35:11 PM PDT 24 Mar 28 12:35:18 PM PDT 24 429141616 ps
T1030 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1408440972 Mar 28 12:35:11 PM PDT 24 Mar 28 12:35:16 PM PDT 24 185947317 ps
T1031 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1343847602 Mar 28 12:35:23 PM PDT 24 Mar 28 12:35:24 PM PDT 24 34150026 ps
T1032 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.928119597 Mar 28 12:35:22 PM PDT 24 Mar 28 12:35:24 PM PDT 24 9908505 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1461595747 Mar 28 12:35:08 PM PDT 24 Mar 28 12:35:11 PM PDT 24 131310967 ps
T1034 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4158938088 Mar 28 12:35:10 PM PDT 24 Mar 28 12:35:11 PM PDT 24 50113064 ps
T1035 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.985887598 Mar 28 12:35:19 PM PDT 24 Mar 28 12:35:20 PM PDT 24 38271307 ps
T1036 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2206541714 Mar 28 12:35:19 PM PDT 24 Mar 28 12:35:20 PM PDT 24 15109934 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2702896634 Mar 28 12:35:09 PM PDT 24 Mar 28 12:35:10 PM PDT 24 26355554 ps
T1038 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.652214152 Mar 28 12:34:57 PM PDT 24 Mar 28 12:34:59 PM PDT 24 30235273 ps
T1039 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4019992540 Mar 28 12:35:02 PM PDT 24 Mar 28 12:35:05 PM PDT 24 86211090 ps
T1040 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2519083316 Mar 28 12:36:13 PM PDT 24 Mar 28 12:36:16 PM PDT 24 242728082 ps
T173 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1262741186 Mar 28 12:34:55 PM PDT 24 Mar 28 12:35:01 PM PDT 24 228318499 ps
T1041 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1307733139 Mar 28 12:35:22 PM PDT 24 Mar 28 12:35:24 PM PDT 24 35581306 ps
T1042 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.686309570 Mar 28 12:35:10 PM PDT 24 Mar 28 12:35:11 PM PDT 24 11420487 ps
T1043 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1991126494 Mar 28 12:35:07 PM PDT 24 Mar 28 12:35:15 PM PDT 24 850630672 ps
T1044 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.746005935 Mar 28 12:35:05 PM PDT 24 Mar 28 12:35:14 PM PDT 24 775624489 ps
T1045 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1140106757 Mar 28 12:35:17 PM PDT 24 Mar 28 12:35:19 PM PDT 24 35248948 ps
T1046 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1234648559 Mar 28 12:35:08 PM PDT 24 Mar 28 12:35:12 PM PDT 24 191510132 ps
T1047 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.228764265 Mar 28 12:34:53 PM PDT 24 Mar 28 12:34:55 PM PDT 24 276641603 ps
T1048 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1866382899 Mar 28 12:35:19 PM PDT 24 Mar 28 12:35:23 PM PDT 24 558281283 ps
T1049 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2796938238 Mar 28 12:36:13 PM PDT 24 Mar 28 12:36:15 PM PDT 24 230441379 ps
T1050 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1837894518 Mar 28 12:35:25 PM PDT 24 Mar 28 12:35:26 PM PDT 24 8881117 ps
T1051 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3468569652 Mar 28 12:35:14 PM PDT 24 Mar 28 12:35:18 PM PDT 24 154906611 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1277041185 Mar 28 12:35:06 PM PDT 24 Mar 28 12:35:11 PM PDT 24 665164369 ps
T1053 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1045136545 Mar 28 12:35:04 PM PDT 24 Mar 28 12:35:07 PM PDT 24 668311288 ps
T170 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.238153205 Mar 28 12:36:11 PM PDT 24 Mar 28 12:36:20 PM PDT 24 304655357 ps
T1054 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3347830085 Mar 28 12:35:19 PM PDT 24 Mar 28 12:35:21 PM PDT 24 80134910 ps
T1055 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3977203062 Mar 28 12:35:09 PM PDT 24 Mar 28 12:35:11 PM PDT 24 22652951 ps
T1056 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1528711094 Mar 28 12:34:53 PM PDT 24 Mar 28 12:34:57 PM PDT 24 905166631 ps
T1057 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4261215003 Mar 28 12:35:25 PM PDT 24 Mar 28 12:35:26 PM PDT 24 8171342 ps
T1058 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.692141539 Mar 28 12:35:18 PM PDT 24 Mar 28 12:35:25 PM PDT 24 146881027 ps
T1059 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1007193890 Mar 28 12:35:23 PM PDT 24 Mar 28 12:35:24 PM PDT 24 27412550 ps
T1060 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4271856448 Mar 28 12:35:00 PM PDT 24 Mar 28 12:35:05 PM PDT 24 23894297 ps
T1061 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.579114778 Mar 28 12:35:24 PM PDT 24 Mar 28 12:35:25 PM PDT 24 12851313 ps
T1062 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3767655717 Mar 28 12:35:08 PM PDT 24 Mar 28 12:35:12 PM PDT 24 60147121 ps
T1063 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3492117146 Mar 28 12:35:25 PM PDT 24 Mar 28 12:35:26 PM PDT 24 10282637 ps
T1064 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2140620957 Mar 28 12:35:06 PM PDT 24 Mar 28 12:35:10 PM PDT 24 19064293 ps
T1065 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3524637052 Mar 28 12:35:23 PM PDT 24 Mar 28 12:35:24 PM PDT 24 30760822 ps
T1066 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.608601010 Mar 28 12:35:24 PM PDT 24 Mar 28 12:35:25 PM PDT 24 19158858 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2445042804 Mar 28 12:35:07 PM PDT 24 Mar 28 12:35:12 PM PDT 24 134102956 ps
T1068 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.251537107 Mar 28 12:35:25 PM PDT 24 Mar 28 12:35:28 PM PDT 24 909941352 ps
T1069 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.531060480 Mar 28 12:35:08 PM PDT 24 Mar 28 12:35:10 PM PDT 24 9101949 ps
T1070 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2744507386 Mar 28 12:35:08 PM PDT 24 Mar 28 12:35:11 PM PDT 24 128224146 ps
T1071 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.633014184 Mar 28 12:35:17 PM PDT 24 Mar 28 12:35:19 PM PDT 24 271360741 ps
T1072 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.483145246 Mar 28 12:34:53 PM PDT 24 Mar 28 12:34:56 PM PDT 24 103257877 ps
T1073 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3105415648 Mar 28 12:35:00 PM PDT 24 Mar 28 12:35:17 PM PDT 24 2395250110 ps
T1074 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.53194961 Mar 28 12:35:03 PM PDT 24 Mar 28 12:35:09 PM PDT 24 557939014 ps

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1652870695
Short name T18
Test name
Test status
Simulation time 214225402 ps
CPU time 5.22 seconds
Started Mar 28 01:29:21 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 208920 kb
Host smart-44628f8b-9c90-4fe5-a494-64e41016effd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652870695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1652870695
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2981776822
Short name T42
Test name
Test status
Simulation time 537543339 ps
CPU time 25.96 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 222916 kb
Host smart-432be76f-9418-41da-8677-3988b180a4c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981776822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2981776822
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3643910332
Short name T60
Test name
Test status
Simulation time 6281084780 ps
CPU time 78.96 seconds
Started Mar 28 01:29:07 PM PDT 24
Finished Mar 28 01:30:27 PM PDT 24
Peak memory 217364 kb
Host smart-45d1375c-a1cb-43ac-aaa9-fc641915f7d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643910332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3643910332
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4193966146
Short name T6
Test name
Test status
Simulation time 1987577998 ps
CPU time 25.57 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 236380 kb
Host smart-54c50e88-07d3-49be-8e14-54a6108a4b88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193966146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4193966146
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2635517757
Short name T127
Test name
Test status
Simulation time 690003267 ps
CPU time 19.04 seconds
Started Mar 28 01:28:44 PM PDT 24
Finished Mar 28 01:29:03 PM PDT 24
Peak memory 221288 kb
Host smart-ac16b3fc-53cc-4d3f-ba5c-976d8a10ade6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635517757 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2635517757
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3473387041
Short name T37
Test name
Test status
Simulation time 255787169 ps
CPU time 3.91 seconds
Started Mar 28 01:27:03 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 214652 kb
Host smart-2c0bc2cb-86ba-4c04-84a0-e9228bdf94fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473387041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3473387041
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.48137234
Short name T47
Test name
Test status
Simulation time 9692343012 ps
CPU time 63.39 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:30:45 PM PDT 24
Peak memory 215708 kb
Host smart-e35ec933-af09-458b-8be6-69640ae16d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48137234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.48137234
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1294840638
Short name T385
Test name
Test status
Simulation time 218363545 ps
CPU time 12.16 seconds
Started Mar 28 01:30:00 PM PDT 24
Finished Mar 28 01:30:12 PM PDT 24
Peak memory 214644 kb
Host smart-59c1efaf-9f28-4c02-9c32-bacab47c67c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1294840638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1294840638
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3576503727
Short name T111
Test name
Test status
Simulation time 163105979 ps
CPU time 7.02 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:30 PM PDT 24
Peak memory 214256 kb
Host smart-cce94873-9b2a-4f4a-8e0e-1d13b84cacec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576503727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3576503727
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3761224874
Short name T11
Test name
Test status
Simulation time 323460992 ps
CPU time 3.92 seconds
Started Mar 28 01:27:42 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 215020 kb
Host smart-eb316c02-445c-4be8-9df2-bc49e447ef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761224874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3761224874
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2395194068
Short name T224
Test name
Test status
Simulation time 480762123 ps
CPU time 26.57 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:29:53 PM PDT 24
Peak memory 220716 kb
Host smart-782eb926-2ef3-4451-8f95-bba92848fd6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395194068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2395194068
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.656680658
Short name T51
Test name
Test status
Simulation time 1342294670 ps
CPU time 13.68 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:37 PM PDT 24
Peak memory 222752 kb
Host smart-13c18357-7e19-40d8-a167-39332d4907b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656680658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.656680658
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.517837776
Short name T115
Test name
Test status
Simulation time 2041218129 ps
CPU time 55.84 seconds
Started Mar 28 01:27:04 PM PDT 24
Finished Mar 28 01:28:01 PM PDT 24
Peak memory 215832 kb
Host smart-718fdec5-da6a-489e-840f-b9584061bd49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=517837776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.517837776
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1330932409
Short name T87
Test name
Test status
Simulation time 835869322 ps
CPU time 8.83 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:29:56 PM PDT 24
Peak memory 214748 kb
Host smart-4b4e58b2-acf7-4abb-8e42-758e1550cc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330932409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1330932409
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.613232229
Short name T377
Test name
Test status
Simulation time 10983871908 ps
CPU time 107.82 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:29:32 PM PDT 24
Peak memory 216204 kb
Host smart-1f6cb434-bb92-4459-ab94-250cac51c5b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613232229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.613232229
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3934127602
Short name T108
Test name
Test status
Simulation time 864294007 ps
CPU time 20.88 seconds
Started Mar 28 01:28:25 PM PDT 24
Finished Mar 28 01:28:46 PM PDT 24
Peak memory 222980 kb
Host smart-efa6b326-57be-4f27-b450-053340b29458
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934127602 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3934127602
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1751467246
Short name T416
Test name
Test status
Simulation time 2800339171 ps
CPU time 38.68 seconds
Started Mar 28 01:27:31 PM PDT 24
Finished Mar 28 01:28:10 PM PDT 24
Peak memory 215472 kb
Host smart-57a27fee-4e4d-4aa2-9942-339e84568cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751467246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1751467246
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1613837173
Short name T3
Test name
Test status
Simulation time 163744075 ps
CPU time 2.65 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 210148 kb
Host smart-1330fe5a-a49b-4d33-a12c-5f2b961aec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613837173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1613837173
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2983675310
Short name T58
Test name
Test status
Simulation time 3725268281 ps
CPU time 58.37 seconds
Started Mar 28 01:26:58 PM PDT 24
Finished Mar 28 01:27:57 PM PDT 24
Peak memory 222948 kb
Host smart-c67a2f60-7180-4d30-8113-0db804654eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983675310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2983675310
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2532069007
Short name T48
Test name
Test status
Simulation time 7430159732 ps
CPU time 48.73 seconds
Started Mar 28 01:27:09 PM PDT 24
Finished Mar 28 01:27:58 PM PDT 24
Peak memory 222896 kb
Host smart-557746b3-aeca-426e-82ad-ea93132a2314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532069007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2532069007
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.525554553
Short name T206
Test name
Test status
Simulation time 4627034861 ps
CPU time 121.95 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:31:29 PM PDT 24
Peak memory 214852 kb
Host smart-6615dfb6-9f18-4c99-8915-2783d586a7dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525554553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.525554553
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3765508856
Short name T317
Test name
Test status
Simulation time 578398630 ps
CPU time 11.68 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:35 PM PDT 24
Peak memory 216172 kb
Host smart-04973c8b-270f-46e3-a977-57d12fac0b96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3765508856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3765508856
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.840047474
Short name T91
Test name
Test status
Simulation time 1377809838 ps
CPU time 35.65 seconds
Started Mar 28 01:29:10 PM PDT 24
Finished Mar 28 01:29:46 PM PDT 24
Peak memory 220452 kb
Host smart-0cd4632e-8f25-4e28-a3ef-6a574d544ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840047474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.840047474
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4176649503
Short name T63
Test name
Test status
Simulation time 1900880303 ps
CPU time 38.71 seconds
Started Mar 28 01:28:25 PM PDT 24
Finished Mar 28 01:29:04 PM PDT 24
Peak memory 215828 kb
Host smart-9d7f6928-fb2e-42ba-910a-158239ec7206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176649503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4176649503
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.441735756
Short name T915
Test name
Test status
Simulation time 1598759650 ps
CPU time 10.54 seconds
Started Mar 28 12:35:03 PM PDT 24
Finished Mar 28 12:35:15 PM PDT 24
Peak memory 214124 kb
Host smart-a09bedc1-6873-4ff0-8a3a-c7d5cde6c530
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441735756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.441735756
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.174640944
Short name T109
Test name
Test status
Simulation time 26296657 ps
CPU time 1.84 seconds
Started Mar 28 01:27:09 PM PDT 24
Finished Mar 28 01:27:11 PM PDT 24
Peak memory 210120 kb
Host smart-e5b20741-2c19-477f-98d8-0ed806583519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174640944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.174640944
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3670277059
Short name T89
Test name
Test status
Simulation time 202758989 ps
CPU time 4.35 seconds
Started Mar 28 01:28:35 PM PDT 24
Finished Mar 28 01:28:40 PM PDT 24
Peak memory 222860 kb
Host smart-65edc777-1ca3-4e80-9f43-fe104e34983a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670277059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3670277059
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4137624926
Short name T266
Test name
Test status
Simulation time 1300060626 ps
CPU time 18.27 seconds
Started Mar 28 01:27:44 PM PDT 24
Finished Mar 28 01:28:05 PM PDT 24
Peak memory 216136 kb
Host smart-ccd67a7c-0928-42e4-9e9c-d45a07360a75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137624926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4137624926
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1211268195
Short name T30
Test name
Test status
Simulation time 599655625 ps
CPU time 6.38 seconds
Started Mar 28 01:27:07 PM PDT 24
Finished Mar 28 01:27:13 PM PDT 24
Peak memory 210500 kb
Host smart-2f814e03-984a-4249-9641-dbd0381c8eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211268195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1211268195
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1458305529
Short name T255
Test name
Test status
Simulation time 341212174 ps
CPU time 10.09 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:32 PM PDT 24
Peak memory 214704 kb
Host smart-8b11c09c-861f-4b8a-bc6f-8575595b03e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458305529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1458305529
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.866090019
Short name T392
Test name
Test status
Simulation time 3593703024 ps
CPU time 99.76 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:31:05 PM PDT 24
Peak memory 216352 kb
Host smart-4afb07a8-1511-4c82-bd0b-d8dbc686d9f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=866090019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.866090019
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.52230018
Short name T59
Test name
Test status
Simulation time 72753240 ps
CPU time 3.8 seconds
Started Mar 28 01:26:59 PM PDT 24
Finished Mar 28 01:27:04 PM PDT 24
Peak memory 218460 kb
Host smart-38c28c52-2242-4f6e-b4d1-e943c16ba455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52230018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.52230018
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.656680905
Short name T33
Test name
Test status
Simulation time 1016705893 ps
CPU time 8.04 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:33 PM PDT 24
Peak memory 211036 kb
Host smart-b13e016a-3b44-40d5-86f7-1ad4065e8985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656680905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.656680905
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2550876423
Short name T214
Test name
Test status
Simulation time 39134544868 ps
CPU time 230.36 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:33:34 PM PDT 24
Peak memory 222992 kb
Host smart-af2b2d72-9acf-4bde-8838-a4e399e3f604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550876423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2550876423
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.4062027946
Short name T262
Test name
Test status
Simulation time 1066044481 ps
CPU time 42.38 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:29:22 PM PDT 24
Peak memory 217236 kb
Host smart-48fabb47-9a7f-408d-8fa7-55c8d34ac1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062027946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.4062027946
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.224518380
Short name T438
Test name
Test status
Simulation time 38590322 ps
CPU time 0.73 seconds
Started Mar 28 01:27:45 PM PDT 24
Finished Mar 28 01:27:48 PM PDT 24
Peak memory 206280 kb
Host smart-e1c09a04-d038-4fe3-9437-3e43abc1b7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224518380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.224518380
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3433164149
Short name T292
Test name
Test status
Simulation time 60015376 ps
CPU time 5.05 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:29:46 PM PDT 24
Peak memory 209252 kb
Host smart-7c039aa6-ec80-4121-a775-8e598a4ccc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433164149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3433164149
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.238153205
Short name T170
Test name
Test status
Simulation time 304655357 ps
CPU time 8.97 seconds
Started Mar 28 12:36:11 PM PDT 24
Finished Mar 28 12:36:20 PM PDT 24
Peak memory 209188 kb
Host smart-b92c8bcf-edea-4cb6-a5d2-231dd4335f11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238153205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.238153205
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2396299790
Short name T77
Test name
Test status
Simulation time 759772745 ps
CPU time 41.73 seconds
Started Mar 28 01:29:05 PM PDT 24
Finished Mar 28 01:29:47 PM PDT 24
Peak memory 222888 kb
Host smart-ba4b54fc-b0d2-4cf1-bd77-d5193c67ff06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396299790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2396299790
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.538182481
Short name T177
Test name
Test status
Simulation time 450325288 ps
CPU time 6.29 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 12:35:08 PM PDT 24
Peak memory 214008 kb
Host smart-a04ddecf-2c96-47e6-81b4-17373230027e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538182481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
538182481
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3884338244
Short name T125
Test name
Test status
Simulation time 438984151 ps
CPU time 12.53 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 222912 kb
Host smart-1f0c5aad-d7f0-40ba-aab0-0a0a7816903d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884338244 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3884338244
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1605007184
Short name T272
Test name
Test status
Simulation time 377719470 ps
CPU time 9.92 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:29 PM PDT 24
Peak memory 216076 kb
Host smart-33e47551-c63f-42a3-b8fc-c4088aee7c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605007184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1605007184
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1411663622
Short name T162
Test name
Test status
Simulation time 201632913 ps
CPU time 7.04 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 218704 kb
Host smart-8a2b994a-1a52-4780-b0d7-b8f1f27632a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411663622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1411663622
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3636521840
Short name T27
Test name
Test status
Simulation time 2919501542 ps
CPU time 10.2 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:20 PM PDT 24
Peak memory 221724 kb
Host smart-ffa102f3-50b0-4499-b1aa-1b380abf3811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636521840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3636521840
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2221756954
Short name T176
Test name
Test status
Simulation time 472475250 ps
CPU time 9.26 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 209348 kb
Host smart-2e2066af-0325-44cd-a79f-3101185b17f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221756954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2221756954
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.302735561
Short name T227
Test name
Test status
Simulation time 467299495 ps
CPU time 5.46 seconds
Started Mar 28 01:29:59 PM PDT 24
Finished Mar 28 01:30:05 PM PDT 24
Peak memory 222748 kb
Host smart-2ee37c0b-0ffe-4a43-b34f-5576b8e36089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302735561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.302735561
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2902088251
Short name T161
Test name
Test status
Simulation time 774724500 ps
CPU time 2.86 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 216712 kb
Host smart-4817f9bd-8bec-49b5-826d-75d3159e1291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902088251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2902088251
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3761924163
Short name T157
Test name
Test status
Simulation time 437736640 ps
CPU time 3.76 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 223076 kb
Host smart-ec182b17-dfd8-4c3b-ba33-ea163eb7ead8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761924163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3761924163
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3786006938
Short name T239
Test name
Test status
Simulation time 210165467 ps
CPU time 9.66 seconds
Started Mar 28 01:27:02 PM PDT 24
Finished Mar 28 01:27:12 PM PDT 24
Peak memory 222660 kb
Host smart-f1b1c6d8-23a4-4bc1-9805-069e57f5b179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786006938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3786006938
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2126980076
Short name T431
Test name
Test status
Simulation time 1827589135 ps
CPU time 91.49 seconds
Started Mar 28 01:28:50 PM PDT 24
Finished Mar 28 01:30:22 PM PDT 24
Peak memory 215776 kb
Host smart-f360a46f-bf42-4eae-a76b-b6a86632e3a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126980076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2126980076
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2432226869
Short name T311
Test name
Test status
Simulation time 253319199 ps
CPU time 4.67 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:29:32 PM PDT 24
Peak memory 214724 kb
Host smart-8dbde586-707c-4559-b7da-e8e01f30526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432226869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2432226869
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1779117364
Short name T344
Test name
Test status
Simulation time 183486874 ps
CPU time 3.72 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 206984 kb
Host smart-9ad8d6bc-0480-4ac7-91ce-bb94bf60a408
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779117364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1779117364
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4288727457
Short name T956
Test name
Test status
Simulation time 81929806 ps
CPU time 2.72 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:34:57 PM PDT 24
Peak memory 214188 kb
Host smart-b9160aeb-68b7-4ad5-bc72-ca631c43c11d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288727457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.4288727457
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1158520275
Short name T81
Test name
Test status
Simulation time 10289238471 ps
CPU time 337.74 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:32:38 PM PDT 24
Peak memory 222832 kb
Host smart-5a3078e0-8bb4-4cb8-a259-93fcf12e52dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158520275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1158520275
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.387701026
Short name T397
Test name
Test status
Simulation time 76568844 ps
CPU time 3.04 seconds
Started Mar 28 01:27:45 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 219944 kb
Host smart-afa6b1c6-0dc6-4cf4-99b3-40c980cf666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387701026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.387701026
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.197066905
Short name T308
Test name
Test status
Simulation time 112392523 ps
CPU time 4.24 seconds
Started Mar 28 01:27:42 PM PDT 24
Finished Mar 28 01:27:47 PM PDT 24
Peak memory 212164 kb
Host smart-d1a0e6fd-1c46-419c-b5e1-26cd06d57a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197066905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.197066905
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.267772201
Short name T364
Test name
Test status
Simulation time 218120131 ps
CPU time 12.69 seconds
Started Mar 28 01:29:46 PM PDT 24
Finished Mar 28 01:29:59 PM PDT 24
Peak memory 215580 kb
Host smart-ccdb9037-21c8-48dd-8bee-d1ab003397f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267772201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.267772201
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3806701800
Short name T549
Test name
Test status
Simulation time 1168227012 ps
CPU time 2.82 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:29:50 PM PDT 24
Peak memory 210224 kb
Host smart-415bce51-74a7-45f2-9965-6dde083243ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806701800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3806701800
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3891993116
Short name T220
Test name
Test status
Simulation time 221207337 ps
CPU time 3.35 seconds
Started Mar 28 01:27:19 PM PDT 24
Finished Mar 28 01:27:23 PM PDT 24
Peak memory 214612 kb
Host smart-03690ea3-3775-46af-b4a9-d6871229d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891993116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3891993116
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.320562092
Short name T79
Test name
Test status
Simulation time 12389317599 ps
CPU time 391.66 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:33:59 PM PDT 24
Peak memory 223056 kb
Host smart-5581b42e-eed6-41df-88da-696c8c9ebc3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320562092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.320562092
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.4131274978
Short name T159
Test name
Test status
Simulation time 91423828 ps
CPU time 2.75 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:12 PM PDT 24
Peak memory 223088 kb
Host smart-8700d749-d827-4f05-88d0-48f1dfda9e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131274978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.4131274978
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.39747942
Short name T160
Test name
Test status
Simulation time 375507078 ps
CPU time 5.68 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:49 PM PDT 24
Peak memory 218052 kb
Host smart-1b17850f-25a0-438c-938e-0df9ae40c818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39747942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.39747942
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1834328581
Short name T302
Test name
Test status
Simulation time 499474915 ps
CPU time 3.83 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:32 PM PDT 24
Peak memory 218564 kb
Host smart-f994950e-53c0-4437-b0fc-ac103094f49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834328581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1834328581
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.958891932
Short name T400
Test name
Test status
Simulation time 414579487 ps
CPU time 4.27 seconds
Started Mar 28 01:27:41 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 214668 kb
Host smart-4168868e-e657-4103-921f-05f5c72d0de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958891932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.958891932
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2947294919
Short name T8
Test name
Test status
Simulation time 13890856736 ps
CPU time 164.26 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:30:28 PM PDT 24
Peak memory 219536 kb
Host smart-bea14fdf-6d22-48fa-be20-376c1c3a07de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947294919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2947294919
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3598081889
Short name T353
Test name
Test status
Simulation time 1952659217 ps
CPU time 26.96 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:47 PM PDT 24
Peak memory 216232 kb
Host smart-9b080c04-ebb4-4bf1-b77d-d6e29e90e2d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598081889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3598081889
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1235304940
Short name T382
Test name
Test status
Simulation time 3405587134 ps
CPU time 26.71 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:29:03 PM PDT 24
Peak memory 214732 kb
Host smart-52e518aa-1521-402b-83c0-7a183e4576db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235304940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1235304940
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.204161365
Short name T23
Test name
Test status
Simulation time 54990120 ps
CPU time 3.48 seconds
Started Mar 28 01:28:44 PM PDT 24
Finished Mar 28 01:28:48 PM PDT 24
Peak memory 214704 kb
Host smart-bcf1656c-a607-4fa0-8813-7a1c0f367665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204161365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.204161365
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2586320719
Short name T241
Test name
Test status
Simulation time 45440285568 ps
CPU time 116.88 seconds
Started Mar 28 01:28:44 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 216644 kb
Host smart-85fd52d5-c302-4e67-a08f-96493357698f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586320719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2586320719
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1774656968
Short name T293
Test name
Test status
Simulation time 2413618857 ps
CPU time 69.62 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:30:52 PM PDT 24
Peak memory 216344 kb
Host smart-1b566982-bb00-47e3-90d8-ca99768a9c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774656968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1774656968
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.168210904
Short name T248
Test name
Test status
Simulation time 1301763514 ps
CPU time 36.2 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 215500 kb
Host smart-2d95fdbf-721f-4afd-8b8b-02d549b0d7c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168210904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.168210904
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3095936611
Short name T264
Test name
Test status
Simulation time 1155105308 ps
CPU time 7.85 seconds
Started Mar 28 01:27:19 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 222700 kb
Host smart-00b4618f-626d-408e-9d63-8bc0a20cd533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095936611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3095936611
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1431361530
Short name T180
Test name
Test status
Simulation time 250111101 ps
CPU time 8.56 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 208912 kb
Host smart-6d5eb8c9-6922-4de5-a31e-5b39ebbfc958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431361530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1431361530
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2292833792
Short name T166
Test name
Test status
Simulation time 667944491 ps
CPU time 6.14 seconds
Started Mar 28 12:35:16 PM PDT 24
Finished Mar 28 12:35:22 PM PDT 24
Peak memory 213740 kb
Host smart-74d7a24b-fd7a-42f2-a062-baca83b4cd8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292833792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2292833792
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.228676083
Short name T179
Test name
Test status
Simulation time 273388317 ps
CPU time 4.43 seconds
Started Mar 28 12:35:18 PM PDT 24
Finished Mar 28 12:35:23 PM PDT 24
Peak memory 209476 kb
Host smart-725112d7-b6c9-4c19-bb1e-bef91b26123e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228676083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.228676083
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1433113976
Short name T174
Test name
Test status
Simulation time 1471731766 ps
CPU time 9.53 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:34 PM PDT 24
Peak memory 213936 kb
Host smart-bbb4cf65-4102-47f5-8c79-6aec3c137d31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433113976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1433113976
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3790019624
Short name T171
Test name
Test status
Simulation time 412622258 ps
CPU time 5.77 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:30 PM PDT 24
Peak memory 213908 kb
Host smart-4fc54994-c1b6-4420-ad3f-21be4ff07c19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790019624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3790019624
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1475419905
Short name T172
Test name
Test status
Simulation time 1919785513 ps
CPU time 47.92 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 12:35:46 PM PDT 24
Peak memory 217316 kb
Host smart-b11d71a4-9bd6-4177-9b17-4a56e8ec09a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475419905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1475419905
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1262741186
Short name T173
Test name
Test status
Simulation time 228318499 ps
CPU time 3.43 seconds
Started Mar 28 12:34:55 PM PDT 24
Finished Mar 28 12:35:01 PM PDT 24
Peak memory 209080 kb
Host smart-644ef0ca-39db-47d2-8c6c-1ae3025ad2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262741186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1262741186
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1254073700
Short name T182
Test name
Test status
Simulation time 496763736 ps
CPU time 5.94 seconds
Started Mar 28 12:35:16 PM PDT 24
Finished Mar 28 12:35:23 PM PDT 24
Peak memory 209088 kb
Host smart-2f513c3a-083a-48de-aa43-18ea9c69beed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254073700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1254073700
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1424057497
Short name T158
Test name
Test status
Simulation time 34292973 ps
CPU time 1.92 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:22 PM PDT 24
Peak memory 217036 kb
Host smart-1ce1a0f9-5aa6-427a-bed6-90d2889f9686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424057497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1424057497
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1375427298
Short name T164
Test name
Test status
Simulation time 224097094 ps
CPU time 4.25 seconds
Started Mar 28 01:29:59 PM PDT 24
Finished Mar 28 01:30:03 PM PDT 24
Peak memory 223008 kb
Host smart-8a856914-7a7b-4ce7-92e5-c7d24b481920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375427298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1375427298
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3879181326
Short name T425
Test name
Test status
Simulation time 536931563 ps
CPU time 14.49 seconds
Started Mar 28 01:27:26 PM PDT 24
Finished Mar 28 01:27:40 PM PDT 24
Peak memory 215508 kb
Host smart-3d4271e3-1c9f-4c96-b231-2669ad30e4fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3879181326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3879181326
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.834337754
Short name T384
Test name
Test status
Simulation time 326008344 ps
CPU time 3.97 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 210488 kb
Host smart-c5ee6722-ca17-415e-b701-50d5330b74d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834337754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.834337754
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1492818011
Short name T374
Test name
Test status
Simulation time 467004649 ps
CPU time 22.3 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 215540 kb
Host smart-765b04a6-d80c-4f1b-9b7c-4996eef6d4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492818011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1492818011
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3892570155
Short name T213
Test name
Test status
Simulation time 358795903 ps
CPU time 2.35 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 210312 kb
Host smart-754e9c14-ab38-45a9-b1ba-dbbad22652a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892570155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3892570155
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2433059547
Short name T238
Test name
Test status
Simulation time 230730627 ps
CPU time 4.3 seconds
Started Mar 28 01:27:42 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 208092 kb
Host smart-f2bf9e83-c7de-413d-969f-6af4f33f27d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433059547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2433059547
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.743914323
Short name T287
Test name
Test status
Simulation time 2099411534 ps
CPU time 21.21 seconds
Started Mar 28 01:27:51 PM PDT 24
Finished Mar 28 01:28:13 PM PDT 24
Peak memory 215376 kb
Host smart-9a217497-8a6d-42e7-afc8-8808d824df17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743914323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.743914323
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1077614132
Short name T289
Test name
Test status
Simulation time 447561511 ps
CPU time 5.03 seconds
Started Mar 28 01:27:48 PM PDT 24
Finished Mar 28 01:27:53 PM PDT 24
Peak memory 222860 kb
Host smart-96496df8-a5b2-4a4c-9553-e6622084f270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077614132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1077614132
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2523512418
Short name T73
Test name
Test status
Simulation time 1945303520 ps
CPU time 27.47 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:28:11 PM PDT 24
Peak memory 216876 kb
Host smart-eec55854-3007-4112-98d6-93309438b346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523512418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2523512418
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1582598560
Short name T237
Test name
Test status
Simulation time 237543248 ps
CPU time 2.83 seconds
Started Mar 28 01:27:46 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 214636 kb
Host smart-21de91ec-433d-41f6-a783-afbac716994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582598560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1582598560
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2892798942
Short name T222
Test name
Test status
Simulation time 117292271 ps
CPU time 3.97 seconds
Started Mar 28 01:27:52 PM PDT 24
Finished Mar 28 01:27:56 PM PDT 24
Peak memory 208688 kb
Host smart-f4e0e769-8e1f-44c0-b3ea-cf001e31b105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892798942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2892798942
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1083389367
Short name T5
Test name
Test status
Simulation time 83908017 ps
CPU time 2.53 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:21 PM PDT 24
Peak memory 207136 kb
Host smart-3ae2613e-6942-4fd3-841d-88ced0f94a40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083389367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1083389367
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.4113257779
Short name T62
Test name
Test status
Simulation time 1508559203 ps
CPU time 39.3 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:29:00 PM PDT 24
Peak memory 215676 kb
Host smart-ad767843-699a-40aa-bdd6-53c660c6ecbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113257779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.4113257779
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.442636507
Short name T244
Test name
Test status
Simulation time 1021908833 ps
CPU time 21.59 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 220856 kb
Host smart-535ebb4c-388b-4f22-bab9-a2e8ae3acc3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442636507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.442636507
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2704866432
Short name T893
Test name
Test status
Simulation time 887367146 ps
CPU time 10.29 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:16 PM PDT 24
Peak memory 215216 kb
Host smart-f7ebb1a3-a5d8-41bc-ba52-2e2ac621412e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704866432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2704866432
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2448090125
Short name T357
Test name
Test status
Simulation time 2605199184 ps
CPU time 33.95 seconds
Started Mar 28 01:28:46 PM PDT 24
Finished Mar 28 01:29:20 PM PDT 24
Peak memory 216060 kb
Host smart-3c5f94fd-c500-403b-8b1d-fb355f89705f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448090125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2448090125
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.488156713
Short name T363
Test name
Test status
Simulation time 163189966 ps
CPU time 6.77 seconds
Started Mar 28 01:28:47 PM PDT 24
Finished Mar 28 01:28:54 PM PDT 24
Peak memory 222772 kb
Host smart-90e2da96-5cd3-4a9b-b226-83692993359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488156713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.488156713
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.369034380
Short name T70
Test name
Test status
Simulation time 110625435 ps
CPU time 2.38 seconds
Started Mar 28 01:28:51 PM PDT 24
Finished Mar 28 01:28:54 PM PDT 24
Peak memory 208096 kb
Host smart-0b406c43-05fc-4a24-918e-b00d7e80a7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369034380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.369034380
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2786858793
Short name T278
Test name
Test status
Simulation time 228955618 ps
CPU time 3.64 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:13 PM PDT 24
Peak memory 211696 kb
Host smart-4cc432e3-d6a6-42a9-9ab6-2f8e1ad80de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786858793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2786858793
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.662836300
Short name T130
Test name
Test status
Simulation time 941238708 ps
CPU time 14.56 seconds
Started Mar 28 01:29:45 PM PDT 24
Finished Mar 28 01:30:00 PM PDT 24
Peak memory 222696 kb
Host smart-cbf8a1f5-3fe3-41c0-81b3-adb00cb5f0b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662836300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.662836300
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.4054472409
Short name T253
Test name
Test status
Simulation time 739951889 ps
CPU time 12.9 seconds
Started Mar 28 01:27:09 PM PDT 24
Finished Mar 28 01:27:22 PM PDT 24
Peak memory 220708 kb
Host smart-9ed5a712-e9eb-4bd2-bec2-00d15416ec2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054472409 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.4054472409
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1001760433
Short name T223
Test name
Test status
Simulation time 97457205 ps
CPU time 4.8 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:28 PM PDT 24
Peak memory 211240 kb
Host smart-c0b29529-06eb-4363-acbd-7246e123626b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001760433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1001760433
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.938367086
Short name T163
Test name
Test status
Simulation time 81830166 ps
CPU time 4.5 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:25 PM PDT 24
Peak memory 215664 kb
Host smart-104dba36-e869-43f0-8b76-eb2d3031dfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938367086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.938367086
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2178953705
Short name T75
Test name
Test status
Simulation time 174759230 ps
CPU time 2.65 seconds
Started Mar 28 01:28:55 PM PDT 24
Finished Mar 28 01:28:57 PM PDT 24
Peak memory 215768 kb
Host smart-6e498cfe-61e5-4410-9c96-d6c5678b32be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178953705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2178953705
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1371017147
Short name T156
Test name
Test status
Simulation time 120710296 ps
CPU time 4.19 seconds
Started Mar 28 01:27:19 PM PDT 24
Finished Mar 28 01:27:24 PM PDT 24
Peak memory 218356 kb
Host smart-4354bafe-773b-40bf-8d2c-fceae506545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371017147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1371017147
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1221981278
Short name T152
Test name
Test status
Simulation time 7184059695 ps
CPU time 11.09 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:20 PM PDT 24
Peak memory 205920 kb
Host smart-b3ce2227-4526-4bb4-964f-80476e5721ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221981278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
221981278
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2157501011
Short name T1023
Test name
Test status
Simulation time 667548071 ps
CPU time 6.29 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 12:35:00 PM PDT 24
Peak memory 205816 kb
Host smart-4328c8b5-17e0-43c2-8444-cb8aabcb95d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157501011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
157501011
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.395889329
Short name T988
Test name
Test status
Simulation time 41823302 ps
CPU time 1.14 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:34:56 PM PDT 24
Peak memory 205572 kb
Host smart-16b13aea-6502-41d1-a8d0-118dd7d6f181
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395889329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.395889329
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2388432820
Short name T973
Test name
Test status
Simulation time 51204269 ps
CPU time 1.94 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 12:35:00 PM PDT 24
Peak memory 213968 kb
Host smart-f656c80d-e43b-4946-a800-ea3aed9cf3fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388432820 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2388432820
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3946669965
Short name T928
Test name
Test status
Simulation time 113606635 ps
CPU time 1.4 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205716 kb
Host smart-c2c4dec3-dea8-4445-8b19-e03213d786c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946669965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3946669965
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2968414653
Short name T916
Test name
Test status
Simulation time 10503298 ps
CPU time 0.79 seconds
Started Mar 28 12:35:10 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 205420 kb
Host smart-78d824ca-4df9-4105-b539-7720a3f24b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968414653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2968414653
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4271856448
Short name T1060
Test name
Test status
Simulation time 23894297 ps
CPU time 1.35 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 12:35:05 PM PDT 24
Peak memory 205700 kb
Host smart-29b7d44e-a54a-4aeb-8974-653ea74dfcb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271856448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4271856448
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.554917510
Short name T926
Test name
Test status
Simulation time 1333091269 ps
CPU time 9.11 seconds
Started Mar 28 12:34:59 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 214164 kb
Host smart-b23da385-cf4f-41f1-aaca-4f2c6bfdc3e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554917510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.554917510
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1771748540
Short name T999
Test name
Test status
Simulation time 40797512 ps
CPU time 2.16 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 213928 kb
Host smart-6388670c-3996-46f9-9d78-ca5e3d2ff5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771748540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1771748540
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3105415648
Short name T1073
Test name
Test status
Simulation time 2395250110 ps
CPU time 14.18 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 12:35:17 PM PDT 24
Peak memory 205588 kb
Host smart-75dcde2f-0cab-4ad8-88de-a3b905b2ec6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105415648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
105415648
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3819203016
Short name T948
Test name
Test status
Simulation time 135011885 ps
CPU time 6.37 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:35:00 PM PDT 24
Peak memory 205736 kb
Host smart-2d5e93d5-5988-495c-a201-a2fbfadf346e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819203016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
819203016
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4019992540
Short name T1039
Test name
Test status
Simulation time 86211090 ps
CPU time 1.06 seconds
Started Mar 28 12:35:02 PM PDT 24
Finished Mar 28 12:35:05 PM PDT 24
Peak memory 205724 kb
Host smart-f7b3d4c7-b95e-4bfe-ac50-c663e5f58b70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019992540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.4
019992540
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1551136207
Short name T1014
Test name
Test status
Simulation time 59921702 ps
CPU time 1.28 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 12:35:04 PM PDT 24
Peak memory 205728 kb
Host smart-4d2e9511-cf47-4328-aa81-85c579ff5388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551136207 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1551136207
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3894853581
Short name T992
Test name
Test status
Simulation time 11998823 ps
CPU time 0.92 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205564 kb
Host smart-9bc2eee0-efec-4af0-b61a-66fe656c576a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894853581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3894853581
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2532646474
Short name T944
Test name
Test status
Simulation time 19671061 ps
CPU time 0.7 seconds
Started Mar 28 12:34:55 PM PDT 24
Finished Mar 28 12:34:56 PM PDT 24
Peak memory 205464 kb
Host smart-3af2f328-dad1-4422-8388-07cab8d820fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532646474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2532646474
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1931240692
Short name T969
Test name
Test status
Simulation time 91677105 ps
CPU time 1.38 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:34:55 PM PDT 24
Peak memory 205732 kb
Host smart-e836e791-2f07-41ba-9fd7-c76b6fd3de67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931240692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1931240692
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.228764265
Short name T1047
Test name
Test status
Simulation time 276641603 ps
CPU time 2.51 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 12:34:55 PM PDT 24
Peak memory 222536 kb
Host smart-7fd3c897-329e-4650-8c11-1991b80fbf35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228764265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.228764265
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.382881513
Short name T921
Test name
Test status
Simulation time 1197468893 ps
CPU time 11.74 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:21 PM PDT 24
Peak memory 214224 kb
Host smart-275191a2-d597-4a3c-8e85-bf904f844f87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382881513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.382881513
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1843699845
Short name T985
Test name
Test status
Simulation time 137099248 ps
CPU time 4.36 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 12:34:57 PM PDT 24
Peak memory 213820 kb
Host smart-93660d7a-0f76-446e-a22b-b0d176cbc763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843699845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1843699845
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.483145246
Short name T1072
Test name
Test status
Simulation time 103257877 ps
CPU time 3.06 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 12:34:56 PM PDT 24
Peak memory 209512 kb
Host smart-4aa77cb4-ea93-4003-acb6-116a2702f699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483145246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
483145246
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2140620957
Short name T1064
Test name
Test status
Simulation time 19064293 ps
CPU time 1.35 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 214020 kb
Host smart-aa033078-5cef-42b9-b14c-c227bcee4492
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140620957 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2140620957
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3679220053
Short name T153
Test name
Test status
Simulation time 14125973 ps
CPU time 0.87 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205476 kb
Host smart-755e485f-f405-406f-aab2-2f8260990995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679220053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3679220053
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.985927107
Short name T904
Test name
Test status
Simulation time 16108988 ps
CPU time 0.73 seconds
Started Mar 28 12:35:05 PM PDT 24
Finished Mar 28 12:35:08 PM PDT 24
Peak memory 205312 kb
Host smart-386e1431-f957-4a57-8047-c32d110a59e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985927107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.985927107
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3164033888
Short name T941
Test name
Test status
Simulation time 122321830 ps
CPU time 1.66 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 205616 kb
Host smart-36564868-7f7a-4587-b013-1db1daafa494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164033888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3164033888
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3375572134
Short name T994
Test name
Test status
Simulation time 892834064 ps
CPU time 12.04 seconds
Started Mar 28 12:35:04 PM PDT 24
Finished Mar 28 12:35:17 PM PDT 24
Peak memory 214268 kb
Host smart-ff2838c6-0a2e-4d0d-a327-85efe3c015be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375572134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3375572134
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.692141539
Short name T1058
Test name
Test status
Simulation time 146881027 ps
CPU time 7.02 seconds
Started Mar 28 12:35:18 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 214180 kb
Host smart-954b7cb5-2786-4291-83e5-6ef16a3b4d4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692141539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.692141539
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1045136545
Short name T1053
Test name
Test status
Simulation time 668311288 ps
CPU time 1.82 seconds
Started Mar 28 12:35:04 PM PDT 24
Finished Mar 28 12:35:07 PM PDT 24
Peak memory 215884 kb
Host smart-db05b639-fe65-4fdb-af70-c44140214224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045136545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1045136545
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2019307731
Short name T918
Test name
Test status
Simulation time 188428493 ps
CPU time 1.73 seconds
Started Mar 28 12:35:05 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 214012 kb
Host smart-004927f5-f25a-41f3-9109-c928eae6875a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019307731 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2019307731
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.367426875
Short name T965
Test name
Test status
Simulation time 36257525 ps
CPU time 1.17 seconds
Started Mar 28 12:35:05 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205612 kb
Host smart-027d3e65-0a05-479b-a2d4-7ec8df35abb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367426875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.367426875
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3206330764
Short name T908
Test name
Test status
Simulation time 64060867 ps
CPU time 0.78 seconds
Started Mar 28 12:35:16 PM PDT 24
Finished Mar 28 12:35:17 PM PDT 24
Peak memory 205476 kb
Host smart-6ed36ffe-a9da-4fad-8898-dade2ebc6760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206330764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3206330764
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3767655717
Short name T1062
Test name
Test status
Simulation time 60147121 ps
CPU time 2.33 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:12 PM PDT 24
Peak memory 205508 kb
Host smart-49bf63a5-7212-4bea-86dc-06864abb38b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767655717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3767655717
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2939800497
Short name T122
Test name
Test status
Simulation time 105052086 ps
CPU time 1.97 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 214200 kb
Host smart-2a11ac85-e9d9-4c9a-ad4b-8c594670a122
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939800497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2939800497
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.170204845
Short name T1029
Test name
Test status
Simulation time 146837174 ps
CPU time 3.3 seconds
Started Mar 28 12:35:16 PM PDT 24
Finished Mar 28 12:35:19 PM PDT 24
Peak memory 214084 kb
Host smart-bd21a423-b481-4505-959a-dced1f1e5654
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170204845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.170204845
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2744507386
Short name T1070
Test name
Test status
Simulation time 128224146 ps
CPU time 1.9 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 205784 kb
Host smart-7852d7a7-ea3f-49c7-acbe-1d8b6e128642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744507386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2744507386
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1022496374
Short name T978
Test name
Test status
Simulation time 28125130 ps
CPU time 1.19 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 213960 kb
Host smart-b7fd331a-d9e7-4ef2-b346-d2b7f61cdc94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022496374 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1022496374
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.157405847
Short name T967
Test name
Test status
Simulation time 23806710 ps
CPU time 1.24 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205712 kb
Host smart-ff4ccff2-92be-460a-ba7d-282058f39fcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157405847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.157405847
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.686309570
Short name T1042
Test name
Test status
Simulation time 11420487 ps
CPU time 0.9 seconds
Started Mar 28 12:35:10 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 205432 kb
Host smart-14ffd666-5368-41ae-a98d-e60cc33fca9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686309570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.686309570
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1640134071
Short name T936
Test name
Test status
Simulation time 668364719 ps
CPU time 1.89 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 205668 kb
Host smart-d543d047-dea5-41e7-a1ee-358607b871f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640134071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1640134071
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.231653442
Short name T939
Test name
Test status
Simulation time 93234406 ps
CPU time 3.45 seconds
Started Mar 28 12:35:02 PM PDT 24
Finished Mar 28 12:35:08 PM PDT 24
Peak memory 214180 kb
Host smart-7bfa9fa1-e2bd-451c-abd6-e6fb46843476
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231653442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.231653442
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1991126494
Short name T1043
Test name
Test status
Simulation time 850630672 ps
CPU time 5.6 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:15 PM PDT 24
Peak memory 214224 kb
Host smart-bf4afc5b-78cb-41d9-86e5-a7421e5ad857
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991126494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1991126494
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2118381900
Short name T1018
Test name
Test status
Simulation time 126416712 ps
CPU time 3.33 seconds
Started Mar 28 12:35:18 PM PDT 24
Finished Mar 28 12:35:21 PM PDT 24
Peak memory 213968 kb
Host smart-5ce437dc-38d7-4507-acab-4a623c8cbdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118381900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2118381900
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1856538274
Short name T1007
Test name
Test status
Simulation time 179840183 ps
CPU time 5.03 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:14 PM PDT 24
Peak memory 208732 kb
Host smart-e517a7ab-f2b0-43bc-9a4f-41cbdab5d9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856538274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1856538274
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1461595747
Short name T1033
Test name
Test status
Simulation time 131310967 ps
CPU time 2.15 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 213980 kb
Host smart-074d877a-5ad5-4e42-82b4-9e115df4e898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461595747 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1461595747
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2389886651
Short name T933
Test name
Test status
Simulation time 17048125 ps
CPU time 1.14 seconds
Started Mar 28 12:35:19 PM PDT 24
Finished Mar 28 12:35:21 PM PDT 24
Peak memory 205736 kb
Host smart-fc142a08-48a7-4fdc-a75b-915b6ea80c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389886651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2389886651
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2206541714
Short name T1036
Test name
Test status
Simulation time 15109934 ps
CPU time 0.69 seconds
Started Mar 28 12:35:19 PM PDT 24
Finished Mar 28 12:35:20 PM PDT 24
Peak memory 205356 kb
Host smart-649682c4-5799-4d40-a7fe-e613edb22505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206541714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2206541714
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1633565096
Short name T1022
Test name
Test status
Simulation time 130186068 ps
CPU time 2.6 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:14 PM PDT 24
Peak memory 205748 kb
Host smart-393d8ac0-a88d-46d4-bf33-acdc8a731d7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633565096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1633565096
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1866382899
Short name T1048
Test name
Test status
Simulation time 558281283 ps
CPU time 3.75 seconds
Started Mar 28 12:35:19 PM PDT 24
Finished Mar 28 12:35:23 PM PDT 24
Peak memory 214244 kb
Host smart-ea3801e8-ed2a-4121-be75-59458e77e2d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866382899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1866382899
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2748916836
Short name T972
Test name
Test status
Simulation time 398389660 ps
CPU time 6.62 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:16 PM PDT 24
Peak memory 214320 kb
Host smart-b8ee3763-08e2-47c9-9d32-5bd3f91a4e0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748916836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2748916836
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1032416685
Short name T955
Test name
Test status
Simulation time 187841256 ps
CPU time 2.55 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:12 PM PDT 24
Peak memory 213964 kb
Host smart-67ff532c-e5cd-4b09-ae61-4d6b116cb8e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032416685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1032416685
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3360028662
Short name T168
Test name
Test status
Simulation time 429141616 ps
CPU time 6.38 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 214012 kb
Host smart-3f4834a0-e57c-4f80-8d4a-38b3d86055ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360028662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3360028662
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4087738962
Short name T202
Test name
Test status
Simulation time 93639206 ps
CPU time 1.55 seconds
Started Mar 28 12:35:04 PM PDT 24
Finished Mar 28 12:35:07 PM PDT 24
Peak memory 213972 kb
Host smart-7b8a85fc-7a1c-4c29-80d9-98f955f85af2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087738962 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.4087738962
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.531060480
Short name T1069
Test name
Test status
Simulation time 9101949 ps
CPU time 0.97 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205628 kb
Host smart-5ba3ffb6-ffdc-4eb6-abdf-7a3dda77c5be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531060480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.531060480
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.4104628642
Short name T931
Test name
Test status
Simulation time 37179168 ps
CPU time 0.79 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:12 PM PDT 24
Peak memory 204944 kb
Host smart-a37a1b60-8497-47fe-bd21-8803f3d962c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104628642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4104628642
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2796938238
Short name T1049
Test name
Test status
Simulation time 230441379 ps
CPU time 1.6 seconds
Started Mar 28 12:36:13 PM PDT 24
Finished Mar 28 12:36:15 PM PDT 24
Peak memory 205752 kb
Host smart-86cdfbef-71f8-47f9-b504-fc806a3e8858
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796938238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2796938238
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2445042804
Short name T1067
Test name
Test status
Simulation time 134102956 ps
CPU time 3.33 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:12 PM PDT 24
Peak memory 222228 kb
Host smart-9254a9e1-59c3-49dc-a9cb-4a9a55797a4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445042804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2445042804
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1732797717
Short name T949
Test name
Test status
Simulation time 184163795 ps
CPU time 7.32 seconds
Started Mar 28 12:35:17 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 220152 kb
Host smart-2c06e3af-82ab-4120-b030-878a15b09e0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732797717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1732797717
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2027733261
Short name T914
Test name
Test status
Simulation time 24520967 ps
CPU time 1.5 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 213912 kb
Host smart-4bc3d31b-9bb3-46a5-b55d-803609177dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027733261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2027733261
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3328575301
Short name T167
Test name
Test status
Simulation time 341081105 ps
CPU time 12.16 seconds
Started Mar 28 12:35:05 PM PDT 24
Finished Mar 28 12:35:21 PM PDT 24
Peak memory 209392 kb
Host smart-8dc32944-1a92-4ecc-8782-47708af07a5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328575301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3328575301
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3360380692
Short name T984
Test name
Test status
Simulation time 92175229 ps
CPU time 1.51 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:13 PM PDT 24
Peak memory 205880 kb
Host smart-8ac894b0-6640-4c63-ab30-8c8317c7a257
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360380692 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3360380692
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1001041084
Short name T937
Test name
Test status
Simulation time 46462383 ps
CPU time 1.05 seconds
Started Mar 28 12:35:59 PM PDT 24
Finished Mar 28 12:36:01 PM PDT 24
Peak memory 204584 kb
Host smart-3f2710c9-2261-436b-b755-df4b1e0eb31a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001041084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1001041084
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2115865538
Short name T979
Test name
Test status
Simulation time 50894438 ps
CPU time 0.84 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:12 PM PDT 24
Peak memory 205448 kb
Host smart-25aa08ab-1dde-41a9-a4ac-21ef5b4e857f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115865538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2115865538
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.4176050170
Short name T1000
Test name
Test status
Simulation time 21541047 ps
CPU time 1.36 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:12 PM PDT 24
Peak memory 205900 kb
Host smart-27d43bde-1a0f-4df7-a9f9-ebf610ed358b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176050170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.4176050170
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1408440972
Short name T1030
Test name
Test status
Simulation time 185947317 ps
CPU time 4.4 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:16 PM PDT 24
Peak memory 213612 kb
Host smart-5a2b1a20-6266-47ce-a663-ba6c2d22e2b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408440972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1408440972
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3865807321
Short name T123
Test name
Test status
Simulation time 457226316 ps
CPU time 14.25 seconds
Started Mar 28 12:35:59 PM PDT 24
Finished Mar 28 12:36:14 PM PDT 24
Peak memory 213192 kb
Host smart-d77f8117-9281-4555-8459-db825ef05b0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865807321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3865807321
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2519083316
Short name T1040
Test name
Test status
Simulation time 242728082 ps
CPU time 2.77 seconds
Started Mar 28 12:36:13 PM PDT 24
Finished Mar 28 12:36:16 PM PDT 24
Peak memory 213836 kb
Host smart-ecea8da6-925e-45c4-a7e5-3a0aa2c5500c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519083316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2519083316
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1508920875
Short name T1003
Test name
Test status
Simulation time 51637318 ps
CPU time 1.21 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205740 kb
Host smart-789d19f2-b3c9-4655-a5b2-a329867f3447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508920875 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1508920875
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.633014184
Short name T1071
Test name
Test status
Simulation time 271360741 ps
CPU time 1.17 seconds
Started Mar 28 12:35:17 PM PDT 24
Finished Mar 28 12:35:19 PM PDT 24
Peak memory 205720 kb
Host smart-f6236848-09b7-48ca-83bf-323f5a266e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633014184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.633014184
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.579114778
Short name T1061
Test name
Test status
Simulation time 12851313 ps
CPU time 0.88 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 205456 kb
Host smart-b8a8a69b-18a4-41e6-85c0-3d7160e0b287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579114778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.579114778
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1307733139
Short name T1041
Test name
Test status
Simulation time 35581306 ps
CPU time 1.58 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205796 kb
Host smart-859871fb-9825-41da-814e-7bf620d06152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307733139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1307733139
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2764394944
Short name T960
Test name
Test status
Simulation time 156187756 ps
CPU time 1.73 seconds
Started Mar 28 12:36:13 PM PDT 24
Finished Mar 28 12:36:15 PM PDT 24
Peak memory 219056 kb
Host smart-8994a1df-bd4d-4f70-a840-7ca25e1b8beb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764394944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2764394944
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2376666967
Short name T110
Test name
Test status
Simulation time 1734942077 ps
CPU time 15.08 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 220536 kb
Host smart-885697a1-735e-425e-af89-e855956929f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376666967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2376666967
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.131361845
Short name T991
Test name
Test status
Simulation time 253859293 ps
CPU time 2.18 seconds
Started Mar 28 12:35:10 PM PDT 24
Finished Mar 28 12:35:12 PM PDT 24
Peak memory 213972 kb
Host smart-9a967213-338b-4889-9b46-754dd1e48d9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131361845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.131361845
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2533416816
Short name T169
Test name
Test status
Simulation time 213757507 ps
CPU time 5.1 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:27 PM PDT 24
Peak memory 213956 kb
Host smart-46e92826-59f4-4f1a-bed6-a56dadbe9a91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533416816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2533416816
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3371256478
Short name T911
Test name
Test status
Simulation time 49161714 ps
CPU time 1.51 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:23 PM PDT 24
Peak memory 214020 kb
Host smart-0ab7ec7b-97a1-401b-b4aa-28fc545b746c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371256478 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3371256478
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2844258386
Short name T1012
Test name
Test status
Simulation time 196071763 ps
CPU time 1.03 seconds
Started Mar 28 12:35:26 PM PDT 24
Finished Mar 28 12:35:28 PM PDT 24
Peak memory 204984 kb
Host smart-12483fa7-9d20-430b-be13-b97c04044c06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844258386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2844258386
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3492117146
Short name T1063
Test name
Test status
Simulation time 10282637 ps
CPU time 0.85 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 205412 kb
Host smart-0e157493-9d3b-4911-b73f-39f6fab9290c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492117146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3492117146
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3428105174
Short name T940
Test name
Test status
Simulation time 124262739 ps
CPU time 3.97 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:28 PM PDT 24
Peak memory 205648 kb
Host smart-1bcc3c84-6753-4473-9b3b-3bfe1bbc144c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428105174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3428105174
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2170830977
Short name T117
Test name
Test status
Simulation time 60203232 ps
CPU time 2.55 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:27 PM PDT 24
Peak memory 214084 kb
Host smart-a00712d7-cba7-4d1b-9121-ab50d616a372
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170830977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2170830977
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.251537107
Short name T1068
Test name
Test status
Simulation time 909941352 ps
CPU time 3.68 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:28 PM PDT 24
Peak memory 213892 kb
Host smart-880efa02-14eb-426b-ad6a-1eb066d7c049
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251537107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.251537107
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.966252730
Short name T217
Test name
Test status
Simulation time 26133564 ps
CPU time 1.14 seconds
Started Mar 28 12:35:21 PM PDT 24
Finished Mar 28 12:35:22 PM PDT 24
Peak memory 205864 kb
Host smart-6d0701f8-8207-478c-8ada-85e0921168f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966252730 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.966252730
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.747791322
Short name T938
Test name
Test status
Simulation time 136403465 ps
CPU time 1.26 seconds
Started Mar 28 12:35:26 PM PDT 24
Finished Mar 28 12:35:28 PM PDT 24
Peak memory 205756 kb
Host smart-1d43efc2-8271-4945-ac5f-fed2c0ee8e95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747791322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.747791322
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4145869615
Short name T929
Test name
Test status
Simulation time 9988221 ps
CPU time 0.81 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:27 PM PDT 24
Peak memory 205524 kb
Host smart-5789f4a9-24ce-4f34-839a-87647b71301c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145869615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4145869615
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3347830085
Short name T1054
Test name
Test status
Simulation time 80134910 ps
CPU time 1.42 seconds
Started Mar 28 12:35:19 PM PDT 24
Finished Mar 28 12:35:21 PM PDT 24
Peak memory 205732 kb
Host smart-1ee187bc-35f5-49e2-96ab-921342eba554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347830085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3347830085
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3733710591
Short name T932
Test name
Test status
Simulation time 592819812 ps
CPU time 5.15 seconds
Started Mar 28 12:35:20 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 222452 kb
Host smart-0c74f76b-10cd-4cf8-9413-c0d76f9276e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733710591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3733710591
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.699635825
Short name T120
Test name
Test status
Simulation time 426185710 ps
CPU time 15.01 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:40 PM PDT 24
Peak memory 214348 kb
Host smart-6506c152-a875-4cef-a723-a8225c8219a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699635825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.699635825
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.362336748
Short name T1002
Test name
Test status
Simulation time 128928772 ps
CPU time 5.28 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:30 PM PDT 24
Peak memory 213908 kb
Host smart-d690cb23-d745-4b7d-b479-41875480da24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362336748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.362336748
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.425837058
Short name T959
Test name
Test status
Simulation time 16677076 ps
CPU time 1.35 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 214068 kb
Host smart-4922268d-1f2c-48d1-848f-5f0e899d9333
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425837058 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.425837058
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1343847602
Short name T1031
Test name
Test status
Simulation time 34150026 ps
CPU time 0.92 seconds
Started Mar 28 12:35:23 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205560 kb
Host smart-b32d0356-d88b-4f4f-8d93-8d0dfec9dfdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343847602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1343847602
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4111959749
Short name T1028
Test name
Test status
Simulation time 13166116 ps
CPU time 0.81 seconds
Started Mar 28 12:35:20 PM PDT 24
Finished Mar 28 12:35:21 PM PDT 24
Peak memory 205456 kb
Host smart-08e29887-a62c-4d6b-9ff9-446ef139645a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111959749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4111959749
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.577752765
Short name T983
Test name
Test status
Simulation time 878807996 ps
CPU time 2.82 seconds
Started Mar 28 12:35:23 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 205696 kb
Host smart-439fd1df-089b-42e2-bc3b-bdb7f8eec770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577752765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.577752765
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.318010614
Short name T121
Test name
Test status
Simulation time 1029715254 ps
CPU time 4.46 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:27 PM PDT 24
Peak memory 214236 kb
Host smart-8eab6076-cfaf-4815-a827-ce8bebc0441f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318010614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.318010614
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3017651053
Short name T118
Test name
Test status
Simulation time 456563758 ps
CPU time 15.71 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:39 PM PDT 24
Peak memory 220176 kb
Host smart-5ac4f478-9815-4a77-9308-71100bc0191b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017651053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3017651053
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4186048369
Short name T964
Test name
Test status
Simulation time 120693816 ps
CPU time 4.55 seconds
Started Mar 28 12:35:21 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 213816 kb
Host smart-4e2cda13-4a08-4711-a1cd-8421fa23e09d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186048369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4186048369
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3516358856
Short name T958
Test name
Test status
Simulation time 137256237 ps
CPU time 5.78 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:28 PM PDT 24
Peak memory 213956 kb
Host smart-af90864b-6cab-47f4-a1dc-d05f6ff48112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516358856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3516358856
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2040533546
Short name T998
Test name
Test status
Simulation time 552920729 ps
CPU time 8.78 seconds
Started Mar 28 12:35:02 PM PDT 24
Finished Mar 28 12:35:14 PM PDT 24
Peak memory 205756 kb
Host smart-3f8623ee-09e9-4f91-9445-d9114fedf918
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040533546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
040533546
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3286823600
Short name T975
Test name
Test status
Simulation time 669718780 ps
CPU time 17.63 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 12:35:16 PM PDT 24
Peak memory 205668 kb
Host smart-823c7d44-23c8-4844-a457-b93e33750647
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286823600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
286823600
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2702896634
Short name T1037
Test name
Test status
Simulation time 26355554 ps
CPU time 0.89 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205496 kb
Host smart-1fcb6885-67a0-4b5f-b323-d4c4389267a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702896634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
702896634
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.244627517
Short name T957
Test name
Test status
Simulation time 75729502 ps
CPU time 1.21 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 12:34:59 PM PDT 24
Peak memory 205800 kb
Host smart-dd8139fc-3109-4fec-afac-bec647b5dc99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244627517 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.244627517
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1162082381
Short name T151
Test name
Test status
Simulation time 162358873 ps
CPU time 1.04 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 12:34:54 PM PDT 24
Peak memory 205456 kb
Host smart-336261e0-60d4-430e-9db0-669a70178616
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162082381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1162082381
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.728658735
Short name T1017
Test name
Test status
Simulation time 22580827 ps
CPU time 0.69 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:34:55 PM PDT 24
Peak memory 205348 kb
Host smart-38e583de-5e82-42db-8274-2013b4411ea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728658735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.728658735
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2321190335
Short name T1016
Test name
Test status
Simulation time 86264884 ps
CPU time 2.72 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 12:35:06 PM PDT 24
Peak memory 205588 kb
Host smart-77df7a8d-bf8a-467a-8257-0e01566f2b5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321190335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2321190335
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3504954553
Short name T1008
Test name
Test status
Simulation time 534377923 ps
CPU time 6.51 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 222420 kb
Host smart-8c407a28-1d97-4e0b-85df-becd2681b90c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504954553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3504954553
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3434356292
Short name T119
Test name
Test status
Simulation time 527847887 ps
CPU time 7.63 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 12:35:17 PM PDT 24
Peak memory 214240 kb
Host smart-36e1b653-8647-4ce4-95b1-d6758d0d1470
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434356292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3434356292
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1357858600
Short name T942
Test name
Test status
Simulation time 139486645 ps
CPU time 2.58 seconds
Started Mar 28 12:34:56 PM PDT 24
Finished Mar 28 12:35:01 PM PDT 24
Peak memory 213820 kb
Host smart-0c7db24e-6d83-43ed-b899-f63fd8b36429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357858600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1357858600
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.902330623
Short name T907
Test name
Test status
Simulation time 42313063 ps
CPU time 0.87 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 205344 kb
Host smart-07254cd3-dddf-45b9-a8d1-e55dac3cfe8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902330623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.902330623
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3492721641
Short name T970
Test name
Test status
Simulation time 33788530 ps
CPU time 0.92 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 205464 kb
Host smart-a7892013-5490-4966-8423-610aef1915d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492721641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3492721641
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2464683286
Short name T922
Test name
Test status
Simulation time 10785742 ps
CPU time 0.8 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 205524 kb
Host smart-57ec1ddf-2567-4843-ad2e-d96efcefa5de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464683286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2464683286
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3862823136
Short name T910
Test name
Test status
Simulation time 12463889 ps
CPU time 0.75 seconds
Started Mar 28 12:35:26 PM PDT 24
Finished Mar 28 12:35:27 PM PDT 24
Peak memory 205436 kb
Host smart-5e6b974b-8164-4a95-b616-4455fc643a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862823136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3862823136
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.608601010
Short name T1066
Test name
Test status
Simulation time 19158858 ps
CPU time 0.74 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 205344 kb
Host smart-ce8ff01c-6070-4d4f-8115-98aba4926320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608601010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.608601010
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1684467381
Short name T1004
Test name
Test status
Simulation time 17305888 ps
CPU time 0.75 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:23 PM PDT 24
Peak memory 205316 kb
Host smart-b2361ec2-1c45-4705-aa02-8e7e3877ead4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684467381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1684467381
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4261215003
Short name T1057
Test name
Test status
Simulation time 8171342 ps
CPU time 0.76 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 205460 kb
Host smart-8e3342a9-1394-465c-8186-67de0290294f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261215003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.4261215003
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3859115019
Short name T925
Test name
Test status
Simulation time 23786778 ps
CPU time 0.79 seconds
Started Mar 28 12:35:17 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 205436 kb
Host smart-f7f131ab-e311-4411-859a-e13e6d095217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859115019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3859115019
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.985887598
Short name T1035
Test name
Test status
Simulation time 38271307 ps
CPU time 0.83 seconds
Started Mar 28 12:35:19 PM PDT 24
Finished Mar 28 12:35:20 PM PDT 24
Peak memory 205388 kb
Host smart-9aba4236-b3a5-4c80-bb61-5eea21873416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985887598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.985887598
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.440529089
Short name T902
Test name
Test status
Simulation time 37697559 ps
CPU time 0.79 seconds
Started Mar 28 12:35:23 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205376 kb
Host smart-11f130ba-61e5-49fe-81fd-0c449925ed0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440529089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.440529089
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1135992377
Short name T927
Test name
Test status
Simulation time 191847631 ps
CPU time 8.81 seconds
Started Mar 28 12:35:10 PM PDT 24
Finished Mar 28 12:35:19 PM PDT 24
Peak memory 205644 kb
Host smart-d10fdf19-c009-4b15-bb31-b8255d39f332
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135992377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
135992377
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2118163527
Short name T1020
Test name
Test status
Simulation time 2313916489 ps
CPU time 16.71 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 205728 kb
Host smart-8a843cf0-a428-405d-8ee5-aae66e790fa3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118163527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
118163527
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4056519700
Short name T1005
Test name
Test status
Simulation time 36234455 ps
CPU time 0.89 seconds
Started Mar 28 12:34:55 PM PDT 24
Finished Mar 28 12:34:56 PM PDT 24
Peak memory 205608 kb
Host smart-052f4c0e-306c-4b7c-a7ca-f7274f348fc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056519700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
056519700
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2413300308
Short name T1013
Test name
Test status
Simulation time 26041025 ps
CPU time 1.43 seconds
Started Mar 28 12:35:11 PM PDT 24
Finished Mar 28 12:35:13 PM PDT 24
Peak memory 214080 kb
Host smart-0f2d9bc1-d1b8-4cec-a93a-d19d08d73545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413300308 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2413300308
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.389589173
Short name T945
Test name
Test status
Simulation time 45484569 ps
CPU time 1.46 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 12:35:04 PM PDT 24
Peak memory 205580 kb
Host smart-c5151412-ccf2-410c-9a85-a71bf25b4b84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389589173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.389589173
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.652214152
Short name T1038
Test name
Test status
Simulation time 30235273 ps
CPU time 0.89 seconds
Started Mar 28 12:34:57 PM PDT 24
Finished Mar 28 12:34:59 PM PDT 24
Peak memory 205584 kb
Host smart-7310ae13-ce0b-43df-b45a-ccc46e37dba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652214152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.652214152
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2617573272
Short name T154
Test name
Test status
Simulation time 431852441 ps
CPU time 1.39 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205812 kb
Host smart-3c71823a-6ce2-4eaf-8d7d-2f2398cb38a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617573272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2617573272
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1528711094
Short name T1056
Test name
Test status
Simulation time 905166631 ps
CPU time 3.34 seconds
Started Mar 28 12:34:53 PM PDT 24
Finished Mar 28 12:34:57 PM PDT 24
Peak memory 222300 kb
Host smart-4b2fda43-6c41-446d-8cde-48424bf47982
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528711094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1528711094
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2449666116
Short name T976
Test name
Test status
Simulation time 342903807 ps
CPU time 4.74 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:14 PM PDT 24
Peak memory 214248 kb
Host smart-2fcd8172-1377-4f1e-8a80-e8bd5ac20b18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449666116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2449666116
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1286650826
Short name T974
Test name
Test status
Simulation time 53738781 ps
CPU time 3.16 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:34:57 PM PDT 24
Peak memory 213936 kb
Host smart-27ba7f7a-49f4-4c04-a187-ae75a58af794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286650826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1286650826
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.928119597
Short name T1032
Test name
Test status
Simulation time 9908505 ps
CPU time 0.73 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205428 kb
Host smart-8fec9dc3-ec6f-49b4-b4e6-b41f47f21848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928119597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.928119597
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2219395806
Short name T947
Test name
Test status
Simulation time 35081414 ps
CPU time 0.77 seconds
Started Mar 28 12:35:19 PM PDT 24
Finished Mar 28 12:35:20 PM PDT 24
Peak memory 205172 kb
Host smart-3c740373-5126-499d-bcf9-6573b3bfa8ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219395806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2219395806
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2445557088
Short name T906
Test name
Test status
Simulation time 29463955 ps
CPU time 0.75 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 205328 kb
Host smart-612dd568-e207-401c-a818-21f8e455a60e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445557088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2445557088
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.21829781
Short name T1025
Test name
Test status
Simulation time 9963845 ps
CPU time 0.82 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 205448 kb
Host smart-3728095e-738a-437b-a9db-b16f97cbf379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21829781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.21829781
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.841111583
Short name T913
Test name
Test status
Simulation time 20561062 ps
CPU time 0.73 seconds
Started Mar 28 12:35:19 PM PDT 24
Finished Mar 28 12:35:20 PM PDT 24
Peak memory 205224 kb
Host smart-4e6de3b9-6400-461e-a3ee-ca32ecfec925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841111583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.841111583
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.355736735
Short name T989
Test name
Test status
Simulation time 11098453 ps
CPU time 0.74 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 205404 kb
Host smart-1cdcc6a9-2a7b-42e4-8cf6-a240a885b5ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355736735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.355736735
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.360892387
Short name T903
Test name
Test status
Simulation time 34753813 ps
CPU time 0.69 seconds
Started Mar 28 12:35:23 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205312 kb
Host smart-e0979b8f-f830-4dc2-a261-c3af65ee8949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360892387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.360892387
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.97338100
Short name T905
Test name
Test status
Simulation time 43746419 ps
CPU time 0.88 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 205448 kb
Host smart-6fe1da55-5fa5-4eb6-abe1-8894e88848ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97338100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.97338100
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3524637052
Short name T1065
Test name
Test status
Simulation time 30760822 ps
CPU time 0.73 seconds
Started Mar 28 12:35:23 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205464 kb
Host smart-bc11cecf-7cb0-4df2-9a2a-8400edb22376
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524637052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3524637052
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1644703010
Short name T1027
Test name
Test status
Simulation time 19357361 ps
CPU time 0.81 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 205524 kb
Host smart-4c575055-9f2e-493b-96be-7ced729002dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644703010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1644703010
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.746005935
Short name T1044
Test name
Test status
Simulation time 775624489 ps
CPU time 4.87 seconds
Started Mar 28 12:35:05 PM PDT 24
Finished Mar 28 12:35:14 PM PDT 24
Peak memory 205548 kb
Host smart-1b5537d4-cadc-4e35-bff3-5f16721dafc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746005935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.746005935
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1695048549
Short name T963
Test name
Test status
Simulation time 438700887 ps
CPU time 13.17 seconds
Started Mar 28 12:34:54 PM PDT 24
Finished Mar 28 12:35:07 PM PDT 24
Peak memory 205796 kb
Host smart-b9c0ba0e-4b76-430d-8bad-55d9d0c653d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695048549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
695048549
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2688611514
Short name T1010
Test name
Test status
Simulation time 21944050 ps
CPU time 0.96 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205496 kb
Host smart-c638583d-012b-4bf8-95ea-11266de379a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688611514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
688611514
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3989697306
Short name T982
Test name
Test status
Simulation time 101454153 ps
CPU time 1.65 seconds
Started Mar 28 12:35:18 PM PDT 24
Finished Mar 28 12:35:21 PM PDT 24
Peak memory 214020 kb
Host smart-07a923a0-51fc-4441-8152-6a78bfae7940
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989697306 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3989697306
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2387419068
Short name T1011
Test name
Test status
Simulation time 18652122 ps
CPU time 0.89 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205496 kb
Host smart-df895d50-670b-40d9-9edf-4de9d028f7b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387419068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2387419068
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2234942362
Short name T987
Test name
Test status
Simulation time 10119546 ps
CPU time 0.71 seconds
Started Mar 28 12:35:04 PM PDT 24
Finished Mar 28 12:35:06 PM PDT 24
Peak memory 205364 kb
Host smart-de30ba26-e3ae-4e91-8ad1-0510e40ac80a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234942362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2234942362
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2182941721
Short name T954
Test name
Test status
Simulation time 94223034 ps
CPU time 3.58 seconds
Started Mar 28 12:35:00 PM PDT 24
Finished Mar 28 12:35:06 PM PDT 24
Peak memory 205728 kb
Host smart-4df8f818-1f07-4bdb-bc45-a5a5cd77cd11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182941721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2182941721
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2839033481
Short name T966
Test name
Test status
Simulation time 88501885 ps
CPU time 2.1 seconds
Started Mar 28 12:34:56 PM PDT 24
Finished Mar 28 12:35:00 PM PDT 24
Peak memory 217984 kb
Host smart-0290c19e-7197-4407-b51f-316f2aa472d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839033481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2839033481
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3309772772
Short name T923
Test name
Test status
Simulation time 163713654 ps
CPU time 6.68 seconds
Started Mar 28 12:34:58 PM PDT 24
Finished Mar 28 12:35:05 PM PDT 24
Peak memory 214216 kb
Host smart-4b46cf98-025d-4c66-ae56-5d8a5f335fbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309772772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3309772772
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3794570731
Short name T930
Test name
Test status
Simulation time 110049567 ps
CPU time 2.58 seconds
Started Mar 28 12:35:04 PM PDT 24
Finished Mar 28 12:35:08 PM PDT 24
Peak memory 214132 kb
Host smart-b32cf53e-2cb7-4d1b-a5ae-05881bc54005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794570731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3794570731
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3866350786
Short name T934
Test name
Test status
Simulation time 805143602 ps
CPU time 10.16 seconds
Started Mar 28 12:34:56 PM PDT 24
Finished Mar 28 12:35:08 PM PDT 24
Peak memory 213960 kb
Host smart-810ee010-3865-48ad-bd70-251d51c0a9e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866350786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3866350786
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1837894518
Short name T1050
Test name
Test status
Simulation time 8881117 ps
CPU time 0.83 seconds
Started Mar 28 12:35:25 PM PDT 24
Finished Mar 28 12:35:26 PM PDT 24
Peak memory 205520 kb
Host smart-f47b6391-e34a-4a37-9edc-dcc4fa05ac46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837894518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1837894518
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.4288970112
Short name T1015
Test name
Test status
Simulation time 34207922 ps
CPU time 0.85 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205524 kb
Host smart-bafebcbb-80a9-4554-8ea5-77dd30cdf5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288970112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.4288970112
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1633241006
Short name T997
Test name
Test status
Simulation time 42091388 ps
CPU time 0.84 seconds
Started Mar 28 12:35:26 PM PDT 24
Finished Mar 28 12:35:27 PM PDT 24
Peak memory 204912 kb
Host smart-6042d73b-44f9-44f3-811c-ee4cd825051c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633241006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1633241006
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.90127279
Short name T919
Test name
Test status
Simulation time 8104963 ps
CPU time 0.75 seconds
Started Mar 28 12:35:21 PM PDT 24
Finished Mar 28 12:35:22 PM PDT 24
Peak memory 205364 kb
Host smart-ffbaa1d7-96fc-477d-8978-18c86c64b1fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90127279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.90127279
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2839646675
Short name T962
Test name
Test status
Simulation time 24749467 ps
CPU time 0.73 seconds
Started Mar 28 12:35:22 PM PDT 24
Finished Mar 28 12:35:23 PM PDT 24
Peak memory 205448 kb
Host smart-1334729f-8028-485e-86c4-c4d263f36b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839646675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2839646675
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3296550012
Short name T935
Test name
Test status
Simulation time 17794089 ps
CPU time 0.73 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 205256 kb
Host smart-10a746c2-ce67-4302-9a61-d92bb82f4dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296550012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3296550012
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1177909119
Short name T909
Test name
Test status
Simulation time 21268942 ps
CPU time 0.75 seconds
Started Mar 28 12:35:23 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205336 kb
Host smart-14ac52ca-fb74-40b7-913c-0e961a671ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177909119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1177909119
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3588449645
Short name T1026
Test name
Test status
Simulation time 33612407 ps
CPU time 0.79 seconds
Started Mar 28 12:35:24 PM PDT 24
Finished Mar 28 12:35:25 PM PDT 24
Peak memory 205388 kb
Host smart-f9521acc-81f4-4785-83c2-fc33ad38a33d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588449645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3588449645
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1007193890
Short name T1059
Test name
Test status
Simulation time 27412550 ps
CPU time 0.84 seconds
Started Mar 28 12:35:23 PM PDT 24
Finished Mar 28 12:35:24 PM PDT 24
Peak memory 205376 kb
Host smart-7f52e004-00b3-47ca-b496-8008d3876ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007193890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1007193890
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1024573126
Short name T943
Test name
Test status
Simulation time 8901509 ps
CPU time 0.7 seconds
Started Mar 28 12:35:26 PM PDT 24
Finished Mar 28 12:35:27 PM PDT 24
Peak memory 205360 kb
Host smart-82e617de-390a-4df7-abc7-d206127cd066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024573126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1024573126
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3468569652
Short name T1051
Test name
Test status
Simulation time 154906611 ps
CPU time 2.81 seconds
Started Mar 28 12:35:14 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 214020 kb
Host smart-8f371345-25e5-4895-a1ef-4a8288542d4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468569652 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3468569652
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1140106757
Short name T1045
Test name
Test status
Simulation time 35248948 ps
CPU time 0.97 seconds
Started Mar 28 12:35:17 PM PDT 24
Finished Mar 28 12:35:19 PM PDT 24
Peak memory 205568 kb
Host smart-466e5807-438c-42a6-b079-f8500bfa7f0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140106757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1140106757
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3324379919
Short name T995
Test name
Test status
Simulation time 10232866 ps
CPU time 0.75 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205424 kb
Host smart-4f38c6cd-0615-4bbc-bc29-739abec37b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324379919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3324379919
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3793403844
Short name T920
Test name
Test status
Simulation time 84934355 ps
CPU time 1.26 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 205872 kb
Host smart-65f1d5db-1d70-4b34-8763-d6b38928c501
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793403844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3793403844
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.53194961
Short name T1074
Test name
Test status
Simulation time 557939014 ps
CPU time 4.57 seconds
Started Mar 28 12:35:03 PM PDT 24
Finished Mar 28 12:35:09 PM PDT 24
Peak memory 214268 kb
Host smart-952f48de-3c5a-4550-b277-fedda14e04a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53194961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_
reg_errors.53194961
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.564234127
Short name T951
Test name
Test status
Simulation time 242854681 ps
CPU time 5.09 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 12:35:15 PM PDT 24
Peak memory 214348 kb
Host smart-a7b735bd-6c15-4f50-87f0-23e08fa37317
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564234127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.564234127
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.358257333
Short name T981
Test name
Test status
Simulation time 1047490807 ps
CPU time 3.36 seconds
Started Mar 28 12:35:04 PM PDT 24
Finished Mar 28 12:35:08 PM PDT 24
Peak memory 217176 kb
Host smart-51e08430-8924-4d48-a12c-69a67abce7be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358257333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.358257333
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1234648559
Short name T1046
Test name
Test status
Simulation time 191510132 ps
CPU time 2.23 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:12 PM PDT 24
Peak memory 218400 kb
Host smart-95be89b8-19f9-4753-b5c9-f952fbfa160e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234648559 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1234648559
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4158938088
Short name T1034
Test name
Test status
Simulation time 50113064 ps
CPU time 1.02 seconds
Started Mar 28 12:35:10 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 205720 kb
Host smart-0906f960-7bda-4e55-a658-bfa12d31ece7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158938088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4158938088
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.476150705
Short name T950
Test name
Test status
Simulation time 34875198 ps
CPU time 0.78 seconds
Started Mar 28 12:35:10 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 205424 kb
Host smart-9e13b539-8a30-4a39-89cb-51ff8dffd938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476150705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.476150705
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1277041185
Short name T1052
Test name
Test status
Simulation time 665164369 ps
CPU time 1.99 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 205644 kb
Host smart-a2e4e79f-46f8-4930-8c27-776bf598c0b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277041185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1277041185
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1048149105
Short name T1006
Test name
Test status
Simulation time 229360784 ps
CPU time 6.22 seconds
Started Mar 28 12:35:06 PM PDT 24
Finished Mar 28 12:35:15 PM PDT 24
Peak memory 214316 kb
Host smart-41e23fff-938c-4564-b244-d6e07ebacb9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048149105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1048149105
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1727359154
Short name T996
Test name
Test status
Simulation time 293460458 ps
CPU time 3.91 seconds
Started Mar 28 12:35:18 PM PDT 24
Finished Mar 28 12:35:22 PM PDT 24
Peak memory 220020 kb
Host smart-9fe0f53d-2047-4fc4-9b46-92f3317efb66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727359154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1727359154
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.131636242
Short name T993
Test name
Test status
Simulation time 306503263 ps
CPU time 2.08 seconds
Started Mar 28 12:35:12 PM PDT 24
Finished Mar 28 12:35:15 PM PDT 24
Peak memory 216328 kb
Host smart-59654e22-3202-4e97-af42-81a6ac7bd5ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131636242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.131636242
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2481936230
Short name T178
Test name
Test status
Simulation time 854415482 ps
CPU time 22.73 seconds
Started Mar 28 12:35:17 PM PDT 24
Finished Mar 28 12:35:40 PM PDT 24
Peak memory 209072 kb
Host smart-12b9a5f3-a1d1-41e9-af8b-2292207baf54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481936230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2481936230
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2837304942
Short name T1009
Test name
Test status
Simulation time 44973173 ps
CPU time 2.16 seconds
Started Mar 28 12:35:01 PM PDT 24
Finished Mar 28 12:35:05 PM PDT 24
Peak memory 218096 kb
Host smart-ced27d2f-46dd-4d73-808b-dc34bf7cb314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837304942 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2837304942
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2014244825
Short name T924
Test name
Test status
Simulation time 27297674 ps
CPU time 1.1 seconds
Started Mar 28 12:35:04 PM PDT 24
Finished Mar 28 12:35:06 PM PDT 24
Peak memory 205732 kb
Host smart-1f0a698b-49b2-4c71-8eaf-56290ec77572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014244825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2014244825
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4014808580
Short name T1021
Test name
Test status
Simulation time 54302332 ps
CPU time 0.74 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205272 kb
Host smart-6c6d3e03-fe87-49bb-bcee-54a9742adefe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014808580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.4014808580
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2909307614
Short name T1019
Test name
Test status
Simulation time 37109251 ps
CPU time 2.55 seconds
Started Mar 28 12:35:15 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 205724 kb
Host smart-00e61d37-21e0-4d2e-91e5-4dc11cdad694
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909307614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2909307614
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2870702829
Short name T953
Test name
Test status
Simulation time 378260583 ps
CPU time 8.95 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 214220 kb
Host smart-1acabd1e-a73f-48da-a4dc-7b53264f45ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870702829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2870702829
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1080206604
Short name T961
Test name
Test status
Simulation time 308311954 ps
CPU time 3.56 seconds
Started Mar 28 12:35:02 PM PDT 24
Finished Mar 28 12:35:07 PM PDT 24
Peak memory 214300 kb
Host smart-67564222-e6e9-4404-bbc0-3800b3982a39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080206604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1080206604
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2048453331
Short name T968
Test name
Test status
Simulation time 34863533 ps
CPU time 2.3 seconds
Started Mar 28 12:34:59 PM PDT 24
Finished Mar 28 12:35:05 PM PDT 24
Peak memory 213856 kb
Host smart-3aa19a8a-e88c-4631-99e1-f04848b9280c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048453331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2048453331
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3368402124
Short name T165
Test name
Test status
Simulation time 100662348 ps
CPU time 5.5 seconds
Started Mar 28 12:35:16 PM PDT 24
Finished Mar 28 12:35:22 PM PDT 24
Peak memory 209252 kb
Host smart-ef676606-0fb7-45b1-ba64-79d2232d8875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368402124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3368402124
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1028157198
Short name T971
Test name
Test status
Simulation time 27294844 ps
CPU time 1.69 seconds
Started Mar 28 12:35:05 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 214064 kb
Host smart-31c90350-aacc-4602-9c81-c90d5d6e349d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028157198 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1028157198
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.802170348
Short name T946
Test name
Test status
Simulation time 26248731 ps
CPU time 1.14 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205680 kb
Host smart-44aefb5b-10af-4835-b383-3f473503a89d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802170348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.802170348
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2601186070
Short name T977
Test name
Test status
Simulation time 60002771 ps
CPU time 0.92 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:10 PM PDT 24
Peak memory 205560 kb
Host smart-c96aea04-98cd-4c0f-a53c-6a104b5d9acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601186070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2601186070
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1556129645
Short name T1001
Test name
Test status
Simulation time 35923305 ps
CPU time 1.29 seconds
Started Mar 28 12:35:17 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 205748 kb
Host smart-c1ade8bf-342f-4c1c-9484-ebc286b95c68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556129645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1556129645
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2789033579
Short name T990
Test name
Test status
Simulation time 1106548913 ps
CPU time 6.28 seconds
Started Mar 28 12:35:05 PM PDT 24
Finished Mar 28 12:35:14 PM PDT 24
Peak memory 214180 kb
Host smart-38a34fa7-fce8-4c44-af8b-f8f6699284c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789033579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2789033579
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.453032232
Short name T112
Test name
Test status
Simulation time 102276579 ps
CPU time 4.06 seconds
Started Mar 28 12:35:07 PM PDT 24
Finished Mar 28 12:35:13 PM PDT 24
Peak memory 214172 kb
Host smart-ae7276e5-28c8-401b-a663-7ea7535ad219
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453032232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.453032232
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3977203062
Short name T1055
Test name
Test status
Simulation time 22652951 ps
CPU time 1.63 seconds
Started Mar 28 12:35:09 PM PDT 24
Finished Mar 28 12:35:11 PM PDT 24
Peak memory 213996 kb
Host smart-7fd4e154-79e3-4b8c-b9c1-237445c3790e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977203062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3977203062
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2282133610
Short name T917
Test name
Test status
Simulation time 57816623 ps
CPU time 1.53 seconds
Started Mar 28 12:35:16 PM PDT 24
Finished Mar 28 12:35:18 PM PDT 24
Peak memory 214028 kb
Host smart-ddc95ca1-f76c-4475-b130-ac119afc5b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282133610 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2282133610
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3215780123
Short name T952
Test name
Test status
Simulation time 55880591 ps
CPU time 1.22 seconds
Started Mar 28 12:35:18 PM PDT 24
Finished Mar 28 12:35:20 PM PDT 24
Peak memory 205768 kb
Host smart-96f74075-a306-4ebd-83e9-9376370ee1b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215780123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3215780123
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.177944860
Short name T912
Test name
Test status
Simulation time 16104585 ps
CPU time 0.71 seconds
Started Mar 28 12:35:04 PM PDT 24
Finished Mar 28 12:35:08 PM PDT 24
Peak memory 205472 kb
Host smart-125336ac-87d3-4274-85c4-a644b2d76089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177944860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.177944860
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.588675640
Short name T986
Test name
Test status
Simulation time 29720680 ps
CPU time 1.32 seconds
Started Mar 28 12:35:16 PM PDT 24
Finished Mar 28 12:35:17 PM PDT 24
Peak memory 205616 kb
Host smart-cbf2c948-2334-426e-a9fe-494dec8fd1e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588675640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.588675640
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.251611622
Short name T1024
Test name
Test status
Simulation time 280089164 ps
CPU time 2.62 seconds
Started Mar 28 12:35:14 PM PDT 24
Finished Mar 28 12:35:17 PM PDT 24
Peak memory 222320 kb
Host smart-2e233ce2-37e2-4291-bb8e-c972ac6d3986
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251611622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.251611622
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1367444915
Short name T980
Test name
Test status
Simulation time 109270606 ps
CPU time 3.97 seconds
Started Mar 28 12:35:08 PM PDT 24
Finished Mar 28 12:35:13 PM PDT 24
Peak memory 213944 kb
Host smart-fe0c59aa-da4e-4759-b411-b5c7aed845c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367444915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1367444915
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3934494472
Short name T736
Test name
Test status
Simulation time 60385458 ps
CPU time 0.76 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:01 PM PDT 24
Peak memory 206336 kb
Host smart-7c6cca2c-a91e-4e97-8500-a80ed9ce5230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934494472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3934494472
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1125267378
Short name T429
Test name
Test status
Simulation time 123381650 ps
CPU time 3.3 seconds
Started Mar 28 01:26:41 PM PDT 24
Finished Mar 28 01:26:44 PM PDT 24
Peak memory 214724 kb
Host smart-6e9a5685-98a9-44fb-bbe4-6fc57bde3c3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125267378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1125267378
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.396880570
Short name T708
Test name
Test status
Simulation time 170791935 ps
CPU time 3.81 seconds
Started Mar 28 01:26:44 PM PDT 24
Finished Mar 28 01:26:48 PM PDT 24
Peak memory 210104 kb
Host smart-79251a34-b0ac-4985-9817-409170a936a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396880570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.396880570
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.879161467
Short name T727
Test name
Test status
Simulation time 102521972 ps
CPU time 5.35 seconds
Started Mar 28 01:26:58 PM PDT 24
Finished Mar 28 01:27:04 PM PDT 24
Peak memory 210124 kb
Host smart-628ecf7c-71f2-4d5a-a8f9-0cc7f1c67e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879161467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.879161467
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4193988914
Short name T242
Test name
Test status
Simulation time 1367024823 ps
CPU time 4.09 seconds
Started Mar 28 01:26:59 PM PDT 24
Finished Mar 28 01:27:03 PM PDT 24
Peak memory 222788 kb
Host smart-2acb142f-6fdf-4a1f-99fe-2351eff83edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193988914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4193988914
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3300413774
Short name T480
Test name
Test status
Simulation time 674129979 ps
CPU time 8.33 seconds
Started Mar 28 01:26:41 PM PDT 24
Finished Mar 28 01:26:49 PM PDT 24
Peak memory 210152 kb
Host smart-346dede5-0c39-477c-8f8e-3a5409c11123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300413774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3300413774
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1782619882
Short name T13
Test name
Test status
Simulation time 3561766217 ps
CPU time 24.16 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 235764 kb
Host smart-54274322-5cd2-480b-b0d5-e921950c9043
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782619882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1782619882
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3966425302
Short name T226
Test name
Test status
Simulation time 672747853 ps
CPU time 7.59 seconds
Started Mar 28 01:26:40 PM PDT 24
Finished Mar 28 01:26:48 PM PDT 24
Peak memory 207732 kb
Host smart-e854ed8e-1b3f-440e-ae76-646592e65e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966425302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3966425302
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3847054682
Short name T816
Test name
Test status
Simulation time 129404426 ps
CPU time 2.19 seconds
Started Mar 28 01:26:42 PM PDT 24
Finished Mar 28 01:26:44 PM PDT 24
Peak memory 207680 kb
Host smart-41d7d23d-6a68-4bb1-b13a-21add01b8558
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847054682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3847054682
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3524918994
Short name T725
Test name
Test status
Simulation time 285734933 ps
CPU time 5.15 seconds
Started Mar 28 01:26:39 PM PDT 24
Finished Mar 28 01:26:44 PM PDT 24
Peak memory 208988 kb
Host smart-cd390232-c6e3-4606-9e8d-8fd141809120
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524918994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3524918994
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1316266003
Short name T137
Test name
Test status
Simulation time 124540087 ps
CPU time 2.9 seconds
Started Mar 28 01:26:38 PM PDT 24
Finished Mar 28 01:26:41 PM PDT 24
Peak memory 209032 kb
Host smart-9bb69cf3-0a80-47a6-aa5b-5aaec13bbb18
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316266003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1316266003
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2360926825
Short name T370
Test name
Test status
Simulation time 452388407 ps
CPU time 5.36 seconds
Started Mar 28 01:27:02 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 216464 kb
Host smart-12d9667e-7aff-43c5-a5d6-1c0e5cd72af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360926825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2360926825
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1781018699
Short name T537
Test name
Test status
Simulation time 487232307 ps
CPU time 6.03 seconds
Started Mar 28 01:26:43 PM PDT 24
Finished Mar 28 01:26:50 PM PDT 24
Peak memory 208648 kb
Host smart-0e97bf6f-f277-4b55-87bb-82200879a1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781018699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1781018699
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2929666478
Short name T324
Test name
Test status
Simulation time 2191287240 ps
CPU time 28.43 seconds
Started Mar 28 01:26:59 PM PDT 24
Finished Mar 28 01:27:28 PM PDT 24
Peak memory 221100 kb
Host smart-42f6ae72-b633-4cef-bb98-5b6aa09c841c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929666478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2929666478
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3663376029
Short name T780
Test name
Test status
Simulation time 7425297847 ps
CPU time 22.94 seconds
Started Mar 28 01:26:57 PM PDT 24
Finished Mar 28 01:27:21 PM PDT 24
Peak memory 218756 kb
Host smart-e49ae2cd-06e7-461f-82df-69fe4edb187f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663376029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3663376029
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1700219055
Short name T186
Test name
Test status
Simulation time 77092823 ps
CPU time 3.17 seconds
Started Mar 28 01:26:59 PM PDT 24
Finished Mar 28 01:27:03 PM PDT 24
Peak memory 210416 kb
Host smart-665d425d-aecc-450f-8cb8-4e2e2d9c13e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700219055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1700219055
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4251862323
Short name T470
Test name
Test status
Simulation time 131588416 ps
CPU time 0.96 seconds
Started Mar 28 01:27:04 PM PDT 24
Finished Mar 28 01:27:06 PM PDT 24
Peak memory 206384 kb
Host smart-b8fa65e3-88f7-46a5-a526-6ea4008c3f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251862323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4251862323
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.289767004
Short name T257
Test name
Test status
Simulation time 3002405881 ps
CPU time 12.01 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:13 PM PDT 24
Peak memory 214768 kb
Host smart-b2115ef4-6e6c-426e-b5c9-c3bd4f026d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289767004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.289767004
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2461178077
Short name T701
Test name
Test status
Simulation time 1224488731 ps
CPU time 10.45 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:11 PM PDT 24
Peak memory 219568 kb
Host smart-d4a2a1e2-a35e-4aea-8f3f-669536460d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461178077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2461178077
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2717748295
Short name T548
Test name
Test status
Simulation time 29512995 ps
CPU time 2.05 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:03 PM PDT 24
Peak memory 214680 kb
Host smart-5aab51fc-5fc2-405c-b012-e054f1f7f4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717748295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2717748295
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1685415479
Short name T395
Test name
Test status
Simulation time 541626211 ps
CPU time 6.85 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 221748 kb
Host smart-4852bb3a-c565-4bfb-a9ea-714c5ef56365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685415479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1685415479
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1474128695
Short name T279
Test name
Test status
Simulation time 85862554 ps
CPU time 5.61 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:06 PM PDT 24
Peak memory 214636 kb
Host smart-3ec35052-c5ef-41b6-acf9-c049dbb80032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474128695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1474128695
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.842573566
Short name T819
Test name
Test status
Simulation time 42515681 ps
CPU time 3.34 seconds
Started Mar 28 01:27:02 PM PDT 24
Finished Mar 28 01:27:05 PM PDT 24
Peak memory 210772 kb
Host smart-a8b5cb86-3c59-4fa3-971e-887abe0d610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842573566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.842573566
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2341579595
Short name T489
Test name
Test status
Simulation time 2193674902 ps
CPU time 14.32 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:15 PM PDT 24
Peak memory 209652 kb
Host smart-3cd24116-56d3-4a84-a80a-54fa469a4cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341579595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2341579595
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.160843988
Short name T12
Test name
Test status
Simulation time 1737387764 ps
CPU time 13.66 seconds
Started Mar 28 01:27:02 PM PDT 24
Finished Mar 28 01:27:15 PM PDT 24
Peak memory 232400 kb
Host smart-0e43c563-e05f-4310-bf5a-f1872479d47a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160843988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.160843988
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1895111897
Short name T650
Test name
Test status
Simulation time 36939682 ps
CPU time 2.47 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:03 PM PDT 24
Peak memory 207108 kb
Host smart-f3380a58-cf76-4ecd-a192-3a74744e4a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895111897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1895111897
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1025664325
Short name T260
Test name
Test status
Simulation time 596194366 ps
CPU time 5.16 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 208732 kb
Host smart-e1165481-ad4f-4aee-8139-2c8c125547bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025664325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1025664325
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.405911937
Short name T573
Test name
Test status
Simulation time 37467919 ps
CPU time 2.15 seconds
Started Mar 28 01:27:02 PM PDT 24
Finished Mar 28 01:27:04 PM PDT 24
Peak memory 208224 kb
Host smart-ad8413b7-8c8d-407e-b74a-b57107bab645
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405911937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.405911937
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1584929929
Short name T864
Test name
Test status
Simulation time 219315544 ps
CPU time 6.07 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 209096 kb
Host smart-eadfac77-60d8-4982-9834-50188a9ba326
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584929929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1584929929
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1736442564
Short name T564
Test name
Test status
Simulation time 101118466 ps
CPU time 2.28 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:02 PM PDT 24
Peak memory 210068 kb
Host smart-4d84db97-ff4a-4d7d-a8ae-3dccd8e5d3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736442564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1736442564
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1186820239
Short name T787
Test name
Test status
Simulation time 99124521 ps
CPU time 2.1 seconds
Started Mar 28 01:26:57 PM PDT 24
Finished Mar 28 01:26:59 PM PDT 24
Peak memory 208540 kb
Host smart-a7609e16-9b74-485d-8048-66d57e88f7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186820239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1186820239
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3121247352
Short name T654
Test name
Test status
Simulation time 586515973 ps
CPU time 5.12 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:06 PM PDT 24
Peak memory 207864 kb
Host smart-8f66cdab-6387-42a1-8029-29fe8986d0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121247352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3121247352
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2809077471
Short name T752
Test name
Test status
Simulation time 1382390456 ps
CPU time 24.79 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:25 PM PDT 24
Peak memory 211184 kb
Host smart-4d53dbcd-e614-4dfd-896d-1f332b6f811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809077471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2809077471
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1089263662
Short name T881
Test name
Test status
Simulation time 139722147 ps
CPU time 0.84 seconds
Started Mar 28 01:27:18 PM PDT 24
Finished Mar 28 01:27:19 PM PDT 24
Peak memory 206280 kb
Host smart-3a3a6ff9-a28f-4b75-bb00-5a23bac31ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089263662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1089263662
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1913253521
Short name T810
Test name
Test status
Simulation time 755384434 ps
CPU time 5.38 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:33 PM PDT 24
Peak memory 209012 kb
Host smart-9d4029ca-7b86-4a28-a761-f671d25e404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913253521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1913253521
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2122064019
Short name T56
Test name
Test status
Simulation time 37628678 ps
CPU time 2.38 seconds
Started Mar 28 01:27:24 PM PDT 24
Finished Mar 28 01:27:28 PM PDT 24
Peak memory 218624 kb
Host smart-b1a1d7b5-0cc0-40d2-b540-d84c86a0d07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122064019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2122064019
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.271402445
Short name T856
Test name
Test status
Simulation time 606489516 ps
CPU time 6.7 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:34 PM PDT 24
Peak memory 209752 kb
Host smart-b8ee7e0f-1a92-4ed3-91f5-b4f51e4bdf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271402445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.271402445
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1143880754
Short name T53
Test name
Test status
Simulation time 73175433 ps
CPU time 2.96 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 215616 kb
Host smart-3f742589-7dc0-4322-bd05-40f3d2cdbdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143880754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1143880754
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.338647940
Short name T686
Test name
Test status
Simulation time 62451237 ps
CPU time 3.59 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 207968 kb
Host smart-2a0fdc25-aa09-4d1f-b3f2-b66eff72539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338647940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.338647940
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2992596770
Short name T358
Test name
Test status
Simulation time 201372383 ps
CPU time 2.5 seconds
Started Mar 28 01:27:26 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 208924 kb
Host smart-b3f40eed-b78b-4027-a9cc-48a2f8e71ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992596770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2992596770
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3188742664
Short name T712
Test name
Test status
Simulation time 252028743 ps
CPU time 3.02 seconds
Started Mar 28 01:27:24 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 207628 kb
Host smart-5647b037-502c-4abf-8874-d2ccf62ac620
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188742664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3188742664
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4169594077
Short name T586
Test name
Test status
Simulation time 4390353598 ps
CPU time 17.66 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:41 PM PDT 24
Peak memory 208488 kb
Host smart-06f89961-8274-45b4-afc6-1c14d77639dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169594077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4169594077
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2893257269
Short name T731
Test name
Test status
Simulation time 1134242399 ps
CPU time 31.52 seconds
Started Mar 28 01:27:27 PM PDT 24
Finished Mar 28 01:27:59 PM PDT 24
Peak memory 208448 kb
Host smart-6ad7dc3d-6496-4e49-b202-ea4fae873682
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893257269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2893257269
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2135391849
Short name T611
Test name
Test status
Simulation time 119766940 ps
CPU time 3.75 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 216052 kb
Host smart-5f2f4f50-f2df-4091-a0bf-d0267a4408ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135391849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2135391849
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3480685943
Short name T129
Test name
Test status
Simulation time 168103519 ps
CPU time 3.46 seconds
Started Mar 28 01:27:27 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 206876 kb
Host smart-d8faa512-4623-4bfc-93d1-7e414c9c0d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480685943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3480685943
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1719705802
Short name T303
Test name
Test status
Simulation time 8920639133 ps
CPU time 208.48 seconds
Started Mar 28 01:27:25 PM PDT 24
Finished Mar 28 01:30:54 PM PDT 24
Peak memory 222980 kb
Host smart-2ce5555c-ab34-488e-93b3-a675cd0e3a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719705802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1719705802
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1817675160
Short name T107
Test name
Test status
Simulation time 1228611432 ps
CPU time 10.36 seconds
Started Mar 28 01:27:19 PM PDT 24
Finished Mar 28 01:27:30 PM PDT 24
Peak memory 222984 kb
Host smart-b8cecbc7-ee85-4217-9db3-fbdd2e356286
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817675160 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1817675160
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3797161692
Short name T583
Test name
Test status
Simulation time 33575363 ps
CPU time 2.77 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 209888 kb
Host smart-98934510-8bf2-4f90-882a-599f4fc631db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797161692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3797161692
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1901144459
Short name T389
Test name
Test status
Simulation time 71153794 ps
CPU time 1.97 seconds
Started Mar 28 01:27:27 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 209920 kb
Host smart-c4d92219-ca50-404a-bbfd-3d3797ea8290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901144459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1901144459
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.880339501
Short name T528
Test name
Test status
Simulation time 13393303 ps
CPU time 0.79 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:24 PM PDT 24
Peak memory 206212 kb
Host smart-66f9d965-117d-43a4-b004-c5d88f92dbd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880339501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.880339501
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2352726300
Short name T424
Test name
Test status
Simulation time 66520451 ps
CPU time 4.61 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:33 PM PDT 24
Peak memory 215104 kb
Host smart-67e98229-c54c-4c9b-bec6-2536956e9936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352726300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2352726300
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3927202452
Short name T406
Test name
Test status
Simulation time 334945945 ps
CPU time 3.48 seconds
Started Mar 28 01:27:20 PM PDT 24
Finished Mar 28 01:27:23 PM PDT 24
Peak memory 218648 kb
Host smart-1d754643-975b-4385-9a34-3dbacb8aa9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927202452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3927202452
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2437922287
Short name T653
Test name
Test status
Simulation time 74469352 ps
CPU time 3.69 seconds
Started Mar 28 01:27:20 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 214724 kb
Host smart-65d5867d-1a5f-40bd-9e3f-b0827297abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437922287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2437922287
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3910637620
Short name T603
Test name
Test status
Simulation time 3885321418 ps
CPU time 48.96 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:28:17 PM PDT 24
Peak memory 217328 kb
Host smart-9abdc0e5-269c-4a90-b96d-114f89e5da16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910637620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3910637620
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3603904919
Short name T453
Test name
Test status
Simulation time 253599587 ps
CPU time 3.79 seconds
Started Mar 28 01:27:20 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 209704 kb
Host smart-655de6ff-9919-4741-a10e-ddbf8201f145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603904919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3603904919
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2785583250
Short name T680
Test name
Test status
Simulation time 661460593 ps
CPU time 8.75 seconds
Started Mar 28 01:27:25 PM PDT 24
Finished Mar 28 01:27:35 PM PDT 24
Peak memory 214664 kb
Host smart-2156e9f5-92ba-4e5a-a8fd-1f8db19d050f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785583250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2785583250
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3407871781
Short name T553
Test name
Test status
Simulation time 1933120723 ps
CPU time 64.14 seconds
Started Mar 28 01:27:26 PM PDT 24
Finished Mar 28 01:28:30 PM PDT 24
Peak memory 208688 kb
Host smart-f53113b1-2eb6-48eb-b436-a29f632a3f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407871781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3407871781
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.275828878
Short name T410
Test name
Test status
Simulation time 1322087771 ps
CPU time 22.69 seconds
Started Mar 28 01:27:27 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 208744 kb
Host smart-c98d8237-271e-4970-91e2-4bbbe5e23106
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275828878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.275828878
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1553984972
Short name T769
Test name
Test status
Simulation time 188617405 ps
CPU time 3.47 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:32 PM PDT 24
Peak memory 209000 kb
Host smart-3c78f51d-7a17-425a-a4cf-78cf9370cbc9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553984972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1553984972
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1229857727
Short name T612
Test name
Test status
Simulation time 79501949 ps
CPU time 2.48 seconds
Started Mar 28 01:27:27 PM PDT 24
Finished Mar 28 01:27:30 PM PDT 24
Peak memory 207164 kb
Host smart-198c30fb-fbc4-4e65-967b-dc8e4b3d245d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229857727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1229857727
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2638396600
Short name T899
Test name
Test status
Simulation time 41904329 ps
CPU time 2.44 seconds
Started Mar 28 01:27:27 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 210624 kb
Host smart-76bcce16-457a-4c81-a65b-bbe1b1b5bc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638396600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2638396600
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.876400388
Short name T883
Test name
Test status
Simulation time 77951608 ps
CPU time 2.94 seconds
Started Mar 28 01:27:27 PM PDT 24
Finished Mar 28 01:27:30 PM PDT 24
Peak memory 208572 kb
Host smart-a4cbaf99-a715-4637-9a4d-91db48610d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876400388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.876400388
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3773390790
Short name T66
Test name
Test status
Simulation time 1261123279 ps
CPU time 14.48 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:38 PM PDT 24
Peak memory 223008 kb
Host smart-e11192d5-00fc-47cb-8249-3b9da4b509bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773390790 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3773390790
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1277820557
Short name T339
Test name
Test status
Simulation time 648630014 ps
CPU time 5.74 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:33 PM PDT 24
Peak memory 210744 kb
Host smart-0bea1adc-e122-484a-a40f-cfd2fa3146ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277820557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1277820557
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3721981694
Short name T452
Test name
Test status
Simulation time 93149972 ps
CPU time 0.95 seconds
Started Mar 28 01:27:45 PM PDT 24
Finished Mar 28 01:27:48 PM PDT 24
Peak memory 206404 kb
Host smart-af1cb9d9-88e5-473f-b8bb-a973973514b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721981694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3721981694
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3558715749
Short name T777
Test name
Test status
Simulation time 105692244 ps
CPU time 3.38 seconds
Started Mar 28 01:27:24 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 219440 kb
Host smart-8f0b7e4f-6437-42ee-bfdd-572e29991170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558715749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3558715749
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1938818620
Short name T64
Test name
Test status
Simulation time 136716181 ps
CPU time 3.4 seconds
Started Mar 28 01:27:31 PM PDT 24
Finished Mar 28 01:27:35 PM PDT 24
Peak memory 218600 kb
Host smart-bfd087f1-ce5d-4834-9e45-94f3e33bb7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938818620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1938818620
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3354710845
Short name T526
Test name
Test status
Simulation time 134356180 ps
CPU time 2.51 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 209996 kb
Host smart-77cc14d4-d7ab-45db-8bc0-ff88b88779f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354710845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3354710845
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.885383965
Short name T781
Test name
Test status
Simulation time 1684119071 ps
CPU time 51.67 seconds
Started Mar 28 01:27:31 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 214744 kb
Host smart-2b5b8651-a067-4e96-89b7-3416431944a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885383965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.885383965
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.467519285
Short name T527
Test name
Test status
Simulation time 164948825 ps
CPU time 5.45 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 208176 kb
Host smart-429ebce8-675a-42fe-b2ad-61a7f6b34c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467519285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.467519285
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3075795488
Short name T591
Test name
Test status
Simulation time 990223768 ps
CPU time 7.69 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 208232 kb
Host smart-aecd9f45-1385-4c19-afdf-c53b41212e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075795488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3075795488
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2147562076
Short name T719
Test name
Test status
Simulation time 1245431866 ps
CPU time 3.96 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 208996 kb
Host smart-0f22d48e-2354-4469-b665-91380823c6bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147562076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2147562076
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4151001868
Short name T901
Test name
Test status
Simulation time 54195796 ps
CPU time 2.97 seconds
Started Mar 28 01:27:31 PM PDT 24
Finished Mar 28 01:27:34 PM PDT 24
Peak memory 208972 kb
Host smart-fa8f9b00-df29-4502-bc8f-e2562a126898
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151001868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4151001868
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3648068085
Short name T694
Test name
Test status
Simulation time 145558724 ps
CPU time 4.03 seconds
Started Mar 28 01:27:31 PM PDT 24
Finished Mar 28 01:27:35 PM PDT 24
Peak memory 209104 kb
Host smart-f3485a4f-2791-46dc-bf1e-9a6d40e50839
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648068085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3648068085
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1673424954
Short name T714
Test name
Test status
Simulation time 50121620 ps
CPU time 2.49 seconds
Started Mar 28 01:27:44 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 218600 kb
Host smart-1f2e9850-c453-4e65-9c9c-3343ed7e4eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673424954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1673424954
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.66998543
Short name T522
Test name
Test status
Simulation time 754512949 ps
CPU time 17.31 seconds
Started Mar 28 01:27:20 PM PDT 24
Finished Mar 28 01:27:37 PM PDT 24
Peak memory 208652 kb
Host smart-3b57d598-4d09-4765-942e-9ef9a69e7634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66998543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.66998543
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.502998669
Short name T690
Test name
Test status
Simulation time 7095033470 ps
CPU time 227.79 seconds
Started Mar 28 01:27:47 PM PDT 24
Finished Mar 28 01:31:35 PM PDT 24
Peak memory 222952 kb
Host smart-73e11947-6c4b-4c87-ac1d-18a260772db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502998669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.502998669
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.789131315
Short name T99
Test name
Test status
Simulation time 483057954 ps
CPU time 5.51 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 210432 kb
Host smart-f025ed88-e4ab-45aa-a5fe-cc0b2c1b4861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789131315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.789131315
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1520186339
Short name T216
Test name
Test status
Simulation time 682975638 ps
CPU time 2.66 seconds
Started Mar 28 01:27:45 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 210176 kb
Host smart-128e5f40-71b3-41c8-acde-5d2c34f36790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520186339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1520186339
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.709187311
Short name T598
Test name
Test status
Simulation time 44794997 ps
CPU time 0.73 seconds
Started Mar 28 01:27:49 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 206296 kb
Host smart-18dee19a-267d-4b00-9848-2b199aeec732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709187311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.709187311
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.327257951
Short name T61
Test name
Test status
Simulation time 419601403 ps
CPU time 3.63 seconds
Started Mar 28 01:27:42 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 207816 kb
Host smart-7a3a671c-eb98-4f14-b53d-a70d815b55e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327257951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.327257951
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2140978085
Short name T647
Test name
Test status
Simulation time 98303332 ps
CPU time 3.64 seconds
Started Mar 28 01:27:48 PM PDT 24
Finished Mar 28 01:27:52 PM PDT 24
Peak memory 210456 kb
Host smart-f0db87f2-5977-450f-b187-b454793ac5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140978085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2140978085
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.578238020
Short name T200
Test name
Test status
Simulation time 7451620930 ps
CPU time 45 seconds
Started Mar 28 01:27:47 PM PDT 24
Finished Mar 28 01:28:32 PM PDT 24
Peak memory 209916 kb
Host smart-5d80d137-149e-45aa-bf80-d9ba4d90b77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578238020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.578238020
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3811654701
Short name T632
Test name
Test status
Simulation time 83065041 ps
CPU time 1.88 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 206968 kb
Host smart-b1775098-fb26-4fa7-ac02-0fc457cc6bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811654701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3811654701
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2340161091
Short name T805
Test name
Test status
Simulation time 236621545 ps
CPU time 4.28 seconds
Started Mar 28 01:27:44 PM PDT 24
Finished Mar 28 01:27:51 PM PDT 24
Peak memory 209008 kb
Host smart-1b49606a-998f-490e-8302-a4d2bf0eab29
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340161091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2340161091
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3847683978
Short name T828
Test name
Test status
Simulation time 154369630 ps
CPU time 2.36 seconds
Started Mar 28 01:27:47 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 206992 kb
Host smart-aae001e1-7420-4fff-b063-5b2ee9ffd416
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847683978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3847683978
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.595109554
Short name T531
Test name
Test status
Simulation time 1585122483 ps
CPU time 36.82 seconds
Started Mar 28 01:27:42 PM PDT 24
Finished Mar 28 01:28:19 PM PDT 24
Peak memory 208728 kb
Host smart-a21c2f5c-b353-4ae5-846a-649434dac8f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595109554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.595109554
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1636482809
Short name T593
Test name
Test status
Simulation time 69775697 ps
CPU time 1.94 seconds
Started Mar 28 01:27:51 PM PDT 24
Finished Mar 28 01:27:54 PM PDT 24
Peak memory 209864 kb
Host smart-1ddca152-4f48-4cdc-a2be-7dcf810dfd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636482809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1636482809
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.4054977278
Short name T454
Test name
Test status
Simulation time 4652308505 ps
CPU time 23.67 seconds
Started Mar 28 01:27:52 PM PDT 24
Finished Mar 28 01:28:16 PM PDT 24
Peak memory 208304 kb
Host smart-0e99f48d-8d9d-4f1a-aab6-57634b0ce34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054977278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4054977278
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3980907854
Short name T355
Test name
Test status
Simulation time 92885624 ps
CPU time 4.15 seconds
Started Mar 28 01:27:48 PM PDT 24
Finished Mar 28 01:27:52 PM PDT 24
Peak memory 208724 kb
Host smart-1b6379a3-39d2-4e08-98e9-4b6477424b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980907854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3980907854
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1707168993
Short name T57
Test name
Test status
Simulation time 218088971 ps
CPU time 2.04 seconds
Started Mar 28 01:27:46 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 209816 kb
Host smart-7b0440cb-dba3-4a61-bcb6-317715d7cefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707168993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1707168993
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.4110672914
Short name T830
Test name
Test status
Simulation time 29332525 ps
CPU time 0.82 seconds
Started Mar 28 01:27:48 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 206296 kb
Host smart-72a3337c-faad-460b-bd75-ee2b259ba926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110672914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4110672914
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3364286160
Short name T418
Test name
Test status
Simulation time 1230018972 ps
CPU time 17.16 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:28:01 PM PDT 24
Peak memory 215536 kb
Host smart-f6d09604-1292-43f1-8b71-4f8ec0fbf300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364286160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3364286160
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2623419144
Short name T748
Test name
Test status
Simulation time 86358421 ps
CPU time 3.33 seconds
Started Mar 28 01:27:42 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 209248 kb
Host smart-d9856d76-482e-4aa5-83f1-40517274e6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623419144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2623419144
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.4262958644
Short name T343
Test name
Test status
Simulation time 97370722 ps
CPU time 4.2 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:27:48 PM PDT 24
Peak memory 218904 kb
Host smart-b299fbfc-9c4e-4fba-bf32-719350ea31f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262958644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.4262958644
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.992863692
Short name T468
Test name
Test status
Simulation time 60922770 ps
CPU time 2.93 seconds
Started Mar 28 01:27:44 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 222740 kb
Host smart-42bb3112-c8a7-406b-81f2-b54a27645ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992863692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.992863692
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1214908067
Short name T340
Test name
Test status
Simulation time 894668063 ps
CPU time 27 seconds
Started Mar 28 01:27:44 PM PDT 24
Finished Mar 28 01:28:11 PM PDT 24
Peak memory 214604 kb
Host smart-7d37bc59-a3bf-452c-a606-7cc53fa59baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214908067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1214908067
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1179889305
Short name T651
Test name
Test status
Simulation time 124116545 ps
CPU time 1.97 seconds
Started Mar 28 01:27:48 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 206340 kb
Host smart-0aa3913b-b0bd-4534-bdc8-e70a5b069fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179889305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1179889305
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2388173977
Short name T483
Test name
Test status
Simulation time 1117628653 ps
CPU time 4.97 seconds
Started Mar 28 01:27:42 PM PDT 24
Finished Mar 28 01:27:47 PM PDT 24
Peak memory 207252 kb
Host smart-3af7020c-ed9c-4481-967c-eeae08e064b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388173977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2388173977
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2786439552
Short name T571
Test name
Test status
Simulation time 1040021962 ps
CPU time 16.81 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:28:00 PM PDT 24
Peak memory 208756 kb
Host smart-be46c1a9-64f3-4efd-a6b2-ad1acb600a73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786439552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2786439552
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3391981804
Short name T700
Test name
Test status
Simulation time 1501133070 ps
CPU time 28.08 seconds
Started Mar 28 01:27:42 PM PDT 24
Finished Mar 28 01:28:11 PM PDT 24
Peak memory 208764 kb
Host smart-09444b9e-eb42-4d90-8900-8ee0a9d465d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391981804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3391981804
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1782158612
Short name T619
Test name
Test status
Simulation time 130687571 ps
CPU time 3.18 seconds
Started Mar 28 01:27:47 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 209792 kb
Host smart-e9c85829-793d-4d07-96b4-6680b3504c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782158612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1782158612
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2778845946
Short name T225
Test name
Test status
Simulation time 26207841 ps
CPU time 1.94 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 208628 kb
Host smart-40b89922-3d32-416a-8bf4-42898ec438e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778845946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2778845946
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1695320077
Short name T753
Test name
Test status
Simulation time 1332789515 ps
CPU time 35.39 seconds
Started Mar 28 01:27:51 PM PDT 24
Finished Mar 28 01:28:27 PM PDT 24
Peak memory 222080 kb
Host smart-1a9bdc99-e263-4be4-9048-c1fdbc8274fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695320077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1695320077
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2273184753
Short name T328
Test name
Test status
Simulation time 57830943 ps
CPU time 3.8 seconds
Started Mar 28 01:27:51 PM PDT 24
Finished Mar 28 01:27:55 PM PDT 24
Peak memory 208672 kb
Host smart-2ffa3904-7329-440c-bcee-4dad0e399696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273184753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2273184753
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3697427048
Short name T35
Test name
Test status
Simulation time 825247968 ps
CPU time 22.95 seconds
Started Mar 28 01:27:52 PM PDT 24
Finished Mar 28 01:28:15 PM PDT 24
Peak memory 211476 kb
Host smart-ce9415e1-e8ad-43aa-8a4b-49a94da26722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697427048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3697427048
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1573640323
Short name T581
Test name
Test status
Simulation time 58425649 ps
CPU time 0.82 seconds
Started Mar 28 01:27:46 PM PDT 24
Finished Mar 28 01:27:48 PM PDT 24
Peak memory 206260 kb
Host smart-1b9d9f30-3b67-4972-aa26-995eef026df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573640323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1573640323
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.239666869
Short name T282
Test name
Test status
Simulation time 98261530 ps
CPU time 3.59 seconds
Started Mar 28 01:27:48 PM PDT 24
Finished Mar 28 01:27:52 PM PDT 24
Peak memory 214628 kb
Host smart-83288d94-c9e3-4828-8447-2d724cb25805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239666869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.239666869
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1270807387
Short name T71
Test name
Test status
Simulation time 1012216355 ps
CPU time 2.96 seconds
Started Mar 28 01:27:52 PM PDT 24
Finished Mar 28 01:27:55 PM PDT 24
Peak memory 221948 kb
Host smart-2af90577-267e-4eeb-8058-8bb84ff8f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270807387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1270807387
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2125216100
Short name T785
Test name
Test status
Simulation time 4984760701 ps
CPU time 27.77 seconds
Started Mar 28 01:27:44 PM PDT 24
Finished Mar 28 01:28:15 PM PDT 24
Peak memory 210840 kb
Host smart-63be4cc3-4bd0-4b5c-8b3e-d68b4d0d48f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125216100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2125216100
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1623497468
Short name T333
Test name
Test status
Simulation time 883884978 ps
CPU time 6.53 seconds
Started Mar 28 01:27:51 PM PDT 24
Finished Mar 28 01:27:58 PM PDT 24
Peak memory 219504 kb
Host smart-6a67ff8b-f76b-45d7-b273-2c8a43d2cddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623497468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1623497468
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_random.3058597009
Short name T861
Test name
Test status
Simulation time 1539596056 ps
CPU time 23.44 seconds
Started Mar 28 01:27:46 PM PDT 24
Finished Mar 28 01:28:10 PM PDT 24
Peak memory 218584 kb
Host smart-1e7060b7-fc60-4c40-8c18-2a725db80f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058597009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3058597009
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.111499017
Short name T872
Test name
Test status
Simulation time 89203992 ps
CPU time 1.8 seconds
Started Mar 28 01:27:47 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 207084 kb
Host smart-c8a2c8f0-786e-43d9-a701-8e6e0b0ed572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111499017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.111499017
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3676166888
Short name T554
Test name
Test status
Simulation time 134975553 ps
CPU time 4.14 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:27:48 PM PDT 24
Peak memory 208900 kb
Host smart-efa561f1-a38b-478a-970b-95226064c2ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676166888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3676166888
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3398732044
Short name T199
Test name
Test status
Simulation time 1023606708 ps
CPU time 8.81 seconds
Started Mar 28 01:27:45 PM PDT 24
Finished Mar 28 01:27:56 PM PDT 24
Peak memory 209228 kb
Host smart-a31ae3f0-5c67-4f4c-b3bd-3b2163c161cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398732044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3398732044
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.284316149
Short name T743
Test name
Test status
Simulation time 117885803 ps
CPU time 3.22 seconds
Started Mar 28 01:27:48 PM PDT 24
Finished Mar 28 01:27:51 PM PDT 24
Peak memory 207136 kb
Host smart-528c29b0-4635-4cc7-8ac5-2030b211f5b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284316149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.284316149
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3701461201
Short name T535
Test name
Test status
Simulation time 315564015 ps
CPU time 4.52 seconds
Started Mar 28 01:27:44 PM PDT 24
Finished Mar 28 01:27:51 PM PDT 24
Peak memory 218732 kb
Host smart-5a518733-8b19-43b1-bb2c-62317106a453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701461201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3701461201
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2648477037
Short name T2
Test name
Test status
Simulation time 92809822 ps
CPU time 4.09 seconds
Started Mar 28 01:27:45 PM PDT 24
Finished Mar 28 01:27:51 PM PDT 24
Peak memory 208684 kb
Host smart-cf11a1b2-71b1-472f-bd64-2b7a35b9393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648477037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2648477037
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1868404919
Short name T190
Test name
Test status
Simulation time 223556808 ps
CPU time 9.35 seconds
Started Mar 28 01:27:44 PM PDT 24
Finished Mar 28 01:27:56 PM PDT 24
Peak memory 219156 kb
Host smart-0b24f170-8aff-4d3d-8460-00061b30fe56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868404919 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1868404919
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.976541678
Short name T233
Test name
Test status
Simulation time 322242054 ps
CPU time 3.85 seconds
Started Mar 28 01:27:49 PM PDT 24
Finished Mar 28 01:27:53 PM PDT 24
Peak memory 208356 kb
Host smart-17dc7862-c77b-4abe-8039-287bedd86adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976541678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.976541678
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.397172199
Short name T790
Test name
Test status
Simulation time 60332334 ps
CPU time 2.05 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:27:46 PM PDT 24
Peak memory 210612 kb
Host smart-b2716ad7-a214-439b-9b9d-34f5480f1b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397172199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.397172199
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1203252172
Short name T860
Test name
Test status
Simulation time 76689636 ps
CPU time 3.3 seconds
Started Mar 28 01:27:49 PM PDT 24
Finished Mar 28 01:27:53 PM PDT 24
Peak memory 218624 kb
Host smart-fd9e1cdf-b71e-459b-bd8c-903cd5647b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203252172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1203252172
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2502086955
Short name T24
Test name
Test status
Simulation time 523665760 ps
CPU time 4.98 seconds
Started Mar 28 01:27:44 PM PDT 24
Finished Mar 28 01:27:52 PM PDT 24
Peak memory 209536 kb
Host smart-574d4859-b105-4dea-a5f1-1c9314bba603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502086955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2502086955
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.304112671
Short name T840
Test name
Test status
Simulation time 130965354 ps
CPU time 5.52 seconds
Started Mar 28 01:27:46 PM PDT 24
Finished Mar 28 01:27:52 PM PDT 24
Peak memory 211000 kb
Host smart-18db1359-6fb4-4154-bb52-a821e6229ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304112671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.304112671
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1605599441
Short name T246
Test name
Test status
Simulation time 99274054 ps
CPU time 4.5 seconds
Started Mar 28 01:27:51 PM PDT 24
Finished Mar 28 01:27:56 PM PDT 24
Peak memory 209996 kb
Host smart-cae71735-cec2-4d3c-aa5f-5ec9439f714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605599441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1605599441
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.778148035
Short name T588
Test name
Test status
Simulation time 1188895344 ps
CPU time 27.24 seconds
Started Mar 28 01:27:51 PM PDT 24
Finished Mar 28 01:28:18 PM PDT 24
Peak memory 214608 kb
Host smart-843080ca-0e93-4416-ab5b-3493b6069142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778148035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.778148035
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2275092795
Short name T582
Test name
Test status
Simulation time 8005477050 ps
CPU time 30.65 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:28:14 PM PDT 24
Peak memory 209044 kb
Host smart-8beb8e0f-2763-41d2-b9ce-e03be020be0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275092795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2275092795
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2956879046
Short name T465
Test name
Test status
Simulation time 294615481 ps
CPU time 5.59 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 208964 kb
Host smart-2462b1a7-ecc5-43ec-83e6-ce6b9b3812b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956879046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2956879046
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.692706616
Short name T494
Test name
Test status
Simulation time 270966350 ps
CPU time 6.94 seconds
Started Mar 28 01:27:51 PM PDT 24
Finished Mar 28 01:27:58 PM PDT 24
Peak memory 209100 kb
Host smart-92ff2c99-d986-4174-aa35-fea89f19670a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692706616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.692706616
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1547819459
Short name T865
Test name
Test status
Simulation time 88772755 ps
CPU time 4.09 seconds
Started Mar 28 01:27:45 PM PDT 24
Finished Mar 28 01:27:51 PM PDT 24
Peak memory 209168 kb
Host smart-42636d09-8940-43f5-a0f2-c9088359711f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547819459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1547819459
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.712587260
Short name T335
Test name
Test status
Simulation time 1662825887 ps
CPU time 45.46 seconds
Started Mar 28 01:27:46 PM PDT 24
Finished Mar 28 01:28:32 PM PDT 24
Peak memory 220136 kb
Host smart-9585a992-499e-4408-b31b-1a10c2773766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712587260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.712587260
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3913704754
Short name T823
Test name
Test status
Simulation time 201324999 ps
CPU time 2.82 seconds
Started Mar 28 01:27:46 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 206836 kb
Host smart-dea6bf19-14a5-464c-9022-f6539fbf7dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913704754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3913704754
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1394688662
Short name T336
Test name
Test status
Simulation time 730924215 ps
CPU time 13.53 seconds
Started Mar 28 01:27:47 PM PDT 24
Finished Mar 28 01:28:00 PM PDT 24
Peak memory 222956 kb
Host smart-d80ef2fc-712d-4b96-9b26-a6b804a25f21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394688662 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1394688662
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2989632377
Short name T386
Test name
Test status
Simulation time 230869734 ps
CPU time 5.82 seconds
Started Mar 28 01:27:43 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 211228 kb
Host smart-7df27248-f58e-4995-91c7-329d424431d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989632377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2989632377
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1428522722
Short name T464
Test name
Test status
Simulation time 18483507 ps
CPU time 0.87 seconds
Started Mar 28 01:28:16 PM PDT 24
Finished Mar 28 01:28:17 PM PDT 24
Peak memory 206196 kb
Host smart-3e7d814c-cd38-4994-b7c8-e870e199bf22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428522722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1428522722
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2650075266
Short name T21
Test name
Test status
Simulation time 115238107 ps
CPU time 4.14 seconds
Started Mar 28 01:28:16 PM PDT 24
Finished Mar 28 01:28:20 PM PDT 24
Peak memory 209612 kb
Host smart-1e66684e-4f7d-497e-8a47-2db7d71e711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650075266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2650075266
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.50553021
Short name T703
Test name
Test status
Simulation time 67005164 ps
CPU time 3.03 seconds
Started Mar 28 01:28:16 PM PDT 24
Finished Mar 28 01:28:19 PM PDT 24
Peak memory 208156 kb
Host smart-ad3472d0-607e-47e5-8d4d-fc99b42c16ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50553021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.50553021
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.951733146
Short name T401
Test name
Test status
Simulation time 241209437 ps
CPU time 3 seconds
Started Mar 28 01:28:16 PM PDT 24
Finished Mar 28 01:28:19 PM PDT 24
Peak memory 208320 kb
Host smart-e0fa033b-034d-44c4-8236-0380d9210599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951733146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.951733146
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.646598012
Short name T590
Test name
Test status
Simulation time 90108221 ps
CPU time 3.72 seconds
Started Mar 28 01:28:16 PM PDT 24
Finished Mar 28 01:28:20 PM PDT 24
Peak memory 214688 kb
Host smart-e5824599-db52-470d-9214-b4101fbd11b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646598012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.646598012
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1339122261
Short name T325
Test name
Test status
Simulation time 698587092 ps
CPU time 24.42 seconds
Started Mar 28 01:28:16 PM PDT 24
Finished Mar 28 01:28:40 PM PDT 24
Peak memory 214604 kb
Host smart-5fa23000-254f-4021-942a-49bbcd2653ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339122261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1339122261
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.378064200
Short name T306
Test name
Test status
Simulation time 67320334 ps
CPU time 2.59 seconds
Started Mar 28 01:27:45 PM PDT 24
Finished Mar 28 01:27:49 PM PDT 24
Peak memory 208932 kb
Host smart-f6e43e03-3141-4fa9-b4b0-cac487856dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378064200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.378064200
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2348318414
Short name T871
Test name
Test status
Simulation time 53724204 ps
CPU time 2.99 seconds
Started Mar 28 01:27:46 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 207340 kb
Host smart-672e6765-861b-43df-b9d4-dc34f17d53b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348318414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2348318414
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1174581919
Short name T776
Test name
Test status
Simulation time 1035795292 ps
CPU time 14.88 seconds
Started Mar 28 01:27:48 PM PDT 24
Finished Mar 28 01:28:03 PM PDT 24
Peak memory 208352 kb
Host smart-cf827429-4244-4af0-b906-199b116b6a86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174581919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1174581919
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3886313186
Short name T716
Test name
Test status
Simulation time 168205470 ps
CPU time 4.76 seconds
Started Mar 28 01:28:14 PM PDT 24
Finished Mar 28 01:28:19 PM PDT 24
Peak memory 208536 kb
Host smart-79c13f71-c837-4a7e-8d50-60574e73ab2d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886313186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3886313186
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.145245263
Short name T898
Test name
Test status
Simulation time 262245924 ps
CPU time 2.8 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:22 PM PDT 24
Peak memory 210168 kb
Host smart-f1656bac-3e33-4e1d-8c9b-cdde471c0bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145245263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.145245263
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1117106221
Short name T897
Test name
Test status
Simulation time 184268111 ps
CPU time 3.26 seconds
Started Mar 28 01:27:47 PM PDT 24
Finished Mar 28 01:27:50 PM PDT 24
Peak memory 208852 kb
Host smart-53fda2ae-dac7-4f83-8e6c-c5f5959c1885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117106221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1117106221
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1252036313
Short name T322
Test name
Test status
Simulation time 18370714624 ps
CPU time 126.57 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:30:25 PM PDT 24
Peak memory 218032 kb
Host smart-b1f17134-b973-4701-981b-1b999b0b568d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252036313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1252036313
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1513094077
Short name T735
Test name
Test status
Simulation time 252080823 ps
CPU time 11.59 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:30 PM PDT 24
Peak memory 220144 kb
Host smart-1a23ffa6-f8b0-42c1-859a-b29044fe6ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513094077 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1513094077
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1979888641
Short name T259
Test name
Test status
Simulation time 11150573138 ps
CPU time 92.97 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:29:51 PM PDT 24
Peak memory 209440 kb
Host smart-f24f1149-ed4b-4750-8d2d-061e2b4072db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979888641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1979888641
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2252750333
Short name T183
Test name
Test status
Simulation time 60287806 ps
CPU time 1.89 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:20 PM PDT 24
Peak memory 208788 kb
Host smart-5952bd8e-5d6d-4ea8-80ae-6c3448ce6403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252750333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2252750333
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1822383583
Short name T648
Test name
Test status
Simulation time 19902257 ps
CPU time 0.94 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:28:22 PM PDT 24
Peak memory 206492 kb
Host smart-738d9c92-ca5a-4bb7-b913-ad2f81bc7f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822383583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1822383583
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.350598579
Short name T194
Test name
Test status
Simulation time 480924977 ps
CPU time 4.2 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:28:25 PM PDT 24
Peak memory 214868 kb
Host smart-e0ff35b8-361b-4e35-86ef-ed4203a431d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350598579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.350598579
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3602876895
Short name T491
Test name
Test status
Simulation time 46149251 ps
CPU time 2.65 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:22 PM PDT 24
Peak memory 209388 kb
Host smart-ffb80ea3-e7e5-4b20-8f0c-520f64006fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602876895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3602876895
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.85317100
Short name T368
Test name
Test status
Simulation time 1457347023 ps
CPU time 11.29 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:30 PM PDT 24
Peak memory 209836 kb
Host smart-84fc23af-f5da-4f4d-bf2e-e77b565d99ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85317100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.85317100
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.416707250
Short name T54
Test name
Test status
Simulation time 107997921 ps
CPU time 3.94 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 210816 kb
Host smart-20d0e417-bc8d-4b4f-bfca-e78d1ada5f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416707250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.416707250
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1891508930
Short name T668
Test name
Test status
Simulation time 39553712 ps
CPU time 3.01 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 214756 kb
Host smart-f6ad3d9e-d9b6-4673-a7a0-9b338d610085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891508930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1891508930
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2200228085
Short name T614
Test name
Test status
Simulation time 474258950 ps
CPU time 4.37 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 214600 kb
Host smart-84d27ddc-3b5f-48df-8a7b-ec39d01ce83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200228085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2200228085
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.702410370
Short name T405
Test name
Test status
Simulation time 401088640 ps
CPU time 4.02 seconds
Started Mar 28 01:28:16 PM PDT 24
Finished Mar 28 01:28:20 PM PDT 24
Peak memory 209144 kb
Host smart-c13dc6eb-465c-4530-9418-1946b2b4068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702410370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.702410370
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.4018387206
Short name T799
Test name
Test status
Simulation time 42530320 ps
CPU time 2.68 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:22 PM PDT 24
Peak memory 208608 kb
Host smart-084d4152-7454-4776-91e5-6036ad138d52
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018387206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.4018387206
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.237965694
Short name T589
Test name
Test status
Simulation time 411083088 ps
CPU time 3.54 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:22 PM PDT 24
Peak memory 207108 kb
Host smart-9d51a715-4458-446f-a51e-bd1920b26ce2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237965694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.237965694
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3951400871
Short name T104
Test name
Test status
Simulation time 269641410 ps
CPU time 2.99 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:28:24 PM PDT 24
Peak memory 209792 kb
Host smart-24f13612-a6a0-4ba2-ad73-0316ed2bc15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951400871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3951400871
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.872766983
Short name T807
Test name
Test status
Simulation time 1071626410 ps
CPU time 3.46 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:22 PM PDT 24
Peak memory 207056 kb
Host smart-8ca5693c-44b0-4911-9a69-8366cc2a08d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872766983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.872766983
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1730664076
Short name T143
Test name
Test status
Simulation time 92972060 ps
CPU time 5.29 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:24 PM PDT 24
Peak memory 214716 kb
Host smart-7784543e-3874-45d9-96ed-6b023a1e64d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730664076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1730664076
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.474104273
Short name T184
Test name
Test status
Simulation time 243650740 ps
CPU time 4.62 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 210532 kb
Host smart-f1f800d7-e83e-495f-981e-97a4be1e9b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474104273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.474104273
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.54465721
Short name T562
Test name
Test status
Simulation time 17989909 ps
CPU time 0.75 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 206244 kb
Host smart-e25e9a7f-2830-4469-aefe-c4403ce13f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54465721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.54465721
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2675757121
Short name T149
Test name
Test status
Simulation time 41131368 ps
CPU time 3.16 seconds
Started Mar 28 01:28:24 PM PDT 24
Finished Mar 28 01:28:27 PM PDT 24
Peak memory 215420 kb
Host smart-0e5a2184-eb1b-4cea-8790-ac75fdb0eaee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675757121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2675757121
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.785977458
Short name T50
Test name
Test status
Simulation time 64358631 ps
CPU time 2.71 seconds
Started Mar 28 01:28:25 PM PDT 24
Finished Mar 28 01:28:27 PM PDT 24
Peak memory 208280 kb
Host smart-835cd6d6-3a81-4d2d-aec0-c802bdd33642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785977458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.785977458
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3791524370
Short name T207
Test name
Test status
Simulation time 1054032180 ps
CPU time 10.55 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:28:32 PM PDT 24
Peak memory 209256 kb
Host smart-66c50f1a-1032-4b4a-8df9-50a08dc6ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791524370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3791524370
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3447138310
Short name T265
Test name
Test status
Simulation time 1383578576 ps
CPU time 8.93 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:31 PM PDT 24
Peak memory 222824 kb
Host smart-70c440cd-8de9-44fa-93d6-3fd091ee20f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447138310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3447138310
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.597523037
Short name T691
Test name
Test status
Simulation time 294350511 ps
CPU time 3.26 seconds
Started Mar 28 01:28:25 PM PDT 24
Finished Mar 28 01:28:28 PM PDT 24
Peak memory 220512 kb
Host smart-6c62f81d-2f0a-436e-a986-f2c08e1b0190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597523037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.597523037
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.69454613
Short name T556
Test name
Test status
Simulation time 2412709889 ps
CPU time 17.1 seconds
Started Mar 28 01:28:25 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 209536 kb
Host smart-cb5b16b1-c6df-4159-b121-d2a970411cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69454613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.69454613
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.819910834
Short name T4
Test name
Test status
Simulation time 523248673 ps
CPU time 4.52 seconds
Started Mar 28 01:28:23 PM PDT 24
Finished Mar 28 01:28:28 PM PDT 24
Peak memory 206780 kb
Host smart-4e6daba8-bbb4-4818-847c-e60eccdf7ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819910834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.819910834
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3359787594
Short name T563
Test name
Test status
Simulation time 48259742 ps
CPU time 2.63 seconds
Started Mar 28 01:28:24 PM PDT 24
Finished Mar 28 01:28:27 PM PDT 24
Peak memory 207260 kb
Host smart-bdd2e2f0-a1cd-4eec-9968-a5a6ef74514c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359787594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3359787594
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.515079475
Short name T625
Test name
Test status
Simulation time 82352508 ps
CPU time 2.49 seconds
Started Mar 28 01:28:23 PM PDT 24
Finished Mar 28 01:28:25 PM PDT 24
Peak memory 207100 kb
Host smart-e62489b5-1019-41a1-93dc-eda484fc118e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515079475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.515079475
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2427091123
Short name T784
Test name
Test status
Simulation time 19422024 ps
CPU time 1.81 seconds
Started Mar 28 01:28:23 PM PDT 24
Finished Mar 28 01:28:25 PM PDT 24
Peak memory 206976 kb
Host smart-d6366fb9-84d8-4504-bc43-0374c42dc5f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427091123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2427091123
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3459890292
Short name T592
Test name
Test status
Simulation time 26702393 ps
CPU time 1.83 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:24 PM PDT 24
Peak memory 207876 kb
Host smart-b5dde1ec-be1a-492f-86b8-b669f92c7f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459890292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3459890292
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.4275085045
Short name T472
Test name
Test status
Simulation time 478840236 ps
CPU time 3.53 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:24 PM PDT 24
Peak memory 206872 kb
Host smart-af13cf8c-b2c6-4ed2-aa9d-cfe706554196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275085045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.4275085045
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1984547232
Short name T128
Test name
Test status
Simulation time 648400483 ps
CPU time 18.36 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 220576 kb
Host smart-353294dc-0156-43d4-88ee-dd55b93a06f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984547232 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1984547232
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2180068770
Short name T267
Test name
Test status
Simulation time 2524367104 ps
CPU time 52.35 seconds
Started Mar 28 01:28:25 PM PDT 24
Finished Mar 28 01:29:17 PM PDT 24
Peak memory 214876 kb
Host smart-d8da91b4-d2f1-40ed-99b3-6c7c4b97b88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180068770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2180068770
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2047884470
Short name T866
Test name
Test status
Simulation time 30681859 ps
CPU time 1.68 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 210532 kb
Host smart-b62aa049-c11e-47e7-83a1-9731e90524ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047884470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2047884470
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2765793678
Short name T135
Test name
Test status
Simulation time 26765642 ps
CPU time 0.79 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:06 PM PDT 24
Peak memory 206320 kb
Host smart-7e6b989a-6873-4ad9-923e-5f9848969f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765793678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2765793678
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1819361646
Short name T509
Test name
Test status
Simulation time 212395862 ps
CPU time 2.53 seconds
Started Mar 28 01:27:09 PM PDT 24
Finished Mar 28 01:27:12 PM PDT 24
Peak memory 207128 kb
Host smart-c73d1961-43b5-48ee-b67c-11980391bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819361646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1819361646
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.745998377
Short name T728
Test name
Test status
Simulation time 318793666 ps
CPU time 5.01 seconds
Started Mar 28 01:27:09 PM PDT 24
Finished Mar 28 01:27:14 PM PDT 24
Peak memory 221152 kb
Host smart-8afd2e78-8079-406a-8b6b-3200f00e9474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745998377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.745998377
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.4057377016
Short name T329
Test name
Test status
Simulation time 519932260 ps
CPU time 11.89 seconds
Started Mar 28 01:27:04 PM PDT 24
Finished Mar 28 01:27:17 PM PDT 24
Peak memory 214632 kb
Host smart-cdd85f22-471e-41af-b991-5eda170c95bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057377016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.4057377016
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2359259041
Short name T243
Test name
Test status
Simulation time 171205184 ps
CPU time 4.68 seconds
Started Mar 28 01:27:09 PM PDT 24
Finished Mar 28 01:27:14 PM PDT 24
Peak memory 210216 kb
Host smart-f363c294-86d3-449c-b9c9-8d238c659a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359259041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2359259041
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1565293117
Short name T133
Test name
Test status
Simulation time 5087538240 ps
CPU time 44.75 seconds
Started Mar 28 01:27:07 PM PDT 24
Finished Mar 28 01:27:52 PM PDT 24
Peak memory 214884 kb
Host smart-40827b88-2a48-4011-8bd2-20bcb948dd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565293117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1565293117
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.505532810
Short name T44
Test name
Test status
Simulation time 32792347098 ps
CPU time 335.74 seconds
Started Mar 28 01:27:07 PM PDT 24
Finished Mar 28 01:32:43 PM PDT 24
Peak memory 302196 kb
Host smart-244e6936-4bc5-425d-959f-9571cb14b1fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505532810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.505532810
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2389472208
Short name T635
Test name
Test status
Simulation time 188746469 ps
CPU time 6.93 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:14 PM PDT 24
Peak memory 209016 kb
Host smart-8f5e62ef-5b22-4d35-83bb-788bdef32062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389472208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2389472208
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3894141452
Short name T669
Test name
Test status
Simulation time 1937301598 ps
CPU time 14.43 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:20 PM PDT 24
Peak memory 209132 kb
Host smart-643d8b8b-18d9-44e6-841a-4f73058fa192
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894141452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3894141452
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4132794728
Short name T84
Test name
Test status
Simulation time 134985357 ps
CPU time 3.55 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:09 PM PDT 24
Peak memory 208208 kb
Host smart-3a262e72-4ece-4bfd-a259-dc0ba6527208
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132794728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4132794728
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1590735350
Short name T146
Test name
Test status
Simulation time 217505728 ps
CPU time 7.96 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:13 PM PDT 24
Peak memory 208980 kb
Host smart-2b1d5e19-6ac2-4877-bf74-d1d4e01c7842
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590735350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1590735350
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.96974846
Short name T705
Test name
Test status
Simulation time 597347477 ps
CPU time 4.78 seconds
Started Mar 28 01:27:03 PM PDT 24
Finished Mar 28 01:27:08 PM PDT 24
Peak memory 209076 kb
Host smart-4c36388b-5d10-4759-ae43-d6aaba5ac28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96974846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.96974846
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3452998705
Short name T782
Test name
Test status
Simulation time 119429181 ps
CPU time 2.95 seconds
Started Mar 28 01:27:02 PM PDT 24
Finished Mar 28 01:27:05 PM PDT 24
Peak memory 209008 kb
Host smart-f977c300-190a-499c-8676-4175e4a65bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452998705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3452998705
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.23986934
Short name T379
Test name
Test status
Simulation time 14955203631 ps
CPU time 444.95 seconds
Started Mar 28 01:27:04 PM PDT 24
Finished Mar 28 01:34:30 PM PDT 24
Peak memory 224664 kb
Host smart-06b20610-b51a-4266-b952-b3286e75cdd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23986934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.23986934
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1022251531
Short name T187
Test name
Test status
Simulation time 1225494150 ps
CPU time 12.56 seconds
Started Mar 28 01:27:03 PM PDT 24
Finished Mar 28 01:27:16 PM PDT 24
Peak memory 223016 kb
Host smart-a33fe428-b045-414b-b94e-01cccb1c66aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022251531 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1022251531
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.758817211
Short name T359
Test name
Test status
Simulation time 512672205 ps
CPU time 12.1 seconds
Started Mar 28 01:27:04 PM PDT 24
Finished Mar 28 01:27:17 PM PDT 24
Peak memory 218756 kb
Host smart-4e1070a4-e21a-44b2-9854-877d438ccaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758817211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.758817211
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.306833019
Short name T587
Test name
Test status
Simulation time 76626053 ps
CPU time 1.89 seconds
Started Mar 28 01:27:03 PM PDT 24
Finished Mar 28 01:27:05 PM PDT 24
Peak memory 210532 kb
Host smart-050b0e87-5246-45eb-92da-7867d4857f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306833019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.306833019
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.684504592
Short name T842
Test name
Test status
Simulation time 45299616 ps
CPU time 0.74 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 206212 kb
Host smart-ca2583e8-530b-478b-bf59-f6cf923dccf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684504592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.684504592
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3221948539
Short name T105
Test name
Test status
Simulation time 86627930 ps
CPU time 3.46 seconds
Started Mar 28 01:28:17 PM PDT 24
Finished Mar 28 01:28:20 PM PDT 24
Peak memory 215552 kb
Host smart-fbea5753-79eb-45bc-bf27-0870df7b645f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221948539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3221948539
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1112224066
Short name T10
Test name
Test status
Simulation time 43843802 ps
CPU time 2.05 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:21 PM PDT 24
Peak memory 216380 kb
Host smart-0ae10b3e-2360-4160-9487-dc86a2d4587c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112224066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1112224066
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2604396339
Short name T638
Test name
Test status
Simulation time 5089608010 ps
CPU time 29.09 seconds
Started Mar 28 01:28:16 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 209320 kb
Host smart-4045cae0-db90-4b56-a2de-c00756a4e72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604396339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2604396339
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1549679924
Short name T756
Test name
Test status
Simulation time 306818452 ps
CPU time 5.36 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:28:27 PM PDT 24
Peak memory 209968 kb
Host smart-de26dc07-1429-4509-8afe-6ed08a65427f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549679924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1549679924
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1508860167
Short name T770
Test name
Test status
Simulation time 330957322 ps
CPU time 4.65 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 210808 kb
Host smart-25506fed-62c0-4a03-8035-b7f6bbc5f0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508860167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1508860167
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1308300731
Short name T802
Test name
Test status
Simulation time 148525954 ps
CPU time 4.74 seconds
Started Mar 28 01:28:15 PM PDT 24
Finished Mar 28 01:28:20 PM PDT 24
Peak memory 216036 kb
Host smart-2f7d8ccb-ed7a-4565-a851-b79f0cab35bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308300731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1308300731
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1795945074
Short name T665
Test name
Test status
Simulation time 6379443224 ps
CPU time 51.26 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:29:12 PM PDT 24
Peak memory 220476 kb
Host smart-9df7c33c-5124-4256-b11d-5fa824ab3dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795945074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1795945074
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3505387356
Short name T663
Test name
Test status
Simulation time 54475459 ps
CPU time 3.01 seconds
Started Mar 28 01:28:15 PM PDT 24
Finished Mar 28 01:28:19 PM PDT 24
Peak memory 207004 kb
Host smart-8b324980-255a-4657-b309-e96d733ba315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505387356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3505387356
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.496932294
Short name T460
Test name
Test status
Simulation time 34264808 ps
CPU time 2.37 seconds
Started Mar 28 01:28:16 PM PDT 24
Finished Mar 28 01:28:19 PM PDT 24
Peak memory 207040 kb
Host smart-89c18305-0d33-49f7-8e94-bef0e173ccbb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496932294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.496932294
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2130062773
Short name T720
Test name
Test status
Simulation time 131254244 ps
CPU time 2.63 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:21 PM PDT 24
Peak memory 207364 kb
Host smart-f5660030-7010-481b-b219-add714f5e7c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130062773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2130062773
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3472965244
Short name T210
Test name
Test status
Simulation time 250602998 ps
CPU time 2.7 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:21 PM PDT 24
Peak memory 207300 kb
Host smart-4d18a1c6-83c8-4314-aa20-45fa62e49050
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472965244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3472965244
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.853679537
Short name T717
Test name
Test status
Simulation time 35822245 ps
CPU time 2.19 seconds
Started Mar 28 01:28:17 PM PDT 24
Finished Mar 28 01:28:20 PM PDT 24
Peak memory 209476 kb
Host smart-1a4d4be2-c576-4ab1-bb53-3881bccfcab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853679537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.853679537
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1015849260
Short name T643
Test name
Test status
Simulation time 717059314 ps
CPU time 5.97 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:28:27 PM PDT 24
Peak memory 208172 kb
Host smart-d9e1b0c2-f8b8-4de2-890a-66a4dcc1686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015849260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1015849260
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.281398732
Short name T124
Test name
Test status
Simulation time 497885345 ps
CPU time 8.94 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:28 PM PDT 24
Peak memory 223056 kb
Host smart-3d632531-e5ab-406c-a3f9-12c677e2d0a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281398732 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.281398732
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1720578748
Short name T473
Test name
Test status
Simulation time 128886325 ps
CPU time 2.54 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:21 PM PDT 24
Peak memory 207664 kb
Host smart-90eb68e0-46e9-44ba-b470-09578d32b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720578748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1720578748
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2402033604
Short name T215
Test name
Test status
Simulation time 1121449706 ps
CPU time 2.59 seconds
Started Mar 28 01:28:17 PM PDT 24
Finished Mar 28 01:28:20 PM PDT 24
Peak memory 210088 kb
Host smart-4da2ee74-593d-4050-bc1e-09206a775f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402033604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2402033604
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2075153379
Short name T500
Test name
Test status
Simulation time 12604423 ps
CPU time 0.78 seconds
Started Mar 28 01:28:25 PM PDT 24
Finished Mar 28 01:28:26 PM PDT 24
Peak memory 206352 kb
Host smart-17601d3e-3b15-4988-9455-caf95fbc2459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075153379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2075153379
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3194333781
Short name T419
Test name
Test status
Simulation time 339511702 ps
CPU time 5.69 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:25 PM PDT 24
Peak memory 215148 kb
Host smart-4bed4b74-d9a5-45dc-b93d-64fc6c39ffe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194333781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3194333781
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3221265274
Short name T72
Test name
Test status
Simulation time 634633960 ps
CPU time 18.33 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:39 PM PDT 24
Peak memory 223200 kb
Host smart-89deb5f1-5163-4a98-b918-cdba060086f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221265274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3221265274
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1279597291
Short name T558
Test name
Test status
Simulation time 42657412 ps
CPU time 2.62 seconds
Started Mar 28 01:28:21 PM PDT 24
Finished Mar 28 01:28:24 PM PDT 24
Peak memory 210408 kb
Host smart-43b7cc0a-ae91-405e-9f8d-4cfb73406af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279597291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1279597291
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.4081190915
Short name T734
Test name
Test status
Simulation time 159320113 ps
CPU time 3.76 seconds
Started Mar 28 01:28:23 PM PDT 24
Finished Mar 28 01:28:27 PM PDT 24
Peak memory 209124 kb
Host smart-193bc4eb-8298-4ea7-a0d3-00aab6f312b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081190915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.4081190915
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1510144620
Short name T744
Test name
Test status
Simulation time 70147376 ps
CPU time 3.67 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:25 PM PDT 24
Peak memory 211032 kb
Host smart-8eaabe39-42a0-44e3-a587-f881e0aaeef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510144620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1510144620
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.4248444586
Short name T481
Test name
Test status
Simulation time 544308599 ps
CPU time 3.73 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:25 PM PDT 24
Peak memory 222864 kb
Host smart-eba5e155-f961-4f6b-8f58-dd754534425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248444586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4248444586
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1554913281
Short name T205
Test name
Test status
Simulation time 1312194570 ps
CPU time 9.23 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:29 PM PDT 24
Peak memory 208660 kb
Host smart-8a1e02b5-ff59-46fa-acc3-bb7a3147c3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554913281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1554913281
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1959682049
Short name T365
Test name
Test status
Simulation time 7444729664 ps
CPU time 10.13 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:32 PM PDT 24
Peak memory 209128 kb
Host smart-c1cd06b9-5c5d-418b-88dc-2f77307748a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959682049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1959682049
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.760621812
Short name T624
Test name
Test status
Simulation time 32506414 ps
CPU time 2.47 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:22 PM PDT 24
Peak memory 207116 kb
Host smart-91dc684a-98c4-4d88-8d6f-6b70759fe137
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760621812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.760621812
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.734769305
Short name T132
Test name
Test status
Simulation time 403975119 ps
CPU time 8.98 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:31 PM PDT 24
Peak memory 209064 kb
Host smart-b23100b8-b47e-4010-9661-ef257680071c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734769305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.734769305
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1611608187
Short name T403
Test name
Test status
Simulation time 171375237 ps
CPU time 7.16 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:28 PM PDT 24
Peak memory 209376 kb
Host smart-d7109981-762c-47e1-8472-5ebc7fce1ebf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611608187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1611608187
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3263520470
Short name T724
Test name
Test status
Simulation time 82797778 ps
CPU time 3.93 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:26 PM PDT 24
Peak memory 214344 kb
Host smart-aa6efdab-7b89-4c4c-b97e-526cf8bd39fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263520470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3263520470
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1314344397
Short name T441
Test name
Test status
Simulation time 209103967 ps
CPU time 2.95 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 207180 kb
Host smart-0faeec5f-d964-4cf5-8993-a73192ab28ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314344397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1314344397
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3536745805
Short name T838
Test name
Test status
Simulation time 513682102 ps
CPU time 18.34 seconds
Started Mar 28 01:28:18 PM PDT 24
Finished Mar 28 01:28:37 PM PDT 24
Peak memory 214672 kb
Host smart-4ed113de-68db-4677-babf-dbb46b7052ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536745805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3536745805
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2153940499
Short name T634
Test name
Test status
Simulation time 495444119 ps
CPU time 4.88 seconds
Started Mar 28 01:28:25 PM PDT 24
Finished Mar 28 01:28:30 PM PDT 24
Peak memory 210648 kb
Host smart-a2c1b99d-62f0-420b-a5ee-ef3cfa640e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153940499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2153940499
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1401987564
Short name T446
Test name
Test status
Simulation time 14895962 ps
CPU time 0.75 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:37 PM PDT 24
Peak memory 206236 kb
Host smart-64bcc22a-7148-4c0e-b8d6-6d6de06488f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401987564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1401987564
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1815430772
Short name T150
Test name
Test status
Simulation time 131051655 ps
CPU time 2.7 seconds
Started Mar 28 01:28:24 PM PDT 24
Finished Mar 28 01:28:27 PM PDT 24
Peak memory 215052 kb
Host smart-4ec041b2-e81c-4746-80c7-ef47d81cc923
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815430772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1815430772
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.4233484063
Short name T874
Test name
Test status
Simulation time 60324318 ps
CPU time 1.46 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:39 PM PDT 24
Peak memory 209888 kb
Host smart-a8becb4b-8e90-4702-abaa-13ff833f9b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233484063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4233484063
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1090527632
Short name T825
Test name
Test status
Simulation time 105313284 ps
CPU time 3.63 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 208988 kb
Host smart-d87d9ecb-9015-4a54-908f-3b7f09570c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090527632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1090527632
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1857319463
Short name T552
Test name
Test status
Simulation time 203171941 ps
CPU time 3.85 seconds
Started Mar 28 01:28:24 PM PDT 24
Finished Mar 28 01:28:28 PM PDT 24
Peak memory 209884 kb
Host smart-8c6b563e-ed73-421e-8fe8-5f8b5695b765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857319463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1857319463
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1974448710
Short name T231
Test name
Test status
Simulation time 3091717261 ps
CPU time 32.97 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 222916 kb
Host smart-c27c9cff-7dd8-4102-8afd-f69e1757e009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974448710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1974448710
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3558848828
Short name T245
Test name
Test status
Simulation time 1001644891 ps
CPU time 4.17 seconds
Started Mar 28 01:28:24 PM PDT 24
Finished Mar 28 01:28:29 PM PDT 24
Peak memory 209056 kb
Host smart-b34b88ee-0ddc-4101-95ed-9f599e45b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558848828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3558848828
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2862976778
Short name T766
Test name
Test status
Simulation time 312358189 ps
CPU time 4.52 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:24 PM PDT 24
Peak memory 209800 kb
Host smart-29daac22-7c95-4b3f-a67a-e4f5790edd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862976778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2862976778
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.164102947
Short name T487
Test name
Test status
Simulation time 912959485 ps
CPU time 10.04 seconds
Started Mar 28 01:28:24 PM PDT 24
Finished Mar 28 01:28:35 PM PDT 24
Peak memory 208932 kb
Host smart-c7026850-f7c5-4dcf-b5e4-fb6d31c002b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164102947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.164102947
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1142478835
Short name T706
Test name
Test status
Simulation time 15434741076 ps
CPU time 98.9 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:29:59 PM PDT 24
Peak memory 207744 kb
Host smart-ddfefa61-e60d-46a4-b1fd-883831860470
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142478835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1142478835
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.4128738901
Short name T145
Test name
Test status
Simulation time 116782641 ps
CPU time 3 seconds
Started Mar 28 01:28:22 PM PDT 24
Finished Mar 28 01:28:25 PM PDT 24
Peak memory 207188 kb
Host smart-0b39c7aa-bf48-40b0-b26a-07638ba22e29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128738901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.4128738901
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.4064324801
Short name T304
Test name
Test status
Simulation time 95113976 ps
CPU time 3.65 seconds
Started Mar 28 01:28:19 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 207128 kb
Host smart-ab68710d-c790-41b2-970b-ca876c81daa8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064324801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4064324801
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3760175877
Short name T739
Test name
Test status
Simulation time 24371022 ps
CPU time 2.09 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 207912 kb
Host smart-c3252f3c-69bb-49a5-ab56-31d008857c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760175877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3760175877
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3116334005
Short name T750
Test name
Test status
Simulation time 206591386 ps
CPU time 2.72 seconds
Started Mar 28 01:28:20 PM PDT 24
Finished Mar 28 01:28:23 PM PDT 24
Peak memory 207144 kb
Host smart-3635ae15-4641-4820-a391-9c02b4400d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116334005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3116334005
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.125991883
Short name T732
Test name
Test status
Simulation time 1283085483 ps
CPU time 21.01 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:29:03 PM PDT 24
Peak memory 216660 kb
Host smart-6315b2e7-9c34-4aaa-9e43-46764b883939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125991883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.125991883
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3965881786
Short name T101
Test name
Test status
Simulation time 940608577 ps
CPU time 7.59 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:50 PM PDT 24
Peak memory 222996 kb
Host smart-8a923ffc-bc34-4a23-ad4a-a5d62d25540d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965881786 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3965881786
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2195917313
Short name T657
Test name
Test status
Simulation time 242409843 ps
CPU time 6.07 seconds
Started Mar 28 01:28:24 PM PDT 24
Finished Mar 28 01:28:31 PM PDT 24
Peak memory 208668 kb
Host smart-74501eee-c05f-4a3a-913f-829d6739bac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195917313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2195917313
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3234031473
Short name T681
Test name
Test status
Simulation time 3836878716 ps
CPU time 33.21 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:29:10 PM PDT 24
Peak memory 211380 kb
Host smart-7de1b731-f02f-42eb-89a4-39b5bd311575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234031473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3234031473
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2881569981
Short name T97
Test name
Test status
Simulation time 45533576 ps
CPU time 0.74 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:38 PM PDT 24
Peak memory 206284 kb
Host smart-0fdc47ea-eb32-4484-a851-3d878255e010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881569981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2881569981
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1858219149
Short name T147
Test name
Test status
Simulation time 382127908 ps
CPU time 11.31 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:50 PM PDT 24
Peak memory 215996 kb
Host smart-f1875ecc-3dba-4e4a-a7f1-f12e1278978e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858219149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1858219149
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1989326493
Short name T827
Test name
Test status
Simulation time 142661598 ps
CPU time 5.16 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:43 PM PDT 24
Peak memory 210408 kb
Host smart-78c6f49a-6ab8-48cc-a55d-5c9593f81275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989326493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1989326493
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1456640351
Short name T510
Test name
Test status
Simulation time 23254778 ps
CPU time 1.86 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 218696 kb
Host smart-186f3a53-a90d-4b06-bc28-b1effdf9d3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456640351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1456640351
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.867320221
Short name T597
Test name
Test status
Simulation time 690783146 ps
CPU time 7.41 seconds
Started Mar 28 01:28:34 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 214672 kb
Host smart-79ac0684-ddaa-4585-be9d-f28b1481e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867320221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.867320221
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1919563169
Short name T221
Test name
Test status
Simulation time 177773252 ps
CPU time 4.6 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 222752 kb
Host smart-00035634-3e86-4b66-bda5-d636d2b80271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919563169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1919563169
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4203687143
Short name T855
Test name
Test status
Simulation time 51536805 ps
CPU time 3.66 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 222856 kb
Host smart-a2753c8c-0630-496a-a043-808a7442c684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203687143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4203687143
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.384352165
Short name T698
Test name
Test status
Simulation time 186733285 ps
CPU time 4.75 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 215404 kb
Host smart-0101e131-8785-45f5-8411-6679c4a41459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384352165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.384352165
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.4181701124
Short name T275
Test name
Test status
Simulation time 42204089 ps
CPU time 1.81 seconds
Started Mar 28 01:28:35 PM PDT 24
Finished Mar 28 01:28:37 PM PDT 24
Peak memory 207172 kb
Host smart-f6f8d28f-8d3d-4304-89b5-2a4d31b80aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181701124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.4181701124
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.4085613111
Short name T600
Test name
Test status
Simulation time 266268774 ps
CPU time 3.44 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:39 PM PDT 24
Peak memory 207612 kb
Host smart-117569e0-bda6-45ce-baa6-33279409e54f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085613111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.4085613111
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3477902779
Short name T408
Test name
Test status
Simulation time 81560273 ps
CPU time 2.47 seconds
Started Mar 28 01:28:41 PM PDT 24
Finished Mar 28 01:28:43 PM PDT 24
Peak memory 207652 kb
Host smart-8bdfe32d-3ccb-4fee-b599-64587fef130f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477902779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3477902779
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1669977966
Short name T456
Test name
Test status
Simulation time 135807414 ps
CPU time 3.36 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 207168 kb
Host smart-f75da3f0-c8f8-40a1-9bbd-fa1e7c122088
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669977966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1669977966
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.571881099
Short name T831
Test name
Test status
Simulation time 111463766 ps
CPU time 3.69 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:40 PM PDT 24
Peak memory 214560 kb
Host smart-b89be20a-d358-4ee0-981b-7fc2563512be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571881099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.571881099
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1989177355
Short name T442
Test name
Test status
Simulation time 1069906796 ps
CPU time 31.21 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:29:07 PM PDT 24
Peak memory 208712 kb
Host smart-b7dd25c0-3868-46ff-8420-938baec70d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989177355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1989177355
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3012878527
Short name T354
Test name
Test status
Simulation time 473826551 ps
CPU time 7.23 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:46 PM PDT 24
Peak memory 220360 kb
Host smart-e7c2c23c-43f3-4774-9531-45687696e572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012878527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3012878527
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.851385719
Short name T252
Test name
Test status
Simulation time 624258777 ps
CPU time 12.5 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:51 PM PDT 24
Peak memory 223012 kb
Host smart-8b7060a9-e626-4cf9-8e61-f580cf47295b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851385719 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.851385719
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.330716355
Short name T747
Test name
Test status
Simulation time 195308351 ps
CPU time 3.62 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:40 PM PDT 24
Peak memory 218516 kb
Host smart-eaaed7f0-a7ac-473b-a3c2-0e8d2e5d9d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330716355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.330716355
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1177533651
Short name T189
Test name
Test status
Simulation time 120170837 ps
CPU time 2.81 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 210196 kb
Host smart-40909756-c041-441f-8f2e-34fcfde95cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177533651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1177533651
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1113935005
Short name T102
Test name
Test status
Simulation time 117001637 ps
CPU time 0.76 seconds
Started Mar 28 01:28:43 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 206304 kb
Host smart-82d96843-54aa-4d73-b904-aca9094037b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113935005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1113935005
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4210647043
Short name T346
Test name
Test status
Simulation time 4507141526 ps
CPU time 52.13 seconds
Started Mar 28 01:28:35 PM PDT 24
Finished Mar 28 01:29:28 PM PDT 24
Peak memory 215500 kb
Host smart-94774988-62e3-44d0-8fe4-db176ae317f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4210647043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4210647043
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4000827122
Short name T870
Test name
Test status
Simulation time 233680820 ps
CPU time 2.85 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 208716 kb
Host smart-55a490eb-f96c-426b-a88d-0501d7fbac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000827122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4000827122
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2327446460
Short name T197
Test name
Test status
Simulation time 2252971713 ps
CPU time 20.12 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:57 PM PDT 24
Peak memory 210000 kb
Host smart-e01dbdbc-b267-4a92-a367-454f75453370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327446460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2327446460
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.4137576552
Short name T341
Test name
Test status
Simulation time 23696778 ps
CPU time 2.17 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 209836 kb
Host smart-83b5074c-f417-494b-b25e-8fe4cf701e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137576552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4137576552
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.4255751646
Short name T550
Test name
Test status
Simulation time 314716388 ps
CPU time 2.77 seconds
Started Mar 28 01:28:41 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 208584 kb
Host smart-a951e218-9ef0-4103-a8f2-3511b6107c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255751646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4255751646
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3153380358
Short name T875
Test name
Test status
Simulation time 5089918276 ps
CPU time 50.77 seconds
Started Mar 28 01:28:35 PM PDT 24
Finished Mar 28 01:29:26 PM PDT 24
Peak memory 208496 kb
Host smart-f37b8ea4-018d-4001-841f-50b54b19f2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153380358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3153380358
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3474436193
Short name T695
Test name
Test status
Simulation time 3564043822 ps
CPU time 37.65 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:29:15 PM PDT 24
Peak memory 209240 kb
Host smart-1e2aa14a-b85d-4b34-b5bd-3f0815b549a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474436193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3474436193
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1344881836
Short name T783
Test name
Test status
Simulation time 113070579 ps
CPU time 3.72 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 207056 kb
Host smart-3d29efe3-1a9b-49ac-9db3-46263af5f347
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344881836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1344881836
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1858470330
Short name T476
Test name
Test status
Simulation time 129252497 ps
CPU time 4.2 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:47 PM PDT 24
Peak memory 208268 kb
Host smart-008586a6-2786-4fd6-bde7-6146d4be0aeb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858470330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1858470330
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2927377540
Short name T863
Test name
Test status
Simulation time 118755399 ps
CPU time 3.66 seconds
Started Mar 28 01:28:35 PM PDT 24
Finished Mar 28 01:28:39 PM PDT 24
Peak memory 216052 kb
Host smart-5c796b66-3336-4fa9-8baf-ee140f5dfdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927377540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2927377540
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3296746000
Short name T884
Test name
Test status
Simulation time 311362141 ps
CPU time 4.15 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:40 PM PDT 24
Peak memory 207396 kb
Host smart-ae892ae9-b7ff-4508-bf5a-1c77c76fa3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296746000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3296746000
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2837096316
Short name T882
Test name
Test status
Simulation time 1210045623 ps
CPU time 17.7 seconds
Started Mar 28 01:28:35 PM PDT 24
Finished Mar 28 01:28:53 PM PDT 24
Peak memory 216952 kb
Host smart-abc03b62-4c9e-4a0a-a478-009d5e5f26c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837096316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2837096316
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1689064958
Short name T474
Test name
Test status
Simulation time 215425679 ps
CPU time 6.19 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 208864 kb
Host smart-23204ded-ca5e-4c8e-b6ce-a09fc3f90275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689064958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1689064958
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1063593016
Short name T387
Test name
Test status
Simulation time 132391807 ps
CPU time 1.6 seconds
Started Mar 28 01:28:41 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 209960 kb
Host smart-e0e4e42d-164c-46a8-86fd-ec0ae6ad5dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063593016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1063593016
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.802433645
Short name T525
Test name
Test status
Simulation time 9584655 ps
CPU time 0.74 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 206312 kb
Host smart-c22f0a30-e20f-4177-9312-2c828b594003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802433645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.802433645
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3129475048
Short name T201
Test name
Test status
Simulation time 1615049605 ps
CPU time 16.63 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:53 PM PDT 24
Peak memory 215344 kb
Host smart-6e861752-caec-4db7-bf8e-856586e42508
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3129475048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3129475048
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.730561096
Short name T679
Test name
Test status
Simulation time 86405773 ps
CPU time 3.4 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 210360 kb
Host smart-9b32f326-b3e7-4cec-8cf0-14a42df77444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730561096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.730561096
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.669542682
Short name T578
Test name
Test status
Simulation time 273207988 ps
CPU time 3.04 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 214636 kb
Host smart-656708be-f6ea-41dc-812d-cd2a85d9daf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669542682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.669542682
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1167295429
Short name T637
Test name
Test status
Simulation time 349587710 ps
CPU time 4.19 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:40 PM PDT 24
Peak memory 210052 kb
Host smart-842db23b-7876-4b96-a4af-07ff95bcf8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167295429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1167295429
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1848870208
Short name T475
Test name
Test status
Simulation time 318631156 ps
CPU time 2.65 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 222836 kb
Host smart-bd52e8ab-f646-417e-8b0e-34d319e205ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848870208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1848870208
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.865709828
Short name T298
Test name
Test status
Simulation time 3042428765 ps
CPU time 8.24 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 218876 kb
Host smart-047e0fa2-d7b7-4d17-b9a3-90c2cf2986c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865709828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.865709828
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1552340249
Short name T879
Test name
Test status
Simulation time 237617368 ps
CPU time 6.88 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:28:52 PM PDT 24
Peak memory 208868 kb
Host smart-13ee560e-0a92-4b3e-afeb-523cc5d19895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552340249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1552340249
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1188438091
Short name T235
Test name
Test status
Simulation time 4478818047 ps
CPU time 31.59 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:29:09 PM PDT 24
Peak memory 209196 kb
Host smart-d4714cf5-5fec-4eba-81e1-48ec16038e1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188438091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1188438091
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.286003068
Short name T718
Test name
Test status
Simulation time 353041543 ps
CPU time 3.84 seconds
Started Mar 28 01:28:34 PM PDT 24
Finished Mar 28 01:28:38 PM PDT 24
Peak memory 209332 kb
Host smart-e5e9b0c7-0a3c-4e3a-b5f0-87cc3c959d0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286003068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.286003068
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3000600959
Short name T699
Test name
Test status
Simulation time 190739204 ps
CPU time 3.37 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 207228 kb
Host smart-809c2ff9-cb7a-44f4-a103-9b7b80f95435
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000600959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3000600959
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1222241092
Short name T532
Test name
Test status
Simulation time 100993548 ps
CPU time 2.8 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 209812 kb
Host smart-6e3bfe2d-24bf-4167-9a63-1bfeda6061d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222241092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1222241092
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.817185493
Short name T755
Test name
Test status
Simulation time 39962685 ps
CPU time 2.37 seconds
Started Mar 28 01:28:46 PM PDT 24
Finished Mar 28 01:28:48 PM PDT 24
Peak memory 208964 kb
Host smart-a02af66b-fec6-4b48-ac82-5c92b9b2561b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817185493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.817185493
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.238076927
Short name T273
Test name
Test status
Simulation time 7361348473 ps
CPU time 52.98 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:29:32 PM PDT 24
Peak memory 216484 kb
Host smart-10e2ce65-c02f-4d5e-b232-636828180a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238076927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.238076927
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.667016861
Short name T82
Test name
Test status
Simulation time 3100417077 ps
CPU time 35.36 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:29:21 PM PDT 24
Peak memory 223088 kb
Host smart-59e31191-b7d7-4581-8d33-88673b4533bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667016861 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.667016861
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3345870226
Short name T467
Test name
Test status
Simulation time 412887366 ps
CPU time 8.31 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:47 PM PDT 24
Peak memory 208972 kb
Host smart-0d729ac7-977e-48c3-8b48-27aba2a30eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345870226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3345870226
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3824671415
Short name T113
Test name
Test status
Simulation time 1748868237 ps
CPU time 11.27 seconds
Started Mar 28 01:28:36 PM PDT 24
Finished Mar 28 01:28:48 PM PDT 24
Peak memory 211208 kb
Host smart-24979b8a-f955-4bd8-857c-2fd2a3bf1778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824671415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3824671415
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2453461450
Short name T835
Test name
Test status
Simulation time 47889976 ps
CPU time 0.79 seconds
Started Mar 28 01:28:41 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 206292 kb
Host smart-b2047bea-1761-4d20-833a-fb4a058c2ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453461450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2453461450
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.804721343
Short name T415
Test name
Test status
Simulation time 2586343301 ps
CPU time 13.57 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:51 PM PDT 24
Peak memory 215828 kb
Host smart-bc73cd5a-ac33-4b72-82fe-63c34136b127
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804721343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.804721343
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2463618127
Short name T837
Test name
Test status
Simulation time 63987634 ps
CPU time 3.6 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 215008 kb
Host smart-095c1360-7793-466f-8d15-d3a46b11c3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463618127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2463618127
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1060811254
Short name T596
Test name
Test status
Simulation time 61254741 ps
CPU time 3.12 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 218560 kb
Host smart-5caa4f31-23ac-4d6d-b1aa-b98e7c206759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060811254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1060811254
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.71815665
Short name T608
Test name
Test status
Simulation time 831430342 ps
CPU time 9.13 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:51 PM PDT 24
Peak memory 214712 kb
Host smart-1b2046c2-73c0-4376-a616-1659131c0d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71815665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.71815665
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1492311951
Short name T383
Test name
Test status
Simulation time 208190086 ps
CPU time 5.22 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:28:50 PM PDT 24
Peak memory 211360 kb
Host smart-dfdb8d42-aaaa-4f96-a88b-f730fe46108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492311951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1492311951
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1826942983
Short name T68
Test name
Test status
Simulation time 92174739 ps
CPU time 3.92 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:43 PM PDT 24
Peak memory 208692 kb
Host smart-f130139a-f032-4e36-9dbb-6ac0fe26335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826942983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1826942983
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3557864206
Short name T234
Test name
Test status
Simulation time 111143374 ps
CPU time 5.46 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 208752 kb
Host smart-b5f56a95-3816-4d93-89f9-2dd047737c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557864206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3557864206
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1942947306
Short name T644
Test name
Test status
Simulation time 152993501 ps
CPU time 2.62 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 207084 kb
Host smart-fa5324f8-f6a0-4b81-a0bb-0942589ecb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942947306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1942947306
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1052690110
Short name T144
Test name
Test status
Simulation time 47069966 ps
CPU time 2.55 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 206976 kb
Host smart-c1dd7ff2-1526-4fc7-9c12-e4fdf06236e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052690110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1052690110
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.324568864
Short name T209
Test name
Test status
Simulation time 63308466 ps
CPU time 3.2 seconds
Started Mar 28 01:28:41 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 209000 kb
Host smart-e3559f48-ea41-48ae-b046-2d92ab836a6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324568864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.324568864
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.4092752590
Short name T684
Test name
Test status
Simulation time 53563647 ps
CPU time 3.12 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 207272 kb
Host smart-331eda02-352d-41f5-9ba5-68db53a3d57e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092752590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4092752590
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1131059583
Short name T791
Test name
Test status
Simulation time 186487386 ps
CPU time 2.44 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 209460 kb
Host smart-c66db4ae-78e3-4bf6-b823-000f475fe7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131059583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1131059583
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.639723166
Short name T436
Test name
Test status
Simulation time 792404016 ps
CPU time 7.73 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:28:53 PM PDT 24
Peak memory 208696 kb
Host smart-4cd660bb-944a-4f21-880a-f4f9e817b8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639723166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.639723166
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.6896973
Short name T76
Test name
Test status
Simulation time 2024773173 ps
CPU time 37.02 seconds
Started Mar 28 01:28:43 PM PDT 24
Finished Mar 28 01:29:20 PM PDT 24
Peak memory 222800 kb
Host smart-3dba8205-1775-41a3-8f61-bb62b5b426a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6896973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.6896973
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3599504796
Short name T685
Test name
Test status
Simulation time 195426000 ps
CPU time 3.87 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 207560 kb
Host smart-13feac28-c212-446a-baed-e83b51e9883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599504796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3599504796
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.597639021
Short name T850
Test name
Test status
Simulation time 563981419 ps
CPU time 4.29 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 210392 kb
Host smart-d6d1676c-7928-421a-a261-36b15212106f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597639021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.597639021
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2841975326
Short name T502
Test name
Test status
Simulation time 44366330 ps
CPU time 0.85 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:40 PM PDT 24
Peak memory 206416 kb
Host smart-d47578ac-e87f-48d8-90ff-3295ca3d1b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841975326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2841975326
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1802755085
Short name T853
Test name
Test status
Simulation time 85863116 ps
CPU time 3.96 seconds
Started Mar 28 01:28:46 PM PDT 24
Finished Mar 28 01:28:50 PM PDT 24
Peak memory 209560 kb
Host smart-2945588a-d596-4951-b588-57a566e461bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802755085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1802755085
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.4074805321
Short name T362
Test name
Test status
Simulation time 983201756 ps
CPU time 10.81 seconds
Started Mar 28 01:28:41 PM PDT 24
Finished Mar 28 01:28:52 PM PDT 24
Peak memory 214692 kb
Host smart-ab1cbffc-b3c7-45ee-9167-abf1771ef16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074805321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.4074805321
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.91966826
Short name T295
Test name
Test status
Simulation time 113588893 ps
CPU time 5.4 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:28:51 PM PDT 24
Peak memory 214600 kb
Host smart-8c23b961-26a3-4fcd-aa18-5c27d49f539b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91966826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.91966826
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.4262906912
Short name T290
Test name
Test status
Simulation time 65287470 ps
CPU time 3.98 seconds
Started Mar 28 01:28:43 PM PDT 24
Finished Mar 28 01:28:47 PM PDT 24
Peak memory 214572 kb
Host smart-21fb8abf-af85-4f01-9516-602b5c36aa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262906912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4262906912
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1909676697
Short name T606
Test name
Test status
Simulation time 738896813 ps
CPU time 2.95 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:43 PM PDT 24
Peak memory 220744 kb
Host smart-d0059429-6787-4989-8e33-6cab6e0850a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909676697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1909676697
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3224263837
Short name T283
Test name
Test status
Simulation time 248317103 ps
CPU time 10.6 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:51 PM PDT 24
Peak memory 209088 kb
Host smart-a0cf5881-0ba3-4565-99ca-0a46cf099619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224263837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3224263837
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2875044174
Short name T569
Test name
Test status
Simulation time 60230935 ps
CPU time 3.15 seconds
Started Mar 28 01:28:41 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 208980 kb
Host smart-d20e389c-4295-4b79-9be7-4b66e8e42091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875044174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2875044174
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3110161966
Short name T666
Test name
Test status
Simulation time 276512497 ps
CPU time 3.66 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 207176 kb
Host smart-3808867e-e884-497f-b8c7-85b123fe3e80
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110161966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3110161966
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2397431969
Short name T477
Test name
Test status
Simulation time 302392516 ps
CPU time 3.1 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:41 PM PDT 24
Peak memory 207160 kb
Host smart-c7485043-95fc-446f-a855-f50239a07c33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397431969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2397431969
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3920230465
Short name T795
Test name
Test status
Simulation time 1126826948 ps
CPU time 8.42 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:48 PM PDT 24
Peak memory 208024 kb
Host smart-d8e4e255-34ca-4c8a-b36b-1003a28a6066
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920230465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3920230465
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3246708847
Short name T847
Test name
Test status
Simulation time 92919146 ps
CPU time 2.14 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:28:47 PM PDT 24
Peak memory 208388 kb
Host smart-9b1c8601-e286-4244-961a-e4391de4dce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246708847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3246708847
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1443067666
Short name T466
Test name
Test status
Simulation time 80822309 ps
CPU time 3.74 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:00 PM PDT 24
Peak memory 209120 kb
Host smart-05b8b6d6-d5cb-4f22-9aad-c65064ce1703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443067666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1443067666
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3245094511
Short name T26
Test name
Test status
Simulation time 706795548 ps
CPU time 5.18 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:48 PM PDT 24
Peak memory 207656 kb
Host smart-a466aa7f-2062-4bd0-942c-3cf7e38e8a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245094511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3245094511
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.975570551
Short name T181
Test name
Test status
Simulation time 368162879 ps
CPU time 3.34 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:46 PM PDT 24
Peak memory 210652 kb
Host smart-6822917f-eb23-4cf9-bf18-646dd6742882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975570551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.975570551
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.605535720
Short name T670
Test name
Test status
Simulation time 55885460 ps
CPU time 0.87 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:40 PM PDT 24
Peak memory 206372 kb
Host smart-2c26b7eb-157d-47de-afb9-1016f2e6a7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605535720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.605535720
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2575389130
Short name T288
Test name
Test status
Simulation time 548963937 ps
CPU time 14.18 seconds
Started Mar 28 01:28:47 PM PDT 24
Finished Mar 28 01:29:01 PM PDT 24
Peak memory 216080 kb
Host smart-e3675826-fb6e-415b-b021-1904e4362375
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2575389130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2575389130
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1267319210
Short name T749
Test name
Test status
Simulation time 99475947 ps
CPU time 2.57 seconds
Started Mar 28 01:28:43 PM PDT 24
Finished Mar 28 01:28:46 PM PDT 24
Peak memory 209688 kb
Host smart-20d1ad76-b447-4e37-9218-894761fd0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267319210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1267319210
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1369827858
Short name T478
Test name
Test status
Simulation time 27567531 ps
CPU time 2.2 seconds
Started Mar 28 01:28:43 PM PDT 24
Finished Mar 28 01:28:46 PM PDT 24
Peak memory 222844 kb
Host smart-3bc4369d-a2e2-4e45-b489-bb0349f553c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369827858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1369827858
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4265406906
Short name T877
Test name
Test status
Simulation time 1656547884 ps
CPU time 10.63 seconds
Started Mar 28 01:28:47 PM PDT 24
Finished Mar 28 01:28:58 PM PDT 24
Peak memory 214400 kb
Host smart-ad157985-c709-4c4a-87c1-7cde329ad2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265406906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4265406906
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1263485010
Short name T313
Test name
Test status
Simulation time 840326584 ps
CPU time 11 seconds
Started Mar 28 01:28:39 PM PDT 24
Finished Mar 28 01:28:50 PM PDT 24
Peak memory 214644 kb
Host smart-04c039b3-d818-4c26-af9a-e10b7cf93974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263485010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1263485010
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2771110116
Short name T485
Test name
Test status
Simulation time 200045027 ps
CPU time 2.51 seconds
Started Mar 28 01:28:48 PM PDT 24
Finished Mar 28 01:28:51 PM PDT 24
Peak memory 219632 kb
Host smart-3c604ce6-f4f1-4709-8406-4e6008546180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771110116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2771110116
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1256723988
Short name T568
Test name
Test status
Simulation time 190641611 ps
CPU time 7.92 seconds
Started Mar 28 01:28:44 PM PDT 24
Finished Mar 28 01:28:52 PM PDT 24
Peak memory 208388 kb
Host smart-d0eb5a9b-a9c3-4cff-8606-acc45fbe6560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256723988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1256723988
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.412028851
Short name T43
Test name
Test status
Simulation time 1220122781 ps
CPU time 12.7 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:52 PM PDT 24
Peak memory 208528 kb
Host smart-cc23f9f3-2926-4e00-92a2-24beeed06773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412028851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.412028851
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1950080623
Short name T636
Test name
Test status
Simulation time 150401277 ps
CPU time 5.19 seconds
Started Mar 28 01:28:48 PM PDT 24
Finished Mar 28 01:28:53 PM PDT 24
Peak memory 208808 kb
Host smart-a49c0ecb-dae0-4f58-b32c-40fe3f62ada4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950080623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1950080623
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2881889532
Short name T543
Test name
Test status
Simulation time 1444139574 ps
CPU time 51.39 seconds
Started Mar 28 01:28:47 PM PDT 24
Finished Mar 28 01:29:39 PM PDT 24
Peak memory 209592 kb
Host smart-30b0971a-5da7-4bd1-ad62-62f44dd2af18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881889532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2881889532
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.124580719
Short name T796
Test name
Test status
Simulation time 1086374690 ps
CPU time 8.22 seconds
Started Mar 28 01:28:47 PM PDT 24
Finished Mar 28 01:28:55 PM PDT 24
Peak memory 208868 kb
Host smart-09e7bc67-7915-487b-a82d-881a27b5e325
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124580719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.124580719
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3399867389
Short name T229
Test name
Test status
Simulation time 127769525 ps
CPU time 2.03 seconds
Started Mar 28 01:28:47 PM PDT 24
Finished Mar 28 01:28:49 PM PDT 24
Peak memory 206832 kb
Host smart-76fa6a17-e74a-4871-8188-5d855ab8ca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399867389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3399867389
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.529978997
Short name T857
Test name
Test status
Simulation time 127286262 ps
CPU time 3.75 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:28:50 PM PDT 24
Peak memory 207036 kb
Host smart-ecde0daa-d00d-48cb-9b96-d9801165f086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529978997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.529978997
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2604927305
Short name T746
Test name
Test status
Simulation time 248313749 ps
CPU time 14.93 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:52 PM PDT 24
Peak memory 223012 kb
Host smart-57053973-af0b-42fc-8f9c-350d71aca57a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604927305 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2604927305
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1683795336
Short name T692
Test name
Test status
Simulation time 135016132 ps
CPU time 3.12 seconds
Started Mar 28 01:28:47 PM PDT 24
Finished Mar 28 01:28:51 PM PDT 24
Peak memory 209264 kb
Host smart-0b1e7125-09d0-4350-b508-0b133da0bf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683795336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1683795336
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1327899962
Short name T388
Test name
Test status
Simulation time 733526186 ps
CPU time 4.5 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:47 PM PDT 24
Peak memory 210724 kb
Host smart-8f1c9ac0-0e81-479e-b918-05756975335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327899962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1327899962
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.489415345
Short name T620
Test name
Test status
Simulation time 49776832 ps
CPU time 0.9 seconds
Started Mar 28 01:28:43 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 206316 kb
Host smart-fb2bf296-53c5-4cfe-8531-4187043b4c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489415345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.489415345
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1667985488
Short name T391
Test name
Test status
Simulation time 1462595173 ps
CPU time 33.84 seconds
Started Mar 28 01:28:44 PM PDT 24
Finished Mar 28 01:29:18 PM PDT 24
Peak memory 214928 kb
Host smart-2afc76ae-37fb-4b54-abc6-7ec8f11fc1c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667985488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1667985488
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3637280104
Short name T28
Test name
Test status
Simulation time 370361578 ps
CPU time 4.76 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:28:49 PM PDT 24
Peak memory 221436 kb
Host smart-cf5444e8-e99c-4377-9db5-48ad7735b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637280104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3637280104
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.4173633414
Short name T618
Test name
Test status
Simulation time 27853566 ps
CPU time 1.95 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 210236 kb
Host smart-91fe2748-7c01-4aaa-bd6e-3bdb3e6f9531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173633414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.4173633414
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1044973444
Short name T759
Test name
Test status
Simulation time 292378364 ps
CPU time 8.9 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:49 PM PDT 24
Peak memory 214636 kb
Host smart-ab4ae6c6-8b7a-4768-8ca8-f7df8b460ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044973444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1044973444
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3287746558
Short name T46
Test name
Test status
Simulation time 163903713 ps
CPU time 3.09 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:43 PM PDT 24
Peak memory 220104 kb
Host smart-21eec18d-9ae0-4335-af7c-1e46b3b9c553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287746558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3287746558
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1380300026
Short name T868
Test name
Test status
Simulation time 717993569 ps
CPU time 24.56 seconds
Started Mar 28 01:28:43 PM PDT 24
Finished Mar 28 01:29:08 PM PDT 24
Peak memory 210328 kb
Host smart-99b178fa-c9be-43d9-b104-972ca0d88f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380300026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1380300026
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.114859698
Short name T570
Test name
Test status
Simulation time 138378878 ps
CPU time 4.97 seconds
Started Mar 28 01:28:37 PM PDT 24
Finished Mar 28 01:28:42 PM PDT 24
Peak memory 207068 kb
Host smart-6d2f0dc7-550b-45bc-baf1-100ca3832fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114859698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.114859698
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1363604876
Short name T404
Test name
Test status
Simulation time 76306101 ps
CPU time 2.52 seconds
Started Mar 28 01:28:41 PM PDT 24
Finished Mar 28 01:28:44 PM PDT 24
Peak memory 208376 kb
Host smart-223b2b96-95ab-4a31-8139-54c9f69d251a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363604876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1363604876
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4219750456
Short name T702
Test name
Test status
Simulation time 202606587 ps
CPU time 7.36 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:28:48 PM PDT 24
Peak memory 208196 kb
Host smart-39fb14cc-cdc1-4ade-a699-5a8dcfd73c84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219750456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4219750456
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2768476352
Short name T523
Test name
Test status
Simulation time 256742215 ps
CPU time 2.74 seconds
Started Mar 28 01:28:41 PM PDT 24
Finished Mar 28 01:28:43 PM PDT 24
Peak memory 208992 kb
Host smart-68e7306a-1b27-427a-96e1-ea614893ae47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768476352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2768476352
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1638734535
Short name T693
Test name
Test status
Simulation time 141226890 ps
CPU time 4.45 seconds
Started Mar 28 01:28:45 PM PDT 24
Finished Mar 28 01:28:50 PM PDT 24
Peak memory 209936 kb
Host smart-d9843fb8-829c-4026-9f40-1388e4d1dd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638734535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1638734535
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2748720933
Short name T682
Test name
Test status
Simulation time 307583145 ps
CPU time 5.13 seconds
Started Mar 28 01:28:44 PM PDT 24
Finished Mar 28 01:28:49 PM PDT 24
Peak memory 208476 kb
Host smart-e38f48fd-a22d-4c17-804a-d8eb2b4bffe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748720933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2748720933
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.806428120
Short name T574
Test name
Test status
Simulation time 2308848733 ps
CPU time 48.9 seconds
Started Mar 28 01:28:40 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 214804 kb
Host smart-77ff1ee0-3030-43f0-ab34-ebf59fda5202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806428120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.806428120
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3683322367
Short name T203
Test name
Test status
Simulation time 71785609 ps
CPU time 2.07 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 210404 kb
Host smart-393e6e8a-aeda-49ea-a56b-794e2bc20e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683322367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3683322367
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.84881678
Short name T675
Test name
Test status
Simulation time 22657445 ps
CPU time 0.78 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:01 PM PDT 24
Peak memory 206256 kb
Host smart-25c59403-30f7-4588-8216-a7afa4b1d57d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84881678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.84881678
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1433855899
Short name T704
Test name
Test status
Simulation time 119053052 ps
CPU time 3.18 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:05 PM PDT 24
Peak memory 218680 kb
Host smart-d0dac102-9f68-41cb-8469-d6eacf62232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433855899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1433855899
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2845912294
Short name T361
Test name
Test status
Simulation time 163368342 ps
CPU time 2.15 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:08 PM PDT 24
Peak memory 209584 kb
Host smart-7a7953c4-d7ce-43ad-a7fb-9886ac49e806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845912294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2845912294
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3697081438
Short name T92
Test name
Test status
Simulation time 1392943035 ps
CPU time 26.56 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 209968 kb
Host smart-92135f9c-660e-44e5-bdda-a15ed1d4735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697081438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3697081438
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.360239628
Short name T627
Test name
Test status
Simulation time 100436974 ps
CPU time 4.87 seconds
Started Mar 28 01:27:09 PM PDT 24
Finished Mar 28 01:27:14 PM PDT 24
Peak memory 209088 kb
Host smart-181a4edb-9dd6-4492-8f7d-e8d4b5ea92e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360239628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.360239628
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2583255906
Short name T854
Test name
Test status
Simulation time 80626457 ps
CPU time 3.48 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:10 PM PDT 24
Peak memory 214708 kb
Host smart-c33629a7-917f-4abb-a723-de1e7db4dab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583255906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2583255906
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.190648866
Short name T604
Test name
Test status
Simulation time 65387472 ps
CPU time 3.23 seconds
Started Mar 28 01:27:04 PM PDT 24
Finished Mar 28 01:27:08 PM PDT 24
Peak memory 206956 kb
Host smart-8a5ef723-18b7-4d71-b612-bdecf545377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190648866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.190648866
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1438743356
Short name T351
Test name
Test status
Simulation time 75520938 ps
CPU time 3.05 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:10 PM PDT 24
Peak memory 208580 kb
Host smart-809cd5a9-770f-4dbb-8a36-975bfc8bc041
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438743356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1438743356
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.4234461
Short name T16
Test name
Test status
Simulation time 53518101 ps
CPU time 2.8 seconds
Started Mar 28 01:27:07 PM PDT 24
Finished Mar 28 01:27:10 PM PDT 24
Peak memory 207156 kb
Host smart-cdda0d06-138f-4f4b-86df-3d3ee3a9a989
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.4234461
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.474907768
Short name T471
Test name
Test status
Simulation time 72121999 ps
CPU time 1.97 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:09 PM PDT 24
Peak memory 207140 kb
Host smart-7e47076b-99a3-46f2-b977-9d3b3761a29f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474907768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.474907768
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1094481551
Short name T771
Test name
Test status
Simulation time 602131958 ps
CPU time 7.35 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 209948 kb
Host smart-4da16724-5a97-409e-bc42-a537bc14648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094481551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1094481551
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3164560017
Short name T713
Test name
Test status
Simulation time 82735843 ps
CPU time 3.6 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:09 PM PDT 24
Peak memory 206992 kb
Host smart-74343f68-088b-4ae5-a605-90edc62b2d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164560017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3164560017
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2067895450
Short name T375
Test name
Test status
Simulation time 290382046 ps
CPU time 4.58 seconds
Started Mar 28 01:26:54 PM PDT 24
Finished Mar 28 01:26:59 PM PDT 24
Peak memory 218708 kb
Host smart-3f85b1e7-08c3-4a97-bb75-b30c58d24f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067895450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2067895450
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1852978710
Short name T185
Test name
Test status
Simulation time 128378128 ps
CPU time 3.4 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:05 PM PDT 24
Peak memory 210508 kb
Host smart-dd33dc64-fe6f-453c-90ec-9de590354ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852978710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1852978710
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.4133695055
Short name T779
Test name
Test status
Simulation time 40906493 ps
CPU time 0.88 seconds
Started Mar 28 01:28:53 PM PDT 24
Finished Mar 28 01:28:54 PM PDT 24
Peak memory 206376 kb
Host smart-e8a3c762-1458-4288-9481-4861cfb10524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133695055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4133695055
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.292607935
Short name T428
Test name
Test status
Simulation time 951240672 ps
CPU time 10.42 seconds
Started Mar 28 01:28:50 PM PDT 24
Finished Mar 28 01:29:01 PM PDT 24
Peak memory 215228 kb
Host smart-00acbf99-1de8-4727-8942-86faa004052e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292607935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.292607935
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2350506548
Short name T758
Test name
Test status
Simulation time 2444239412 ps
CPU time 53.55 seconds
Started Mar 28 01:28:49 PM PDT 24
Finished Mar 28 01:29:42 PM PDT 24
Peak memory 210748 kb
Host smart-50895c8a-f647-4338-a234-8e9cb5a32eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350506548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2350506548
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2277452602
Short name T134
Test name
Test status
Simulation time 285274511 ps
CPU time 3.38 seconds
Started Mar 28 01:28:51 PM PDT 24
Finished Mar 28 01:28:54 PM PDT 24
Peak memory 207908 kb
Host smart-e9a0a470-58b5-4452-a2cf-822a83f30899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277452602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2277452602
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2809716255
Short name T867
Test name
Test status
Simulation time 2077157129 ps
CPU time 9 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:06 PM PDT 24
Peak memory 209776 kb
Host smart-cb2d0995-7632-45c4-b287-6d742d68f228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809716255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2809716255
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3345938316
Short name T251
Test name
Test status
Simulation time 141620318 ps
CPU time 3.97 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:01 PM PDT 24
Peak memory 208428 kb
Host smart-93039731-6155-4929-b512-2e5dcc56dce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345938316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3345938316
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1294245336
Short name T555
Test name
Test status
Simulation time 46335442 ps
CPU time 3.37 seconds
Started Mar 28 01:28:49 PM PDT 24
Finished Mar 28 01:28:54 PM PDT 24
Peak memory 207652 kb
Host smart-2378c8ce-9ef8-4749-8040-0290a5df9a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294245336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1294245336
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.4183328843
Short name T45
Test name
Test status
Simulation time 862845486 ps
CPU time 6.45 seconds
Started Mar 28 01:28:38 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 208344 kb
Host smart-44a46c95-60ee-4844-b89e-03f49bb62418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183328843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.4183328843
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3369924969
Short name T524
Test name
Test status
Simulation time 2325371319 ps
CPU time 7.5 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:04 PM PDT 24
Peak memory 207156 kb
Host smart-7ef52f1f-6de8-48fe-b41e-cb2d12ee6292
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369924969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3369924969
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3060442204
Short name T697
Test name
Test status
Simulation time 162862483 ps
CPU time 3.61 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:12 PM PDT 24
Peak memory 208584 kb
Host smart-e06212c4-536d-4f66-80a4-16aa5516dbd2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060442204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3060442204
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.911357460
Short name T437
Test name
Test status
Simulation time 204945006 ps
CPU time 2.79 seconds
Started Mar 28 01:28:59 PM PDT 24
Finished Mar 28 01:29:02 PM PDT 24
Peak memory 208704 kb
Host smart-1ac0a119-1bf0-4e90-a78b-a2dcec2c2d23
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911357460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.911357460
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1438244051
Short name T300
Test name
Test status
Simulation time 52417033 ps
CPU time 2.19 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 207644 kb
Host smart-5207d10d-6420-48c0-b0bd-897971f3c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438244051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1438244051
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2637732918
Short name T414
Test name
Test status
Simulation time 67278062 ps
CPU time 2.41 seconds
Started Mar 28 01:28:42 PM PDT 24
Finished Mar 28 01:28:45 PM PDT 24
Peak memory 206996 kb
Host smart-1947b9b2-d380-4139-9934-094621cc9ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637732918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2637732918
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.779416297
Short name T285
Test name
Test status
Simulation time 123493534 ps
CPU time 4.26 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:01 PM PDT 24
Peak memory 207716 kb
Host smart-4b7b067b-91b5-4149-8aec-f9f17c288f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779416297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.779416297
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1679355056
Short name T41
Test name
Test status
Simulation time 402955691 ps
CPU time 3.49 seconds
Started Mar 28 01:29:00 PM PDT 24
Finished Mar 28 01:29:04 PM PDT 24
Peak memory 210520 kb
Host smart-de83f540-954f-4ea5-bb8d-9f25d80241ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679355056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1679355056
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3256325735
Short name T715
Test name
Test status
Simulation time 18132329 ps
CPU time 0.84 seconds
Started Mar 28 01:28:49 PM PDT 24
Finished Mar 28 01:28:50 PM PDT 24
Peak memory 206264 kb
Host smart-add2f392-46aa-4ed6-b5c3-732b1e4a6f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256325735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3256325735
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3089355578
Short name T20
Test name
Test status
Simulation time 212771831 ps
CPU time 2.13 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:10 PM PDT 24
Peak memory 223140 kb
Host smart-d5e8bea4-b745-4121-b37a-c232f089eb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089355578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3089355578
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1134906233
Short name T688
Test name
Test status
Simulation time 174148166 ps
CPU time 2.47 seconds
Started Mar 28 01:28:55 PM PDT 24
Finished Mar 28 01:28:58 PM PDT 24
Peak memory 209556 kb
Host smart-5284f3f0-eeff-43cf-8347-f8c02b499055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134906233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1134906233
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1741650303
Short name T757
Test name
Test status
Simulation time 95984242 ps
CPU time 4.32 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:02 PM PDT 24
Peak memory 214672 kb
Host smart-24797a7c-59b4-4c53-9f39-42db235a8d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741650303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1741650303
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3523944675
Short name T312
Test name
Test status
Simulation time 498321539 ps
CPU time 11.1 seconds
Started Mar 28 01:28:59 PM PDT 24
Finished Mar 28 01:29:10 PM PDT 24
Peak memory 210024 kb
Host smart-8a9213e8-247a-40be-9802-79d0f65d7a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523944675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3523944675
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2151285850
Short name T52
Test name
Test status
Simulation time 70295085 ps
CPU time 3.31 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:12 PM PDT 24
Peak memory 206500 kb
Host smart-de9fffcd-cabe-4ca0-9f6c-f40b9c5e3e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151285850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2151285850
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1172699405
Short name T674
Test name
Test status
Simulation time 1116044176 ps
CPU time 7.3 seconds
Started Mar 28 01:28:55 PM PDT 24
Finished Mar 28 01:29:03 PM PDT 24
Peak memory 208556 kb
Host smart-181400f9-a10e-4450-b132-77e30abf4408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172699405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1172699405
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.398735998
Short name T760
Test name
Test status
Simulation time 59327250 ps
CPU time 2.73 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:00 PM PDT 24
Peak memory 207860 kb
Host smart-babecbc6-60ad-4027-b554-89861b3222bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398735998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.398735998
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1577459677
Short name T710
Test name
Test status
Simulation time 123402682 ps
CPU time 3.81 seconds
Started Mar 28 01:28:52 PM PDT 24
Finished Mar 28 01:28:56 PM PDT 24
Peak memory 208940 kb
Host smart-40b7f3d1-4508-451d-ae3c-2ea35209a50f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577459677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1577459677
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.4239518686
Short name T451
Test name
Test status
Simulation time 74423005 ps
CPU time 2.62 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:01 PM PDT 24
Peak memory 209032 kb
Host smart-9419a235-ea8f-4058-8451-8284d92ca41f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239518686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4239518686
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2447886911
Short name T299
Test name
Test status
Simulation time 168737879 ps
CPU time 3.23 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:12 PM PDT 24
Peak memory 208964 kb
Host smart-d256b613-0ed7-4783-9899-a2fcc434e14f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447886911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2447886911
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.209275760
Short name T833
Test name
Test status
Simulation time 166869024 ps
CPU time 4.76 seconds
Started Mar 28 01:28:48 PM PDT 24
Finished Mar 28 01:28:53 PM PDT 24
Peak memory 209652 kb
Host smart-15c0333f-ad89-44ec-95af-a12b24c1ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209275760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.209275760
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1934096647
Short name T497
Test name
Test status
Simulation time 530550093 ps
CPU time 4.14 seconds
Started Mar 28 01:28:48 PM PDT 24
Finished Mar 28 01:28:52 PM PDT 24
Peak memory 208964 kb
Host smart-5b580118-e19a-4d8f-9cad-af06c11fd72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934096647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1934096647
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3803354551
Short name T849
Test name
Test status
Simulation time 19078130973 ps
CPU time 105.09 seconds
Started Mar 28 01:28:48 PM PDT 24
Finished Mar 28 01:30:33 PM PDT 24
Peak memory 222936 kb
Host smart-7ba7575d-1670-4a12-9fba-bf0e5bd1a991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803354551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3803354551
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.626911970
Short name T258
Test name
Test status
Simulation time 900272582 ps
CPU time 31.75 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 208780 kb
Host smart-cfeccf05-830a-4baa-9681-4fcfa4469ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626911970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.626911970
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1462821171
Short name T409
Test name
Test status
Simulation time 174051473 ps
CPU time 4 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:02 PM PDT 24
Peak memory 210884 kb
Host smart-758a57f0-3a16-40b2-a5aa-6b32de48ab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462821171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1462821171
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.807279944
Short name T520
Test name
Test status
Simulation time 11203592 ps
CPU time 0.84 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:28:59 PM PDT 24
Peak memory 206304 kb
Host smart-419180ae-ec05-4fac-a115-7a949b7ca168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807279944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.807279944
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2642660278
Short name T427
Test name
Test status
Simulation time 86658601 ps
CPU time 4.04 seconds
Started Mar 28 01:29:00 PM PDT 24
Finished Mar 28 01:29:04 PM PDT 24
Peak memory 215260 kb
Host smart-4049e946-c9a4-4e87-ba18-1348741f9e05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642660278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2642660278
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3586014906
Short name T495
Test name
Test status
Simulation time 658924227 ps
CPU time 2.12 seconds
Started Mar 28 01:28:50 PM PDT 24
Finished Mar 28 01:28:53 PM PDT 24
Peak memory 207660 kb
Host smart-dd24d6b6-e678-4975-bb9a-9b5404db178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586014906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3586014906
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.655352875
Short name T316
Test name
Test status
Simulation time 1161120002 ps
CPU time 11.51 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:09 PM PDT 24
Peak memory 208300 kb
Host smart-d26e1fe3-031d-4ec6-9731-1b77f35d66a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655352875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.655352875
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2033350992
Short name T330
Test name
Test status
Simulation time 320297841 ps
CPU time 5 seconds
Started Mar 28 01:28:49 PM PDT 24
Finished Mar 28 01:28:54 PM PDT 24
Peak memory 211476 kb
Host smart-f8674a96-bd3d-49da-9d24-e4d9faa000de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033350992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2033350992
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_random.1326332714
Short name T530
Test name
Test status
Simulation time 31841997 ps
CPU time 2.51 seconds
Started Mar 28 01:28:55 PM PDT 24
Finished Mar 28 01:28:58 PM PDT 24
Peak memory 207688 kb
Host smart-1f94990b-7e10-48b8-a903-846b0ccf7d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326332714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1326332714
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3960746386
Short name T297
Test name
Test status
Simulation time 449320876 ps
CPU time 3.06 seconds
Started Mar 28 01:28:59 PM PDT 24
Finished Mar 28 01:29:02 PM PDT 24
Peak memory 209004 kb
Host smart-f7aa6def-ef91-49ef-8fcd-5e3386e7392c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960746386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3960746386
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3764458000
Short name T269
Test name
Test status
Simulation time 3281577321 ps
CPU time 45.31 seconds
Started Mar 28 01:28:51 PM PDT 24
Finished Mar 28 01:29:36 PM PDT 24
Peak memory 209384 kb
Host smart-a0c4a38d-d829-4f8b-a25c-4352b76cbeb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764458000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3764458000
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1104119467
Short name T380
Test name
Test status
Simulation time 47208612 ps
CPU time 1.8 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:00 PM PDT 24
Peak memory 207176 kb
Host smart-474abac8-3c00-4f08-8fbe-07b4d7bc9f47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104119467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1104119467
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2542500649
Short name T561
Test name
Test status
Simulation time 441741333 ps
CPU time 5.67 seconds
Started Mar 28 01:28:55 PM PDT 24
Finished Mar 28 01:29:01 PM PDT 24
Peak memory 207184 kb
Host smart-cdc39436-2e52-484d-9798-36bb7832cbb4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542500649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2542500649
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2675163631
Short name T601
Test name
Test status
Simulation time 2033749489 ps
CPU time 17.97 seconds
Started Mar 28 01:28:59 PM PDT 24
Finished Mar 28 01:29:17 PM PDT 24
Peak memory 209312 kb
Host smart-98e07a2e-e142-4639-a5c3-b3c8adc952b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675163631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2675163631
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.22921040
Short name T641
Test name
Test status
Simulation time 29762716 ps
CPU time 1.97 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:28:59 PM PDT 24
Peak memory 208824 kb
Host smart-46fefa08-ae92-4cb2-900f-50c78c3b4fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22921040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.22921040
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.114048890
Short name T80
Test name
Test status
Simulation time 18949458741 ps
CPU time 550.74 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:38:09 PM PDT 24
Peak memory 218764 kb
Host smart-0857b8c4-4e38-4e28-94d7-10cab6e9f26f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114048890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.114048890
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3269575088
Short name T411
Test name
Test status
Simulation time 2113057533 ps
CPU time 40.21 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:37 PM PDT 24
Peak memory 219012 kb
Host smart-76344272-1e8d-40b9-97b3-633646cd8b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269575088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3269575088
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3529486574
Short name T832
Test name
Test status
Simulation time 396291734 ps
CPU time 5.11 seconds
Started Mar 28 01:29:00 PM PDT 24
Finished Mar 28 01:29:05 PM PDT 24
Peak memory 210852 kb
Host smart-1c008554-4206-475c-850f-5b43e8789e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529486574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3529486574
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1063071142
Short name T873
Test name
Test status
Simulation time 26787380 ps
CPU time 0.91 seconds
Started Mar 28 01:29:00 PM PDT 24
Finished Mar 28 01:29:01 PM PDT 24
Peak memory 206460 kb
Host smart-7ac46de6-1d35-42ef-a11e-d6aa5f413cec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063071142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1063071142
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2709853594
Short name T417
Test name
Test status
Simulation time 439568947 ps
CPU time 9.26 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:18 PM PDT 24
Peak memory 222652 kb
Host smart-5c1d93b6-513e-497c-912f-20b59704c15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709853594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2709853594
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.779745148
Short name T32
Test name
Test status
Simulation time 84639489 ps
CPU time 3.03 seconds
Started Mar 28 01:29:00 PM PDT 24
Finished Mar 28 01:29:03 PM PDT 24
Peak memory 211216 kb
Host smart-bfc7f935-7e49-4a1a-b183-2e73fc932db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779745148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.779745148
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1291888716
Short name T499
Test name
Test status
Simulation time 1256831475 ps
CPU time 20.85 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:30 PM PDT 24
Peak memory 218612 kb
Host smart-e76fc72d-5e9c-42ec-904c-3caed8daadbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291888716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1291888716
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3618336762
Short name T399
Test name
Test status
Simulation time 40963045 ps
CPU time 2.62 seconds
Started Mar 28 01:29:01 PM PDT 24
Finished Mar 28 01:29:04 PM PDT 24
Peak memory 208132 kb
Host smart-83d47ec7-3d4a-415f-8692-3eb8b1a00e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618336762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3618336762
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1645798155
Short name T296
Test name
Test status
Simulation time 56428793 ps
CPU time 3.5 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:02 PM PDT 24
Peak memory 214636 kb
Host smart-3f66e049-378d-4b2c-83fc-a67850bb70e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645798155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1645798155
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.764151130
Short name T65
Test name
Test status
Simulation time 448508478 ps
CPU time 5.44 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:14 PM PDT 24
Peak memory 208596 kb
Host smart-5f3e7969-1565-4927-834a-bd2313a6487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764151130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.764151130
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.593303010
Short name T751
Test name
Test status
Simulation time 1078517543 ps
CPU time 15.48 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:13 PM PDT 24
Peak memory 209056 kb
Host smart-9b76fe1a-69a9-4f25-a83b-9eff8b944b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593303010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.593303010
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2015099475
Short name T768
Test name
Test status
Simulation time 500230496 ps
CPU time 12.32 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 208728 kb
Host smart-25b6ff06-8bcb-4da6-9179-9f0a1da935bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015099475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2015099475
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2574989107
Short name T900
Test name
Test status
Simulation time 770692701 ps
CPU time 6.68 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:05 PM PDT 24
Peak memory 208992 kb
Host smart-1a6d8fee-e8c3-4897-af2d-8e0cdc1de12e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574989107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2574989107
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4262397950
Short name T722
Test name
Test status
Simulation time 1961492276 ps
CPU time 8.5 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:17 PM PDT 24
Peak memory 208116 kb
Host smart-29896c56-a878-4e95-9b05-0e579979f878
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262397950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4262397950
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2135443956
Short name T369
Test name
Test status
Simulation time 3102274980 ps
CPU time 5.49 seconds
Started Mar 28 01:29:00 PM PDT 24
Finished Mar 28 01:29:06 PM PDT 24
Peak memory 209348 kb
Host smart-ad460ddf-e035-480a-9157-ac523142dcc9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135443956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2135443956
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2580974351
Short name T730
Test name
Test status
Simulation time 382970758 ps
CPU time 9.47 seconds
Started Mar 28 01:29:00 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 209316 kb
Host smart-57e68c73-1afb-4b5f-9c06-90652a002cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580974351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2580974351
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.68904501
Short name T851
Test name
Test status
Simulation time 591774165 ps
CPU time 6.37 seconds
Started Mar 28 01:28:57 PM PDT 24
Finished Mar 28 01:29:04 PM PDT 24
Peak memory 208796 kb
Host smart-fe53cdc5-edcf-4e2a-b3d6-7feb732da88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68904501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.68904501
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2572408868
Short name T319
Test name
Test status
Simulation time 519795583 ps
CPU time 11.41 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:09 PM PDT 24
Peak memory 216800 kb
Host smart-43433e77-ce5c-44f4-9325-6b503c05f900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572408868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2572408868
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3768764852
Short name T277
Test name
Test status
Simulation time 332153308 ps
CPU time 4.55 seconds
Started Mar 28 01:28:49 PM PDT 24
Finished Mar 28 01:28:55 PM PDT 24
Peak memory 209312 kb
Host smart-7447b585-585f-466a-b830-44ec2e9474bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768764852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3768764852
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1978441995
Short name T175
Test name
Test status
Simulation time 784337258 ps
CPU time 17.69 seconds
Started Mar 28 01:29:01 PM PDT 24
Finished Mar 28 01:29:19 PM PDT 24
Peak memory 210804 kb
Host smart-dfb2e63f-2e57-4dd4-a538-570bf93e506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978441995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1978441995
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2851617018
Short name T457
Test name
Test status
Simulation time 8649047 ps
CPU time 0.73 seconds
Started Mar 28 01:29:05 PM PDT 24
Finished Mar 28 01:29:06 PM PDT 24
Peak memory 206324 kb
Host smart-3d608023-bc51-4bb4-8b8b-446b865f85ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851617018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2851617018
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.627833619
Short name T434
Test name
Test status
Simulation time 760117681 ps
CPU time 5.54 seconds
Started Mar 28 01:28:56 PM PDT 24
Finished Mar 28 01:29:01 PM PDT 24
Peak memory 214632 kb
Host smart-ccb68483-8039-4d1a-a0da-745b3e5a7b8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627833619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.627833619
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.96029135
Short name T808
Test name
Test status
Simulation time 2023931720 ps
CPU time 4.91 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:03 PM PDT 24
Peak memory 214700 kb
Host smart-681fb284-b7d3-43fc-8591-28a99eb28593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96029135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.96029135
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1518789951
Short name T889
Test name
Test status
Simulation time 864058743 ps
CPU time 9.65 seconds
Started Mar 28 01:29:01 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 208232 kb
Host smart-d75653c7-5784-4423-8035-0f6f84bdf454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518789951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1518789951
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.606164795
Short name T394
Test name
Test status
Simulation time 6659757385 ps
CPU time 56.05 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:55 PM PDT 24
Peak memory 210640 kb
Host smart-a88a74bf-a901-4502-ba22-a15ab0972af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606164795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.606164795
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2773164470
Short name T846
Test name
Test status
Simulation time 41569076 ps
CPU time 3.34 seconds
Started Mar 28 01:28:55 PM PDT 24
Finished Mar 28 01:28:59 PM PDT 24
Peak memory 222604 kb
Host smart-14eefaf1-0e5e-4990-b8eb-d4657c918531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773164470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2773164470
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1220992392
Short name T646
Test name
Test status
Simulation time 876277009 ps
CPU time 3.12 seconds
Started Mar 28 01:28:55 PM PDT 24
Finished Mar 28 01:28:58 PM PDT 24
Peak memory 215912 kb
Host smart-94f864da-ae7e-49bf-88ae-cbba77f0cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220992392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1220992392
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3764273732
Short name T455
Test name
Test status
Simulation time 2366149597 ps
CPU time 15.81 seconds
Started Mar 28 01:28:56 PM PDT 24
Finished Mar 28 01:29:12 PM PDT 24
Peak memory 208424 kb
Host smart-b54668aa-3e9c-4321-9eda-598a7e20190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764273732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3764273732
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2779461093
Short name T788
Test name
Test status
Simulation time 138912493 ps
CPU time 3.44 seconds
Started Mar 28 01:28:58 PM PDT 24
Finished Mar 28 01:29:01 PM PDT 24
Peak memory 207500 kb
Host smart-3870f378-28ee-474a-a5de-f188bed098e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779461093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2779461093
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1515159214
Short name T533
Test name
Test status
Simulation time 20645130 ps
CPU time 1.8 seconds
Started Mar 28 01:28:51 PM PDT 24
Finished Mar 28 01:28:53 PM PDT 24
Peak memory 207160 kb
Host smart-fa27e80b-16f7-40b6-9efd-22be3ec90fe6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515159214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1515159214
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3062908582
Short name T557
Test name
Test status
Simulation time 214849573 ps
CPU time 3.12 seconds
Started Mar 28 01:28:59 PM PDT 24
Finished Mar 28 01:29:03 PM PDT 24
Peak memory 207160 kb
Host smart-c93b0093-5d96-4d37-a011-405460783164
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062908582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3062908582
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3463376013
Short name T350
Test name
Test status
Simulation time 514937182 ps
CPU time 8.46 seconds
Started Mar 28 01:29:00 PM PDT 24
Finished Mar 28 01:29:08 PM PDT 24
Peak memory 208932 kb
Host smart-b2ce732d-a356-4796-b623-d61e6801faac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463376013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3463376013
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2665198872
Short name T484
Test name
Test status
Simulation time 20075731 ps
CPU time 1.63 seconds
Started Mar 28 01:28:55 PM PDT 24
Finished Mar 28 01:28:57 PM PDT 24
Peak memory 208460 kb
Host smart-44e0d1ca-827e-4943-b3c2-f6f5acc0c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665198872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2665198872
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2342499614
Short name T664
Test name
Test status
Simulation time 81010342 ps
CPU time 1.87 seconds
Started Mar 28 01:28:49 PM PDT 24
Finished Mar 28 01:28:51 PM PDT 24
Peak memory 207628 kb
Host smart-eefaa436-9e0c-46ca-a59b-020a63b98146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342499614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2342499614
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.823142953
Short name T479
Test name
Test status
Simulation time 833629821 ps
CPU time 7.11 seconds
Started Mar 28 01:28:56 PM PDT 24
Finished Mar 28 01:29:03 PM PDT 24
Peak memory 207428 kb
Host smart-2eef53f0-aaed-4558-b2b2-16f9e31f4e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823142953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.823142953
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1722543216
Short name T34
Test name
Test status
Simulation time 170374267 ps
CPU time 2.5 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 210176 kb
Host smart-a9fe1931-83c9-4930-a993-8726830b50fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722543216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1722543216
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3019495
Short name T541
Test name
Test status
Simulation time 17641358 ps
CPU time 0.85 seconds
Started Mar 28 01:29:10 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 206292 kb
Host smart-78c7169c-e70d-49af-86cc-27a46c0ea4c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3019495
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3138343720
Short name T426
Test name
Test status
Simulation time 34167327 ps
CPU time 2.86 seconds
Started Mar 28 01:29:06 PM PDT 24
Finished Mar 28 01:29:09 PM PDT 24
Peak memory 214592 kb
Host smart-b5b2c3a1-cedc-4e05-9469-57b2111d3ded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138343720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3138343720
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.837395579
Short name T349
Test name
Test status
Simulation time 385937114 ps
CPU time 6.2 seconds
Started Mar 28 01:29:06 PM PDT 24
Finished Mar 28 01:29:13 PM PDT 24
Peak memory 214744 kb
Host smart-1720afad-bd5b-4bac-8322-c0b8cbd2f912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837395579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.837395579
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3383257654
Short name T85
Test name
Test status
Simulation time 590095121 ps
CPU time 4.15 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:13 PM PDT 24
Peak memory 220792 kb
Host smart-3f487dac-34fa-4dda-8c7c-da2bdcbf764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383257654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3383257654
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2738488974
Short name T818
Test name
Test status
Simulation time 144149797 ps
CPU time 2.34 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 220344 kb
Host smart-7bb05d98-bb58-4ca4-8045-6f2a17452291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738488974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2738488974
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3454104813
Short name T542
Test name
Test status
Simulation time 1356048731 ps
CPU time 42 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:51 PM PDT 24
Peak memory 209900 kb
Host smart-2a029ef0-c72c-43fa-bd2e-f5ccc9119ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454104813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3454104813
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2110190419
Short name T372
Test name
Test status
Simulation time 74100485 ps
CPU time 3.37 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 208032 kb
Host smart-7df572ff-8156-49cb-8e5a-eecb1c38fd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110190419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2110190419
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3399073174
Short name T412
Test name
Test status
Simulation time 792444656 ps
CPU time 6.44 seconds
Started Mar 28 01:29:11 PM PDT 24
Finished Mar 28 01:29:18 PM PDT 24
Peak memory 209096 kb
Host smart-dc642720-74ce-45da-adfb-eafc2cfb0c05
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399073174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3399073174
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1791397104
Short name T496
Test name
Test status
Simulation time 885953569 ps
CPU time 22.01 seconds
Started Mar 28 01:29:07 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 209372 kb
Host smart-0c380c6f-6d93-424f-8f62-6c45b090ceea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791397104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1791397104
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.842215749
Short name T773
Test name
Test status
Simulation time 132461948 ps
CPU time 3.56 seconds
Started Mar 28 01:29:06 PM PDT 24
Finished Mar 28 01:29:09 PM PDT 24
Peak memory 209200 kb
Host smart-f7cb1804-e217-40c3-8505-d1683346ca63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842215749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.842215749
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.856829121
Short name T505
Test name
Test status
Simulation time 45563860 ps
CPU time 1.91 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:10 PM PDT 24
Peak memory 208588 kb
Host smart-c419e7a9-8924-4d40-9019-53929331ea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856829121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.856829121
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1051559654
Short name T228
Test name
Test status
Simulation time 883299001 ps
CPU time 19.2 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 208228 kb
Host smart-c3c13f55-1c9b-42ee-8b11-4abb33fff05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051559654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1051559654
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1206330018
Short name T709
Test name
Test status
Simulation time 306282747 ps
CPU time 9.64 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:19 PM PDT 24
Peak memory 209404 kb
Host smart-aa864baf-b4aa-432e-9ab7-598db6f69f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206330018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1206330018
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1308685780
Short name T390
Test name
Test status
Simulation time 188319799 ps
CPU time 2.34 seconds
Started Mar 28 01:29:07 PM PDT 24
Finished Mar 28 01:29:10 PM PDT 24
Peak memory 210588 kb
Host smart-a2e37fb1-e668-4b1d-ab3a-a5fb3835cbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308685780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1308685780
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.227015061
Short name T742
Test name
Test status
Simulation time 29397200 ps
CPU time 0.78 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:10 PM PDT 24
Peak memory 206236 kb
Host smart-33ab080a-80a6-4aa3-913c-56b156884122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227015061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.227015061
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.578925079
Short name T116
Test name
Test status
Simulation time 46315932 ps
CPU time 3.52 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:12 PM PDT 24
Peak memory 214776 kb
Host smart-0c09b563-b195-4d3a-8ac5-ea82294eef59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578925079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.578925079
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.102646970
Short name T315
Test name
Test status
Simulation time 465212259 ps
CPU time 3.22 seconds
Started Mar 28 01:29:11 PM PDT 24
Finished Mar 28 01:29:14 PM PDT 24
Peak memory 218824 kb
Host smart-8b8d0ef3-5b7c-480a-99d6-a7057523cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102646970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.102646970
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1241930281
Short name T83
Test name
Test status
Simulation time 225390533 ps
CPU time 3.62 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:13 PM PDT 24
Peak memory 209972 kb
Host smart-9fbb5597-b2ce-4b29-a0c8-1dc6264db478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241930281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1241930281
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.970340323
Short name T250
Test name
Test status
Simulation time 292964179 ps
CPU time 3.88 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:13 PM PDT 24
Peak memory 209248 kb
Host smart-db5997b4-9d8f-4645-87f7-3f5022576511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970340323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.970340323
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.883188410
Short name T274
Test name
Test status
Simulation time 814694055 ps
CPU time 5.63 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:15 PM PDT 24
Peak memory 209896 kb
Host smart-6c6db52b-5664-48b4-b277-808be4d64137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883188410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.883188410
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.955195126
Short name T579
Test name
Test status
Simulation time 437290526 ps
CPU time 4.43 seconds
Started Mar 28 01:29:11 PM PDT 24
Finished Mar 28 01:29:16 PM PDT 24
Peak memory 208956 kb
Host smart-29a42f98-a6d6-44bd-b66a-5377f9ba7815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955195126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.955195126
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3999116430
Short name T462
Test name
Test status
Simulation time 264782290 ps
CPU time 3.64 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:13 PM PDT 24
Peak memory 209212 kb
Host smart-e1bb6d85-8d25-4b53-a3d3-39a28eb9490d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999116430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3999116430
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.769940282
Short name T585
Test name
Test status
Simulation time 448531659 ps
CPU time 5.97 seconds
Started Mar 28 01:29:10 PM PDT 24
Finished Mar 28 01:29:17 PM PDT 24
Peak memory 208516 kb
Host smart-a76d583b-531a-490e-afcd-8612e7b80ecc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769940282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.769940282
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2225452284
Short name T738
Test name
Test status
Simulation time 74644210 ps
CPU time 3.41 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 209100 kb
Host smart-c06ef9b5-15be-4fa2-963e-1356d2e85c9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225452284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2225452284
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1002339901
Short name T793
Test name
Test status
Simulation time 48832464 ps
CPU time 2.7 seconds
Started Mar 28 01:29:10 PM PDT 24
Finished Mar 28 01:29:13 PM PDT 24
Peak memory 209004 kb
Host smart-5887c0a3-07bd-4a4b-898d-0b1efac31c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002339901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1002339901
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.180104475
Short name T623
Test name
Test status
Simulation time 1051736550 ps
CPU time 3.14 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:12 PM PDT 24
Peak memory 208988 kb
Host smart-168a7def-d62d-4251-a5bb-1bf8577a39f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180104475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.180104475
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3327138126
Short name T240
Test name
Test status
Simulation time 12056983845 ps
CPU time 20.72 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 222836 kb
Host smart-0a1c4d08-315a-433a-af05-4504cbcd40a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327138126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3327138126
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.256526786
Short name T219
Test name
Test status
Simulation time 2540079660 ps
CPU time 7.56 seconds
Started Mar 28 01:29:09 PM PDT 24
Finished Mar 28 01:29:16 PM PDT 24
Peak memory 214796 kb
Host smart-13bad4fa-e6f8-40bc-873c-e6af0270be58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256526786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.256526786
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.4068255284
Short name T817
Test name
Test status
Simulation time 281639226 ps
CPU time 1.9 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:10 PM PDT 24
Peak memory 210304 kb
Host smart-b187ce95-a9e6-4165-9d5f-cd804d940088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068255284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4068255284
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2047998489
Short name T721
Test name
Test status
Simulation time 15865223 ps
CPU time 0.88 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 206260 kb
Host smart-e9e23992-ba96-427c-a40e-14c57da468c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047998489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2047998489
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4185058929
Short name T774
Test name
Test status
Simulation time 139904125 ps
CPU time 3.02 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 215120 kb
Host smart-048081f9-5c67-4c4e-a33f-761ebffd3e85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185058929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4185058929
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3189212019
Short name T9
Test name
Test status
Simulation time 337567721 ps
CPU time 2.66 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 215016 kb
Host smart-f172ca28-3e7a-4af0-9a83-a9ca1a037abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189212019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3189212019
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4283410613
Short name T67
Test name
Test status
Simulation time 259830566 ps
CPU time 3.52 seconds
Started Mar 28 01:29:22 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 214632 kb
Host smart-7d7b83a0-ff73-47b8-9475-23d0cf761a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283410613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4283410613
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.445246915
Short name T764
Test name
Test status
Simulation time 664573558 ps
CPU time 13.33 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:37 PM PDT 24
Peak memory 222772 kb
Host smart-883ba1ed-ba0b-4e46-9e70-287187d526b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445246915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.445246915
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.185737187
Short name T247
Test name
Test status
Simulation time 350909381 ps
CPU time 3.66 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 216376 kb
Host smart-472264d0-2cfb-4884-92c9-a4b85ce7904b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185737187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.185737187
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1139868414
Short name T610
Test name
Test status
Simulation time 1653198069 ps
CPU time 7.95 seconds
Started Mar 28 01:29:22 PM PDT 24
Finished Mar 28 01:29:31 PM PDT 24
Peak memory 208900 kb
Host smart-5e81b123-de89-4e87-84ec-c2e72145a82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139868414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1139868414
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1675208190
Short name T538
Test name
Test status
Simulation time 80799073 ps
CPU time 2.54 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 206928 kb
Host smart-763c0be7-d3b5-48a7-9638-f0a61b6aab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675208190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1675208190
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.433184917
Short name T511
Test name
Test status
Simulation time 244045949 ps
CPU time 7.25 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:29:34 PM PDT 24
Peak memory 208216 kb
Host smart-e7dc18ff-d455-4e9d-9ea6-9472265e0c4d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433184917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.433184917
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1874367335
Short name T580
Test name
Test status
Simulation time 141681522 ps
CPU time 3.63 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 208968 kb
Host smart-03dce075-8b03-4c01-a0c1-4126ed0cc87f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874367335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1874367335
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1957666438
Short name T534
Test name
Test status
Simulation time 163373139 ps
CPU time 3.26 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 209404 kb
Host smart-76b2d7d5-a2d0-44e0-9f36-8845c5773541
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957666438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1957666438
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1236050235
Short name T140
Test name
Test status
Simulation time 124518121 ps
CPU time 4.13 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:28 PM PDT 24
Peak memory 214596 kb
Host smart-edb2f90c-8367-47f0-96fe-91718bc95dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236050235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1236050235
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.361503329
Short name T469
Test name
Test status
Simulation time 45621005 ps
CPU time 2.6 seconds
Started Mar 28 01:29:08 PM PDT 24
Finished Mar 28 01:29:11 PM PDT 24
Peak memory 207212 kb
Host smart-37292be1-24ec-4a35-ae80-9f94a8a262d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361503329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.361503329
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.4099077048
Short name T367
Test name
Test status
Simulation time 36428401014 ps
CPU time 376.06 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:35:41 PM PDT 24
Peak memory 223000 kb
Host smart-a26b9679-1b4c-4edf-ac0d-b4fec51eb203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099077048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4099077048
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.222099205
Short name T514
Test name
Test status
Simulation time 675596165 ps
CPU time 8.05 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:29:35 PM PDT 24
Peak memory 208928 kb
Host smart-e08a3da6-795e-447b-990a-54828054f2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222099205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.222099205
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1132569450
Short name T841
Test name
Test status
Simulation time 73687645 ps
CPU time 1.98 seconds
Started Mar 28 01:29:22 PM PDT 24
Finished Mar 28 01:29:25 PM PDT 24
Peak memory 210008 kb
Host smart-55d1f846-acef-4b6c-8987-e890f3b2f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132569450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1132569450
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3346514593
Short name T616
Test name
Test status
Simulation time 13106874 ps
CPU time 0.75 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:24 PM PDT 24
Peak memory 206208 kb
Host smart-e74a4c08-5362-4330-9e43-1ce95b3eb5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346514593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3346514593
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1232085198
Short name T577
Test name
Test status
Simulation time 155707295 ps
CPU time 3.03 seconds
Started Mar 28 01:29:20 PM PDT 24
Finished Mar 28 01:29:24 PM PDT 24
Peak memory 223060 kb
Host smart-32e02af8-1a9e-43a1-baf3-1d207f9f6a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232085198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1232085198
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.999457986
Short name T660
Test name
Test status
Simulation time 157518821 ps
CPU time 3.07 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 210180 kb
Host smart-9c3e9b75-00b7-4c55-a8a5-0cc563c75c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999457986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.999457986
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.64665838
Short name T88
Test name
Test status
Simulation time 261991850 ps
CPU time 8.73 seconds
Started Mar 28 01:29:22 PM PDT 24
Finished Mar 28 01:29:31 PM PDT 24
Peak memory 214676 kb
Host smart-21954f9d-6962-49c3-8e7e-8f4fd4fe0cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64665838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.64665838
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2630825573
Short name T291
Test name
Test status
Simulation time 174875414 ps
CPU time 6.95 seconds
Started Mar 28 01:29:22 PM PDT 24
Finished Mar 28 01:29:30 PM PDT 24
Peak memory 222684 kb
Host smart-6b04c289-e32f-4c7c-bda1-fcca62731d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630825573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2630825573
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3103767110
Short name T49
Test name
Test status
Simulation time 63815394 ps
CPU time 2.14 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:26 PM PDT 24
Peak memory 222788 kb
Host smart-24d192c6-edd5-4cbc-993b-f503d1959896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103767110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3103767110
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.615765717
Short name T642
Test name
Test status
Simulation time 873347395 ps
CPU time 8.54 seconds
Started Mar 28 01:29:21 PM PDT 24
Finished Mar 28 01:29:30 PM PDT 24
Peak memory 209016 kb
Host smart-949939b3-4029-427b-856e-5f3a70569ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615765717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.615765717
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.962283634
Short name T337
Test name
Test status
Simulation time 119398122 ps
CPU time 2.11 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:26 PM PDT 24
Peak memory 208764 kb
Host smart-d86ef8c3-4f53-4528-bd32-8d184fd95a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962283634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.962283634
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4031249346
Short name T613
Test name
Test status
Simulation time 136561386 ps
CPU time 5.64 seconds
Started Mar 28 01:29:22 PM PDT 24
Finished Mar 28 01:29:28 PM PDT 24
Peak memory 207208 kb
Host smart-bdca4b97-4694-4bd7-938f-ac6224001bbd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031249346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4031249346
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.136170435
Short name T345
Test name
Test status
Simulation time 6069376963 ps
CPU time 60.23 seconds
Started Mar 28 01:29:21 PM PDT 24
Finished Mar 28 01:30:22 PM PDT 24
Peak memory 209084 kb
Host smart-bd38e21b-84c3-474e-8aef-d68bac4b316e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136170435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.136170435
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2590065742
Short name T740
Test name
Test status
Simulation time 24352842 ps
CPU time 1.92 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:28 PM PDT 24
Peak memory 207176 kb
Host smart-29d324b4-0eca-45c3-a3fa-d97e0dbccdee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590065742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2590065742
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3899564337
Short name T767
Test name
Test status
Simulation time 7646521575 ps
CPU time 37.12 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:30:00 PM PDT 24
Peak memory 220336 kb
Host smart-ffa78b59-a770-4283-9c0b-0004c08a98ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899564337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3899564337
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.23714399
Short name T444
Test name
Test status
Simulation time 145629459 ps
CPU time 3.44 seconds
Started Mar 28 01:29:21 PM PDT 24
Finished Mar 28 01:29:25 PM PDT 24
Peak memory 208612 kb
Host smart-cd0b5831-6924-40fe-ab5d-e73658752998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23714399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.23714399
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.994047573
Short name T892
Test name
Test status
Simulation time 90825551 ps
CPU time 4.22 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 208332 kb
Host smart-6747c76b-2e01-4713-a5d2-4c2d394164a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994047573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.994047573
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.114196201
Short name T38
Test name
Test status
Simulation time 74671172 ps
CPU time 3.19 seconds
Started Mar 28 01:29:29 PM PDT 24
Finished Mar 28 01:29:32 PM PDT 24
Peak memory 210476 kb
Host smart-63585b79-4c3d-4be3-90b1-e69b40becaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114196201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.114196201
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3028728114
Short name T544
Test name
Test status
Simulation time 16888559 ps
CPU time 1.03 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:29:26 PM PDT 24
Peak memory 206356 kb
Host smart-1a9bc61c-88f1-4e5a-9c24-96eeb14a57fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028728114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3028728114
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.557245078
Short name T371
Test name
Test status
Simulation time 36277663 ps
CPU time 2.34 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 210452 kb
Host smart-dd1e3daa-3de1-45ea-814c-c211b2f85ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557245078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.557245078
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.745387256
Short name T812
Test name
Test status
Simulation time 311763607 ps
CPU time 3.23 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:28 PM PDT 24
Peak memory 209400 kb
Host smart-0417af6a-298e-4ca9-97f3-1301162c023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745387256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.745387256
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3331244534
Short name T519
Test name
Test status
Simulation time 63877779 ps
CPU time 1.42 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:29:26 PM PDT 24
Peak memory 206624 kb
Host smart-ff8b7311-3376-4069-a94a-8385bfced65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331244534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3331244534
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3219160907
Short name T737
Test name
Test status
Simulation time 290930180 ps
CPU time 2.99 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:26 PM PDT 24
Peak memory 207604 kb
Host smart-bc44b314-605f-4cb4-8bcb-67eaf3d1321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219160907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3219160907
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.447817862
Short name T602
Test name
Test status
Simulation time 186274053 ps
CPU time 2.54 seconds
Started Mar 28 01:29:22 PM PDT 24
Finished Mar 28 01:29:26 PM PDT 24
Peak memory 208960 kb
Host smart-08f01ae4-63c4-4c81-9446-f0d43cd28388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447817862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.447817862
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2453032823
Short name T862
Test name
Test status
Simulation time 48376939 ps
CPU time 2.84 seconds
Started Mar 28 01:29:21 PM PDT 24
Finished Mar 28 01:29:24 PM PDT 24
Peak memory 207216 kb
Host smart-c3d42233-fdc0-482e-9ee7-20b454ef3ac0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453032823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2453032823
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2742622466
Short name T195
Test name
Test status
Simulation time 199495844 ps
CPU time 6.82 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:31 PM PDT 24
Peak memory 209020 kb
Host smart-813de49b-262d-46ba-bda7-1c7c581c06ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742622466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2742622466
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2348206895
Short name T503
Test name
Test status
Simulation time 1411082274 ps
CPU time 17.08 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:43 PM PDT 24
Peak memory 209380 kb
Host smart-88522678-3745-4ec1-b7a8-2afb34bf65e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348206895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2348206895
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.289458371
Short name T895
Test name
Test status
Simulation time 50799856 ps
CPU time 2.5 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 208068 kb
Host smart-5d3fbf0c-6089-43bf-858a-f0733740497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289458371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.289458371
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3666552881
Short name T138
Test name
Test status
Simulation time 1003230438 ps
CPU time 19.23 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 223128 kb
Host smart-707a0306-81be-4ec3-83bf-7ac61421b611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666552881 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3666552881
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2122852734
Short name T366
Test name
Test status
Simulation time 114570482 ps
CPU time 5.78 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:31 PM PDT 24
Peak memory 218568 kb
Host smart-60976d26-ef50-42bc-8df7-9b3def7652eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122852734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2122852734
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3991984531
Short name T139
Test name
Test status
Simulation time 206945481 ps
CPU time 5.59 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 211032 kb
Host smart-c7143cfa-76d4-4f65-91ed-4e1c8fa53fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991984531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3991984531
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3289562582
Short name T450
Test name
Test status
Simulation time 35053552 ps
CPU time 0.87 seconds
Started Mar 28 01:27:07 PM PDT 24
Finished Mar 28 01:27:08 PM PDT 24
Peak memory 206268 kb
Host smart-545930e1-92f8-4060-b332-040ac4743a34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289562582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3289562582
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2719849838
Short name T378
Test name
Test status
Simulation time 157716522 ps
CPU time 8.92 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:10 PM PDT 24
Peak memory 214580 kb
Host smart-24f81c92-df3c-4ff7-98ce-11ac43e4ddd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2719849838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2719849838
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.420367598
Short name T822
Test name
Test status
Simulation time 92442609 ps
CPU time 2.46 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:03 PM PDT 24
Peak memory 208328 kb
Host smart-dcf60f82-4f47-4628-a6be-93f004b80d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420367598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.420367598
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3352171891
Short name T96
Test name
Test status
Simulation time 40009171 ps
CPU time 2.84 seconds
Started Mar 28 01:27:03 PM PDT 24
Finished Mar 28 01:27:06 PM PDT 24
Peak memory 209908 kb
Host smart-93349df2-d162-46f7-aa43-56d5921720c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352171891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3352171891
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4180059986
Short name T230
Test name
Test status
Simulation time 496265050 ps
CPU time 6.14 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 222700 kb
Host smart-b13713e7-3bc5-4df7-9a12-bfba555fb601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180059986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4180059986
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3468193683
Short name T678
Test name
Test status
Simulation time 154364052 ps
CPU time 2.84 seconds
Started Mar 28 01:27:02 PM PDT 24
Finished Mar 28 01:27:05 PM PDT 24
Peak memory 209672 kb
Host smart-eb04ad10-c4fc-4d38-a6ce-0386dc73d4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468193683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3468193683
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3073945730
Short name T545
Test name
Test status
Simulation time 95106435 ps
CPU time 5.12 seconds
Started Mar 28 01:27:02 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 207756 kb
Host smart-1c1b56e9-58c5-4f85-8805-62dab665d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073945730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3073945730
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.401755934
Short name T100
Test name
Test status
Simulation time 3553576968 ps
CPU time 20.02 seconds
Started Mar 28 01:27:09 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 233868 kb
Host smart-77288b13-e574-4e91-9261-3b88d3d17dd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401755934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.401755934
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2036344089
Short name T676
Test name
Test status
Simulation time 76694425 ps
CPU time 2.66 seconds
Started Mar 28 01:27:08 PM PDT 24
Finished Mar 28 01:27:12 PM PDT 24
Peak memory 209192 kb
Host smart-b16d173b-473f-4419-aa07-a3c5244efe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036344089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2036344089
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3311936313
Short name T824
Test name
Test status
Simulation time 4025747716 ps
CPU time 43.24 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:28:07 PM PDT 24
Peak memory 208272 kb
Host smart-67d7a45b-9421-42a1-99a5-be0c07c27684
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311936313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3311936313
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1552831774
Short name T683
Test name
Test status
Simulation time 217798554 ps
CPU time 6.71 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:13 PM PDT 24
Peak memory 208116 kb
Host smart-9e049a41-8687-4271-a304-a1e4035fa8d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552831774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1552831774
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.362317686
Short name T268
Test name
Test status
Simulation time 288158949 ps
CPU time 6.26 seconds
Started Mar 28 01:27:08 PM PDT 24
Finished Mar 28 01:27:15 PM PDT 24
Peak memory 208840 kb
Host smart-9af0006e-e354-4863-9c51-9900c4fb4c77
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362317686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.362317686
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3823014457
Short name T813
Test name
Test status
Simulation time 178070844 ps
CPU time 2.55 seconds
Started Mar 28 01:27:07 PM PDT 24
Finished Mar 28 01:27:09 PM PDT 24
Peak memory 207892 kb
Host smart-5b39784a-b74c-49af-bfb7-693627c64eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823014457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3823014457
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1961040523
Short name T435
Test name
Test status
Simulation time 2501075832 ps
CPU time 16.14 seconds
Started Mar 28 01:27:03 PM PDT 24
Finished Mar 28 01:27:19 PM PDT 24
Peak memory 209220 kb
Host smart-8b668924-0293-4b93-883c-388a1353a9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961040523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1961040523
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1092292970
Short name T649
Test name
Test status
Simulation time 203175666 ps
CPU time 8.27 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:15 PM PDT 24
Peak memory 220588 kb
Host smart-4628c636-55b4-4323-a159-84689f8b8f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092292970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1092292970
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.196680968
Short name T829
Test name
Test status
Simulation time 132986545 ps
CPU time 6.26 seconds
Started Mar 28 01:27:04 PM PDT 24
Finished Mar 28 01:27:11 PM PDT 24
Peak memory 210272 kb
Host smart-0c4ce45e-635e-40c2-9e8e-602cc4ba76a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196680968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.196680968
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1557073565
Short name T36
Test name
Test status
Simulation time 109245915 ps
CPU time 1.88 seconds
Started Mar 28 01:27:07 PM PDT 24
Finished Mar 28 01:27:09 PM PDT 24
Peak memory 210200 kb
Host smart-e64250b3-15d7-404b-8dc4-39e4972e6b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557073565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1557073565
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.647104341
Short name T463
Test name
Test status
Simulation time 235701630 ps
CPU time 0.95 seconds
Started Mar 28 01:29:23 PM PDT 24
Finished Mar 28 01:29:24 PM PDT 24
Peak memory 206256 kb
Host smart-3578c564-b10b-4c74-9cc7-419f0dbe5a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647104341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.647104341
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3332426456
Short name T271
Test name
Test status
Simulation time 979647403 ps
CPU time 4.53 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:30 PM PDT 24
Peak memory 215568 kb
Host smart-93c31d44-26a0-4c1e-86cc-3ce2325cb759
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332426456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3332426456
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1599593523
Short name T249
Test name
Test status
Simulation time 299974012 ps
CPU time 3.99 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:29:31 PM PDT 24
Peak memory 208228 kb
Host smart-09172649-78e3-4f26-963d-4a666e645b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599593523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1599593523
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.223239635
Short name T551
Test name
Test status
Simulation time 835110182 ps
CPU time 3.77 seconds
Started Mar 28 01:29:22 PM PDT 24
Finished Mar 28 01:29:27 PM PDT 24
Peak memory 218644 kb
Host smart-44e1ad0b-70b0-44cc-be91-4b210599c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223239635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.223239635
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.697882410
Short name T396
Test name
Test status
Simulation time 971445209 ps
CPU time 7.33 seconds
Started Mar 28 01:29:22 PM PDT 24
Finished Mar 28 01:29:31 PM PDT 24
Peak memory 210088 kb
Host smart-55827441-fced-40cf-9f1c-3d212a3b0a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697882410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.697882410
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2497825962
Short name T888
Test name
Test status
Simulation time 2278183335 ps
CPU time 20.05 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 222856 kb
Host smart-11fbc089-d368-425a-8277-a62bd6f0fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497825962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2497825962
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1521622438
Short name T891
Test name
Test status
Simulation time 182313913 ps
CPU time 2.07 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:29:28 PM PDT 24
Peak memory 214700 kb
Host smart-ba0f1347-386c-4cbc-aacb-df83662eca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521622438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1521622438
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3518528428
Short name T501
Test name
Test status
Simulation time 2107971523 ps
CPU time 49.79 seconds
Started Mar 28 01:29:24 PM PDT 24
Finished Mar 28 01:30:15 PM PDT 24
Peak memory 209980 kb
Host smart-270116e6-17f1-46d8-ba58-22bbf4f8eac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518528428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3518528428
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3621850110
Short name T789
Test name
Test status
Simulation time 3608022435 ps
CPU time 70.48 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:30:37 PM PDT 24
Peak memory 208764 kb
Host smart-f8dcd4e0-5fb9-4914-9d14-578fbba67524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621850110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3621850110
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2266540578
Short name T347
Test name
Test status
Simulation time 124418950 ps
CPU time 4.49 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:31 PM PDT 24
Peak memory 207136 kb
Host smart-06d5a2b6-0446-4cea-8d8a-9adde31fb027
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266540578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2266540578
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2101790765
Short name T504
Test name
Test status
Simulation time 201311051 ps
CPU time 1.8 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 207108 kb
Host smart-41edb39e-b73f-4900-ab91-710aa4cdf98c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101790765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2101790765
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1302177765
Short name T599
Test name
Test status
Simulation time 75200977 ps
CPU time 2.47 seconds
Started Mar 28 01:29:25 PM PDT 24
Finished Mar 28 01:29:28 PM PDT 24
Peak memory 207160 kb
Host smart-3ba08e1b-ee99-45ff-a29e-2df988d30ec6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302177765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1302177765
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1273455911
Short name T536
Test name
Test status
Simulation time 270465746 ps
CPU time 2.14 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 214612 kb
Host smart-047ba706-a2ff-4070-9521-229ee09eed74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273455911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1273455911
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1868506842
Short name T449
Test name
Test status
Simulation time 204941403 ps
CPU time 4.21 seconds
Started Mar 28 01:29:28 PM PDT 24
Finished Mar 28 01:29:32 PM PDT 24
Peak memory 209108 kb
Host smart-b3b45dbd-2ef3-46ed-9419-b73fefcb96d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868506842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1868506842
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.55079712
Short name T326
Test name
Test status
Simulation time 315461635 ps
CPU time 13.59 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:29:41 PM PDT 24
Peak memory 216624 kb
Host smart-b4fa8f57-61e9-4aa1-a122-1e16a475ce20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55079712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.55079712
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2316381669
Short name T858
Test name
Test status
Simulation time 93843038 ps
CPU time 3.46 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:29:31 PM PDT 24
Peak memory 210156 kb
Host smart-88c48499-efe4-4c30-93a6-80bd275f83da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316381669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2316381669
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2297506351
Short name T439
Test name
Test status
Simulation time 13763689 ps
CPU time 0.77 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:43 PM PDT 24
Peak memory 206260 kb
Host smart-b8810f43-f167-4c60-95ef-a1e054b9be4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297506351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2297506351
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1728431091
Short name T352
Test name
Test status
Simulation time 1062045772 ps
CPU time 4.97 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:29:32 PM PDT 24
Peak memory 214692 kb
Host smart-29ea3182-3c17-4adc-9f0c-b3ea630895dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728431091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1728431091
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1949201048
Short name T74
Test name
Test status
Simulation time 133559004 ps
CPU time 2.09 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 209572 kb
Host smart-60063052-2dbe-448a-8fe7-2c818549f8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949201048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1949201048
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1703531981
Short name T90
Test name
Test status
Simulation time 172913678 ps
CPU time 6.27 seconds
Started Mar 28 01:29:38 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 209192 kb
Host smart-ee83b573-53e1-4375-aa13-7d3f9ec62535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703531981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1703531981
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2522545436
Short name T595
Test name
Test status
Simulation time 207052208 ps
CPU time 5.72 seconds
Started Mar 28 01:29:39 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 214600 kb
Host smart-e7446c22-47fa-4426-8e1b-033fbb711d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522545436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2522545436
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.663167866
Short name T814
Test name
Test status
Simulation time 159528457 ps
CPU time 3.76 seconds
Started Mar 28 01:29:38 PM PDT 24
Finished Mar 28 01:29:42 PM PDT 24
Peak memory 220820 kb
Host smart-be6ba5f8-3df2-4f66-8e46-b5c706ba6019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663167866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.663167866
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2321894896
Short name T672
Test name
Test status
Simulation time 32532074 ps
CPU time 2.57 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 207860 kb
Host smart-b1d1d9f6-16b8-4d79-a213-2266d9843aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321894896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2321894896
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.4138361902
Short name T834
Test name
Test status
Simulation time 84879507 ps
CPU time 3.92 seconds
Started Mar 28 01:29:27 PM PDT 24
Finished Mar 28 01:29:31 PM PDT 24
Peak memory 208820 kb
Host smart-974bb13e-21f6-4972-bb01-01f002255bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138361902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.4138361902
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2955074708
Short name T633
Test name
Test status
Simulation time 214919746 ps
CPU time 2.36 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 207540 kb
Host smart-6a80f3e9-2a74-4dd4-808c-123cfc438bc3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955074708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2955074708
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.605540058
Short name T332
Test name
Test status
Simulation time 175214753 ps
CPU time 5.65 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:32 PM PDT 24
Peak memory 209020 kb
Host smart-d3b8a2ea-ed13-4cc9-b028-0e2094dddfa4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605540058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.605540058
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3468584988
Short name T284
Test name
Test status
Simulation time 61591004 ps
CPU time 3.05 seconds
Started Mar 28 01:29:26 PM PDT 24
Finished Mar 28 01:29:29 PM PDT 24
Peak memory 207152 kb
Host smart-6de5af43-7d82-4bff-8a0d-dff77a30a48e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468584988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3468584988
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2763443601
Short name T286
Test name
Test status
Simulation time 194243336 ps
CPU time 2.38 seconds
Started Mar 28 01:29:39 PM PDT 24
Finished Mar 28 01:29:42 PM PDT 24
Peak memory 216200 kb
Host smart-c7a431eb-556d-4c17-8fa0-1bdca41bc073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763443601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2763443601
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.7770013
Short name T887
Test name
Test status
Simulation time 2513007600 ps
CPU time 15.93 seconds
Started Mar 28 01:29:28 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 208272 kb
Host smart-ba7d95cd-5c91-4c1b-b0b8-45fbb528e0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7770013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.7770013
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.571404219
Short name T188
Test name
Test status
Simulation time 402874796 ps
CPU time 15.67 seconds
Started Mar 28 01:29:40 PM PDT 24
Finished Mar 28 01:29:55 PM PDT 24
Peak memory 223020 kb
Host smart-54656817-edd0-4fef-92eb-0fd25ac707c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571404219 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.571404219
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.673407432
Short name T761
Test name
Test status
Simulation time 57117664 ps
CPU time 3.54 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:47 PM PDT 24
Peak memory 214572 kb
Host smart-0e2280b4-651f-44d9-8bd6-5b981834de5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673407432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.673407432
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2460704296
Short name T575
Test name
Test status
Simulation time 58834114 ps
CPU time 2.06 seconds
Started Mar 28 01:29:35 PM PDT 24
Finished Mar 28 01:29:38 PM PDT 24
Peak memory 210300 kb
Host smart-acfd3f10-859a-4410-a57e-91a2d30cc691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460704296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2460704296
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.512545327
Short name T859
Test name
Test status
Simulation time 25418678 ps
CPU time 0.77 seconds
Started Mar 28 01:29:40 PM PDT 24
Finished Mar 28 01:29:40 PM PDT 24
Peak memory 206324 kb
Host smart-a51ef8ea-fe0b-42cd-aa2b-1b41a9679641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512545327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.512545327
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.283044832
Short name T155
Test name
Test status
Simulation time 55851403 ps
CPU time 4.25 seconds
Started Mar 28 01:29:45 PM PDT 24
Finished Mar 28 01:29:49 PM PDT 24
Peak memory 215764 kb
Host smart-3c7b8875-8896-487f-9883-109d17014c09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283044832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.283044832
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1290066775
Short name T517
Test name
Test status
Simulation time 268449488 ps
CPU time 3.08 seconds
Started Mar 28 01:29:40 PM PDT 24
Finished Mar 28 01:29:43 PM PDT 24
Peak memory 210404 kb
Host smart-124a49c7-8e7d-456f-b986-1c9b8a1dd498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290066775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1290066775
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3503131854
Short name T845
Test name
Test status
Simulation time 373052468 ps
CPU time 4.71 seconds
Started Mar 28 01:29:40 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 214600 kb
Host smart-fbadc9ab-d612-48b5-8515-6c06dcea6b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503131854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3503131854
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.197790681
Short name T631
Test name
Test status
Simulation time 111108763 ps
CPU time 3.42 seconds
Started Mar 28 01:29:40 PM PDT 24
Finished Mar 28 01:29:43 PM PDT 24
Peak memory 210012 kb
Host smart-416d8c04-ab09-413f-ac34-d0576f6ad9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197790681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.197790681
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2076847841
Short name T263
Test name
Test status
Simulation time 2128314397 ps
CPU time 11.21 seconds
Started Mar 28 01:29:40 PM PDT 24
Finished Mar 28 01:29:52 PM PDT 24
Peak memory 209072 kb
Host smart-6bb1b634-1b90-45ba-82c8-7c662b3ec26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076847841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2076847841
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1297405610
Short name T280
Test name
Test status
Simulation time 296107370 ps
CPU time 3.43 seconds
Started Mar 28 01:29:39 PM PDT 24
Finished Mar 28 01:29:42 PM PDT 24
Peak memory 208896 kb
Host smart-52a9edf9-cf9b-440d-a910-355affaece78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297405610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1297405610
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2009433998
Short name T617
Test name
Test status
Simulation time 177071811 ps
CPU time 5.47 seconds
Started Mar 28 01:29:37 PM PDT 24
Finished Mar 28 01:29:42 PM PDT 24
Peak memory 208272 kb
Host smart-8afc2812-65f3-4566-8f8a-e2766bc8b7c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009433998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2009433998
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1721962877
Short name T17
Test name
Test status
Simulation time 46936716 ps
CPU time 2.79 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 207208 kb
Host smart-d03b9655-ad52-4105-b2bb-55ab963772fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721962877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1721962877
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2612300070
Short name T820
Test name
Test status
Simulation time 132936240 ps
CPU time 4.75 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:29:46 PM PDT 24
Peak memory 209116 kb
Host smart-79585a04-ca7a-4ec0-8978-54fa33d1c7fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612300070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2612300070
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4043784292
Short name T576
Test name
Test status
Simulation time 572202167 ps
CPU time 4.07 seconds
Started Mar 28 01:29:39 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 210084 kb
Host smart-47d4c0d6-449a-4cd3-b09c-fb60ef571039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043784292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4043784292
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2084235890
Short name T836
Test name
Test status
Simulation time 1847932719 ps
CPU time 40.08 seconds
Started Mar 28 01:29:38 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 209140 kb
Host smart-1f32a83f-991a-4428-a17f-1f33e2148c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084235890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2084235890
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1278035246
Short name T342
Test name
Test status
Simulation time 1269693060 ps
CPU time 40.96 seconds
Started Mar 28 01:29:38 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 215476 kb
Host smart-d5b4ee80-ca04-4abf-906f-de57498c30f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278035246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1278035246
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.873200726
Short name T141
Test name
Test status
Simulation time 133810177 ps
CPU time 5.54 seconds
Started Mar 28 01:29:40 PM PDT 24
Finished Mar 28 01:29:46 PM PDT 24
Peak memory 207796 kb
Host smart-023ccf73-cb70-42b6-9442-2536957a61e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873200726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.873200726
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2094143190
Short name T584
Test name
Test status
Simulation time 49631633 ps
CPU time 1.96 seconds
Started Mar 28 01:29:39 PM PDT 24
Finished Mar 28 01:29:41 PM PDT 24
Peak memory 210448 kb
Host smart-a2a5220e-a039-4456-8799-9ac979fd5971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094143190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2094143190
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3608110298
Short name T98
Test name
Test status
Simulation time 53630970 ps
CPU time 0.85 seconds
Started Mar 28 01:29:36 PM PDT 24
Finished Mar 28 01:29:37 PM PDT 24
Peak memory 206244 kb
Host smart-39762674-f695-4de6-9eaa-3502e1079969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608110298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3608110298
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3847816211
Short name T433
Test name
Test status
Simulation time 661635372 ps
CPU time 6.08 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:29:48 PM PDT 24
Peak memory 214512 kb
Host smart-adfad23e-c73a-4900-b405-e45aa0a6ccc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847816211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3847816211
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1638094954
Short name T31
Test name
Test status
Simulation time 648508625 ps
CPU time 5.49 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:29:47 PM PDT 24
Peak memory 218716 kb
Host smart-8928c646-267a-4563-8310-cb1008891f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638094954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1638094954
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2322054486
Short name T763
Test name
Test status
Simulation time 107125727 ps
CPU time 3.11 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 208400 kb
Host smart-ca27f487-d5d5-443e-8b16-4cefdad8a909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322054486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2322054486
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2910077846
Short name T398
Test name
Test status
Simulation time 252275071 ps
CPU time 3.8 seconds
Started Mar 28 01:29:37 PM PDT 24
Finished Mar 28 01:29:41 PM PDT 24
Peak memory 209340 kb
Host smart-e0841b09-d7c4-491e-8605-0d3c97277981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910077846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2910077846
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.691929625
Short name T218
Test name
Test status
Simulation time 419222599 ps
CPU time 9.39 seconds
Started Mar 28 01:29:39 PM PDT 24
Finished Mar 28 01:29:49 PM PDT 24
Peak memory 214416 kb
Host smart-9a0acf4a-b187-4ff4-acda-ad0cf8947d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691929625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.691929625
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1030346366
Short name T148
Test name
Test status
Simulation time 2248633636 ps
CPU time 9.1 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:52 PM PDT 24
Peak memory 223100 kb
Host smart-ea6aa8b5-d282-4fde-bc6e-4cd562c29d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030346366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1030346366
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2657737683
Short name T652
Test name
Test status
Simulation time 116718960 ps
CPU time 4.58 seconds
Started Mar 28 01:29:45 PM PDT 24
Finished Mar 28 01:29:49 PM PDT 24
Peak memory 209896 kb
Host smart-266f54ed-aa64-4c01-8428-3a8dce3f3931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657737683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2657737683
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.703084678
Short name T844
Test name
Test status
Simulation time 403603864 ps
CPU time 6.87 seconds
Started Mar 28 01:29:45 PM PDT 24
Finished Mar 28 01:29:51 PM PDT 24
Peak memory 207112 kb
Host smart-37eda013-9cb6-410d-a03e-72c0a02ce37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703084678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.703084678
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2132038067
Short name T765
Test name
Test status
Simulation time 263764305 ps
CPU time 3.38 seconds
Started Mar 28 01:29:36 PM PDT 24
Finished Mar 28 01:29:40 PM PDT 24
Peak memory 209248 kb
Host smart-be7b3709-b260-44cb-90e7-dd284bc3897d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132038067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2132038067
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.338547430
Short name T815
Test name
Test status
Simulation time 112748833 ps
CPU time 3.09 seconds
Started Mar 28 01:29:36 PM PDT 24
Finished Mar 28 01:29:39 PM PDT 24
Peak memory 208808 kb
Host smart-3a9b80ca-fb67-4c3d-8c58-0b9bc2b9a271
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338547430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.338547430
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2988339186
Short name T655
Test name
Test status
Simulation time 1047454148 ps
CPU time 8.14 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:50 PM PDT 24
Peak memory 208808 kb
Host smart-d1b867c8-b8ad-4e2e-b44c-b8d1dc179622
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988339186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2988339186
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3557447929
Short name T800
Test name
Test status
Simulation time 232321073 ps
CPU time 3.98 seconds
Started Mar 28 01:29:36 PM PDT 24
Finished Mar 28 01:29:40 PM PDT 24
Peak memory 218844 kb
Host smart-8c7a371f-cee1-4510-a59e-6c8e82dca8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557447929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3557447929
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.455608474
Short name T15
Test name
Test status
Simulation time 2640177789 ps
CPU time 8.56 seconds
Started Mar 28 01:29:39 PM PDT 24
Finished Mar 28 01:29:48 PM PDT 24
Peak memory 207056 kb
Host smart-3a3d7e02-2822-4026-998c-ab0a1a47cea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455608474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.455608474
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.818697104
Short name T192
Test name
Test status
Simulation time 359587368 ps
CPU time 11.49 seconds
Started Mar 28 01:29:38 PM PDT 24
Finished Mar 28 01:29:50 PM PDT 24
Peak memory 222920 kb
Host smart-a8d51e78-9de0-4ec2-afe0-6b7a5f847c47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818697104 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.818697104
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.903191810
Short name T885
Test name
Test status
Simulation time 647586664 ps
CPU time 9.22 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:29:53 PM PDT 24
Peak memory 214744 kb
Host smart-7c4a4b5e-3ae6-4bf3-971d-035ffbcb0d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903191810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.903191810
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1831745406
Short name T711
Test name
Test status
Simulation time 223108481 ps
CPU time 1.89 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 210208 kb
Host smart-224f630b-b1ad-41b5-9cec-c2f49e0823df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831745406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1831745406
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2656232612
Short name T486
Test name
Test status
Simulation time 15397277 ps
CPU time 0.81 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 206292 kb
Host smart-9b0df7b1-3a71-4ad5-8227-0811b16a8d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656232612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2656232612
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2803198700
Short name T19
Test name
Test status
Simulation time 120723391 ps
CPU time 2.82 seconds
Started Mar 28 01:29:45 PM PDT 24
Finished Mar 28 01:29:48 PM PDT 24
Peak memory 222172 kb
Host smart-0a44b2ba-3976-40f4-ac37-f0f2266ab5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803198700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2803198700
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2715298275
Short name T338
Test name
Test status
Simulation time 219130321 ps
CPU time 2.94 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 214700 kb
Host smart-5d2a50f6-3ef8-4722-99c9-f164ead416d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715298275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2715298275
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1213806665
Short name T94
Test name
Test status
Simulation time 222043709 ps
CPU time 6.1 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:29:50 PM PDT 24
Peak memory 209548 kb
Host smart-7d22620c-3106-46ea-abd2-2c28a00c38ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213806665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1213806665
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3212335981
Short name T461
Test name
Test status
Simulation time 100803008 ps
CPU time 3.13 seconds
Started Mar 28 01:29:46 PM PDT 24
Finished Mar 28 01:29:49 PM PDT 24
Peak memory 209204 kb
Host smart-d2d6f511-b539-4ba8-bcff-5ef6c09a10a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212335981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3212335981
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.809467064
Short name T307
Test name
Test status
Simulation time 2745838311 ps
CPU time 54.96 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:30:40 PM PDT 24
Peak memory 209860 kb
Host smart-fb41d9b7-281d-43be-b383-b2e02f599731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809467064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.809467064
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.4241944655
Short name T301
Test name
Test status
Simulation time 58168327 ps
CPU time 3.03 seconds
Started Mar 28 01:29:36 PM PDT 24
Finished Mar 28 01:29:40 PM PDT 24
Peak memory 208560 kb
Host smart-5b2c4305-5566-4e82-b6ce-fa04b66aba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241944655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.4241944655
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1297494371
Short name T440
Test name
Test status
Simulation time 558478733 ps
CPU time 7.86 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:50 PM PDT 24
Peak memory 208852 kb
Host smart-1445fa24-9cce-4b8b-b181-af602b6a0f22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297494371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1297494371
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2540376870
Short name T594
Test name
Test status
Simulation time 1885531228 ps
CPU time 15.02 seconds
Started Mar 28 01:29:45 PM PDT 24
Finished Mar 28 01:30:00 PM PDT 24
Peak memory 208884 kb
Host smart-1c0a999d-8fb3-4d2c-be4b-cf3bd5eccc54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540376870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2540376870
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.317563710
Short name T445
Test name
Test status
Simulation time 131917072 ps
CPU time 5.04 seconds
Started Mar 28 01:29:40 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 207176 kb
Host smart-895a9332-2f79-4baf-b376-4227ab9ec05e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317563710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.317563710
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2112849594
Short name T521
Test name
Test status
Simulation time 78590860 ps
CPU time 2.97 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 210512 kb
Host smart-f3bbd6cb-392f-4587-829c-91c68d59b93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112849594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2112849594
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.540778514
Short name T786
Test name
Test status
Simulation time 139976480 ps
CPU time 2.77 seconds
Started Mar 28 01:29:40 PM PDT 24
Finished Mar 28 01:29:43 PM PDT 24
Peak memory 208760 kb
Host smart-117922d5-4d92-4277-8388-1364e05e6e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540778514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.540778514
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4134689373
Short name T880
Test name
Test status
Simulation time 21751234885 ps
CPU time 143.72 seconds
Started Mar 28 01:29:41 PM PDT 24
Finished Mar 28 01:32:05 PM PDT 24
Peak memory 219636 kb
Host smart-eda77cc2-3352-4b6f-b261-976f915dbca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134689373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4134689373
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2645173693
Short name T376
Test name
Test status
Simulation time 240882270 ps
CPU time 3.49 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:29:48 PM PDT 24
Peak memory 207952 kb
Host smart-67fb0d62-8237-4a9a-aa23-19fc58aab64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645173693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2645173693
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2629057076
Short name T559
Test name
Test status
Simulation time 49677534 ps
CPU time 1.96 seconds
Started Mar 28 01:29:46 PM PDT 24
Finished Mar 28 01:29:48 PM PDT 24
Peak memory 210592 kb
Host smart-2ce64118-5f4d-4772-8999-70dad652afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629057076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2629057076
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3225277555
Short name T490
Test name
Test status
Simulation time 9398498 ps
CPU time 0.72 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 206320 kb
Host smart-a631173a-7c7a-4f31-b813-f860d6076b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225277555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3225277555
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3991977986
Short name T29
Test name
Test status
Simulation time 167167595 ps
CPU time 6.11 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:50 PM PDT 24
Peak memory 222276 kb
Host smart-5aeb8288-6c60-48b7-80fb-9184bff2ae3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991977986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3991977986
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2960621340
Short name T794
Test name
Test status
Simulation time 289117880 ps
CPU time 3.49 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:29:51 PM PDT 24
Peak memory 207516 kb
Host smart-f68de17c-8524-4025-b693-1f7bc1e4cbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960621340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2960621340
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2726427779
Short name T615
Test name
Test status
Simulation time 495582646 ps
CPU time 5.74 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:49 PM PDT 24
Peak memory 220740 kb
Host smart-fe6464cd-467d-4771-8a64-e5989c6955dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726427779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2726427779
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3918559943
Short name T95
Test name
Test status
Simulation time 1164090870 ps
CPU time 21.61 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:30:09 PM PDT 24
Peak memory 211860 kb
Host smart-6dc0de01-64d3-4ad9-b99c-2acb7e45b073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918559943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3918559943
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3582834156
Short name T745
Test name
Test status
Simulation time 531498512 ps
CPU time 4.71 seconds
Started Mar 28 01:29:48 PM PDT 24
Finished Mar 28 01:29:53 PM PDT 24
Peak memory 220480 kb
Host smart-fdffbef6-33a6-46bc-b473-465d9c02e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582834156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3582834156
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.4093220219
Short name T661
Test name
Test status
Simulation time 175455895 ps
CPU time 4.84 seconds
Started Mar 28 01:29:48 PM PDT 24
Finished Mar 28 01:29:53 PM PDT 24
Peak memory 210044 kb
Host smart-488e0d7e-cc47-4cfb-81f9-3d47e2ab856a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093220219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.4093220219
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3090924762
Short name T723
Test name
Test status
Simulation time 106255738 ps
CPU time 4.59 seconds
Started Mar 28 01:29:37 PM PDT 24
Finished Mar 28 01:29:42 PM PDT 24
Peak memory 209236 kb
Host smart-30bb027a-35c1-4c17-8dd3-d5310e1da483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090924762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3090924762
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3317950098
Short name T605
Test name
Test status
Simulation time 2065821131 ps
CPU time 25.59 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:30:08 PM PDT 24
Peak memory 208408 kb
Host smart-c0544ee9-1686-40e2-b7e9-2ddb71fd3cdc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317950098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3317950098
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1624822129
Short name T667
Test name
Test status
Simulation time 1843435819 ps
CPU time 44.16 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:30:26 PM PDT 24
Peak memory 208932 kb
Host smart-bd84d9bb-de2d-4670-af87-ccd313ce7035
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624822129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1624822129
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3997713821
Short name T482
Test name
Test status
Simulation time 31747952 ps
CPU time 1.83 seconds
Started Mar 28 01:29:48 PM PDT 24
Finished Mar 28 01:29:50 PM PDT 24
Peak memory 207176 kb
Host smart-ba333f22-9f75-4d0c-88bb-e993210f61e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997713821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3997713821
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1267696271
Short name T498
Test name
Test status
Simulation time 76777400 ps
CPU time 2.75 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:29:47 PM PDT 24
Peak memory 218728 kb
Host smart-f03ebc4a-da69-42d2-aa9c-fd3f482dc081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267696271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1267696271
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1060338762
Short name T512
Test name
Test status
Simulation time 144869468 ps
CPU time 4.69 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:47 PM PDT 24
Peak memory 206924 kb
Host smart-526065d2-d6fe-4a22-bc69-9a1b943c74f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060338762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1060338762
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.4083230262
Short name T334
Test name
Test status
Simulation time 4709576890 ps
CPU time 57.45 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:30:41 PM PDT 24
Peak memory 217468 kb
Host smart-34777158-e980-40eb-b7fa-7a7e37b7d524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083230262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.4083230262
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.4078272606
Short name T629
Test name
Test status
Simulation time 4865552124 ps
CPU time 30.16 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:30:18 PM PDT 24
Peak memory 209596 kb
Host smart-0722b5e1-7109-4175-b896-b997b2b563ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078272606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.4078272606
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1562485599
Short name T630
Test name
Test status
Simulation time 99832452 ps
CPU time 3.77 seconds
Started Mar 28 01:29:48 PM PDT 24
Finished Mar 28 01:29:52 PM PDT 24
Peak memory 210060 kb
Host smart-021c93f8-d6a4-4136-9cf5-ba4880b04105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562485599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1562485599
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1707572288
Short name T754
Test name
Test status
Simulation time 31193996 ps
CPU time 0.81 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 206352 kb
Host smart-7b1ac24b-0d1b-477c-9e8f-0b94262b1fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707572288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1707572288
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2892525103
Short name T658
Test name
Test status
Simulation time 123810278 ps
CPU time 4.09 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:29:52 PM PDT 24
Peak memory 218764 kb
Host smart-676bcc2b-1ec3-4b7b-8e95-4e45bbb144dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892525103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2892525103
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2233984233
Short name T566
Test name
Test status
Simulation time 221157389 ps
CPU time 6.11 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:29:54 PM PDT 24
Peak memory 207144 kb
Host smart-a6de0679-b5ae-441f-9f55-f6ee9e26a0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233984233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2233984233
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2328201441
Short name T645
Test name
Test status
Simulation time 1013140967 ps
CPU time 12.12 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:55 PM PDT 24
Peak memory 214580 kb
Host smart-141c5b54-1448-454f-a621-e9f4261cfbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328201441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2328201441
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1706335452
Short name T628
Test name
Test status
Simulation time 43423405 ps
CPU time 1.96 seconds
Started Mar 28 01:29:45 PM PDT 24
Finished Mar 28 01:29:47 PM PDT 24
Peak memory 210756 kb
Host smart-1fed1193-c3b2-41e2-a0c0-218411e9f6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706335452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1706335452
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2043981108
Short name T254
Test name
Test status
Simulation time 1042123261 ps
CPU time 3.65 seconds
Started Mar 28 01:29:45 PM PDT 24
Finished Mar 28 01:29:49 PM PDT 24
Peak memory 220656 kb
Host smart-e5616bdc-7451-41a7-b929-0621b3ff2d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043981108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2043981108
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.4027273239
Short name T806
Test name
Test status
Simulation time 289842118 ps
CPU time 6.84 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:50 PM PDT 24
Peak memory 210236 kb
Host smart-1d524e6f-f530-44da-838e-a4eba6fc0a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027273239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4027273239
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1451481436
Short name T204
Test name
Test status
Simulation time 114335442 ps
CPU time 2.65 seconds
Started Mar 28 01:29:48 PM PDT 24
Finished Mar 28 01:29:51 PM PDT 24
Peak memory 206960 kb
Host smart-b2f47691-b650-4cfd-843d-4d6a3a18469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451481436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1451481436
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2612303760
Short name T515
Test name
Test status
Simulation time 31675509 ps
CPU time 2.4 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 207016 kb
Host smart-c7594b66-6d39-4d67-9c6a-17e33ab74b42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612303760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2612303760
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1876990262
Short name T687
Test name
Test status
Simulation time 32188743 ps
CPU time 2.32 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 208720 kb
Host smart-dffb48c5-115d-432f-a2ce-dc6903356a68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876990262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1876990262
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.708496551
Short name T689
Test name
Test status
Simulation time 43634529 ps
CPU time 1.82 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 206992 kb
Host smart-3271879b-943c-4ac5-aeb0-5417c18428e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708496551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.708496551
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1428350786
Short name T506
Test name
Test status
Simulation time 68486816 ps
CPU time 3.43 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:29:51 PM PDT 24
Peak memory 210156 kb
Host smart-38f0ccd7-9400-4e4f-82f8-b96296726f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428350786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1428350786
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2357251525
Short name T1
Test name
Test status
Simulation time 74561687 ps
CPU time 2.93 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:29:46 PM PDT 24
Peak memory 207020 kb
Host smart-2ccd36e1-053c-4e33-9e90-7c6e70d895d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357251525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2357251525
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2565496746
Short name T373
Test name
Test status
Simulation time 706151786 ps
CPU time 15.12 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:30:03 PM PDT 24
Peak memory 207892 kb
Host smart-5c610415-24e0-4c1e-a9b8-c453e0bc19da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565496746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2565496746
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.173721366
Short name T270
Test name
Test status
Simulation time 5421651367 ps
CPU time 26.38 seconds
Started Mar 28 01:29:43 PM PDT 24
Finished Mar 28 01:30:10 PM PDT 24
Peak memory 223156 kb
Host smart-179fa829-c61a-47a7-9a6a-bdfe4de05dbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173721366 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.173721366
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1287774642
Short name T492
Test name
Test status
Simulation time 465109374 ps
CPU time 6.58 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:29:54 PM PDT 24
Peak memory 209836 kb
Host smart-a294325f-8773-4e59-b730-50c3613be8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287774642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1287774642
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.4253975718
Short name T540
Test name
Test status
Simulation time 1393834016 ps
CPU time 3.1 seconds
Started Mar 28 01:29:38 PM PDT 24
Finished Mar 28 01:29:41 PM PDT 24
Peak memory 210772 kb
Host smart-e6d68e70-a7d7-4371-9028-7995595eca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253975718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.4253975718
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.682966294
Short name T14
Test name
Test status
Simulation time 16362005 ps
CPU time 0.79 seconds
Started Mar 28 01:29:48 PM PDT 24
Finished Mar 28 01:29:49 PM PDT 24
Peak memory 206320 kb
Host smart-50ab87ee-6b95-4949-a40c-23058cbce3f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682966294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.682966294
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1043132574
Short name T432
Test name
Test status
Simulation time 260734631 ps
CPU time 4.34 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:29:48 PM PDT 24
Peak memory 215712 kb
Host smart-153e35f5-41a4-4caa-bef4-861f577a6957
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043132574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1043132574
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.281083920
Short name T393
Test name
Test status
Simulation time 37089139 ps
CPU time 2.61 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:44 PM PDT 24
Peak memory 218580 kb
Host smart-617a3b08-5cc6-4ea3-82fc-c27faaea24f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281083920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.281083920
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.534173092
Short name T196
Test name
Test status
Simulation time 53634005 ps
CPU time 2.65 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:29:50 PM PDT 24
Peak memory 214692 kb
Host smart-3d107c39-1010-4988-a428-44a78300d77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534173092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.534173092
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1318703890
Short name T826
Test name
Test status
Simulation time 194861369 ps
CPU time 4.12 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:29:48 PM PDT 24
Peak memory 214612 kb
Host smart-1f512f5b-b61e-4079-b1dc-b7ae9341d40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318703890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1318703890
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3090835803
Short name T772
Test name
Test status
Simulation time 104889512 ps
CPU time 3.08 seconds
Started Mar 28 01:29:47 PM PDT 24
Finished Mar 28 01:29:51 PM PDT 24
Peak memory 220544 kb
Host smart-9194c104-9d80-4049-b8de-25eb87285f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090835803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3090835803
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.58904100
Short name T876
Test name
Test status
Simulation time 3137836270 ps
CPU time 31.07 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:30:13 PM PDT 24
Peak memory 214840 kb
Host smart-94e6ed0b-0413-41cf-93ba-a988d0fb3cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58904100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.58904100
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.766772061
Short name T305
Test name
Test status
Simulation time 919998392 ps
CPU time 7.34 seconds
Started Mar 28 01:29:46 PM PDT 24
Finished Mar 28 01:29:54 PM PDT 24
Peak memory 209020 kb
Host smart-1a805f8c-c2f9-47e2-ba00-c51a73899af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766772061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.766772061
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2502349515
Short name T513
Test name
Test status
Simulation time 577023152 ps
CPU time 4.64 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:29:49 PM PDT 24
Peak memory 207044 kb
Host smart-d8931909-e00e-43f8-995b-515c7d52c709
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502349515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2502349515
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1634163800
Short name T673
Test name
Test status
Simulation time 214445010 ps
CPU time 2.88 seconds
Started Mar 28 01:29:42 PM PDT 24
Finished Mar 28 01:29:45 PM PDT 24
Peak memory 209068 kb
Host smart-7c8bc222-e0e8-4c52-a9ef-c15f7cab6ca4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634163800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1634163800
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1852533053
Short name T236
Test name
Test status
Simulation time 233726166 ps
CPU time 3.37 seconds
Started Mar 28 01:29:44 PM PDT 24
Finished Mar 28 01:29:48 PM PDT 24
Peak memory 207052 kb
Host smart-1cc60453-0fa6-4bc9-b8f7-b5384ff98bbf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852533053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1852533053
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3841965110
Short name T198
Test name
Test status
Simulation time 4042619670 ps
CPU time 40.15 seconds
Started Mar 28 01:29:37 PM PDT 24
Finished Mar 28 01:30:17 PM PDT 24
Peak memory 219984 kb
Host smart-79df6ba7-74f7-4dcf-9b04-f22291a253c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841965110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3841965110
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2636040618
Short name T839
Test name
Test status
Simulation time 3307556243 ps
CPU time 15.35 seconds
Started Mar 28 01:29:46 PM PDT 24
Finished Mar 28 01:30:02 PM PDT 24
Peak memory 209028 kb
Host smart-f00de5bb-55fb-4da3-bb95-4371f5bbade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636040618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2636040618
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2665996167
Short name T539
Test name
Test status
Simulation time 521559763 ps
CPU time 4.58 seconds
Started Mar 28 01:29:46 PM PDT 24
Finished Mar 28 01:29:51 PM PDT 24
Peak memory 209012 kb
Host smart-8e360ddf-6243-4562-86ef-3e93cdc5e7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665996167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2665996167
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4225539744
Short name T890
Test name
Test status
Simulation time 86277555 ps
CPU time 1.06 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:30:00 PM PDT 24
Peak memory 206532 kb
Host smart-7b367b83-32a4-4a9c-aba0-be9f48760169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225539744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4225539744
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3007055563
Short name T256
Test name
Test status
Simulation time 401231926 ps
CPU time 2.55 seconds
Started Mar 28 01:29:54 PM PDT 24
Finished Mar 28 01:29:57 PM PDT 24
Peak memory 215688 kb
Host smart-41663b29-9a5c-475d-9011-fedf011c7290
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007055563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3007055563
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.207982085
Short name T518
Test name
Test status
Simulation time 42437956 ps
CPU time 1.64 seconds
Started Mar 28 01:29:59 PM PDT 24
Finished Mar 28 01:30:01 PM PDT 24
Peak memory 209084 kb
Host smart-bd49de4e-7d85-4374-b3cf-d56b8d4e858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207982085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.207982085
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.4115549422
Short name T86
Test name
Test status
Simulation time 5400008351 ps
CPU time 32.18 seconds
Started Mar 28 01:29:57 PM PDT 24
Finished Mar 28 01:30:29 PM PDT 24
Peak memory 222956 kb
Host smart-86e609fc-857f-49f9-a40d-e90d1ac46150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115549422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.4115549422
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.508087871
Short name T878
Test name
Test status
Simulation time 396234046 ps
CPU time 3.44 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 218768 kb
Host smart-763eed49-599d-4b9d-9894-36aa3c9c93b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508087871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.508087871
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.613889753
Short name T488
Test name
Test status
Simulation time 3076965421 ps
CPU time 22.28 seconds
Started Mar 28 01:29:56 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 208580 kb
Host smart-83a9b66e-e5e0-49cc-a4bf-637a25edae8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613889753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.613889753
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3191472447
Short name T741
Test name
Test status
Simulation time 621974713 ps
CPU time 3.75 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:30:01 PM PDT 24
Peak memory 207060 kb
Host smart-12c16a05-6fee-4467-8b1c-93d68cf112ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191472447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3191472447
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2435276909
Short name T729
Test name
Test status
Simulation time 997077162 ps
CPU time 7.16 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:30:05 PM PDT 24
Peak memory 208412 kb
Host smart-0ca922b5-64e7-4255-a51b-f81a4f844555
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435276909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2435276909
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.331088852
Short name T546
Test name
Test status
Simulation time 1049089654 ps
CPU time 28.59 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:30:26 PM PDT 24
Peak memory 209276 kb
Host smart-d828a0cb-650f-45c4-bb81-e2c5a09d3c1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331088852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.331088852
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.787699921
Short name T276
Test name
Test status
Simulation time 120601352 ps
CPU time 3.21 seconds
Started Mar 28 01:29:57 PM PDT 24
Finished Mar 28 01:30:00 PM PDT 24
Peak memory 207612 kb
Host smart-cc4124f5-b9eb-4ca6-aec8-d6325c1a1256
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787699921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.787699921
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2537928221
Short name T422
Test name
Test status
Simulation time 356695110 ps
CPU time 2.95 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:30:01 PM PDT 24
Peak memory 216284 kb
Host smart-813f8f29-a9e4-4286-bda9-98a80f2aa281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537928221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2537928221
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1695440149
Short name T458
Test name
Test status
Simulation time 191320889 ps
CPU time 2.73 seconds
Started Mar 28 01:29:57 PM PDT 24
Finished Mar 28 01:30:00 PM PDT 24
Peak memory 206920 kb
Host smart-54e7fc32-7130-4af1-b5a5-3030cd647b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695440149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1695440149
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2632194120
Short name T7
Test name
Test status
Simulation time 16540089257 ps
CPU time 103.69 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:31:42 PM PDT 24
Peak memory 222736 kb
Host smart-d9bf0491-689c-4fed-803d-bc03af08b1e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632194120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2632194120
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.4071270214
Short name T191
Test name
Test status
Simulation time 545375739 ps
CPU time 20.03 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:30:22 PM PDT 24
Peak memory 223016 kb
Host smart-06acc33d-6722-4ee1-a551-20db279b4da9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071270214 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.4071270214
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1058201099
Short name T516
Test name
Test status
Simulation time 437655272 ps
CPU time 5.25 seconds
Started Mar 28 01:29:57 PM PDT 24
Finished Mar 28 01:30:02 PM PDT 24
Peak memory 208472 kb
Host smart-08dbefd9-c669-47c7-b163-690a87e1e75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058201099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1058201099
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1030519150
Short name T622
Test name
Test status
Simulation time 202346249 ps
CPU time 2.37 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:30:01 PM PDT 24
Peak memory 210324 kb
Host smart-10fac77c-b7ea-4919-a086-15388ad020b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030519150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1030519150
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2009142931
Short name T803
Test name
Test status
Simulation time 48303978 ps
CPU time 0.76 seconds
Started Mar 28 01:30:04 PM PDT 24
Finished Mar 28 01:30:05 PM PDT 24
Peak memory 206260 kb
Host smart-6d61d2f8-bb25-4535-8160-c54ddc8e6704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009142931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2009142931
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3220450487
Short name T39
Test name
Test status
Simulation time 2800488788 ps
CPU time 15.96 seconds
Started Mar 28 01:30:03 PM PDT 24
Finished Mar 28 01:30:19 PM PDT 24
Peak memory 220544 kb
Host smart-8c1dae55-362c-40da-99dc-422b8383cc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220450487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3220450487
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2787540481
Short name T360
Test name
Test status
Simulation time 240341640 ps
CPU time 3.12 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 207056 kb
Host smart-b064c173-19fc-4b07-a1e8-f655e25f76f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787540481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2787540481
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2531367791
Short name T775
Test name
Test status
Simulation time 57263518 ps
CPU time 2.99 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 216512 kb
Host smart-c2e73dcb-1dc7-4e7d-927e-1dd9855dbc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531367791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2531367791
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.578643705
Short name T208
Test name
Test status
Simulation time 2585563009 ps
CPU time 73.54 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:31:16 PM PDT 24
Peak memory 230252 kb
Host smart-d2d31ddb-837c-48d1-bb71-d5856ae0df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578643705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.578643705
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2559051501
Short name T69
Test name
Test status
Simulation time 48534542 ps
CPU time 3.65 seconds
Started Mar 28 01:30:00 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 208320 kb
Host smart-343158e8-bd65-4dc5-a179-43e91323a597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559051501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2559051501
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.4252617224
Short name T640
Test name
Test status
Simulation time 268744223 ps
CPU time 5.79 seconds
Started Mar 28 01:29:59 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 210168 kb
Host smart-06526c34-b053-48d0-b2c3-4a6dbaf3a9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252617224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.4252617224
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.262268305
Short name T896
Test name
Test status
Simulation time 681699513 ps
CPU time 3.67 seconds
Started Mar 28 01:30:00 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 207472 kb
Host smart-cb3c044e-d3d9-42e7-a0ae-0ad66d893623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262268305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.262268305
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.202111747
Short name T821
Test name
Test status
Simulation time 989523775 ps
CPU time 3.56 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:30:05 PM PDT 24
Peak memory 209140 kb
Host smart-12e3dec3-3632-46f7-b4a2-6d451df08307
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202111747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.202111747
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1734489910
Short name T448
Test name
Test status
Simulation time 97122218 ps
CPU time 3.6 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:30:06 PM PDT 24
Peak memory 207124 kb
Host smart-4471cade-de47-4606-bd32-550c924c01da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734489910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1734489910
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4280079906
Short name T193
Test name
Test status
Simulation time 187638905 ps
CPU time 7.98 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:30:06 PM PDT 24
Peak memory 208992 kb
Host smart-3752c8a7-7d70-4883-8006-4a83cdab2a47
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280079906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4280079906
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3419543633
Short name T323
Test name
Test status
Simulation time 69492360 ps
CPU time 3.3 seconds
Started Mar 28 01:30:01 PM PDT 24
Finished Mar 28 01:30:05 PM PDT 24
Peak memory 210468 kb
Host smart-7c734912-2060-47fc-b32d-450bf9104b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419543633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3419543633
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3672266832
Short name T565
Test name
Test status
Simulation time 43304874 ps
CPU time 2.36 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:30:04 PM PDT 24
Peak memory 206536 kb
Host smart-28a31a81-b61d-46d9-a8df-758cc5dff211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672266832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3672266832
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2448126278
Short name T321
Test name
Test status
Simulation time 17705665335 ps
CPU time 106.15 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:31:48 PM PDT 24
Peak memory 220552 kb
Host smart-a8457b75-8049-425e-9112-fb32169cd489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448126278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2448126278
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.461414573
Short name T894
Test name
Test status
Simulation time 1104699193 ps
CPU time 12.53 seconds
Started Mar 28 01:30:02 PM PDT 24
Finished Mar 28 01:30:14 PM PDT 24
Peak memory 207696 kb
Host smart-8550461d-24b7-4cb0-be59-c254ea8393bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461414573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.461414573
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3790616046
Short name T869
Test name
Test status
Simulation time 1177537667 ps
CPU time 18.5 seconds
Started Mar 28 01:29:58 PM PDT 24
Finished Mar 28 01:30:17 PM PDT 24
Peak memory 211824 kb
Host smart-0c04cb44-762d-4017-a6b0-051cc96b82ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790616046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3790616046
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4015898500
Short name T459
Test name
Test status
Simulation time 143748285 ps
CPU time 0.91 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:02 PM PDT 24
Peak memory 206284 kb
Host smart-50dd6ed0-6778-406b-b31e-1358563855ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015898500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4015898500
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3655115937
Short name T320
Test name
Test status
Simulation time 99168997 ps
CPU time 4.2 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:10 PM PDT 24
Peak memory 214704 kb
Host smart-4b597a1e-6ce7-44b5-92d1-70dd6c10c664
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655115937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3655115937
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1219418445
Short name T662
Test name
Test status
Simulation time 66424284 ps
CPU time 2.72 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:10 PM PDT 24
Peak memory 223216 kb
Host smart-9af8288a-8a8d-4ce4-bea7-79e56c0c970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219418445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1219418445
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3875875864
Short name T381
Test name
Test status
Simulation time 408571836 ps
CPU time 2.75 seconds
Started Mar 28 01:27:07 PM PDT 24
Finished Mar 28 01:27:10 PM PDT 24
Peak memory 208736 kb
Host smart-3789db22-59dc-4ffa-b800-a5756dc47675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875875864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3875875864
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.795331234
Short name T93
Test name
Test status
Simulation time 862031417 ps
CPU time 6.51 seconds
Started Mar 28 01:27:04 PM PDT 24
Finished Mar 28 01:27:12 PM PDT 24
Peak memory 214668 kb
Host smart-e4bb5289-66ca-4af5-94f6-0e5811cea3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795331234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.795331234
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4242279082
Short name T309
Test name
Test status
Simulation time 1275630299 ps
CPU time 11.26 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:16 PM PDT 24
Peak memory 211880 kb
Host smart-a803845f-6578-4d18-b4c2-b88b4d5750bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242279082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4242279082
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4222839747
Short name T733
Test name
Test status
Simulation time 207950551 ps
CPU time 2.85 seconds
Started Mar 28 01:27:07 PM PDT 24
Finished Mar 28 01:27:10 PM PDT 24
Peak memory 215328 kb
Host smart-4117f1b0-58cc-41c4-b6db-0cbc6ec2a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222839747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4222839747
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3585190809
Short name T567
Test name
Test status
Simulation time 363548465 ps
CPU time 10.15 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:16 PM PDT 24
Peak memory 208412 kb
Host smart-dfcb354b-d9e5-484a-93c8-66e41ae9af49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585190809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3585190809
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2721897527
Short name T142
Test name
Test status
Simulation time 4151190451 ps
CPU time 26.62 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:33 PM PDT 24
Peak memory 209376 kb
Host smart-20116a6f-8a46-4cbc-b729-25ca7add5d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721897527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2721897527
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.969679168
Short name T801
Test name
Test status
Simulation time 76830123 ps
CPU time 3.97 seconds
Started Mar 28 01:27:05 PM PDT 24
Finished Mar 28 01:27:09 PM PDT 24
Peak memory 209128 kb
Host smart-2b2cc4d3-28c5-4315-9051-a8e1bbf1c5f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969679168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.969679168
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1519770270
Short name T507
Test name
Test status
Simulation time 91164860 ps
CPU time 2.99 seconds
Started Mar 28 01:27:03 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 209276 kb
Host smart-409af997-7d68-49f0-b29c-385c8f3e1587
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519770270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1519770270
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.16998121
Short name T136
Test name
Test status
Simulation time 102162674 ps
CPU time 2.86 seconds
Started Mar 28 01:27:03 PM PDT 24
Finished Mar 28 01:27:06 PM PDT 24
Peak memory 208820 kb
Host smart-d1d4e0e3-1dd7-4c3f-8ec8-d957b6824435
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16998121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.16998121
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1291307811
Short name T443
Test name
Test status
Simulation time 220513582 ps
CPU time 2.41 seconds
Started Mar 28 01:27:08 PM PDT 24
Finished Mar 28 01:27:11 PM PDT 24
Peak memory 207336 kb
Host smart-41929d5c-a9df-41e7-9122-9b6bee077a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291307811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1291307811
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2277212666
Short name T493
Test name
Test status
Simulation time 60305104 ps
CPU time 2.46 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:03 PM PDT 24
Peak memory 208636 kb
Host smart-551ba118-c580-4463-9ca6-e6c8aefa3998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277212666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2277212666
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.4205107865
Short name T547
Test name
Test status
Simulation time 27199390 ps
CPU time 2.09 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:09 PM PDT 24
Peak memory 207780 kb
Host smart-f0578bf3-5e54-4634-8384-72397cd398d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205107865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4205107865
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2352161589
Short name T609
Test name
Test status
Simulation time 12735413 ps
CPU time 0.95 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:24 PM PDT 24
Peak memory 206492 kb
Host smart-c39d1ebd-feab-461f-9bed-6d5af50ff362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352161589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2352161589
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1018787190
Short name T114
Test name
Test status
Simulation time 4477118659 ps
CPU time 120.82 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:29:25 PM PDT 24
Peak memory 216004 kb
Host smart-3af001d8-02db-4719-910e-5deacbea3a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018787190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1018787190
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1852925426
Short name T40
Test name
Test status
Simulation time 68630597 ps
CPU time 3.09 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 209864 kb
Host smart-e262adc5-8f3c-412e-ae16-4ab847974e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852925426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1852925426
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2253471713
Short name T421
Test name
Test status
Simulation time 220904639 ps
CPU time 2.16 seconds
Started Mar 28 01:27:19 PM PDT 24
Finished Mar 28 01:27:22 PM PDT 24
Peak memory 208224 kb
Host smart-177ee243-7793-4b9e-98e0-50c0a9d9360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253471713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2253471713
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.667797178
Short name T843
Test name
Test status
Simulation time 114349490 ps
CPU time 4.23 seconds
Started Mar 28 01:27:18 PM PDT 24
Finished Mar 28 01:27:22 PM PDT 24
Peak memory 214740 kb
Host smart-887cb917-bfe6-4e20-ab75-51739540aef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667797178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.667797178
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3955652290
Short name T626
Test name
Test status
Simulation time 297430044 ps
CPU time 3.94 seconds
Started Mar 28 01:27:20 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 220396 kb
Host smart-5d248250-e142-4400-a48d-3574b8aa23ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955652290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3955652290
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3400169529
Short name T726
Test name
Test status
Simulation time 133688483 ps
CPU time 5.52 seconds
Started Mar 28 01:27:00 PM PDT 24
Finished Mar 28 01:27:06 PM PDT 24
Peak memory 207848 kb
Host smart-93c7a384-d7b1-4383-a5f8-a5797b13fbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400169529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3400169529
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.478966888
Short name T211
Test name
Test status
Simulation time 224914070 ps
CPU time 5.92 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:13 PM PDT 24
Peak memory 209036 kb
Host smart-68b151a3-b4b9-4f58-86c0-2f1cc2f96ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478966888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.478966888
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1992712272
Short name T106
Test name
Test status
Simulation time 151911589 ps
CPU time 2.61 seconds
Started Mar 28 01:27:01 PM PDT 24
Finished Mar 28 01:27:04 PM PDT 24
Peak memory 207688 kb
Host smart-00636301-936e-403e-a3e1-3673aeb6d465
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992712272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1992712272
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.59983077
Short name T671
Test name
Test status
Simulation time 3362364059 ps
CPU time 56.76 seconds
Started Mar 28 01:27:09 PM PDT 24
Finished Mar 28 01:28:06 PM PDT 24
Peak memory 208440 kb
Host smart-083f1714-3400-4aad-904b-f86070514be6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59983077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.59983077
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4054404401
Short name T281
Test name
Test status
Simulation time 71132380 ps
CPU time 3.32 seconds
Started Mar 28 01:27:02 PM PDT 24
Finished Mar 28 01:27:05 PM PDT 24
Peak memory 209092 kb
Host smart-c51948fc-98d7-49ee-9964-4ccd5a441f29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054404401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4054404401
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.564867410
Short name T103
Test name
Test status
Simulation time 84025265 ps
CPU time 2.21 seconds
Started Mar 28 01:27:24 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 209652 kb
Host smart-56153805-c943-4a26-b578-a9c3ddf4b49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564867410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.564867410
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2126742393
Short name T529
Test name
Test status
Simulation time 76392005 ps
CPU time 2.99 seconds
Started Mar 28 01:27:06 PM PDT 24
Finished Mar 28 01:27:10 PM PDT 24
Peak memory 207052 kb
Host smart-2707772a-8ccf-4719-b68f-669c4edca6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126742393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2126742393
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.4048905765
Short name T792
Test name
Test status
Simulation time 7870912419 ps
CPU time 13.16 seconds
Started Mar 28 01:27:26 PM PDT 24
Finished Mar 28 01:27:39 PM PDT 24
Peak memory 220684 kb
Host smart-dbb5c99a-6c05-4b9e-af5b-440db22c1be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048905765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.4048905765
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.799010258
Short name T327
Test name
Test status
Simulation time 3885269718 ps
CPU time 44.39 seconds
Started Mar 28 01:27:18 PM PDT 24
Finished Mar 28 01:28:03 PM PDT 24
Peak memory 214764 kb
Host smart-0a819e83-f22c-463b-8db5-728c67bee1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799010258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.799010258
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1446473414
Short name T797
Test name
Test status
Simulation time 372135881 ps
CPU time 9.02 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:33 PM PDT 24
Peak memory 211416 kb
Host smart-3b6a217e-94b4-40dc-b18a-92d7bd171a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446473414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1446473414
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2999941705
Short name T848
Test name
Test status
Simulation time 65483388 ps
CPU time 0.84 seconds
Started Mar 28 01:27:19 PM PDT 24
Finished Mar 28 01:27:20 PM PDT 24
Peak memory 206252 kb
Host smart-85ba7368-3b8d-4d70-9cc6-6ead36ac0a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999941705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2999941705
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2058579435
Short name T886
Test name
Test status
Simulation time 110734333 ps
CPU time 4.12 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:28 PM PDT 24
Peak memory 210404 kb
Host smart-19512740-1dd0-469b-832e-acedb5cfe70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058579435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2058579435
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3174572467
Short name T413
Test name
Test status
Simulation time 138965758 ps
CPU time 3.27 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:25 PM PDT 24
Peak memory 209020 kb
Host smart-667d32b7-066b-43f6-973e-c0717132949b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174572467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3174572467
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3563553705
Short name T348
Test name
Test status
Simulation time 91291363 ps
CPU time 4.87 seconds
Started Mar 28 01:27:26 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 214680 kb
Host smart-d112edcc-980a-4770-a513-75ee47610c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563553705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3563553705
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2941128279
Short name T294
Test name
Test status
Simulation time 505140487 ps
CPU time 6.09 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:34 PM PDT 24
Peak memory 220976 kb
Host smart-7759eaa3-0075-4802-b53c-481204274cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941128279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2941128279
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.17002725
Short name T261
Test name
Test status
Simulation time 159477972 ps
CPU time 6.18 seconds
Started Mar 28 01:27:24 PM PDT 24
Finished Mar 28 01:27:30 PM PDT 24
Peak memory 208884 kb
Host smart-db5442b8-2d93-4bad-9f4f-1ab2cca3ac59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17002725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.17002725
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2810554141
Short name T656
Test name
Test status
Simulation time 743113981 ps
CPU time 3.85 seconds
Started Mar 28 01:27:18 PM PDT 24
Finished Mar 28 01:27:22 PM PDT 24
Peak memory 208948 kb
Host smart-15f689b2-ec9a-45d0-a2ca-6d430351f2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810554141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2810554141
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2465221081
Short name T508
Test name
Test status
Simulation time 321593578 ps
CPU time 3.86 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 207016 kb
Host smart-a607f06a-3b78-4f71-8188-3ef1da99c399
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465221081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2465221081
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2351440707
Short name T659
Test name
Test status
Simulation time 66715576 ps
CPU time 3.46 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 208352 kb
Host smart-8817c30a-89c3-4e9c-9526-464ca28f1cd0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351440707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2351440707
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2797679436
Short name T811
Test name
Test status
Simulation time 137246907 ps
CPU time 3.45 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 208984 kb
Host smart-3cb2692d-39b5-4440-8de3-5c83400ea3b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797679436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2797679436
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1491122950
Short name T318
Test name
Test status
Simulation time 655825140 ps
CPU time 5.19 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 219012 kb
Host smart-ecb11c27-154e-4156-980d-732dcc595fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491122950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1491122950
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1290429770
Short name T852
Test name
Test status
Simulation time 86285547 ps
CPU time 2.93 seconds
Started Mar 28 01:27:18 PM PDT 24
Finished Mar 28 01:27:21 PM PDT 24
Peak memory 208172 kb
Host smart-0c69f18e-8952-40da-ab1c-446b1cf1dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290429770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1290429770
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2451626749
Short name T78
Test name
Test status
Simulation time 3333186348 ps
CPU time 66 seconds
Started Mar 28 01:27:26 PM PDT 24
Finished Mar 28 01:28:32 PM PDT 24
Peak memory 222920 kb
Host smart-e4d81c46-58f2-4834-b377-cdc90c0700cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451626749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2451626749
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3413087848
Short name T131
Test name
Test status
Simulation time 109554969 ps
CPU time 1.88 seconds
Started Mar 28 01:27:23 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 207220 kb
Host smart-5a91bcef-e535-4521-b80b-848faa8684a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413087848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3413087848
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1803685610
Short name T55
Test name
Test status
Simulation time 79169758 ps
CPU time 1.68 seconds
Started Mar 28 01:27:17 PM PDT 24
Finished Mar 28 01:27:19 PM PDT 24
Peak memory 210272 kb
Host smart-26795f26-dc4a-4fe7-a42f-990925a0a9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803685610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1803685610
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2139493313
Short name T447
Test name
Test status
Simulation time 53521750 ps
CPU time 0.73 seconds
Started Mar 28 01:27:27 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 206320 kb
Host smart-d2806158-6566-4570-9d0c-c6e6d3b3b0ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139493313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2139493313
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1932758555
Short name T430
Test name
Test status
Simulation time 130713407 ps
CPU time 5.08 seconds
Started Mar 28 01:27:19 PM PDT 24
Finished Mar 28 01:27:24 PM PDT 24
Peak memory 215832 kb
Host smart-7734e540-b078-4a1a-bd68-eca70edb0f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932758555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1932758555
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4143351897
Short name T420
Test name
Test status
Simulation time 25453078 ps
CPU time 1.46 seconds
Started Mar 28 01:27:17 PM PDT 24
Finished Mar 28 01:27:19 PM PDT 24
Peak memory 208036 kb
Host smart-6f31f450-388e-4396-bcec-0c9a0f25080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143351897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4143351897
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3433171622
Short name T22
Test name
Test status
Simulation time 202245246 ps
CPU time 3.8 seconds
Started Mar 28 01:27:26 PM PDT 24
Finished Mar 28 01:27:30 PM PDT 24
Peak memory 209188 kb
Host smart-ff008251-b1c8-48e5-9416-73f413245713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433171622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3433171622
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.140200844
Short name T310
Test name
Test status
Simulation time 91391219 ps
CPU time 4.32 seconds
Started Mar 28 01:27:24 PM PDT 24
Finished Mar 28 01:27:28 PM PDT 24
Peak memory 214544 kb
Host smart-ea526e5d-bb37-490f-8166-ec47864ba29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140200844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.140200844
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3184791886
Short name T762
Test name
Test status
Simulation time 605207710 ps
CPU time 2.96 seconds
Started Mar 28 01:27:19 PM PDT 24
Finished Mar 28 01:27:22 PM PDT 24
Peak memory 214656 kb
Host smart-b6d8022e-2b07-4045-afb5-3c76e98cd1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184791886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3184791886
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.35625548
Short name T331
Test name
Test status
Simulation time 147452649 ps
CPU time 5.49 seconds
Started Mar 28 01:27:26 PM PDT 24
Finished Mar 28 01:27:32 PM PDT 24
Peak memory 218768 kb
Host smart-fa3d80ee-5b59-4f48-b439-932fac3bd7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35625548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.35625548
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1826071712
Short name T232
Test name
Test status
Simulation time 222843230 ps
CPU time 6.55 seconds
Started Mar 28 01:27:24 PM PDT 24
Finished Mar 28 01:27:30 PM PDT 24
Peak memory 208112 kb
Host smart-fb2dfee5-c52b-4844-92e4-0f135efda62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826071712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1826071712
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.431703180
Short name T778
Test name
Test status
Simulation time 570337931 ps
CPU time 6.88 seconds
Started Mar 28 01:27:24 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 208916 kb
Host smart-228a3cd6-89cc-42e8-a0f3-0aa4aebdb46d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431703180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.431703180
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2830049898
Short name T607
Test name
Test status
Simulation time 120794153 ps
CPU time 2.59 seconds
Started Mar 28 01:27:20 PM PDT 24
Finished Mar 28 01:27:22 PM PDT 24
Peak memory 207144 kb
Host smart-6a562fc6-9935-4bdc-83dd-3ae9c3d7d756
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830049898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2830049898
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1550681867
Short name T696
Test name
Test status
Simulation time 56705185 ps
CPU time 2.93 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 208844 kb
Host smart-1410250d-1638-44d6-b18d-18eeccbd050b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550681867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1550681867
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2063368421
Short name T402
Test name
Test status
Simulation time 90290780 ps
CPU time 4.14 seconds
Started Mar 28 01:27:18 PM PDT 24
Finished Mar 28 01:27:23 PM PDT 24
Peak memory 218576 kb
Host smart-7c171c95-564c-4190-b50a-e6a6ed2fc94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063368421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2063368421
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3746946544
Short name T639
Test name
Test status
Simulation time 1368896099 ps
CPU time 28.78 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:52 PM PDT 24
Peak memory 208856 kb
Host smart-bf0d5b10-cf80-4f92-af0f-77a145e5a5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746946544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3746946544
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.707165543
Short name T126
Test name
Test status
Simulation time 989150667 ps
CPU time 20.41 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:44 PM PDT 24
Peak memory 221340 kb
Host smart-f1be0c51-a7e7-4b15-ae2a-bef414d2e623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707165543 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.707165543
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3540166140
Short name T314
Test name
Test status
Simulation time 302993853 ps
CPU time 4.82 seconds
Started Mar 28 01:27:25 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 214588 kb
Host smart-5a8cd9a7-e5f9-4b30-a88c-99efdc14b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540166140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3540166140
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1332049327
Short name T212
Test name
Test status
Simulation time 185412040 ps
CPU time 1.73 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:25 PM PDT 24
Peak memory 210068 kb
Host smart-77cafe2f-0263-4b31-ae5c-1bc2ad4b074f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332049327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1332049327
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3270619966
Short name T621
Test name
Test status
Simulation time 40163027 ps
CPU time 0.91 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 206332 kb
Host smart-63e7eb7d-af5a-40fb-b1ac-68a101935f33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270619966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3270619966
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.426241752
Short name T25
Test name
Test status
Simulation time 1551070813 ps
CPU time 46.08 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:28:08 PM PDT 24
Peak memory 219536 kb
Host smart-b50fe868-6ebc-4eea-bfc3-018e520a7b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426241752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.426241752
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1816691929
Short name T804
Test name
Test status
Simulation time 278529146 ps
CPU time 4.14 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:28 PM PDT 24
Peak memory 219440 kb
Host smart-656944b5-0b39-45bf-90df-05ada82fe518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816691929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1816691929
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1197429913
Short name T356
Test name
Test status
Simulation time 115292792 ps
CPU time 4.86 seconds
Started Mar 28 01:27:20 PM PDT 24
Finished Mar 28 01:27:28 PM PDT 24
Peak memory 209916 kb
Host smart-54a7dda6-38b0-4567-b5d6-a9d4d9d40b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197429913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1197429913
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2857361054
Short name T677
Test name
Test status
Simulation time 96050933 ps
CPU time 2.76 seconds
Started Mar 28 01:27:20 PM PDT 24
Finished Mar 28 01:27:26 PM PDT 24
Peak memory 208700 kb
Host smart-fda8ebff-d79d-4293-8691-01fcbf698c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857361054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2857361054
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3984562477
Short name T560
Test name
Test status
Simulation time 259319728 ps
CPU time 7.94 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:31 PM PDT 24
Peak memory 208996 kb
Host smart-f6d78760-f3fb-48f5-a08e-dd285534d927
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984562477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3984562477
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3846426886
Short name T407
Test name
Test status
Simulation time 184829755 ps
CPU time 3.67 seconds
Started Mar 28 01:27:30 PM PDT 24
Finished Mar 28 01:27:34 PM PDT 24
Peak memory 207188 kb
Host smart-7b522c9e-47f9-4624-8f0a-1edbecd15d0f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846426886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3846426886
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.43564428
Short name T707
Test name
Test status
Simulation time 74850701 ps
CPU time 2.57 seconds
Started Mar 28 01:27:24 PM PDT 24
Finished Mar 28 01:27:28 PM PDT 24
Peak memory 208832 kb
Host smart-29cd124e-fb17-4588-b1c5-24ede6161f1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43564428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.43564428
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.865920830
Short name T423
Test name
Test status
Simulation time 78250500 ps
CPU time 2.49 seconds
Started Mar 28 01:27:28 PM PDT 24
Finished Mar 28 01:27:30 PM PDT 24
Peak memory 209952 kb
Host smart-c3d27f75-921d-4d84-9ae8-4c97bdc8c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865920830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.865920830
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.672561469
Short name T572
Test name
Test status
Simulation time 431059287 ps
CPU time 3.87 seconds
Started Mar 28 01:27:22 PM PDT 24
Finished Mar 28 01:27:27 PM PDT 24
Peak memory 206872 kb
Host smart-3f8b7362-2a0f-4ac1-b6ea-aea02b4ebcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672561469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.672561469
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.846751966
Short name T809
Test name
Test status
Simulation time 648986029 ps
CPU time 6.13 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:29 PM PDT 24
Peak memory 214636 kb
Host smart-25e923f8-1692-4c67-aa59-3e45c592c866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846751966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.846751966
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4269503557
Short name T798
Test name
Test status
Simulation time 33322889 ps
CPU time 2.03 seconds
Started Mar 28 01:27:21 PM PDT 24
Finished Mar 28 01:27:25 PM PDT 24
Peak memory 209064 kb
Host smart-847908b1-896c-479b-b14a-a943ccdbb760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269503557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4269503557
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%