SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 779 | 1 | T22 | 30 | T23 | 20 | T24 | 30 | ||||
auto[OtpRootKeyValidLow] | 167 | 1 | T22 | 7 | T23 | 7 | T24 | 7 | ||||
auto[LcStateInvalid] | 56 | 1 | T267 | 8 | T278 | 24 | T318 | 24 | ||||
auto[OtpDevIdInvalid] | 84 | 1 | T85 | 12 | T401 | 12 | T345 | 24 | ||||
auto[RomDigestInvalid] | 84 | 1 | T94 | 12 | T293 | 24 | T345 | 24 | ||||
auto[RomDigestValidLow] | 96 | 1 | T254 | 12 | T402 | 48 | T360 | 24 | ||||
auto[FlashCreatorSeedInvalid] | 24 | 1 | T293 | 12 | T403 | 12 | - | - | ||||
auto[FlashOwnerSeedInvalid] | 144 | 1 | T97 | 60 | T98 | 12 | T99 | 24 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |