Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10990

1

T1

16

T2

14

T3

13

auto[Attestation]

8212

1

T1

17

T2

8

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2771	1			T1	8		T2	3		T3	4
auto[Aes]	3463	1			T1	4		T2	6		T3	3
auto[Kmac]	3393	1			T1	3		T2	2		T3	2
auto[Otbn]	3464	1			T1	1		T2	2		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7782	1			T1	8		T2	8		T3	8
auto[OpGenId]	6111	1			T1	17		T2	9		T3	6
auto[OpGenSwOut]	5824	1			T1	10		T2	7		T3	6
auto[OpGenHwOut]	7267	1			T1	6		T2	6		T3	4
auto[OpDisable]	152	1			T49	1		T50	1		T51	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10272

1

T1

14

T2

14

T3

8

auto[OpDoneFail]

16864

1

T1

27

T2

16

T3

16

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6121	1			T1	4		T2	2		T3	9
auto[StInit]	4298	1			T1	2		T2	4		T3	2
auto[StCreatorRootKey]	3083	1			T1	6		T2	5		T3	2
auto[StOwnerIntKey]	2668	1			T1	5		T2	6		T3	2
auto[StOwnerKey]	2374	1			T1	4		T2	1		T3	2
auto[StDisabled]	7590	1			T1	20		T2	12		T3	7
auto[StInvalid]	1002	1			T36	17		T108	21		T198	26

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	290	1			T3	2		T14	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	114	1			T14	1		T18	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T3	1		T42	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T2	1		T202	1		T74	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T26	1		T203	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	201	1			T1	1		T35	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	25	1			T108	1		T198	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	300	1			T16	2		T105	1		T206	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	99	1			T2	1		T17	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	67	1			T13	1		T57	1		T44	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	67	1			T1	1		T2	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	54	1			T35	1		T74	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	185	1			T2	1		T35	2		T42	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	31	1			T36	2		T205	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	292	1			T3	1		T16	1		T105	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	113	1			T27	1		T22	2		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T50	1		T130	1		T97	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T26	1		T45	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	43	1			T89	1		T42	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	185	1			T25	1		T42	1		T50	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	27	1			T36	1		T108	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	304	1			T3	1		T14	2		T16	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	108	1			T18	1		T35	1		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T36	1		T204	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	76	1			T36	1		T74	3		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	64	1			T18	1		T35	1		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	184	1			T1	1		T2	1		T89	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	23	1			T198	1		T205	1		T209	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	84	1			T74	8		T44	4		T45	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	118	1			T16	1		T18	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	83	1			T42	1		T51	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T1	2		T14	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T35	1		T70	1		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	193	1			T1	1		T2	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	41	1			T36	1		T108	1		T198	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	90	1			T74	3		T57	1		T44	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	108	1			T25	1		T22	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	87	1			T1	1		T13	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	54	1			T2	1		T14	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	49	1			T14	1		T210	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	218	1			T1	2		T3	1		T105	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	24	1			T205	1		T207	2		T212	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	66	1			T74	2		T57	1		T45	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	134	1			T13	1		T22	3		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T1	1		T89	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	53	1			T49	1		T74	2		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	47	1			T70	1		T74	2		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	205	1			T105	2		T26	2		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	30	1			T36	1		T108	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	83	1			T74	6		T57	2		T44	6
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	116	1			T203	1		T23	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T42	1		T130	1		T74	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T74	1		T44	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	58	1			T26	1		T202	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	176	1			T18	1		T25	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	28	1			T108	1		T198	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	235	1			T1	1		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T105	1		T27	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	65	1			T13	1		T208	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	54	1			T2	1		T44	1		T146	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	50	1			T1	1		T50	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	158	1			T42	1		T210	2		T74	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	32	1			T108	1		T198	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	498	1			T3	1		T14	2		T15	8
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	124	1			T214	1		T23	2		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	97	1			T2	1		T15	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	80	1			T15	1		T214	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T15	1		T42	1		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	292	1			T2	1		T3	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	22	1			T36	1		T108	1		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	442	1			T2	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	145	1			T14	1		T88	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	73	1			T130	1		T211	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T88	1		T133	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	84	1			T14	1		T88	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	276	1			T2	1		T3	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	32	1			T36	1		T205	2		T207	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	473	1			T16	1		T41	7		T106	10
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	144	1			T35	1		T41	1		T106	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	103	1			T106	1		T107	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T203	1		T216	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	94	1			T14	2		T107	1		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	277	1			T18	1		T35	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	32	1			T108	1		T212	1		T218	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	77	1			T74	1		T44	6		T45	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	125	1			T105	1		T23	2		T24	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T25	1		T50	1		T97	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	60	1			T74	1		T219	1		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	43	1			T130	1		T36	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	184	1			T1	2		T18	2		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T108	1		T198	1		T205	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	60	1			T74	1		T44	1		T45	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	154	1			T15	1		T16	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	108	1			T35	2		T25	2		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	97	1			T35	1		T131	1		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	83	1			T25	1		T214	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	288	1			T15	2		T105	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	33	1			T108	1		T198	1		T205	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	63	1			T74	2		T44	4		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	150	1			T35	1		T133	1		T23	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T1	1		T88	1		T133	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T35	1		T74	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	86	1			T14	3		T35	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T1	1		T88	4		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	30	1			T36	1		T207	1		T218	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	53	1			T57	1		T44	4		T116	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	132	1			T13	1		T22	2		T97	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T41	1		T25	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	99	1			T41	1		T106	1		T107	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	96	1			T41	1		T106	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	270	1			T2	1		T18	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	31	1			T198	2		T212	1		T218	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	172	1			T2	1		T3	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	648	1			T1	1		T3	2		T14	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	176	1			T1	1		T2	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	627	1			T2	2		T16	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	200	1			T89	1		T42	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	625	1			T3	1		T16	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T18	1		T35	1		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	637	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	206	1			T1	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	451	1			T1	2		T2	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	181	1			T2	1		T13	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	449	1			T1	3		T3	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	172	1			T1	1		T89	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	447	1			T13	1		T105	2		T26	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	215	1			T42	1		T26	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	412	1			T18	1		T25	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	154	1			T1	1		T2	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	544	1			T1	1		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	256	1			T2	1		T15	3		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	951	1			T2	1		T3	2		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	234	1			T14	1		T88	2		T133	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	907	1			T2	2		T3	1		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T14	2		T106	1		T107	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	943	1			T16	1		T18	1		T35	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	159	1			T25	1		T50	1		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	437	1			T1	2		T18	2		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	276	1			T35	3		T25	3		T214	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	547	1			T15	3		T16	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	269	1			T14	3		T35	2		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	539	1			T1	2		T35	1		T88	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	278	1			T41	3		T25	1		T106	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	500	1			T2	1		T13	1		T18	1