Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31173

1

T1

45

T2

33

T3

27

auto[1]

297

1

T2

8

T121

3

T146

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31181	1			T1	45		T2	33		T3	27
auto[134217728:268435455]	9	1			T300	1		T415	1		T362	2
auto[268435456:402653183]	15	1			T376	1		T415	2		T282	1
auto[402653184:536870911]	7	1			T135	1		T300	1		T416	2
auto[536870912:671088639]	8	1			T136	1		T137	3		T417	1
auto[671088640:805306367]	14	1			T417	1		T415	1		T416	1
auto[805306368:939524095]	8	1			T319	1		T344	1		T327	1
auto[939524096:1073741823]	7	1			T186	1		T136	1		T137	1
auto[1073741824:1207959551]	10	1			T135	1		T136	1		T137	1
auto[1207959552:1342177279]	7	1			T344	1		T258	1		T418	1
auto[1342177280:1476395007]	4	1			T121	1		T415	1		T344	1
auto[1476395008:1610612735]	10	1			T319	1		T322	1		T344	1
auto[1610612736:1744830463]	12	1			T135	1		T136	1		T417	1
auto[1744830464:1879048191]	8	1			T417	1		T399	1		T300	1
auto[1879048192:2013265919]	13	1			T2	1		T146	1		T137	2
auto[2013265920:2147483647]	10	1			T146	2		T137	1		T319	2
auto[2147483648:2281701375]	6	1			T300	1		T415	1		T258	1
auto[2281701376:2415919103]	12	1			T2	1		T146	1		T136	1
auto[2415919104:2550136831]	8	1			T416	1		T419	1		T400	1
auto[2550136832:2684354559]	7	1			T136	1		T399	1		T420	1
auto[2684354560:2818572287]	8	1			T415	1		T362	1		T284	2
auto[2818572288:2952790015]	10	1			T146	1		T138	1		T258	1
auto[2952790016:3087007743]	5	1			T344	1		T421	1		T418	1
auto[3087007744:3221225471]	13	1			T146	1		T417	1		T416	1
auto[3221225472:3355443199]	9	1			T2	1		T146	1		T137	1
auto[3355443200:3489660927]	6	1			T399	1		T344	1		T370	1
auto[3489660928:3623878655]	10	1			T137	1		T376	1		T298	1
auto[3623878656:3758096383]	19	1			T2	2		T121	1		T146	1
auto[3758096384:3892314111]	4	1			T138	1		T416	1		T421	1
auto[3892314112:4026531839]	7	1			T136	1		T258	3		T422	1
auto[4026531840:4160749567]	16	1			T2	2		T121	1		T137	1
auto[4160749568:4294967295]	7	1			T2	1		T137	2		T319	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31173	1			T1	45		T2	33		T3	27
auto[0:134217727]	auto[1]	8	1			T146	1		T136	1		T319	1
auto[134217728:268435455]	auto[1]	9	1			T300	1		T415	1		T362	2
auto[268435456:402653183]	auto[1]	15	1			T376	1		T415	2		T282	1
auto[402653184:536870911]	auto[1]	7	1			T135	1		T300	1		T416	2
auto[536870912:671088639]	auto[1]	8	1			T136	1		T137	3		T417	1
auto[671088640:805306367]	auto[1]	14	1			T417	1		T415	1		T416	1
auto[805306368:939524095]	auto[1]	8	1			T319	1		T344	1		T327	1
auto[939524096:1073741823]	auto[1]	7	1			T186	1		T136	1		T137	1
auto[1073741824:1207959551]	auto[1]	10	1			T135	1		T136	1		T137	1
auto[1207959552:1342177279]	auto[1]	7	1			T344	1		T258	1		T418	1
auto[1342177280:1476395007]	auto[1]	4	1			T121	1		T415	1		T344	1
auto[1476395008:1610612735]	auto[1]	10	1			T319	1		T322	1		T344	1
auto[1610612736:1744830463]	auto[1]	12	1			T135	1		T136	1		T417	1
auto[1744830464:1879048191]	auto[1]	8	1			T417	1		T399	1		T300	1
auto[1879048192:2013265919]	auto[1]	13	1			T2	1		T146	1		T137	2
auto[2013265920:2147483647]	auto[1]	10	1			T146	2		T137	1		T319	2
auto[2147483648:2281701375]	auto[1]	6	1			T300	1		T415	1		T258	1
auto[2281701376:2415919103]	auto[1]	12	1			T2	1		T146	1		T136	1
auto[2415919104:2550136831]	auto[1]	8	1			T416	1		T419	1		T400	1
auto[2550136832:2684354559]	auto[1]	7	1			T136	1		T399	1		T420	1
auto[2684354560:2818572287]	auto[1]	8	1			T415	1		T362	1		T284	2
auto[2818572288:2952790015]	auto[1]	10	1			T146	1		T138	1		T258	1
auto[2952790016:3087007743]	auto[1]	5	1			T344	1		T421	1		T418	1
auto[3087007744:3221225471]	auto[1]	13	1			T146	1		T417	1		T416	1
auto[3221225472:3355443199]	auto[1]	9	1			T2	1		T146	1		T137	1
auto[3355443200:3489660927]	auto[1]	6	1			T399	1		T344	1		T370	1
auto[3489660928:3623878655]	auto[1]	10	1			T137	1		T376	1		T298	1
auto[3623878656:3758096383]	auto[1]	19	1			T2	2		T121	1		T146	1
auto[3758096384:3892314111]	auto[1]	4	1			T138	1		T416	1		T421	1
auto[3892314112:4026531839]	auto[1]	7	1			T136	1		T258	3		T422	1
auto[4026531840:4160749567]	auto[1]	16	1			T2	2		T121	1		T137	1
auto[4160749568:4294967295]	auto[1]	7	1			T2	1		T137	2		T319	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1482

1

T1

1

T12

1

T14

2

auto[1]

1657

1

T1

3

T2

3

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T49	1		T74	1		T44	3
auto[134217728:268435455]	99	1			T22	1		T208	1		T24	1
auto[268435456:402653183]	95	1			T1	1		T42	1		T74	1
auto[402653184:536870911]	101	1			T208	1		T50	1		T210	1
auto[536870912:671088639]	102	1			T22	1		T28	1		T74	2
auto[671088640:805306367]	94	1			T42	1		T22	1		T49	2
auto[805306368:939524095]	93	1			T1	1		T26	1		T208	2
auto[939524096:1073741823]	89	1			T49	1		T210	1		T37	1
auto[1073741824:1207959551]	118	1			T18	1		T97	1		T211	1
auto[1207959552:1342177279]	98	1			T51	1		T55	1		T44	1
auto[1342177280:1476395007]	97	1			T18	1		T49	1		T51	1
auto[1476395008:1610612735]	102	1			T26	3		T57	1		T241	1
auto[1610612736:1744830463]	97	1			T12	1		T14	1		T25	1
auto[1744830464:1879048191]	90	1			T31	1		T26	1		T7	1
auto[1879048192:2013265919]	95	1			T55	1		T74	1		T44	1
auto[2013265920:2147483647]	101	1			T26	1		T24	1		T49	1
auto[2147483648:2281701375]	113	1			T49	1		T210	1		T108	1
auto[2281701376:2415919103]	95	1			T105	2		T36	1		T57	1
auto[2415919104:2550136831]	88	1			T18	1		T35	1		T22	1
auto[2550136832:2684354559]	86	1			T2	1		T12	1		T14	2
auto[2684354560:2818572287]	131	1			T35	1		T42	2		T50	1
auto[2818572288:2952790015]	104	1			T12	1		T25	1		T28	1
auto[2952790016:3087007743]	102	1			T2	1		T35	1		T26	1
auto[3087007744:3221225471]	92	1			T105	2		T74	1		T44	3
auto[3221225472:3355443199]	107	1			T26	1		T23	1		T49	1
auto[3355443200:3489660927]	86	1			T35	1		T25	1		T23	1
auto[3489660928:3623878655]	96	1			T1	1		T49	1		T50	1
auto[3623878656:3758096383]	94	1			T208	1		T74	1		T44	5
auto[3758096384:3892314111]	86	1			T14	1		T105	1		T49	1
auto[3892314112:4026531839]	101	1			T2	1		T42	2		T208	1
auto[4026531840:4160749567]	76	1			T23	1		T130	1		T210	1
auto[4160749568:4294967295]	103	1			T1	1		T27	1		T97	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T49	1		T44	2		T94	1
auto[0:134217727]	auto[1]	66	1			T74	1		T44	1		T54	1
auto[134217728:268435455]	auto[0]	47	1			T22	1		T208	1		T24	1
auto[134217728:268435455]	auto[1]	52	1			T44	4		T45	1		T136	1
auto[268435456:402653183]	auto[0]	45	1			T1	1		T42	1		T44	3
auto[268435456:402653183]	auto[1]	50	1			T74	1		T44	1		T198	1
auto[402653184:536870911]	auto[0]	53	1			T50	1		T210	1		T57	1
auto[402653184:536870911]	auto[1]	48	1			T208	1		T57	1		T45	2
auto[536870912:671088639]	auto[0]	53	1			T28	1		T74	2		T44	1
auto[536870912:671088639]	auto[1]	49	1			T22	1		T69	1		T190	2
auto[671088640:805306367]	auto[0]	48	1			T42	1		T49	2		T97	1
auto[671088640:805306367]	auto[1]	46	1			T22	1		T70	1		T210	1
auto[805306368:939524095]	auto[0]	43	1			T208	1		T210	1		T68	1
auto[805306368:939524095]	auto[1]	50	1			T1	1		T26	1		T208	1
auto[939524096:1073741823]	auto[0]	45	1			T49	1		T57	1		T44	1
auto[939524096:1073741823]	auto[1]	44	1			T210	1		T37	1		T286	1
auto[1073741824:1207959551]	auto[0]	55	1			T211	1		T45	3		T90	1
auto[1073741824:1207959551]	auto[1]	63	1			T18	1		T97	1		T44	1
auto[1207959552:1342177279]	auto[0]	46	1			T55	1		T207	1		T212	1
auto[1207959552:1342177279]	auto[1]	52	1			T51	1		T44	1		T198	1
auto[1342177280:1476395007]	auto[0]	49	1			T44	2		T121	1		T45	1
auto[1342177280:1476395007]	auto[1]	48	1			T18	1		T49	1		T51	1
auto[1476395008:1610612735]	auto[0]	49	1			T26	2		T57	1		T241	1
auto[1476395008:1610612735]	auto[1]	53	1			T26	1		T45	1		T71	1
auto[1610612736:1744830463]	auto[0]	53	1			T24	1		T45	1		T90	1
auto[1610612736:1744830463]	auto[1]	44	1			T12	1		T14	1		T25	1
auto[1744830464:1879048191]	auto[0]	35	1			T26	1		T7	1		T45	2
auto[1744830464:1879048191]	auto[1]	55	1			T31	1		T85	1		T44	1
auto[1879048192:2013265919]	auto[0]	51	1			T55	1		T8	1		T20	1
auto[1879048192:2013265919]	auto[1]	44	1			T74	1		T44	1		T45	1
auto[2013265920:2147483647]	auto[0]	48	1			T24	1		T50	2		T74	1
auto[2013265920:2147483647]	auto[1]	53	1			T26	1		T49	1		T50	1
auto[2147483648:2281701375]	auto[0]	55	1			T49	1		T210	1		T108	1
auto[2147483648:2281701375]	auto[1]	58	1			T44	2		T45	1		T92	1
auto[2281701376:2415919103]	auto[0]	44	1			T105	1		T57	1		T198	1
auto[2281701376:2415919103]	auto[1]	51	1			T105	1		T36	1		T44	3
auto[2415919104:2550136831]	auto[0]	38	1			T35	1		T22	1		T70	1
auto[2415919104:2550136831]	auto[1]	50	1			T18	1		T44	1		T146	2
auto[2550136832:2684354559]	auto[0]	35	1			T14	1		T45	1		T207	1
auto[2550136832:2684354559]	auto[1]	51	1			T2	1		T12	1		T14	1
auto[2684354560:2818572287]	auto[0]	69	1			T35	1		T50	1		T97	1
auto[2684354560:2818572287]	auto[1]	62	1			T42	2		T70	1		T44	2
auto[2818572288:2952790015]	auto[0]	49	1			T12	1		T25	1		T28	1
auto[2818572288:2952790015]	auto[1]	55	1			T130	1		T7	1		T135	1
auto[2952790016:3087007743]	auto[0]	51	1			T35	1		T198	1		T92	1
auto[2952790016:3087007743]	auto[1]	51	1			T2	1		T26	1		T49	1
auto[3087007744:3221225471]	auto[0]	41	1			T105	1		T74	1		T44	2
auto[3087007744:3221225471]	auto[1]	51	1			T105	1		T44	1		T113	1
auto[3221225472:3355443199]	auto[0]	53	1			T26	1		T49	1		T121	1
auto[3221225472:3355443199]	auto[1]	54	1			T23	1		T108	1		T85	1
auto[3355443200:3489660927]	auto[0]	37	1			T25	1		T74	1		T198	1
auto[3355443200:3489660927]	auto[1]	49	1			T35	1		T23	1		T108	1
auto[3489660928:3623878655]	auto[0]	46	1			T50	1		T53	1		T44	1
auto[3489660928:3623878655]	auto[1]	50	1			T1	1		T49	1		T44	1
auto[3623878656:3758096383]	auto[0]	43	1			T44	1		T343	1		T218	1
auto[3623878656:3758096383]	auto[1]	51	1			T208	1		T74	1		T44	4
auto[3758096384:3892314111]	auto[0]	40	1			T14	1		T44	1		T45	1
auto[3758096384:3892314111]	auto[1]	46	1			T105	1		T49	1		T51	1
auto[3892314112:4026531839]	auto[0]	40	1			T42	1		T49	1		T211	1
auto[3892314112:4026531839]	auto[1]	61	1			T2	1		T42	1		T208	1
auto[4026531840:4160749567]	auto[0]	35	1			T210	1		T57	1		T198	1
auto[4026531840:4160749567]	auto[1]	41	1			T23	1		T130	1		T44	2
auto[4160749568:4294967295]	auto[0]	44	1			T97	1		T45	1		T358	1
auto[4160749568:4294967295]	auto[1]	59	1			T1	1		T27	1		T54	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1453

1

T1

1

T12

1

T14

2

auto[1]

1686

1

T1

3

T2

3

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T14	1		T50	1		T51	1
auto[134217728:268435455]	97	1			T26	1		T23	1		T7	1
auto[268435456:402653183]	102	1			T1	1		T42	1		T105	1
auto[402653184:536870911]	88	1			T49	2		T44	2		T54	1
auto[536870912:671088639]	115	1			T12	1		T18	1		T25	1
auto[671088640:805306367]	104	1			T14	1		T35	1		T49	1
auto[805306368:939524095]	92	1			T210	1		T44	1		T45	1
auto[939524096:1073741823]	96	1			T25	1		T49	1		T55	1
auto[1073741824:1207959551]	93	1			T2	1		T35	1		T208	1
auto[1207959552:1342177279]	97	1			T26	1		T22	1		T23	1
auto[1342177280:1476395007]	93	1			T22	1		T50	1		T210	1
auto[1476395008:1610612735]	90	1			T18	1		T208	1		T23	1
auto[1610612736:1744830463]	117	1			T2	1		T44	3		T198	1
auto[1744830464:1879048191]	90	1			T26	1		T44	3		T8	1
auto[1879048192:2013265919]	96	1			T14	1		T105	1		T26	1
auto[2013265920:2147483647]	99	1			T12	1		T28	2		T49	1
auto[2147483648:2281701375]	104	1			T42	1		T22	1		T24	1
auto[2281701376:2415919103]	102	1			T26	1		T24	1		T97	1
auto[2415919104:2550136831]	95	1			T25	1		T27	1		T49	1
auto[2550136832:2684354559]	67	1			T12	1		T105	1		T26	1
auto[2684354560:2818572287]	114	1			T42	1		T26	1		T49	1
auto[2818572288:2952790015]	91	1			T1	1		T22	1		T49	1
auto[2952790016:3087007743]	86	1			T74	1		T85	1		T44	3
auto[3087007744:3221225471]	84	1			T1	1		T25	1		T26	1
auto[3221225472:3355443199]	86	1			T35	1		T208	2		T49	1
auto[3355443200:3489660927]	118	1			T18	1		T211	2		T74	2
auto[3489660928:3623878655]	104	1			T50	1		T44	2		T45	6
auto[3623878656:3758096383]	109	1			T31	1		T42	1		T23	1
auto[3758096384:3892314111]	104	1			T14	1		T35	1		T42	1
auto[3892314112:4026531839]	102	1			T2	1		T105	1		T208	1
auto[4026531840:4160749567]	104	1			T53	1		T44	1		T45	2
auto[4160749568:4294967295]	103	1			T1	1		T42	1		T105	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T14	1		T74	1		T45	1
auto[0:134217727]	auto[1]	49	1			T50	1		T51	1		T97	1
auto[134217728:268435455]	auto[0]	45	1			T7	1		T55	1		T286	1
auto[134217728:268435455]	auto[1]	52	1			T26	1		T23	1		T57	1
auto[268435456:402653183]	auto[0]	48	1			T1	1		T42	1		T49	1
auto[268435456:402653183]	auto[1]	54	1			T105	1		T208	1		T49	1
auto[402653184:536870911]	auto[0]	41	1			T49	1		T44	1		T45	1
auto[402653184:536870911]	auto[1]	47	1			T49	1		T44	1		T54	1
auto[536870912:671088639]	auto[0]	53	1			T44	2		T121	1		T198	1
auto[536870912:671088639]	auto[1]	62	1			T12	1		T18	1		T25	1
auto[671088640:805306367]	auto[0]	46	1			T35	1		T70	1		T108	1
auto[671088640:805306367]	auto[1]	58	1			T14	1		T49	1		T207	1
auto[805306368:939524095]	auto[0]	38	1			T210	1		T44	1		T20	1
auto[805306368:939524095]	auto[1]	54	1			T45	1		T90	1		T423	1
auto[939524096:1073741823]	auto[0]	39	1			T49	1		T55	1		T44	1
auto[939524096:1073741823]	auto[1]	57	1			T25	1		T74	1		T44	2
auto[1073741824:1207959551]	auto[0]	30	1			T210	1		T45	2		T19	1
auto[1073741824:1207959551]	auto[1]	63	1			T2	1		T35	1		T208	1
auto[1207959552:1342177279]	auto[0]	39	1			T22	1		T28	1		T57	1
auto[1207959552:1342177279]	auto[1]	58	1			T26	1		T23	1		T70	1
auto[1342177280:1476395007]	auto[0]	44	1			T50	1		T210	1		T57	1
auto[1342177280:1476395007]	auto[1]	49	1			T22	1		T44	1		T45	2
auto[1476395008:1610612735]	auto[0]	40	1			T186	1		T93	1		T116	1
auto[1476395008:1610612735]	auto[1]	50	1			T18	1		T208	1		T23	1
auto[1610612736:1744830463]	auto[0]	49	1			T198	1		T93	1		T245	1
auto[1610612736:1744830463]	auto[1]	68	1			T2	1		T44	3		T286	1
auto[1744830464:1879048191]	auto[0]	47	1			T44	1		T8	1		T45	1
auto[1744830464:1879048191]	auto[1]	43	1			T26	1		T44	2		T286	1
auto[1879048192:2013265919]	auto[0]	45	1			T14	1		T26	1		T45	1
auto[1879048192:2013265919]	auto[1]	51	1			T105	1		T130	1		T37	1
auto[2013265920:2147483647]	auto[0]	52	1			T12	1		T28	2		T49	1
auto[2013265920:2147483647]	auto[1]	47	1			T50	1		T130	1		T44	2
auto[2147483648:2281701375]	auto[0]	57	1			T42	1		T22	1		T24	1
auto[2147483648:2281701375]	auto[1]	47	1			T44	1		T190	1		T341	1
auto[2281701376:2415919103]	auto[0]	39	1			T24	1		T45	1		T6	1
auto[2281701376:2415919103]	auto[1]	63	1			T26	1		T97	1		T70	1
auto[2415919104:2550136831]	auto[0]	45	1			T25	1		T49	1		T57	1
auto[2415919104:2550136831]	auto[1]	50	1			T27	1		T44	1		T45	3
auto[2550136832:2684354559]	auto[0]	29	1			T105	1		T49	1		T198	2
auto[2550136832:2684354559]	auto[1]	38	1			T12	1		T26	1		T51	1
auto[2684354560:2818572287]	auto[0]	60	1			T26	1		T49	1		T108	1
auto[2684354560:2818572287]	auto[1]	54	1			T42	1		T108	1		T44	1
auto[2818572288:2952790015]	auto[0]	39	1			T49	1		T8	1		T121	1
auto[2818572288:2952790015]	auto[1]	52	1			T1	1		T22	1		T7	1
auto[2952790016:3087007743]	auto[0]	38	1			T85	1		T44	1		T46	1
auto[2952790016:3087007743]	auto[1]	48	1			T74	1		T44	2		T45	1
auto[3087007744:3221225471]	auto[0]	47	1			T25	1		T26	1		T97	2
auto[3087007744:3221225471]	auto[1]	37	1			T1	1		T44	2		T94	1
auto[3221225472:3355443199]	auto[0]	42	1			T208	1		T50	1		T211	1
auto[3221225472:3355443199]	auto[1]	44	1			T35	1		T208	1		T49	1
auto[3355443200:3489660927]	auto[0]	54	1			T211	1		T74	2		T45	1
auto[3355443200:3489660927]	auto[1]	64	1			T18	1		T211	1		T57	1
auto[3489660928:3623878655]	auto[0]	54	1			T50	1		T45	3		T90	1
auto[3489660928:3623878655]	auto[1]	50	1			T44	2		T45	3		T58	1
auto[3623878656:3758096383]	auto[0]	47	1			T57	1		T121	1		T189	1
auto[3623878656:3758096383]	auto[1]	62	1			T31	1		T42	1		T23	1
auto[3758096384:3892314111]	auto[0]	58	1			T35	1		T50	1		T70	1
auto[3758096384:3892314111]	auto[1]	46	1			T14	1		T42	1		T44	1
auto[3892314112:4026531839]	auto[0]	52	1			T105	1		T24	1		T45	1
auto[3892314112:4026531839]	auto[1]	50	1			T2	1		T208	1		T45	3
auto[4026531840:4160749567]	auto[0]	39	1			T45	1		T90	1		T56	1
auto[4026531840:4160749567]	auto[1]	65	1			T53	1		T44	1		T45	1
auto[4160749568:4294967295]	auto[0]	49	1			T210	1		T108	1		T57	1
auto[4160749568:4294967295]	auto[1]	54	1			T1	1		T42	1		T105	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1460

1

T1

1

T12

1

T14

2

auto[1]

1679

1

T1

3

T2

3

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T2	1		T18	1		T42	1
auto[134217728:268435455]	97	1			T14	1		T50	2		T45	2
auto[268435456:402653183]	106	1			T2	1		T105	1		T49	1
auto[402653184:536870911]	87	1			T108	2		T74	1		T57	1
auto[536870912:671088639]	98	1			T1	1		T49	1		T50	1
auto[671088640:805306367]	91	1			T23	1		T49	2		T210	1
auto[805306368:939524095]	107	1			T35	1		T22	1		T24	1
auto[939524096:1073741823]	107	1			T105	1		T70	2		T210	1
auto[1073741824:1207959551]	100	1			T26	1		T44	2		T45	1
auto[1207959552:1342177279]	85	1			T26	1		T23	1		T74	1
auto[1342177280:1476395007]	114	1			T12	1		T26	1		T208	1
auto[1476395008:1610612735]	98	1			T1	1		T26	2		T44	5
auto[1610612736:1744830463]	95	1			T105	1		T210	1		T57	1
auto[1744830464:1879048191]	99	1			T130	1		T51	1		T97	1
auto[1879048192:2013265919]	114	1			T14	1		T18	1		T25	1
auto[2013265920:2147483647]	92	1			T208	1		T108	1		T44	1
auto[2147483648:2281701375]	101	1			T14	1		T35	1		T42	1
auto[2281701376:2415919103]	112	1			T12	1		T42	1		T27	1
auto[2415919104:2550136831]	112	1			T1	1		T28	1		T49	1
auto[2550136832:2684354559]	86	1			T51	1		T108	1		T44	3
auto[2684354560:2818572287]	90	1			T26	1		T28	1		T49	1
auto[2818572288:2952790015]	96	1			T26	1		T50	1		T97	1
auto[2952790016:3087007743]	87	1			T12	1		T14	1		T50	1
auto[3087007744:3221225471]	96	1			T31	1		T7	2		T85	1
auto[3221225472:3355443199]	91	1			T42	1		T22	1		T208	1
auto[3355443200:3489660927]	99	1			T35	1		T42	1		T49	1
auto[3489660928:3623878655]	103	1			T1	1		T25	1		T105	1
auto[3623878656:3758096383]	94	1			T2	1		T25	1		T210	1
auto[3758096384:3892314111]	87	1			T35	1		T25	1		T42	1
auto[3892314112:4026531839]	102	1			T18	1		T208	1		T24	1
auto[4026531840:4160749567]	98	1			T22	1		T74	1		T57	1
auto[4160749568:4294967295]	94	1			T130	1		T70	1		T108	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T105	1		T26	1		T74	1
auto[0:134217727]	auto[1]	53	1			T2	1		T18	1		T42	1
auto[134217728:268435455]	auto[0]	50	1			T14	1		T50	1		T45	1
auto[134217728:268435455]	auto[1]	47	1			T50	1		T45	1		T113	1
auto[268435456:402653183]	auto[0]	47	1			T49	1		T97	1		T198	1
auto[268435456:402653183]	auto[1]	59	1			T2	1		T105	1		T55	1
auto[402653184:536870911]	auto[0]	40	1			T108	1		T57	1		T198	1
auto[402653184:536870911]	auto[1]	47	1			T108	1		T74	1		T44	1
auto[536870912:671088639]	auto[0]	47	1			T1	1		T49	1		T210	1
auto[536870912:671088639]	auto[1]	51	1			T50	1		T37	1		T57	1
auto[671088640:805306367]	auto[0]	39	1			T49	1		T198	1		T72	1
auto[671088640:805306367]	auto[1]	52	1			T23	1		T49	1		T210	1
auto[805306368:939524095]	auto[0]	51	1			T22	1		T24	1		T49	2
auto[805306368:939524095]	auto[1]	56	1			T35	1		T74	1		T45	2
auto[939524096:1073741823]	auto[0]	52	1			T70	1		T210	1		T44	2
auto[939524096:1073741823]	auto[1]	55	1			T105	1		T70	1		T57	1
auto[1073741824:1207959551]	auto[0]	47	1			T44	1		T45	1		T92	1
auto[1073741824:1207959551]	auto[1]	53	1			T26	1		T44	1		T58	1
auto[1207959552:1342177279]	auto[0]	42	1			T45	1		T20	1		T90	1
auto[1207959552:1342177279]	auto[1]	43	1			T26	1		T23	1		T74	1
auto[1342177280:1476395007]	auto[0]	62	1			T26	1		T50	1		T55	1
auto[1342177280:1476395007]	auto[1]	52	1			T12	1		T208	1		T210	1
auto[1476395008:1610612735]	auto[0]	49	1			T26	1		T44	1		T8	1
auto[1476395008:1610612735]	auto[1]	49	1			T1	1		T26	1		T44	4
auto[1610612736:1744830463]	auto[0]	39	1			T105	1		T210	1		T57	1
auto[1610612736:1744830463]	auto[1]	56	1			T44	1		T121	1		T198	1
auto[1744830464:1879048191]	auto[0]	46	1			T51	1		T74	1		T45	1
auto[1744830464:1879048191]	auto[1]	53	1			T130	1		T97	1		T74	1
auto[1879048192:2013265919]	auto[0]	52	1			T14	1		T18	1		T25	1
auto[1879048192:2013265919]	auto[1]	62	1			T22	1		T49	1		T70	1
auto[2013265920:2147483647]	auto[0]	43	1			T108	1		T92	1		T189	1
auto[2013265920:2147483647]	auto[1]	49	1			T208	1		T44	1		T69	1
auto[2147483648:2281701375]	auto[0]	47	1			T42	1		T74	1		T57	1
auto[2147483648:2281701375]	auto[1]	54	1			T14	1		T35	1		T70	1
auto[2281701376:2415919103]	auto[0]	54	1			T42	1		T49	1		T74	1
auto[2281701376:2415919103]	auto[1]	58	1			T12	1		T27	1		T23	1
auto[2415919104:2550136831]	auto[0]	44	1			T28	1		T97	1		T44	1
auto[2415919104:2550136831]	auto[1]	68	1			T1	1		T49	1		T51	1
auto[2550136832:2684354559]	auto[0]	32	1			T108	1		T44	1		T207	1
auto[2550136832:2684354559]	auto[1]	54	1			T51	1		T44	2		T69	1
auto[2684354560:2818572287]	auto[0]	43	1			T26	1		T28	1		T49	1
auto[2684354560:2818572287]	auto[1]	47	1			T44	1		T45	5		T71	1
auto[2818572288:2952790015]	auto[0]	52	1			T26	1		T50	1		T57	1
auto[2818572288:2952790015]	auto[1]	44	1			T97	1		T44	1		T45	1
auto[2952790016:3087007743]	auto[0]	43	1			T12	1		T50	1		T57	1
auto[2952790016:3087007743]	auto[1]	44	1			T14	1		T68	1		T245	1
auto[3087007744:3221225471]	auto[0]	40	1			T7	2		T85	1		T8	1
auto[3087007744:3221225471]	auto[1]	56	1			T31	1		T44	2		T54	1
auto[3221225472:3355443199]	auto[0]	42	1			T208	1		T97	1		T211	1
auto[3221225472:3355443199]	auto[1]	49	1			T42	1		T22	1		T53	1
auto[3355443200:3489660927]	auto[0]	34	1			T211	1		T210	1		T44	1
auto[3355443200:3489660927]	auto[1]	65	1			T35	1		T42	1		T49	1
auto[3489660928:3623878655]	auto[0]	33	1			T25	1		T28	1		T44	1
auto[3489660928:3623878655]	auto[1]	70	1			T1	1		T105	1		T208	1
auto[3623878656:3758096383]	auto[0]	47	1			T210	1		T44	1		T198	1
auto[3623878656:3758096383]	auto[1]	47	1			T2	1		T25	1		T45	1
auto[3758096384:3892314111]	auto[0]	34	1			T35	1		T42	1		T24	1
auto[3758096384:3892314111]	auto[1]	53	1			T25	1		T44	1		T45	2
auto[3892314112:4026531839]	auto[0]	61	1			T18	1		T208	1		T45	1
auto[3892314112:4026531839]	auto[1]	41	1			T24	1		T50	1		T286	1
auto[4026531840:4160749567]	auto[0]	52	1			T22	1		T74	1		T57	1
auto[4026531840:4160749567]	auto[1]	46	1			T85	1		T44	1		T146	1
auto[4160749568:4294967295]	auto[0]	48	1			T70	1		T108	1		T71	1
auto[4160749568:4294967295]	auto[1]	46	1			T130	1		T44	1		T45	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1467

1

T2

1

T12

1

T14

1

auto[1]

1672

1

T1

4

T2

2

T12

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T49	1		T50	1		T44	2
auto[134217728:268435455]	88	1			T74	1		T121	1		T146	1
auto[268435456:402653183]	117	1			T25	1		T57	1		T44	1
auto[402653184:536870911]	123	1			T105	1		T26	1		T22	1
auto[536870912:671088639]	103	1			T2	1		T57	1		T44	2
auto[671088640:805306367]	91	1			T25	1		T130	1		T44	1
auto[805306368:939524095]	96	1			T42	1		T28	1		T74	1
auto[939524096:1073741823]	98	1			T12	1		T14	1		T49	1
auto[1073741824:1207959551]	93	1			T22	1		T208	2		T50	1
auto[1207959552:1342177279]	101	1			T14	1		T42	1		T26	1
auto[1342177280:1476395007]	98	1			T14	1		T35	1		T49	1
auto[1476395008:1610612735]	98	1			T2	1		T12	1		T24	1
auto[1610612736:1744830463]	102	1			T1	1		T35	1		T70	2
auto[1744830464:1879048191]	111	1			T105	1		T22	1		T49	1
auto[1879048192:2013265919]	92	1			T23	1		T130	1		T97	1
auto[2013265920:2147483647]	97	1			T25	1		T23	1		T24	1
auto[2147483648:2281701375]	91	1			T2	1		T18	1		T208	1
auto[2281701376:2415919103]	82	1			T50	1		T44	2		T198	1
auto[2415919104:2550136831]	104	1			T26	1		T50	2		T74	1
auto[2550136832:2684354559]	91	1			T26	1		T24	1		T49	2
auto[2684354560:2818572287]	93	1			T1	1		T23	1		T211	1
auto[2818572288:2952790015]	101	1			T12	1		T18	1		T49	1
auto[2952790016:3087007743]	124	1			T1	1		T49	1		T50	1
auto[3087007744:3221225471]	90	1			T105	1		T27	1		T22	1
auto[3221225472:3355443199]	96	1			T26	2		T130	1		T70	1
auto[3355443200:3489660927]	99	1			T1	1		T14	1		T42	1
auto[3489660928:3623878655]	81	1			T31	1		T97	1		T53	1
auto[3623878656:3758096383]	92	1			T18	1		T25	1		T42	1
auto[3758096384:3892314111]	102	1			T35	1		T208	1		T28	1
auto[3892314112:4026531839]	107	1			T42	1		T208	1		T97	1
auto[4026531840:4160749567]	98	1			T35	1		T105	1		T26	1
auto[4160749568:4294967295]	87	1			T42	1		T211	1		T37	1