Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.84 99.07 98.10 98.63 100.00 99.11 98.41 91.56


Total test records in report: 1073
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T1007 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1313130798 Mar 31 12:36:10 PM PDT 24 Mar 31 12:36:12 PM PDT 24 228727935 ps
T1008 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3913963006 Mar 31 12:36:40 PM PDT 24 Mar 31 12:36:45 PM PDT 24 13243358 ps
T1009 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3608171599 Mar 31 12:35:54 PM PDT 24 Mar 31 12:36:13 PM PDT 24 1280683137 ps
T1010 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1419622953 Mar 31 12:35:56 PM PDT 24 Mar 31 12:35:58 PM PDT 24 106492511 ps
T1011 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3334087617 Mar 31 12:36:04 PM PDT 24 Mar 31 12:36:06 PM PDT 24 11387637 ps
T1012 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2620434995 Mar 31 12:36:33 PM PDT 24 Mar 31 12:36:35 PM PDT 24 171806562 ps
T1013 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.551362866 Mar 31 12:36:16 PM PDT 24 Mar 31 12:36:19 PM PDT 24 33642017 ps
T160 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.806855163 Mar 31 12:37:39 PM PDT 24 Mar 31 12:37:45 PM PDT 24 257456483 ps
T1014 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.597035221 Mar 31 12:37:40 PM PDT 24 Mar 31 12:37:40 PM PDT 24 15884311 ps
T1015 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2929368453 Mar 31 12:36:20 PM PDT 24 Mar 31 12:36:22 PM PDT 24 16147351 ps
T1016 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2817586587 Mar 31 12:36:17 PM PDT 24 Mar 31 12:36:20 PM PDT 24 262487959 ps
T1017 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.583079256 Mar 31 12:36:16 PM PDT 24 Mar 31 12:36:24 PM PDT 24 203821003 ps
T1018 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1016388058 Mar 31 12:36:09 PM PDT 24 Mar 31 12:36:12 PM PDT 24 456939937 ps
T1019 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4236494825 Mar 31 12:37:40 PM PDT 24 Mar 31 12:37:41 PM PDT 24 16827938 ps
T1020 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1130612533 Mar 31 12:36:28 PM PDT 24 Mar 31 12:36:32 PM PDT 24 283401645 ps
T1021 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1486088818 Mar 31 12:36:00 PM PDT 24 Mar 31 12:36:01 PM PDT 24 29696531 ps
T1022 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2727316912 Mar 31 12:36:18 PM PDT 24 Mar 31 12:36:23 PM PDT 24 721925803 ps
T1023 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1712279419 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:35 PM PDT 24 30300338 ps
T1024 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2665548683 Mar 31 12:36:22 PM PDT 24 Mar 31 12:36:27 PM PDT 24 247134103 ps
T167 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3334471129 Mar 31 12:36:11 PM PDT 24 Mar 31 12:36:20 PM PDT 24 282114775 ps
T1025 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4191823799 Mar 31 12:36:28 PM PDT 24 Mar 31 12:36:29 PM PDT 24 13922898 ps
T1026 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3400973279 Mar 31 12:36:13 PM PDT 24 Mar 31 12:36:16 PM PDT 24 130901970 ps
T1027 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.480293900 Mar 31 12:35:58 PM PDT 24 Mar 31 12:35:59 PM PDT 24 23130309 ps
T1028 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1740520169 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:39 PM PDT 24 192148186 ps
T1029 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4122148654 Mar 31 12:36:31 PM PDT 24 Mar 31 12:36:32 PM PDT 24 28145192 ps
T1030 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3228580007 Mar 31 12:36:18 PM PDT 24 Mar 31 12:36:22 PM PDT 24 107548431 ps
T1031 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2386998797 Mar 31 12:36:20 PM PDT 24 Mar 31 12:36:22 PM PDT 24 32750049 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2506939432 Mar 31 12:36:22 PM PDT 24 Mar 31 12:36:25 PM PDT 24 48588562 ps
T1033 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3700396940 Mar 31 12:36:18 PM PDT 24 Mar 31 12:36:21 PM PDT 24 63200608 ps
T1034 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4244670800 Mar 31 12:36:25 PM PDT 24 Mar 31 12:36:28 PM PDT 24 73488423 ps
T1035 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3281073232 Mar 31 12:36:20 PM PDT 24 Mar 31 12:36:21 PM PDT 24 60542612 ps
T1036 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1036200247 Mar 31 12:36:07 PM PDT 24 Mar 31 12:36:08 PM PDT 24 68135161 ps
T1037 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.957208790 Mar 31 12:36:18 PM PDT 24 Mar 31 12:36:21 PM PDT 24 73226542 ps
T1038 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2138532379 Mar 31 12:36:40 PM PDT 24 Mar 31 12:36:42 PM PDT 24 49951803 ps
T1039 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2954903019 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:35 PM PDT 24 31269592 ps
T1040 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.65823661 Mar 31 12:36:16 PM PDT 24 Mar 31 12:36:18 PM PDT 24 46085336 ps
T157 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3194247903 Mar 31 12:36:19 PM PDT 24 Mar 31 12:36:23 PM PDT 24 59710769 ps
T1041 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2657466682 Mar 31 12:36:37 PM PDT 24 Mar 31 12:37:46 PM PDT 24 4225653772 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2937010951 Mar 31 12:36:04 PM PDT 24 Mar 31 12:36:06 PM PDT 24 27147632 ps
T1043 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3707205263 Mar 31 12:36:21 PM PDT 24 Mar 31 12:36:22 PM PDT 24 8938933 ps
T1044 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2760215031 Mar 31 12:36:20 PM PDT 24 Mar 31 12:36:20 PM PDT 24 12747416 ps
T1045 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3361953575 Mar 31 12:36:36 PM PDT 24 Mar 31 12:36:37 PM PDT 24 11029423 ps
T1046 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2672029795 Mar 31 12:36:38 PM PDT 24 Mar 31 12:36:42 PM PDT 24 215682286 ps
T1047 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1035331972 Mar 31 12:36:03 PM PDT 24 Mar 31 12:36:05 PM PDT 24 26921444 ps
T1048 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2440597242 Mar 31 12:36:40 PM PDT 24 Mar 31 12:36:42 PM PDT 24 186854742 ps
T1049 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1054207386 Mar 31 12:36:35 PM PDT 24 Mar 31 12:36:37 PM PDT 24 42081940 ps
T1050 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4158130028 Mar 31 12:36:11 PM PDT 24 Mar 31 12:36:13 PM PDT 24 49016974 ps
T1051 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1029101678 Mar 31 12:36:20 PM PDT 24 Mar 31 12:36:21 PM PDT 24 41093928 ps
T1052 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1250274501 Mar 31 12:36:17 PM PDT 24 Mar 31 12:36:18 PM PDT 24 15622668 ps
T1053 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2811202694 Mar 31 12:36:27 PM PDT 24 Mar 31 12:36:36 PM PDT 24 1183879713 ps
T1054 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2818851904 Mar 31 12:36:20 PM PDT 24 Mar 31 12:36:24 PM PDT 24 175757251 ps
T155 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3495798770 Mar 31 12:35:55 PM PDT 24 Mar 31 12:36:02 PM PDT 24 317740934 ps
T1055 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1992225914 Mar 31 12:36:27 PM PDT 24 Mar 31 12:36:29 PM PDT 24 148046108 ps
T1056 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1976457181 Mar 31 12:36:12 PM PDT 24 Mar 31 12:36:22 PM PDT 24 1518459174 ps
T156 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.213843284 Mar 31 12:37:39 PM PDT 24 Mar 31 12:37:45 PM PDT 24 405624942 ps
T1057 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2258769360 Mar 31 12:36:35 PM PDT 24 Mar 31 12:36:37 PM PDT 24 244504955 ps
T1058 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1972840933 Mar 31 12:36:19 PM PDT 24 Mar 31 12:36:20 PM PDT 24 14129943 ps
T1059 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3527924869 Mar 31 12:36:34 PM PDT 24 Mar 31 12:36:36 PM PDT 24 25171579 ps
T1060 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3065150348 Mar 31 12:37:24 PM PDT 24 Mar 31 12:37:25 PM PDT 24 10445965 ps
T1061 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1740977716 Mar 31 12:36:20 PM PDT 24 Mar 31 12:36:21 PM PDT 24 20053803 ps
T1062 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1722917821 Mar 31 12:36:08 PM PDT 24 Mar 31 12:36:10 PM PDT 24 39853624 ps
T1063 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1191313123 Mar 31 12:36:39 PM PDT 24 Mar 31 12:36:40 PM PDT 24 13696688 ps
T1064 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.610449292 Mar 31 12:36:05 PM PDT 24 Mar 31 12:36:09 PM PDT 24 71534490 ps
T1065 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3511594388 Mar 31 12:36:05 PM PDT 24 Mar 31 12:36:08 PM PDT 24 44853414 ps
T1066 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.361582277 Mar 31 12:36:28 PM PDT 24 Mar 31 12:36:29 PM PDT 24 13935929 ps
T1067 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2440931527 Mar 31 12:36:14 PM PDT 24 Mar 31 12:36:17 PM PDT 24 31737688 ps
T1068 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2177558370 Mar 31 12:36:20 PM PDT 24 Mar 31 12:36:21 PM PDT 24 20129533 ps
T1069 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4270987852 Mar 31 12:36:27 PM PDT 24 Mar 31 12:36:30 PM PDT 24 114149744 ps
T1070 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2319687504 Mar 31 12:36:15 PM PDT 24 Mar 31 12:36:16 PM PDT 24 27643379 ps
T1071 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4166544665 Mar 31 12:36:22 PM PDT 24 Mar 31 12:36:24 PM PDT 24 20493183 ps
T1072 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.662884916 Mar 31 12:36:17 PM PDT 24 Mar 31 12:36:19 PM PDT 24 383993379 ps
T151 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1086062448 Mar 31 12:36:05 PM PDT 24 Mar 31 12:36:18 PM PDT 24 1276445131 ps
T1073 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2291855974 Mar 31 12:36:40 PM PDT 24 Mar 31 12:36:42 PM PDT 24 22888988 ps

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2242043386
Short name T1
Test name
Test status
Simulation time 3366363427 ps
CPU time 38 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:56:12 PM PDT 24
Peak memory 214776 kb
Host smart-88bc18ff-38cc-4326-a100-272ab67d0bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242043386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2242043386
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.280548784
Short name T44
Test name
Test status
Simulation time 3888972725 ps
CPU time 91.35 seconds
Started Mar 31 03:55:44 PM PDT 24
Finished Mar 31 03:57:15 PM PDT 24
Peak memory 217704 kb
Host smart-a724c3a1-aa98-4f42-95e3-3c010b812eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280548784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.280548784
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2535484680
Short name T49
Test name
Test status
Simulation time 481526303 ps
CPU time 8.64 seconds
Started Mar 31 03:55:48 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 223004 kb
Host smart-8adb9ae2-0a19-47ae-9b1f-3d8a3e4f5a99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535484680 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2535484680
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1873308232
Short name T5
Test name
Test status
Simulation time 1206677625 ps
CPU time 10.68 seconds
Started Mar 31 03:54:12 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 231152 kb
Host smart-e7db226a-bc40-49ee-b3b6-95a726b2e3b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873308232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1873308232
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2875254206
Short name T58
Test name
Test status
Simulation time 570283188 ps
CPU time 21.07 seconds
Started Mar 31 03:55:51 PM PDT 24
Finished Mar 31 03:56:12 PM PDT 24
Peak memory 223000 kb
Host smart-aa074302-e363-4788-b506-5c36aad64a1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875254206 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2875254206
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1893847036
Short name T2
Test name
Test status
Simulation time 188621802 ps
CPU time 10.16 seconds
Started Mar 31 03:54:56 PM PDT 24
Finished Mar 31 03:55:07 PM PDT 24
Peak memory 215332 kb
Host smart-ac7151e6-a568-4cee-85ef-d047d49fd057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893847036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1893847036
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3866987049
Short name T45
Test name
Test status
Simulation time 1983937079 ps
CPU time 55.7 seconds
Started Mar 31 03:56:00 PM PDT 24
Finished Mar 31 03:56:55 PM PDT 24
Peak memory 216264 kb
Host smart-afcfde21-dbab-4d93-a2e0-113ade115a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866987049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3866987049
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4165337513
Short name T7
Test name
Test status
Simulation time 111574976 ps
CPU time 4.98 seconds
Started Mar 31 03:54:32 PM PDT 24
Finished Mar 31 03:54:37 PM PDT 24
Peak memory 216884 kb
Host smart-1fa41dc1-a0f2-454a-96ae-e5099759aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165337513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4165337513
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1038792312
Short name T118
Test name
Test status
Simulation time 1883851934 ps
CPU time 13.59 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:49 PM PDT 24
Peak memory 220556 kb
Host smart-2fc9ad19-eab0-4187-a0ac-544400b226f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038792312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1038792312
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1992557420
Short name T14
Test name
Test status
Simulation time 162742166 ps
CPU time 3.07 seconds
Started Mar 31 03:55:28 PM PDT 24
Finished Mar 31 03:55:32 PM PDT 24
Peak memory 210344 kb
Host smart-dab803fe-d7e9-4328-8d97-625b2628ada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992557420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1992557420
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.4038903287
Short name T132
Test name
Test status
Simulation time 202448803 ps
CPU time 10.49 seconds
Started Mar 31 03:55:58 PM PDT 24
Finished Mar 31 03:56:09 PM PDT 24
Peak memory 223036 kb
Host smart-d72326cb-8149-47c1-844e-fd245ecf0559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038903287 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.4038903287
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2182549134
Short name T52
Test name
Test status
Simulation time 26981195801 ps
CPU time 332.64 seconds
Started Mar 31 03:54:44 PM PDT 24
Finished Mar 31 04:00:16 PM PDT 24
Peak memory 222984 kb
Host smart-6fec6bed-278d-422b-8935-0574638a612a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182549134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2182549134
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3604427656
Short name T137
Test name
Test status
Simulation time 1000681325 ps
CPU time 16.12 seconds
Started Mar 31 03:54:52 PM PDT 24
Finished Mar 31 03:55:08 PM PDT 24
Peak memory 215912 kb
Host smart-26c06fb4-a243-4afa-8a0b-43edefc59a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604427656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3604427656
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.837246909
Short name T189
Test name
Test status
Simulation time 1743985103 ps
CPU time 5.63 seconds
Started Mar 31 03:54:15 PM PDT 24
Finished Mar 31 03:54:21 PM PDT 24
Peak memory 214592 kb
Host smart-72360158-4cb2-4480-802a-9c45986a2b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837246909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.837246909
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3069954329
Short name T427
Test name
Test status
Simulation time 289450376 ps
CPU time 15.79 seconds
Started Mar 31 03:55:44 PM PDT 24
Finished Mar 31 03:56:00 PM PDT 24
Peak memory 215016 kb
Host smart-375dc179-bc81-4e31-ab14-0e827ce42b33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3069954329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3069954329
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3131240764
Short name T198
Test name
Test status
Simulation time 1243938575 ps
CPU time 10.54 seconds
Started Mar 31 03:55:32 PM PDT 24
Finished Mar 31 03:55:43 PM PDT 24
Peak memory 214680 kb
Host smart-4b4d808f-183e-4924-b02a-e50b10737a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131240764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3131240764
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.114400506
Short name T344
Test name
Test status
Simulation time 6152815635 ps
CPU time 86.53 seconds
Started Mar 31 03:55:24 PM PDT 24
Finished Mar 31 03:56:52 PM PDT 24
Peak memory 216320 kb
Host smart-aa6d9465-7108-411a-a7cc-051b356955ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114400506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.114400506
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.120233797
Short name T50
Test name
Test status
Simulation time 8732326538 ps
CPU time 26.17 seconds
Started Mar 31 03:54:36 PM PDT 24
Finished Mar 31 03:55:02 PM PDT 24
Peak memory 214864 kb
Host smart-4d834e79-f8d6-4582-93dc-f69710d57dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120233797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.120233797
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.957471814
Short name T376
Test name
Test status
Simulation time 276204950 ps
CPU time 4.55 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 215920 kb
Host smart-38178f58-0d24-4fd8-abc7-4614fdc46a46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957471814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.957471814
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1999051019
Short name T19
Test name
Test status
Simulation time 467347577 ps
CPU time 3.44 seconds
Started Mar 31 03:54:05 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 222216 kb
Host smart-4c0a382c-a2b6-4025-a0ce-fee32ed5fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999051019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1999051019
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2723027591
Short name T26
Test name
Test status
Simulation time 2441580999 ps
CPU time 59.23 seconds
Started Mar 31 03:54:58 PM PDT 24
Finished Mar 31 03:55:58 PM PDT 24
Peak memory 220540 kb
Host smart-b549449e-5fc7-47fa-a39f-a1db00c77476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723027591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2723027591
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3368298767
Short name T284
Test name
Test status
Simulation time 156693562 ps
CPU time 8.75 seconds
Started Mar 31 03:55:37 PM PDT 24
Finished Mar 31 03:55:46 PM PDT 24
Peak memory 215120 kb
Host smart-b1f4719b-cd18-428a-9893-3dfcd91986c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368298767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3368298767
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3314160470
Short name T13
Test name
Test status
Simulation time 94045745 ps
CPU time 2.04 seconds
Started Mar 31 03:55:03 PM PDT 24
Finished Mar 31 03:55:05 PM PDT 24
Peak memory 210532 kb
Host smart-072ff0f8-8a33-4be6-af20-988423ec8385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314160470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3314160470
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.669801615
Short name T123
Test name
Test status
Simulation time 708792266 ps
CPU time 4.85 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:44 PM PDT 24
Peak memory 214208 kb
Host smart-41da788b-c8d1-4681-a3a4-f9215fb38d36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669801615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.669801615
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4255077371
Short name T146
Test name
Test status
Simulation time 492118776 ps
CPU time 7.8 seconds
Started Mar 31 03:54:27 PM PDT 24
Finished Mar 31 03:54:35 PM PDT 24
Peak memory 214872 kb
Host smart-9aec10b0-b43f-4bb3-a74f-bfe56dde50c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4255077371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4255077371
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1065393624
Short name T37
Test name
Test status
Simulation time 749583528 ps
CPU time 4.31 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 208688 kb
Host smart-08549a70-48b9-4abe-8565-b54c4f54e5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065393624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1065393624
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3162333932
Short name T98
Test name
Test status
Simulation time 596636198 ps
CPU time 8.28 seconds
Started Mar 31 03:54:42 PM PDT 24
Finished Mar 31 03:54:50 PM PDT 24
Peak memory 214704 kb
Host smart-d0012e01-54d4-467c-aada-82cc386f275a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162333932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3162333932
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1342180370
Short name T319
Test name
Test status
Simulation time 139708210 ps
CPU time 4.97 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 215688 kb
Host smart-5e71afe4-a670-456a-b15b-d4533377628e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342180370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1342180370
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1228465537
Short name T48
Test name
Test status
Simulation time 12328661016 ps
CPU time 37.91 seconds
Started Mar 31 03:55:47 PM PDT 24
Finished Mar 31 03:56:25 PM PDT 24
Peak memory 222240 kb
Host smart-e348a2fb-7156-462c-93c3-372b5360c41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228465537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1228465537
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1398235594
Short name T267
Test name
Test status
Simulation time 540785023 ps
CPU time 5.43 seconds
Started Mar 31 03:55:52 PM PDT 24
Finished Mar 31 03:55:58 PM PDT 24
Peak memory 222800 kb
Host smart-665434e0-9643-4a12-9eb2-820b6505f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398235594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1398235594
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1366184269
Short name T33
Test name
Test status
Simulation time 102143678 ps
CPU time 1.98 seconds
Started Mar 31 03:53:52 PM PDT 24
Finished Mar 31 03:53:54 PM PDT 24
Peak memory 208840 kb
Host smart-7c2107a4-dbea-4515-8d10-4572a071c47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366184269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1366184269
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2484267159
Short name T74
Test name
Test status
Simulation time 492026471 ps
CPU time 17.94 seconds
Started Mar 31 03:55:10 PM PDT 24
Finished Mar 31 03:55:29 PM PDT 24
Peak memory 217084 kb
Host smart-8c3ed4d1-03e8-4078-8006-45ef19ae7124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484267159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2484267159
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4087021262
Short name T175
Test name
Test status
Simulation time 119088601 ps
CPU time 3.39 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 218196 kb
Host smart-57b45e9b-5350-4dcd-b329-bec62ea859c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087021262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4087021262
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3202849815
Short name T399
Test name
Test status
Simulation time 188522313 ps
CPU time 3.57 seconds
Started Mar 31 03:55:20 PM PDT 24
Finished Mar 31 03:55:24 PM PDT 24
Peak memory 214684 kb
Host smart-d937d229-fc76-4cb9-84bf-73a7f92af497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202849815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3202849815
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.4143033547
Short name T107
Test name
Test status
Simulation time 264145300 ps
CPU time 4.42 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 208720 kb
Host smart-75644336-34cb-4508-85a5-9671d86df2c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143033547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.4143033547
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.213843284
Short name T156
Test name
Test status
Simulation time 405624942 ps
CPU time 5.7 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:45 PM PDT 24
Peak memory 209180 kb
Host smart-e000c5e6-ba27-40fb-b48a-9173745cf7d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213843284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.213843284
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3739497415
Short name T258
Test name
Test status
Simulation time 46272388 ps
CPU time 3.48 seconds
Started Mar 31 03:55:23 PM PDT 24
Finished Mar 31 03:55:27 PM PDT 24
Peak memory 214660 kb
Host smart-f424987d-083d-40f6-8913-f82b544cddb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739497415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3739497415
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2278884220
Short name T104
Test name
Test status
Simulation time 12770365 ps
CPU time 0.89 seconds
Started Mar 31 03:53:49 PM PDT 24
Finished Mar 31 03:53:50 PM PDT 24
Peak memory 206452 kb
Host smart-fea0ecdf-46fa-4bd2-9fba-649e3e294f75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278884220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2278884220
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.4290469887
Short name T223
Test name
Test status
Simulation time 451509284 ps
CPU time 22.02 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:56:17 PM PDT 24
Peak memory 222968 kb
Host smart-2942db24-acc9-407a-b63c-1ffd647b8dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290469887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.4290469887
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.735931508
Short name T245
Test name
Test status
Simulation time 9673155235 ps
CPU time 50.93 seconds
Started Mar 31 03:55:39 PM PDT 24
Finished Mar 31 03:56:30 PM PDT 24
Peak memory 222968 kb
Host smart-946973be-e847-448e-b7e9-147b6a97ceaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735931508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.735931508
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3310652119
Short name T29
Test name
Test status
Simulation time 223581928 ps
CPU time 3.05 seconds
Started Mar 31 03:55:06 PM PDT 24
Finished Mar 31 03:55:10 PM PDT 24
Peak memory 221980 kb
Host smart-b64d543c-fcff-4758-bb02-89dc54dc0702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310652119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3310652119
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1086062448
Short name T151
Test name
Test status
Simulation time 1276445131 ps
CPU time 13.31 seconds
Started Mar 31 12:36:05 PM PDT 24
Finished Mar 31 12:36:18 PM PDT 24
Peak memory 209468 kb
Host smart-8a4d6525-8ae2-443d-bb55-800fd5e720ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086062448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1086062448
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1690380297
Short name T108
Test name
Test status
Simulation time 341972467 ps
CPU time 3.41 seconds
Started Mar 31 03:54:38 PM PDT 24
Finished Mar 31 03:54:42 PM PDT 24
Peak memory 211556 kb
Host smart-b8d98656-152c-4486-b5a1-4e4e94d6eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690380297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1690380297
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3099304215
Short name T138
Test name
Test status
Simulation time 269862434 ps
CPU time 15.39 seconds
Started Mar 31 03:54:40 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 222896 kb
Host smart-297e31b1-1d86-434f-b0fe-7b909556cddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3099304215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3099304215
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.538478837
Short name T382
Test name
Test status
Simulation time 689341029 ps
CPU time 7.89 seconds
Started Mar 31 03:54:59 PM PDT 24
Finished Mar 31 03:55:07 PM PDT 24
Peak memory 215164 kb
Host smart-b228c64e-0493-4fa4-96bb-48232b542815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538478837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.538478837
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3615085257
Short name T72
Test name
Test status
Simulation time 7839286992 ps
CPU time 138.12 seconds
Started Mar 31 03:54:48 PM PDT 24
Finished Mar 31 03:57:07 PM PDT 24
Peak memory 223020 kb
Host smart-3d83b9fc-135c-4b51-a892-9314af791aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615085257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3615085257
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4044350008
Short name T152
Test name
Test status
Simulation time 813590273 ps
CPU time 8.77 seconds
Started Mar 31 12:36:31 PM PDT 24
Finished Mar 31 12:36:40 PM PDT 24
Peak memory 213952 kb
Host smart-df98fe71-7067-4e03-8e66-fdd1b96fcfd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044350008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4044350008
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3965442144
Short name T9
Test name
Test status
Simulation time 336733031 ps
CPU time 3 seconds
Started Mar 31 03:55:53 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 218364 kb
Host smart-1946f683-1377-47df-a4d8-af07db99dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965442144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3965442144
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3261570380
Short name T238
Test name
Test status
Simulation time 634684436 ps
CPU time 25.23 seconds
Started Mar 31 03:54:32 PM PDT 24
Finished Mar 31 03:54:57 PM PDT 24
Peak memory 222944 kb
Host smart-7c157223-8a52-4f9c-8b30-e5305d072496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261570380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3261570380
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.681071111
Short name T66
Test name
Test status
Simulation time 1779757860 ps
CPU time 20.13 seconds
Started Mar 31 03:55:42 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 220796 kb
Host smart-66708298-6721-445c-8f00-ee5fbb680537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681071111 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.681071111
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3846732471
Short name T332
Test name
Test status
Simulation time 5624632215 ps
CPU time 55.7 seconds
Started Mar 31 03:56:21 PM PDT 24
Finished Mar 31 03:57:17 PM PDT 24
Peak memory 217220 kb
Host smart-22585075-29ad-4379-a777-b3aed93b90d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846732471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3846732471
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1510682700
Short name T95
Test name
Test status
Simulation time 549259103 ps
CPU time 6.07 seconds
Started Mar 31 03:54:36 PM PDT 24
Finished Mar 31 03:54:42 PM PDT 24
Peak memory 214600 kb
Host smart-d96a4749-f7e7-4c74-8610-fd6834637447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510682700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1510682700
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.954196939
Short name T169
Test name
Test status
Simulation time 308189959 ps
CPU time 8.3 seconds
Started Mar 31 03:55:12 PM PDT 24
Finished Mar 31 03:55:20 PM PDT 24
Peak memory 217116 kb
Host smart-907c0381-8358-47a1-a5a7-7c2c3b027eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954196939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.954196939
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.454415298
Short name T172
Test name
Test status
Simulation time 172920471 ps
CPU time 3.73 seconds
Started Mar 31 03:55:49 PM PDT 24
Finished Mar 31 03:55:52 PM PDT 24
Peak memory 217432 kb
Host smart-b72171b3-1764-4749-8d69-42f5e66a2b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454415298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.454415298
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2678846085
Short name T170
Test name
Test status
Simulation time 58657766 ps
CPU time 3.51 seconds
Started Mar 31 03:54:20 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 217880 kb
Host smart-1e96a2aa-3613-4134-baf4-4488044aca50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678846085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2678846085
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.929959563
Short name T249
Test name
Test status
Simulation time 125969162 ps
CPU time 6.32 seconds
Started Mar 31 03:54:37 PM PDT 24
Finished Mar 31 03:54:44 PM PDT 24
Peak memory 211164 kb
Host smart-82c522c7-126d-40f9-9f50-d2bd833b8b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929959563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.929959563
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3840883021
Short name T298
Test name
Test status
Simulation time 27255566 ps
CPU time 2.47 seconds
Started Mar 31 03:54:55 PM PDT 24
Finished Mar 31 03:54:58 PM PDT 24
Peak memory 214612 kb
Host smart-fe9db209-db86-433c-8f2e-239b757a7abc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3840883021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3840883021
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1841301235
Short name T283
Test name
Test status
Simulation time 1720776194 ps
CPU time 45.32 seconds
Started Mar 31 03:55:11 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 216392 kb
Host smart-8295ce23-942c-4a77-ba56-d32246f29832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841301235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1841301235
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3127109424
Short name T314
Test name
Test status
Simulation time 3448697419 ps
CPU time 32.13 seconds
Started Mar 31 03:55:31 PM PDT 24
Finished Mar 31 03:56:04 PM PDT 24
Peak memory 221364 kb
Host smart-56e3f896-e3f5-4ee6-a45e-eec8d168f7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127109424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3127109424
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1949365218
Short name T392
Test name
Test status
Simulation time 161776420 ps
CPU time 3.9 seconds
Started Mar 31 03:54:17 PM PDT 24
Finished Mar 31 03:54:21 PM PDT 24
Peak memory 210736 kb
Host smart-47aa9e1b-ff91-4562-9805-84e5c21be119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949365218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1949365218
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3334471129
Short name T167
Test name
Test status
Simulation time 282114775 ps
CPU time 9.46 seconds
Started Mar 31 12:36:11 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 209116 kb
Host smart-98fe4027-e0fe-43b5-a2da-462db790252a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334471129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3334471129
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3071568292
Short name T173
Test name
Test status
Simulation time 133579790 ps
CPU time 5.48 seconds
Started Mar 31 03:55:11 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 223020 kb
Host smart-2e4a7052-2470-4895-90d5-a8681cac60ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071568292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3071568292
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2855892289
Short name T209
Test name
Test status
Simulation time 520774859 ps
CPU time 6.08 seconds
Started Mar 31 03:53:59 PM PDT 24
Finished Mar 31 03:54:06 PM PDT 24
Peak memory 211200 kb
Host smart-81ae617c-fced-4086-b822-ae32d7a065df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855892289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2855892289
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.851491885
Short name T94
Test name
Test status
Simulation time 428287016 ps
CPU time 3.94 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:27 PM PDT 24
Peak memory 209400 kb
Host smart-1d920d90-c817-40ca-9da9-719bfa4af06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851491885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.851491885
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2296234732
Short name T360
Test name
Test status
Simulation time 141024267 ps
CPU time 3.3 seconds
Started Mar 31 03:54:39 PM PDT 24
Finished Mar 31 03:54:42 PM PDT 24
Peak memory 210448 kb
Host smart-33894de0-53b3-4930-be52-664bafff73c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296234732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2296234732
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2000756159
Short name T419
Test name
Test status
Simulation time 2027583296 ps
CPU time 8.27 seconds
Started Mar 31 03:54:41 PM PDT 24
Finished Mar 31 03:54:50 PM PDT 24
Peak memory 214616 kb
Host smart-f0f5397e-ec11-49f3-bd87-75cfbb078f07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000756159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2000756159
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.957690357
Short name T271
Test name
Test status
Simulation time 901666306 ps
CPU time 48.21 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 216384 kb
Host smart-fcfd5772-e60e-4c18-a6a3-c413e7728a85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957690357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.957690357
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3785545061
Short name T154
Test name
Test status
Simulation time 464427579 ps
CPU time 9.21 seconds
Started Mar 31 12:36:15 PM PDT 24
Finished Mar 31 12:36:25 PM PDT 24
Peak memory 209120 kb
Host smart-3d73a041-41b5-4bb9-87a8-26a7f195928d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785545061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3785545061
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.4239470029
Short name T55
Test name
Test status
Simulation time 108145237 ps
CPU time 3.96 seconds
Started Mar 31 03:54:15 PM PDT 24
Finished Mar 31 03:54:19 PM PDT 24
Peak memory 218168 kb
Host smart-35dd1741-299f-40d4-b12d-865cadfc473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239470029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.4239470029
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4065598448
Short name T171
Test name
Test status
Simulation time 629428633 ps
CPU time 3.37 seconds
Started Mar 31 03:55:42 PM PDT 24
Finished Mar 31 03:55:46 PM PDT 24
Peak memory 216984 kb
Host smart-9174677a-6190-413e-8f7c-fbd66dfd7440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065598448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4065598448
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3021159210
Short name T316
Test name
Test status
Simulation time 2153485302 ps
CPU time 25.34 seconds
Started Mar 31 03:54:07 PM PDT 24
Finished Mar 31 03:54:33 PM PDT 24
Peak memory 222440 kb
Host smart-77e0f97b-af38-436f-9860-7ffb34d9289f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021159210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3021159210
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2260222567
Short name T356
Test name
Test status
Simulation time 157298778 ps
CPU time 3.35 seconds
Started Mar 31 03:54:49 PM PDT 24
Finished Mar 31 03:54:53 PM PDT 24
Peak memory 222744 kb
Host smart-bdd0f7ff-f65c-4249-b409-d38a4295e8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260222567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2260222567
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1940212694
Short name T121
Test name
Test status
Simulation time 214458175 ps
CPU time 3.82 seconds
Started Mar 31 03:56:19 PM PDT 24
Finished Mar 31 03:56:24 PM PDT 24
Peak memory 214540 kb
Host smart-60160a48-cff1-4ee1-bbce-6a74649f27d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940212694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1940212694
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2689122238
Short name T221
Test name
Test status
Simulation time 2267401489 ps
CPU time 40.8 seconds
Started Mar 31 03:55:04 PM PDT 24
Finished Mar 31 03:55:45 PM PDT 24
Peak memory 221940 kb
Host smart-fdd9662e-7f37-4e0e-be4b-2a8bc30d2618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689122238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2689122238
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.4031060617
Short name T386
Test name
Test status
Simulation time 317262714 ps
CPU time 10.47 seconds
Started Mar 31 03:55:06 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 222824 kb
Host smart-aa3bd528-664f-4cfa-9f03-d8c3d71b9f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031060617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4031060617
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2257198938
Short name T269
Test name
Test status
Simulation time 2155433907 ps
CPU time 62.11 seconds
Started Mar 31 03:55:05 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 225120 kb
Host smart-4a65e90e-41ff-4963-8b75-67eecaef6842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257198938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2257198938
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.762201183
Short name T362
Test name
Test status
Simulation time 1857043875 ps
CPU time 25.5 seconds
Started Mar 31 03:55:29 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 215588 kb
Host smart-6941f4ea-a69a-42c7-9a7e-bcb826057dff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=762201183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.762201183
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3387868080
Short name T205
Test name
Test status
Simulation time 1988750226 ps
CPU time 10.17 seconds
Started Mar 31 03:54:09 PM PDT 24
Finished Mar 31 03:54:20 PM PDT 24
Peak memory 214564 kb
Host smart-67386233-6a2c-4e3e-8731-10196cfd2cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387868080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3387868080
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4198705973
Short name T459
Test name
Test status
Simulation time 8068801462 ps
CPU time 40.9 seconds
Started Mar 31 03:54:08 PM PDT 24
Finished Mar 31 03:54:50 PM PDT 24
Peak memory 208680 kb
Host smart-4149f6f2-d0dc-4456-af6c-93c9a7e651a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198705973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4198705973
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3495798770
Short name T155
Test name
Test status
Simulation time 317740934 ps
CPU time 6.72 seconds
Started Mar 31 12:35:55 PM PDT 24
Finished Mar 31 12:36:02 PM PDT 24
Peak memory 214040 kb
Host smart-3c937788-209d-4713-9a03-7e35b969fda4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495798770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3495798770
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2008812799
Short name T149
Test name
Test status
Simulation time 1272663263 ps
CPU time 13.62 seconds
Started Mar 31 12:36:11 PM PDT 24
Finished Mar 31 12:36:25 PM PDT 24
Peak memory 209224 kb
Host smart-e8965f9a-b9b9-436b-a1f0-4f61971d4bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008812799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2008812799
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2657466682
Short name T1041
Test name
Test status
Simulation time 4225653772 ps
CPU time 68.06 seconds
Started Mar 31 12:36:37 PM PDT 24
Finished Mar 31 12:37:46 PM PDT 24
Peak memory 214584 kb
Host smart-8175b1d4-0587-49c9-ae91-33c6b586490c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657466682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2657466682
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3622339581
Short name T161
Test name
Test status
Simulation time 297840977 ps
CPU time 7.9 seconds
Started Mar 31 12:36:21 PM PDT 24
Finished Mar 31 12:36:30 PM PDT 24
Peak memory 209188 kb
Host smart-47cdd5b4-9836-488c-99af-16349e347d13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622339581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3622339581
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2891035723
Short name T150
Test name
Test status
Simulation time 411031159 ps
CPU time 8.22 seconds
Started Mar 31 12:36:22 PM PDT 24
Finished Mar 31 12:36:31 PM PDT 24
Peak memory 213988 kb
Host smart-671dc2f9-e45c-44e5-b3cf-674817c124e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891035723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2891035723
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.85081882
Short name T176
Test name
Test status
Simulation time 3741570509 ps
CPU time 11.49 seconds
Started Mar 31 03:55:27 PM PDT 24
Finished Mar 31 03:55:39 PM PDT 24
Peak memory 223164 kb
Host smart-be6aa45f-6e99-4bef-89f0-93f8bc222203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85081882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.85081882
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3043570936
Short name T178
Test name
Test status
Simulation time 3208227280 ps
CPU time 22.47 seconds
Started Mar 31 03:54:36 PM PDT 24
Finished Mar 31 03:54:58 PM PDT 24
Peak memory 218132 kb
Host smart-dfafb9a3-cc7c-40e8-b218-10a6f7ceac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043570936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3043570936
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1233110296
Short name T75
Test name
Test status
Simulation time 2692901576 ps
CPU time 50.38 seconds
Started Mar 31 03:56:13 PM PDT 24
Finished Mar 31 03:57:04 PM PDT 24
Peak memory 217540 kb
Host smart-85b760d2-6281-44f0-bc9f-f54bf312d447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233110296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1233110296
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3764102278
Short name T433
Test name
Test status
Simulation time 206550476 ps
CPU time 2.95 seconds
Started Mar 31 03:53:56 PM PDT 24
Finished Mar 31 03:54:00 PM PDT 24
Peak memory 214700 kb
Host smart-bac32efc-8e11-458d-be72-c07e88f8c1b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764102278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3764102278
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4227623413
Short name T422
Test name
Test status
Simulation time 57386682 ps
CPU time 3.6 seconds
Started Mar 31 03:54:17 PM PDT 24
Finished Mar 31 03:54:20 PM PDT 24
Peak memory 214736 kb
Host smart-467dcf03-8144-4d9f-920a-5aef922a4882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227623413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4227623413
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3159266035
Short name T232
Test name
Test status
Simulation time 624642941 ps
CPU time 12.15 seconds
Started Mar 31 03:54:34 PM PDT 24
Finished Mar 31 03:54:46 PM PDT 24
Peak memory 215508 kb
Host smart-895d4261-dfd0-4a97-b7d1-b239ab34b099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159266035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3159266035
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sideload.510481319
Short name T351
Test name
Test status
Simulation time 209109317 ps
CPU time 3.43 seconds
Started Mar 31 03:54:28 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 206960 kb
Host smart-7a26c250-de7f-4638-a050-23f935f12fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510481319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.510481319
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2279722346
Short name T3
Test name
Test status
Simulation time 324076367 ps
CPU time 10.33 seconds
Started Mar 31 03:55:00 PM PDT 24
Finished Mar 31 03:55:11 PM PDT 24
Peak memory 208828 kb
Host smart-c399d683-7b85-43c1-a802-e408bc512b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279722346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2279722346
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_random.1102674590
Short name T842
Test name
Test status
Simulation time 1439748893 ps
CPU time 14.08 seconds
Started Mar 31 03:54:48 PM PDT 24
Finished Mar 31 03:55:02 PM PDT 24
Peak memory 219428 kb
Host smart-6a78ddbe-c609-4115-a220-f58b658887e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102674590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1102674590
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3407038784
Short name T261
Test name
Test status
Simulation time 265945005 ps
CPU time 5.13 seconds
Started Mar 31 03:54:08 PM PDT 24
Finished Mar 31 03:54:14 PM PDT 24
Peak memory 210440 kb
Host smart-e9d4f933-a71c-456e-9bc1-81c3e2abdfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407038784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3407038784
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2245871251
Short name T327
Test name
Test status
Simulation time 53314597 ps
CPU time 3.67 seconds
Started Mar 31 03:54:57 PM PDT 24
Finished Mar 31 03:55:01 PM PDT 24
Peak memory 214716 kb
Host smart-5291ea28-018e-47c5-ab40-43ce89e8eac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245871251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2245871251
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1311044711
Short name T39
Test name
Test status
Simulation time 128876890 ps
CPU time 1.47 seconds
Started Mar 31 03:54:49 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 214700 kb
Host smart-49ed8ca4-4fc2-42d5-b5e8-b0282df08bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311044711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1311044711
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3755185433
Short name T675
Test name
Test status
Simulation time 44608224 ps
CPU time 2.15 seconds
Started Mar 31 03:55:06 PM PDT 24
Finished Mar 31 03:55:08 PM PDT 24
Peak memory 210024 kb
Host smart-03fb8f89-cc12-448a-b929-d2e5e46029ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755185433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3755185433
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.745292268
Short name T233
Test name
Test status
Simulation time 271863566 ps
CPU time 4.5 seconds
Started Mar 31 03:55:25 PM PDT 24
Finished Mar 31 03:55:31 PM PDT 24
Peak memory 210204 kb
Host smart-13c7fbc6-f4e8-4b16-8fae-e6e77a1ba758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745292268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.745292268
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2577469184
Short name T239
Test name
Test status
Simulation time 13059020464 ps
CPU time 71.76 seconds
Started Mar 31 03:54:02 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 217112 kb
Host smart-2725c4c8-68cc-4c5f-abd6-2b798a1aa954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577469184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2577469184
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1942683817
Short name T237
Test name
Test status
Simulation time 372718050 ps
CPU time 4.25 seconds
Started Mar 31 03:55:18 PM PDT 24
Finished Mar 31 03:55:23 PM PDT 24
Peak memory 222896 kb
Host smart-5b0c69f4-01f7-45d2-a7b3-63f06600a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942683817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1942683817
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3371672995
Short name T403
Test name
Test status
Simulation time 1134010491 ps
CPU time 27.97 seconds
Started Mar 31 03:55:29 PM PDT 24
Finished Mar 31 03:55:58 PM PDT 24
Peak memory 209728 kb
Host smart-db2b598b-7332-4d82-a69e-4f76e646e84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371672995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3371672995
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2606944357
Short name T34
Test name
Test status
Simulation time 1695107582 ps
CPU time 50.16 seconds
Started Mar 31 03:55:26 PM PDT 24
Finished Mar 31 03:56:16 PM PDT 24
Peak memory 232308 kb
Host smart-f6b266da-2a3f-4ed0-8fd3-b82c29fc84c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606944357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2606944357
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3743095680
Short name T373
Test name
Test status
Simulation time 89449500 ps
CPU time 1.49 seconds
Started Mar 31 03:55:15 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 207688 kb
Host smart-f3881fb3-0893-4892-9a2d-91c1ca5dfc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743095680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3743095680
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2970337627
Short name T333
Test name
Test status
Simulation time 431225013 ps
CPU time 9.01 seconds
Started Mar 31 03:55:32 PM PDT 24
Finished Mar 31 03:55:46 PM PDT 24
Peak memory 214636 kb
Host smart-fc33c3fb-5e82-4705-b21c-cbe1e9147b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970337627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2970337627
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2743791164
Short name T354
Test name
Test status
Simulation time 14659420354 ps
CPU time 112.23 seconds
Started Mar 31 03:55:21 PM PDT 24
Finished Mar 31 03:57:13 PM PDT 24
Peak memory 226324 kb
Host smart-efac6e73-7dcd-4589-b3b0-6852613d5697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743791164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2743791164
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.925708462
Short name T235
Test name
Test status
Simulation time 403401221 ps
CPU time 3.65 seconds
Started Mar 31 03:55:39 PM PDT 24
Finished Mar 31 03:55:43 PM PDT 24
Peak memory 220916 kb
Host smart-10b5341e-3177-4728-a1e3-b6033a4524c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925708462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.925708462
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1573608782
Short name T224
Test name
Test status
Simulation time 2072064353 ps
CPU time 23.06 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:55:41 PM PDT 24
Peak memory 222748 kb
Host smart-210d20f5-ca17-46a1-b3eb-24261c08c340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573608782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1573608782
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3680258226
Short name T186
Test name
Test status
Simulation time 31103591 ps
CPU time 2.59 seconds
Started Mar 31 03:56:01 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 214640 kb
Host smart-8315cff2-446a-4b5a-bca3-6acb536c7f0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3680258226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3680258226
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.362721255
Short name T174
Test name
Test status
Simulation time 1908984982 ps
CPU time 10.64 seconds
Started Mar 31 03:55:07 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 218232 kb
Host smart-4e4705d7-e3bd-4dd3-8f5c-947c8da01e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362721255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.362721255
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.965980011
Short name T961
Test name
Test status
Simulation time 640578443 ps
CPU time 8.98 seconds
Started Mar 31 12:35:55 PM PDT 24
Finished Mar 31 12:36:04 PM PDT 24
Peak memory 205900 kb
Host smart-2e2e1792-fc96-4332-b752-04aa6839865f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965980011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.965980011
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4200772465
Short name T934
Test name
Test status
Simulation time 5575955122 ps
CPU time 17.92 seconds
Started Mar 31 12:35:59 PM PDT 24
Finished Mar 31 12:36:17 PM PDT 24
Peak memory 205976 kb
Host smart-460236d5-f3ac-4678-8fa6-ad8826f1405d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200772465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4
200772465
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1353772389
Short name T927
Test name
Test status
Simulation time 359894820 ps
CPU time 1 seconds
Started Mar 31 12:36:06 PM PDT 24
Finished Mar 31 12:36:08 PM PDT 24
Peak memory 205512 kb
Host smart-a6c64527-4869-41ab-ae07-22a9d8e31e98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353772389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
353772389
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1419622953
Short name T1010
Test name
Test status
Simulation time 106492511 ps
CPU time 2.17 seconds
Started Mar 31 12:35:56 PM PDT 24
Finished Mar 31 12:35:58 PM PDT 24
Peak memory 214104 kb
Host smart-9fecb5d3-0f54-402d-8d9e-60839fef8d79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419622953 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1419622953
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2749997096
Short name T988
Test name
Test status
Simulation time 22301649 ps
CPU time 1.09 seconds
Started Mar 31 12:35:54 PM PDT 24
Finished Mar 31 12:35:55 PM PDT 24
Peak memory 205868 kb
Host smart-70399045-a448-4183-b977-358d1822152f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749997096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2749997096
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.666014117
Short name T996
Test name
Test status
Simulation time 30422777 ps
CPU time 0.77 seconds
Started Mar 31 12:35:56 PM PDT 24
Finished Mar 31 12:35:57 PM PDT 24
Peak memory 205456 kb
Host smart-b7414bfb-1ab5-4990-97af-fbb88697e3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666014117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.666014117
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1498966998
Short name T982
Test name
Test status
Simulation time 224751280 ps
CPU time 2.53 seconds
Started Mar 31 12:36:07 PM PDT 24
Finished Mar 31 12:36:10 PM PDT 24
Peak memory 205820 kb
Host smart-331d3132-fb45-414c-aa43-03c8e1707684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498966998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1498966998
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.916219331
Short name T978
Test name
Test status
Simulation time 256982653 ps
CPU time 4.15 seconds
Started Mar 31 12:36:06 PM PDT 24
Finished Mar 31 12:36:10 PM PDT 24
Peak memory 214264 kb
Host smart-08f94914-84e0-428a-8d50-975e4bf23c1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916219331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.916219331
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1877741531
Short name T963
Test name
Test status
Simulation time 258796566 ps
CPU time 9.24 seconds
Started Mar 31 12:36:08 PM PDT 24
Finished Mar 31 12:36:18 PM PDT 24
Peak memory 214364 kb
Host smart-60b89716-c7bf-48c2-bc4b-82a161522738
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877741531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1877741531
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1827553177
Short name T916
Test name
Test status
Simulation time 26419253 ps
CPU time 2.18 seconds
Started Mar 31 12:35:57 PM PDT 24
Finished Mar 31 12:35:59 PM PDT 24
Peak memory 216112 kb
Host smart-1d49f4c3-286c-4010-a69e-12fc23df0965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827553177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1827553177
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.4262299743
Short name T912
Test name
Test status
Simulation time 378506543 ps
CPU time 7.57 seconds
Started Mar 31 12:36:11 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 205720 kb
Host smart-8685c50d-32fd-4838-8169-dddb73b1c40d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262299743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.4
262299743
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3608171599
Short name T1009
Test name
Test status
Simulation time 1280683137 ps
CPU time 18.41 seconds
Started Mar 31 12:35:54 PM PDT 24
Finished Mar 31 12:36:13 PM PDT 24
Peak memory 205764 kb
Host smart-75f2849d-50ba-4698-9219-e0c41faffc64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608171599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
608171599
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.480293900
Short name T1027
Test name
Test status
Simulation time 23130309 ps
CPU time 0.91 seconds
Started Mar 31 12:35:58 PM PDT 24
Finished Mar 31 12:35:59 PM PDT 24
Peak memory 205596 kb
Host smart-3895b17d-6ba9-42b7-96d5-1c8788623a66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480293900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.480293900
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.694040063
Short name T148
Test name
Test status
Simulation time 98962032 ps
CPU time 1.41 seconds
Started Mar 31 12:36:10 PM PDT 24
Finished Mar 31 12:36:12 PM PDT 24
Peak memory 205880 kb
Host smart-ed752ead-8074-4ad8-99b2-a6e97666932f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694040063 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.694040063
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1486088818
Short name T1021
Test name
Test status
Simulation time 29696531 ps
CPU time 1.03 seconds
Started Mar 31 12:36:00 PM PDT 24
Finished Mar 31 12:36:01 PM PDT 24
Peak memory 205672 kb
Host smart-c64bbd6e-89e6-4735-b0d2-10c89ba806de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486088818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1486088818
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.48473633
Short name T999
Test name
Test status
Simulation time 36647112 ps
CPU time 0.71 seconds
Started Mar 31 12:35:56 PM PDT 24
Finished Mar 31 12:35:57 PM PDT 24
Peak memory 205404 kb
Host smart-670dedba-4e53-48ef-9d98-3920e4f7e2d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48473633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.48473633
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2196470096
Short name T974
Test name
Test status
Simulation time 180200049 ps
CPU time 2.49 seconds
Started Mar 31 12:36:07 PM PDT 24
Finished Mar 31 12:36:09 PM PDT 24
Peak memory 205824 kb
Host smart-ca275b2d-aa1d-4039-9e86-b03f15ffec72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196470096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2196470096
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2261259555
Short name T973
Test name
Test status
Simulation time 168840451 ps
CPU time 4.45 seconds
Started Mar 31 12:35:56 PM PDT 24
Finished Mar 31 12:36:00 PM PDT 24
Peak memory 222632 kb
Host smart-83a52e05-b237-4fed-917c-4c2ec9c0de55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261259555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2261259555
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3827042335
Short name T993
Test name
Test status
Simulation time 320729848 ps
CPU time 8.02 seconds
Started Mar 31 12:35:59 PM PDT 24
Finished Mar 31 12:36:07 PM PDT 24
Peak memory 214352 kb
Host smart-45607003-e6b4-4e8e-b691-3ed5c0cb31e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827042335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3827042335
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2582791457
Short name T990
Test name
Test status
Simulation time 140913825 ps
CPU time 2.43 seconds
Started Mar 31 12:35:58 PM PDT 24
Finished Mar 31 12:36:01 PM PDT 24
Peak memory 216388 kb
Host smart-6665777a-1ae5-43fa-844b-b94a2c5918ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582791457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2582791457
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1778885270
Short name T935
Test name
Test status
Simulation time 77084709 ps
CPU time 1.88 seconds
Started Mar 31 12:36:13 PM PDT 24
Finished Mar 31 12:36:16 PM PDT 24
Peak memory 214008 kb
Host smart-0989cfff-4b06-49bb-99f5-7af8a899fe30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778885270 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1778885270
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3252407100
Short name T1002
Test name
Test status
Simulation time 19446480 ps
CPU time 1.23 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 205832 kb
Host smart-745f94da-12a6-402b-86dc-919bb106e2f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252407100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3252407100
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.148881739
Short name T924
Test name
Test status
Simulation time 10382742 ps
CPU time 0.73 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:35 PM PDT 24
Peak memory 205476 kb
Host smart-b52e5281-4335-40fa-8fc2-cfa97b5d67ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148881739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.148881739
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4158130028
Short name T1050
Test name
Test status
Simulation time 49016974 ps
CPU time 1.39 seconds
Started Mar 31 12:36:11 PM PDT 24
Finished Mar 31 12:36:13 PM PDT 24
Peak memory 205800 kb
Host smart-c37b9b33-994b-4b23-8c5c-a1ba7cf72509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158130028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4158130028
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.302794345
Short name T998
Test name
Test status
Simulation time 127983834 ps
CPU time 1.59 seconds
Started Mar 31 12:36:30 PM PDT 24
Finished Mar 31 12:36:32 PM PDT 24
Peak memory 214276 kb
Host smart-633fb7f7-e055-438a-8554-4fc3faded846
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302794345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.302794345
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2884606501
Short name T119
Test name
Test status
Simulation time 283865108 ps
CPU time 6.61 seconds
Started Mar 31 12:36:14 PM PDT 24
Finished Mar 31 12:36:21 PM PDT 24
Peak memory 214244 kb
Host smart-95354567-5d71-4a39-a9a3-f58ca1f2e4f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884606501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2884606501
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2860359367
Short name T184
Test name
Test status
Simulation time 151265252 ps
CPU time 4.64 seconds
Started Mar 31 12:36:24 PM PDT 24
Finished Mar 31 12:36:29 PM PDT 24
Peak memory 214064 kb
Host smart-fe9e9545-bd14-4e3a-b247-f0bb5344b622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860359367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2860359367
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1869536691
Short name T981
Test name
Test status
Simulation time 154005808 ps
CPU time 2.19 seconds
Started Mar 31 12:36:14 PM PDT 24
Finished Mar 31 12:36:16 PM PDT 24
Peak memory 214112 kb
Host smart-f8f0bef7-1e5c-4dae-937b-edf68a79a160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869536691 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1869536691
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1191313123
Short name T1063
Test name
Test status
Simulation time 13696688 ps
CPU time 0.88 seconds
Started Mar 31 12:36:39 PM PDT 24
Finished Mar 31 12:36:40 PM PDT 24
Peak memory 205576 kb
Host smart-f947e079-9697-41f6-b35a-f4b74b73a4f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191313123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1191313123
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2319687504
Short name T1070
Test name
Test status
Simulation time 27643379 ps
CPU time 0.78 seconds
Started Mar 31 12:36:15 PM PDT 24
Finished Mar 31 12:36:16 PM PDT 24
Peak memory 205380 kb
Host smart-90e6851a-0853-40b9-8e2e-1aec7d73d2ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319687504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2319687504
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3072943331
Short name T141
Test name
Test status
Simulation time 259810638 ps
CPU time 4.05 seconds
Started Mar 31 12:36:12 PM PDT 24
Finished Mar 31 12:36:16 PM PDT 24
Peak memory 205784 kb
Host smart-5ca5ff4d-8ec1-4eca-8694-8cb91e4f049a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072943331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3072943331
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1740520169
Short name T1028
Test name
Test status
Simulation time 192148186 ps
CPU time 4.82 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:39 PM PDT 24
Peak memory 214296 kb
Host smart-f5484df4-68e0-4634-af30-d28cb620f040
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740520169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1740520169
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4212634959
Short name T989
Test name
Test status
Simulation time 220088537 ps
CPU time 7.35 seconds
Started Mar 31 12:36:12 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 214348 kb
Host smart-d1dbbcf6-8bf6-4714-a06d-f91e25cfc4a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212634959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.4212634959
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1123964758
Short name T908
Test name
Test status
Simulation time 252638777 ps
CPU time 2.18 seconds
Started Mar 31 12:36:12 PM PDT 24
Finished Mar 31 12:36:14 PM PDT 24
Peak memory 213904 kb
Host smart-06564d86-476c-4bd6-a820-4798e79e0027
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123964758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1123964758
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2954903019
Short name T1039
Test name
Test status
Simulation time 31269592 ps
CPU time 1.28 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:35 PM PDT 24
Peak memory 213976 kb
Host smart-399e32a5-7fbc-4215-8a82-3060e4a89729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954903019 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2954903019
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3736087417
Short name T967
Test name
Test status
Simulation time 101665309 ps
CPU time 1.19 seconds
Started Mar 31 12:36:30 PM PDT 24
Finished Mar 31 12:36:32 PM PDT 24
Peak memory 205788 kb
Host smart-29129848-19e8-4fb9-8ac9-2c6445345079
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736087417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3736087417
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3003880919
Short name T1003
Test name
Test status
Simulation time 10349274 ps
CPU time 0.72 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:34 PM PDT 24
Peak memory 205412 kb
Host smart-6098f7f3-2452-4e39-8659-4cdbbf0ac147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003880919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3003880919
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.95786172
Short name T947
Test name
Test status
Simulation time 81666663 ps
CPU time 1.29 seconds
Started Mar 31 12:36:17 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 205804 kb
Host smart-f33f5977-3442-4ec9-b8bc-f1e7dae67f9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95786172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sam
e_csr_outstanding.95786172
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2727316912
Short name T1022
Test name
Test status
Simulation time 721925803 ps
CPU time 4.86 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:23 PM PDT 24
Peak memory 222432 kb
Host smart-57481c55-b270-469a-8aa6-6ce0b938cced
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727316912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2727316912
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3838073033
Short name T124
Test name
Test status
Simulation time 510848583 ps
CPU time 10.55 seconds
Started Mar 31 12:36:32 PM PDT 24
Finished Mar 31 12:36:43 PM PDT 24
Peak memory 214352 kb
Host smart-4365f4e1-330c-4fea-aa25-859f869bd85e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838073033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3838073033
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3689776347
Short name T1006
Test name
Test status
Simulation time 1416246725 ps
CPU time 2.93 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 216120 kb
Host smart-a982f90f-cefd-4deb-ae2e-a652619b6ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689776347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3689776347
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.61040268
Short name T991
Test name
Test status
Simulation time 120923773 ps
CPU time 1.42 seconds
Started Mar 31 12:36:27 PM PDT 24
Finished Mar 31 12:36:28 PM PDT 24
Peak memory 214048 kb
Host smart-e3db1b1f-c95d-4f7d-9e8d-5a5744eef87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61040268 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.61040268
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1740977716
Short name T1061
Test name
Test status
Simulation time 20053803 ps
CPU time 0.89 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:21 PM PDT 24
Peak memory 205636 kb
Host smart-25a5a09d-4288-46c1-9cc2-5ecd37d25056
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740977716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1740977716
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1898047042
Short name T951
Test name
Test status
Simulation time 18820714 ps
CPU time 0.74 seconds
Started Mar 31 12:36:17 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 205428 kb
Host smart-eb266b15-d502-44f4-872d-26146ec740b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898047042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1898047042
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3527924869
Short name T1059
Test name
Test status
Simulation time 25171579 ps
CPU time 1.58 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:36 PM PDT 24
Peak memory 205944 kb
Host smart-3f4b0008-c8c5-4aef-af40-463d3803a4f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527924869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3527924869
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3228580007
Short name T1030
Test name
Test status
Simulation time 107548431 ps
CPU time 2.95 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 214420 kb
Host smart-25ecb51e-68be-4ff0-a0fc-52ba948d948f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228580007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3228580007
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.583079256
Short name T1017
Test name
Test status
Simulation time 203821003 ps
CPU time 7.54 seconds
Started Mar 31 12:36:16 PM PDT 24
Finished Mar 31 12:36:24 PM PDT 24
Peak memory 214356 kb
Host smart-4a12500c-e0d3-499e-ac7e-e99734ee3ab5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583079256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.583079256
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2817586587
Short name T1016
Test name
Test status
Simulation time 262487959 ps
CPU time 2.1 seconds
Started Mar 31 12:36:17 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 214000 kb
Host smart-24426653-4db0-40cf-82cb-e212b33bcd05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817586587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2817586587
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.339877502
Short name T153
Test name
Test status
Simulation time 157685851 ps
CPU time 6.34 seconds
Started Mar 31 12:36:16 PM PDT 24
Finished Mar 31 12:36:23 PM PDT 24
Peak memory 213872 kb
Host smart-3dc7d2f3-0cd3-4c77-b221-53304baee4cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339877502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.339877502
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.65823661
Short name T1040
Test name
Test status
Simulation time 46085336 ps
CPU time 1.63 seconds
Started Mar 31 12:36:16 PM PDT 24
Finished Mar 31 12:36:18 PM PDT 24
Peak memory 214144 kb
Host smart-5901cd38-197e-4148-aabd-3072ae51e11c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65823661 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.65823661
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2455646739
Short name T959
Test name
Test status
Simulation time 15136843 ps
CPU time 1.04 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:34 PM PDT 24
Peak memory 205728 kb
Host smart-f21e467d-874e-4883-8452-e13613e9ba5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455646739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2455646739
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.482037908
Short name T919
Test name
Test status
Simulation time 7505991 ps
CPU time 0.74 seconds
Started Mar 31 12:36:16 PM PDT 24
Finished Mar 31 12:36:17 PM PDT 24
Peak memory 205552 kb
Host smart-1c6560eb-ed9f-4b33-81a8-3854eedc102e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482037908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.482037908
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.551362866
Short name T1013
Test name
Test status
Simulation time 33642017 ps
CPU time 2.46 seconds
Started Mar 31 12:36:16 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 205924 kb
Host smart-bcab9d35-36cf-4d55-807c-4ba51a25a31b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551362866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.551362866
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3700396940
Short name T1033
Test name
Test status
Simulation time 63200608 ps
CPU time 2.5 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:21 PM PDT 24
Peak memory 214292 kb
Host smart-edffecb3-b952-42ee-a43e-5547778cb07e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700396940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3700396940
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2818851904
Short name T1054
Test name
Test status
Simulation time 175757251 ps
CPU time 3.97 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:24 PM PDT 24
Peak memory 222556 kb
Host smart-5ec68209-56bf-4eb9-8be3-44489873810d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818851904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2818851904
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1285589993
Short name T909
Test name
Test status
Simulation time 107282721 ps
CPU time 4.25 seconds
Started Mar 31 12:36:15 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 214124 kb
Host smart-cbb269bd-e890-4931-81a2-0a7f8e9c7299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285589993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1285589993
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2131581864
Short name T159
Test name
Test status
Simulation time 935410889 ps
CPU time 27.54 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:46 PM PDT 24
Peak memory 208988 kb
Host smart-d7714cb6-b187-46b0-92af-219d37106e07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131581864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2131581864
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1583268810
Short name T926
Test name
Test status
Simulation time 723393465 ps
CPU time 1.78 seconds
Started Mar 31 12:37:23 PM PDT 24
Finished Mar 31 12:37:27 PM PDT 24
Peak memory 204940 kb
Host smart-45b026a6-d9fb-400a-b68e-735c2ed7d88e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583268810 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1583268810
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2885716653
Short name T980
Test name
Test status
Simulation time 68210250 ps
CPU time 1.2 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 12:36:41 PM PDT 24
Peak memory 205732 kb
Host smart-1c2065fe-0b3d-4d97-86b9-c7802d9c687d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885716653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2885716653
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1250274501
Short name T1052
Test name
Test status
Simulation time 15622668 ps
CPU time 0.76 seconds
Started Mar 31 12:36:17 PM PDT 24
Finished Mar 31 12:36:18 PM PDT 24
Peak memory 205364 kb
Host smart-57344bb2-a041-45d1-8ef6-b8a8980ead74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250274501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1250274501
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.4157984645
Short name T1004
Test name
Test status
Simulation time 245974997 ps
CPU time 1.69 seconds
Started Mar 31 12:36:29 PM PDT 24
Finished Mar 31 12:36:31 PM PDT 24
Peak memory 205920 kb
Host smart-5071b8f1-e8b9-4631-970f-176dfd48660b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157984645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.4157984645
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2097764730
Short name T950
Test name
Test status
Simulation time 1643396000 ps
CPU time 5.24 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:26 PM PDT 24
Peak memory 214308 kb
Host smart-a05f5055-b3f1-41fc-876b-e1076f24b350
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097764730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2097764730
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3704728588
Short name T960
Test name
Test status
Simulation time 182963501 ps
CPU time 7.32 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:27 PM PDT 24
Peak memory 214268 kb
Host smart-6b1916c5-c781-4dbe-9024-0eff8c36adf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704728588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3704728588
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2774716958
Short name T942
Test name
Test status
Simulation time 153431201 ps
CPU time 5.68 seconds
Started Mar 31 12:36:13 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 213880 kb
Host smart-263b237d-352a-4e77-a9e9-d85c7e85f161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774716958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2774716958
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3194247903
Short name T157
Test name
Test status
Simulation time 59710769 ps
CPU time 3.39 seconds
Started Mar 31 12:36:19 PM PDT 24
Finished Mar 31 12:36:23 PM PDT 24
Peak memory 213996 kb
Host smart-5ee141d2-09bc-46f0-9a2c-042294e94b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194247903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3194247903
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2015233896
Short name T979
Test name
Test status
Simulation time 73326337 ps
CPU time 1.54 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 214100 kb
Host smart-7e9be4d7-0f43-4f61-815c-a774aa4a0992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015233896 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2015233896
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.662884916
Short name T1072
Test name
Test status
Simulation time 383993379 ps
CPU time 1.68 seconds
Started Mar 31 12:36:17 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 205820 kb
Host smart-5539e5b6-15a5-44d3-9b64-2fb28f5daac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662884916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.662884916
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3281073232
Short name T1035
Test name
Test status
Simulation time 60542612 ps
CPU time 0.87 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:21 PM PDT 24
Peak memory 205476 kb
Host smart-1bcd54c5-3d97-4784-8278-cbf5ebe7a528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281073232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3281073232
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.63996178
Short name T1000
Test name
Test status
Simulation time 59163596 ps
CPU time 2.14 seconds
Started Mar 31 12:36:19 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205860 kb
Host smart-9232cd6d-c932-4f4e-aeaa-1d102f9d10e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63996178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sam
e_csr_outstanding.63996178
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2620434995
Short name T1012
Test name
Test status
Simulation time 171806562 ps
CPU time 2.13 seconds
Started Mar 31 12:36:33 PM PDT 24
Finished Mar 31 12:36:35 PM PDT 24
Peak memory 214320 kb
Host smart-313fd18f-c9e0-4cc6-ac93-d93649c60573
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620434995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2620434995
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3461924891
Short name T201
Test name
Test status
Simulation time 305423148 ps
CPU time 2.85 seconds
Started Mar 31 12:36:27 PM PDT 24
Finished Mar 31 12:36:30 PM PDT 24
Peak memory 216268 kb
Host smart-38f28da7-6fa4-4b78-b083-cb84d2a39f08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461924891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3461924891
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1196452173
Short name T932
Test name
Test status
Simulation time 511659738 ps
CPU time 11.45 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:48 PM PDT 24
Peak memory 213824 kb
Host smart-dfc211b1-2724-48f9-9406-f66701bf5de4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196452173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1196452173
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2258769360
Short name T1057
Test name
Test status
Simulation time 244504955 ps
CPU time 1.26 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 206056 kb
Host smart-78091833-2bc0-4355-811d-6a7cbe7abad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258769360 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2258769360
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2929368453
Short name T1015
Test name
Test status
Simulation time 16147351 ps
CPU time 1.1 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205752 kb
Host smart-a15de8d2-b3a1-4a3f-a253-7410d3b4a10f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929368453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2929368453
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3472484630
Short name T939
Test name
Test status
Simulation time 50711253 ps
CPU time 0.74 seconds
Started Mar 31 12:36:17 PM PDT 24
Finished Mar 31 12:36:18 PM PDT 24
Peak memory 205580 kb
Host smart-dcc4b4de-6107-41f2-af1f-62e1938f6bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472484630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3472484630
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3069274586
Short name T984
Test name
Test status
Simulation time 39985397 ps
CPU time 1.35 seconds
Started Mar 31 12:36:21 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205928 kb
Host smart-735c2849-54cd-43d3-8db3-984cbc4d9a52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069274586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3069274586
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2665548683
Short name T1024
Test name
Test status
Simulation time 247134103 ps
CPU time 4.31 seconds
Started Mar 31 12:36:22 PM PDT 24
Finished Mar 31 12:36:27 PM PDT 24
Peak memory 222372 kb
Host smart-c5a7cb5b-82bc-4323-b4ba-a9a88e5cba12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665548683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2665548683
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2672029795
Short name T1046
Test name
Test status
Simulation time 215682286 ps
CPU time 4.23 seconds
Started Mar 31 12:36:38 PM PDT 24
Finished Mar 31 12:36:42 PM PDT 24
Peak memory 214228 kb
Host smart-4e285963-0094-4ca4-8fb3-473ebb8d925c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672029795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2672029795
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.957208790
Short name T1037
Test name
Test status
Simulation time 73226542 ps
CPU time 2.29 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:21 PM PDT 24
Peak memory 215284 kb
Host smart-007c0665-5214-4f32-a499-2321c9123224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957208790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.957208790
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3497253358
Short name T921
Test name
Test status
Simulation time 161398597 ps
CPU time 2.42 seconds
Started Mar 31 12:37:40 PM PDT 24
Finished Mar 31 12:37:42 PM PDT 24
Peak memory 219660 kb
Host smart-61c4ad68-8316-47a0-b5b2-083105bf8532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497253358 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3497253358
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2291855974
Short name T1073
Test name
Test status
Simulation time 22888988 ps
CPU time 1.11 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 12:36:42 PM PDT 24
Peak memory 205136 kb
Host smart-8a02d05e-fd0e-4962-a9a4-3bcb4a05b65e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291855974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2291855974
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3794921146
Short name T907
Test name
Test status
Simulation time 11349461 ps
CPU time 0.8 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 205568 kb
Host smart-da9afc6c-87a5-4672-b6ec-2ab5e9f436cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794921146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3794921146
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.75249861
Short name T987
Test name
Test status
Simulation time 110225143 ps
CPU time 2.35 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 205772 kb
Host smart-4f2127c2-feff-4845-bd6a-546f61d053d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75249861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sam
e_csr_outstanding.75249861
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3679415354
Short name T1001
Test name
Test status
Simulation time 230536002 ps
CPU time 4.09 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:23 PM PDT 24
Peak memory 214356 kb
Host smart-6e12a4ac-1716-490c-a4e3-1afe4bff0f1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679415354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3679415354
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3618658414
Short name T922
Test name
Test status
Simulation time 135934650 ps
CPU time 1.77 seconds
Started Mar 31 12:36:38 PM PDT 24
Finished Mar 31 12:36:40 PM PDT 24
Peak memory 205952 kb
Host smart-4710e0ac-4416-45ce-be6d-bdc2547a61d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618658414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3618658414
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.806855163
Short name T160
Test name
Test status
Simulation time 257456483 ps
CPU time 5.42 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:45 PM PDT 24
Peak memory 209420 kb
Host smart-14a19669-1cac-46df-9251-0d891bbd0b78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806855163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.806855163
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2440597242
Short name T1048
Test name
Test status
Simulation time 186854742 ps
CPU time 1.82 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 12:36:42 PM PDT 24
Peak memory 217112 kb
Host smart-86a871ca-a81c-4008-a197-cbc397b71a10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440597242 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2440597242
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.960607955
Short name T933
Test name
Test status
Simulation time 50475196 ps
CPU time 1.42 seconds
Started Mar 31 12:36:17 PM PDT 24
Finished Mar 31 12:36:18 PM PDT 24
Peak memory 205696 kb
Host smart-f3ece6bf-3e6c-4f39-b58d-55167d685a54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960607955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.960607955
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.213757266
Short name T997
Test name
Test status
Simulation time 20548384 ps
CPU time 0.82 seconds
Started Mar 31 12:36:22 PM PDT 24
Finished Mar 31 12:36:24 PM PDT 24
Peak memory 205328 kb
Host smart-ba6f9129-49a0-43d9-a27a-3bb4dd8792ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213757266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.213757266
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2138532379
Short name T1038
Test name
Test status
Simulation time 49951803 ps
CPU time 1.54 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 12:36:42 PM PDT 24
Peak memory 205784 kb
Host smart-780f259b-26a3-496f-beaa-3056a694af6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138532379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2138532379
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3232321908
Short name T122
Test name
Test status
Simulation time 134732271 ps
CPU time 2.37 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 214396 kb
Host smart-3f00d85a-ed5a-4fd6-9623-1e11c4bf4ac1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232321908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3232321908
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2259708558
Short name T940
Test name
Test status
Simulation time 281875536 ps
CPU time 4.41 seconds
Started Mar 31 12:36:31 PM PDT 24
Finished Mar 31 12:36:35 PM PDT 24
Peak memory 214292 kb
Host smart-ebadbce9-4472-4873-915b-bcbf9b45e674
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259708558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2259708558
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.157290553
Short name T964
Test name
Test status
Simulation time 50519090 ps
CPU time 2.83 seconds
Started Mar 31 12:37:20 PM PDT 24
Finished Mar 31 12:37:24 PM PDT 24
Peak memory 213756 kb
Host smart-593a82c2-1df9-47c6-bfc3-ea20fe67ae26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157290553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.157290553
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.582584459
Short name T143
Test name
Test status
Simulation time 258665693 ps
CPU time 4.99 seconds
Started Mar 31 12:36:26 PM PDT 24
Finished Mar 31 12:36:32 PM PDT 24
Peak memory 205776 kb
Host smart-f88b7639-516f-4021-a311-30685ea37539
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582584459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.582584459
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3362440517
Short name T966
Test name
Test status
Simulation time 1075732950 ps
CPU time 13.37 seconds
Started Mar 31 12:36:05 PM PDT 24
Finished Mar 31 12:36:18 PM PDT 24
Peak memory 205852 kb
Host smart-f8e4a9ff-aac6-4cb3-b144-4a442cf9373d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362440517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
362440517
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4166544665
Short name T1071
Test name
Test status
Simulation time 20493183 ps
CPU time 1.08 seconds
Started Mar 31 12:36:22 PM PDT 24
Finished Mar 31 12:36:24 PM PDT 24
Peak memory 205760 kb
Host smart-13b709dd-c5a3-4e54-81b7-bc0705cb2fc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166544665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.4
166544665
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3703161599
Short name T937
Test name
Test status
Simulation time 41043268 ps
CPU time 1.33 seconds
Started Mar 31 12:36:15 PM PDT 24
Finished Mar 31 12:36:17 PM PDT 24
Peak memory 214084 kb
Host smart-ddecf2b7-1861-4e9d-9474-f5b1eec52b23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703161599 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3703161599
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2937010951
Short name T1042
Test name
Test status
Simulation time 27147632 ps
CPU time 1.24 seconds
Started Mar 31 12:36:04 PM PDT 24
Finished Mar 31 12:36:06 PM PDT 24
Peak memory 205884 kb
Host smart-1a52557c-29b1-4b6b-99a5-93ae82651c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937010951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2937010951
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4194770014
Short name T930
Test name
Test status
Simulation time 15751929 ps
CPU time 1.04 seconds
Started Mar 31 12:36:05 PM PDT 24
Finished Mar 31 12:36:06 PM PDT 24
Peak memory 205572 kb
Host smart-0c470bee-6522-4cea-9956-443424eabba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194770014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4194770014
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2312121940
Short name T145
Test name
Test status
Simulation time 86630587 ps
CPU time 1.5 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:29 PM PDT 24
Peak memory 205800 kb
Host smart-54fb49ea-0db6-4f4b-8293-e9248ee07a9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312121940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2312121940
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3901274177
Short name T977
Test name
Test status
Simulation time 102049760 ps
CPU time 3.84 seconds
Started Mar 31 12:36:23 PM PDT 24
Finished Mar 31 12:36:27 PM PDT 24
Peak memory 222512 kb
Host smart-af99af7e-4f2d-4e77-bc61-72f5a5f2273b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901274177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3901274177
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4091358324
Short name T117
Test name
Test status
Simulation time 399213670 ps
CPU time 13.77 seconds
Started Mar 31 12:36:02 PM PDT 24
Finished Mar 31 12:36:16 PM PDT 24
Peak memory 214268 kb
Host smart-9cfb2335-bb18-4079-a376-5323377e46cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091358324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4091358324
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3511594388
Short name T1065
Test name
Test status
Simulation time 44853414 ps
CPU time 2.91 seconds
Started Mar 31 12:36:05 PM PDT 24
Finished Mar 31 12:36:08 PM PDT 24
Peak memory 214136 kb
Host smart-73244932-521b-4d8a-95de-aa66cd9318e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511594388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3511594388
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1029101678
Short name T1051
Test name
Test status
Simulation time 41093928 ps
CPU time 0.89 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:21 PM PDT 24
Peak memory 205552 kb
Host smart-ed5e7dca-e988-4b8a-823b-eabd19436293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029101678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1029101678
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1485262637
Short name T910
Test name
Test status
Simulation time 44706926 ps
CPU time 0.85 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:21 PM PDT 24
Peak memory 205476 kb
Host smart-839e410a-900c-4327-a470-0e2ee5d363ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485262637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1485262637
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.475930634
Short name T911
Test name
Test status
Simulation time 19608475 ps
CPU time 0.69 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205480 kb
Host smart-beee04f9-404f-4924-8a60-a629269076a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475930634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.475930634
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3707205263
Short name T1043
Test name
Test status
Simulation time 8938933 ps
CPU time 0.74 seconds
Started Mar 31 12:36:21 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205432 kb
Host smart-6828f2d5-2124-4d3f-af91-d3c36fd3a529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707205263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3707205263
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2790513620
Short name T918
Test name
Test status
Simulation time 13189935 ps
CPU time 0.75 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:40 PM PDT 24
Peak memory 205308 kb
Host smart-f2dad881-0643-4303-b840-a4a7b6ab54d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790513620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2790513620
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3361953575
Short name T1045
Test name
Test status
Simulation time 11029423 ps
CPU time 0.83 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 205532 kb
Host smart-afc9077b-483a-476f-acff-2d8780296271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361953575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3361953575
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2040906647
Short name T906
Test name
Test status
Simulation time 12919982 ps
CPU time 0.72 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 205476 kb
Host smart-83ab0958-fdca-4a49-bfeb-ef458baa8b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040906647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2040906647
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4191823799
Short name T1025
Test name
Test status
Simulation time 13922898 ps
CPU time 0.9 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:29 PM PDT 24
Peak memory 205872 kb
Host smart-ef457d89-ed75-46e9-8c88-d27bc15a665b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191823799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4191823799
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.612304345
Short name T969
Test name
Test status
Simulation time 11253850 ps
CPU time 0.77 seconds
Started Mar 31 12:37:39 PM PDT 24
Finished Mar 31 12:37:40 PM PDT 24
Peak memory 205296 kb
Host smart-0246ef86-e763-4815-b39e-de341faa5bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612304345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.612304345
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2635915898
Short name T920
Test name
Test status
Simulation time 11921698 ps
CPU time 0.74 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 205704 kb
Host smart-70393ac1-7c39-4398-8ddd-a0780bf86d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635915898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2635915898
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.610449292
Short name T1064
Test name
Test status
Simulation time 71534490 ps
CPU time 3.94 seconds
Started Mar 31 12:36:05 PM PDT 24
Finished Mar 31 12:36:09 PM PDT 24
Peak memory 205904 kb
Host smart-2b470041-37dc-4615-bb1f-ef6bf159589e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610449292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.610449292
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.591818353
Short name T931
Test name
Test status
Simulation time 410360918 ps
CPU time 7.79 seconds
Started Mar 31 12:36:06 PM PDT 24
Finished Mar 31 12:36:14 PM PDT 24
Peak memory 205832 kb
Host smart-95fabc88-eae0-4bac-9aa5-8b5f968fc8b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591818353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.591818353
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1890233123
Short name T914
Test name
Test status
Simulation time 42412644 ps
CPU time 0.87 seconds
Started Mar 31 12:36:03 PM PDT 24
Finished Mar 31 12:36:05 PM PDT 24
Peak memory 205656 kb
Host smart-f019df8c-8038-4b24-aaa8-f7ddfd4165bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890233123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
890233123
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1035331972
Short name T1047
Test name
Test status
Simulation time 26921444 ps
CPU time 1.17 seconds
Started Mar 31 12:36:03 PM PDT 24
Finished Mar 31 12:36:05 PM PDT 24
Peak memory 205936 kb
Host smart-5706d3fe-6a23-41d5-b5ba-9a1442ee8d06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035331972 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1035331972
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3937676509
Short name T398
Test name
Test status
Simulation time 33973866 ps
CPU time 0.86 seconds
Started Mar 31 12:36:06 PM PDT 24
Finished Mar 31 12:36:07 PM PDT 24
Peak memory 205528 kb
Host smart-61ff1cf1-6d9f-423c-b13c-0c05fa61ef8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937676509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3937676509
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3334087617
Short name T1011
Test name
Test status
Simulation time 11387637 ps
CPU time 0.85 seconds
Started Mar 31 12:36:04 PM PDT 24
Finished Mar 31 12:36:06 PM PDT 24
Peak memory 205428 kb
Host smart-3fb79938-2886-4ef3-869a-e1dc59c0b965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334087617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3334087617
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1855339125
Short name T958
Test name
Test status
Simulation time 125222744 ps
CPU time 1.77 seconds
Started Mar 31 12:36:05 PM PDT 24
Finished Mar 31 12:36:07 PM PDT 24
Peak memory 205924 kb
Host smart-9c0f0eb0-8d3e-4fb7-91df-0f6f7fc3d7a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855339125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1855339125
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1992225914
Short name T1055
Test name
Test status
Simulation time 148046108 ps
CPU time 1.75 seconds
Started Mar 31 12:36:27 PM PDT 24
Finished Mar 31 12:36:29 PM PDT 24
Peak memory 214376 kb
Host smart-e7b69d09-8b50-4169-a0e3-0138a03f1d90
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992225914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1992225914
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3323552212
Short name T992
Test name
Test status
Simulation time 447401842 ps
CPU time 9.34 seconds
Started Mar 31 12:36:15 PM PDT 24
Finished Mar 31 12:36:25 PM PDT 24
Peak memory 220484 kb
Host smart-da89a120-2348-45dc-ba6c-1c67a23c6284
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323552212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3323552212
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3547400546
Short name T956
Test name
Test status
Simulation time 197878507 ps
CPU time 5.28 seconds
Started Mar 31 12:36:05 PM PDT 24
Finished Mar 31 12:36:10 PM PDT 24
Peak memory 216336 kb
Host smart-8255e6ce-a72b-4494-b0f3-4f6e7b6f53a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547400546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3547400546
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2870121983
Short name T941
Test name
Test status
Simulation time 14877158 ps
CPU time 0.73 seconds
Started Mar 31 12:36:21 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205400 kb
Host smart-a8e0bc93-639d-433c-a9c5-f663dfe899b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870121983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2870121983
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.597035221
Short name T1014
Test name
Test status
Simulation time 15884311 ps
CPU time 0.81 seconds
Started Mar 31 12:37:40 PM PDT 24
Finished Mar 31 12:37:40 PM PDT 24
Peak memory 205296 kb
Host smart-b1bcecc0-a40d-4730-8505-e50bd5bf4eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597035221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.597035221
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.837037297
Short name T975
Test name
Test status
Simulation time 24683346 ps
CPU time 0.76 seconds
Started Mar 31 12:36:21 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205420 kb
Host smart-9604d140-3c9d-4a79-a154-2bcec27d56d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837037297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.837037297
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.714960733
Short name T965
Test name
Test status
Simulation time 22515561 ps
CPU time 0.73 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:36 PM PDT 24
Peak memory 205520 kb
Host smart-f5038cf6-e409-4158-b10a-314bbbd0d57f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714960733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.714960733
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.18316982
Short name T952
Test name
Test status
Simulation time 32404181 ps
CPU time 0.65 seconds
Started Mar 31 12:37:15 PM PDT 24
Finished Mar 31 12:37:16 PM PDT 24
Peak memory 205312 kb
Host smart-e3c93921-3cb5-4c9d-8fcf-e4272eb28bc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18316982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.18316982
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4236494825
Short name T1019
Test name
Test status
Simulation time 16827938 ps
CPU time 0.73 seconds
Started Mar 31 12:37:40 PM PDT 24
Finished Mar 31 12:37:41 PM PDT 24
Peak memory 205328 kb
Host smart-42298f1e-7479-473b-b63c-0236704cac8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236494825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4236494825
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2386998797
Short name T1031
Test name
Test status
Simulation time 32750049 ps
CPU time 0.78 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205480 kb
Host smart-4d299e93-da63-4e1a-97d0-a6ac69051d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386998797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2386998797
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.361582277
Short name T1066
Test name
Test status
Simulation time 13935929 ps
CPU time 0.85 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:29 PM PDT 24
Peak memory 205560 kb
Host smart-a9ee3ba9-20cb-4f80-82c0-9616d056019d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361582277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.361582277
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3913963006
Short name T1008
Test name
Test status
Simulation time 13243358 ps
CPU time 0.72 seconds
Started Mar 31 12:36:40 PM PDT 24
Finished Mar 31 12:36:45 PM PDT 24
Peak memory 205628 kb
Host smart-71f0675e-d456-499d-8d0f-4ab9c488e4cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913963006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3913963006
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1972840933
Short name T1058
Test name
Test status
Simulation time 14129943 ps
CPU time 0.89 seconds
Started Mar 31 12:36:19 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 205576 kb
Host smart-327c4a36-f40b-44be-8eb9-6f8b9545be93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972840933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1972840933
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1130612533
Short name T1020
Test name
Test status
Simulation time 283401645 ps
CPU time 3.74 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:32 PM PDT 24
Peak memory 205876 kb
Host smart-ff5e8b2d-73a1-4538-8ded-be3caf133789
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130612533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
130612533
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2412806037
Short name T936
Test name
Test status
Simulation time 1005166588 ps
CPU time 12.16 seconds
Started Mar 31 12:36:03 PM PDT 24
Finished Mar 31 12:36:16 PM PDT 24
Peak memory 205736 kb
Host smart-dcc47060-5529-4539-9c75-358d15310e3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412806037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
412806037
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2506939432
Short name T1032
Test name
Test status
Simulation time 48588562 ps
CPU time 1.36 seconds
Started Mar 31 12:36:22 PM PDT 24
Finished Mar 31 12:36:25 PM PDT 24
Peak memory 205768 kb
Host smart-a8923c66-0784-4078-a854-a3bd531d4097
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506939432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
506939432
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3014222508
Short name T147
Test name
Test status
Simulation time 164442746 ps
CPU time 1.55 seconds
Started Mar 31 12:36:07 PM PDT 24
Finished Mar 31 12:36:09 PM PDT 24
Peak memory 214068 kb
Host smart-37886c9c-439e-40cc-95c7-d4cc5cabfe55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014222508 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3014222508
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3305693130
Short name T986
Test name
Test status
Simulation time 16093044 ps
CPU time 0.89 seconds
Started Mar 31 12:36:10 PM PDT 24
Finished Mar 31 12:36:11 PM PDT 24
Peak memory 205548 kb
Host smart-1b812257-580e-493b-8e51-b7fc46c840b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305693130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3305693130
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3038930234
Short name T955
Test name
Test status
Simulation time 10718117 ps
CPU time 0.84 seconds
Started Mar 31 12:36:13 PM PDT 24
Finished Mar 31 12:36:15 PM PDT 24
Peak memory 205444 kb
Host smart-efea1782-5e5d-4bf3-92ec-7854c53d0420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038930234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3038930234
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3200548666
Short name T144
Test name
Test status
Simulation time 39940956 ps
CPU time 1.31 seconds
Started Mar 31 12:36:04 PM PDT 24
Finished Mar 31 12:36:06 PM PDT 24
Peak memory 205756 kb
Host smart-92024434-bb14-4c66-a36e-aa2969932b7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200548666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3200548666
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1016388058
Short name T1018
Test name
Test status
Simulation time 456939937 ps
CPU time 3.62 seconds
Started Mar 31 12:36:09 PM PDT 24
Finished Mar 31 12:36:12 PM PDT 24
Peak memory 222400 kb
Host smart-20777df1-b4a3-4f8f-ad3b-11b2b0b99249
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016388058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1016388058
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3085058115
Short name T983
Test name
Test status
Simulation time 1407204092 ps
CPU time 12.99 seconds
Started Mar 31 12:36:23 PM PDT 24
Finished Mar 31 12:36:36 PM PDT 24
Peak memory 220580 kb
Host smart-80dd797e-b6f7-4772-9f7d-06d46ef54521
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085058115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3085058115
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1043801924
Short name T943
Test name
Test status
Simulation time 668676875 ps
CPU time 4.53 seconds
Started Mar 31 12:36:08 PM PDT 24
Finished Mar 31 12:36:13 PM PDT 24
Peak memory 213984 kb
Host smart-347e3d62-f2e9-4996-82e8-6ec78f1c0d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043801924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1043801924
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.595519830
Short name T1005
Test name
Test status
Simulation time 9608298 ps
CPU time 0.71 seconds
Started Mar 31 12:36:19 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 205456 kb
Host smart-f8130ffd-509a-42de-a091-894d5cd871f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595519830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.595519830
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1198466373
Short name T946
Test name
Test status
Simulation time 27382584 ps
CPU time 0.71 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 205460 kb
Host smart-c6111236-1f51-4cec-ad1f-4e2afb4ce986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198466373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1198466373
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.64349992
Short name T968
Test name
Test status
Simulation time 32981442 ps
CPU time 0.83 seconds
Started Mar 31 12:36:21 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205484 kb
Host smart-ff46df98-1971-434b-ad18-088c4281e8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64349992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.64349992
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3065150348
Short name T1060
Test name
Test status
Simulation time 10445965 ps
CPU time 0.78 seconds
Started Mar 31 12:37:24 PM PDT 24
Finished Mar 31 12:37:25 PM PDT 24
Peak memory 205244 kb
Host smart-f9ab3709-38c8-4601-a9ca-0262eb6e50d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065150348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3065150348
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.916208659
Short name T938
Test name
Test status
Simulation time 49189716 ps
CPU time 0.77 seconds
Started Mar 31 12:37:40 PM PDT 24
Finished Mar 31 12:37:40 PM PDT 24
Peak memory 205372 kb
Host smart-f3a0e45b-2454-4d0a-8315-cdd5f14000b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916208659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.916208659
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2760215031
Short name T1044
Test name
Test status
Simulation time 12747416 ps
CPU time 0.76 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 205460 kb
Host smart-b8a31567-d327-4f4e-92f7-1514c87d4757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760215031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2760215031
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1712279419
Short name T1023
Test name
Test status
Simulation time 30300338 ps
CPU time 0.7 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:35 PM PDT 24
Peak memory 205552 kb
Host smart-16657069-4d3c-41b4-8cf2-2fcd8d5c5605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712279419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1712279419
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2307967973
Short name T917
Test name
Test status
Simulation time 37630713 ps
CPU time 0.7 seconds
Started Mar 31 12:36:25 PM PDT 24
Finished Mar 31 12:36:26 PM PDT 24
Peak memory 205580 kb
Host smart-47175057-0665-4dbf-9a1c-ccd5ce48be4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307967973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2307967973
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4122148654
Short name T1029
Test name
Test status
Simulation time 28145192 ps
CPU time 0.76 seconds
Started Mar 31 12:36:31 PM PDT 24
Finished Mar 31 12:36:32 PM PDT 24
Peak memory 205464 kb
Host smart-cbc1a32e-4285-4751-8ed4-48830c74a1ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122148654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4122148654
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.327600297
Short name T928
Test name
Test status
Simulation time 30517221 ps
CPU time 0.78 seconds
Started Mar 31 12:36:36 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 205396 kb
Host smart-7716e728-f9bb-487f-878c-db434b272d3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327600297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.327600297
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1031800180
Short name T971
Test name
Test status
Simulation time 39329930 ps
CPU time 1.58 seconds
Started Mar 31 12:36:07 PM PDT 24
Finished Mar 31 12:36:08 PM PDT 24
Peak memory 218512 kb
Host smart-60bcedaa-25a0-4156-8648-6860200d26cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031800180 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1031800180
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1036200247
Short name T1036
Test name
Test status
Simulation time 68135161 ps
CPU time 0.99 seconds
Started Mar 31 12:36:07 PM PDT 24
Finished Mar 31 12:36:08 PM PDT 24
Peak memory 205600 kb
Host smart-911e21b6-3b27-4c4f-8c0a-1800cca5ad49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036200247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1036200247
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1124608224
Short name T995
Test name
Test status
Simulation time 26752326 ps
CPU time 0.79 seconds
Started Mar 31 12:36:17 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 205560 kb
Host smart-acd6b6df-9d17-44b5-8384-4962bbad5b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124608224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1124608224
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2968706068
Short name T142
Test name
Test status
Simulation time 459875062 ps
CPU time 2.85 seconds
Started Mar 31 12:36:19 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 205752 kb
Host smart-2f842eed-384b-43dd-a315-d1648bc2d123
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968706068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2968706068
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1981147339
Short name T125
Test name
Test status
Simulation time 229139957 ps
CPU time 4.81 seconds
Started Mar 31 12:36:23 PM PDT 24
Finished Mar 31 12:36:28 PM PDT 24
Peak memory 222356 kb
Host smart-cb4f7f3e-0f39-4cb1-be9f-1910428b7bb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981147339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1981147339
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1108649969
Short name T972
Test name
Test status
Simulation time 642067613 ps
CPU time 12.41 seconds
Started Mar 31 12:36:06 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 214204 kb
Host smart-de186c6a-8dfa-4ec5-beb3-9f760d7474e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108649969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1108649969
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3955046794
Short name T985
Test name
Test status
Simulation time 92120196 ps
CPU time 3.27 seconds
Started Mar 31 12:36:16 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 214008 kb
Host smart-0dc25091-497c-4139-819a-763a848eec96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955046794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3955046794
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.4260641766
Short name T163
Test name
Test status
Simulation time 456356831 ps
CPU time 5.36 seconds
Started Mar 31 12:36:08 PM PDT 24
Finished Mar 31 12:36:13 PM PDT 24
Peak memory 213964 kb
Host smart-e6583887-db75-4b4f-a552-e5102db61175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260641766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.4260641766
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1722917821
Short name T1062
Test name
Test status
Simulation time 39853624 ps
CPU time 1.55 seconds
Started Mar 31 12:36:08 PM PDT 24
Finished Mar 31 12:36:10 PM PDT 24
Peak memory 205776 kb
Host smart-390bda26-8608-4090-a2fe-2b9d4b8c7d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722917821 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1722917821
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1485215535
Short name T945
Test name
Test status
Simulation time 20341557 ps
CPU time 1.12 seconds
Started Mar 31 12:36:32 PM PDT 24
Finished Mar 31 12:36:34 PM PDT 24
Peak memory 205820 kb
Host smart-1241739f-228d-4043-b9aa-dd4b0af1c68b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485215535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1485215535
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2177558370
Short name T1068
Test name
Test status
Simulation time 20129533 ps
CPU time 0.85 seconds
Started Mar 31 12:36:20 PM PDT 24
Finished Mar 31 12:36:21 PM PDT 24
Peak memory 205420 kb
Host smart-3bd45e3c-1743-4f2d-8c7c-7511362266e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177558370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2177558370
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.445440091
Short name T976
Test name
Test status
Simulation time 646434642 ps
CPU time 1.46 seconds
Started Mar 31 12:36:06 PM PDT 24
Finished Mar 31 12:36:08 PM PDT 24
Peak memory 205776 kb
Host smart-b7784a34-2e3f-4630-8f92-d271060cd6bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445440091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.445440091
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1151327432
Short name T120
Test name
Test status
Simulation time 670536332 ps
CPU time 4.93 seconds
Started Mar 31 12:36:08 PM PDT 24
Finished Mar 31 12:36:13 PM PDT 24
Peak memory 219080 kb
Host smart-9c46975a-d47b-4600-85e0-98aee800c609
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151327432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1151327432
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2811202694
Short name T1053
Test name
Test status
Simulation time 1183879713 ps
CPU time 8.87 seconds
Started Mar 31 12:36:27 PM PDT 24
Finished Mar 31 12:36:36 PM PDT 24
Peak memory 214384 kb
Host smart-7be50c09-d3b1-4e39-ac0e-d3a22e5ee8eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811202694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2811202694
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2308211208
Short name T915
Test name
Test status
Simulation time 155809046 ps
CPU time 2.44 seconds
Started Mar 31 12:36:27 PM PDT 24
Finished Mar 31 12:36:30 PM PDT 24
Peak memory 222228 kb
Host smart-a97f08c9-fb2d-40b5-b977-d5afb10a9dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308211208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2308211208
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.931579450
Short name T162
Test name
Test status
Simulation time 1115322692 ps
CPU time 9.67 seconds
Started Mar 31 12:36:05 PM PDT 24
Finished Mar 31 12:36:15 PM PDT 24
Peak memory 209440 kb
Host smart-1bd3bd4c-226d-4137-a12f-e20836cc2105
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931579450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
931579450
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.620291333
Short name T953
Test name
Test status
Simulation time 28170704 ps
CPU time 1.36 seconds
Started Mar 31 12:36:12 PM PDT 24
Finished Mar 31 12:36:13 PM PDT 24
Peak memory 214024 kb
Host smart-8160dda8-8408-41b4-a5ad-3a00db6a5491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620291333 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.620291333
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3685922098
Short name T140
Test name
Test status
Simulation time 46455394 ps
CPU time 1.46 seconds
Started Mar 31 12:36:29 PM PDT 24
Finished Mar 31 12:36:31 PM PDT 24
Peak memory 205776 kb
Host smart-7e9138d5-78cf-4433-a5d1-72004bf107b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685922098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3685922098
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3050416993
Short name T925
Test name
Test status
Simulation time 22628931 ps
CPU time 0.74 seconds
Started Mar 31 12:36:09 PM PDT 24
Finished Mar 31 12:36:10 PM PDT 24
Peak memory 205504 kb
Host smart-aa9ebe3a-7214-4c4a-b1e2-2ffe8348eece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050416993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3050416993
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1054207386
Short name T1049
Test name
Test status
Simulation time 42081940 ps
CPU time 1.54 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 205920 kb
Host smart-81ed5a8f-b514-4388-9c20-3aa2ee797de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054207386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1054207386
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4244670800
Short name T1034
Test name
Test status
Simulation time 73488423 ps
CPU time 1.93 seconds
Started Mar 31 12:36:25 PM PDT 24
Finished Mar 31 12:36:28 PM PDT 24
Peak memory 222424 kb
Host smart-a6d262d5-dfaf-4cc6-b561-bc1a32005d65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244670800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.4244670800
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.926174988
Short name T929
Test name
Test status
Simulation time 83999440 ps
CPU time 4.38 seconds
Started Mar 31 12:36:23 PM PDT 24
Finished Mar 31 12:36:27 PM PDT 24
Peak memory 214324 kb
Host smart-f0efa373-a49b-4e8c-81cd-db0f6e98715c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926174988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.926174988
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3990429089
Short name T913
Test name
Test status
Simulation time 284617495 ps
CPU time 5.3 seconds
Started Mar 31 12:36:26 PM PDT 24
Finished Mar 31 12:36:31 PM PDT 24
Peak memory 214032 kb
Host smart-f178f231-f8c6-45a5-be9b-d3711f94330d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990429089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3990429089
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.461430407
Short name T165
Test name
Test status
Simulation time 379751099 ps
CPU time 6.02 seconds
Started Mar 31 12:36:14 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 209364 kb
Host smart-a6696aff-f599-4e35-b108-4609d590285f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461430407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
461430407
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2513800047
Short name T949
Test name
Test status
Simulation time 213398423 ps
CPU time 1.33 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:20 PM PDT 24
Peak memory 205860 kb
Host smart-b4fbdde2-5b07-4110-b1b5-2e3b8b5782dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513800047 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2513800047
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.89465082
Short name T970
Test name
Test status
Simulation time 20470631 ps
CPU time 1.15 seconds
Started Mar 31 12:36:28 PM PDT 24
Finished Mar 31 12:36:29 PM PDT 24
Peak memory 205724 kb
Host smart-ad6edec5-79a8-47b7-afef-470c5d51e602
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89465082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.89465082
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2299853970
Short name T923
Test name
Test status
Simulation time 35699715 ps
CPU time 0.74 seconds
Started Mar 31 12:36:18 PM PDT 24
Finished Mar 31 12:36:19 PM PDT 24
Peak memory 205476 kb
Host smart-d0203b9e-38ce-4e12-9431-f0a3fe85579a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299853970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2299853970
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1904633972
Short name T957
Test name
Test status
Simulation time 304946693 ps
CPU time 2.41 seconds
Started Mar 31 12:36:30 PM PDT 24
Finished Mar 31 12:36:33 PM PDT 24
Peak memory 205760 kb
Host smart-664c5d4b-e672-4680-9224-5d61c257a8b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904633972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1904633972
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.767417249
Short name T948
Test name
Test status
Simulation time 270333692 ps
CPU time 4.02 seconds
Started Mar 31 12:36:12 PM PDT 24
Finished Mar 31 12:36:16 PM PDT 24
Peak memory 214292 kb
Host smart-cf7f3474-1ef3-4191-b613-fc42cd0364fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767417249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.767417249
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1079380120
Short name T962
Test name
Test status
Simulation time 469391242 ps
CPU time 9.89 seconds
Started Mar 31 12:36:34 PM PDT 24
Finished Mar 31 12:36:44 PM PDT 24
Peak memory 214408 kb
Host smart-425c8a8f-f69a-40a8-b66c-678eaed5e3ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079380120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1079380120
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1313130798
Short name T1007
Test name
Test status
Simulation time 228727935 ps
CPU time 2.02 seconds
Started Mar 31 12:36:10 PM PDT 24
Finished Mar 31 12:36:12 PM PDT 24
Peak memory 214076 kb
Host smart-8531fbda-f945-4681-a940-426501d2a3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313130798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1313130798
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1455985131
Short name T164
Test name
Test status
Simulation time 773873946 ps
CPU time 8.78 seconds
Started Mar 31 12:36:23 PM PDT 24
Finished Mar 31 12:36:32 PM PDT 24
Peak memory 209636 kb
Host smart-7d6dbced-c101-41e4-a84d-936ee6d9d381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455985131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1455985131
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3158706867
Short name T994
Test name
Test status
Simulation time 25758369 ps
CPU time 1.67 seconds
Started Mar 31 12:36:11 PM PDT 24
Finished Mar 31 12:36:12 PM PDT 24
Peak memory 214160 kb
Host smart-6d1b4752-bb51-4eab-a417-8880f984cf94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158706867 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3158706867
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2440931527
Short name T1067
Test name
Test status
Simulation time 31737688 ps
CPU time 1.27 seconds
Started Mar 31 12:36:14 PM PDT 24
Finished Mar 31 12:36:17 PM PDT 24
Peak memory 205828 kb
Host smart-835a6956-37d1-4be9-be64-ac9e683a8188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440931527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2440931527
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2884391141
Short name T954
Test name
Test status
Simulation time 11278061 ps
CPU time 0.82 seconds
Started Mar 31 12:36:35 PM PDT 24
Finished Mar 31 12:36:36 PM PDT 24
Peak memory 205548 kb
Host smart-5f06c0a7-77f1-4b28-a8f3-d5883e668441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884391141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2884391141
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4270987852
Short name T1069
Test name
Test status
Simulation time 114149744 ps
CPU time 2.53 seconds
Started Mar 31 12:36:27 PM PDT 24
Finished Mar 31 12:36:30 PM PDT 24
Peak memory 205872 kb
Host smart-a444ab66-a177-4718-a09d-b1c0086d4f30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270987852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4270987852
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3400973279
Short name T1026
Test name
Test status
Simulation time 130901970 ps
CPU time 2.97 seconds
Started Mar 31 12:36:13 PM PDT 24
Finished Mar 31 12:36:16 PM PDT 24
Peak memory 214288 kb
Host smart-f30f3bfe-51bc-4b56-9642-5cb1b893df59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400973279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3400973279
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1976457181
Short name T1056
Test name
Test status
Simulation time 1518459174 ps
CPU time 9.47 seconds
Started Mar 31 12:36:12 PM PDT 24
Finished Mar 31 12:36:22 PM PDT 24
Peak memory 214320 kb
Host smart-215499a5-b23a-4948-9bc0-84f3700520e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976457181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1976457181
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3393539533
Short name T944
Test name
Test status
Simulation time 148131098 ps
CPU time 4.94 seconds
Started Mar 31 12:36:31 PM PDT 24
Finished Mar 31 12:36:37 PM PDT 24
Peak memory 214044 kb
Host smart-cb3a5bf7-dfbc-446a-b52e-71f5e6d2ae84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393539533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3393539533
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2557459972
Short name T166
Test name
Test status
Simulation time 440297282 ps
CPU time 4.83 seconds
Started Mar 31 12:36:24 PM PDT 24
Finished Mar 31 12:36:28 PM PDT 24
Peak memory 209316 kb
Host smart-91c9b86d-e278-4053-ae29-9876d518de39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557459972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2557459972
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1203895986
Short name T418
Test name
Test status
Simulation time 82314222 ps
CPU time 3.49 seconds
Started Mar 31 03:54:11 PM PDT 24
Finished Mar 31 03:54:15 PM PDT 24
Peak memory 214620 kb
Host smart-60439d3f-23be-441b-8064-2094b2e368e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203895986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1203895986
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2626791821
Short name T456
Test name
Test status
Simulation time 159977967 ps
CPU time 3.14 seconds
Started Mar 31 03:54:04 PM PDT 24
Finished Mar 31 03:54:09 PM PDT 24
Peak memory 209740 kb
Host smart-81b66fc5-3b32-4732-8026-dbacef144aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626791821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2626791821
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4199019220
Short name T881
Test name
Test status
Simulation time 228824216 ps
CPU time 5.59 seconds
Started Mar 31 03:54:07 PM PDT 24
Finished Mar 31 03:54:14 PM PDT 24
Peak memory 214596 kb
Host smart-1f28fabc-fc6c-42f1-9dc9-3c8b6eaee7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199019220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4199019220
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2494240843
Short name T790
Test name
Test status
Simulation time 172312987 ps
CPU time 3.1 seconds
Started Mar 31 03:54:06 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 209120 kb
Host smart-e4b97754-9266-49ab-9bb5-87f2e1435738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494240843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2494240843
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1350567350
Short name T264
Test name
Test status
Simulation time 386905114 ps
CPU time 4.44 seconds
Started Mar 31 03:53:52 PM PDT 24
Finished Mar 31 03:53:56 PM PDT 24
Peak memory 207488 kb
Host smart-21a91a7c-1b82-47dc-b17b-387a71a73474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350567350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1350567350
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2848741786
Short name T768
Test name
Test status
Simulation time 4871710828 ps
CPU time 40.7 seconds
Started Mar 31 03:53:59 PM PDT 24
Finished Mar 31 03:54:40 PM PDT 24
Peak memory 208520 kb
Host smart-e0ccd6bd-8c80-417b-ab92-864c3066aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848741786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2848741786
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3225334892
Short name T859
Test name
Test status
Simulation time 88270233 ps
CPU time 1.95 seconds
Started Mar 31 03:54:17 PM PDT 24
Finished Mar 31 03:54:19 PM PDT 24
Peak memory 208980 kb
Host smart-4e38ee10-bd5e-4ee7-85f5-d195e5dc9be1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225334892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3225334892
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3966180895
Short name T134
Test name
Test status
Simulation time 304004850 ps
CPU time 3.73 seconds
Started Mar 31 03:53:56 PM PDT 24
Finished Mar 31 03:54:00 PM PDT 24
Peak memory 208916 kb
Host smart-34126855-8876-452f-b0ae-407abb82ac3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966180895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3966180895
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.851108763
Short name T352
Test name
Test status
Simulation time 5724791630 ps
CPU time 34.6 seconds
Started Mar 31 03:53:59 PM PDT 24
Finished Mar 31 03:54:34 PM PDT 24
Peak memory 208384 kb
Host smart-dd84619c-0241-4edc-8353-c8aca968676f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851108763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.851108763
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2880781090
Short name T536
Test name
Test status
Simulation time 48550608 ps
CPU time 2.29 seconds
Started Mar 31 03:54:00 PM PDT 24
Finished Mar 31 03:54:02 PM PDT 24
Peak memory 218696 kb
Host smart-5ecfc983-c7c9-4392-998d-fa3cab37a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880781090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2880781090
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1363890991
Short name T873
Test name
Test status
Simulation time 1330896328 ps
CPU time 5.45 seconds
Started Mar 31 03:53:56 PM PDT 24
Finished Mar 31 03:54:02 PM PDT 24
Peak memory 208636 kb
Host smart-92b383e7-1b67-4f79-8d6c-faa785b085a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363890991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1363890991
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2739469008
Short name T367
Test name
Test status
Simulation time 518459083 ps
CPU time 9.04 seconds
Started Mar 31 03:54:09 PM PDT 24
Finished Mar 31 03:54:19 PM PDT 24
Peak memory 223060 kb
Host smart-23f0c720-003e-422d-95f9-7bc1cd26d2ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739469008 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2739469008
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1732346045
Short name T591
Test name
Test status
Simulation time 419259612 ps
CPU time 5.09 seconds
Started Mar 31 03:53:51 PM PDT 24
Finished Mar 31 03:53:57 PM PDT 24
Peak memory 218676 kb
Host smart-f754d985-37f5-4b36-ac4b-e71aaabdfaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732346045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1732346045
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3042455761
Short name T804
Test name
Test status
Simulation time 125561518 ps
CPU time 2.7 seconds
Started Mar 31 03:54:07 PM PDT 24
Finished Mar 31 03:54:11 PM PDT 24
Peak memory 210024 kb
Host smart-bf20338e-d711-4406-a9e3-0ed06d5cd681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042455761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3042455761
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2153932380
Short name T879
Test name
Test status
Simulation time 76285132 ps
CPU time 1.03 seconds
Started Mar 31 03:54:00 PM PDT 24
Finished Mar 31 03:54:01 PM PDT 24
Peak memory 206484 kb
Host smart-a3ee40a6-e011-4500-96fd-b97d4c9e402e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153932380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2153932380
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2938532042
Short name T69
Test name
Test status
Simulation time 140360037 ps
CPU time 5 seconds
Started Mar 31 03:54:02 PM PDT 24
Finished Mar 31 03:54:09 PM PDT 24
Peak memory 210432 kb
Host smart-21e6538c-408f-4ef6-bbb1-2e74653bf582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938532042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2938532042
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3674597990
Short name T669
Test name
Test status
Simulation time 65996201 ps
CPU time 2.51 seconds
Started Mar 31 03:53:59 PM PDT 24
Finished Mar 31 03:54:02 PM PDT 24
Peak memory 210296 kb
Host smart-24f1572f-a3d5-4a5b-8811-831e033c15e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674597990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3674597990
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1005273804
Short name T24
Test name
Test status
Simulation time 101086051 ps
CPU time 4.6 seconds
Started Mar 31 03:54:05 PM PDT 24
Finished Mar 31 03:54:11 PM PDT 24
Peak memory 214704 kb
Host smart-7306380e-9f63-4c9d-96b1-af7cbc27a667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005273804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1005273804
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1438695871
Short name T270
Test name
Test status
Simulation time 141070386 ps
CPU time 5.73 seconds
Started Mar 31 03:54:03 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 222712 kb
Host smart-14d9a60c-5947-4d5b-82de-f9a13915d5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438695871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1438695871
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3832629063
Short name T480
Test name
Test status
Simulation time 165437107 ps
CPU time 2.82 seconds
Started Mar 31 03:54:03 PM PDT 24
Finished Mar 31 03:54:07 PM PDT 24
Peak memory 208552 kb
Host smart-b69b3a55-b228-4d3e-acc3-0d32f63bd301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832629063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3832629063
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3033461398
Short name T42
Test name
Test status
Simulation time 179709674 ps
CPU time 6.53 seconds
Started Mar 31 03:54:11 PM PDT 24
Finished Mar 31 03:54:17 PM PDT 24
Peak memory 209648 kb
Host smart-c78b773e-857a-409c-9bb4-6eeb621cbdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033461398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3033461398
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.190403542
Short name T109
Test name
Test status
Simulation time 1052745939 ps
CPU time 10.39 seconds
Started Mar 31 03:53:58 PM PDT 24
Finished Mar 31 03:54:09 PM PDT 24
Peak memory 231148 kb
Host smart-db1a65dc-9c71-481e-b6b5-f62bf679216f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190403542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.190403542
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.644063332
Short name T774
Test name
Test status
Simulation time 6250887093 ps
CPU time 39.87 seconds
Started Mar 31 03:54:00 PM PDT 24
Finished Mar 31 03:54:41 PM PDT 24
Peak memory 208676 kb
Host smart-6db1772b-d04a-425a-a1ca-28f9336a8782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644063332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.644063332
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1707707615
Short name T664
Test name
Test status
Simulation time 562470667 ps
CPU time 3.53 seconds
Started Mar 31 03:53:55 PM PDT 24
Finished Mar 31 03:53:58 PM PDT 24
Peak memory 209156 kb
Host smart-bec7e083-a0d2-4ed4-a6a5-af81ec6797a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707707615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1707707615
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3301028030
Short name T611
Test name
Test status
Simulation time 300456027 ps
CPU time 2.61 seconds
Started Mar 31 03:53:46 PM PDT 24
Finished Mar 31 03:53:49 PM PDT 24
Peak memory 206960 kb
Host smart-d53bf71c-15f3-4b48-a832-5fc859ff17c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301028030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3301028030
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2781333357
Short name T691
Test name
Test status
Simulation time 141627996 ps
CPU time 5.73 seconds
Started Mar 31 03:53:56 PM PDT 24
Finished Mar 31 03:54:02 PM PDT 24
Peak memory 208276 kb
Host smart-2ed60160-b5b9-43ca-ac4d-f5f32c850b11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781333357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2781333357
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3640694686
Short name T257
Test name
Test status
Simulation time 208503776 ps
CPU time 4.61 seconds
Started Mar 31 03:53:47 PM PDT 24
Finished Mar 31 03:53:54 PM PDT 24
Peak memory 218768 kb
Host smart-8b33f3da-b735-46bf-9501-e415c5acd525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640694686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3640694686
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2621249409
Short name T690
Test name
Test status
Simulation time 839560232 ps
CPU time 13.93 seconds
Started Mar 31 03:53:56 PM PDT 24
Finished Mar 31 03:54:11 PM PDT 24
Peak memory 208344 kb
Host smart-8ec53b36-a204-44c2-95ae-c98d829c1c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621249409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2621249409
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.882678013
Short name T811
Test name
Test status
Simulation time 4582048769 ps
CPU time 12.47 seconds
Started Mar 31 03:53:48 PM PDT 24
Finished Mar 31 03:54:00 PM PDT 24
Peak memory 217456 kb
Host smart-3ac28ced-0c67-444c-acae-5363f07023f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882678013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.882678013
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.477505213
Short name T387
Test name
Test status
Simulation time 53147609 ps
CPU time 3.5 seconds
Started Mar 31 03:54:05 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 207784 kb
Host smart-d4cfdadb-1d59-4e21-a204-26ac49e765a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477505213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.477505213
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2143121625
Short name T59
Test name
Test status
Simulation time 207646362 ps
CPU time 2.61 seconds
Started Mar 31 03:53:58 PM PDT 24
Finished Mar 31 03:54:00 PM PDT 24
Peak memory 210204 kb
Host smart-4dd2d2a6-dc9f-4dd9-b9e1-72cb4c48e7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143121625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2143121625
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2472170152
Short name T787
Test name
Test status
Simulation time 14704022 ps
CPU time 0.91 seconds
Started Mar 31 03:54:30 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 206616 kb
Host smart-73e4f9f6-abdd-4198-b9db-6da492283488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472170152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2472170152
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2306517916
Short name T31
Test name
Test status
Simulation time 37187318 ps
CPU time 1.9 seconds
Started Mar 31 03:54:21 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 214676 kb
Host smart-4fe2117f-4971-450d-b9c9-9f50cea13911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306517916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2306517916
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1635486553
Short name T731
Test name
Test status
Simulation time 131644533 ps
CPU time 2.15 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 208108 kb
Host smart-cd925e12-3359-45da-bbed-e1fb70af96f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635486553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1635486553
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1552494917
Short name T645
Test name
Test status
Simulation time 148086190 ps
CPU time 3.69 seconds
Started Mar 31 03:54:12 PM PDT 24
Finished Mar 31 03:54:16 PM PDT 24
Peak memory 214692 kb
Host smart-50277a12-c913-4034-83bf-5c2d5b10f011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552494917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1552494917
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.695415737
Short name T251
Test name
Test status
Simulation time 504504051 ps
CPU time 6.27 seconds
Started Mar 31 03:54:38 PM PDT 24
Finished Mar 31 03:54:44 PM PDT 24
Peak memory 222836 kb
Host smart-8164f8ed-aa00-4e7c-a550-d0d7203924a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695415737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.695415737
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1321610336
Short name T524
Test name
Test status
Simulation time 508840615 ps
CPU time 2.88 seconds
Started Mar 31 03:54:21 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 206408 kb
Host smart-afa473e0-f1c9-44b6-a998-cee57b832f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321610336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1321610336
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3700587076
Short name T491
Test name
Test status
Simulation time 538219445 ps
CPU time 5.17 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:28 PM PDT 24
Peak memory 208356 kb
Host smart-0984cd2b-290c-4bac-85f4-bf595b303056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700587076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3700587076
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.893822702
Short name T455
Test name
Test status
Simulation time 948759876 ps
CPU time 4.53 seconds
Started Mar 31 03:54:15 PM PDT 24
Finished Mar 31 03:54:20 PM PDT 24
Peak memory 206976 kb
Host smart-0de92afd-5cdb-449a-a3f1-a0430c620135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893822702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.893822702
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.257862411
Short name T364
Test name
Test status
Simulation time 1139322193 ps
CPU time 5.15 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 207236 kb
Host smart-0c4e5d43-e32c-491b-bcf6-bfd162fe8f35
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257862411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.257862411
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2508301821
Short name T720
Test name
Test status
Simulation time 250710177 ps
CPU time 2.81 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 207228 kb
Host smart-eaa15ab6-99c4-4dfc-887b-e8df883f33e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508301821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2508301821
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3425333410
Short name T754
Test name
Test status
Simulation time 204872865 ps
CPU time 3.73 seconds
Started Mar 31 03:54:29 PM PDT 24
Finished Mar 31 03:54:33 PM PDT 24
Peak memory 207132 kb
Host smart-78e60aca-8da9-4d8a-9a8a-dfdad847c01a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425333410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3425333410
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3251159103
Short name T296
Test name
Test status
Simulation time 375311177 ps
CPU time 4.73 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 208972 kb
Host smart-6875dce1-a0b1-4e29-bc59-fafd4df138d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251159103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3251159103
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3651413377
Short name T771
Test name
Test status
Simulation time 746170158 ps
CPU time 7.78 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:34 PM PDT 24
Peak memory 207008 kb
Host smart-eddfa980-e499-4cc1-aee4-5b194e55edf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651413377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3651413377
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2853970632
Short name T228
Test name
Test status
Simulation time 5279278107 ps
CPU time 148.91 seconds
Started Mar 31 03:54:22 PM PDT 24
Finished Mar 31 03:56:51 PM PDT 24
Peak memory 222364 kb
Host smart-c6ce6a03-f378-4267-85c4-bd39825ea126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853970632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2853970632
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2562162358
Short name T625
Test name
Test status
Simulation time 327418450 ps
CPU time 3.47 seconds
Started Mar 31 03:54:25 PM PDT 24
Finished Mar 31 03:54:28 PM PDT 24
Peak memory 207292 kb
Host smart-e8a82d79-9827-4b7f-8463-ae6b26899d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562162358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2562162358
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3421369837
Short name T671
Test name
Test status
Simulation time 309306081 ps
CPU time 3.46 seconds
Started Mar 31 03:54:20 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 210040 kb
Host smart-9437e6f4-59e1-42f0-9143-526293c5896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421369837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3421369837
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2007883354
Short name T732
Test name
Test status
Simulation time 12425014 ps
CPU time 0.74 seconds
Started Mar 31 03:54:24 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 206304 kb
Host smart-421655f3-58a1-4b8a-a14d-1d91432eefa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007883354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2007883354
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2938715726
Short name T814
Test name
Test status
Simulation time 626072773 ps
CPU time 8.7 seconds
Started Mar 31 03:54:22 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 214688 kb
Host smart-5b9e9ad5-6edd-4c9e-9a6d-8c61e5fd1251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938715726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2938715726
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3683867610
Short name T522
Test name
Test status
Simulation time 2814250125 ps
CPU time 18.45 seconds
Started Mar 31 03:54:22 PM PDT 24
Finished Mar 31 03:54:40 PM PDT 24
Peak memory 208532 kb
Host smart-133967d9-9d98-419f-8133-a1e455ed27dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683867610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3683867610
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1599900782
Short name T877
Test name
Test status
Simulation time 395574528 ps
CPU time 3.27 seconds
Started Mar 31 03:54:21 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 214680 kb
Host smart-0636cb24-a3f4-4b67-84c6-8e70a2ef122f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599900782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1599900782
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2794794896
Short name T130
Test name
Test status
Simulation time 357745590 ps
CPU time 9.03 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:32 PM PDT 24
Peak memory 209220 kb
Host smart-3b48860a-d701-47c1-b11c-618bd53b5733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794794896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2794794896
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3765687135
Short name T556
Test name
Test status
Simulation time 189767085 ps
CPU time 5.21 seconds
Started Mar 31 03:54:25 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 209124 kb
Host smart-1164cc44-af86-4706-bb51-e6d538f62651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765687135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3765687135
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2542017802
Short name T458
Test name
Test status
Simulation time 131942908 ps
CPU time 4.96 seconds
Started Mar 31 03:54:22 PM PDT 24
Finished Mar 31 03:54:27 PM PDT 24
Peak memory 208164 kb
Host smart-4f322905-bd73-464a-ae8f-f2a854e0a42c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542017802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2542017802
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1292692741
Short name T889
Test name
Test status
Simulation time 430164982 ps
CPU time 5.15 seconds
Started Mar 31 03:54:25 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 207588 kb
Host smart-8b0eb0d2-ec8a-4d46-aaec-cdb8acf501f0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292692741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1292692741
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3661609286
Short name T860
Test name
Test status
Simulation time 41940466 ps
CPU time 1.68 seconds
Started Mar 31 03:54:30 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 207408 kb
Host smart-5c2df497-7ea2-401b-af08-78b0cc7b4e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661609286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3661609286
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3993367673
Short name T897
Test name
Test status
Simulation time 295701727 ps
CPU time 16.65 seconds
Started Mar 31 03:54:17 PM PDT 24
Finished Mar 31 03:54:34 PM PDT 24
Peak memory 223008 kb
Host smart-df165b88-ffd2-49f6-a653-ee36bacb1aca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993367673 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3993367673
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2614836257
Short name T713
Test name
Test status
Simulation time 109177224 ps
CPU time 5.37 seconds
Started Mar 31 03:54:17 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 214688 kb
Host smart-6f6199b6-0dc0-4154-aa5a-01b6f646ec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614836257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2614836257
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.379821103
Short name T396
Test name
Test status
Simulation time 530955613 ps
CPU time 2.57 seconds
Started Mar 31 03:54:20 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 210448 kb
Host smart-66f7bc68-7ed6-4d55-83f3-b106b2b5335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379821103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.379821103
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1577068499
Short name T521
Test name
Test status
Simulation time 22455184 ps
CPU time 0.77 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:26 PM PDT 24
Peak memory 206268 kb
Host smart-8805eb24-dae9-40f5-bd51-670342ae7322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577068499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1577068499
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.498405969
Short name T53
Test name
Test status
Simulation time 50933151 ps
CPU time 2 seconds
Started Mar 31 03:54:32 PM PDT 24
Finished Mar 31 03:54:34 PM PDT 24
Peak memory 220020 kb
Host smart-a0723be4-95b9-43dc-b6fd-95358e755868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498405969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.498405969
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3127771048
Short name T289
Test name
Test status
Simulation time 225211808 ps
CPU time 7.72 seconds
Started Mar 31 03:54:22 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 209652 kb
Host smart-583ea09b-2218-4cee-bb0d-6bd9626ac59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127771048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3127771048
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1523421793
Short name T797
Test name
Test status
Simulation time 63375686 ps
CPU time 3.24 seconds
Started Mar 31 03:54:43 PM PDT 24
Finished Mar 31 03:54:46 PM PDT 24
Peak memory 221064 kb
Host smart-77ada12e-265f-492d-8e60-472e1fdead4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523421793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1523421793
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2649990831
Short name T365
Test name
Test status
Simulation time 299898881 ps
CPU time 3.4 seconds
Started Mar 31 03:54:13 PM PDT 24
Finished Mar 31 03:54:17 PM PDT 24
Peak memory 209912 kb
Host smart-9e98db9c-b132-4340-9c1d-b43bcb154c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649990831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2649990831
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2746996880
Short name T632
Test name
Test status
Simulation time 1132003859 ps
CPU time 5.68 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:28 PM PDT 24
Peak memory 208984 kb
Host smart-53c572e5-0b45-4199-aabd-2a624b7f5885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746996880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2746996880
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.931840467
Short name T326
Test name
Test status
Simulation time 197346698 ps
CPU time 2.79 seconds
Started Mar 31 03:54:24 PM PDT 24
Finished Mar 31 03:54:26 PM PDT 24
Peak memory 208628 kb
Host smart-4b33abc8-734a-4e36-b6f6-bd49d369e539
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931840467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.931840467
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4271056913
Short name T110
Test name
Test status
Simulation time 111852217 ps
CPU time 2.37 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:33 PM PDT 24
Peak memory 207640 kb
Host smart-64e39860-222e-478a-8f1b-5572e7928d43
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271056913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4271056913
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.795203239
Short name T685
Test name
Test status
Simulation time 129487058 ps
CPU time 4.96 seconds
Started Mar 31 03:54:24 PM PDT 24
Finished Mar 31 03:54:29 PM PDT 24
Peak memory 209244 kb
Host smart-0d365b91-5ba7-4dda-b0dc-eb633ace7085
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795203239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.795203239
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1699493274
Short name T423
Test name
Test status
Simulation time 66150950 ps
CPU time 2.28 seconds
Started Mar 31 03:54:34 PM PDT 24
Finished Mar 31 03:54:37 PM PDT 24
Peak memory 208832 kb
Host smart-184ca4a4-4d92-4e38-86ed-ac067b96755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699493274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1699493274
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.454407223
Short name T615
Test name
Test status
Simulation time 341956574 ps
CPU time 5.55 seconds
Started Mar 31 03:54:25 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 207016 kb
Host smart-7461f1eb-c5d6-4486-8498-ce9e724e6de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454407223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.454407223
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2269827802
Short name T210
Test name
Test status
Simulation time 166056585 ps
CPU time 5.51 seconds
Started Mar 31 03:54:24 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 214772 kb
Host smart-935860c5-92e5-458a-ae67-e86c1f837260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269827802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2269827802
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3603274238
Short name T537
Test name
Test status
Simulation time 874962096 ps
CPU time 5.97 seconds
Started Mar 31 03:54:28 PM PDT 24
Finished Mar 31 03:54:34 PM PDT 24
Peak memory 214680 kb
Host smart-a4262d61-12b7-4a83-bc2f-851edab3de67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603274238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3603274238
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1266228296
Short name T395
Test name
Test status
Simulation time 51833236 ps
CPU time 1.88 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:28 PM PDT 24
Peak memory 210328 kb
Host smart-4773f54d-99a6-4ebe-9a6f-d6508f5805bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266228296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1266228296
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3455805152
Short name T435
Test name
Test status
Simulation time 17729270 ps
CPU time 0.99 seconds
Started Mar 31 03:54:28 PM PDT 24
Finished Mar 31 03:54:29 PM PDT 24
Peak memory 206416 kb
Host smart-43e07c70-5a1e-46ba-95c4-1458e91c076f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455805152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3455805152
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.757622312
Short name T30
Test name
Test status
Simulation time 305565464 ps
CPU time 2.53 seconds
Started Mar 31 03:54:27 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 209796 kb
Host smart-ec192d60-d1cb-4e07-93bb-9b0cf8d8866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757622312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.757622312
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3486101005
Short name T111
Test name
Test status
Simulation time 253170290 ps
CPU time 3.27 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 209784 kb
Host smart-63a8b2fd-9bf5-44bf-81f7-9fa54238ce0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486101005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3486101005
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.389680249
Short name T96
Test name
Test status
Simulation time 218011488 ps
CPU time 8.89 seconds
Started Mar 31 03:54:27 PM PDT 24
Finished Mar 31 03:54:36 PM PDT 24
Peak memory 221496 kb
Host smart-7df3c1ca-df15-46ce-8d63-9f404d3967cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389680249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.389680249
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1449823495
Short name T355
Test name
Test status
Simulation time 6690556667 ps
CPU time 55.14 seconds
Started Mar 31 03:54:38 PM PDT 24
Finished Mar 31 03:55:33 PM PDT 24
Peak memory 226776 kb
Host smart-e535f294-0298-4e90-8fbc-bf4bbebd656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449823495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1449823495
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1194082642
Short name T582
Test name
Test status
Simulation time 558334069 ps
CPU time 2.4 seconds
Started Mar 31 03:54:24 PM PDT 24
Finished Mar 31 03:54:27 PM PDT 24
Peak memory 220192 kb
Host smart-c64a406c-f6af-4399-9547-a097ec45a763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194082642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1194082642
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4136149092
Short name T648
Test name
Test status
Simulation time 119189287 ps
CPU time 4.19 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 218524 kb
Host smart-5a036917-592b-4d9b-96c4-1b518b1ac2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136149092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4136149092
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1266870470
Short name T329
Test name
Test status
Simulation time 108212764 ps
CPU time 2.86 seconds
Started Mar 31 03:54:25 PM PDT 24
Finished Mar 31 03:54:28 PM PDT 24
Peak memory 207076 kb
Host smart-62e19c78-ab82-46f2-b55c-07b6313d7861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266870470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1266870470
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1782773184
Short name T886
Test name
Test status
Simulation time 416328657 ps
CPU time 3.66 seconds
Started Mar 31 03:54:39 PM PDT 24
Finished Mar 31 03:54:48 PM PDT 24
Peak memory 208732 kb
Host smart-2ddf13c6-7390-4cbb-a0b9-b8b5a1adfa13
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782773184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1782773184
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4022808543
Short name T566
Test name
Test status
Simulation time 188059847 ps
CPU time 7.24 seconds
Started Mar 31 03:54:28 PM PDT 24
Finished Mar 31 03:54:35 PM PDT 24
Peak memory 208780 kb
Host smart-2af1bd93-5ce6-4bda-bf76-d527dac10d46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022808543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4022808543
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2223650285
Short name T353
Test name
Test status
Simulation time 152125886 ps
CPU time 2.39 seconds
Started Mar 31 03:54:29 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 207196 kb
Host smart-e8a73772-fcb2-422e-ac2f-d0ef345dbc57
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223650285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2223650285
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3913852621
Short name T323
Test name
Test status
Simulation time 43072044 ps
CPU time 1.98 seconds
Started Mar 31 03:54:38 PM PDT 24
Finished Mar 31 03:54:40 PM PDT 24
Peak memory 207668 kb
Host smart-377d64f0-60d0-4789-9927-d3be5f407ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913852621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3913852621
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.528346470
Short name T618
Test name
Test status
Simulation time 583390562 ps
CPU time 4.89 seconds
Started Mar 31 03:54:34 PM PDT 24
Finished Mar 31 03:54:39 PM PDT 24
Peak memory 208576 kb
Host smart-b430f32c-19f5-4d94-b31a-7fb161318ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528346470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.528346470
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1989863801
Short name T63
Test name
Test status
Simulation time 757495125 ps
CPU time 16.25 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:42 PM PDT 24
Peak memory 222876 kb
Host smart-802e3b6d-2a2e-4383-a73f-5868ff8a2e30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989863801 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1989863801
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2591379678
Short name T789
Test name
Test status
Simulation time 9076482831 ps
CPU time 45.41 seconds
Started Mar 31 03:54:27 PM PDT 24
Finished Mar 31 03:55:12 PM PDT 24
Peak memory 209676 kb
Host smart-121a17cb-2e60-417f-b534-69076f40bbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591379678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2591379678
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2709821352
Short name T61
Test name
Test status
Simulation time 244731051 ps
CPU time 2.93 seconds
Started Mar 31 03:54:50 PM PDT 24
Finished Mar 31 03:54:53 PM PDT 24
Peak memory 210608 kb
Host smart-87889a3b-03bd-4c14-8164-52a26a4f215a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709821352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2709821352
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3105322992
Short name T761
Test name
Test status
Simulation time 26531894 ps
CPU time 0.69 seconds
Started Mar 31 03:54:34 PM PDT 24
Finished Mar 31 03:54:35 PM PDT 24
Peak memory 206072 kb
Host smart-6d527ee8-9c4d-4beb-9c97-76e116925907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105322992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3105322992
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2868700197
Short name T901
Test name
Test status
Simulation time 4123696834 ps
CPU time 12.73 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:39 PM PDT 24
Peak memory 209092 kb
Host smart-f1f4dea5-dd08-40ea-958d-1627d1897b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868700197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2868700197
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.409049565
Short name T336
Test name
Test status
Simulation time 3505838818 ps
CPU time 13.61 seconds
Started Mar 31 03:54:29 PM PDT 24
Finished Mar 31 03:54:43 PM PDT 24
Peak memory 222900 kb
Host smart-77bfa1dd-7927-4bf3-8e63-dbc1268aa7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409049565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.409049565
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3133303036
Short name T325
Test name
Test status
Simulation time 46012588 ps
CPU time 2.93 seconds
Started Mar 31 03:54:55 PM PDT 24
Finished Mar 31 03:54:58 PM PDT 24
Peak memory 214736 kb
Host smart-fb07b454-dc4c-461e-819e-832d7cea1f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133303036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3133303036
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1052559456
Short name T902
Test name
Test status
Simulation time 160429621 ps
CPU time 7.46 seconds
Started Mar 31 03:54:38 PM PDT 24
Finished Mar 31 03:54:46 PM PDT 24
Peak memory 207720 kb
Host smart-7525a04d-c504-4e0a-8bc9-99e1ed758dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052559456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1052559456
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1867893461
Short name T698
Test name
Test status
Simulation time 47415305 ps
CPU time 2.55 seconds
Started Mar 31 03:54:22 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 206660 kb
Host smart-99c8b696-c87d-4eaa-addc-b8a062c96224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867893461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1867893461
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.738866069
Short name T621
Test name
Test status
Simulation time 262998615 ps
CPU time 6.96 seconds
Started Mar 31 03:54:37 PM PDT 24
Finished Mar 31 03:54:44 PM PDT 24
Peak memory 208664 kb
Host smart-51817fa9-d8ae-447f-966e-5a6fcda4abed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738866069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.738866069
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2677977001
Short name T535
Test name
Test status
Simulation time 139993926 ps
CPU time 5.58 seconds
Started Mar 31 03:54:43 PM PDT 24
Finished Mar 31 03:54:49 PM PDT 24
Peak memory 208884 kb
Host smart-2bb0b2ae-972b-4cdb-89cb-940e85be53f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677977001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2677977001
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.329157747
Short name T693
Test name
Test status
Simulation time 217583686 ps
CPU time 3.05 seconds
Started Mar 31 03:54:34 PM PDT 24
Finished Mar 31 03:54:37 PM PDT 24
Peak memory 207080 kb
Host smart-6dffded4-fc28-449d-8e82-7b91a5ebe337
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329157747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.329157747
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2642618283
Short name T253
Test name
Test status
Simulation time 305532017 ps
CPU time 3.62 seconds
Started Mar 31 03:54:24 PM PDT 24
Finished Mar 31 03:54:28 PM PDT 24
Peak memory 218632 kb
Host smart-fd3d74a9-d6f6-4491-a389-ccb69d0b1863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642618283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2642618283
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.4076783195
Short name T624
Test name
Test status
Simulation time 1254669915 ps
CPU time 20.99 seconds
Started Mar 31 03:54:35 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 208744 kb
Host smart-a1f388a1-6f43-419c-b45a-8fffb9f2d575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076783195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.4076783195
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1793597035
Short name T815
Test name
Test status
Simulation time 905520959 ps
CPU time 23.67 seconds
Started Mar 31 03:54:35 PM PDT 24
Finished Mar 31 03:54:58 PM PDT 24
Peak memory 217868 kb
Host smart-8789261b-41e3-41eb-9855-2e8d81b033bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793597035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1793597035
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1001011030
Short name T266
Test name
Test status
Simulation time 663522450 ps
CPU time 3.49 seconds
Started Mar 31 03:54:27 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 208560 kb
Host smart-15e444dc-ea67-4493-8727-f86cba7d396e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001011030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1001011030
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1246049319
Short name T682
Test name
Test status
Simulation time 124438088 ps
CPU time 2.1 seconds
Started Mar 31 03:54:33 PM PDT 24
Finished Mar 31 03:54:35 PM PDT 24
Peak memory 210388 kb
Host smart-21f57888-ddce-4442-975d-98217b131641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246049319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1246049319
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.107465662
Short name T677
Test name
Test status
Simulation time 9424737 ps
CPU time 0.71 seconds
Started Mar 31 03:54:38 PM PDT 24
Finished Mar 31 03:54:38 PM PDT 24
Peak memory 206320 kb
Host smart-09f525e3-37a9-422c-a1d3-fdf51de7de48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107465662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.107465662
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.560643043
Short name T322
Test name
Test status
Simulation time 125421154 ps
CPU time 2.68 seconds
Started Mar 31 03:54:27 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 215596 kb
Host smart-77864587-3df7-4620-94f3-3405e0400ce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=560643043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.560643043
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3258056780
Short name T878
Test name
Test status
Simulation time 467247642 ps
CPU time 2.76 seconds
Started Mar 31 03:54:49 PM PDT 24
Finished Mar 31 03:54:52 PM PDT 24
Peak memory 209132 kb
Host smart-263c5d12-f416-439b-aff5-5a9bc0bdf74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258056780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3258056780
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2463074043
Short name T864
Test name
Test status
Simulation time 5525205131 ps
CPU time 28.03 seconds
Started Mar 31 03:54:34 PM PDT 24
Finished Mar 31 03:55:02 PM PDT 24
Peak memory 209816 kb
Host smart-d4c680d2-ecea-4d6a-b028-e5969c743f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463074043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2463074043
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1742932136
Short name T335
Test name
Test status
Simulation time 242421216 ps
CPU time 6.76 seconds
Started Mar 31 03:54:33 PM PDT 24
Finished Mar 31 03:54:40 PM PDT 24
Peak memory 214568 kb
Host smart-77ac310b-ede0-45e2-85ce-ef3332275248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742932136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1742932136
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3806786646
Short name T734
Test name
Test status
Simulation time 160276594 ps
CPU time 2.45 seconds
Started Mar 31 03:54:27 PM PDT 24
Finished Mar 31 03:54:29 PM PDT 24
Peak memory 208804 kb
Host smart-386177a3-3552-476f-9d97-7908c8ed5a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806786646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3806786646
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1619322407
Short name T722
Test name
Test status
Simulation time 384205403 ps
CPU time 4.94 seconds
Started Mar 31 03:54:51 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 214704 kb
Host smart-ee913cbb-bb68-4b20-a46c-4eb19d782a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619322407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1619322407
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1389172672
Short name T777
Test name
Test status
Simulation time 145930928 ps
CPU time 3.77 seconds
Started Mar 31 03:54:44 PM PDT 24
Finished Mar 31 03:54:48 PM PDT 24
Peak memory 209076 kb
Host smart-2814f9a0-ea02-4de1-9dc3-095eb4193620
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389172672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1389172672
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1278797605
Short name T449
Test name
Test status
Simulation time 123872652 ps
CPU time 4.12 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:27 PM PDT 24
Peak memory 208980 kb
Host smart-a038af04-2cec-4f80-9652-58683cf10620
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278797605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1278797605
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3752785372
Short name T41
Test name
Test status
Simulation time 925217273 ps
CPU time 3.99 seconds
Started Mar 31 03:54:24 PM PDT 24
Finished Mar 31 03:54:28 PM PDT 24
Peak memory 208976 kb
Host smart-c6be0ff6-5cdf-4cdf-a713-0745d8d5404b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752785372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3752785372
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3601898856
Short name T605
Test name
Test status
Simulation time 54937358 ps
CPU time 2.89 seconds
Started Mar 31 03:54:48 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 214708 kb
Host smart-3f7a2bb2-634c-4ffb-a871-16e2f9ab5315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601898856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3601898856
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3521492963
Short name T299
Test name
Test status
Simulation time 4301216160 ps
CPU time 38.6 seconds
Started Mar 31 03:54:46 PM PDT 24
Finished Mar 31 03:55:24 PM PDT 24
Peak memory 222324 kb
Host smart-dc447f17-1141-435a-af2d-68d59bfecd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521492963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3521492963
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2186678769
Short name T714
Test name
Test status
Simulation time 226949591 ps
CPU time 2.82 seconds
Started Mar 31 03:54:37 PM PDT 24
Finished Mar 31 03:54:40 PM PDT 24
Peak memory 210340 kb
Host smart-563e2c50-7f94-4f42-afec-8288657cb156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186678769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2186678769
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3428943746
Short name T101
Test name
Test status
Simulation time 46030756 ps
CPU time 0.81 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:54:55 PM PDT 24
Peak memory 206288 kb
Host smart-3325f73f-45d9-42e9-aa93-4243ef308319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428943746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3428943746
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.602049560
Short name T825
Test name
Test status
Simulation time 1533634062 ps
CPU time 41.62 seconds
Started Mar 31 03:54:36 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 222652 kb
Host smart-88ba37de-f697-4879-bcad-51f471765b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=602049560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.602049560
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1991031741
Short name T8
Test name
Test status
Simulation time 62038948 ps
CPU time 2.76 seconds
Started Mar 31 03:54:40 PM PDT 24
Finished Mar 31 03:54:43 PM PDT 24
Peak memory 223220 kb
Host smart-77d522cf-f15a-4595-8e18-fe9aa2a217e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991031741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1991031741
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.369526134
Short name T586
Test name
Test status
Simulation time 360015632 ps
CPU time 4.42 seconds
Started Mar 31 03:54:36 PM PDT 24
Finished Mar 31 03:54:41 PM PDT 24
Peak memory 214708 kb
Host smart-1fc5dc16-35d2-4f5c-81b4-7142270f6ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369526134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.369526134
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3013352999
Short name T808
Test name
Test status
Simulation time 33540208 ps
CPU time 2.63 seconds
Started Mar 31 03:54:40 PM PDT 24
Finished Mar 31 03:54:43 PM PDT 24
Peak memory 210192 kb
Host smart-1c49bb2d-a537-456d-adbf-c80205728541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013352999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3013352999
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2220573153
Short name T746
Test name
Test status
Simulation time 104241906 ps
CPU time 2.18 seconds
Started Mar 31 03:54:57 PM PDT 24
Finished Mar 31 03:55:00 PM PDT 24
Peak memory 208564 kb
Host smart-9adf6c1a-a21d-4dce-9acf-9c56262b193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220573153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2220573153
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2036896748
Short name T340
Test name
Test status
Simulation time 83137667 ps
CPU time 2.64 seconds
Started Mar 31 03:54:48 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 209256 kb
Host smart-97893cce-dc91-4f3e-a1d7-513b253e9715
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036896748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2036896748
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3120157293
Short name T485
Test name
Test status
Simulation time 218113847 ps
CPU time 2.88 seconds
Started Mar 31 03:54:58 PM PDT 24
Finished Mar 31 03:55:01 PM PDT 24
Peak memory 207184 kb
Host smart-bb99a633-13d8-453c-b0d7-56fc1613836b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120157293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3120157293
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2540303870
Short name T898
Test name
Test status
Simulation time 100047228 ps
CPU time 2.29 seconds
Started Mar 31 03:54:36 PM PDT 24
Finished Mar 31 03:54:38 PM PDT 24
Peak memory 209020 kb
Host smart-e361edc8-4d8a-4d41-9039-2a2f26359aa7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540303870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2540303870
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2721676443
Short name T533
Test name
Test status
Simulation time 72403083 ps
CPU time 3.16 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 210160 kb
Host smart-c6d53887-0c54-4b38-a743-44e93f36509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721676443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2721676443
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.475169032
Short name T468
Test name
Test status
Simulation time 69626763 ps
CPU time 2.87 seconds
Started Mar 31 03:54:50 PM PDT 24
Finished Mar 31 03:54:53 PM PDT 24
Peak memory 208740 kb
Host smart-9d55c443-e426-4713-8cd7-d334685aea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475169032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.475169032
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2946470443
Short name T230
Test name
Test status
Simulation time 1014569439 ps
CPU time 37.1 seconds
Started Mar 31 03:54:36 PM PDT 24
Finished Mar 31 03:55:14 PM PDT 24
Peak memory 215440 kb
Host smart-940ba9fe-6a15-45c6-bc2d-9cb0119f9187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946470443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2946470443
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4256517530
Short name T182
Test name
Test status
Simulation time 1021820643 ps
CPU time 21.17 seconds
Started Mar 31 03:54:42 PM PDT 24
Finished Mar 31 03:55:03 PM PDT 24
Peak memory 222996 kb
Host smart-77b317a7-e5c1-429c-a2e3-14cd5b949b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256517530 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4256517530
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1617867749
Short name T829
Test name
Test status
Simulation time 173798103 ps
CPU time 4.57 seconds
Started Mar 31 03:55:04 PM PDT 24
Finished Mar 31 03:55:08 PM PDT 24
Peak memory 208988 kb
Host smart-48860d49-ac22-494a-bfdd-95ce5b12c734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617867749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1617867749
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.110570394
Short name T706
Test name
Test status
Simulation time 54899109 ps
CPU time 2.65 seconds
Started Mar 31 03:54:41 PM PDT 24
Finished Mar 31 03:54:44 PM PDT 24
Peak memory 210216 kb
Host smart-1a9f4196-2fc9-42f2-9de8-abca30c551dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110570394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.110570394
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.58972122
Short name T700
Test name
Test status
Simulation time 9810506 ps
CPU time 0.85 seconds
Started Mar 31 03:54:47 PM PDT 24
Finished Mar 31 03:54:48 PM PDT 24
Peak memory 206264 kb
Host smart-a162935c-0006-4f2b-aae1-7a9135fb396d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58972122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.58972122
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1670696211
Short name T662
Test name
Test status
Simulation time 120924123 ps
CPU time 5.02 seconds
Started Mar 31 03:54:58 PM PDT 24
Finished Mar 31 03:55:03 PM PDT 24
Peak memory 210924 kb
Host smart-af43bd7b-a35d-40ef-8586-ce75042f0c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670696211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1670696211
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.4109119882
Short name T709
Test name
Test status
Simulation time 84351335 ps
CPU time 3.3 seconds
Started Mar 31 03:54:50 PM PDT 24
Finished Mar 31 03:54:54 PM PDT 24
Peak memory 209344 kb
Host smart-70081c0f-0333-4eb1-a705-fa88df5b23d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109119882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.4109119882
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.607782009
Short name T402
Test name
Test status
Simulation time 259784739 ps
CPU time 6.51 seconds
Started Mar 31 03:54:45 PM PDT 24
Finished Mar 31 03:54:52 PM PDT 24
Peak memory 214652 kb
Host smart-a2e01e6d-79e0-4b52-bd9c-dacc8984bffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607782009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.607782009
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1700295906
Short name T291
Test name
Test status
Simulation time 474771173 ps
CPU time 5.6 seconds
Started Mar 31 03:54:51 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 222796 kb
Host smart-a7c3bdd0-4c28-4303-adf4-63164a8d975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700295906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1700295906
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3356368263
Short name T56
Test name
Test status
Simulation time 548462568 ps
CPU time 4.28 seconds
Started Mar 31 03:54:44 PM PDT 24
Finished Mar 31 03:54:49 PM PDT 24
Peak memory 210764 kb
Host smart-0823fa23-5a52-4541-a951-f91ffc26ad2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356368263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3356368263
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3769589733
Short name T861
Test name
Test status
Simulation time 72669994 ps
CPU time 3 seconds
Started Mar 31 03:54:54 PM PDT 24
Finished Mar 31 03:54:57 PM PDT 24
Peak memory 214572 kb
Host smart-80883e00-83f4-4503-9e7c-2d9fe3fb3e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769589733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3769589733
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3583039780
Short name T737
Test name
Test status
Simulation time 132334031 ps
CPU time 3.96 seconds
Started Mar 31 03:54:40 PM PDT 24
Finished Mar 31 03:54:44 PM PDT 24
Peak memory 207172 kb
Host smart-b8b99676-6dfe-4c2a-8b7c-0e0764c89507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583039780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3583039780
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1203830591
Short name T499
Test name
Test status
Simulation time 198580910 ps
CPU time 3.49 seconds
Started Mar 31 03:54:46 PM PDT 24
Finished Mar 31 03:54:50 PM PDT 24
Peak memory 207100 kb
Host smart-21ce718b-1e7a-49a0-93c9-a7e39f768d41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203830591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1203830591
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2645944388
Short name T823
Test name
Test status
Simulation time 41113160 ps
CPU time 2.36 seconds
Started Mar 31 03:54:29 PM PDT 24
Finished Mar 31 03:54:32 PM PDT 24
Peak memory 207112 kb
Host smart-ad84df6f-872a-4869-82a8-ee8b8e9ecc87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645944388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2645944388
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3011667551
Short name T339
Test name
Test status
Simulation time 76459910 ps
CPU time 3.73 seconds
Started Mar 31 03:54:43 PM PDT 24
Finished Mar 31 03:54:47 PM PDT 24
Peak memory 209204 kb
Host smart-59f361fe-452f-4698-bf84-1fee226c287c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011667551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3011667551
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1332714381
Short name T358
Test name
Test status
Simulation time 2867268330 ps
CPU time 10.64 seconds
Started Mar 31 03:54:43 PM PDT 24
Finished Mar 31 03:54:53 PM PDT 24
Peak memory 214904 kb
Host smart-f98b4e2c-7f83-419a-b399-f8f79733e05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332714381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1332714381
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1956014655
Short name T610
Test name
Test status
Simulation time 226859556 ps
CPU time 2.89 seconds
Started Mar 31 03:54:40 PM PDT 24
Finished Mar 31 03:54:43 PM PDT 24
Peak memory 207044 kb
Host smart-d4b9ab1e-c96e-4a67-bd77-1d4d3b659fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956014655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1956014655
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.497723180
Short name T77
Test name
Test status
Simulation time 206406199 ps
CPU time 14.95 seconds
Started Mar 31 03:54:51 PM PDT 24
Finished Mar 31 03:55:06 PM PDT 24
Peak memory 222672 kb
Host smart-0baa5afd-05ec-41c2-a365-3e700bcaf390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497723180 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.497723180
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3650411251
Short name T833
Test name
Test status
Simulation time 788296039 ps
CPU time 9.2 seconds
Started Mar 31 03:54:52 PM PDT 24
Finished Mar 31 03:55:02 PM PDT 24
Peak memory 214740 kb
Host smart-c2687484-8538-40b1-ac54-007a5571d4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650411251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3650411251
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4129931676
Short name T766
Test name
Test status
Simulation time 52467341 ps
CPU time 2.47 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 210368 kb
Host smart-56f35cdb-c6b4-4beb-a9d8-d0668808865f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129931676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4129931676
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3783180127
Short name T634
Test name
Test status
Simulation time 16658171 ps
CPU time 0.97 seconds
Started Mar 31 03:54:46 PM PDT 24
Finished Mar 31 03:54:47 PM PDT 24
Peak memory 206452 kb
Host smart-c118f612-5d21-4f9b-ae19-ed0442158343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783180127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3783180127
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4247408676
Short name T32
Test name
Test status
Simulation time 67247516 ps
CPU time 2.85 seconds
Started Mar 31 03:54:49 PM PDT 24
Finished Mar 31 03:54:52 PM PDT 24
Peak memory 208860 kb
Host smart-4a3cc223-149f-4066-ab1e-f0e324683f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247408676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4247408676
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3125068686
Short name T603
Test name
Test status
Simulation time 65531309 ps
CPU time 2.21 seconds
Started Mar 31 03:55:12 PM PDT 24
Finished Mar 31 03:55:14 PM PDT 24
Peak memory 208612 kb
Host smart-a6335735-74ab-4771-bdd9-82d12b47d7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125068686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3125068686
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.436062201
Short name T794
Test name
Test status
Simulation time 714985732 ps
CPU time 4.89 seconds
Started Mar 31 03:54:54 PM PDT 24
Finished Mar 31 03:55:00 PM PDT 24
Peak memory 214636 kb
Host smart-ae0a3527-5c70-428a-850f-ae1d8873e8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436062201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.436062201
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.388238369
Short name T374
Test name
Test status
Simulation time 1196942420 ps
CPU time 34.39 seconds
Started Mar 31 03:54:45 PM PDT 24
Finished Mar 31 03:55:20 PM PDT 24
Peak memory 222252 kb
Host smart-7ed8ddf6-8460-4681-8649-9a8f70b1e799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388238369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.388238369
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1156765662
Short name T297
Test name
Test status
Simulation time 1496268851 ps
CPU time 4.69 seconds
Started Mar 31 03:54:48 PM PDT 24
Finished Mar 31 03:54:52 PM PDT 24
Peak memory 220332 kb
Host smart-968e1b54-0d78-471e-ab51-256b97a7713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156765662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1156765662
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1469899279
Short name T461
Test name
Test status
Simulation time 2152833137 ps
CPU time 8.88 seconds
Started Mar 31 03:54:57 PM PDT 24
Finished Mar 31 03:55:06 PM PDT 24
Peak memory 208780 kb
Host smart-ad8b6964-b8b3-4278-8174-29ca7085f0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469899279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1469899279
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2179122929
Short name T903
Test name
Test status
Simulation time 1256244504 ps
CPU time 13.73 seconds
Started Mar 31 03:54:45 PM PDT 24
Finished Mar 31 03:54:59 PM PDT 24
Peak memory 208144 kb
Host smart-edc71396-1729-4df6-baac-7a0e6e0d3983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179122929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2179122929
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1095008195
Short name T572
Test name
Test status
Simulation time 27294344 ps
CPU time 2.13 seconds
Started Mar 31 03:54:52 PM PDT 24
Finished Mar 31 03:54:54 PM PDT 24
Peak memory 209128 kb
Host smart-99ec077c-c286-4aa0-8c24-78091845126e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095008195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1095008195
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.273480905
Short name T641
Test name
Test status
Simulation time 80147980 ps
CPU time 4.2 seconds
Started Mar 31 03:54:52 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 208812 kb
Host smart-debced49-0c38-43b5-8672-080dd4c9df73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273480905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.273480905
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3692146416
Short name T406
Test name
Test status
Simulation time 711210810 ps
CPU time 8.43 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:55:02 PM PDT 24
Peak memory 207268 kb
Host smart-6f86548f-74ef-49d6-b42b-afaa6949e572
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692146416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3692146416
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2155612042
Short name T803
Test name
Test status
Simulation time 554132409 ps
CPU time 4.44 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:54:57 PM PDT 24
Peak memory 209176 kb
Host smart-b8e90e26-217d-41c8-b49f-93c1d7074a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155612042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2155612042
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3345707987
Short name T730
Test name
Test status
Simulation time 148582217 ps
CPU time 4.05 seconds
Started Mar 31 03:54:43 PM PDT 24
Finished Mar 31 03:54:47 PM PDT 24
Peak memory 208632 kb
Host smart-51d95c20-a934-41e7-ba6e-a8096a678dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345707987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3345707987
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.815869985
Short name T463
Test name
Test status
Simulation time 60623986 ps
CPU time 2.48 seconds
Started Mar 31 03:54:42 PM PDT 24
Finished Mar 31 03:54:44 PM PDT 24
Peak memory 207864 kb
Host smart-48604f4e-3dc3-479c-bf8f-090337475674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815869985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.815869985
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1196123459
Short name T68
Test name
Test status
Simulation time 4041738984 ps
CPU time 20.64 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:55:15 PM PDT 24
Peak memory 221836 kb
Host smart-a7e0394c-e46e-4ea5-84d3-04b1d33b0a63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196123459 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1196123459
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1255325169
Short name T200
Test name
Test status
Simulation time 173938060 ps
CPU time 3.46 seconds
Started Mar 31 03:54:46 PM PDT 24
Finished Mar 31 03:54:49 PM PDT 24
Peak memory 210444 kb
Host smart-75740f75-55d6-4ce7-9727-e17636466698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255325169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1255325169
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.431127007
Short name T597
Test name
Test status
Simulation time 23607053 ps
CPU time 0.79 seconds
Started Mar 31 03:54:50 PM PDT 24
Finished Mar 31 03:54:50 PM PDT 24
Peak memory 206312 kb
Host smart-655b0f0f-b416-4e93-aec0-984406c96351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431127007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.431127007
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2542874202
Short name T388
Test name
Test status
Simulation time 2624276823 ps
CPU time 20.81 seconds
Started Mar 31 03:54:59 PM PDT 24
Finished Mar 31 03:55:20 PM PDT 24
Peak memory 223248 kb
Host smart-937270a1-b7b5-47f4-93a6-ae6e2b8795e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542874202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2542874202
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2973091216
Short name T262
Test name
Test status
Simulation time 699754151 ps
CPU time 4.83 seconds
Started Mar 31 03:54:44 PM PDT 24
Finished Mar 31 03:54:49 PM PDT 24
Peak memory 218516 kb
Host smart-d14d87dc-b1d8-4db9-bd79-52a53e2171e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973091216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2973091216
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3379208096
Short name T256
Test name
Test status
Simulation time 136143307 ps
CPU time 3.09 seconds
Started Mar 31 03:54:48 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 208972 kb
Host smart-b6f5610e-24bf-41d1-95c9-cbe34ccf38e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379208096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3379208096
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2956490531
Short name T207
Test name
Test status
Simulation time 147535726 ps
CPU time 3.96 seconds
Started Mar 31 03:54:41 PM PDT 24
Finished Mar 31 03:54:45 PM PDT 24
Peak memory 214536 kb
Host smart-ef695e0c-fae3-4299-baf1-e069cd58753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956490531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2956490531
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4209364482
Short name T870
Test name
Test status
Simulation time 409244052 ps
CPU time 3.92 seconds
Started Mar 31 03:54:47 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 220200 kb
Host smart-1167b5bd-7097-409a-bb9a-fb9e6533c2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209364482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4209364482
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_sideload.372357495
Short name T512
Test name
Test status
Simulation time 138241755 ps
CPU time 1.83 seconds
Started Mar 31 03:54:49 PM PDT 24
Finished Mar 31 03:54:50 PM PDT 24
Peak memory 207552 kb
Host smart-b4792f08-c3db-42d9-8038-e672215e65ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372357495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.372357495
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3366582177
Short name T384
Test name
Test status
Simulation time 31743653 ps
CPU time 2.22 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:55:01 PM PDT 24
Peak memory 207076 kb
Host smart-c39ea702-e8a1-4879-8807-cd5e6dee624a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366582177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3366582177
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2267507755
Short name T517
Test name
Test status
Simulation time 193443122 ps
CPU time 2.87 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:54:55 PM PDT 24
Peak memory 207240 kb
Host smart-186232aa-0f31-41b3-8836-04d700af4ed8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267507755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2267507755
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2667810155
Short name T772
Test name
Test status
Simulation time 190423506 ps
CPU time 4 seconds
Started Mar 31 03:54:41 PM PDT 24
Finished Mar 31 03:54:45 PM PDT 24
Peak memory 208924 kb
Host smart-c234f372-5119-475d-8fd2-0ea108ac4fce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667810155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2667810155
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1305438704
Short name T576
Test name
Test status
Simulation time 88134450 ps
CPU time 3.35 seconds
Started Mar 31 03:54:46 PM PDT 24
Finished Mar 31 03:54:49 PM PDT 24
Peak memory 215620 kb
Host smart-15a17388-087a-46c1-93d1-e0d77b0ceea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305438704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1305438704
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3330218848
Short name T764
Test name
Test status
Simulation time 52641583 ps
CPU time 2.55 seconds
Started Mar 31 03:54:46 PM PDT 24
Finished Mar 31 03:54:49 PM PDT 24
Peak memory 207068 kb
Host smart-4f178a1a-f866-4a6d-b0f4-da5cfa56fedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330218848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3330218848
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1295505785
Short name T81
Test name
Test status
Simulation time 7777500319 ps
CPU time 229.76 seconds
Started Mar 31 03:54:55 PM PDT 24
Finished Mar 31 03:58:45 PM PDT 24
Peak memory 221436 kb
Host smart-fc99815e-2d3c-4e83-a39f-6c290a43bf3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295505785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1295505785
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2791628134
Short name T836
Test name
Test status
Simulation time 232647848 ps
CPU time 8.8 seconds
Started Mar 31 03:54:46 PM PDT 24
Finished Mar 31 03:54:55 PM PDT 24
Peak memory 218860 kb
Host smart-3fdb15d6-debb-4c27-a3c1-fe50b428daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791628134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2791628134
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1813584699
Short name T518
Test name
Test status
Simulation time 680705646 ps
CPU time 12.86 seconds
Started Mar 31 03:54:44 PM PDT 24
Finished Mar 31 03:55:02 PM PDT 24
Peak memory 211076 kb
Host smart-92e7a300-12f1-4523-800f-d5ec130138e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813584699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1813584699
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2638094365
Short name T103
Test name
Test status
Simulation time 40081381 ps
CPU time 0.72 seconds
Started Mar 31 03:54:05 PM PDT 24
Finished Mar 31 03:54:06 PM PDT 24
Peak memory 206296 kb
Host smart-4e6551ad-d426-41a3-9f77-3d24c6742fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638094365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2638094365
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.453023801
Short name T432
Test name
Test status
Simulation time 4412960051 ps
CPU time 118.19 seconds
Started Mar 31 03:54:07 PM PDT 24
Finished Mar 31 03:56:06 PM PDT 24
Peak memory 215096 kb
Host smart-e7130b76-ca29-4c87-827f-2e6744b3e97e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453023801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.453023801
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3444110900
Short name T581
Test name
Test status
Simulation time 355018410 ps
CPU time 6.39 seconds
Started Mar 31 03:54:05 PM PDT 24
Finished Mar 31 03:54:13 PM PDT 24
Peak memory 218928 kb
Host smart-cec2f129-df85-4fdc-8540-65edbbae0081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444110900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3444110900
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3958281603
Short name T307
Test name
Test status
Simulation time 27787536 ps
CPU time 2.26 seconds
Started Mar 31 03:54:02 PM PDT 24
Finished Mar 31 03:54:06 PM PDT 24
Peak memory 207900 kb
Host smart-9637069b-ebe7-44f2-86fc-ee8e6db1267a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958281603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3958281603
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3662867057
Short name T278
Test name
Test status
Simulation time 1016055041 ps
CPU time 8.16 seconds
Started Mar 31 03:54:09 PM PDT 24
Finished Mar 31 03:54:18 PM PDT 24
Peak memory 209880 kb
Host smart-1555e260-e838-4088-92bf-94e3f5e7b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662867057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3662867057
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_random.3570619092
Short name T788
Test name
Test status
Simulation time 738767094 ps
CPU time 7.85 seconds
Started Mar 31 03:53:43 PM PDT 24
Finished Mar 31 03:53:51 PM PDT 24
Peak memory 208992 kb
Host smart-8e67bbd0-2c30-45df-a52c-e1dce3278643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570619092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3570619092
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1289760634
Short name T10
Test name
Test status
Simulation time 4960083116 ps
CPU time 16.7 seconds
Started Mar 31 03:53:54 PM PDT 24
Finished Mar 31 03:54:12 PM PDT 24
Peak memory 239700 kb
Host smart-4b000e26-9d61-46ec-99fe-b0b63b3a3a17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289760634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1289760634
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3724398800
Short name T590
Test name
Test status
Simulation time 52145193 ps
CPU time 2.74 seconds
Started Mar 31 03:53:59 PM PDT 24
Finished Mar 31 03:54:02 PM PDT 24
Peak memory 208204 kb
Host smart-0361e949-1a27-4382-bbff-73ac8639e355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724398800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3724398800
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.824555543
Short name T683
Test name
Test status
Simulation time 225959713 ps
CPU time 4.99 seconds
Started Mar 31 03:53:55 PM PDT 24
Finished Mar 31 03:54:00 PM PDT 24
Peak memory 207984 kb
Host smart-33af0b57-6cf8-4f8a-a8c4-1b801e9656f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824555543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.824555543
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.214136579
Short name T497
Test name
Test status
Simulation time 174597128 ps
CPU time 5.86 seconds
Started Mar 31 03:54:02 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 208948 kb
Host smart-b39af502-74b7-4475-8980-c8640553bf93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214136579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.214136579
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.223887836
Short name T511
Test name
Test status
Simulation time 6885750068 ps
CPU time 69.1 seconds
Started Mar 31 03:54:08 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 209588 kb
Host smart-ea1be8ea-0266-41d5-85b0-d5aea6964b77
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223887836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.223887836
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3591415625
Short name T305
Test name
Test status
Simulation time 80799912 ps
CPU time 3.58 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 215868 kb
Host smart-919144f6-9c40-45dd-84f6-17fe81299905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591415625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3591415625
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2005405896
Short name T457
Test name
Test status
Simulation time 468666520 ps
CPU time 4.96 seconds
Started Mar 31 03:53:52 PM PDT 24
Finished Mar 31 03:53:57 PM PDT 24
Peak memory 208644 kb
Host smart-aa4841a6-06e2-4055-87ea-72387f8bf2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005405896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2005405896
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2994846507
Short name T236
Test name
Test status
Simulation time 750143067 ps
CPU time 31.45 seconds
Started Mar 31 03:54:06 PM PDT 24
Finished Mar 31 03:54:38 PM PDT 24
Peak memory 216640 kb
Host smart-49736fed-ddcc-406f-ab04-04e668dfca25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994846507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2994846507
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2072667180
Short name T244
Test name
Test status
Simulation time 454953285 ps
CPU time 10.33 seconds
Started Mar 31 03:54:00 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 210620 kb
Host smart-cc33b55d-ad2f-4690-8c37-b3ed44b39a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072667180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2072667180
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2603739652
Short name T729
Test name
Test status
Simulation time 109178315 ps
CPU time 1.72 seconds
Started Mar 31 03:54:08 PM PDT 24
Finished Mar 31 03:54:11 PM PDT 24
Peak memory 209940 kb
Host smart-59afc7ed-21ea-40f2-8d32-67f81be227f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603739652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2603739652
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2385071520
Short name T560
Test name
Test status
Simulation time 59824885 ps
CPU time 0.77 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:54:55 PM PDT 24
Peak memory 206304 kb
Host smart-d56a566a-b963-48c1-a905-a056b45c8efa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385071520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2385071520
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1363799127
Short name T885
Test name
Test status
Simulation time 457864305 ps
CPU time 4.65 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 218700 kb
Host smart-03c3a13b-42aa-48c7-b8d7-8cb9c941c9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363799127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1363799127
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.489853406
Short name T51
Test name
Test status
Simulation time 193856527 ps
CPU time 3.57 seconds
Started Mar 31 03:54:59 PM PDT 24
Finished Mar 31 03:55:02 PM PDT 24
Peak memory 210072 kb
Host smart-190eab6d-2206-4883-88e9-dee6ed2e1f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489853406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.489853406
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1739120961
Short name T828
Test name
Test status
Simulation time 330607687 ps
CPU time 11.56 seconds
Started Mar 31 03:55:08 PM PDT 24
Finished Mar 31 03:55:20 PM PDT 24
Peak memory 210000 kb
Host smart-a2292d82-20fe-4258-9e10-c3531be5bcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739120961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1739120961
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1031642920
Short name T6
Test name
Test status
Simulation time 586421113 ps
CPU time 4.08 seconds
Started Mar 31 03:55:03 PM PDT 24
Finished Mar 31 03:55:07 PM PDT 24
Peak memory 220252 kb
Host smart-8d43d155-8aac-45b5-b930-34a864f1e075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031642920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1031642920
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.432334823
Short name T800
Test name
Test status
Simulation time 508310721 ps
CPU time 13.43 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:14 PM PDT 24
Peak memory 208804 kb
Host smart-98374610-af27-4302-9cfc-472bfab7bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432334823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.432334823
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2466773558
Short name T243
Test name
Test status
Simulation time 377316541 ps
CPU time 4.99 seconds
Started Mar 31 03:54:49 PM PDT 24
Finished Mar 31 03:54:54 PM PDT 24
Peak memory 207204 kb
Host smart-9e49f92e-2e92-479b-b065-3601a5b0fffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466773558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2466773558
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2242373123
Short name T220
Test name
Test status
Simulation time 155323181 ps
CPU time 3.66 seconds
Started Mar 31 03:54:47 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 208888 kb
Host smart-02443db5-9b9a-4f04-b778-aaac7eb950d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242373123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2242373123
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.711196888
Short name T242
Test name
Test status
Simulation time 1541796066 ps
CPU time 26.84 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 208440 kb
Host smart-1f8b3ef6-c907-48cc-81e6-baa756ac26d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711196888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.711196888
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1637819983
Short name T562
Test name
Test status
Simulation time 47249661 ps
CPU time 2.57 seconds
Started Mar 31 03:54:51 PM PDT 24
Finished Mar 31 03:54:54 PM PDT 24
Peak memory 207368 kb
Host smart-3d5efdd4-591e-4c9b-a16b-217f76ad0a66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637819983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1637819983
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2718070726
Short name T638
Test name
Test status
Simulation time 283488987 ps
CPU time 2.55 seconds
Started Mar 31 03:56:31 PM PDT 24
Finished Mar 31 03:56:33 PM PDT 24
Peak memory 209240 kb
Host smart-fdb43e96-a5f9-49d3-b5de-b9116ea27f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718070726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2718070726
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.576913846
Short name T440
Test name
Test status
Simulation time 165457430 ps
CPU time 5.14 seconds
Started Mar 31 03:54:45 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 206920 kb
Host smart-2d98857a-fd75-4511-a563-568798abd8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576913846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.576913846
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1891109502
Short name T851
Test name
Test status
Simulation time 786274785 ps
CPU time 20.54 seconds
Started Mar 31 03:54:46 PM PDT 24
Finished Mar 31 03:55:06 PM PDT 24
Peak memory 216072 kb
Host smart-f6836eb7-a4d2-4969-9194-06ff4ea168ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891109502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1891109502
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.718794833
Short name T128
Test name
Test status
Simulation time 726502404 ps
CPU time 10.5 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:12 PM PDT 24
Peak memory 220308 kb
Host smart-211ace80-e75c-49fd-8751-ff3bc4295af4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718794833 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.718794833
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1930686249
Short name T680
Test name
Test status
Simulation time 62453274 ps
CPU time 3.16 seconds
Started Mar 31 03:54:59 PM PDT 24
Finished Mar 31 03:55:02 PM PDT 24
Peak memory 207484 kb
Host smart-7777b08b-ff7d-4e27-9c7e-fa9850e029fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930686249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1930686249
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.65195840
Short name T531
Test name
Test status
Simulation time 54474990 ps
CPU time 1.35 seconds
Started Mar 31 03:54:54 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 209824 kb
Host smart-b2513800-03ea-4861-b75c-e314bbdf1267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65195840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.65195840
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1139777334
Short name T742
Test name
Test status
Simulation time 28784900 ps
CPU time 0.76 seconds
Started Mar 31 03:54:50 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 206216 kb
Host smart-c06dc512-ddb9-4f36-9622-5bec4a01d366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139777334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1139777334
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.138364464
Short name T38
Test name
Test status
Simulation time 1466765213 ps
CPU time 15.48 seconds
Started Mar 31 03:54:50 PM PDT 24
Finished Mar 31 03:55:05 PM PDT 24
Peak memory 220112 kb
Host smart-57e3af8b-eb4c-4021-96a0-b1c50da70cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138364464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.138364464
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.639440276
Short name T467
Test name
Test status
Simulation time 144159981 ps
CPU time 2.1 seconds
Started Mar 31 03:54:47 PM PDT 24
Finished Mar 31 03:54:50 PM PDT 24
Peak memory 222796 kb
Host smart-1b3caec4-8565-4cd4-ac92-bdee4d0a0a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639440276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.639440276
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2480953217
Short name T22
Test name
Test status
Simulation time 1107547195 ps
CPU time 33.2 seconds
Started Mar 31 03:54:47 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 214660 kb
Host smart-88c283bb-a99e-4c08-9cbb-23af109ccd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480953217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2480953217
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3462035559
Short name T218
Test name
Test status
Simulation time 110013808 ps
CPU time 5.15 seconds
Started Mar 31 03:55:05 PM PDT 24
Finished Mar 31 03:55:11 PM PDT 24
Peak memory 214572 kb
Host smart-9581d661-8b24-4dc4-a0b5-d0ffe12a5345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462035559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3462035559
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3140956322
Short name T775
Test name
Test status
Simulation time 143373654 ps
CPU time 4.69 seconds
Started Mar 31 03:54:51 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 214664 kb
Host smart-90df58df-ed49-45af-92f3-6333e4d88a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140956322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3140956322
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2967020118
Short name T869
Test name
Test status
Simulation time 305923053 ps
CPU time 4.01 seconds
Started Mar 31 03:55:00 PM PDT 24
Finished Mar 31 03:55:04 PM PDT 24
Peak memory 207924 kb
Host smart-99b36f6e-c283-4bc5-a844-6bd3f8bfbed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967020118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2967020118
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1545189626
Short name T470
Test name
Test status
Simulation time 457296640 ps
CPU time 8.64 seconds
Started Mar 31 03:55:12 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 208372 kb
Host smart-4b346eb6-11c9-4c2f-a804-5ae1e6ae5dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545189626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1545189626
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3928998403
Short name T525
Test name
Test status
Simulation time 139470504 ps
CPU time 4.36 seconds
Started Mar 31 03:54:52 PM PDT 24
Finished Mar 31 03:54:57 PM PDT 24
Peak memory 208904 kb
Host smart-09cf8a52-3328-4832-b081-f91549aa2c32
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928998403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3928998403
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3455554839
Short name T728
Test name
Test status
Simulation time 114693031 ps
CPU time 4.88 seconds
Started Mar 31 03:54:54 PM PDT 24
Finished Mar 31 03:54:59 PM PDT 24
Peak memory 207244 kb
Host smart-adcf4f77-bfec-41a9-98ac-610d3e24f54f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455554839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3455554839
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3915198461
Short name T758
Test name
Test status
Simulation time 195076618 ps
CPU time 6.84 seconds
Started Mar 31 03:54:47 PM PDT 24
Finished Mar 31 03:54:54 PM PDT 24
Peak memory 208112 kb
Host smart-3c690652-b971-4df8-b6b9-182cf179a01e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915198461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3915198461
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2009232709
Short name T341
Test name
Test status
Simulation time 651215986 ps
CPU time 2.48 seconds
Started Mar 31 03:54:57 PM PDT 24
Finished Mar 31 03:55:00 PM PDT 24
Peak memory 208800 kb
Host smart-2c1650ba-796c-4d49-9374-e0701f4fd03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009232709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2009232709
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2787793454
Short name T620
Test name
Test status
Simulation time 57490563 ps
CPU time 2.89 seconds
Started Mar 31 03:55:02 PM PDT 24
Finished Mar 31 03:55:06 PM PDT 24
Peak memory 208200 kb
Host smart-ebe1ee0a-51f3-4822-807a-de45e39c77cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787793454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2787793454
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.333677689
Short name T295
Test name
Test status
Simulation time 44318201 ps
CPU time 2.52 seconds
Started Mar 31 03:54:52 PM PDT 24
Finished Mar 31 03:54:55 PM PDT 24
Peak memory 214564 kb
Host smart-3efca7fa-a9ac-49c1-a5a4-baa7a844d6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333677689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.333677689
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3840390781
Short name T807
Test name
Test status
Simulation time 146946625 ps
CPU time 1.49 seconds
Started Mar 31 03:56:20 PM PDT 24
Finished Mar 31 03:56:22 PM PDT 24
Peak memory 208704 kb
Host smart-acd6b3d8-d16f-46ce-8f7f-75a5e2b61327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840390781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3840390781
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3857193177
Short name T503
Test name
Test status
Simulation time 33698327 ps
CPU time 1.04 seconds
Started Mar 31 03:55:03 PM PDT 24
Finished Mar 31 03:55:05 PM PDT 24
Peak memory 206496 kb
Host smart-63c03db8-94a5-428a-98ad-a7931bc76202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857193177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3857193177
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.809390984
Short name T135
Test name
Test status
Simulation time 210252404 ps
CPU time 3.61 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 214604 kb
Host smart-93142e3e-ab7c-4e9c-948c-203e1a31d721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809390984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.809390984
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2452323869
Short name T819
Test name
Test status
Simulation time 671207376 ps
CPU time 5.2 seconds
Started Mar 31 03:54:55 PM PDT 24
Finished Mar 31 03:55:00 PM PDT 24
Peak memory 208556 kb
Host smart-16ce5324-6d89-4072-a9a3-d43afba41428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452323869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2452323869
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2145303547
Short name T478
Test name
Test status
Simulation time 123819283 ps
CPU time 5.09 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:14 PM PDT 24
Peak memory 209720 kb
Host smart-594ded5c-f968-4c1e-880d-476e65ba6fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145303547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2145303547
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1739736239
Short name T213
Test name
Test status
Simulation time 837686308 ps
CPU time 10.74 seconds
Started Mar 31 03:54:51 PM PDT 24
Finished Mar 31 03:55:02 PM PDT 24
Peak memory 222804 kb
Host smart-d73bd454-98e4-4652-b08d-4beafe8d7fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739736239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1739736239
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3475204339
Short name T646
Test name
Test status
Simulation time 147478754 ps
CPU time 2.63 seconds
Started Mar 31 03:54:43 PM PDT 24
Finished Mar 31 03:54:46 PM PDT 24
Peak memory 214688 kb
Host smart-cb9a402d-f4d1-4e64-907d-85fc23f772ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475204339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3475204339
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.516727172
Short name T286
Test name
Test status
Simulation time 44598371 ps
CPU time 2.97 seconds
Started Mar 31 03:54:55 PM PDT 24
Finished Mar 31 03:54:58 PM PDT 24
Peak memory 209612 kb
Host smart-416e60e3-da3c-4422-99cf-8208ef322eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516727172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.516727172
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.296818899
Short name T845
Test name
Test status
Simulation time 149333872 ps
CPU time 5.15 seconds
Started Mar 31 03:55:03 PM PDT 24
Finished Mar 31 03:55:09 PM PDT 24
Peak memory 206988 kb
Host smart-3e11bd8a-dbba-4fda-a7ee-dab6a11ad08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296818899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.296818899
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3137249191
Short name T469
Test name
Test status
Simulation time 946110170 ps
CPU time 20.43 seconds
Started Mar 31 03:54:58 PM PDT 24
Finished Mar 31 03:55:18 PM PDT 24
Peak memory 208408 kb
Host smart-43b9de71-467a-4fc2-a46c-aa0775698a1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137249191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3137249191
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1399206297
Short name T733
Test name
Test status
Simulation time 1556209149 ps
CPU time 7.76 seconds
Started Mar 31 03:56:32 PM PDT 24
Finished Mar 31 03:56:40 PM PDT 24
Peak memory 209348 kb
Host smart-ad4a7c8d-154d-4af2-81b8-19fc2037df58
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399206297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1399206297
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1588996046
Short name T216
Test name
Test status
Simulation time 130697324 ps
CPU time 2.5 seconds
Started Mar 31 03:54:59 PM PDT 24
Finished Mar 31 03:55:01 PM PDT 24
Peak memory 207484 kb
Host smart-05d8181a-b020-4cc2-8950-072d8527485e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588996046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1588996046
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.248454445
Short name T294
Test name
Test status
Simulation time 41737477 ps
CPU time 2.78 seconds
Started Mar 31 03:54:49 PM PDT 24
Finished Mar 31 03:54:52 PM PDT 24
Peak memory 209432 kb
Host smart-c1cf0192-ed93-4c17-b1ef-d264864b3bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248454445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.248454445
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3172203531
Short name T767
Test name
Test status
Simulation time 622288325 ps
CPU time 17.04 seconds
Started Mar 31 03:54:58 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 209020 kb
Host smart-574caf0a-7b61-448f-801e-6ea11957fceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172203531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3172203531
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2313331712
Short name T281
Test name
Test status
Simulation time 137165886 ps
CPU time 3.55 seconds
Started Mar 31 03:54:53 PM PDT 24
Finished Mar 31 03:54:58 PM PDT 24
Peak memory 214700 kb
Host smart-fbbba357-17b9-4727-b193-5fa8d36fedec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313331712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2313331712
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3842896650
Short name T849
Test name
Test status
Simulation time 60287053 ps
CPU time 2.18 seconds
Started Mar 31 03:56:00 PM PDT 24
Finished Mar 31 03:56:02 PM PDT 24
Peak memory 209532 kb
Host smart-7414c6eb-c8c0-4f1d-9e7c-7728d6a03650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842896650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3842896650
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3449431187
Short name T520
Test name
Test status
Simulation time 24381603 ps
CPU time 0.91 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:03 PM PDT 24
Peak memory 206356 kb
Host smart-80806cec-970d-447a-92f1-43fb04f1dbb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449431187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3449431187
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1827937836
Short name T421
Test name
Test status
Simulation time 67774285 ps
CPU time 4.97 seconds
Started Mar 31 03:55:06 PM PDT 24
Finished Mar 31 03:55:11 PM PDT 24
Peak memory 215624 kb
Host smart-3f3007d1-3713-406b-98dd-2fcfe4a90b86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827937836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1827937836
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.598055635
Short name T532
Test name
Test status
Simulation time 2951661555 ps
CPU time 17.07 seconds
Started Mar 31 03:54:58 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 208828 kb
Host smart-31206364-0104-470a-9ff5-5f1639179a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598055635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.598055635
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3855260887
Short name T292
Test name
Test status
Simulation time 195656335 ps
CPU time 6 seconds
Started Mar 31 03:55:27 PM PDT 24
Finished Mar 31 03:55:33 PM PDT 24
Peak memory 209752 kb
Host smart-ec0addc1-18d6-4edd-b9fe-70141278a4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855260887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3855260887
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.241722938
Short name T609
Test name
Test status
Simulation time 194427562 ps
CPU time 4.27 seconds
Started Mar 31 03:54:56 PM PDT 24
Finished Mar 31 03:55:01 PM PDT 24
Peak memory 220596 kb
Host smart-9f5a990b-5571-4163-ba9e-b0f49772727b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241722938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.241722938
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2033861116
Short name T348
Test name
Test status
Simulation time 65611103 ps
CPU time 4.25 seconds
Started Mar 31 03:55:08 PM PDT 24
Finished Mar 31 03:55:13 PM PDT 24
Peak memory 218640 kb
Host smart-5a11059b-5ef9-42fd-9eec-7b80e5e91ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033861116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2033861116
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.839475564
Short name T848
Test name
Test status
Simulation time 448032345 ps
CPU time 4.07 seconds
Started Mar 31 03:54:54 PM PDT 24
Finished Mar 31 03:54:58 PM PDT 24
Peak memory 208588 kb
Host smart-748baf59-cba4-4e1b-b730-94fe26a6335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839475564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.839475564
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2742645156
Short name T378
Test name
Test status
Simulation time 71872533 ps
CPU time 3.49 seconds
Started Mar 31 03:55:08 PM PDT 24
Finished Mar 31 03:55:12 PM PDT 24
Peak memory 209064 kb
Host smart-63dd8163-c097-46ee-bf07-44ce294eb36d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742645156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2742645156
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3788999505
Short name T115
Test name
Test status
Simulation time 2610786212 ps
CPU time 29.18 seconds
Started Mar 31 03:55:06 PM PDT 24
Finished Mar 31 03:55:35 PM PDT 24
Peak memory 208440 kb
Host smart-36da6f3a-4852-4804-996b-c52309654060
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788999505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3788999505
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2720319050
Short name T826
Test name
Test status
Simulation time 125722754 ps
CPU time 3.32 seconds
Started Mar 31 03:55:06 PM PDT 24
Finished Mar 31 03:55:09 PM PDT 24
Peak memory 209268 kb
Host smart-04670315-fc65-4fc0-8bd1-4c6646efa359
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720319050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2720319050
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2065649359
Short name T838
Test name
Test status
Simulation time 365533035 ps
CPU time 4.21 seconds
Started Mar 31 03:55:12 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 210196 kb
Host smart-a5c17df6-790d-463c-b767-bfabeddfa845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065649359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2065649359
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.178321174
Short name T818
Test name
Test status
Simulation time 3652413276 ps
CPU time 22.85 seconds
Started Mar 31 03:54:56 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 208756 kb
Host smart-936acab9-b391-46aa-b3df-4eca368f9319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178321174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.178321174
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1816057755
Short name T324
Test name
Test status
Simulation time 753510999 ps
CPU time 18.56 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:55:35 PM PDT 24
Peak memory 216240 kb
Host smart-45c3b8b4-3343-4470-9511-55dbbd79d99f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816057755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1816057755
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1930024286
Short name T180
Test name
Test status
Simulation time 917581780 ps
CPU time 9.2 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:18 PM PDT 24
Peak memory 222952 kb
Host smart-70abc50d-7a74-41aa-945c-5ca869ec9846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930024286 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1930024286
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2016435292
Short name T684
Test name
Test status
Simulation time 229891950 ps
CPU time 8.53 seconds
Started Mar 31 03:55:00 PM PDT 24
Finished Mar 31 03:55:09 PM PDT 24
Peak memory 208840 kb
Host smart-f143e3ad-b896-47ef-b015-c4399b374976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016435292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2016435292
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1237326451
Short name T643
Test name
Test status
Simulation time 11935432 ps
CPU time 0.83 seconds
Started Mar 31 03:55:04 PM PDT 24
Finished Mar 31 03:55:05 PM PDT 24
Peak memory 206296 kb
Host smart-4362ac11-d350-4418-8074-b3e06adb534a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237326451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1237326451
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.544320098
Short name T663
Test name
Test status
Simulation time 786948745 ps
CPU time 8.69 seconds
Started Mar 31 03:56:20 PM PDT 24
Finished Mar 31 03:56:29 PM PDT 24
Peak memory 218516 kb
Host smart-c070a34e-40c0-44a1-8590-680838a07ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544320098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.544320098
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1994740232
Short name T606
Test name
Test status
Simulation time 26095014 ps
CPU time 1.54 seconds
Started Mar 31 03:55:10 PM PDT 24
Finished Mar 31 03:55:12 PM PDT 24
Peak memory 207768 kb
Host smart-2951e686-435d-4098-b975-fe5cdbd93c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994740232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1994740232
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1137358000
Short name T832
Test name
Test status
Simulation time 336674916 ps
CPU time 6.05 seconds
Started Mar 31 03:54:58 PM PDT 24
Finished Mar 31 03:55:04 PM PDT 24
Peak memory 208080 kb
Host smart-5b9ec000-34ed-4b93-b102-9f27d7923692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137358000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1137358000
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3178085884
Short name T248
Test name
Test status
Simulation time 1378752419 ps
CPU time 5.37 seconds
Started Mar 31 03:54:50 PM PDT 24
Finished Mar 31 03:54:55 PM PDT 24
Peak memory 222852 kb
Host smart-18e465fe-f778-466d-aec1-00698d83439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178085884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3178085884
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2247617399
Short name T411
Test name
Test status
Simulation time 109956034 ps
CPU time 3.52 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 217216 kb
Host smart-225cf3d2-dc1e-432d-b181-f8c76154922a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247617399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2247617399
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2122305328
Short name T301
Test name
Test status
Simulation time 198734801 ps
CPU time 5.21 seconds
Started Mar 31 03:55:05 PM PDT 24
Finished Mar 31 03:55:11 PM PDT 24
Peak memory 207660 kb
Host smart-4781b2f8-ca4e-4774-8f01-55164c7df7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122305328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2122305328
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.523140024
Short name T747
Test name
Test status
Simulation time 49580249 ps
CPU time 2.74 seconds
Started Mar 31 03:54:57 PM PDT 24
Finished Mar 31 03:55:00 PM PDT 24
Peak memory 207192 kb
Host smart-498faea1-d7b1-4acc-902e-f29f5949dafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523140024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.523140024
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3729285053
Short name T882
Test name
Test status
Simulation time 251603968 ps
CPU time 4.31 seconds
Started Mar 31 03:55:04 PM PDT 24
Finished Mar 31 03:55:08 PM PDT 24
Peak memory 208820 kb
Host smart-b5dd7f32-c08f-4b4d-b5f8-ad2f78430a20
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729285053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3729285053
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3235572175
Short name T502
Test name
Test status
Simulation time 48062950 ps
CPU time 2.61 seconds
Started Mar 31 03:54:57 PM PDT 24
Finished Mar 31 03:55:00 PM PDT 24
Peak memory 209080 kb
Host smart-dd85b89f-9df2-4687-97d6-afc3b1f2e8b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235572175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3235572175
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.925156341
Short name T866
Test name
Test status
Simulation time 274091167 ps
CPU time 3.53 seconds
Started Mar 31 03:55:04 PM PDT 24
Finished Mar 31 03:55:08 PM PDT 24
Peak memory 208764 kb
Host smart-ad0191d4-11b3-4ebd-aa0c-68e7f324b84e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925156341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.925156341
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2355274868
Short name T627
Test name
Test status
Simulation time 794830055 ps
CPU time 2.97 seconds
Started Mar 31 03:54:58 PM PDT 24
Finished Mar 31 03:55:01 PM PDT 24
Peak memory 210084 kb
Host smart-4cee2b2c-9fc9-40b8-ab1f-392bdb4ca303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355274868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2355274868
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1781768471
Short name T542
Test name
Test status
Simulation time 232394570 ps
CPU time 2.84 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:04 PM PDT 24
Peak memory 208776 kb
Host smart-ab3967c4-f4f3-43f5-8893-a9ead1897af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781768471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1781768471
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2786226947
Short name T80
Test name
Test status
Simulation time 2481328038 ps
CPU time 29.7 seconds
Started Mar 31 03:55:02 PM PDT 24
Finished Mar 31 03:55:32 PM PDT 24
Peak memory 217076 kb
Host smart-e75e63e7-1053-4d3e-8fc8-af4a3027fb54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786226947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2786226947
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1415902864
Short name T739
Test name
Test status
Simulation time 51186334 ps
CPU time 2.32 seconds
Started Mar 31 03:55:08 PM PDT 24
Finished Mar 31 03:55:10 PM PDT 24
Peak memory 207980 kb
Host smart-7bf02eda-be79-4ae2-b803-9265994e5ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415902864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1415902864
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2101610014
Short name T391
Test name
Test status
Simulation time 206144305 ps
CPU time 2.46 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:03 PM PDT 24
Peak memory 210656 kb
Host smart-3b4df397-6efe-404b-965b-84962a9b5ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101610014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2101610014
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1388528412
Short name T437
Test name
Test status
Simulation time 10267036 ps
CPU time 0.78 seconds
Started Mar 31 03:55:05 PM PDT 24
Finished Mar 31 03:55:06 PM PDT 24
Peak memory 206228 kb
Host smart-8280b913-a5a2-4a54-8170-8065432acaa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388528412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1388528412
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3161198706
Short name T424
Test name
Test status
Simulation time 773249457 ps
CPU time 7.16 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 215032 kb
Host smart-f050d9cd-d203-404e-adae-d6e6c52d49cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161198706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3161198706
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2172939777
Short name T534
Test name
Test status
Simulation time 52999268 ps
CPU time 1.84 seconds
Started Mar 31 03:55:20 PM PDT 24
Finished Mar 31 03:55:22 PM PDT 24
Peak memory 208020 kb
Host smart-7ebd3f00-b023-4e3d-b1e0-60c5c5ce6d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172939777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2172939777
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2178692838
Short name T488
Test name
Test status
Simulation time 204437010 ps
CPU time 5.03 seconds
Started Mar 31 03:55:03 PM PDT 24
Finished Mar 31 03:55:08 PM PDT 24
Peak memory 209292 kb
Host smart-a4e87484-dc91-4ea5-b5a4-ffa2c1faf5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178692838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2178692838
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2075446594
Short name T309
Test name
Test status
Simulation time 239311789 ps
CPU time 4.03 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:05 PM PDT 24
Peak memory 211044 kb
Host smart-f3920c35-dc68-4135-b287-fe76611c1eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075446594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2075446594
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.645404425
Short name T548
Test name
Test status
Simulation time 107277029 ps
CPU time 1.76 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:03 PM PDT 24
Peak memory 220132 kb
Host smart-b623e8b2-d756-449b-ae33-fed2e2d6dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645404425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.645404425
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2827607356
Short name T35
Test name
Test status
Simulation time 116652221 ps
CPU time 4.77 seconds
Started Mar 31 03:54:58 PM PDT 24
Finished Mar 31 03:55:03 PM PDT 24
Peak memory 209004 kb
Host smart-2bb7e37d-e9dd-43f7-ae05-fc778f68a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827607356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2827607356
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1858388051
Short name T484
Test name
Test status
Simulation time 64446615 ps
CPU time 2.85 seconds
Started Mar 31 03:56:17 PM PDT 24
Finished Mar 31 03:56:20 PM PDT 24
Peak memory 207264 kb
Host smart-0cc9b28b-c0d0-4604-8fe5-6aa4dc5768a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858388051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1858388051
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1698394988
Short name T361
Test name
Test status
Simulation time 134728203 ps
CPU time 3.24 seconds
Started Mar 31 03:56:20 PM PDT 24
Finished Mar 31 03:56:24 PM PDT 24
Peak memory 209228 kb
Host smart-20ea7758-aa80-4c56-a9cc-9afbec79eb49
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698394988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1698394988
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.781103837
Short name T501
Test name
Test status
Simulation time 25138587 ps
CPU time 2.09 seconds
Started Mar 31 03:55:11 PM PDT 24
Finished Mar 31 03:55:13 PM PDT 24
Peak memory 209080 kb
Host smart-aeac351b-dba2-49c0-9789-232fb48dbf18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781103837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.781103837
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2096885904
Short name T830
Test name
Test status
Simulation time 11302899298 ps
CPU time 27.49 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:28 PM PDT 24
Peak memory 209480 kb
Host smart-848bde80-6f25-4876-8740-c8293447acea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096885904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2096885904
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.658563366
Short name T197
Test name
Test status
Simulation time 62660240 ps
CPU time 2 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:04 PM PDT 24
Peak memory 215932 kb
Host smart-94543872-3f55-43a0-8e6b-df3abb6c954a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658563366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.658563366
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.685110731
Short name T670
Test name
Test status
Simulation time 467869115 ps
CPU time 7.08 seconds
Started Mar 31 03:56:20 PM PDT 24
Finished Mar 31 03:56:28 PM PDT 24
Peak memory 206876 kb
Host smart-b6644672-c746-4c0d-b7ee-dcb3eb488f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685110731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.685110731
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.144991467
Short name T127
Test name
Test status
Simulation time 225953824 ps
CPU time 11.55 seconds
Started Mar 31 03:55:11 PM PDT 24
Finished Mar 31 03:55:23 PM PDT 24
Peak memory 222996 kb
Host smart-8efb162d-261a-4e78-aada-1d5f69f928f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144991467 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.144991467
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1262525337
Short name T649
Test name
Test status
Simulation time 399116823 ps
CPU time 4.22 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:42 PM PDT 24
Peak memory 207804 kb
Host smart-689c2ba6-c3dd-4146-bd89-7a3741015775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262525337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1262525337
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3092714479
Short name T65
Test name
Test status
Simulation time 73334114 ps
CPU time 2.41 seconds
Started Mar 31 03:55:23 PM PDT 24
Finished Mar 31 03:55:26 PM PDT 24
Peak memory 210540 kb
Host smart-ab9ab173-4f77-4468-8a32-1f542decc07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092714479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3092714479
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3364374148
Short name T719
Test name
Test status
Simulation time 101250495 ps
CPU time 0.93 seconds
Started Mar 31 03:55:02 PM PDT 24
Finished Mar 31 03:55:03 PM PDT 24
Peak memory 206432 kb
Host smart-14c2cf2f-4afe-44cd-a389-4f4a4980c0e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364374148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3364374148
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3662855799
Short name T608
Test name
Test status
Simulation time 514322083 ps
CPU time 4.54 seconds
Started Mar 31 03:55:01 PM PDT 24
Finished Mar 31 03:55:06 PM PDT 24
Peak memory 218464 kb
Host smart-ef3277f4-abfd-4c64-a9dd-b88ccebf2143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662855799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3662855799
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.347839622
Short name T318
Test name
Test status
Simulation time 328969503 ps
CPU time 6.46 seconds
Started Mar 31 03:54:54 PM PDT 24
Finished Mar 31 03:55:01 PM PDT 24
Peak memory 214636 kb
Host smart-43c26a6e-b50e-4ae8-8b78-72c9dd84a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347839622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.347839622
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.777536316
Short name T616
Test name
Test status
Simulation time 53166940 ps
CPU time 2.47 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:11 PM PDT 24
Peak memory 222780 kb
Host smart-e8452833-d596-4aee-be2c-5dde6d5c0ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777536316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.777536316
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4158049881
Short name T265
Test name
Test status
Simulation time 112699728 ps
CPU time 5.24 seconds
Started Mar 31 03:55:07 PM PDT 24
Finished Mar 31 03:55:12 PM PDT 24
Peak memory 218656 kb
Host smart-ddeb7395-35bd-45d6-b8b5-cf480fb12f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158049881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4158049881
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.4199029922
Short name T896
Test name
Test status
Simulation time 159984614 ps
CPU time 3.13 seconds
Started Mar 31 03:55:11 PM PDT 24
Finished Mar 31 03:55:15 PM PDT 24
Peak memory 207080 kb
Host smart-da900ff8-1eb5-41fe-be20-e9405ae19244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199029922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.4199029922
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1570317106
Short name T874
Test name
Test status
Simulation time 32735423 ps
CPU time 2.28 seconds
Started Mar 31 03:55:08 PM PDT 24
Finished Mar 31 03:55:11 PM PDT 24
Peak memory 207144 kb
Host smart-368a8f62-9307-4e4e-93f0-9f20c86e5a41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570317106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1570317106
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3853761961
Short name T544
Test name
Test status
Simulation time 131565002 ps
CPU time 4.24 seconds
Started Mar 31 03:55:04 PM PDT 24
Finished Mar 31 03:55:08 PM PDT 24
Peak memory 208288 kb
Host smart-37dcc9ec-bf5a-4941-90f9-47d96bc9207e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853761961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3853761961
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3083046132
Short name T569
Test name
Test status
Simulation time 312603517 ps
CPU time 7.76 seconds
Started Mar 31 03:54:55 PM PDT 24
Finished Mar 31 03:55:03 PM PDT 24
Peak memory 208776 kb
Host smart-369336a2-0f89-46ee-b287-ffbed6ec1db8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083046132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3083046132
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.873262026
Short name T383
Test name
Test status
Simulation time 248842672 ps
CPU time 2.89 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:12 PM PDT 24
Peak memory 208024 kb
Host smart-84d31c07-4d6d-4070-aa22-657d0bb53137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873262026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.873262026
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.549081709
Short name T408
Test name
Test status
Simulation time 2990117188 ps
CPU time 19.45 seconds
Started Mar 31 03:55:12 PM PDT 24
Finished Mar 31 03:55:32 PM PDT 24
Peak memory 207892 kb
Host smart-d2e1d680-b1af-4abc-8485-f3e7797db3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549081709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.549081709
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1543750384
Short name T723
Test name
Test status
Simulation time 19400368946 ps
CPU time 388.32 seconds
Started Mar 31 03:55:04 PM PDT 24
Finished Mar 31 04:01:33 PM PDT 24
Peak memory 224960 kb
Host smart-eb9a7ac7-7a18-4d2b-83a5-355285afe056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543750384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1543750384
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1894673585
Short name T222
Test name
Test status
Simulation time 3450578373 ps
CPU time 12.6 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:22 PM PDT 24
Peak memory 223040 kb
Host smart-dc6d54dc-e6ee-4993-82b5-08064b7ce00a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894673585 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1894673585
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4146682118
Short name T673
Test name
Test status
Simulation time 59487418 ps
CPU time 3.24 seconds
Started Mar 31 03:55:05 PM PDT 24
Finished Mar 31 03:55:08 PM PDT 24
Peak memory 207168 kb
Host smart-a12975ec-9465-4c91-9d41-d6b2fb53c902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146682118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4146682118
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1623590681
Short name T191
Test name
Test status
Simulation time 554146582 ps
CPU time 3.74 seconds
Started Mar 31 03:55:18 PM PDT 24
Finished Mar 31 03:55:22 PM PDT 24
Peak memory 210580 kb
Host smart-57a7cc36-1186-412b-8524-45b1ab5f2347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623590681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1623590681
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.169998668
Short name T652
Test name
Test status
Simulation time 34951648 ps
CPU time 1.05 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:11 PM PDT 24
Peak memory 206476 kb
Host smart-2be6e8de-d834-4201-bd46-0b0e4131bf15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169998668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.169998668
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2862720185
Short name T20
Test name
Test status
Simulation time 54905345 ps
CPU time 2.67 seconds
Started Mar 31 03:55:10 PM PDT 24
Finished Mar 31 03:55:13 PM PDT 24
Peak memory 214936 kb
Host smart-a5adc1f4-f28d-4b1c-9a66-152ba3b8ee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862720185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2862720185
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3449005832
Short name T320
Test name
Test status
Simulation time 618281292 ps
CPU time 3.82 seconds
Started Mar 31 03:55:10 PM PDT 24
Finished Mar 31 03:55:14 PM PDT 24
Peak memory 219016 kb
Host smart-bfe87e96-f4c2-4721-b048-15315041d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449005832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3449005832
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1588829377
Short name T475
Test name
Test status
Simulation time 117191212 ps
CPU time 5.41 seconds
Started Mar 31 03:55:08 PM PDT 24
Finished Mar 31 03:55:14 PM PDT 24
Peak memory 209780 kb
Host smart-057419a4-da28-4a48-92b2-bfe4d26e5722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588829377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1588829377
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2251393081
Short name T290
Test name
Test status
Simulation time 270631739 ps
CPU time 7.24 seconds
Started Mar 31 03:55:05 PM PDT 24
Finished Mar 31 03:55:12 PM PDT 24
Peak memory 210184 kb
Host smart-0fdb3628-0179-4afd-bb9c-d13015c8615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251393081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2251393081
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2829643613
Short name T769
Test name
Test status
Simulation time 218262204 ps
CPU time 3.35 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 220524 kb
Host smart-e4446e82-86c1-4e9d-a561-5148f1c470f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829643613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2829643613
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3011822740
Short name T381
Test name
Test status
Simulation time 3338102535 ps
CPU time 23.87 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:33 PM PDT 24
Peak memory 210032 kb
Host smart-c13e1f28-de40-4df2-adff-c88f28a1860e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011822740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3011822740
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2122747216
Short name T312
Test name
Test status
Simulation time 76599673 ps
CPU time 3.87 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:55:22 PM PDT 24
Peak memory 209024 kb
Host smart-96045778-89fa-4d99-b746-64bff356ca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122747216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2122747216
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3157191004
Short name T773
Test name
Test status
Simulation time 66311748 ps
CPU time 3.1 seconds
Started Mar 31 03:55:05 PM PDT 24
Finished Mar 31 03:55:08 PM PDT 24
Peak memory 208860 kb
Host smart-1b3990d6-14a2-47ff-81d4-45cabab1cd02
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157191004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3157191004
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3399762738
Short name T888
Test name
Test status
Simulation time 104590373 ps
CPU time 4.01 seconds
Started Mar 31 03:55:10 PM PDT 24
Finished Mar 31 03:55:15 PM PDT 24
Peak memory 208604 kb
Host smart-29b45ade-cf00-4ecb-9047-4f6937b799f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399762738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3399762738
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.846857587
Short name T477
Test name
Test status
Simulation time 236616585 ps
CPU time 4.37 seconds
Started Mar 31 03:55:07 PM PDT 24
Finished Mar 31 03:55:11 PM PDT 24
Peak memory 208680 kb
Host smart-d45ff099-9d75-4054-bb52-d4c83bea1a1c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846857587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.846857587
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.993800271
Short name T508
Test name
Test status
Simulation time 76435036 ps
CPU time 3.31 seconds
Started Mar 31 03:55:07 PM PDT 24
Finished Mar 31 03:55:10 PM PDT 24
Peak memory 208288 kb
Host smart-ae1f1f7d-6b8e-45b7-a87c-643a255495ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993800271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.993800271
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2274258325
Short name T674
Test name
Test status
Simulation time 75874851 ps
CPU time 1.79 seconds
Started Mar 31 03:55:05 PM PDT 24
Finished Mar 31 03:55:07 PM PDT 24
Peak memory 207200 kb
Host smart-1f8d44cd-6c91-4380-8084-9ed98d7dbe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274258325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2274258325
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2546563482
Short name T647
Test name
Test status
Simulation time 189033949 ps
CPU time 6.01 seconds
Started Mar 31 03:55:09 PM PDT 24
Finished Mar 31 03:55:25 PM PDT 24
Peak memory 207676 kb
Host smart-b83cf368-67e1-4a1f-95b3-beadf11d3d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546563482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2546563482
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3037665315
Short name T473
Test name
Test status
Simulation time 67697958 ps
CPU time 1.03 seconds
Started Mar 31 03:55:30 PM PDT 24
Finished Mar 31 03:55:31 PM PDT 24
Peak memory 206308 kb
Host smart-7e0639fa-3384-460b-a8c2-14856f8c386e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037665315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3037665315
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3888915588
Short name T280
Test name
Test status
Simulation time 197579849 ps
CPU time 3.63 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 214812 kb
Host smart-3aac3b70-de46-4125-b962-7d7d756bd3eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888915588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3888915588
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.45570563
Short name T227
Test name
Test status
Simulation time 822619675 ps
CPU time 17.76 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:33 PM PDT 24
Peak memory 220928 kb
Host smart-e9b8a2d1-a6c4-4965-912e-b1d4584f1d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45570563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.45570563
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1230680852
Short name T79
Test name
Test status
Simulation time 85612517 ps
CPU time 2.82 seconds
Started Mar 31 03:55:15 PM PDT 24
Finished Mar 31 03:55:18 PM PDT 24
Peak memory 210164 kb
Host smart-edcabceb-fabb-4da2-a298-ab96f465f155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230680852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1230680852
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1456286163
Short name T858
Test name
Test status
Simulation time 9033096817 ps
CPU time 83.58 seconds
Started Mar 31 03:55:10 PM PDT 24
Finished Mar 31 03:56:34 PM PDT 24
Peak memory 214784 kb
Host smart-7c34fca7-7eb4-4a21-a74b-d0baf1963a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456286163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1456286163
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2610158385
Short name T852
Test name
Test status
Simulation time 169617128 ps
CPU time 3.23 seconds
Started Mar 31 03:55:06 PM PDT 24
Finished Mar 31 03:55:10 PM PDT 24
Peak memory 214700 kb
Host smart-a0b2326d-66f5-495e-98d0-62723a7b943e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610158385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2610158385
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3468046726
Short name T409
Test name
Test status
Simulation time 196338432 ps
CPU time 3.46 seconds
Started Mar 31 03:55:12 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 208444 kb
Host smart-053a2371-761f-410f-a693-5970b066a7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468046726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3468046726
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.363828601
Short name T519
Test name
Test status
Simulation time 58551746 ps
CPU time 2.4 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 208788 kb
Host smart-037dd349-6ea1-43bd-88b7-57105cf32016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363828601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.363828601
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2913072429
Short name T564
Test name
Test status
Simulation time 171532627 ps
CPU time 6.32 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:20 PM PDT 24
Peak memory 209440 kb
Host smart-8aea9299-88e6-4cad-8011-2ff9b0585a16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913072429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2913072429
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3595659175
Short name T844
Test name
Test status
Simulation time 653432799 ps
CPU time 3 seconds
Started Mar 31 03:55:29 PM PDT 24
Finished Mar 31 03:55:32 PM PDT 24
Peak memory 209008 kb
Host smart-64aa5b36-51f1-4bec-ae66-d3c5ea791961
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595659175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3595659175
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3780879095
Short name T129
Test name
Test status
Simulation time 288448726 ps
CPU time 7.7 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 208896 kb
Host smart-26c10dc6-1a91-4cf9-955b-ba5eca5de700
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780879095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3780879095
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2802971529
Short name T557
Test name
Test status
Simulation time 227271311 ps
CPU time 3.46 seconds
Started Mar 31 03:55:15 PM PDT 24
Finished Mar 31 03:55:18 PM PDT 24
Peak memory 214508 kb
Host smart-03581330-4a3b-4fbc-9bec-a383e634c072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802971529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2802971529
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2686544358
Short name T202
Test name
Test status
Simulation time 21380206 ps
CPU time 1.81 seconds
Started Mar 31 03:55:11 PM PDT 24
Finished Mar 31 03:55:13 PM PDT 24
Peak memory 207016 kb
Host smart-d27a4c96-9aa3-4ea2-9dd0-bdd27784b3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686544358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2686544358
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2281191806
Short name T139
Test name
Test status
Simulation time 4005724422 ps
CPU time 27.05 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:41 PM PDT 24
Peak memory 215364 kb
Host smart-006ccd21-a04d-4ce5-8c24-8d1dede659ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281191806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2281191806
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2840070116
Short name T315
Test name
Test status
Simulation time 602272053 ps
CPU time 4.81 seconds
Started Mar 31 03:55:08 PM PDT 24
Finished Mar 31 03:55:13 PM PDT 24
Peak memory 210244 kb
Host smart-f8f223d7-1b50-4b4b-910a-0d5c4ed0b8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840070116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2840070116
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3950192393
Short name T668
Test name
Test status
Simulation time 133701320 ps
CPU time 2.93 seconds
Started Mar 31 03:55:08 PM PDT 24
Finished Mar 31 03:55:11 PM PDT 24
Peak memory 210744 kb
Host smart-6859cfc7-d59e-408c-969b-4fa2af704af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950192393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3950192393
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.156182187
Short name T782
Test name
Test status
Simulation time 42544712 ps
CPU time 0.85 seconds
Started Mar 31 03:55:30 PM PDT 24
Finished Mar 31 03:55:31 PM PDT 24
Peak memory 206240 kb
Host smart-0afbba81-d13e-4bfc-bb01-5e6ac745952e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156182187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.156182187
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1669627252
Short name T370
Test name
Test status
Simulation time 802436108 ps
CPU time 4.1 seconds
Started Mar 31 03:55:11 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 214716 kb
Host smart-35922af0-c265-4cc9-bc85-64c72aff55d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669627252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1669627252
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.99222282
Short name T462
Test name
Test status
Simulation time 92154885 ps
CPU time 1.35 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 208152 kb
Host smart-c5ca7c40-8517-49d9-a8a0-6bea86a5866d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99222282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.99222282
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1908511288
Short name T275
Test name
Test status
Simulation time 32292861 ps
CPU time 2.41 seconds
Started Mar 31 03:55:32 PM PDT 24
Finished Mar 31 03:55:35 PM PDT 24
Peak memory 209180 kb
Host smart-e369821a-9109-47cd-b024-f21a83f6656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908511288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1908511288
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.610433570
Short name T288
Test name
Test status
Simulation time 95119248 ps
CPU time 3.41 seconds
Started Mar 31 03:55:18 PM PDT 24
Finished Mar 31 03:55:22 PM PDT 24
Peak memory 211744 kb
Host smart-c8c0e28e-6ade-4f84-9cd8-b1437d9d3c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610433570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.610433570
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2594166693
Short name T190
Test name
Test status
Simulation time 51725931 ps
CPU time 2.81 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 220568 kb
Host smart-998eb854-2301-4127-aef2-55e92dc05de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594166693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2594166693
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.717519438
Short name T505
Test name
Test status
Simulation time 753278782 ps
CPU time 23.16 seconds
Started Mar 31 03:55:15 PM PDT 24
Finished Mar 31 03:55:38 PM PDT 24
Peak memory 214676 kb
Host smart-99f90bf9-3d0a-4f17-a052-e7869c300737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717519438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.717519438
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1390332143
Short name T304
Test name
Test status
Simulation time 264701491 ps
CPU time 3.48 seconds
Started Mar 31 03:55:12 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 208732 kb
Host smart-c970144d-60cb-46f5-8c05-653c98170243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390332143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1390332143
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1002253786
Short name T633
Test name
Test status
Simulation time 73965861 ps
CPU time 1.84 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:18 PM PDT 24
Peak memory 207168 kb
Host smart-aeb0995a-b873-4bb1-935e-a3c11955f982
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002253786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1002253786
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.498447108
Short name T574
Test name
Test status
Simulation time 141362469 ps
CPU time 2.46 seconds
Started Mar 31 03:55:10 PM PDT 24
Finished Mar 31 03:55:13 PM PDT 24
Peak memory 207712 kb
Host smart-116c2615-db79-4f22-b1b9-a979153a0ff2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498447108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.498447108
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1886396557
Short name T106
Test name
Test status
Simulation time 91444329 ps
CPU time 4.05 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 209452 kb
Host smart-bdc55c60-d8b3-4774-ba7b-56b646d4446d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886396557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1886396557
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4242687161
Short name T613
Test name
Test status
Simulation time 531390161 ps
CPU time 4.71 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 218632 kb
Host smart-66447f9b-73b3-417f-b458-e603d7081882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242687161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4242687161
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1665049427
Short name T628
Test name
Test status
Simulation time 2359006973 ps
CPU time 22.18 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:39 PM PDT 24
Peak memory 208936 kb
Host smart-2ade2669-8037-4819-9e2e-6c19cb076f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665049427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1665049427
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2677653022
Short name T599
Test name
Test status
Simulation time 217877963 ps
CPU time 6.33 seconds
Started Mar 31 03:55:35 PM PDT 24
Finished Mar 31 03:55:41 PM PDT 24
Peak memory 209096 kb
Host smart-062d46a8-0b90-4b31-a7f1-372de223759d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677653022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2677653022
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.711048596
Short name T158
Test name
Test status
Simulation time 405287944 ps
CPU time 4.54 seconds
Started Mar 31 03:55:26 PM PDT 24
Finished Mar 31 03:55:31 PM PDT 24
Peak memory 211116 kb
Host smart-60bb9d07-b378-4694-be66-adbbc9edf900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711048596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.711048596
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.765994788
Short name T760
Test name
Test status
Simulation time 15128266 ps
CPU time 0.8 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:20 PM PDT 24
Peak memory 206300 kb
Host smart-e613306f-1144-434e-920c-1d600c3c1630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765994788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.765994788
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.404691034
Short name T715
Test name
Test status
Simulation time 63494553 ps
CPU time 2.69 seconds
Started Mar 31 03:54:17 PM PDT 24
Finished Mar 31 03:54:20 PM PDT 24
Peak memory 214724 kb
Host smart-b594c3fd-18ff-4941-a242-14f95163bc2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404691034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.404691034
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2315153315
Short name T781
Test name
Test status
Simulation time 1934164200 ps
CPU time 22.59 seconds
Started Mar 31 03:54:00 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 223144 kb
Host smart-395d5230-e798-4e31-b9b0-edbe93c4049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315153315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2315153315
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3769568003
Short name T865
Test name
Test status
Simulation time 235816042 ps
CPU time 3.22 seconds
Started Mar 31 03:54:09 PM PDT 24
Finished Mar 31 03:54:13 PM PDT 24
Peak memory 210060 kb
Host smart-64eb81c5-a2d9-4d95-9407-b3905bf3d125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769568003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3769568003
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4248003935
Short name T401
Test name
Test status
Simulation time 265528257 ps
CPU time 5.96 seconds
Started Mar 31 03:54:12 PM PDT 24
Finished Mar 31 03:54:18 PM PDT 24
Peak memory 214664 kb
Host smart-f5211af1-8725-46b2-8bc4-f9894b00e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248003935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4248003935
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3970990033
Short name T540
Test name
Test status
Simulation time 472382483 ps
CPU time 5.43 seconds
Started Mar 31 03:54:14 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 209840 kb
Host smart-01f6bc57-4fdd-4f1c-9476-e45b96f321b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970990033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3970990033
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2827995352
Short name T349
Test name
Test status
Simulation time 219881773 ps
CPU time 5.41 seconds
Started Mar 31 03:54:08 PM PDT 24
Finished Mar 31 03:54:14 PM PDT 24
Peak memory 208832 kb
Host smart-760aa9e5-305b-43b2-b097-778f8b516f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827995352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2827995352
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2210069933
Short name T11
Test name
Test status
Simulation time 553513645 ps
CPU time 16.88 seconds
Started Mar 31 03:54:04 PM PDT 24
Finished Mar 31 03:54:21 PM PDT 24
Peak memory 236440 kb
Host smart-b7522197-be11-4897-9963-d58e6969a01a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210069933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2210069933
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.596850437
Short name T905
Test name
Test status
Simulation time 8026248342 ps
CPU time 46.8 seconds
Started Mar 31 03:54:03 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 209288 kb
Host smart-34875ff0-cf24-4f4f-99e0-860adc639c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596850437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.596850437
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1034070136
Short name T589
Test name
Test status
Simulation time 657229309 ps
CPU time 5.37 seconds
Started Mar 31 03:54:07 PM PDT 24
Finished Mar 31 03:54:13 PM PDT 24
Peak memory 209020 kb
Host smart-cf61dd7d-b6af-4818-ab55-71fd0e8983d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034070136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1034070136
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1604231067
Short name T656
Test name
Test status
Simulation time 62861124 ps
CPU time 2.87 seconds
Started Mar 31 03:54:06 PM PDT 24
Finished Mar 31 03:54:09 PM PDT 24
Peak memory 206996 kb
Host smart-10ba2804-cbee-4287-8361-0771688ec288
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604231067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1604231067
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4159337127
Short name T448
Test name
Test status
Simulation time 1499722042 ps
CPU time 50.17 seconds
Started Mar 31 03:54:05 PM PDT 24
Finished Mar 31 03:54:56 PM PDT 24
Peak memory 208424 kb
Host smart-5f92fd4f-ca1b-40dc-b457-251ebfad948f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159337127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4159337127
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3551898615
Short name T755
Test name
Test status
Simulation time 262441902 ps
CPU time 2.6 seconds
Started Mar 31 03:54:10 PM PDT 24
Finished Mar 31 03:54:13 PM PDT 24
Peak memory 207816 kb
Host smart-2b0297bb-8701-4091-ba79-0af59d4d3e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551898615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3551898615
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.479603147
Short name T795
Test name
Test status
Simulation time 197350506 ps
CPU time 3.56 seconds
Started Mar 31 03:54:03 PM PDT 24
Finished Mar 31 03:54:08 PM PDT 24
Peak memory 208620 kb
Host smart-659410cd-c238-4adf-8c5b-db6b0938f2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479603147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.479603147
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2825143994
Short name T872
Test name
Test status
Simulation time 1199152546 ps
CPU time 14.2 seconds
Started Mar 31 03:54:07 PM PDT 24
Finished Mar 31 03:54:21 PM PDT 24
Peak memory 222924 kb
Host smart-fc076956-1218-48d6-8ed9-46455874387b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825143994 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2825143994
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3589542248
Short name T330
Test name
Test status
Simulation time 340181434 ps
CPU time 4.75 seconds
Started Mar 31 03:54:04 PM PDT 24
Finished Mar 31 03:54:09 PM PDT 24
Peak memory 214700 kb
Host smart-5933b9dc-736d-4d08-b9d7-e50e8b982fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589542248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3589542248
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1354002716
Short name T40
Test name
Test status
Simulation time 215839724 ps
CPU time 2.01 seconds
Started Mar 31 03:54:04 PM PDT 24
Finished Mar 31 03:54:07 PM PDT 24
Peak memory 210272 kb
Host smart-742c402a-7e14-413d-b81b-c859c835a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354002716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1354002716
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3381762036
Short name T446
Test name
Test status
Simulation time 11496567 ps
CPU time 0.69 seconds
Started Mar 31 03:55:26 PM PDT 24
Finished Mar 31 03:55:27 PM PDT 24
Peak memory 206240 kb
Host smart-6f364b75-5649-468d-8ad8-b6ec1f1e55d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381762036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3381762036
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3320147972
Short name T76
Test name
Test status
Simulation time 153756386 ps
CPU time 5.53 seconds
Started Mar 31 03:55:27 PM PDT 24
Finished Mar 31 03:55:33 PM PDT 24
Peak memory 208864 kb
Host smart-92fc2d55-4afc-478f-87b4-9a2f5fc87ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320147972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3320147972
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1255317662
Short name T513
Test name
Test status
Simulation time 527594990 ps
CPU time 9.8 seconds
Started Mar 31 03:55:22 PM PDT 24
Finished Mar 31 03:55:32 PM PDT 24
Peak memory 214644 kb
Host smart-225bdd11-bfba-4ba0-aa7e-3693129f0304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255317662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1255317662
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3039229465
Short name T250
Test name
Test status
Simulation time 183860224 ps
CPU time 5 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 210436 kb
Host smart-042c87df-5e06-4bc5-ade5-1eecf7af4296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039229465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3039229465
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1307120836
Short name T527
Test name
Test status
Simulation time 459123335 ps
CPU time 3.87 seconds
Started Mar 31 03:55:18 PM PDT 24
Finished Mar 31 03:55:22 PM PDT 24
Peak memory 214720 kb
Host smart-b0bb70f7-be3d-4d9d-b14f-f2ec7d790df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307120836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1307120836
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.581765170
Short name T876
Test name
Test status
Simulation time 514386410 ps
CPU time 4.71 seconds
Started Mar 31 03:55:26 PM PDT 24
Finished Mar 31 03:55:31 PM PDT 24
Peak memory 218728 kb
Host smart-95d86ccc-26b2-4390-a9e2-1abee5dbfbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581765170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.581765170
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2618013192
Short name T554
Test name
Test status
Simulation time 605524698 ps
CPU time 6.67 seconds
Started Mar 31 03:55:15 PM PDT 24
Finished Mar 31 03:55:22 PM PDT 24
Peak memory 209032 kb
Host smart-4b66a0bd-e9ba-48dc-bc4f-5559b750008d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618013192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2618013192
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3018669829
Short name T86
Test name
Test status
Simulation time 139848600 ps
CPU time 2.4 seconds
Started Mar 31 03:55:20 PM PDT 24
Finished Mar 31 03:55:22 PM PDT 24
Peak memory 207088 kb
Host smart-a8a003ac-3718-4a4f-b991-7343f6d0c65a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018669829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3018669829
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.785918191
Short name T765
Test name
Test status
Simulation time 146002325 ps
CPU time 3.71 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:37 PM PDT 24
Peak memory 208352 kb
Host smart-f9b4a0b7-b325-421d-aa14-127763230ab9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785918191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.785918191
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2240365819
Short name T567
Test name
Test status
Simulation time 484919863 ps
CPU time 6.55 seconds
Started Mar 31 03:55:10 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 208768 kb
Host smart-0ff73e93-ceb6-48ef-bd81-0eaaa4b36f42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240365819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2240365819
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1411197236
Short name T650
Test name
Test status
Simulation time 175880781 ps
CPU time 5.88 seconds
Started Mar 31 03:55:12 PM PDT 24
Finished Mar 31 03:55:18 PM PDT 24
Peak memory 214716 kb
Host smart-b299fe54-ff06-4113-ad29-3594ca93c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411197236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1411197236
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.74655440
Short name T444
Test name
Test status
Simulation time 1012461063 ps
CPU time 6.23 seconds
Started Mar 31 03:55:23 PM PDT 24
Finished Mar 31 03:55:29 PM PDT 24
Peak memory 207260 kb
Host smart-50a69299-9328-4de5-85fa-4bf8127f3ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74655440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.74655440
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1285710109
Short name T78
Test name
Test status
Simulation time 48918882020 ps
CPU time 311.63 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 04:00:26 PM PDT 24
Peak memory 219936 kb
Host smart-b674c618-6b71-4161-a677-56c4d838ac8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285710109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1285710109
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2240603277
Short name T179
Test name
Test status
Simulation time 1371893966 ps
CPU time 23.86 seconds
Started Mar 31 03:55:23 PM PDT 24
Finished Mar 31 03:55:47 PM PDT 24
Peak memory 222972 kb
Host smart-a7d54355-a324-465e-b4f3-9ee054ec98e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240603277 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2240603277
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3480697809
Short name T721
Test name
Test status
Simulation time 8711273058 ps
CPU time 92.37 seconds
Started Mar 31 03:55:20 PM PDT 24
Finished Mar 31 03:56:52 PM PDT 24
Peak memory 209672 kb
Host smart-bfce25e0-4921-4e04-b069-fac5f8ecdff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480697809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3480697809
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3923488797
Short name T492
Test name
Test status
Simulation time 657737512 ps
CPU time 17.94 seconds
Started Mar 31 03:55:29 PM PDT 24
Finished Mar 31 03:55:48 PM PDT 24
Peak memory 211284 kb
Host smart-5048b3f8-80f6-464c-a997-eff61e5af66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923488797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3923488797
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1142114793
Short name T862
Test name
Test status
Simulation time 20974415 ps
CPU time 0.81 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 206240 kb
Host smart-95134c1f-4fd4-4d70-a83c-575ac746b931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142114793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1142114793
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.429138752
Short name T429
Test name
Test status
Simulation time 4958566445 ps
CPU time 127.98 seconds
Started Mar 31 03:55:19 PM PDT 24
Finished Mar 31 03:57:27 PM PDT 24
Peak memory 214768 kb
Host smart-584b31cc-288b-4677-b2b3-6297bcc3f72c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429138752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.429138752
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.396299217
Short name T792
Test name
Test status
Simulation time 219562410 ps
CPU time 2.57 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 218584 kb
Host smart-e2c587eb-d8f1-468c-8e02-61be74ea782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396299217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.396299217
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.897697742
Short name T345
Test name
Test status
Simulation time 180414907 ps
CPU time 3.39 seconds
Started Mar 31 03:55:20 PM PDT 24
Finished Mar 31 03:55:24 PM PDT 24
Peak memory 209872 kb
Host smart-15878d54-da96-486f-891f-662bd93ef449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897697742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.897697742
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2928983947
Short name T212
Test name
Test status
Simulation time 425693000 ps
CPU time 5.17 seconds
Started Mar 31 03:57:36 PM PDT 24
Finished Mar 31 03:57:41 PM PDT 24
Peak memory 210840 kb
Host smart-e5043573-ea7b-4358-a044-313e81aa7eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928983947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2928983947
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2164429662
Short name T558
Test name
Test status
Simulation time 131934685 ps
CPU time 3.1 seconds
Started Mar 31 03:57:30 PM PDT 24
Finished Mar 31 03:57:33 PM PDT 24
Peak memory 219828 kb
Host smart-a7079c20-5b25-4224-8e20-6048cb82a3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164429662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2164429662
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1510621201
Short name T407
Test name
Test status
Simulation time 2770492816 ps
CPU time 29.43 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:43 PM PDT 24
Peak memory 220152 kb
Host smart-bec0a1ad-9364-45b1-a1a6-7c6d3811a604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510621201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1510621201
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2797869051
Short name T904
Test name
Test status
Simulation time 272708282 ps
CPU time 3.34 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:18 PM PDT 24
Peak memory 209160 kb
Host smart-6532e4f7-3c2c-4c9e-9460-4bd7c781e0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797869051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2797869051
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2291176201
Short name T809
Test name
Test status
Simulation time 216373263 ps
CPU time 6.78 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:23 PM PDT 24
Peak memory 208208 kb
Host smart-7553e153-1f83-4f42-ab11-b5cd2361a752
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291176201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2291176201
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2506748132
Short name T710
Test name
Test status
Simulation time 718234436 ps
CPU time 19.59 seconds
Started Mar 31 03:55:10 PM PDT 24
Finished Mar 31 03:55:30 PM PDT 24
Peak memory 209220 kb
Host smart-8e9ab4d4-57b9-4482-9595-127edeabddaa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506748132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2506748132
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2845377879
Short name T526
Test name
Test status
Simulation time 68241666 ps
CPU time 3.15 seconds
Started Mar 31 03:55:18 PM PDT 24
Finished Mar 31 03:55:22 PM PDT 24
Peak memory 208972 kb
Host smart-279dce4e-07a4-4359-938a-4906d6e439df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845377879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2845377879
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3100782045
Short name T479
Test name
Test status
Simulation time 402237994 ps
CPU time 3.44 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:18 PM PDT 24
Peak memory 210108 kb
Host smart-0b90cd0a-b896-4d12-9422-69e8c1cf211c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100782045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3100782045
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3450341948
Short name T487
Test name
Test status
Simulation time 246357896 ps
CPU time 5.99 seconds
Started Mar 31 03:55:23 PM PDT 24
Finished Mar 31 03:55:29 PM PDT 24
Peak memory 208784 kb
Host smart-db24b672-abb6-402f-95b5-4390edfc2b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450341948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3450341948
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1866206206
Short name T285
Test name
Test status
Simulation time 2056385679 ps
CPU time 15.15 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:32 PM PDT 24
Peak memory 221832 kb
Host smart-5e7e8229-7c3d-4945-919b-2228b4e5e83d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866206206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1866206206
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.416813772
Short name T229
Test name
Test status
Simulation time 247714800 ps
CPU time 7.94 seconds
Started Mar 31 03:55:19 PM PDT 24
Finished Mar 31 03:55:27 PM PDT 24
Peak memory 222948 kb
Host smart-a05238c7-1ba7-47c6-8da6-19b9b333415c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416813772 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.416813772
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3501536237
Short name T707
Test name
Test status
Simulation time 93257340 ps
CPU time 3.48 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 209892 kb
Host smart-5693f159-3b94-4bf4-9eeb-e2b51213a72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501536237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3501536237
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2039005311
Short name T126
Test name
Test status
Simulation time 88356677 ps
CPU time 1.55 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 209904 kb
Host smart-610b9215-1827-4b88-8fcb-ed0734fee08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039005311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2039005311
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3055702164
Short name T550
Test name
Test status
Simulation time 93340799 ps
CPU time 0.75 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 206340 kb
Host smart-8a1f241f-6cd8-40cc-b1ef-5c6c61eff29f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055702164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3055702164
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.421485329
Short name T791
Test name
Test status
Simulation time 134058001 ps
CPU time 4.01 seconds
Started Mar 31 03:56:20 PM PDT 24
Finished Mar 31 03:56:24 PM PDT 24
Peak memory 210020 kb
Host smart-8016d5c8-f07a-4e91-8d4a-555bed3bf9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421485329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.421485329
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.4294854905
Short name T254
Test name
Test status
Simulation time 1844262482 ps
CPU time 5.15 seconds
Started Mar 31 03:55:24 PM PDT 24
Finished Mar 31 03:55:30 PM PDT 24
Peak memory 209544 kb
Host smart-ff8f2adb-ef48-4448-bccd-a678257107a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294854905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.4294854905
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1350301247
Short name T801
Test name
Test status
Simulation time 1879081625 ps
CPU time 28.4 seconds
Started Mar 31 03:55:21 PM PDT 24
Finished Mar 31 03:55:50 PM PDT 24
Peak memory 214644 kb
Host smart-c84a8a35-1c1d-40a9-927a-1b3e736a5f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350301247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1350301247
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_random.3364329760
Short name T219
Test name
Test status
Simulation time 53011604 ps
CPU time 3.29 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:37 PM PDT 24
Peak memory 208428 kb
Host smart-84901004-edea-4692-8499-bd5db4019a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364329760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3364329760
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1902969529
Short name T843
Test name
Test status
Simulation time 120086158 ps
CPU time 2.95 seconds
Started Mar 31 03:55:21 PM PDT 24
Finished Mar 31 03:55:24 PM PDT 24
Peak memory 207180 kb
Host smart-c9be8e51-97f0-4d80-8583-76951b03392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902969529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1902969529
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2612591725
Short name T660
Test name
Test status
Simulation time 210313460 ps
CPU time 2.87 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 207160 kb
Host smart-88dceedd-d884-446d-bdc6-b9b2f4d9e747
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612591725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2612591725
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3899818820
Short name T629
Test name
Test status
Simulation time 189081635 ps
CPU time 2.77 seconds
Started Mar 31 03:55:14 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 207128 kb
Host smart-87dadbea-b0fc-4965-bb5d-14131c40e585
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899818820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3899818820
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.802518241
Short name T442
Test name
Test status
Simulation time 668246005 ps
CPU time 3.39 seconds
Started Mar 31 03:55:30 PM PDT 24
Finished Mar 31 03:55:34 PM PDT 24
Peak memory 207264 kb
Host smart-fae4588e-c579-4060-8bd4-07c2598691a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802518241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.802518241
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2838750311
Short name T328
Test name
Test status
Simulation time 959801846 ps
CPU time 12.21 seconds
Started Mar 31 03:55:42 PM PDT 24
Finished Mar 31 03:55:54 PM PDT 24
Peak memory 214716 kb
Host smart-215ec84b-76a6-40fc-a42d-ed178482ce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838750311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2838750311
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.618816995
Short name T204
Test name
Test status
Simulation time 918935799 ps
CPU time 6.48 seconds
Started Mar 31 03:55:21 PM PDT 24
Finished Mar 31 03:55:28 PM PDT 24
Peak memory 208552 kb
Host smart-1abbf9b4-02f0-49ca-918e-0596ee06eb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618816995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.618816995
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1801832551
Short name T607
Test name
Test status
Simulation time 76953889 ps
CPU time 2.56 seconds
Started Mar 31 03:56:33 PM PDT 24
Finished Mar 31 03:56:36 PM PDT 24
Peak memory 207972 kb
Host smart-a036c16f-8c70-4cac-b84a-4c7b8b5c783e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801832551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1801832551
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1353914098
Short name T273
Test name
Test status
Simulation time 228573397 ps
CPU time 8.65 seconds
Started Mar 31 03:55:15 PM PDT 24
Finished Mar 31 03:55:24 PM PDT 24
Peak memory 210036 kb
Host smart-63fc149f-8d4d-4d0f-9e29-646a7a70ca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353914098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1353914098
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2906760278
Short name T389
Test name
Test status
Simulation time 93870341 ps
CPU time 2.5 seconds
Started Mar 31 03:55:08 PM PDT 24
Finished Mar 31 03:55:10 PM PDT 24
Peak memory 210412 kb
Host smart-bf4a88fe-33d1-4a06-9540-eaab7b94086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906760278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2906760278
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1300778781
Short name T441
Test name
Test status
Simulation time 17885326 ps
CPU time 0.81 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 206332 kb
Host smart-3ac7776a-ae01-4102-90d5-d31e00e97c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300778781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1300778781
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.476208082
Short name T430
Test name
Test status
Simulation time 566197260 ps
CPU time 4.8 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 215608 kb
Host smart-cf381e58-c9e8-429d-889a-51de06e280a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476208082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.476208082
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3349690819
Short name T226
Test name
Test status
Simulation time 170665007 ps
CPU time 4.22 seconds
Started Mar 31 03:55:23 PM PDT 24
Finished Mar 31 03:55:27 PM PDT 24
Peak memory 216848 kb
Host smart-6315f76f-07ff-491e-a02c-86bd9850c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349690819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3349690819
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1790709490
Short name T687
Test name
Test status
Simulation time 56293260 ps
CPU time 2.06 seconds
Started Mar 31 03:55:19 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 207452 kb
Host smart-d57ee7b8-6a15-4263-bec9-70c83a65f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790709490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1790709490
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.599196943
Short name T36
Test name
Test status
Simulation time 1164027944 ps
CPU time 13.47 seconds
Started Mar 31 03:55:41 PM PDT 24
Finished Mar 31 03:55:55 PM PDT 24
Peak memory 211692 kb
Host smart-a4d45d8e-4e56-4409-a581-6b6c03220085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599196943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.599196943
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2048423601
Short name T272
Test name
Test status
Simulation time 37462493 ps
CPU time 2.85 seconds
Started Mar 31 03:55:32 PM PDT 24
Finished Mar 31 03:55:35 PM PDT 24
Peak memory 220724 kb
Host smart-9adad02d-93d9-4799-84fd-66d17be91998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048423601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2048423601
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1962252776
Short name T552
Test name
Test status
Simulation time 136492821 ps
CPU time 3.66 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 208692 kb
Host smart-1e361eb6-8a96-4aa0-82c7-b5c4de952474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962252776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1962252776
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3545521989
Short name T489
Test name
Test status
Simulation time 306183470 ps
CPU time 3.21 seconds
Started Mar 31 03:55:13 PM PDT 24
Finished Mar 31 03:55:16 PM PDT 24
Peak memory 207136 kb
Host smart-73510689-cfcd-4bca-802d-40be19ce9e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545521989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3545521989
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1827102897
Short name T892
Test name
Test status
Simulation time 410059737 ps
CPU time 4 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 207232 kb
Host smart-5eaf0427-7737-442f-bf04-8093839b55cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827102897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1827102897
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2486041136
Short name T88
Test name
Test status
Simulation time 158312462 ps
CPU time 3.11 seconds
Started Mar 31 03:55:22 PM PDT 24
Finished Mar 31 03:55:26 PM PDT 24
Peak memory 207884 kb
Host smart-77af70f4-b3ad-4dd8-a3b1-a51fbd8257e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486041136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2486041136
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1647780500
Short name T785
Test name
Test status
Simulation time 408936772 ps
CPU time 5.07 seconds
Started Mar 31 03:55:15 PM PDT 24
Finished Mar 31 03:55:20 PM PDT 24
Peak memory 208984 kb
Host smart-ccf0ab90-2af0-46c9-8235-bdb0307ce2d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647780500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1647780500
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3170367721
Short name T472
Test name
Test status
Simulation time 1086858986 ps
CPU time 13.23 seconds
Started Mar 31 03:55:30 PM PDT 24
Finished Mar 31 03:55:43 PM PDT 24
Peak memory 208232 kb
Host smart-30c7fa54-0150-4f97-8e0b-d88187fd2be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170367721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3170367721
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.872877286
Short name T350
Test name
Test status
Simulation time 4382885319 ps
CPU time 41.26 seconds
Started Mar 31 03:55:31 PM PDT 24
Finished Mar 31 03:56:13 PM PDT 24
Peak memory 223008 kb
Host smart-f38638bb-5bd4-470f-967d-c0f284bd6117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872877286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.872877286
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.904151564
Short name T644
Test name
Test status
Simulation time 425496314 ps
CPU time 17.46 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:33 PM PDT 24
Peak memory 223040 kb
Host smart-4d6f303c-80e6-4e8d-ab4f-d1eada4ddd1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904151564 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.904151564
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2530512839
Short name T357
Test name
Test status
Simulation time 1896425731 ps
CPU time 4.34 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 214680 kb
Host smart-fe576a01-da40-4ee9-9a64-f7ed9c8ee031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530512839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2530512839
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.4003165314
Short name T855
Test name
Test status
Simulation time 176590205 ps
CPU time 2.2 seconds
Started Mar 31 03:55:45 PM PDT 24
Finished Mar 31 03:55:48 PM PDT 24
Peak memory 210528 kb
Host smart-cb82b924-54af-47dc-99a5-dbbc34f990b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003165314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.4003165314
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2283133513
Short name T504
Test name
Test status
Simulation time 14188854 ps
CPU time 0.93 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:17 PM PDT 24
Peak memory 206496 kb
Host smart-4a9b4080-918e-4e1a-aa0f-54251dece5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283133513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2283133513
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.81046083
Short name T596
Test name
Test status
Simulation time 5899196394 ps
CPU time 56.9 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:56:15 PM PDT 24
Peak memory 214796 kb
Host smart-818f29e1-0bde-404c-9e3e-036a3242f96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81046083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.81046083
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_random.3511932315
Short name T105
Test name
Test status
Simulation time 424528363 ps
CPU time 8.64 seconds
Started Mar 31 03:55:48 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 214708 kb
Host smart-714edd59-624c-43e4-aa29-5cc27cd48c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511932315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3511932315
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3483027462
Short name T413
Test name
Test status
Simulation time 181681316 ps
CPU time 5.46 seconds
Started Mar 31 03:55:19 PM PDT 24
Finished Mar 31 03:55:25 PM PDT 24
Peak memory 208284 kb
Host smart-9706a5d1-c8c9-4894-b549-22433f190751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483027462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3483027462
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.607444279
Short name T450
Test name
Test status
Simulation time 63190916 ps
CPU time 3.29 seconds
Started Mar 31 03:55:24 PM PDT 24
Finished Mar 31 03:55:29 PM PDT 24
Peak memory 207196 kb
Host smart-7e610abb-d742-4e18-ace0-9102aaa3c4bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607444279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.607444279
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2193611117
Short name T623
Test name
Test status
Simulation time 2410068401 ps
CPU time 8.27 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:42 PM PDT 24
Peak memory 208556 kb
Host smart-46b90c0f-22d3-446c-aa3b-f421cd135c45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193611117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2193611117
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1225198790
Short name T636
Test name
Test status
Simulation time 198951625 ps
CPU time 5.57 seconds
Started Mar 31 03:55:24 PM PDT 24
Finished Mar 31 03:55:30 PM PDT 24
Peak memory 208168 kb
Host smart-5aaf9cd0-0e09-4ad6-bbc4-e3e7182a3598
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225198790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1225198790
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1331836154
Short name T279
Test name
Test status
Simulation time 213309835 ps
CPU time 1.69 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:55:18 PM PDT 24
Peak memory 214676 kb
Host smart-9ef456c1-087f-42bb-874c-cabd8de27ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331836154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1331836154
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3819214876
Short name T439
Test name
Test status
Simulation time 20829380 ps
CPU time 1.83 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:35 PM PDT 24
Peak memory 207196 kb
Host smart-018f5bb2-ebe1-4270-8447-7cb3351cdb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819214876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3819214876
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1476223294
Short name T255
Test name
Test status
Simulation time 102039433 ps
CPU time 5.1 seconds
Started Mar 31 03:55:36 PM PDT 24
Finished Mar 31 03:55:41 PM PDT 24
Peak memory 218744 kb
Host smart-51397351-8913-4a5f-97ac-ccf6398fab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476223294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1476223294
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1155731868
Short name T565
Test name
Test status
Simulation time 62254654 ps
CPU time 2.34 seconds
Started Mar 31 03:55:23 PM PDT 24
Finished Mar 31 03:55:26 PM PDT 24
Peak memory 210256 kb
Host smart-f5e29f6e-6705-49b6-bcb0-865ff8397051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155731868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1155731868
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3266954162
Short name T443
Test name
Test status
Simulation time 12133500 ps
CPU time 0.74 seconds
Started Mar 31 03:55:18 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 206360 kb
Host smart-03b193d1-849f-4ffd-bae6-b8ddd5c59e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266954162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3266954162
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.326595836
Short name T28
Test name
Test status
Simulation time 278913276 ps
CPU time 4.31 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:37 PM PDT 24
Peak memory 210100 kb
Host smart-4d197478-9568-4aad-a67b-bc38389f9b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326595836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.326595836
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3915870896
Short name T813
Test name
Test status
Simulation time 65991762 ps
CPU time 2.51 seconds
Started Mar 31 03:55:34 PM PDT 24
Finished Mar 31 03:55:37 PM PDT 24
Peak memory 207544 kb
Host smart-44f7913e-31fd-4ccc-85a3-43952aba88b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915870896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3915870896
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.564500212
Short name T99
Test name
Test status
Simulation time 79931637 ps
CPU time 3.02 seconds
Started Mar 31 03:55:24 PM PDT 24
Finished Mar 31 03:55:28 PM PDT 24
Peak memory 222636 kb
Host smart-10142822-69f4-4955-9cfa-6e71ae2fe7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564500212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.564500212
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_random.1383239958
Short name T578
Test name
Test status
Simulation time 1422611087 ps
CPU time 48.25 seconds
Started Mar 31 03:55:39 PM PDT 24
Finished Mar 31 03:56:28 PM PDT 24
Peak memory 209784 kb
Host smart-3e74617c-2970-4cf9-9836-329d59803895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383239958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1383239958
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3889865925
Short name T555
Test name
Test status
Simulation time 230525971 ps
CPU time 8.69 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:55:26 PM PDT 24
Peak memory 208376 kb
Host smart-a3b96e63-e72a-43ba-bad9-4e5536d007ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889865925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3889865925
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1704566488
Short name T744
Test name
Test status
Simulation time 110865034 ps
CPU time 3.19 seconds
Started Mar 31 03:55:43 PM PDT 24
Finished Mar 31 03:55:47 PM PDT 24
Peak memory 207224 kb
Host smart-a758a596-9b1d-4157-a658-a27f3e9bf796
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704566488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1704566488
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.299491607
Short name T759
Test name
Test status
Simulation time 163320576 ps
CPU time 3.05 seconds
Started Mar 31 03:55:18 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 209120 kb
Host smart-9a4db665-534f-45bd-beb6-e4faeaa70df0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299491607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.299491607
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.612674061
Short name T868
Test name
Test status
Simulation time 105482822 ps
CPU time 2.79 seconds
Started Mar 31 03:55:28 PM PDT 24
Finished Mar 31 03:55:31 PM PDT 24
Peak memory 207152 kb
Host smart-59509736-21d3-4d07-acab-3890a9d2a89a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612674061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.612674061
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3504461728
Short name T434
Test name
Test status
Simulation time 75379818 ps
CPU time 2.07 seconds
Started Mar 31 03:55:39 PM PDT 24
Finished Mar 31 03:55:42 PM PDT 24
Peak memory 209136 kb
Host smart-392c1812-971d-4bb2-822f-0ba763df3508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504461728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3504461728
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2596767135
Short name T658
Test name
Test status
Simulation time 458716961 ps
CPU time 2.82 seconds
Started Mar 31 03:55:29 PM PDT 24
Finished Mar 31 03:55:33 PM PDT 24
Peak memory 208828 kb
Host smart-cfebc477-b4bd-44e7-8dad-2affa63fc784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596767135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2596767135
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2130484662
Short name T412
Test name
Test status
Simulation time 611765852 ps
CPU time 4.41 seconds
Started Mar 31 03:55:17 PM PDT 24
Finished Mar 31 03:55:21 PM PDT 24
Peak memory 214576 kb
Host smart-d48cf69f-f7ef-4132-b803-8cc096af9460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130484662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2130484662
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2746396340
Short name T199
Test name
Test status
Simulation time 116581994 ps
CPU time 1.84 seconds
Started Mar 31 03:55:31 PM PDT 24
Finished Mar 31 03:55:34 PM PDT 24
Peak memory 210212 kb
Host smart-e86d2efd-1548-4cf8-84d8-9cc2d73d23c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746396340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2746396340
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.468729082
Short name T786
Test name
Test status
Simulation time 34831428 ps
CPU time 0.84 seconds
Started Mar 31 03:55:42 PM PDT 24
Finished Mar 31 03:55:43 PM PDT 24
Peak memory 206224 kb
Host smart-76022fbe-8678-41b1-823d-347209f8641b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468729082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.468729082
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3678368121
Short name T894
Test name
Test status
Simulation time 145666770 ps
CPU time 3.41 seconds
Started Mar 31 03:55:19 PM PDT 24
Finished Mar 31 03:55:23 PM PDT 24
Peak memory 214596 kb
Host smart-c3f8f5bd-c05e-4b1d-8a3b-810ea4d88d72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678368121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3678368121
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1147547253
Short name T73
Test name
Test status
Simulation time 85277947 ps
CPU time 3.18 seconds
Started Mar 31 03:55:27 PM PDT 24
Finished Mar 31 03:55:31 PM PDT 24
Peak memory 219124 kb
Host smart-17f4b6e6-ea09-4ed3-9a9e-4180d57527ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147547253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1147547253
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1298823396
Short name T507
Test name
Test status
Simulation time 98581046 ps
CPU time 2.9 seconds
Started Mar 31 03:55:16 PM PDT 24
Finished Mar 31 03:55:19 PM PDT 24
Peak memory 214504 kb
Host smart-7645b880-e0f5-40f2-b540-88556d2a4d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298823396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1298823396
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2378363187
Short name T306
Test name
Test status
Simulation time 1628081314 ps
CPU time 40.44 seconds
Started Mar 31 03:55:38 PM PDT 24
Finished Mar 31 03:56:19 PM PDT 24
Peak memory 209616 kb
Host smart-85f647b7-411b-48a6-976a-e9390ef20454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378363187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2378363187
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2713256762
Short name T863
Test name
Test status
Simulation time 781321692 ps
CPU time 3.45 seconds
Started Mar 31 03:55:25 PM PDT 24
Finished Mar 31 03:55:29 PM PDT 24
Peak memory 214640 kb
Host smart-e2a419da-26d6-47c2-83ea-173b915bad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713256762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2713256762
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2919309334
Short name T580
Test name
Test status
Simulation time 187182592 ps
CPU time 7 seconds
Started Mar 31 03:55:27 PM PDT 24
Finished Mar 31 03:55:34 PM PDT 24
Peak memory 215504 kb
Host smart-5eddebb8-e1c5-4778-a502-18151f5730e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919309334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2919309334
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3997385379
Short name T208
Test name
Test status
Simulation time 3598562792 ps
CPU time 47.97 seconds
Started Mar 31 03:55:19 PM PDT 24
Finished Mar 31 03:56:07 PM PDT 24
Peak memory 209412 kb
Host smart-7b2d9ced-5d21-4567-93c3-240aeee7b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997385379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3997385379
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3305294880
Short name T490
Test name
Test status
Simulation time 11301971707 ps
CPU time 40.21 seconds
Started Mar 31 03:55:36 PM PDT 24
Finished Mar 31 03:56:16 PM PDT 24
Peak memory 208288 kb
Host smart-f3df5e6a-7ba5-43ff-95ec-cc0915d6e675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305294880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3305294880
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1305971435
Short name T529
Test name
Test status
Simulation time 253614136 ps
CPU time 3.71 seconds
Started Mar 31 03:55:34 PM PDT 24
Finished Mar 31 03:55:38 PM PDT 24
Peak memory 207176 kb
Host smart-c6936fa1-f84d-4a3e-b74e-875c521e3600
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305971435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1305971435
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.956733588
Short name T187
Test name
Test status
Simulation time 475040980 ps
CPU time 4.46 seconds
Started Mar 31 03:55:20 PM PDT 24
Finished Mar 31 03:55:25 PM PDT 24
Peak memory 209172 kb
Host smart-86443d83-c03a-41c7-8905-b8b1498c9e53
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956733588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.956733588
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1607342657
Short name T474
Test name
Test status
Simulation time 148713263 ps
CPU time 5.53 seconds
Started Mar 31 03:55:35 PM PDT 24
Finished Mar 31 03:55:40 PM PDT 24
Peak memory 208328 kb
Host smart-984e72a3-93df-4be9-bb97-7a30ddbf36fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607342657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1607342657
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.964550213
Short name T738
Test name
Test status
Simulation time 19129862 ps
CPU time 1.73 seconds
Started Mar 31 03:55:50 PM PDT 24
Finished Mar 31 03:55:52 PM PDT 24
Peak memory 207944 kb
Host smart-b47f9209-4130-49d8-8d18-d0bad4762bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964550213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.964550213
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1404094
Short name T802
Test name
Test status
Simulation time 47843872 ps
CPU time 2.48 seconds
Started Mar 31 03:55:37 PM PDT 24
Finished Mar 31 03:55:40 PM PDT 24
Peak memory 206984 kb
Host smart-3423969c-5a3c-4658-a3f4-63ef973fabc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1404094
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3592856088
Short name T884
Test name
Test status
Simulation time 810773060 ps
CPU time 24.45 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:58 PM PDT 24
Peak memory 209056 kb
Host smart-e0ba435b-6c6a-41ff-9b7a-85061e208fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592856088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3592856088
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1097260550
Short name T686
Test name
Test status
Simulation time 450155671 ps
CPU time 3.9 seconds
Started Mar 31 03:55:49 PM PDT 24
Finished Mar 31 03:55:53 PM PDT 24
Peak memory 210388 kb
Host smart-3b76fe2a-cb48-4c6b-b69a-bea68e470eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097260550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1097260550
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.886466421
Short name T570
Test name
Test status
Simulation time 24740678 ps
CPU time 0.88 seconds
Started Mar 31 03:55:35 PM PDT 24
Finished Mar 31 03:55:36 PM PDT 24
Peak memory 206520 kb
Host smart-7d03369e-7a44-4602-b369-5eaae501645b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886466421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.886466421
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.408762882
Short name T400
Test name
Test status
Simulation time 882925034 ps
CPU time 3.94 seconds
Started Mar 31 03:55:24 PM PDT 24
Finished Mar 31 03:55:28 PM PDT 24
Peak memory 214704 kb
Host smart-468b524e-6bba-469d-a6c9-4a955878ec91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408762882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.408762882
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3632307543
Short name T579
Test name
Test status
Simulation time 68182824 ps
CPU time 1.71 seconds
Started Mar 31 03:55:52 PM PDT 24
Finished Mar 31 03:55:54 PM PDT 24
Peak memory 219376 kb
Host smart-aa7ee50c-67e1-40d9-96a0-14016ee3d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632307543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3632307543
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1910881747
Short name T337
Test name
Test status
Simulation time 143001104 ps
CPU time 3.32 seconds
Started Mar 31 03:55:34 PM PDT 24
Finished Mar 31 03:55:37 PM PDT 24
Peak memory 214648 kb
Host smart-740f1b1d-ae9c-4ff1-a122-d8f31e62aa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910881747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1910881747
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1668085669
Short name T23
Test name
Test status
Simulation time 150432632 ps
CPU time 4.08 seconds
Started Mar 31 03:55:35 PM PDT 24
Finished Mar 31 03:55:39 PM PDT 24
Peak memory 209820 kb
Host smart-da70a470-9055-43e2-99f2-d6a42cd9ba68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668085669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1668085669
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3236845153
Short name T62
Test name
Test status
Simulation time 428749104 ps
CPU time 2.97 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:36 PM PDT 24
Peak memory 218572 kb
Host smart-393b5818-ca0f-4e39-8ad6-a22238826e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236845153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3236845153
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2703161528
Short name T276
Test name
Test status
Simulation time 2706625267 ps
CPU time 60.39 seconds
Started Mar 31 03:55:48 PM PDT 24
Finished Mar 31 03:56:49 PM PDT 24
Peak memory 214844 kb
Host smart-bd10034d-3549-4d90-b7dc-c27d566aeba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703161528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2703161528
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3499324072
Short name T541
Test name
Test status
Simulation time 355024241 ps
CPU time 3.5 seconds
Started Mar 31 03:55:47 PM PDT 24
Finished Mar 31 03:55:51 PM PDT 24
Peak memory 207088 kb
Host smart-e6bc1b4a-8ddd-439a-a14f-381cac0393b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499324072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3499324072
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2360082378
Short name T678
Test name
Test status
Simulation time 71006115 ps
CPU time 2.81 seconds
Started Mar 31 03:55:44 PM PDT 24
Finished Mar 31 03:55:47 PM PDT 24
Peak memory 209256 kb
Host smart-fa09ec06-988e-44bb-a37a-aee5589c8b3a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360082378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2360082378
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2083593115
Short name T895
Test name
Test status
Simulation time 228772577 ps
CPU time 4.32 seconds
Started Mar 31 03:55:48 PM PDT 24
Finished Mar 31 03:55:52 PM PDT 24
Peak memory 207120 kb
Host smart-17b34db6-a0cb-4052-9130-185b36a4bc75
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083593115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2083593115
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3561105334
Short name T798
Test name
Test status
Simulation time 1129923191 ps
CPU time 21.28 seconds
Started Mar 31 03:55:31 PM PDT 24
Finished Mar 31 03:55:53 PM PDT 24
Peak memory 209208 kb
Host smart-cf2c0b81-ac40-48be-b395-6b48c7a9cde9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561105334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3561105334
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2563067846
Short name T506
Test name
Test status
Simulation time 565031131 ps
CPU time 7.83 seconds
Started Mar 31 03:55:39 PM PDT 24
Finished Mar 31 03:55:47 PM PDT 24
Peak memory 210112 kb
Host smart-18bf233f-9e0c-42a4-9ff5-10409cc590f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563067846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2563067846
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3109189683
Short name T414
Test name
Test status
Simulation time 854332157 ps
CPU time 17.68 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:51 PM PDT 24
Peak memory 208104 kb
Host smart-667febf6-30e1-411d-9050-519f1c7821cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109189683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3109189683
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.829286095
Short name T193
Test name
Test status
Simulation time 540731106 ps
CPU time 12.26 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:45 PM PDT 24
Peak memory 217192 kb
Host smart-e63f2d4f-f7ce-44cd-8243-5e00925a4807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829286095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.829286095
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2927498824
Short name T116
Test name
Test status
Simulation time 139217046 ps
CPU time 6.95 seconds
Started Mar 31 03:55:40 PM PDT 24
Finished Mar 31 03:55:47 PM PDT 24
Peak memory 222860 kb
Host smart-f76206fb-b4e3-42c3-af3f-4da843458fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927498824 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2927498824
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.18586699
Short name T25
Test name
Test status
Simulation time 1996761394 ps
CPU time 8.03 seconds
Started Mar 31 03:55:31 PM PDT 24
Finished Mar 31 03:55:40 PM PDT 24
Peak memory 209640 kb
Host smart-d32560de-fb59-4963-a140-64491320f2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18586699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.18586699
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.4112205158
Short name T559
Test name
Test status
Simulation time 953817676 ps
CPU time 23.14 seconds
Started Mar 31 03:55:34 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 221924 kb
Host smart-c2b0fab4-6c45-42f9-8663-34c91b735f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112205158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.4112205158
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2870052721
Short name T515
Test name
Test status
Simulation time 16607681 ps
CPU time 0.75 seconds
Started Mar 31 03:55:45 PM PDT 24
Finished Mar 31 03:55:45 PM PDT 24
Peak memory 206324 kb
Host smart-85c74bcd-a329-4e9e-a5ca-d41f17c3268c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870052721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2870052721
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.511456008
Short name T622
Test name
Test status
Simulation time 747234013 ps
CPU time 13.95 seconds
Started Mar 31 03:55:43 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 222952 kb
Host smart-53fe3c2b-0f34-4f01-9201-6bee5263acad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511456008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.511456008
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2748830268
Short name T681
Test name
Test status
Simulation time 578173832 ps
CPU time 6.44 seconds
Started Mar 31 03:55:40 PM PDT 24
Finished Mar 31 03:55:47 PM PDT 24
Peak memory 214584 kb
Host smart-95fc7798-9778-45b9-b97c-4e16d3bed347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748830268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2748830268
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2676251726
Short name T375
Test name
Test status
Simulation time 401525767 ps
CPU time 12.41 seconds
Started Mar 31 03:55:42 PM PDT 24
Finished Mar 31 03:55:55 PM PDT 24
Peak memory 222784 kb
Host smart-267e1fa3-df7f-421d-8c37-c042d10ca4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676251726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2676251726
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2956668412
Short name T46
Test name
Test status
Simulation time 46651866 ps
CPU time 2.53 seconds
Started Mar 31 03:55:40 PM PDT 24
Finished Mar 31 03:55:42 PM PDT 24
Peak memory 220824 kb
Host smart-ff36a1aa-1509-4629-9c6c-5d5f95a2bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956668412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2956668412
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2956885261
Short name T846
Test name
Test status
Simulation time 181268933 ps
CPU time 5.63 seconds
Started Mar 31 03:55:43 PM PDT 24
Finished Mar 31 03:55:49 PM PDT 24
Peak memory 214632 kb
Host smart-c277e69a-605c-42a5-8076-b82f974d81aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956885261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2956885261
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1134365261
Short name T854
Test name
Test status
Simulation time 63861952 ps
CPU time 2.34 seconds
Started Mar 31 03:55:23 PM PDT 24
Finished Mar 31 03:55:25 PM PDT 24
Peak memory 207196 kb
Host smart-3390d9b8-6000-4891-aa34-f280964f6a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134365261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1134365261
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2186573639
Short name T547
Test name
Test status
Simulation time 122257255 ps
CPU time 3.88 seconds
Started Mar 31 03:55:42 PM PDT 24
Finished Mar 31 03:55:46 PM PDT 24
Peak memory 206924 kb
Host smart-ff32b0f8-7aef-429f-abf5-dc78cce3c4d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186573639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2186573639
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2341800808
Short name T539
Test name
Test status
Simulation time 41116459 ps
CPU time 1.85 seconds
Started Mar 31 03:55:35 PM PDT 24
Finished Mar 31 03:55:37 PM PDT 24
Peak memory 207152 kb
Host smart-4755cdcd-d688-4b21-b45d-32d70b805c56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341800808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2341800808
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.709803538
Short name T810
Test name
Test status
Simulation time 514014264 ps
CPU time 7.21 seconds
Started Mar 31 03:55:34 PM PDT 24
Finished Mar 31 03:55:42 PM PDT 24
Peak memory 208300 kb
Host smart-a9eea6d0-3b4a-4af9-91eb-6f22789e5ba1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709803538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.709803538
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4031458181
Short name T661
Test name
Test status
Simulation time 148690383 ps
CPU time 1.73 seconds
Started Mar 31 03:55:38 PM PDT 24
Finished Mar 31 03:55:40 PM PDT 24
Peak memory 214672 kb
Host smart-f33fb30a-6beb-40eb-9fc6-3a5bd3a120ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031458181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4031458181
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2388655850
Short name T619
Test name
Test status
Simulation time 84312431 ps
CPU time 3.36 seconds
Started Mar 31 03:55:33 PM PDT 24
Finished Mar 31 03:55:37 PM PDT 24
Peak memory 206976 kb
Host smart-8dcb2341-a0b7-4afb-a6f8-1847077cdf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388655850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2388655850
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.243642303
Short name T342
Test name
Test status
Simulation time 4810255482 ps
CPU time 44.52 seconds
Started Mar 31 03:55:40 PM PDT 24
Finished Mar 31 03:56:25 PM PDT 24
Peak memory 222840 kb
Host smart-113cb96d-00a5-4088-8b4e-da26dae05291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243642303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.243642303
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1263242364
Short name T635
Test name
Test status
Simulation time 717159181 ps
CPU time 5.65 seconds
Started Mar 31 03:55:44 PM PDT 24
Finished Mar 31 03:55:50 PM PDT 24
Peak memory 207492 kb
Host smart-bfc13fba-98b6-431a-8f02-248dd92c1908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263242364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1263242364
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4142210528
Short name T16
Test name
Test status
Simulation time 34681222 ps
CPU time 2.16 seconds
Started Mar 31 03:55:45 PM PDT 24
Finished Mar 31 03:55:48 PM PDT 24
Peak memory 210288 kb
Host smart-b95266a8-34da-4fb9-8b2a-02155fadb876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142210528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4142210528
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1795534426
Short name T453
Test name
Test status
Simulation time 29909611 ps
CPU time 0.83 seconds
Started Mar 31 03:55:29 PM PDT 24
Finished Mar 31 03:55:31 PM PDT 24
Peak memory 206256 kb
Host smart-0269ffb4-10de-4a9f-8634-8e512a799551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795534426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1795534426
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3349469131
Short name T417
Test name
Test status
Simulation time 2048064002 ps
CPU time 55.81 seconds
Started Mar 31 03:55:38 PM PDT 24
Finished Mar 31 03:56:33 PM PDT 24
Peak memory 214772 kb
Host smart-695c8ef6-2802-4a68-a75b-5131da9cc95a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349469131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3349469131
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2460675415
Short name T523
Test name
Test status
Simulation time 282813627 ps
CPU time 3.18 seconds
Started Mar 31 03:55:42 PM PDT 24
Finished Mar 31 03:55:45 PM PDT 24
Peak memory 214968 kb
Host smart-c9c6463c-c193-4d79-a13e-13c00efaea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460675415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2460675415
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2979123729
Short name T54
Test name
Test status
Simulation time 164163538 ps
CPU time 3.97 seconds
Started Mar 31 03:55:44 PM PDT 24
Finished Mar 31 03:55:48 PM PDT 24
Peak memory 214752 kb
Host smart-aef06fde-9e8a-4e75-bd91-6f529adabd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979123729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2979123729
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.637839681
Short name T321
Test name
Test status
Simulation time 91258689 ps
CPU time 3.29 seconds
Started Mar 31 03:55:46 PM PDT 24
Finished Mar 31 03:55:49 PM PDT 24
Peak memory 209328 kb
Host smart-15ac0902-ffed-4caf-84bc-80788d692617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637839681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.637839681
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3168697933
Short name T12
Test name
Test status
Simulation time 59673892 ps
CPU time 3.12 seconds
Started Mar 31 03:55:42 PM PDT 24
Finished Mar 31 03:55:46 PM PDT 24
Peak memory 214700 kb
Host smart-72c106b0-ef01-4cba-9d10-23fdeb2d5366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168697933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3168697933
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3503011883
Short name T640
Test name
Test status
Simulation time 130326482 ps
CPU time 3.43 seconds
Started Mar 31 03:56:00 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 210380 kb
Host smart-27646995-f11f-413f-92ea-e32bdf34a04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503011883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3503011883
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1468483764
Short name T563
Test name
Test status
Simulation time 544850326 ps
CPU time 15.14 seconds
Started Mar 31 03:55:38 PM PDT 24
Finished Mar 31 03:55:54 PM PDT 24
Peak memory 209088 kb
Host smart-93c2ea8b-370a-486d-a756-a971ebf97b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468483764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1468483764
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1933137663
Short name T215
Test name
Test status
Simulation time 170822038 ps
CPU time 4 seconds
Started Mar 31 03:55:49 PM PDT 24
Finished Mar 31 03:55:53 PM PDT 24
Peak memory 207712 kb
Host smart-e5d3f35e-ff7f-4bbe-ac71-82a8c44e0811
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933137663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1933137663
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1210530265
Short name T571
Test name
Test status
Simulation time 78065154 ps
CPU time 2.8 seconds
Started Mar 31 03:55:41 PM PDT 24
Finished Mar 31 03:55:44 PM PDT 24
Peak memory 209032 kb
Host smart-107dfb45-c24f-4813-b082-b09f59526ba4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210530265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1210530265
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.933607416
Short name T741
Test name
Test status
Simulation time 61304298 ps
CPU time 2.83 seconds
Started Mar 31 03:55:46 PM PDT 24
Finished Mar 31 03:55:49 PM PDT 24
Peak memory 209564 kb
Host smart-77490fdd-73e7-4dc9-98a6-7898c5bd2087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933607416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.933607416
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.697740594
Short name T196
Test name
Test status
Simulation time 593255166 ps
CPU time 6.31 seconds
Started Mar 31 03:55:37 PM PDT 24
Finished Mar 31 03:55:44 PM PDT 24
Peak memory 207168 kb
Host smart-ff6b3c57-a66f-4134-8ad9-5d663b9ecfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697740594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.697740594
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.894651560
Short name T899
Test name
Test status
Simulation time 2786497882 ps
CPU time 22.92 seconds
Started Mar 31 03:55:40 PM PDT 24
Finished Mar 31 03:56:04 PM PDT 24
Peak memory 216024 kb
Host smart-50173b5c-ca5e-4e14-a591-bb59367930ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894651560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.894651560
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3825298621
Short name T821
Test name
Test status
Simulation time 99203216 ps
CPU time 4.76 seconds
Started Mar 31 03:55:51 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 209456 kb
Host smart-246d0812-172f-4eee-bdd6-0798c6821ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825298621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3825298621
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.118913802
Short name T397
Test name
Test status
Simulation time 59912978 ps
CPU time 1.42 seconds
Started Mar 31 03:55:38 PM PDT 24
Finished Mar 31 03:55:40 PM PDT 24
Peak memory 210024 kb
Host smart-547741e4-26f9-4983-b85a-59801cfd547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118913802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.118913802
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1829075504
Short name T822
Test name
Test status
Simulation time 261042957 ps
CPU time 1 seconds
Started Mar 31 03:54:11 PM PDT 24
Finished Mar 31 03:54:13 PM PDT 24
Peak memory 206504 kb
Host smart-91eb7a52-4edf-4efa-82f7-1eeb82a85e7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829075504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1829075504
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1724220421
Short name T431
Test name
Test status
Simulation time 204839528 ps
CPU time 3.85 seconds
Started Mar 31 03:54:21 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 214568 kb
Host smart-7cf894b6-ec53-49bf-832f-27476d3be80e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724220421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1724220421
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3427183608
Short name T717
Test name
Test status
Simulation time 34516304 ps
CPU time 1.65 seconds
Started Mar 31 03:54:07 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 206912 kb
Host smart-e57c9585-3f37-4d54-9b9b-5e577f4bd8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427183608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3427183608
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2795827672
Short name T725
Test name
Test status
Simulation time 777724189 ps
CPU time 4.41 seconds
Started Mar 31 03:54:00 PM PDT 24
Finished Mar 31 03:54:06 PM PDT 24
Peak memory 221116 kb
Host smart-8b657635-0aa3-4248-a885-d8fd09b137e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795827672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2795827672
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1288285965
Short name T827
Test name
Test status
Simulation time 84997710 ps
CPU time 3.59 seconds
Started Mar 31 03:54:03 PM PDT 24
Finished Mar 31 03:54:08 PM PDT 24
Peak memory 209340 kb
Host smart-c43a69f2-0179-4826-921b-10f122207c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288285965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1288285965
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.697930602
Short name T584
Test name
Test status
Simulation time 299218740 ps
CPU time 3.55 seconds
Started Mar 31 03:54:07 PM PDT 24
Finished Mar 31 03:54:11 PM PDT 24
Peak memory 209844 kb
Host smart-a28a9d68-ba3d-44e2-bf9f-a455e4248078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697930602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.697930602
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.420870109
Short name T43
Test name
Test status
Simulation time 2099513050 ps
CPU time 29.8 seconds
Started Mar 31 03:54:03 PM PDT 24
Finished Mar 31 03:54:34 PM PDT 24
Peak memory 230756 kb
Host smart-de5b6d0a-28fb-444f-8ec2-2a385dd24dea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420870109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.420870109
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3732070393
Short name T831
Test name
Test status
Simulation time 63003379 ps
CPU time 2.94 seconds
Started Mar 31 03:54:12 PM PDT 24
Finished Mar 31 03:54:15 PM PDT 24
Peak memory 208924 kb
Host smart-c9afdc7c-3c25-4bcb-afa5-490871d14919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732070393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3732070393
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.825214774
Short name T15
Test name
Test status
Simulation time 735450142 ps
CPU time 6 seconds
Started Mar 31 03:54:10 PM PDT 24
Finished Mar 31 03:54:16 PM PDT 24
Peak memory 208920 kb
Host smart-ecb3c5ec-01b9-4f75-ac38-94ed68c9b386
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825214774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.825214774
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2548982569
Short name T379
Test name
Test status
Simulation time 610596447 ps
CPU time 17.57 seconds
Started Mar 31 03:54:21 PM PDT 24
Finished Mar 31 03:54:38 PM PDT 24
Peak memory 208076 kb
Host smart-8dfb03e6-ce82-40ec-acd5-c8fbcce07afb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548982569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2548982569
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1399007931
Short name T757
Test name
Test status
Simulation time 63631186 ps
CPU time 2.75 seconds
Started Mar 31 03:54:14 PM PDT 24
Finished Mar 31 03:54:17 PM PDT 24
Peak memory 214680 kb
Host smart-ade5df42-5f0b-4c57-8f45-f7f6039c69aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399007931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1399007931
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1331859313
Short name T84
Test name
Test status
Simulation time 367388717 ps
CPU time 2.78 seconds
Started Mar 31 03:54:20 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 208612 kb
Host smart-6b0b2f48-5e84-4c5f-a677-3ea69a8fc54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331859313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1331859313
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2810887276
Short name T195
Test name
Test status
Simulation time 2159957438 ps
CPU time 15.22 seconds
Started Mar 31 03:53:52 PM PDT 24
Finished Mar 31 03:54:08 PM PDT 24
Peak memory 217500 kb
Host smart-4ee05e11-817e-403d-aef9-0c273ee79f3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810887276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2810887276
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.208741369
Short name T496
Test name
Test status
Simulation time 200846806 ps
CPU time 3.11 seconds
Started Mar 31 03:54:04 PM PDT 24
Finished Mar 31 03:54:09 PM PDT 24
Peak memory 207680 kb
Host smart-d98c4618-19c8-4470-bfe8-c87a3b1de6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208741369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.208741369
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.4090986994
Short name T60
Test name
Test status
Simulation time 85146880 ps
CPU time 2.75 seconds
Started Mar 31 03:54:13 PM PDT 24
Finished Mar 31 03:54:15 PM PDT 24
Peak memory 210756 kb
Host smart-519bb639-c3a6-408c-a230-054028d3d4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090986994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.4090986994
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3916965760
Short name T436
Test name
Test status
Simulation time 84445282 ps
CPU time 0.78 seconds
Started Mar 31 03:55:53 PM PDT 24
Finished Mar 31 03:55:54 PM PDT 24
Peak memory 206204 kb
Host smart-6b7e2a0a-f7c9-4e66-8622-ce6fc8c32b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916965760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3916965760
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.877277772
Short name T893
Test name
Test status
Simulation time 154086150 ps
CPU time 8.69 seconds
Started Mar 31 03:55:49 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 214608 kb
Host smart-c68849d2-97ef-45d7-96a6-61d965ce2bc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877277772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.877277772
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.171551157
Short name T27
Test name
Test status
Simulation time 234610217 ps
CPU time 3.6 seconds
Started Mar 31 03:55:49 PM PDT 24
Finished Mar 31 03:55:52 PM PDT 24
Peak memory 220920 kb
Host smart-7753806b-de80-4af4-bbdc-de157e1a0ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171551157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.171551157
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.843496508
Short name T372
Test name
Test status
Simulation time 344096539 ps
CPU time 7.89 seconds
Started Mar 31 03:55:43 PM PDT 24
Finished Mar 31 03:55:51 PM PDT 24
Peak memory 209100 kb
Host smart-191a6dd1-ed17-443d-8313-2d3b233c88b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843496508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.843496508
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.201314775
Short name T659
Test name
Test status
Simulation time 763920030 ps
CPU time 4.71 seconds
Started Mar 31 03:55:52 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 222756 kb
Host smart-e364b4ec-6f33-4aa5-bd8a-4d8c866ad4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201314775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.201314775
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2276167643
Short name T887
Test name
Test status
Simulation time 64386165 ps
CPU time 3.55 seconds
Started Mar 31 03:55:44 PM PDT 24
Finished Mar 31 03:55:48 PM PDT 24
Peak memory 209536 kb
Host smart-6a4c6ff3-01f1-4379-a4f8-e5258b2a59c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276167643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2276167643
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3434218614
Short name T588
Test name
Test status
Simulation time 83814888 ps
CPU time 3.87 seconds
Started Mar 31 03:55:35 PM PDT 24
Finished Mar 31 03:55:39 PM PDT 24
Peak memory 210088 kb
Host smart-07511df0-91f4-4bf8-8db9-40c5ba4abaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434218614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3434218614
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3612036053
Short name T114
Test name
Test status
Simulation time 33338083 ps
CPU time 2.37 seconds
Started Mar 31 03:55:36 PM PDT 24
Finished Mar 31 03:55:38 PM PDT 24
Peak memory 207532 kb
Host smart-8ef5354c-402c-4506-a633-3ee470bff0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612036053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3612036053
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4000728837
Short name T630
Test name
Test status
Simulation time 127926011 ps
CPU time 2.38 seconds
Started Mar 31 03:55:31 PM PDT 24
Finished Mar 31 03:55:34 PM PDT 24
Peak memory 207188 kb
Host smart-597418e4-c532-4c80-b4e2-2ebad6c41f13
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000728837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4000728837
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2794776302
Short name T133
Test name
Test status
Simulation time 1051286541 ps
CPU time 15.27 seconds
Started Mar 31 03:55:47 PM PDT 24
Finished Mar 31 03:56:02 PM PDT 24
Peak memory 208144 kb
Host smart-de084f6c-98f3-4ab3-8d01-f6d9c011e4a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794776302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2794776302
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1113959639
Short name T509
Test name
Test status
Simulation time 196839948 ps
CPU time 2.82 seconds
Started Mar 31 03:55:45 PM PDT 24
Finished Mar 31 03:55:48 PM PDT 24
Peak memory 207332 kb
Host smart-bc6d57ea-31fe-4afd-8f48-4b8c47e661f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113959639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1113959639
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2623922886
Short name T799
Test name
Test status
Simulation time 1239064758 ps
CPU time 3.9 seconds
Started Mar 31 03:55:31 PM PDT 24
Finished Mar 31 03:55:36 PM PDT 24
Peak memory 214676 kb
Host smart-cd79f0b4-cdd0-466b-a0a7-9f77dd4c83fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623922886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2623922886
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2718560251
Short name T476
Test name
Test status
Simulation time 691001070 ps
CPU time 12.69 seconds
Started Mar 31 03:55:37 PM PDT 24
Finished Mar 31 03:55:50 PM PDT 24
Peak memory 208196 kb
Host smart-bed50f63-85dc-41b4-b7af-e32874150f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718560251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2718560251
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.4008237170
Short name T359
Test name
Test status
Simulation time 1307267756 ps
CPU time 32.95 seconds
Started Mar 31 03:55:56 PM PDT 24
Finished Mar 31 03:56:29 PM PDT 24
Peak memory 222892 kb
Host smart-8a18a8cc-ddaf-46b3-a476-a602550572ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008237170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4008237170
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.303486415
Short name T465
Test name
Test status
Simulation time 409377850 ps
CPU time 4.83 seconds
Started Mar 31 03:55:51 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 207956 kb
Host smart-23d0a1bb-f1fb-44ab-8555-5421db9c38d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303486415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.303486415
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.670285593
Short name T17
Test name
Test status
Simulation time 370291707 ps
CPU time 9.73 seconds
Started Mar 31 03:55:59 PM PDT 24
Finished Mar 31 03:56:09 PM PDT 24
Peak memory 211004 kb
Host smart-9b1ce51f-dcf3-4e20-9d75-7f5fdedcb440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670285593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.670285593
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2695998670
Short name T601
Test name
Test status
Simulation time 10906575 ps
CPU time 0.87 seconds
Started Mar 31 03:55:43 PM PDT 24
Finished Mar 31 03:55:44 PM PDT 24
Peak memory 206276 kb
Host smart-4a17acd9-9b88-43de-a623-52583f5d9365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695998670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2695998670
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3054793751
Short name T300
Test name
Test status
Simulation time 575487955 ps
CPU time 22.4 seconds
Started Mar 31 03:56:02 PM PDT 24
Finished Mar 31 03:56:24 PM PDT 24
Peak memory 215620 kb
Host smart-741e0ea9-5864-4536-8cea-7013e742f3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054793751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3054793751
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1885950889
Short name T460
Test name
Test status
Simulation time 806153060 ps
CPU time 4.06 seconds
Started Mar 31 03:55:51 PM PDT 24
Finished Mar 31 03:55:55 PM PDT 24
Peak memory 214756 kb
Host smart-d002e574-86c7-435f-8401-26c0d5628757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885950889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1885950889
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.596620732
Short name T293
Test name
Test status
Simulation time 97306066 ps
CPU time 3.94 seconds
Started Mar 31 03:56:06 PM PDT 24
Finished Mar 31 03:56:10 PM PDT 24
Peak memory 218808 kb
Host smart-889a64b5-d6b9-4975-8c75-b9a6ebd72ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596620732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.596620732
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3802296762
Short name T793
Test name
Test status
Simulation time 2267290442 ps
CPU time 35.87 seconds
Started Mar 31 03:55:40 PM PDT 24
Finished Mar 31 03:56:15 PM PDT 24
Peak memory 212288 kb
Host smart-07694ffe-f579-4348-bf08-2e08cf354746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802296762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3802296762
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.906894499
Short name T676
Test name
Test status
Simulation time 145220915 ps
CPU time 1.98 seconds
Started Mar 31 03:56:01 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 207084 kb
Host smart-2bf2bdee-04ba-4cbb-a508-f28ba0d26ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906894499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.906894499
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.767083442
Short name T260
Test name
Test status
Simulation time 2151427334 ps
CPU time 16.14 seconds
Started Mar 31 03:55:48 PM PDT 24
Finished Mar 31 03:56:05 PM PDT 24
Peak memory 209556 kb
Host smart-47c60236-2a7d-43bd-8309-478f9359e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767083442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.767083442
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3666206978
Short name T712
Test name
Test status
Simulation time 63212771 ps
CPU time 2.47 seconds
Started Mar 31 03:55:50 PM PDT 24
Finished Mar 31 03:55:52 PM PDT 24
Peak memory 207752 kb
Host smart-5f9a4875-c109-42fe-a5b6-80018ad40bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666206978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3666206978
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3508278250
Short name T82
Test name
Test status
Simulation time 38466387 ps
CPU time 2.46 seconds
Started Mar 31 03:55:43 PM PDT 24
Finished Mar 31 03:55:45 PM PDT 24
Peak memory 208736 kb
Host smart-37358ba7-cb3b-43bc-91d5-15430d86a608
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508278250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3508278250
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3261859670
Short name T708
Test name
Test status
Simulation time 5583889143 ps
CPU time 58.44 seconds
Started Mar 31 03:55:53 PM PDT 24
Finished Mar 31 03:56:51 PM PDT 24
Peak memory 209044 kb
Host smart-4f2ded16-98c6-4766-b7f1-af07860fed81
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261859670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3261859670
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1513307344
Short name T500
Test name
Test status
Simulation time 453483189 ps
CPU time 4.29 seconds
Started Mar 31 03:55:51 PM PDT 24
Finished Mar 31 03:55:55 PM PDT 24
Peak memory 206996 kb
Host smart-6cccce93-1d92-4aa3-ac89-f19568564374
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513307344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1513307344
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4053796213
Short name T551
Test name
Test status
Simulation time 37980365 ps
CPU time 1.96 seconds
Started Mar 31 03:55:54 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 208528 kb
Host smart-a6024c54-f626-4045-bb53-ec47b95f488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053796213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4053796213
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3385275448
Short name T770
Test name
Test status
Simulation time 336823392 ps
CPU time 3.02 seconds
Started Mar 31 03:55:53 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 207100 kb
Host smart-4d9feb53-2cc6-4773-8bbf-50900706baf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385275448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3385275448
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3157900243
Short name T753
Test name
Test status
Simulation time 1442456273 ps
CPU time 15.71 seconds
Started Mar 31 03:55:45 PM PDT 24
Finished Mar 31 03:56:00 PM PDT 24
Peak memory 216912 kb
Host smart-d8fa40aa-1e91-4334-9c38-622ec900fba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157900243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3157900243
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.858996032
Short name T263
Test name
Test status
Simulation time 871293276 ps
CPU time 22.03 seconds
Started Mar 31 03:55:57 PM PDT 24
Finished Mar 31 03:56:19 PM PDT 24
Peak memory 209432 kb
Host smart-f6efec22-be22-4f50-b2cc-c569464bbc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858996032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.858996032
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3928519014
Short name T390
Test name
Test status
Simulation time 251098625 ps
CPU time 2.11 seconds
Started Mar 31 03:55:58 PM PDT 24
Finished Mar 31 03:56:00 PM PDT 24
Peak memory 210068 kb
Host smart-0e2db0c9-547c-447c-a1ac-c38e0cca42cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928519014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3928519014
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.453776706
Short name T87
Test name
Test status
Simulation time 10319845 ps
CPU time 0.87 seconds
Started Mar 31 03:55:52 PM PDT 24
Finished Mar 31 03:55:53 PM PDT 24
Peak memory 206328 kb
Host smart-eed951f9-6f62-4d23-903f-5abd72d12aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453776706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.453776706
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3207063257
Short name T415
Test name
Test status
Simulation time 819253433 ps
CPU time 11.24 seconds
Started Mar 31 03:55:45 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 215476 kb
Host smart-5cb1d041-086d-4961-b2a8-3cad1e7bfaeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207063257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3207063257
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3172764690
Short name T21
Test name
Test status
Simulation time 114874483 ps
CPU time 2.93 seconds
Started Mar 31 03:55:50 PM PDT 24
Finished Mar 31 03:55:53 PM PDT 24
Peak memory 223144 kb
Host smart-25e8782b-ebb2-4044-b002-3f20c30d055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172764690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3172764690
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1002006680
Short name T495
Test name
Test status
Simulation time 245283437 ps
CPU time 3.79 seconds
Started Mar 31 03:55:58 PM PDT 24
Finished Mar 31 03:56:01 PM PDT 24
Peak memory 216480 kb
Host smart-7d743089-e829-41b3-8938-a2a77c9a1d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002006680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1002006680
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1801711223
Short name T85
Test name
Test status
Simulation time 287790045 ps
CPU time 3.53 seconds
Started Mar 31 03:55:41 PM PDT 24
Finished Mar 31 03:55:45 PM PDT 24
Peak memory 209724 kb
Host smart-d7e21a24-0d0e-4f00-9a47-d737dd66fcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801711223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1801711223
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1347310895
Short name T780
Test name
Test status
Simulation time 346369115 ps
CPU time 7.63 seconds
Started Mar 31 03:55:53 PM PDT 24
Finished Mar 31 03:56:00 PM PDT 24
Peak memory 214616 kb
Host smart-06168af5-e971-4ca4-b2d5-bc41aff8d02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347310895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1347310895
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2537412056
Short name T234
Test name
Test status
Simulation time 961623514 ps
CPU time 5.39 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:56:01 PM PDT 24
Peak memory 210228 kb
Host smart-961048ff-e9dd-4b25-9d16-ae1c7e9eeda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537412056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2537412056
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2805272466
Short name T699
Test name
Test status
Simulation time 647470837 ps
CPU time 8.17 seconds
Started Mar 31 03:55:56 PM PDT 24
Finished Mar 31 03:56:04 PM PDT 24
Peak memory 214716 kb
Host smart-6da98520-ad9a-409f-9548-9d327eb0f29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805272466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2805272466
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.212904981
Short name T274
Test name
Test status
Simulation time 57298312 ps
CPU time 2.33 seconds
Started Mar 31 03:55:51 PM PDT 24
Finished Mar 31 03:55:53 PM PDT 24
Peak memory 209192 kb
Host smart-4c73214f-3bf4-4e24-a750-c1890321b195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212904981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.212904981
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4111009970
Short name T346
Test name
Test status
Simulation time 1652595328 ps
CPU time 31.03 seconds
Started Mar 31 03:55:42 PM PDT 24
Finished Mar 31 03:56:14 PM PDT 24
Peak memory 208644 kb
Host smart-42c5ea7d-7e01-4833-83b9-1665bc553c0d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111009970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4111009970
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.348017581
Short name T471
Test name
Test status
Simulation time 847756503 ps
CPU time 9.45 seconds
Started Mar 31 03:55:52 PM PDT 24
Finished Mar 31 03:56:01 PM PDT 24
Peak memory 209344 kb
Host smart-4391058a-6d05-4670-849a-00686abd4c05
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348017581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.348017581
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3984328393
Short name T841
Test name
Test status
Simulation time 413659224 ps
CPU time 2.99 seconds
Started Mar 31 03:56:00 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 208808 kb
Host smart-71b2ea56-61f3-4050-b723-cfebebf0969a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984328393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3984328393
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.225993846
Short name T514
Test name
Test status
Simulation time 475290756 ps
CPU time 3.85 seconds
Started Mar 31 03:55:45 PM PDT 24
Finished Mar 31 03:55:49 PM PDT 24
Peak memory 210880 kb
Host smart-3cd5861d-8778-4aaf-bc96-f83bfcc472e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225993846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.225993846
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2430348736
Short name T464
Test name
Test status
Simulation time 50343738 ps
CPU time 2.52 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 208440 kb
Host smart-fd4f7d50-b11f-49b4-8d9a-174d126fe7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430348736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2430348736
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.648552222
Short name T185
Test name
Test status
Simulation time 19146873 ps
CPU time 0.76 seconds
Started Mar 31 03:56:03 PM PDT 24
Finished Mar 31 03:56:04 PM PDT 24
Peak memory 206312 kb
Host smart-3643da15-0181-4d68-9ea7-cc46fd524e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648552222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.648552222
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2717688460
Short name T585
Test name
Test status
Simulation time 111672261 ps
CPU time 4.6 seconds
Started Mar 31 03:55:56 PM PDT 24
Finished Mar 31 03:56:01 PM PDT 24
Peak memory 220092 kb
Host smart-0463aeee-6998-4253-a808-ee85f862553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717688460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2717688460
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2858473912
Short name T600
Test name
Test status
Simulation time 2697849920 ps
CPU time 25.87 seconds
Started Mar 31 03:55:50 PM PDT 24
Finished Mar 31 03:56:16 PM PDT 24
Peak memory 219864 kb
Host smart-b7e22d32-c657-49ac-b7fb-8ae11774b5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858473912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2858473912
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1304928096
Short name T112
Test name
Test status
Simulation time 109786888 ps
CPU time 0.81 seconds
Started Mar 31 03:56:22 PM PDT 24
Finished Mar 31 03:56:23 PM PDT 24
Peak memory 206328 kb
Host smart-1b9b0f32-e105-4ad7-9872-f4c0091face0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304928096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1304928096
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3264998979
Short name T366
Test name
Test status
Simulation time 45045804 ps
CPU time 3.25 seconds
Started Mar 31 03:56:02 PM PDT 24
Finished Mar 31 03:56:05 PM PDT 24
Peak memory 214708 kb
Host smart-498b5f69-4604-4b6a-8b60-c109ff7fbb00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264998979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3264998979
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2972188000
Short name T4
Test name
Test status
Simulation time 111999633 ps
CPU time 2.83 seconds
Started Mar 31 03:56:05 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 209720 kb
Host smart-96ea0194-5b5f-4565-93d9-cdab310256e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972188000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2972188000
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1791909442
Short name T840
Test name
Test status
Simulation time 543932690 ps
CPU time 3.4 seconds
Started Mar 31 03:56:00 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 218704 kb
Host smart-763451b1-3bd7-4d6b-a399-f4ce0de9ebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791909442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1791909442
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.561645257
Short name T338
Test name
Test status
Simulation time 344620696 ps
CPU time 4.5 seconds
Started Mar 31 03:56:04 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 214616 kb
Host smart-55148374-6140-4238-8771-625efeef550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561645257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.561645257
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.318226554
Short name T752
Test name
Test status
Simulation time 163001801 ps
CPU time 2.2 seconds
Started Mar 31 03:56:06 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 214764 kb
Host smart-d2ac6f08-f6f0-4da6-b6c1-19ebd31d9426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318226554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.318226554
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.513335812
Short name T806
Test name
Test status
Simulation time 347122990 ps
CPU time 4.05 seconds
Started Mar 31 03:55:47 PM PDT 24
Finished Mar 31 03:55:51 PM PDT 24
Peak memory 208948 kb
Host smart-12611526-b58b-42e2-8d7a-ac15f6d80fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513335812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.513335812
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1651131257
Short name T637
Test name
Test status
Simulation time 27818616 ps
CPU time 1.9 seconds
Started Mar 31 03:55:59 PM PDT 24
Finished Mar 31 03:56:01 PM PDT 24
Peak memory 207200 kb
Host smart-e36435dc-6fa1-44fc-8e69-6745c693b02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651131257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1651131257
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2835904388
Short name T653
Test name
Test status
Simulation time 258533233 ps
CPU time 3.31 seconds
Started Mar 31 03:56:01 PM PDT 24
Finished Mar 31 03:56:04 PM PDT 24
Peak memory 207656 kb
Host smart-d6a4eade-87b0-4cb6-b942-8ee42eb13ca8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835904388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2835904388
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2368991553
Short name T593
Test name
Test status
Simulation time 150633949 ps
CPU time 5.56 seconds
Started Mar 31 03:56:05 PM PDT 24
Finished Mar 31 03:56:10 PM PDT 24
Peak memory 209044 kb
Host smart-3572560a-b146-4e59-b764-d99eb74af602
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368991553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2368991553
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3887978102
Short name T498
Test name
Test status
Simulation time 257095895 ps
CPU time 6.36 seconds
Started Mar 31 03:55:50 PM PDT 24
Finished Mar 31 03:55:58 PM PDT 24
Peak memory 208760 kb
Host smart-a3ecb543-da5a-4007-bffe-a41a7d08bee4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887978102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3887978102
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3949854439
Short name T587
Test name
Test status
Simulation time 170594404 ps
CPU time 3.46 seconds
Started Mar 31 03:56:02 PM PDT 24
Finished Mar 31 03:56:06 PM PDT 24
Peak memory 214484 kb
Host smart-21ef5b28-4154-45df-92be-f23a6b07335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949854439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3949854439
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.430214732
Short name T404
Test name
Test status
Simulation time 38774330 ps
CPU time 2.56 seconds
Started Mar 31 03:55:53 PM PDT 24
Finished Mar 31 03:55:55 PM PDT 24
Peak memory 208392 kb
Host smart-b3802741-c417-4258-8228-64de0217b3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430214732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.430214732
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2169946642
Short name T317
Test name
Test status
Simulation time 46496498 ps
CPU time 3.29 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:55:59 PM PDT 24
Peak memory 210672 kb
Host smart-3dac9e98-0f60-401f-96d0-42dc46b1ca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169946642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2169946642
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.157112113
Short name T546
Test name
Test status
Simulation time 1439624777 ps
CPU time 7.27 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:56:02 PM PDT 24
Peak memory 211124 kb
Host smart-9d4f219b-07f8-40b1-aff8-39e9d0e5bbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157112113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.157112113
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3327422403
Short name T447
Test name
Test status
Simulation time 22957077 ps
CPU time 0.77 seconds
Started Mar 31 03:56:08 PM PDT 24
Finished Mar 31 03:56:09 PM PDT 24
Peak memory 206072 kb
Host smart-6b8732d2-d9aa-48cb-b538-257804d811eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327422403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3327422403
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1939566696
Short name T136
Test name
Test status
Simulation time 317286384 ps
CPU time 8.41 seconds
Started Mar 31 03:56:07 PM PDT 24
Finished Mar 31 03:56:15 PM PDT 24
Peak memory 214516 kb
Host smart-6be6aac0-2a82-4ebc-a62e-7abf06a2eb9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939566696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1939566696
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4193602574
Short name T711
Test name
Test status
Simulation time 2275852676 ps
CPU time 3.99 seconds
Started Mar 31 03:55:58 PM PDT 24
Finished Mar 31 03:56:02 PM PDT 24
Peak memory 214732 kb
Host smart-62b9aeb5-48d7-4153-a6c5-e6fce9117364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193602574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4193602574
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3181567534
Short name T100
Test name
Test status
Simulation time 873443302 ps
CPU time 7.01 seconds
Started Mar 31 03:55:48 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 209672 kb
Host smart-34b65d5d-d6bf-4a2a-ba3c-c78b32458364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181567534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3181567534
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3219947292
Short name T268
Test name
Test status
Simulation time 144171333 ps
CPU time 2.16 seconds
Started Mar 31 03:55:52 PM PDT 24
Finished Mar 31 03:55:55 PM PDT 24
Peak memory 209188 kb
Host smart-b2b96366-fb49-4923-8b48-0fd066b9edf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219947292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3219947292
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1686772943
Short name T67
Test name
Test status
Simulation time 106751279 ps
CPU time 2.13 seconds
Started Mar 31 03:56:06 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 215716 kb
Host smart-8b4edbb7-4547-41fa-9368-3e196dbefacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686772943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1686772943
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2571837185
Short name T377
Test name
Test status
Simulation time 3408796052 ps
CPU time 36.78 seconds
Started Mar 31 03:55:52 PM PDT 24
Finished Mar 31 03:56:29 PM PDT 24
Peak memory 214872 kb
Host smart-e8fb15ed-c86f-410b-b297-6a678ec7a6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571837185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2571837185
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1257211740
Short name T385
Test name
Test status
Simulation time 170981378 ps
CPU time 2.47 seconds
Started Mar 31 03:55:51 PM PDT 24
Finished Mar 31 03:55:54 PM PDT 24
Peak memory 207068 kb
Host smart-2a2d15df-e5c4-4100-addf-bbac4ad23595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257211740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1257211740
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3144158688
Short name T214
Test name
Test status
Simulation time 365750576 ps
CPU time 3.94 seconds
Started Mar 31 03:55:50 PM PDT 24
Finished Mar 31 03:55:54 PM PDT 24
Peak memory 207092 kb
Host smart-02520d32-c629-43a1-8498-f5bc19ccb9ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144158688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3144158688
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3661822555
Short name T553
Test name
Test status
Simulation time 256306527 ps
CPU time 7.28 seconds
Started Mar 31 03:55:53 PM PDT 24
Finished Mar 31 03:56:00 PM PDT 24
Peak memory 208220 kb
Host smart-605fa6b2-de9d-46db-a7cb-7a2550459146
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661822555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3661822555
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3977812714
Short name T451
Test name
Test status
Simulation time 21158095 ps
CPU time 1.82 seconds
Started Mar 31 03:56:00 PM PDT 24
Finished Mar 31 03:56:02 PM PDT 24
Peak memory 207224 kb
Host smart-83b25e65-09c7-4301-95e8-dd9ddc182881
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977812714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3977812714
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2975476565
Short name T847
Test name
Test status
Simulation time 492160233 ps
CPU time 6.99 seconds
Started Mar 31 03:56:04 PM PDT 24
Finished Mar 31 03:56:11 PM PDT 24
Peak memory 218568 kb
Host smart-020dcfeb-e151-4d16-a427-7858722f9ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975476565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2975476565
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2800494849
Short name T454
Test name
Test status
Simulation time 1477794573 ps
CPU time 13.62 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:56:09 PM PDT 24
Peak memory 208444 kb
Host smart-a70b2c2c-c733-40e5-8c5b-8cc900ad288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800494849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2800494849
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2567015592
Short name T369
Test name
Test status
Simulation time 769379510 ps
CPU time 6.74 seconds
Started Mar 31 03:55:54 PM PDT 24
Finished Mar 31 03:56:01 PM PDT 24
Peak memory 214696 kb
Host smart-7cdad17a-6b7b-4093-ad9a-8b1286000451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567015592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2567015592
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3156076068
Short name T694
Test name
Test status
Simulation time 98040775 ps
CPU time 3.66 seconds
Started Mar 31 03:56:07 PM PDT 24
Finished Mar 31 03:56:11 PM PDT 24
Peak memory 209944 kb
Host smart-2f3eaabb-d7ff-4e2f-9ed4-4a19647779ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156076068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3156076068
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.140019119
Short name T102
Test name
Test status
Simulation time 125479035 ps
CPU time 0.93 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 206316 kb
Host smart-7b34cf37-9a59-4f81-9d43-39e6574b4b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140019119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.140019119
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.868452731
Short name T665
Test name
Test status
Simulation time 119155451 ps
CPU time 2.03 seconds
Started Mar 31 03:55:54 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 219464 kb
Host smart-3a354d76-3ec3-4b2a-b1f8-f16d4eb7a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868452731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.868452731
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3532272366
Short name T252
Test name
Test status
Simulation time 78331417 ps
CPU time 1.75 seconds
Started Mar 31 03:55:54 PM PDT 24
Finished Mar 31 03:55:56 PM PDT 24
Peak memory 214652 kb
Host smart-f69bf5e6-d5c9-45f5-8185-69eec73bd0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532272366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3532272366
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.18249138
Short name T93
Test name
Test status
Simulation time 1099382854 ps
CPU time 8.03 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 209604 kb
Host smart-d2426cd0-9a74-49b0-a4ed-f7b9edb4362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18249138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.18249138
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3815698147
Short name T308
Test name
Test status
Simulation time 73395608 ps
CPU time 3.9 seconds
Started Mar 31 03:56:04 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 211256 kb
Host smart-7ef360ec-5400-4141-9dd6-ed4c89fa7d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815698147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3815698147
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.541236580
Short name T688
Test name
Test status
Simulation time 300860171 ps
CPU time 2.38 seconds
Started Mar 31 03:56:04 PM PDT 24
Finished Mar 31 03:56:06 PM PDT 24
Peak memory 220184 kb
Host smart-ff91a6be-3363-4be3-ad47-2ca71e8ece3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541236580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.541236580
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.408862315
Short name T246
Test name
Test status
Simulation time 345222230 ps
CPU time 4.65 seconds
Started Mar 31 03:55:57 PM PDT 24
Finished Mar 31 03:56:02 PM PDT 24
Peak memory 216832 kb
Host smart-191f98de-00e9-4e3e-b61d-aaaccc7f00be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408862315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.408862315
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1885629353
Short name T883
Test name
Test status
Simulation time 356429535 ps
CPU time 5.4 seconds
Started Mar 31 03:55:45 PM PDT 24
Finished Mar 31 03:55:51 PM PDT 24
Peak memory 209016 kb
Host smart-52fb37c5-b9f5-41b1-a11a-7b6498346796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885629353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1885629353
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1529006103
Short name T749
Test name
Test status
Simulation time 922762744 ps
CPU time 5.87 seconds
Started Mar 31 03:56:02 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 208972 kb
Host smart-c312bc88-2195-451c-8dac-c1a54efd1834
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529006103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1529006103
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2964590346
Short name T696
Test name
Test status
Simulation time 157996936 ps
CPU time 2.54 seconds
Started Mar 31 03:55:47 PM PDT 24
Finished Mar 31 03:55:50 PM PDT 24
Peak memory 207668 kb
Host smart-62226c1d-e2aa-4080-899e-ee6f3a9b495d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964590346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2964590346
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.804118578
Short name T347
Test name
Test status
Simulation time 103628129 ps
CPU time 2.85 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:55:58 PM PDT 24
Peak memory 208292 kb
Host smart-8c380e8c-79e4-46fd-97dd-f2afbf66c795
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804118578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.804118578
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3298635654
Short name T850
Test name
Test status
Simulation time 4844758158 ps
CPU time 5.89 seconds
Started Mar 31 03:56:05 PM PDT 24
Finished Mar 31 03:56:11 PM PDT 24
Peak memory 210264 kb
Host smart-24e9bc6a-6caa-44d2-b78a-2589541e16f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298635654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3298635654
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1929873695
Short name T438
Test name
Test status
Simulation time 180423433 ps
CPU time 7.01 seconds
Started Mar 31 03:55:56 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 208700 kb
Host smart-fdacf596-35c6-46b3-97a2-319264320d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929873695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1929873695
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.210762764
Short name T194
Test name
Test status
Simulation time 11334655682 ps
CPU time 58.71 seconds
Started Mar 31 03:55:51 PM PDT 24
Finished Mar 31 03:56:50 PM PDT 24
Peak memory 216320 kb
Host smart-202f10c8-6b50-42f9-a6e9-5667741c063e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210762764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.210762764
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.246051285
Short name T817
Test name
Test status
Simulation time 1245816840 ps
CPU time 12.86 seconds
Started Mar 31 03:56:04 PM PDT 24
Finished Mar 31 03:56:17 PM PDT 24
Peak memory 218672 kb
Host smart-09fc2490-4b01-4b66-a0b7-f538fe9b5c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246051285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.246051285
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2732441551
Short name T545
Test name
Test status
Simulation time 144071077 ps
CPU time 2.56 seconds
Started Mar 31 03:55:51 PM PDT 24
Finished Mar 31 03:55:54 PM PDT 24
Peak memory 210556 kb
Host smart-729e259a-0ca4-427c-8816-b7ea073281c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732441551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2732441551
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.109038850
Short name T726
Test name
Test status
Simulation time 86618713 ps
CPU time 0.86 seconds
Started Mar 31 03:56:09 PM PDT 24
Finished Mar 31 03:56:10 PM PDT 24
Peak memory 206188 kb
Host smart-87bef84f-cab1-4d70-a7c4-2834fa23539d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109038850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.109038850
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.520844461
Short name T380
Test name
Test status
Simulation time 273038739 ps
CPU time 2.6 seconds
Started Mar 31 03:55:57 PM PDT 24
Finished Mar 31 03:55:59 PM PDT 24
Peak memory 214688 kb
Host smart-f20e2aa3-b032-449b-be18-210ff0f3462b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520844461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.520844461
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3896785377
Short name T240
Test name
Test status
Simulation time 62977264 ps
CPU time 1.84 seconds
Started Mar 31 03:56:03 PM PDT 24
Finished Mar 31 03:56:05 PM PDT 24
Peak memory 221856 kb
Host smart-1bf09baf-c0b3-4a3e-a386-179317257d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896785377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3896785377
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.4287312611
Short name T666
Test name
Test status
Simulation time 651270252 ps
CPU time 4.67 seconds
Started Mar 31 03:55:59 PM PDT 24
Finished Mar 31 03:56:04 PM PDT 24
Peak memory 207788 kb
Host smart-8071aa84-faf1-4f02-a752-1d5f07627376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287312611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4287312611
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.394226502
Short name T812
Test name
Test status
Simulation time 1182152389 ps
CPU time 9.06 seconds
Started Mar 31 03:55:50 PM PDT 24
Finished Mar 31 03:55:59 PM PDT 24
Peak memory 222800 kb
Host smart-3f504b46-eb9e-4250-b58e-6bf3998bbffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394226502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.394226502
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3024638698
Short name T748
Test name
Test status
Simulation time 291003225 ps
CPU time 9.17 seconds
Started Mar 31 03:55:56 PM PDT 24
Finished Mar 31 03:56:06 PM PDT 24
Peak memory 222140 kb
Host smart-13b3fc2c-1180-468c-9ea2-8c5420017786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024638698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3024638698
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3209420146
Short name T612
Test name
Test status
Simulation time 87000286 ps
CPU time 3.07 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:55:58 PM PDT 24
Peak memory 221184 kb
Host smart-9b457126-3571-4f10-aa47-6055cd891e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209420146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3209420146
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.105258362
Short name T672
Test name
Test status
Simulation time 54068582 ps
CPU time 3.41 seconds
Started Mar 31 03:55:59 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 208424 kb
Host smart-f16caa25-ef51-4477-8935-1c5626222778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105258362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.105258362
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.681336749
Short name T604
Test name
Test status
Simulation time 60125132 ps
CPU time 3.07 seconds
Started Mar 31 03:56:06 PM PDT 24
Finished Mar 31 03:56:09 PM PDT 24
Peak memory 209096 kb
Host smart-f45d6d37-faeb-49e2-ac67-f11b77530b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681336749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.681336749
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3060948186
Short name T871
Test name
Test status
Simulation time 73337343 ps
CPU time 3.41 seconds
Started Mar 31 03:56:10 PM PDT 24
Finished Mar 31 03:56:14 PM PDT 24
Peak memory 208808 kb
Host smart-f6ab0203-9da8-47f3-9961-e185f95ef0a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060948186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3060948186
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2200501659
Short name T483
Test name
Test status
Simulation time 42406953 ps
CPU time 2.65 seconds
Started Mar 31 03:55:54 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 207116 kb
Host smart-3b0280c4-c045-4118-b5d0-05bf5abdcac5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200501659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2200501659
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.890159725
Short name T631
Test name
Test status
Simulation time 1318282777 ps
CPU time 31.9 seconds
Started Mar 31 03:56:14 PM PDT 24
Finished Mar 31 03:56:46 PM PDT 24
Peak memory 209096 kb
Host smart-ae1dc962-a1d8-46e0-8f89-91902d14c504
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890159725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.890159725
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2098260
Short name T655
Test name
Test status
Simulation time 274021221 ps
CPU time 2.92 seconds
Started Mar 31 03:55:54 PM PDT 24
Finished Mar 31 03:55:57 PM PDT 24
Peak memory 208828 kb
Host smart-40e7e49b-da54-49b8-9602-68934f045143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2098260
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.560405856
Short name T89
Test name
Test status
Simulation time 61648780 ps
CPU time 2.91 seconds
Started Mar 31 03:56:05 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 208056 kb
Host smart-fc3901ae-63f0-490b-a0f1-67696ecc6c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560405856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.560405856
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4058724811
Short name T57
Test name
Test status
Simulation time 2421968638 ps
CPU time 18.62 seconds
Started Mar 31 03:56:02 PM PDT 24
Finished Mar 31 03:56:21 PM PDT 24
Peak memory 219408 kb
Host smart-b9947720-c13f-4458-9df3-9f92965d7cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058724811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4058724811
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2231365942
Short name T756
Test name
Test status
Simulation time 50195413 ps
CPU time 3.43 seconds
Started Mar 31 03:56:02 PM PDT 24
Finished Mar 31 03:56:06 PM PDT 24
Peak memory 207736 kb
Host smart-ef6e3335-a0aa-41af-a856-cab2fedd7c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231365942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2231365942
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3629215108
Short name T568
Test name
Test status
Simulation time 83940272 ps
CPU time 2.84 seconds
Started Mar 31 03:56:07 PM PDT 24
Finished Mar 31 03:56:10 PM PDT 24
Peak memory 210652 kb
Host smart-00cea1fa-091a-47ef-8831-4ba20aa22069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629215108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3629215108
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2894295066
Short name T530
Test name
Test status
Simulation time 72093097 ps
CPU time 0.74 seconds
Started Mar 31 03:56:07 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 206352 kb
Host smart-38821e97-4ef0-4911-8a1d-e6b60f0ddcc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894295066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2894295066
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1681812944
Short name T420
Test name
Test status
Simulation time 67870521 ps
CPU time 4.64 seconds
Started Mar 31 03:56:02 PM PDT 24
Finished Mar 31 03:56:07 PM PDT 24
Peak memory 214700 kb
Host smart-b97b75e6-75f3-402f-a4aa-503b5519f83e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681812944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1681812944
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2657228939
Short name T177
Test name
Test status
Simulation time 1039173515 ps
CPU time 4.39 seconds
Started Mar 31 03:56:02 PM PDT 24
Finished Mar 31 03:56:07 PM PDT 24
Peak memory 218824 kb
Host smart-b8b51eee-cbd8-4748-835d-ce28b9cf385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657228939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2657228939
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3277111373
Short name T287
Test name
Test status
Simulation time 276411768 ps
CPU time 2.34 seconds
Started Mar 31 03:56:01 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 210192 kb
Host smart-9a827537-1049-442e-b5b6-9a016f8a8d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277111373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3277111373
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.350594911
Short name T313
Test name
Test status
Simulation time 138766130 ps
CPU time 5.3 seconds
Started Mar 31 03:55:55 PM PDT 24
Finished Mar 31 03:56:01 PM PDT 24
Peak memory 221172 kb
Host smart-6e2ab8a6-2a9e-46e9-9e50-af58ee993cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350594911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.350594911
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.943854697
Short name T310
Test name
Test status
Simulation time 870000632 ps
CPU time 10.37 seconds
Started Mar 31 03:56:03 PM PDT 24
Finished Mar 31 03:56:14 PM PDT 24
Peak memory 222852 kb
Host smart-a6e3d6d4-9c4f-406e-a6fe-0a4c1ed05240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943854697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.943854697
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2433919252
Short name T528
Test name
Test status
Simulation time 60569286 ps
CPU time 3.97 seconds
Started Mar 31 03:56:00 PM PDT 24
Finished Mar 31 03:56:04 PM PDT 24
Peak memory 210384 kb
Host smart-f9568419-ed1d-4997-9557-416dce2e13bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433919252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2433919252
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3856232436
Short name T303
Test name
Test status
Simulation time 216566001 ps
CPU time 3.01 seconds
Started Mar 31 03:56:10 PM PDT 24
Finished Mar 31 03:56:13 PM PDT 24
Peak memory 207188 kb
Host smart-33196a54-b9ef-492f-8e34-84150b03676a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856232436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3856232436
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1317888735
Short name T692
Test name
Test status
Simulation time 45676056 ps
CPU time 2.48 seconds
Started Mar 31 03:55:56 PM PDT 24
Finished Mar 31 03:55:59 PM PDT 24
Peak memory 207192 kb
Host smart-31735caf-87e6-4f72-bb04-6a949ef48318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317888735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1317888735
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2120160682
Short name T131
Test name
Test status
Simulation time 989947393 ps
CPU time 7.6 seconds
Started Mar 31 03:55:58 PM PDT 24
Finished Mar 31 03:56:06 PM PDT 24
Peak memory 208272 kb
Host smart-083b0cf0-01e6-453c-a71d-c670a0b0b0a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120160682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2120160682
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.411457454
Short name T617
Test name
Test status
Simulation time 151553616 ps
CPU time 4.91 seconds
Started Mar 31 03:56:03 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 208868 kb
Host smart-88eb74de-b0bd-4ae2-9465-3b86f89e6c83
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411457454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.411457454
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1942097709
Short name T543
Test name
Test status
Simulation time 230973079 ps
CPU time 3.04 seconds
Started Mar 31 03:56:11 PM PDT 24
Finished Mar 31 03:56:14 PM PDT 24
Peak memory 209428 kb
Host smart-2d34d630-8f73-436e-98d2-ad963348d032
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942097709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1942097709
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.422674825
Short name T900
Test name
Test status
Simulation time 1255814938 ps
CPU time 7.68 seconds
Started Mar 31 03:55:57 PM PDT 24
Finished Mar 31 03:56:05 PM PDT 24
Peak memory 218756 kb
Host smart-a77fcb61-3b5f-47fa-8c0c-1ffa15dbc4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422674825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.422674825
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3979368167
Short name T776
Test name
Test status
Simulation time 119523780 ps
CPU time 2.91 seconds
Started Mar 31 03:56:01 PM PDT 24
Finished Mar 31 03:56:04 PM PDT 24
Peak memory 208724 kb
Host smart-ccfb8c9e-ea7f-4f1d-82bd-eb9f3a065e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979368167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3979368167
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4282941004
Short name T718
Test name
Test status
Simulation time 5641087145 ps
CPU time 60.17 seconds
Started Mar 31 03:56:03 PM PDT 24
Finished Mar 31 03:57:04 PM PDT 24
Peak memory 214900 kb
Host smart-41e28741-d70a-487b-9eee-fac6fd6374db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282941004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4282941004
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3924270975
Short name T394
Test name
Test status
Simulation time 369069257 ps
CPU time 3.33 seconds
Started Mar 31 03:56:08 PM PDT 24
Finished Mar 31 03:56:11 PM PDT 24
Peak memory 210752 kb
Host smart-0e15e905-2cc7-44fa-97d7-2c5f644918de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924270975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3924270975
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1993634891
Short name T83
Test name
Test status
Simulation time 37447244 ps
CPU time 0.82 seconds
Started Mar 31 03:56:01 PM PDT 24
Finished Mar 31 03:56:02 PM PDT 24
Peak memory 206328 kb
Host smart-146e0ccd-940f-4ee7-bfcc-18b5f16a463e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993634891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1993634891
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3496623883
Short name T428
Test name
Test status
Simulation time 75952900 ps
CPU time 4.52 seconds
Started Mar 31 03:55:57 PM PDT 24
Finished Mar 31 03:56:02 PM PDT 24
Peak memory 216004 kb
Host smart-6360c259-fc5b-4999-9011-31ee72128659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496623883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3496623883
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2371559629
Short name T837
Test name
Test status
Simulation time 191993994 ps
CPU time 2.32 seconds
Started Mar 31 03:56:11 PM PDT 24
Finished Mar 31 03:56:13 PM PDT 24
Peak memory 210296 kb
Host smart-0e9a52d2-b5af-4d2c-9032-9a294439caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371559629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2371559629
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1819729347
Short name T835
Test name
Test status
Simulation time 54221829 ps
CPU time 2.9 seconds
Started Mar 31 03:56:01 PM PDT 24
Finished Mar 31 03:56:04 PM PDT 24
Peak memory 214624 kb
Host smart-2b6de56d-e156-4973-adff-3dc2e16a2d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819729347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1819729347
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.932142144
Short name T92
Test name
Test status
Simulation time 1383637345 ps
CPU time 17.89 seconds
Started Mar 31 03:56:04 PM PDT 24
Finished Mar 31 03:56:22 PM PDT 24
Peak memory 210376 kb
Host smart-aeca12ca-e38c-4bbc-b9b0-abdaa74df35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932142144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.932142144
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2329576862
Short name T762
Test name
Test status
Simulation time 1306952222 ps
CPU time 16.39 seconds
Started Mar 31 03:56:09 PM PDT 24
Finished Mar 31 03:56:25 PM PDT 24
Peak memory 211084 kb
Host smart-197be87b-7a05-465f-9552-6df7f5d74a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329576862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2329576862
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1018694743
Short name T47
Test name
Test status
Simulation time 289762942 ps
CPU time 3.78 seconds
Started Mar 31 03:56:03 PM PDT 24
Finished Mar 31 03:56:06 PM PDT 24
Peak memory 214684 kb
Host smart-a42c5a18-a1c3-4f29-96a5-5660c02b28af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018694743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1018694743
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.326629612
Short name T839
Test name
Test status
Simulation time 61298057 ps
CPU time 3.88 seconds
Started Mar 31 03:56:03 PM PDT 24
Finished Mar 31 03:56:07 PM PDT 24
Peak memory 210760 kb
Host smart-b1ba2fc2-abf8-4f7c-a8df-df5befd4f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326629612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.326629612
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1163465425
Short name T784
Test name
Test status
Simulation time 4244452331 ps
CPU time 28.09 seconds
Started Mar 31 03:56:06 PM PDT 24
Finished Mar 31 03:56:34 PM PDT 24
Peak memory 209452 kb
Host smart-c5d8f731-6649-4788-b319-b36100f12858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163465425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1163465425
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.4050908521
Short name T834
Test name
Test status
Simulation time 120547101 ps
CPU time 2.75 seconds
Started Mar 31 03:56:04 PM PDT 24
Finished Mar 31 03:56:07 PM PDT 24
Peak memory 207088 kb
Host smart-5787b382-bb50-4e46-b51e-a099f3ec871e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050908521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.4050908521
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2779618827
Short name T816
Test name
Test status
Simulation time 120325072 ps
CPU time 2.96 seconds
Started Mar 31 03:56:08 PM PDT 24
Finished Mar 31 03:56:11 PM PDT 24
Peak memory 209040 kb
Host smart-7a74c87f-2021-4ce6-bde0-646887b44a9c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779618827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2779618827
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.4170165267
Short name T856
Test name
Test status
Simulation time 90471780 ps
CPU time 3.31 seconds
Started Mar 31 03:56:07 PM PDT 24
Finished Mar 31 03:56:11 PM PDT 24
Peak memory 209096 kb
Host smart-abc660a0-ef92-426c-ac7d-15837ed77b59
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170165267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.4170165267
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4065050646
Short name T705
Test name
Test status
Simulation time 52561375 ps
CPU time 2.69 seconds
Started Mar 31 03:56:07 PM PDT 24
Finished Mar 31 03:56:10 PM PDT 24
Peak memory 207240 kb
Host smart-bbd65b70-14cb-4fa5-84ce-43081c52a016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065050646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4065050646
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2018328774
Short name T751
Test name
Test status
Simulation time 143000242 ps
CPU time 4.02 seconds
Started Mar 31 03:56:04 PM PDT 24
Finished Mar 31 03:56:08 PM PDT 24
Peak memory 208916 kb
Host smart-345bb728-4160-4a0e-b66b-b9e7086429b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018328774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2018328774
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2484158936
Short name T410
Test name
Test status
Simulation time 1471883859 ps
CPU time 31.14 seconds
Started Mar 31 03:56:06 PM PDT 24
Finished Mar 31 03:56:38 PM PDT 24
Peak memory 217192 kb
Host smart-c2a975ce-0a95-4231-9c7e-490257727304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484158936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2484158936
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.942181532
Short name T575
Test name
Test status
Simulation time 564359884 ps
CPU time 9.62 seconds
Started Mar 31 03:56:15 PM PDT 24
Finished Mar 31 03:56:25 PM PDT 24
Peak memory 220540 kb
Host smart-68e8d7af-569c-4d60-af2a-b438fe7da2d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942181532 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.942181532
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2105472393
Short name T311
Test name
Test status
Simulation time 2071190024 ps
CPU time 4.89 seconds
Started Mar 31 03:56:10 PM PDT 24
Finished Mar 31 03:56:15 PM PDT 24
Peak memory 209748 kb
Host smart-54358d6d-65bd-4f01-a53f-c68e6848aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105472393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2105472393
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1576103770
Short name T701
Test name
Test status
Simulation time 78555025 ps
CPU time 1.9 seconds
Started Mar 31 03:56:01 PM PDT 24
Finished Mar 31 03:56:03 PM PDT 24
Peak memory 210136 kb
Host smart-7cb0d0dc-fc97-434b-820d-da465a4ef369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576103770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1576103770
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3851967104
Short name T697
Test name
Test status
Simulation time 11991297 ps
CPU time 0.75 seconds
Started Mar 31 03:56:00 PM PDT 24
Finished Mar 31 03:56:01 PM PDT 24
Peak memory 206252 kb
Host smart-2ee3a661-4c7e-4878-ac4b-9c0648d9d15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851967104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3851967104
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.34198866
Short name T867
Test name
Test status
Simulation time 54723749 ps
CPU time 4.08 seconds
Started Mar 31 03:56:07 PM PDT 24
Finished Mar 31 03:56:11 PM PDT 24
Peak memory 214992 kb
Host smart-0b3bb7b8-cafa-4ab0-9487-88789445fbff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34198866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.34198866
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2294770809
Short name T820
Test name
Test status
Simulation time 130752557 ps
CPU time 2.44 seconds
Started Mar 31 03:56:12 PM PDT 24
Finished Mar 31 03:56:14 PM PDT 24
Peak memory 210348 kb
Host smart-0082b2b1-9619-4368-98d9-70eda126e42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294770809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2294770809
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3808166516
Short name T97
Test name
Test status
Simulation time 370879087 ps
CPU time 5.78 seconds
Started Mar 31 03:56:03 PM PDT 24
Finished Mar 31 03:56:09 PM PDT 24
Peak memory 214676 kb
Host smart-bb5b1d31-c330-4635-84bc-bf4e5282e311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808166516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3808166516
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.125422222
Short name T334
Test name
Test status
Simulation time 295272326 ps
CPU time 8.72 seconds
Started Mar 31 03:56:06 PM PDT 24
Finished Mar 31 03:56:14 PM PDT 24
Peak memory 222844 kb
Host smart-870301d2-9681-41fc-b62d-4d4d292c9d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125422222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.125422222
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2675954674
Short name T716
Test name
Test status
Simulation time 106935678 ps
CPU time 2.21 seconds
Started Mar 31 03:56:03 PM PDT 24
Finished Mar 31 03:56:05 PM PDT 24
Peak memory 208412 kb
Host smart-d4dd3f5d-4fb7-4e66-9ccd-3f1c95d0b2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675954674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2675954674
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1335723534
Short name T510
Test name
Test status
Simulation time 44098696 ps
CPU time 3.14 seconds
Started Mar 31 03:56:08 PM PDT 24
Finished Mar 31 03:56:12 PM PDT 24
Peak memory 214708 kb
Host smart-95fbd2a1-532f-43c4-820d-bbff4ca26f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335723534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1335723534
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.182537548
Short name T592
Test name
Test status
Simulation time 939292452 ps
CPU time 16.93 seconds
Started Mar 31 03:56:14 PM PDT 24
Finished Mar 31 03:56:31 PM PDT 24
Peak memory 208184 kb
Host smart-13e43b51-6ebc-44de-a9ec-2b11c8eb33fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182537548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.182537548
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.133471298
Short name T704
Test name
Test status
Simulation time 358171772 ps
CPU time 10.31 seconds
Started Mar 31 03:56:11 PM PDT 24
Finished Mar 31 03:56:21 PM PDT 24
Peak memory 209028 kb
Host smart-e1cca242-b8ea-4ed2-b597-93898b991203
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133471298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.133471298
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1324243340
Short name T745
Test name
Test status
Simulation time 151396228 ps
CPU time 2.86 seconds
Started Mar 31 03:56:11 PM PDT 24
Finished Mar 31 03:56:14 PM PDT 24
Peak memory 207948 kb
Host smart-493a1053-7bb0-4f06-9e1e-01f95ecfc972
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324243340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1324243340
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2790986700
Short name T778
Test name
Test status
Simulation time 32064576 ps
CPU time 2.12 seconds
Started Mar 31 03:56:08 PM PDT 24
Finished Mar 31 03:56:10 PM PDT 24
Peak memory 209112 kb
Host smart-cf35cde4-19f5-41ce-a323-9499958abce1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790986700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2790986700
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.606714954
Short name T890
Test name
Test status
Simulation time 126518670 ps
CPU time 3.67 seconds
Started Mar 31 03:56:12 PM PDT 24
Finished Mar 31 03:56:16 PM PDT 24
Peak memory 209796 kb
Host smart-0b0c41c8-d846-475c-8580-9dd158feefa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606714954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.606714954
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2553828587
Short name T466
Test name
Test status
Simulation time 358762233 ps
CPU time 4.96 seconds
Started Mar 31 03:56:06 PM PDT 24
Finished Mar 31 03:56:11 PM PDT 24
Peak memory 208416 kb
Host smart-4fd4f55a-ef06-4164-a343-f06a2e1684de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553828587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2553828587
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.113372109
Short name T259
Test name
Test status
Simulation time 1450834970 ps
CPU time 54.11 seconds
Started Mar 31 03:56:02 PM PDT 24
Finished Mar 31 03:56:56 PM PDT 24
Peak memory 217256 kb
Host smart-2af20b62-11c3-4e69-9316-a1a512fd2552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113372109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.113372109
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.4109308467
Short name T183
Test name
Test status
Simulation time 1320312381 ps
CPU time 12.52 seconds
Started Mar 31 03:56:06 PM PDT 24
Finished Mar 31 03:56:19 PM PDT 24
Peak memory 222960 kb
Host smart-6a900799-eb8a-4ae7-8c5b-945e5535ff02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109308467 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.4109308467
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3065698887
Short name T371
Test name
Test status
Simulation time 123661425 ps
CPU time 2.23 seconds
Started Mar 31 03:56:10 PM PDT 24
Finished Mar 31 03:56:12 PM PDT 24
Peak memory 208156 kb
Host smart-8b60742b-0f45-418d-9770-e21948630aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065698887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3065698887
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3782484027
Short name T393
Test name
Test status
Simulation time 290049096 ps
CPU time 2.63 seconds
Started Mar 31 03:56:12 PM PDT 24
Finished Mar 31 03:56:14 PM PDT 24
Peak memory 210492 kb
Host smart-b27334d8-c2e7-4359-b25d-4e4d577a6a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782484027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3782484027
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2162238853
Short name T493
Test name
Test status
Simulation time 45061865 ps
CPU time 0.76 seconds
Started Mar 31 03:54:10 PM PDT 24
Finished Mar 31 03:54:11 PM PDT 24
Peak memory 206332 kb
Host smart-aca9b77a-78ad-4239-a834-6df5881d5d18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162238853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2162238853
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1217027106
Short name T416
Test name
Test status
Simulation time 1733075719 ps
CPU time 94.68 seconds
Started Mar 31 03:54:09 PM PDT 24
Finished Mar 31 03:55:44 PM PDT 24
Peak memory 214800 kb
Host smart-2670155d-56ed-47d8-a4dc-1b31c94848d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217027106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1217027106
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1976150773
Short name T595
Test name
Test status
Simulation time 60804709 ps
CPU time 1.8 seconds
Started Mar 31 03:54:01 PM PDT 24
Finished Mar 31 03:54:05 PM PDT 24
Peak memory 207908 kb
Host smart-02334210-6561-4ad5-a1bc-33a135750b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976150773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1976150773
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.812541535
Short name T639
Test name
Test status
Simulation time 8842834954 ps
CPU time 84.57 seconds
Started Mar 31 03:54:16 PM PDT 24
Finished Mar 31 03:55:41 PM PDT 24
Peak memory 210096 kb
Host smart-f6bf0bbf-6b57-48d9-901e-4298c6f2aaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812541535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.812541535
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2950549114
Short name T743
Test name
Test status
Simulation time 554937300 ps
CPU time 5.95 seconds
Started Mar 31 03:54:25 PM PDT 24
Finished Mar 31 03:54:31 PM PDT 24
Peak memory 211116 kb
Host smart-7f20d9ae-8c2f-4c59-9efc-32db196e03f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950549114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2950549114
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.283228196
Short name T70
Test name
Test status
Simulation time 353775405 ps
CPU time 4.69 seconds
Started Mar 31 03:54:08 PM PDT 24
Finished Mar 31 03:54:13 PM PDT 24
Peak memory 210288 kb
Host smart-a914b268-4a49-485d-870c-d0ee36681d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283228196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.283228196
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2935049979
Short name T779
Test name
Test status
Simulation time 110842146 ps
CPU time 5.2 seconds
Started Mar 31 03:54:02 PM PDT 24
Finished Mar 31 03:54:09 PM PDT 24
Peak memory 218440 kb
Host smart-de0e0e02-20a3-4365-bcf2-2a83cd6ffb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935049979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2935049979
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2794214113
Short name T363
Test name
Test status
Simulation time 489952536 ps
CPU time 4.15 seconds
Started Mar 31 03:54:05 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 208856 kb
Host smart-7fb0b142-c0e4-4545-858f-29baa469912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794214113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2794214113
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4273003948
Short name T331
Test name
Test status
Simulation time 40430619 ps
CPU time 2.44 seconds
Started Mar 31 03:54:05 PM PDT 24
Finished Mar 31 03:54:09 PM PDT 24
Peak memory 207140 kb
Host smart-db39517e-242a-4e08-8e80-06e600f3a1a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273003948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4273003948
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2954035288
Short name T642
Test name
Test status
Simulation time 155983770 ps
CPU time 5.92 seconds
Started Mar 31 03:54:04 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 208960 kb
Host smart-e6248a26-a10a-4c7a-bbff-edfa3cbf5036
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954035288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2954035288
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2032590899
Short name T573
Test name
Test status
Simulation time 45117661 ps
CPU time 2.52 seconds
Started Mar 31 03:54:08 PM PDT 24
Finished Mar 31 03:54:11 PM PDT 24
Peak memory 207256 kb
Host smart-b3980413-8f07-485e-9de0-9e6afa81b6fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032590899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2032590899
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.661629192
Short name T241
Test name
Test status
Simulation time 51003233 ps
CPU time 2.07 seconds
Started Mar 31 03:54:14 PM PDT 24
Finished Mar 31 03:54:16 PM PDT 24
Peak memory 216048 kb
Host smart-09930590-3d35-44b6-bfd2-dccc31948fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661629192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.661629192
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1535489159
Short name T577
Test name
Test status
Simulation time 826355192 ps
CPU time 10.87 seconds
Started Mar 31 03:54:13 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 208276 kb
Host smart-468dea7f-c69a-4130-ad53-a01dcc05c649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535489159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1535489159
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3679349417
Short name T740
Test name
Test status
Simulation time 386743935 ps
CPU time 3.29 seconds
Started Mar 31 03:54:02 PM PDT 24
Finished Mar 31 03:54:07 PM PDT 24
Peak memory 216612 kb
Host smart-a9ec636c-5870-4e81-89ca-29d0c6269ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679349417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3679349417
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2094837161
Short name T481
Test name
Test status
Simulation time 16573292 ps
CPU time 0.74 seconds
Started Mar 31 03:54:09 PM PDT 24
Finished Mar 31 03:54:10 PM PDT 24
Peak memory 206340 kb
Host smart-5bfd67f2-cdbc-47a7-87de-ef2decc81b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094837161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2094837161
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2563462726
Short name T426
Test name
Test status
Simulation time 241950444 ps
CPU time 4.34 seconds
Started Mar 31 03:54:01 PM PDT 24
Finished Mar 31 03:54:06 PM PDT 24
Peak memory 214704 kb
Host smart-a06a2619-1d46-4340-88ce-f30f66201bac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2563462726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2563462726
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2625880933
Short name T549
Test name
Test status
Simulation time 121921747 ps
CPU time 4.82 seconds
Started Mar 31 03:54:15 PM PDT 24
Finished Mar 31 03:54:20 PM PDT 24
Peak memory 210476 kb
Host smart-d557716e-f690-4244-83fb-8ecde0a43c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625880933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2625880933
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.289583238
Short name T651
Test name
Test status
Simulation time 40793509 ps
CPU time 1.71 seconds
Started Mar 31 03:54:17 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 214724 kb
Host smart-bd38e468-1b1a-4cab-b8b2-6b88552f305c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289583238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.289583238
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3905128113
Short name T90
Test name
Test status
Simulation time 110599101 ps
CPU time 4.81 seconds
Started Mar 31 03:54:20 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 214748 kb
Host smart-dba130d8-cc71-4704-9f6b-a570d7b776e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905128113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3905128113
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2257858836
Short name T702
Test name
Test status
Simulation time 120333890 ps
CPU time 3.85 seconds
Started Mar 31 03:54:29 PM PDT 24
Finished Mar 31 03:54:33 PM PDT 24
Peak memory 220604 kb
Host smart-f11a59d0-a337-4b26-9a02-04da01ddc25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257858836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2257858836
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.133534199
Short name T486
Test name
Test status
Simulation time 207307819 ps
CPU time 4.51 seconds
Started Mar 31 03:54:11 PM PDT 24
Finished Mar 31 03:54:16 PM PDT 24
Peak memory 207908 kb
Host smart-c22e0c9f-0141-4dd1-9849-06f35658e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133534199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.133534199
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.269999026
Short name T727
Test name
Test status
Simulation time 36266205 ps
CPU time 2.43 seconds
Started Mar 31 03:54:04 PM PDT 24
Finished Mar 31 03:54:07 PM PDT 24
Peak memory 207088 kb
Host smart-78be55b0-141b-4aaf-b4cc-b2144812058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269999026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.269999026
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.535229138
Short name T583
Test name
Test status
Simulation time 254824214 ps
CPU time 6.83 seconds
Started Mar 31 03:54:03 PM PDT 24
Finished Mar 31 03:54:11 PM PDT 24
Peak memory 209160 kb
Host smart-c267b874-5c85-4482-99ba-e0a6a03393fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535229138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.535229138
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2682405887
Short name T494
Test name
Test status
Simulation time 66234827 ps
CPU time 2.51 seconds
Started Mar 31 03:54:13 PM PDT 24
Finished Mar 31 03:54:15 PM PDT 24
Peak memory 207160 kb
Host smart-19804deb-f313-4618-8fce-b5f19a500328
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682405887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2682405887
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4174501507
Short name T853
Test name
Test status
Simulation time 97642634 ps
CPU time 3.38 seconds
Started Mar 31 03:54:12 PM PDT 24
Finished Mar 31 03:54:16 PM PDT 24
Peak memory 207228 kb
Host smart-9d8cb057-1dae-4d08-9cad-305af6c9d3bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174501507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4174501507
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.837539685
Short name T667
Test name
Test status
Simulation time 31108674 ps
CPU time 2.41 seconds
Started Mar 31 03:54:09 PM PDT 24
Finished Mar 31 03:54:12 PM PDT 24
Peak memory 209788 kb
Host smart-515f0adf-29e1-4b8b-94c9-61c7708daae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837539685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.837539685
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.719331990
Short name T561
Test name
Test status
Simulation time 278229680 ps
CPU time 3.62 seconds
Started Mar 31 03:54:21 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 207844 kb
Host smart-884b3b2f-f852-4c44-85a2-0ce8d94378a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719331990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.719331990
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2516692549
Short name T192
Test name
Test status
Simulation time 5474123268 ps
CPU time 22.88 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:49 PM PDT 24
Peak memory 220996 kb
Host smart-20b81168-70d4-4211-a638-d2de518255d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516692549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2516692549
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2021720981
Short name T796
Test name
Test status
Simulation time 777913942 ps
CPU time 5.94 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 210028 kb
Host smart-6040a7fd-d269-481e-9daf-fcc6faade754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021720981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2021720981
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2476615224
Short name T679
Test name
Test status
Simulation time 43348435 ps
CPU time 2.19 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:21 PM PDT 24
Peak memory 209744 kb
Host smart-74658183-d1f4-4f07-bc6a-a6e6e3851663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476615224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2476615224
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2436056872
Short name T891
Test name
Test status
Simulation time 40282741 ps
CPU time 0.75 seconds
Started Mar 31 03:54:22 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 206316 kb
Host smart-8ba0be98-3984-490a-9ab6-a5f363732a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436056872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2436056872
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.811173776
Short name T875
Test name
Test status
Simulation time 413437536 ps
CPU time 3.02 seconds
Started Mar 31 03:54:18 PM PDT 24
Finished Mar 31 03:54:21 PM PDT 24
Peak memory 208036 kb
Host smart-ff012f02-6b95-4543-bc0a-6294e96cd5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811173776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.811173776
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1079302256
Short name T783
Test name
Test status
Simulation time 56672019 ps
CPU time 2.99 seconds
Started Mar 31 03:54:13 PM PDT 24
Finished Mar 31 03:54:16 PM PDT 24
Peak memory 209908 kb
Host smart-f107c09f-b23b-4e0c-aa92-257a0ee4fc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079302256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1079302256
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3434317739
Short name T805
Test name
Test status
Simulation time 1030156500 ps
CPU time 5.18 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:28 PM PDT 24
Peak memory 209964 kb
Host smart-384343aa-c65a-456f-af94-187f15879253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434317739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3434317739
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3424520825
Short name T538
Test name
Test status
Simulation time 7064287401 ps
CPU time 23.04 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:46 PM PDT 24
Peak memory 209712 kb
Host smart-ecc655ab-b4d0-4d7a-9714-b8940b9f193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424520825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3424520825
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2657714313
Short name T206
Test name
Test status
Simulation time 116863919 ps
CPU time 3.33 seconds
Started Mar 31 03:54:21 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 208812 kb
Host smart-25cf57e4-7552-415c-b815-dc555e66e1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657714313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2657714313
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1703560518
Short name T657
Test name
Test status
Simulation time 5330611568 ps
CPU time 32.95 seconds
Started Mar 31 03:54:17 PM PDT 24
Finished Mar 31 03:54:51 PM PDT 24
Peak memory 209492 kb
Host smart-78ababa5-1e84-4249-82be-3bad839770cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703560518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1703560518
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2090233282
Short name T880
Test name
Test status
Simulation time 10388446248 ps
CPU time 44.47 seconds
Started Mar 31 03:54:17 PM PDT 24
Finished Mar 31 03:55:01 PM PDT 24
Peak memory 209252 kb
Host smart-3f913a0e-5420-46e1-b7da-248ac3c25719
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090233282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2090233282
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1673752195
Short name T724
Test name
Test status
Simulation time 40966039 ps
CPU time 2.82 seconds
Started Mar 31 03:54:15 PM PDT 24
Finished Mar 31 03:54:18 PM PDT 24
Peak memory 208940 kb
Host smart-8d557f8e-e68a-462f-9cf7-418d03f6eca1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673752195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1673752195
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3342070421
Short name T703
Test name
Test status
Simulation time 108543952 ps
CPU time 3.79 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 210160 kb
Host smart-88c968cc-855a-4a27-9e77-92c14a945b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342070421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3342070421
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1226581944
Short name T482
Test name
Test status
Simulation time 69822950 ps
CPU time 2.48 seconds
Started Mar 31 03:54:26 PM PDT 24
Finished Mar 31 03:54:28 PM PDT 24
Peak memory 206928 kb
Host smart-c70a55a6-6730-4ea5-b34c-5a924e72c253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226581944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1226581944
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1913622798
Short name T763
Test name
Test status
Simulation time 338281049 ps
CPU time 9.07 seconds
Started Mar 31 03:54:14 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 215356 kb
Host smart-b718bfe3-a7a1-4f10-8137-23365a68d100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913622798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1913622798
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3185738256
Short name T225
Test name
Test status
Simulation time 1029681956 ps
CPU time 27.04 seconds
Started Mar 31 03:54:18 PM PDT 24
Finished Mar 31 03:54:45 PM PDT 24
Peak memory 223240 kb
Host smart-474521c8-e654-454f-ab8a-07b6296e2056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185738256 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3185738256
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.4070953759
Short name T302
Test name
Test status
Simulation time 165027313 ps
CPU time 4.36 seconds
Started Mar 31 03:54:11 PM PDT 24
Finished Mar 31 03:54:16 PM PDT 24
Peak memory 208276 kb
Host smart-99793738-dff0-411c-bf9f-5a7e9f7b04da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070953759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.4070953759
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1849558340
Short name T168
Test name
Test status
Simulation time 69783263 ps
CPU time 1.54 seconds
Started Mar 31 03:54:14 PM PDT 24
Finished Mar 31 03:54:15 PM PDT 24
Peak memory 210184 kb
Host smart-dcf03124-494c-4672-ab5a-ec3d360c7a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849558340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1849558340
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2738852198
Short name T452
Test name
Test status
Simulation time 14566883 ps
CPU time 0.74 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:20 PM PDT 24
Peak memory 206200 kb
Host smart-7a8953b1-202b-4637-bf0c-573ec3e2bf9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738852198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2738852198
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3727974599
Short name T282
Test name
Test status
Simulation time 79505676 ps
CPU time 3.05 seconds
Started Mar 31 03:54:22 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 215888 kb
Host smart-8aa93179-b84b-4856-964b-cfc3926bfcb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3727974599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3727974599
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3195962956
Short name T516
Test name
Test status
Simulation time 81266760 ps
CPU time 3.56 seconds
Started Mar 31 03:54:25 PM PDT 24
Finished Mar 31 03:54:29 PM PDT 24
Peak memory 209516 kb
Host smart-897b41d2-f48f-4cab-8438-254401622c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195962956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3195962956
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2870666574
Short name T445
Test name
Test status
Simulation time 27448357 ps
CPU time 1.71 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:21 PM PDT 24
Peak memory 207780 kb
Host smart-c2d30dc6-7e59-4253-bb0d-2e4726b7f5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870666574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2870666574
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1483622324
Short name T614
Test name
Test status
Simulation time 583282958 ps
CPU time 5.21 seconds
Started Mar 31 03:54:12 PM PDT 24
Finished Mar 31 03:54:17 PM PDT 24
Peak memory 209796 kb
Host smart-76dfbdbe-386b-4c2b-bf77-3f63f08579d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483622324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1483622324
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.542338082
Short name T247
Test name
Test status
Simulation time 104864704 ps
CPU time 5.07 seconds
Started Mar 31 03:54:11 PM PDT 24
Finished Mar 31 03:54:16 PM PDT 24
Peak memory 210064 kb
Host smart-31535cf1-1c74-47bc-9ea8-8cf18ad17917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542338082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.542338082
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3868289614
Short name T750
Test name
Test status
Simulation time 233740898 ps
CPU time 6.62 seconds
Started Mar 31 03:54:08 PM PDT 24
Finished Mar 31 03:54:15 PM PDT 24
Peak memory 222904 kb
Host smart-81dc3cda-c662-4f83-840e-2551dacf06d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868289614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3868289614
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1488031842
Short name T18
Test name
Test status
Simulation time 123032233 ps
CPU time 2.27 seconds
Started Mar 31 03:54:15 PM PDT 24
Finished Mar 31 03:54:17 PM PDT 24
Peak memory 207440 kb
Host smart-250d0feb-4522-4efa-9fb1-8ffc6d33b734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488031842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1488031842
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3903274413
Short name T203
Test name
Test status
Simulation time 2151738744 ps
CPU time 40.66 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:55:00 PM PDT 24
Peak memory 208592 kb
Host smart-6b6dc17a-5f66-4f44-87af-87ed8f056e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903274413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3903274413
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1185432236
Short name T188
Test name
Test status
Simulation time 5933222662 ps
CPU time 28.99 seconds
Started Mar 31 03:54:30 PM PDT 24
Finished Mar 31 03:54:59 PM PDT 24
Peak memory 208304 kb
Host smart-6e5289f0-093e-4d2e-a062-612574d4d2f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185432236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1185432236
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3492053972
Short name T857
Test name
Test status
Simulation time 3443796412 ps
CPU time 38.77 seconds
Started Mar 31 03:54:15 PM PDT 24
Finished Mar 31 03:54:54 PM PDT 24
Peak memory 208852 kb
Host smart-8c588f2b-0207-4488-9d62-33ec1dfadcc2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492053972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3492053972
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2874827837
Short name T217
Test name
Test status
Simulation time 107473566 ps
CPU time 2.33 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 209352 kb
Host smart-365098a4-ea4f-415e-9e0c-84996e2ae68d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874827837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2874827837
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1738953963
Short name T211
Test name
Test status
Simulation time 102560393 ps
CPU time 3.96 seconds
Started Mar 31 03:54:21 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 214672 kb
Host smart-1cae5571-952e-4b1b-838d-d067794ede99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738953963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1738953963
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1918687131
Short name T736
Test name
Test status
Simulation time 123376565 ps
CPU time 2.91 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:26 PM PDT 24
Peak memory 207076 kb
Host smart-f1906ffa-e9ce-4afc-9e39-effe9fd0a56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918687131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1918687131
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1471527566
Short name T231
Test name
Test status
Simulation time 7345775004 ps
CPU time 48.58 seconds
Started Mar 31 03:54:12 PM PDT 24
Finished Mar 31 03:55:01 PM PDT 24
Peak memory 222792 kb
Host smart-927c49bf-3a94-4b0e-8f6d-6818fd3e08e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471527566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1471527566
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1909517882
Short name T181
Test name
Test status
Simulation time 558396297 ps
CPU time 6.16 seconds
Started Mar 31 03:54:15 PM PDT 24
Finished Mar 31 03:54:22 PM PDT 24
Peak memory 223028 kb
Host smart-d52dd4a1-da95-424b-8381-7ea9df069990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909517882 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1909517882
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.4125861148
Short name T343
Test name
Test status
Simulation time 593071143 ps
CPU time 8.06 seconds
Started Mar 31 03:54:14 PM PDT 24
Finished Mar 31 03:54:22 PM PDT 24
Peak memory 208564 kb
Host smart-e75577a2-43e5-4ee8-b4f9-728fc3f68ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125861148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.4125861148
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1684505765
Short name T695
Test name
Test status
Simulation time 98941789 ps
CPU time 3.05 seconds
Started Mar 31 03:54:18 PM PDT 24
Finished Mar 31 03:54:26 PM PDT 24
Peak memory 211132 kb
Host smart-6c5bf4d2-c47b-441f-b13b-10f554a0f911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684505765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1684505765
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1336984039
Short name T602
Test name
Test status
Simulation time 53685414 ps
CPU time 0.88 seconds
Started Mar 31 03:54:20 PM PDT 24
Finished Mar 31 03:54:21 PM PDT 24
Peak memory 206340 kb
Host smart-53a55b75-6e9f-4027-a69b-301b701a737c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336984039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1336984039
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.4214520714
Short name T425
Test name
Test status
Simulation time 101624386 ps
CPU time 2.35 seconds
Started Mar 31 03:54:28 PM PDT 24
Finished Mar 31 03:54:30 PM PDT 24
Peak memory 214716 kb
Host smart-eb0b6250-26b3-404f-a5ca-1c40a94b20c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4214520714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4214520714
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1861871029
Short name T113
Test name
Test status
Simulation time 442555317 ps
CPU time 4.63 seconds
Started Mar 31 03:54:28 PM PDT 24
Finished Mar 31 03:54:33 PM PDT 24
Peak memory 218784 kb
Host smart-f93960b7-29dc-4ff2-bcfe-e821772e571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861871029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1861871029
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.553552069
Short name T91
Test name
Test status
Simulation time 195574644 ps
CPU time 3.61 seconds
Started Mar 31 03:54:20 PM PDT 24
Finished Mar 31 03:54:24 PM PDT 24
Peak memory 209888 kb
Host smart-352d120b-1359-4e37-b467-6566af5733e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553552069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.553552069
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3321494902
Short name T71
Test name
Test status
Simulation time 260113554 ps
CPU time 4.51 seconds
Started Mar 31 03:54:19 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 222564 kb
Host smart-060c2ff3-0ca3-4431-9718-7f7c8011f5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321494902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3321494902
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3703547322
Short name T735
Test name
Test status
Simulation time 224257940 ps
CPU time 6.58 seconds
Started Mar 31 03:54:27 PM PDT 24
Finished Mar 31 03:54:33 PM PDT 24
Peak memory 208184 kb
Host smart-145e4d2a-502b-4c29-a11f-16acc6fdcb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703547322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3703547322
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.22044678
Short name T594
Test name
Test status
Simulation time 151374963 ps
CPU time 3.51 seconds
Started Mar 31 03:54:20 PM PDT 24
Finished Mar 31 03:54:23 PM PDT 24
Peak memory 209000 kb
Host smart-fbda62bd-a726-4f60-aa68-3575d52da4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22044678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.22044678
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3812568594
Short name T689
Test name
Test status
Simulation time 307559424 ps
CPU time 3.71 seconds
Started Mar 31 03:54:22 PM PDT 24
Finished Mar 31 03:54:25 PM PDT 24
Peak memory 209124 kb
Host smart-c895c5bb-56be-4c77-8d48-0705825b3c35
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812568594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3812568594
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.589221432
Short name T598
Test name
Test status
Simulation time 301469787 ps
CPU time 3.24 seconds
Started Mar 31 03:54:13 PM PDT 24
Finished Mar 31 03:54:17 PM PDT 24
Peak memory 207148 kb
Host smart-6e7cc5e8-7582-4060-8fd0-9cc40b880d87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589221432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.589221432
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1028487618
Short name T654
Test name
Test status
Simulation time 67131362 ps
CPU time 2.66 seconds
Started Mar 31 03:54:14 PM PDT 24
Finished Mar 31 03:54:17 PM PDT 24
Peak memory 207152 kb
Host smart-1a4982f8-b03a-40ee-8375-6287de0e9cc6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028487618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1028487618
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.500345872
Short name T824
Test name
Test status
Simulation time 123099295 ps
CPU time 2.31 seconds
Started Mar 31 03:54:14 PM PDT 24
Finished Mar 31 03:54:16 PM PDT 24
Peak memory 218668 kb
Host smart-3720c8ed-e439-4680-86e4-9edafcb309cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500345872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.500345872
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.4199300013
Short name T405
Test name
Test status
Simulation time 95675061 ps
CPU time 2.92 seconds
Started Mar 31 03:54:09 PM PDT 24
Finished Mar 31 03:54:13 PM PDT 24
Peak memory 207288 kb
Host smart-3c79cf37-0b75-4a6a-ba80-f2b831db550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199300013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.4199300013
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2956720224
Short name T368
Test name
Test status
Simulation time 1236098237 ps
CPU time 31.78 seconds
Started Mar 31 03:54:23 PM PDT 24
Finished Mar 31 03:54:55 PM PDT 24
Peak memory 222776 kb
Host smart-61fdaddd-0c54-4551-b8d9-f61b750f9c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956720224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2956720224
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.168249113
Short name T277
Test name
Test status
Simulation time 1083863788 ps
CPU time 22.71 seconds
Started Mar 31 03:54:20 PM PDT 24
Finished Mar 31 03:54:43 PM PDT 24
Peak memory 223100 kb
Host smart-1835b824-1e93-4491-95c9-7616804d55bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168249113 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.168249113
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2269807003
Short name T626
Test name
Test status
Simulation time 174199400 ps
CPU time 4.77 seconds
Started Mar 31 03:54:30 PM PDT 24
Finished Mar 31 03:54:35 PM PDT 24
Peak memory 207888 kb
Host smart-959c77b8-5ce2-463f-a481-260edf2c9636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269807003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2269807003
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.535502653
Short name T64
Test name
Test status
Simulation time 420075287 ps
CPU time 4.1 seconds
Started Mar 31 03:54:16 PM PDT 24
Finished Mar 31 03:54:20 PM PDT 24
Peak memory 210668 kb
Host smart-e2690dab-23ae-4de8-a304-f0db8c92b758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535502653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.535502653
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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