Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	47	1			T38	1		T39	1		T40	1
auto[OpGenId]	13	1			T23	1		T63	1		T249	2
auto[OpGenSwOut]	16	1			T47	1		T67	1		T250	1
auto[OpGenHwOut]	22	1			T6	1		T7	1		T41	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1815	1			T5	90		T105	2		T47	1
auto[StInit]	79	1			T13	1		T17	1		T44	1
auto[StCreatorRootKey]	51	1			T47	1		T52	1		T53	1
auto[StOwnerIntKey]	43	1			T54	1		T55	1		T56	1
auto[StOwnerKey]	28	1			T60	1		T63	2		T64	1
auto[StDisabled]	422	1			T34	8		T160	1		T105	2
auto[StInvalid]	43	1			T3	1		T30	1		T31	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3446

1

T1

1

T2

1

T3

2

auto[1]

98

1

T6

1

T47

1

T38

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1811	1			T5	90		T105	2		T47	1
auto[StReset]	auto[1]	4	1			T23	1		T45	1		T251	1
auto[StInit]	auto[0]	35	1			T13	1		T17	1		T44	1
auto[StInit]	auto[1]	44	1			T6	1		T38	1		T39	1
auto[StCreatorRootKey]	auto[0]	31	1			T50	1		T73	1		T51	1
auto[StCreatorRootKey]	auto[1]	20	1			T47	1		T52	1		T53	1
auto[StOwnerIntKey]	auto[0]	31	1			T54	1		T55	1		T56	1
auto[StOwnerIntKey]	auto[1]	12	1			T63	1		T219	1		T252	1
auto[StOwnerKey]	auto[0]	22	1			T60	1		T64	1		T61	1
auto[StOwnerKey]	auto[1]	6	1			T63	2		T65	1		T222	1
auto[StDisabled]	auto[0]	410	1			T34	8		T160	1		T105	2
auto[StDisabled]	auto[1]	12	1			T67	1		T253	1		T63	1
auto[StInvalid]	auto[0]	43	1			T3	1		T30	1		T31	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	3
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	3	1			T45	1		T251	1		T46	1
auto[StReset]	auto[OpGenId]	1	1			T23	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	21	1			T38	1		T39	1		T40	1
auto[StInit]	auto[OpGenId]	6	1			T249	1		T254	1		T209	1
auto[StInit]	auto[OpGenSwOut]	6	1			T255	1		T256	1		T125	1
auto[StInit]	auto[OpGenHwOut]	11	1			T6	1		T7	1		T41	1
auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T52	1		T53	1		T41	1
auto[StCreatorRootKey]	auto[OpGenId]	4	1			T249	1		T257	1		T204	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T47	1		T250	1		T258	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	3	1			T259	1		T260	1		T261	1
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T63	1		T219	1		T262	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T201	1		T209	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	6	1			T252	1		T155	1		T263	1
auto[StOwnerKey]	auto[OpAdvance]	3	1			T63	1		T65	1		T264	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T265	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T222	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T63	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	7	1			T253	1		T140	1		T266	1
auto[StDisabled]	auto[OpGenId]	1	1			T63	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T67	1		T267	1		T268	1
auto[StDisabled]	auto[OpGenHwOut]	1	1			T269	1		-	-		-	-