Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11381

1

T1

6

T3

22

T4

13

auto[Attestation]

8144

1

T1

6

T3

11

T4

13

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2920	1			T1	1		T3	10		T4	1
auto[Aes]	3444	1			T1	2		T3	4		T4	4
auto[Kmac]	3405	1			T1	4		T3	2		T4	4
auto[Otbn]	3533	1			T1	1		T3	4		T4	6

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7853	1			T1	8		T3	8		T4	8
auto[OpGenId]	6223	1			T1	4		T3	13		T4	11
auto[OpGenSwOut]	6081	1			T1	4		T3	4		T4	8
auto[OpGenHwOut]	7221	1			T1	4		T3	16		T4	7
auto[OpDisable]	133	1			T34	4		T42	1		T43	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10203

1

T1

1

T3

1

T4

12

auto[OpDoneFail]

17308

1

T1

19

T3

40

T4

22

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6413	1			T1	1		T3	19		T4	1
auto[StInit]	4234	1			T1	19		T3	2		T4	6
auto[StCreatorRootKey]	3075	1			T4	2		T14	1		T15	2
auto[StOwnerIntKey]	2618	1			T4	4		T14	1		T15	2
auto[StOwnerKey]	2394	1			T4	4		T14	4		T15	2
auto[StDisabled]	7714	1			T4	17		T14	15		T15	7
auto[StInvalid]	1063	1			T3	20		T30	21		T31	26

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	323	1			T17	1		T37	1		T21	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	127	1			T16	1		T21	1		T225	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T37	1		T160	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T34	1		T38	1		T49	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	65	1			T38	3		T226	1		T227	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	188	1			T14	1		T34	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	31	1			T30	1		T228	1		T229	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	322	1			T37	1		T105	2		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	117	1			T4	1		T88	1		T21	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	81	1			T38	1		T230	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	62	1			T34	1		T231	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	56	1			T4	1		T88	1		T49	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	182	1			T14	1		T18	1		T232	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T228	2		T233	2		T234	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	312	1			T232	1		T89	1		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T1	1		T34	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	70	1			T34	1		T89	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T38	4		T49	1		T230	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	64	1			T18	1		T88	1		T235	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	186	1			T4	1		T34	2		T236	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T31	1		T229	2		T237	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	311	1			T37	1		T34	1		T21	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	105	1			T37	1		T34	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T34	1		T105	1		T43	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T38	1		T49	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	56	1			T232	1		T38	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	227	1			T14	1		T87	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	36	1			T3	1		T30	1		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	79	1			T38	1		T49	1		T69	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	130	1			T1	1		T44	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T49	5		T238	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	69	1			T37	1		T34	2		T232	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T88	1		T105	1		T38	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	223	1			T4	1		T14	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	29	1			T30	2		T31	2		T233	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	90	1			T3	1		T34	2		T49	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	136	1			T1	1		T3	1		T34	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	57	1			T42	1		T105	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	58	1			T18	1		T105	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	68	1			T4	1		T14	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	193	1			T4	1		T18	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	37	1			T3	1		T30	2		T228	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T34	1		T38	4		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	124	1			T1	1		T34	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T4	1		T18	1		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	64	1			T42	1		T38	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	66	1			T34	1		T239	1		T240	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	222	1			T18	1		T34	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	23	1			T228	1		T234	1		T241	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	67	1			T38	2		T233	1		T41	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	109	1			T4	1		T34	1		T38	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T87	1		T231	1		T38	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T34	1		T49	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	64	1			T14	1		T34	1		T105	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	215	1			T34	3		T87	1		T232	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T30	2		T228	1		T233	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	305	1			T3	3		T21	1		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T34	1		T21	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	67	1			T34	2		T89	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T34	2		T35	1		T242	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	51	1			T34	1		T38	1		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	185	1			T34	1		T231	1		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	31	1			T3	3		T31	1		T228	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	467	1			T34	1		T21	1		T236	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	134	1			T1	1		T14	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	130	1			T16	1		T35	1		T243	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	94	1			T106	1		T243	1		T38	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	66	1			T34	1		T106	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	273	1			T34	1		T87	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T3	1		T31	2		T228	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	431	1			T231	1		T89	2		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	122	1			T1	1		T88	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	104	1			T34	1		T244	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T34	1		T244	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	76	1			T14	1		T34	1		T232	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	260	1			T4	1		T244	3		T35	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	27	1			T30	1		T228	1		T229	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	466	1			T3	2		T15	12		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	139	1			T1	1		T15	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	126	1			T15	1		T108	1		T242	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T4	1		T88	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T15	1		T34	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	298	1			T4	2		T15	2		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	32	1			T31	1		T237	2		T245	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	65	1			T3	2		T34	2		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	117	1			T16	1		T34	2		T232	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	65	1			T38	1		T49	3		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	59	1			T34	1		T232	1		T246	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	44	1			T34	1		T242	1		T231	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	168	1			T14	1		T16	1		T34	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	41	1			T3	2		T30	1		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	71	1			T34	1		T38	1		T233	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T106	1		T44	1		T247	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	114	1			T16	1		T34	1		T106	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	73	1			T236	1		T35	1		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	79	1			T232	1		T242	2		T243	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	279	1			T16	1		T34	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	24	1			T31	1		T228	1		T229	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	59	1			T3	2		T34	3		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	126	1			T1	1		T13	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	107	1			T34	2		T247	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T16	1		T49	1		T248	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	68	1			T34	1		T236	1		T49	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	304	1			T4	1		T14	2		T34	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	39	1			T30	1		T31	2		T233	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	74	1			T38	1		T69	3		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	129	1			T4	1		T21	2		T242	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	107	1			T34	2		T247	2		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T15	1		T108	1		T242	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	80	1			T34	1		T108	1		T38	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	264	1			T4	1		T14	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	34	1			T3	1		T228	2		T233	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	199	1			T37	1		T34	1		T160	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	687	1			T14	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	177	1			T4	1		T34	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	675	1			T4	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	198	1			T18	1		T34	1		T88	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	652	1			T1	1		T4	1		T34	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T34	1		T232	1		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	685	1			T3	1		T14	1		T37	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	194	1			T37	1		T34	2		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	479	1			T1	1		T4	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	163	1			T4	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	476	1			T1	1		T3	3		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	189	1			T4	1		T18	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	468	1			T1	1		T18	1		T34	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T14	1		T34	2		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	446	1			T4	1		T34	4		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	169	1			T34	5		T35	1		T242	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	633	1			T3	6		T34	2		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	267	1			T16	1		T34	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	929	1			T1	1		T3	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	256	1			T14	1		T34	3		T232	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	851	1			T1	1		T4	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	285	1			T4	1		T15	2		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	953	1			T1	1		T3	2		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	159	1			T34	2		T232	1		T242	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	400	1			T3	4		T14	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	255	1			T16	1		T34	1		T236	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	502	1			T16	1		T34	2		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	248	1			T16	1		T34	3		T236	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	543	1			T1	1		T3	2		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	256	1			T15	1		T34	3		T108	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	515	1			T3	1		T4	2		T14	1