Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31534

1

T1

25

T3

43

T4

38

auto[1]

282

1

T14

11

T115

6

T150

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31546	1			T1	25		T3	43		T4	38
auto[134217728:268435455]	11	1			T115	1		T139	1		T408	1
auto[268435456:402653183]	9	1			T394	1		T306	1		T145	1
auto[402653184:536870911]	7	1			T394	1		T306	1		T379	1
auto[536870912:671088639]	11	1			T14	1		T141	1		T143	1
auto[671088640:805306367]	9	1			T394	1		T141	1		T144	2
auto[805306368:939524095]	8	1			T14	1		T150	1		T394	1
auto[939524096:1073741823]	5	1			T306	1		T145	1		T404	1
auto[1073741824:1207959551]	13	1			T141	1		T142	1		T143	1
auto[1207959552:1342177279]	7	1			T14	1		T150	1		T408	1
auto[1342177280:1476395007]	11	1			T144	1		T379	1		T404	1
auto[1476395008:1610612735]	5	1			T14	1		T306	1		T421	1
auto[1610612736:1744830463]	5	1			T144	1		T422	1		T341	1
auto[1744830464:1879048191]	10	1			T150	2		T144	1		T408	1
auto[1879048192:2013265919]	15	1			T139	2		T394	1		T379	2
auto[2013265920:2147483647]	9	1			T14	2		T142	1		T408	1
auto[2147483648:2281701375]	8	1			T150	1		T144	1		T404	1
auto[2281701376:2415919103]	7	1			T151	1		T308	2		T421	1
auto[2415919104:2550136831]	8	1			T14	1		T139	1		T404	1
auto[2550136832:2684354559]	6	1			T141	1		T142	1		T406	1
auto[2684354560:2818572287]	12	1			T14	1		T142	1		T308	1
auto[2818572288:2952790015]	7	1			T14	1		T150	1		T357	1
auto[2952790016:3087007743]	10	1			T14	1		T139	1		T141	1
auto[3087007744:3221225471]	6	1			T143	1		T306	1		T145	1
auto[3221225472:3355443199]	5	1			T115	1		T408	1		T379	1
auto[3355443200:3489660927]	4	1			T150	1		T151	1		T423	1
auto[3489660928:3623878655]	7	1			T151	1		T142	1		T308	1
auto[3623878656:3758096383]	15	1			T115	1		T306	1		T145	1
auto[3758096384:3892314111]	14	1			T115	1		T141	1		T143	1
auto[3892314112:4026531839]	9	1			T142	1		T306	1		T144	1
auto[4026531840:4160749567]	7	1			T115	1		T150	1		T394	1
auto[4160749568:4294967295]	10	1			T14	1		T394	1		T144	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31534	1			T1	25		T3	43		T4	38
auto[0:134217727]	auto[1]	12	1			T115	1		T151	1		T394	1
auto[134217728:268435455]	auto[1]	11	1			T115	1		T139	1		T408	1
auto[268435456:402653183]	auto[1]	9	1			T394	1		T306	1		T145	1
auto[402653184:536870911]	auto[1]	7	1			T394	1		T306	1		T379	1
auto[536870912:671088639]	auto[1]	11	1			T14	1		T141	1		T143	1
auto[671088640:805306367]	auto[1]	9	1			T394	1		T141	1		T144	2
auto[805306368:939524095]	auto[1]	8	1			T14	1		T150	1		T394	1
auto[939524096:1073741823]	auto[1]	5	1			T306	1		T145	1		T404	1
auto[1073741824:1207959551]	auto[1]	13	1			T141	1		T142	1		T143	1
auto[1207959552:1342177279]	auto[1]	7	1			T14	1		T150	1		T408	1
auto[1342177280:1476395007]	auto[1]	11	1			T144	1		T379	1		T404	1
auto[1476395008:1610612735]	auto[1]	5	1			T14	1		T306	1		T421	1
auto[1610612736:1744830463]	auto[1]	5	1			T144	1		T422	1		T341	1
auto[1744830464:1879048191]	auto[1]	10	1			T150	2		T144	1		T408	1
auto[1879048192:2013265919]	auto[1]	15	1			T139	2		T394	1		T379	2
auto[2013265920:2147483647]	auto[1]	9	1			T14	2		T142	1		T408	1
auto[2147483648:2281701375]	auto[1]	8	1			T150	1		T144	1		T404	1
auto[2281701376:2415919103]	auto[1]	7	1			T151	1		T308	2		T421	1
auto[2415919104:2550136831]	auto[1]	8	1			T14	1		T139	1		T404	1
auto[2550136832:2684354559]	auto[1]	6	1			T141	1		T142	1		T406	1
auto[2684354560:2818572287]	auto[1]	12	1			T14	1		T142	1		T308	1
auto[2818572288:2952790015]	auto[1]	7	1			T14	1		T150	1		T357	1
auto[2952790016:3087007743]	auto[1]	10	1			T14	1		T139	1		T141	1
auto[3087007744:3221225471]	auto[1]	6	1			T143	1		T306	1		T145	1
auto[3221225472:3355443199]	auto[1]	5	1			T115	1		T408	1		T379	1
auto[3355443200:3489660927]	auto[1]	4	1			T150	1		T151	1		T423	1
auto[3489660928:3623878655]	auto[1]	7	1			T151	1		T142	1		T308	1
auto[3623878656:3758096383]	auto[1]	15	1			T115	1		T306	1		T145	1
auto[3758096384:3892314111]	auto[1]	14	1			T115	1		T141	1		T143	1
auto[3892314112:4026531839]	auto[1]	9	1			T142	1		T306	1		T144	1
auto[4026531840:4160749567]	auto[1]	7	1			T115	1		T150	1		T394	1
auto[4160749568:4294967295]	auto[1]	10	1			T14	1		T394	1		T144	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1475

1

T1

2

T3

5

T14

1

auto[1]

1639

1

T1

2

T3

1

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T17	1		T88	1		T89	1
auto[134217728:268435455]	110	1			T34	1		T21	1		T242	1
auto[268435456:402653183]	89	1			T47	1		T38	2		T137	1
auto[402653184:536870911]	90	1			T34	1		T21	2		T247	1
auto[536870912:671088639]	100	1			T38	3		T49	2		T230	1
auto[671088640:805306367]	99	1			T16	1		T30	1		T47	1
auto[805306368:939524095]	94	1			T34	1		T242	1		T30	1
auto[939524096:1073741823]	93	1			T1	1		T88	1		T232	1
auto[1073741824:1207959551]	111	1			T14	1		T16	1		T34	1
auto[1207959552:1342177279]	90	1			T232	2		T6	1		T38	3
auto[1342177280:1476395007]	96	1			T4	1		T88	1		T232	1
auto[1476395008:1610612735]	93	1			T160	1		T30	1		T42	1
auto[1610612736:1744830463]	70	1			T13	1		T88	1		T232	1
auto[1744830464:1879048191]	104	1			T4	1		T30	1		T49	1
auto[1879048192:2013265919]	98	1			T88	1		T21	1		T89	1
auto[2013265920:2147483647]	106	1			T3	1		T14	1		T89	2
auto[2147483648:2281701375]	96	1			T42	1		T43	1		T49	1
auto[2281701376:2415919103]	100	1			T1	1		T242	1		T6	1
auto[2415919104:2550136831]	110	1			T3	1		T34	3		T49	2
auto[2550136832:2684354559]	81	1			T49	2		T230	1		T226	1
auto[2684354560:2818572287]	98	1			T35	1		T130	1		T49	2
auto[2818572288:2952790015]	79	1			T34	1		T38	2		T230	1
auto[2952790016:3087007743]	110	1			T3	2		T14	1		T160	1
auto[3087007744:3221225471]	104	1			T1	1		T30	1		T89	1
auto[3221225472:3355443199]	97	1			T21	1		T105	1		T6	1
auto[3355443200:3489660927]	103	1			T1	1		T3	1		T44	1
auto[3489660928:3623878655]	81	1			T3	1		T21	1		T35	1
auto[3623878656:3758096383]	109	1			T4	1		T105	1		T38	1
auto[3758096384:3892314111]	122	1			T4	1		T16	1		T21	1
auto[3892314112:4026531839]	99	1			T105	1		T130	2		T47	1
auto[4026531840:4160749567]	105	1			T34	2		T21	1		T38	1
auto[4160749568:4294967295]	89	1			T34	1		T88	1		T35	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T17	1		T49	1		T90	1
auto[0:134217727]	auto[1]	48	1			T88	1		T89	1		T38	3
auto[134217728:268435455]	auto[0]	51	1			T21	1		T38	2		T39	2
auto[134217728:268435455]	auto[1]	59	1			T34	1		T242	1		T105	1
auto[268435456:402653183]	auto[0]	42	1			T38	1		T137	1		T409	1
auto[268435456:402653183]	auto[1]	47	1			T47	1		T38	1		T233	1
auto[402653184:536870911]	auto[0]	41	1			T34	1		T21	1		T247	1
auto[402653184:536870911]	auto[1]	49	1			T21	1		T105	1		T6	1
auto[536870912:671088639]	auto[0]	39	1			T49	1		T102	1		T58	1
auto[536870912:671088639]	auto[1]	61	1			T38	3		T49	1		T230	1
auto[671088640:805306367]	auto[0]	43	1			T30	1		T38	2		T67	1
auto[671088640:805306367]	auto[1]	56	1			T16	1		T47	1		T49	2
auto[805306368:939524095]	auto[0]	48	1			T242	1		T30	1		T43	1
auto[805306368:939524095]	auto[1]	46	1			T34	1		T38	1		T101	1
auto[939524096:1073741823]	auto[0]	49	1			T1	1		T232	1		T35	1
auto[939524096:1073741823]	auto[1]	44	1			T88	1		T101	1		T137	1
auto[1073741824:1207959551]	auto[0]	52	1			T6	1		T38	1		T49	1
auto[1073741824:1207959551]	auto[1]	59	1			T14	1		T16	1		T34	1
auto[1207959552:1342177279]	auto[0]	40	1			T232	1		T38	1		T7	1
auto[1207959552:1342177279]	auto[1]	50	1			T232	1		T6	1		T38	2
auto[1342177280:1476395007]	auto[0]	55	1			T88	1		T38	1		T101	1
auto[1342177280:1476395007]	auto[1]	41	1			T4	1		T232	1		T95	1
auto[1476395008:1610612735]	auto[0]	40	1			T30	1		T38	1		T228	1
auto[1476395008:1610612735]	auto[1]	53	1			T160	1		T42	1		T38	1
auto[1610612736:1744830463]	auto[0]	31	1			T232	1		T30	1		T40	1
auto[1610612736:1744830463]	auto[1]	39	1			T13	1		T88	1		T105	1
auto[1744830464:1879048191]	auto[0]	46	1			T30	1		T39	1		T138	1
auto[1744830464:1879048191]	auto[1]	58	1			T4	1		T49	1		T67	1
auto[1879048192:2013265919]	auto[0]	50	1			T21	1		T47	1		T49	1
auto[1879048192:2013265919]	auto[1]	48	1			T88	1		T89	1		T49	2
auto[2013265920:2147483647]	auto[0]	52	1			T3	1		T14	1		T38	2
auto[2013265920:2147483647]	auto[1]	54	1			T89	2		T49	3		T115	1
auto[2147483648:2281701375]	auto[0]	55	1			T42	1		T43	1		T49	1
auto[2147483648:2281701375]	auto[1]	41	1			T115	1		T90	1		T41	1
auto[2281701376:2415919103]	auto[0]	57	1			T1	1		T242	1		T49	1
auto[2281701376:2415919103]	auto[1]	43	1			T6	1		T31	1		T240	1
auto[2415919104:2550136831]	auto[0]	44	1			T3	1		T34	1		T228	1
auto[2415919104:2550136831]	auto[1]	66	1			T34	2		T49	2		T233	1
auto[2550136832:2684354559]	auto[0]	40	1			T49	1		T226	1		T294	1
auto[2550136832:2684354559]	auto[1]	41	1			T49	1		T230	1		T324	1
auto[2684354560:2818572287]	auto[0]	45	1			T130	1		T49	1		T54	1
auto[2684354560:2818572287]	auto[1]	53	1			T35	1		T49	1		T41	2
auto[2818572288:2952790015]	auto[0]	35	1			T38	1		T115	1		T239	2
auto[2818572288:2952790015]	auto[1]	44	1			T34	1		T38	1		T230	1
auto[2952790016:3087007743]	auto[0]	48	1			T3	1		T105	1		T47	1
auto[2952790016:3087007743]	auto[1]	62	1			T3	1		T14	1		T160	1
auto[3087007744:3221225471]	auto[0]	49	1			T30	1		T138	1		T282	1
auto[3087007744:3221225471]	auto[1]	55	1			T1	1		T89	1		T38	1
auto[3221225472:3355443199]	auto[0]	49	1			T21	1		T105	1		T38	3
auto[3221225472:3355443199]	auto[1]	48	1			T6	1		T38	1		T49	2
auto[3355443200:3489660927]	auto[0]	46	1			T3	1		T38	1		T49	1
auto[3355443200:3489660927]	auto[1]	57	1			T1	1		T44	1		T48	1
auto[3489660928:3623878655]	auto[0]	40	1			T3	1		T21	1		T35	1
auto[3489660928:3623878655]	auto[1]	41	1			T160	1		T38	1		T49	1
auto[3623878656:3758096383]	auto[0]	50	1			T105	1		T38	1		T31	1
auto[3623878656:3758096383]	auto[1]	59	1			T4	1		T49	1		T71	1
auto[3758096384:3892314111]	auto[0]	58	1			T21	1		T30	1		T105	1
auto[3758096384:3892314111]	auto[1]	64	1			T4	1		T16	1		T38	1
auto[3892314112:4026531839]	auto[0]	53	1			T47	1		T38	1		T49	1
auto[3892314112:4026531839]	auto[1]	46	1			T105	1		T130	2		T38	1
auto[4026531840:4160749567]	auto[0]	47	1			T34	1		T38	1		T409	1
auto[4026531840:4160749567]	auto[1]	58	1			T34	1		T21	1		T115	1
auto[4160749568:4294967295]	auto[0]	40	1			T88	1		T35	1		T89	1
auto[4160749568:4294967295]	auto[1]	49	1			T34	1		T137	1		T96	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1430

1

T1

3

T3

5

T14

2

auto[1]

1684

1

T1

1

T3

1

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T35	2		T42	1		T38	3
auto[134217728:268435455]	89	1			T105	1		T6	1		T49	2
auto[268435456:402653183]	90	1			T34	1		T247	1		T89	1
auto[402653184:536870911]	109	1			T38	2		T49	1		T39	1
auto[536870912:671088639]	82	1			T14	1		T21	1		T38	3
auto[671088640:805306367]	96	1			T3	1		T30	1		T38	1
auto[805306368:939524095]	112	1			T89	1		T105	1		T49	2
auto[939524096:1073741823]	107	1			T3	1		T21	1		T232	1
auto[1073741824:1207959551]	87	1			T4	1		T34	1		T105	1
auto[1207959552:1342177279]	93	1			T4	1		T13	1		T34	2
auto[1342177280:1476395007]	126	1			T3	1		T34	1		T232	1
auto[1476395008:1610612735]	82	1			T1	1		T3	1		T34	1
auto[1610612736:1744830463]	78	1			T88	1		T47	1		T38	2
auto[1744830464:1879048191]	80	1			T88	1		T89	1		T47	1
auto[1879048192:2013265919]	94	1			T3	1		T4	1		T14	1
auto[2013265920:2147483647]	95	1			T34	1		T21	1		T30	1
auto[2147483648:2281701375]	87	1			T47	1		T101	1		T40	1
auto[2281701376:2415919103]	106	1			T34	1		T88	1		T30	1
auto[2415919104:2550136831]	90	1			T34	1		T88	1		T6	1
auto[2550136832:2684354559]	92	1			T1	1		T4	1		T16	1
auto[2684354560:2818572287]	108	1			T34	1		T88	1		T232	1
auto[2818572288:2952790015]	101	1			T232	1		T105	1		T130	1
auto[2952790016:3087007743]	94	1			T14	1		T21	1		T35	1
auto[3087007744:3221225471]	96	1			T1	1		T3	1		T88	1
auto[3221225472:3355443199]	99	1			T21	1		T6	1		T38	1
auto[3355443200:3489660927]	106	1			T38	3		T230	1		T31	1
auto[3489660928:3623878655]	108	1			T6	1		T38	1		T49	2
auto[3623878656:3758096383]	108	1			T16	1		T34	1		T89	1
auto[3758096384:3892314111]	100	1			T17	1		T160	1		T47	1
auto[3892314112:4026531839]	99	1			T21	1		T242	1		T89	1
auto[4026531840:4160749567]	104	1			T16	1		T21	1		T6	1
auto[4160749568:4294967295]	87	1			T1	1		T160	1		T49	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T35	2		T42	1		T38	1
auto[0:134217727]	auto[1]	57	1			T38	2		T95	1		T313	1
auto[134217728:268435455]	auto[0]	36	1			T40	2		T137	1		T138	1
auto[134217728:268435455]	auto[1]	53	1			T105	1		T6	1		T49	2
auto[268435456:402653183]	auto[0]	36	1			T105	1		T38	1		T49	1
auto[268435456:402653183]	auto[1]	54	1			T34	1		T247	1		T89	1
auto[402653184:536870911]	auto[0]	50	1			T38	1		T49	1		T39	1
auto[402653184:536870911]	auto[1]	59	1			T38	1		T115	1		T67	1
auto[536870912:671088639]	auto[0]	35	1			T14	1		T21	1		T38	2
auto[536870912:671088639]	auto[1]	47	1			T38	1		T31	1		T138	1
auto[671088640:805306367]	auto[0]	48	1			T3	1		T30	1		T38	1
auto[671088640:805306367]	auto[1]	48	1			T234	1		T41	1		T63	1
auto[805306368:939524095]	auto[0]	48	1			T105	1		T49	1		T41	1
auto[805306368:939524095]	auto[1]	64	1			T89	1		T49	1		T95	1
auto[939524096:1073741823]	auto[0]	55	1			T3	1		T21	1		T232	1
auto[939524096:1073741823]	auto[1]	52	1			T105	1		T38	2		T49	1
auto[1073741824:1207959551]	auto[0]	47	1			T34	1		T49	1		T39	1
auto[1073741824:1207959551]	auto[1]	40	1			T4	1		T105	1		T49	1
auto[1207959552:1342177279]	auto[0]	49	1			T34	2		T232	1		T30	1
auto[1207959552:1342177279]	auto[1]	44	1			T4	1		T13	1		T160	1
auto[1342177280:1476395007]	auto[0]	53	1			T3	1		T137	1		T67	1
auto[1342177280:1476395007]	auto[1]	73	1			T34	1		T232	1		T44	1
auto[1476395008:1610612735]	auto[0]	31	1			T1	1		T30	1		T39	1
auto[1476395008:1610612735]	auto[1]	51	1			T3	1		T34	1		T89	1
auto[1610612736:1744830463]	auto[0]	28	1			T88	1		T38	1		T49	1
auto[1610612736:1744830463]	auto[1]	50	1			T47	1		T38	1		T101	1
auto[1744830464:1879048191]	auto[0]	36	1			T38	1		T49	1		T40	1
auto[1744830464:1879048191]	auto[1]	44	1			T88	1		T89	1		T47	1
auto[1879048192:2013265919]	auto[0]	43	1			T3	1		T14	1		T42	1
auto[1879048192:2013265919]	auto[1]	51	1			T4	1		T88	1		T242	1
auto[2013265920:2147483647]	auto[0]	48	1			T21	1		T30	1		T38	1
auto[2013265920:2147483647]	auto[1]	47	1			T34	1		T230	2		T69	1
auto[2147483648:2281701375]	auto[0]	39	1			T47	1		T40	1		T69	1
auto[2147483648:2281701375]	auto[1]	48	1			T101	1		T67	1		T239	1
auto[2281701376:2415919103]	auto[0]	58	1			T30	1		T89	1		T38	1
auto[2281701376:2415919103]	auto[1]	48	1			T34	1		T88	1		T49	1
auto[2415919104:2550136831]	auto[0]	43	1			T88	1		T47	1		T138	1
auto[2415919104:2550136831]	auto[1]	47	1			T34	1		T6	1		T48	1
auto[2550136832:2684354559]	auto[0]	38	1			T1	1		T16	1		T21	1
auto[2550136832:2684354559]	auto[1]	54	1			T4	1		T38	1		T31	1
auto[2684354560:2818572287]	auto[0]	48	1			T30	1		T105	1		T6	1
auto[2684354560:2818572287]	auto[1]	60	1			T34	1		T88	1		T232	1
auto[2818572288:2952790015]	auto[0]	43	1			T130	1		T115	1		T137	1
auto[2818572288:2952790015]	auto[1]	58	1			T232	1		T105	1		T38	1
auto[2952790016:3087007743]	auto[0]	43	1			T35	1		T105	1		T67	1
auto[2952790016:3087007743]	auto[1]	51	1			T14	1		T21	1		T49	3
auto[3087007744:3221225471]	auto[0]	50	1			T1	1		T3	1		T88	1
auto[3087007744:3221225471]	auto[1]	46	1			T130	1		T38	2		T230	1
auto[3221225472:3355443199]	auto[0]	44	1			T21	1		T49	1		T40	1
auto[3221225472:3355443199]	auto[1]	55	1			T6	1		T38	1		T151	1
auto[3355443200:3489660927]	auto[0]	53	1			T38	2		T67	1		T150	1
auto[3355443200:3489660927]	auto[1]	53	1			T38	1		T230	1		T31	1
auto[3489660928:3623878655]	auto[0]	46	1			T38	1		T49	1		T69	1
auto[3489660928:3623878655]	auto[1]	62	1			T6	1		T49	1		T115	1
auto[3623878656:3758096383]	auto[0]	48	1			T38	1		T49	1		T72	1
auto[3623878656:3758096383]	auto[1]	60	1			T16	1		T34	1		T89	1
auto[3758096384:3892314111]	auto[0]	48	1			T160	1		T47	1		T38	3
auto[3758096384:3892314111]	auto[1]	52	1			T17	1		T38	1		T248	1
auto[3892314112:4026531839]	auto[0]	55	1			T21	1		T242	1		T49	1
auto[3892314112:4026531839]	auto[1]	44	1			T89	1		T105	1		T49	1
auto[4026531840:4160749567]	auto[0]	40	1			T16	1		T38	3		T39	1
auto[4026531840:4160749567]	auto[1]	64	1			T21	1		T6	1		T38	2
auto[4160749568:4294967295]	auto[0]	39	1			T160	1		T69	1		T226	1
auto[4160749568:4294967295]	auto[1]	48	1			T1	1		T49	1		T274	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1447

1

T1

2

T3

5

T14

1

auto[1]

1667

1

T1

2

T3

1

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T1	1		T34	1		T89	1
auto[134217728:268435455]	125	1			T232	1		T30	1		T38	2
auto[268435456:402653183]	88	1			T34	1		T88	1		T35	1
auto[402653184:536870911]	99	1			T21	2		T242	1		T89	1
auto[536870912:671088639]	84	1			T3	1		T89	1		T38	3
auto[671088640:805306367]	114	1			T34	1		T30	1		T89	1
auto[805306368:939524095]	93	1			T1	1		T34	1		T89	1
auto[939524096:1073741823]	97	1			T3	1		T34	1		T88	2
auto[1073741824:1207959551]	85	1			T4	1		T89	1		T38	1
auto[1207959552:1342177279]	98	1			T38	1		T49	2		T31	1
auto[1342177280:1476395007]	107	1			T13	1		T34	2		T105	1
auto[1476395008:1610612735]	98	1			T3	1		T17	1		T88	1
auto[1610612736:1744830463]	103	1			T21	1		T38	1		T49	1
auto[1744830464:1879048191]	92	1			T4	1		T14	3		T89	1
auto[1879048192:2013265919]	102	1			T30	1		T38	3		T49	1
auto[2013265920:2147483647]	89	1			T232	2		T44	1		T43	1
auto[2147483648:2281701375]	111	1			T232	2		T130	1		T38	1
auto[2281701376:2415919103]	86	1			T6	1		T38	3		T49	1
auto[2415919104:2550136831]	80	1			T1	1		T30	1		T49	4
auto[2550136832:2684354559]	94	1			T1	1		T16	1		T38	1
auto[2684354560:2818572287]	110	1			T88	1		T35	1		T105	1
auto[2818572288:2952790015]	88	1			T21	1		T130	1		T47	1
auto[2952790016:3087007743]	82	1			T242	1		T42	1		T105	1
auto[3087007744:3221225471]	94	1			T34	1		T30	1		T38	1
auto[3221225472:3355443199]	89	1			T16	1		T30	1		T130	1
auto[3355443200:3489660927]	107	1			T21	1		T105	2		T38	1
auto[3489660928:3623878655]	99	1			T3	1		T4	2		T88	1
auto[3623878656:3758096383]	91	1			T34	1		T35	1		T6	1
auto[3758096384:3892314111]	106	1			T3	1		T88	1		T42	1
auto[3892314112:4026531839]	104	1			T34	2		T247	1		T160	1
auto[4026531840:4160749567]	83	1			T3	1		T21	1		T47	1
auto[4160749568:4294967295]	116	1			T16	1		T30	1		T38	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T38	3		T40	1		T96	1
auto[0:134217727]	auto[1]	55	1			T1	1		T34	1		T89	1
auto[134217728:268435455]	auto[0]	51	1			T30	1		T38	1		T49	1
auto[134217728:268435455]	auto[1]	74	1			T232	1		T38	1		T49	5
auto[268435456:402653183]	auto[0]	46	1			T34	1		T88	1		T242	1
auto[268435456:402653183]	auto[1]	42	1			T35	1		T115	1		T67	1
auto[402653184:536870911]	auto[0]	49	1			T21	2		T38	2		T72	1
auto[402653184:536870911]	auto[1]	50	1			T242	1		T89	1		T6	1
auto[536870912:671088639]	auto[0]	40	1			T3	1		T38	3		T67	1
auto[536870912:671088639]	auto[1]	44	1			T89	1		T49	1		T41	2
auto[671088640:805306367]	auto[0]	62	1			T30	1		T38	1		T39	1
auto[671088640:805306367]	auto[1]	52	1			T34	1		T89	1		T230	1
auto[805306368:939524095]	auto[0]	48	1			T1	1		T34	1		T38	1
auto[805306368:939524095]	auto[1]	45	1			T89	1		T6	1		T38	1
auto[939524096:1073741823]	auto[0]	42	1			T3	1		T88	2		T21	2
auto[939524096:1073741823]	auto[1]	55	1			T34	1		T38	1		T49	1
auto[1073741824:1207959551]	auto[0]	35	1			T89	1		T58	1		T59	1
auto[1073741824:1207959551]	auto[1]	50	1			T4	1		T38	1		T137	1
auto[1207959552:1342177279]	auto[0]	43	1			T49	2		T409	1		T41	2
auto[1207959552:1342177279]	auto[1]	55	1			T38	1		T31	1		T233	1
auto[1342177280:1476395007]	auto[0]	48	1			T54	1		T69	1		T90	1
auto[1342177280:1476395007]	auto[1]	59	1			T13	1		T34	2		T105	1
auto[1476395008:1610612735]	auto[0]	36	1			T3	1		T35	1		T39	2
auto[1476395008:1610612735]	auto[1]	62	1			T17	1		T88	1		T160	1
auto[1610612736:1744830463]	auto[0]	46	1			T21	1		T38	1		T150	1
auto[1610612736:1744830463]	auto[1]	57	1			T49	1		T69	1		T41	1
auto[1744830464:1879048191]	auto[0]	47	1			T14	1		T105	2		T38	2
auto[1744830464:1879048191]	auto[1]	45	1			T4	1		T14	2		T89	1
auto[1879048192:2013265919]	auto[0]	51	1			T30	1		T38	2		T248	1
auto[1879048192:2013265919]	auto[1]	51	1			T38	1		T49	1		T95	1
auto[2013265920:2147483647]	auto[0]	48	1			T232	1		T47	1		T38	1
auto[2013265920:2147483647]	auto[1]	41	1			T232	1		T44	1		T43	1
auto[2147483648:2281701375]	auto[0]	56	1			T232	1		T49	4		T248	1
auto[2147483648:2281701375]	auto[1]	55	1			T232	1		T130	1		T38	1
auto[2281701376:2415919103]	auto[0]	37	1			T95	1		T138	1		T53	1
auto[2281701376:2415919103]	auto[1]	49	1			T6	1		T38	3		T49	1
auto[2415919104:2550136831]	auto[0]	44	1			T1	1		T30	1		T409	1
auto[2415919104:2550136831]	auto[1]	36	1			T49	4		T52	1		T69	1
auto[2550136832:2684354559]	auto[0]	38	1			T49	1		T95	1		T246	1
auto[2550136832:2684354559]	auto[1]	56	1			T1	1		T16	1		T38	1
auto[2684354560:2818572287]	auto[0]	52	1			T35	1		T105	1		T138	1
auto[2684354560:2818572287]	auto[1]	58	1			T88	1		T49	1		T115	1
auto[2818572288:2952790015]	auto[0]	39	1			T47	1		T49	2		T40	2
auto[2818572288:2952790015]	auto[1]	49	1			T21	1		T130	1		T49	1
auto[2952790016:3087007743]	auto[0]	35	1			T242	1		T42	1		T38	1
auto[2952790016:3087007743]	auto[1]	47	1			T105	1		T38	2		T49	1
auto[3087007744:3221225471]	auto[0]	42	1			T34	1		T38	1		T239	1
auto[3087007744:3221225471]	auto[1]	52	1			T30	1		T48	1		T49	1
auto[3221225472:3355443199]	auto[0]	36	1			T30	1		T130	1		T39	1
auto[3221225472:3355443199]	auto[1]	53	1			T16	1		T49	1		T101	1
auto[3355443200:3489660927]	auto[0]	55	1			T21	1		T105	1		T49	1
auto[3355443200:3489660927]	auto[1]	52	1			T105	1		T38	1		T49	2
auto[3489660928:3623878655]	auto[0]	35	1			T3	1		T43	2		T47	1
auto[3489660928:3623878655]	auto[1]	64	1			T4	2		T88	1		T160	1
auto[3623878656:3758096383]	auto[0]	40	1			T34	1		T35	1		T228	1
auto[3623878656:3758096383]	auto[1]	51	1			T6	1		T49	1		T234	1
auto[3758096384:3892314111]	auto[0]	42	1			T3	1		T6	1		T31	1
auto[3758096384:3892314111]	auto[1]	64	1			T88	1		T42	1		T47	1
auto[3892314112:4026531839]	auto[0]	54	1			T34	1		T247	1		T38	2
auto[3892314112:4026531839]	auto[1]	50	1			T34	1		T160	1		T54	1
auto[4026531840:4160749567]	auto[0]	37	1			T38	1		T137	2		T246	1
auto[4026531840:4160749567]	auto[1]	46	1			T3	1		T21	1		T47	1
auto[4160749568:4294967295]	auto[0]	68	1			T16	1		T30	1		T38	1
auto[4160749568:4294967295]	auto[1]	48	1			T38	1		T230	1		T115	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1436

1

T1

2

T3

4

T14

2

auto[1]

1678

1

T1

2

T3

2

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T3	1		T34	1		T89	2
auto[134217728:268435455]	98	1			T38	2		T49	1		T40	1
auto[268435456:402653183]	91	1			T88	1		T232	1		T160	1
auto[402653184:536870911]	112	1			T34	2		T105	1		T47	2
auto[536870912:671088639]	128	1			T34	1		T35	1		T105	1
auto[671088640:805306367]	89	1			T38	2		T49	2		T67	1
auto[805306368:939524095]	82	1			T3	1		T17	1		T88	1
auto[939524096:1073741823]	101	1			T16	2		T43	1		T47	1
auto[1073741824:1207959551]	88	1			T34	1		T21	1		T30	1
auto[1207959552:1342177279]	98	1			T3	1		T14	1		T34	1
auto[1342177280:1476395007]	95	1			T21	2		T38	3		T49	1
auto[1476395008:1610612735]	89	1			T88	2		T105	1		T48	1
auto[1610612736:1744830463]	95	1			T88	1		T242	1		T30	1
auto[1744830464:1879048191]	83	1			T1	1		T49	2		T31	1
auto[1879048192:2013265919]	89	1			T1	1		T3	1		T242	1
auto[2013265920:2147483647]	113	1			T232	1		T247	1		T38	1
auto[2147483648:2281701375]	100	1			T160	1		T38	2		T49	1
auto[2281701376:2415919103]	100	1			T4	1		T34	1		T232	1
auto[2415919104:2550136831]	90	1			T13	1		T242	1		T130	1
auto[2550136832:2684354559]	117	1			T105	1		T43	1		T38	2
auto[2684354560:2818572287]	90	1			T21	1		T232	1		T38	2
auto[2818572288:2952790015]	105	1			T89	1		T49	2		T150	1
auto[2952790016:3087007743]	92	1			T21	1		T30	1		T43	1
auto[3087007744:3221225471]	89	1			T4	1		T38	5		T49	2
auto[3221225472:3355443199]	108	1			T4	2		T88	1		T89	1
auto[3355443200:3489660927]	83	1			T1	1		T35	1		T38	3
auto[3489660928:3623878655]	99	1			T1	1		T14	1		T44	1
auto[3623878656:3758096383]	103	1			T88	1		T38	1		T49	4
auto[3758096384:3892314111]	94	1			T14	1		T34	2		T21	1
auto[3892314112:4026531839]	86	1			T3	1		T35	1		T160	1
auto[4026531840:4160749567]	106	1			T3	1		T16	1		T34	2
auto[4160749568:4294967295]	101	1			T21	1		T35	1		T130	1