Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.07 97.99 98.39 100.00 99.11 98.41 91.63


Total test records in report: 1063
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1004 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.683457024 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:38 PM PDT 24 25234885 ps
T1005 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3875657986 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:43 PM PDT 24 1558497599 ps
T1006 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2034978715 Apr 02 12:31:05 PM PDT 24 Apr 02 12:31:06 PM PDT 24 25817438 ps
T1007 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2352902477 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:41 PM PDT 24 1282778566 ps
T1008 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1934576595 Apr 02 12:30:46 PM PDT 24 Apr 02 12:30:47 PM PDT 24 22433788 ps
T1009 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1751402090 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:45 PM PDT 24 1659241468 ps
T1010 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1132003788 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:38 PM PDT 24 32504875 ps
T1011 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.366318380 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:53 PM PDT 24 664847277 ps
T1012 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3095607858 Apr 02 12:30:47 PM PDT 24 Apr 02 12:30:54 PM PDT 24 232857553 ps
T1013 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3757323308 Apr 02 12:30:53 PM PDT 24 Apr 02 12:30:58 PM PDT 24 119829508 ps
T1014 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3108180018 Apr 02 12:31:07 PM PDT 24 Apr 02 12:31:09 PM PDT 24 50219913 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.296302916 Apr 02 12:30:46 PM PDT 24 Apr 02 12:30:55 PM PDT 24 209611531 ps
T1016 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2320254177 Apr 02 12:31:14 PM PDT 24 Apr 02 12:31:17 PM PDT 24 110783915 ps
T1017 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.255023116 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:39 PM PDT 24 23762947 ps
T1018 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3306232435 Apr 02 12:30:44 PM PDT 24 Apr 02 12:30:48 PM PDT 24 556462106 ps
T1019 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2517990491 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:39 PM PDT 24 87224320 ps
T1020 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2289047533 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:39 PM PDT 24 15754377 ps
T1021 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2977008863 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:38 PM PDT 24 66020419 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1562712150 Apr 02 12:30:39 PM PDT 24 Apr 02 12:30:40 PM PDT 24 20984744 ps
T1023 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2532057474 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:41 PM PDT 24 81419992 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2525040412 Apr 02 12:31:49 PM PDT 24 Apr 02 12:31:51 PM PDT 24 43566487 ps
T1025 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3190910979 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:37 PM PDT 24 29277123 ps
T1026 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2141109657 Apr 02 12:31:48 PM PDT 24 Apr 02 12:31:50 PM PDT 24 38029327 ps
T1027 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.301039594 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:39 PM PDT 24 28059989 ps
T1028 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1507734468 Apr 02 12:30:39 PM PDT 24 Apr 02 12:30:41 PM PDT 24 47308615 ps
T175 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2627042284 Apr 02 12:31:00 PM PDT 24 Apr 02 12:31:06 PM PDT 24 185873252 ps
T1029 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1807999191 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:36 PM PDT 24 55579260 ps
T1030 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1022597864 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:35 PM PDT 24 35036319 ps
T1031 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3106099441 Apr 02 12:30:59 PM PDT 24 Apr 02 12:31:00 PM PDT 24 28446162 ps
T1032 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3258221313 Apr 02 12:31:09 PM PDT 24 Apr 02 12:31:18 PM PDT 24 264639319 ps
T173 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2012015013 Apr 02 12:30:41 PM PDT 24 Apr 02 12:30:50 PM PDT 24 216622238 ps
T1033 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3319678462 Apr 02 12:31:14 PM PDT 24 Apr 02 12:31:15 PM PDT 24 10722219 ps
T1034 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4091447147 Apr 02 12:30:40 PM PDT 24 Apr 02 12:30:41 PM PDT 24 32961290 ps
T1035 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3077102866 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:32 PM PDT 24 25943102 ps
T183 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.735058927 Apr 02 12:31:07 PM PDT 24 Apr 02 12:31:11 PM PDT 24 57559745 ps
T1036 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2800159229 Apr 02 12:30:38 PM PDT 24 Apr 02 12:30:40 PM PDT 24 124522714 ps
T1037 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3486472092 Apr 02 12:30:43 PM PDT 24 Apr 02 12:30:53 PM PDT 24 3429297785 ps
T1038 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3727471064 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:40 PM PDT 24 263830216 ps
T1039 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3799693953 Apr 02 12:30:55 PM PDT 24 Apr 02 12:30:56 PM PDT 24 15915665 ps
T1040 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3043591777 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:49 PM PDT 24 536262499 ps
T1041 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2667087336 Apr 02 12:31:17 PM PDT 24 Apr 02 12:31:20 PM PDT 24 46719835 ps
T1042 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.441349477 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:38 PM PDT 24 53267980 ps
T1043 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1737855040 Apr 02 12:31:04 PM PDT 24 Apr 02 12:31:12 PM PDT 24 1182425474 ps
T1044 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1308574109 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:37 PM PDT 24 477291948 ps
T1045 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4181578696 Apr 02 12:30:40 PM PDT 24 Apr 02 12:30:41 PM PDT 24 43870986 ps
T1046 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2587498158 Apr 02 12:30:39 PM PDT 24 Apr 02 12:30:40 PM PDT 24 75893454 ps
T1047 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.330824383 Apr 02 12:30:38 PM PDT 24 Apr 02 12:30:44 PM PDT 24 18096592 ps
T1048 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3410297427 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:41 PM PDT 24 93937346 ps
T1049 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1292217598 Apr 02 12:30:48 PM PDT 24 Apr 02 12:30:51 PM PDT 24 144229097 ps
T1050 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3348041297 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:43 PM PDT 24 254212591 ps
T1051 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.55245682 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:44 PM PDT 24 468649444 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3045753794 Apr 02 12:31:07 PM PDT 24 Apr 02 12:31:09 PM PDT 24 109954679 ps
T1053 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.516352663 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:35 PM PDT 24 295669076 ps
T1054 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4178222110 Apr 02 12:30:39 PM PDT 24 Apr 02 12:30:43 PM PDT 24 1108263894 ps
T1055 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.243742118 Apr 02 12:30:38 PM PDT 24 Apr 02 12:30:42 PM PDT 24 125415407 ps
T1056 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2370092006 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:39 PM PDT 24 201903372 ps
T1057 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1759587635 Apr 02 12:31:48 PM PDT 24 Apr 02 12:31:52 PM PDT 24 484007220 ps
T1058 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2373394215 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:36 PM PDT 24 154131440 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3870037289 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:42 PM PDT 24 133993874 ps
T1060 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3153008917 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:33 PM PDT 24 13248065 ps
T1061 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1854247167 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:36 PM PDT 24 34173698 ps
T1062 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2291068290 Apr 02 12:31:08 PM PDT 24 Apr 02 12:31:09 PM PDT 24 13863742 ps
T1063 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.190302367 Apr 02 12:31:19 PM PDT 24 Apr 02 12:31:22 PM PDT 24 119168612 ps

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3175567670
Short name T3
Test name
Test status
Simulation time 548410116 ps
CPU time 6.23 seconds
Started Apr 02 01:44:15 PM PDT 24
Finished Apr 02 01:44:21 PM PDT 24
Peak memory 222700 kb
Host smart-682f503c-5fb5-4a5d-9204-33d7a90cd07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175567670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3175567670
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1747705096
Short name T38
Test name
Test status
Simulation time 927928540 ps
CPU time 36.7 seconds
Started Apr 02 01:45:35 PM PDT 24
Finished Apr 02 01:46:12 PM PDT 24
Peak memory 215556 kb
Host smart-f278e0f5-2b0a-4531-8b4d-2f5dda0f0ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747705096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1747705096
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4041527180
Short name T34
Test name
Test status
Simulation time 2320720760 ps
CPU time 17.13 seconds
Started Apr 02 01:46:49 PM PDT 24
Finished Apr 02 01:47:06 PM PDT 24
Peak memory 216212 kb
Host smart-01006772-7c75-4cab-bedd-2a6483af647d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041527180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4041527180
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2568374378
Short name T63
Test name
Test status
Simulation time 1096551529 ps
CPU time 22.49 seconds
Started Apr 02 01:47:21 PM PDT 24
Finished Apr 02 01:47:45 PM PDT 24
Peak memory 216884 kb
Host smart-ad8a45d6-1af1-4df9-8178-04f9b02a4300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568374378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2568374378
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1285289107
Short name T5
Test name
Test status
Simulation time 964774336 ps
CPU time 18.6 seconds
Started Apr 02 01:42:01 PM PDT 24
Finished Apr 02 01:42:20 PM PDT 24
Peak memory 234892 kb
Host smart-bdd27d3f-8aae-486f-980f-c5272310dbe7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285289107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1285289107
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3987643120
Short name T112
Test name
Test status
Simulation time 419204944 ps
CPU time 14.67 seconds
Started Apr 02 12:30:56 PM PDT 24
Finished Apr 02 12:31:10 PM PDT 24
Peak memory 214236 kb
Host smart-f10748e4-cf2d-47f1-98be-6e8d89d59eae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987643120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3987643120
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.764661909
Short name T41
Test name
Test status
Simulation time 3623380681 ps
CPU time 40.8 seconds
Started Apr 02 01:41:44 PM PDT 24
Finished Apr 02 01:42:25 PM PDT 24
Peak memory 222972 kb
Host smart-7e57645e-4772-4c71-87f1-e3ab095904fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764661909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.764661909
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.608776463
Short name T105
Test name
Test status
Simulation time 197603438 ps
CPU time 7.81 seconds
Started Apr 02 01:46:49 PM PDT 24
Finished Apr 02 01:46:57 PM PDT 24
Peak memory 218420 kb
Host smart-9fdfa309-c8c7-41c7-8ff0-7689fc06cd49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608776463 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.608776463
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.845750194
Short name T150
Test name
Test status
Simulation time 2294056470 ps
CPU time 59.43 seconds
Started Apr 02 01:47:43 PM PDT 24
Finished Apr 02 01:48:42 PM PDT 24
Peak memory 215616 kb
Host smart-815fe578-6b8f-4e2e-b957-8f19dcef0f37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845750194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.845750194
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3931112153
Short name T8
Test name
Test status
Simulation time 79098788 ps
CPU time 2.78 seconds
Started Apr 02 01:46:43 PM PDT 24
Finished Apr 02 01:46:46 PM PDT 24
Peak memory 210444 kb
Host smart-72a71307-7e26-4841-86af-d9bf5562ffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931112153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3931112153
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.4161450127
Short name T49
Test name
Test status
Simulation time 393021147 ps
CPU time 21.88 seconds
Started Apr 02 01:47:49 PM PDT 24
Finished Apr 02 01:48:11 PM PDT 24
Peak memory 222796 kb
Host smart-61ced1af-e270-4172-931b-3f1d583d7744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161450127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4161450127
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.104719017
Short name T45
Test name
Test status
Simulation time 1668657900 ps
CPU time 19.07 seconds
Started Apr 02 01:43:40 PM PDT 24
Finished Apr 02 01:43:59 PM PDT 24
Peak memory 222784 kb
Host smart-fcc45ea9-1d7a-4765-b318-b76d6c00a958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104719017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.104719017
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3433690934
Short name T431
Test name
Test status
Simulation time 106023564 ps
CPU time 5.55 seconds
Started Apr 02 01:47:26 PM PDT 24
Finished Apr 02 01:47:31 PM PDT 24
Peak memory 214548 kb
Host smart-a72e8692-182f-48a3-80ee-0c5a3941c580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3433690934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3433690934
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.55533877
Short name T126
Test name
Test status
Simulation time 670320665 ps
CPU time 28.24 seconds
Started Apr 02 01:42:11 PM PDT 24
Finished Apr 02 01:42:39 PM PDT 24
Peak memory 223024 kb
Host smart-bf0e12f7-94f3-437d-bbd8-0d1e7ae7a277
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55533877 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.55533877
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.365403941
Short name T14
Test name
Test status
Simulation time 277895516 ps
CPU time 15.63 seconds
Started Apr 02 01:44:51 PM PDT 24
Finished Apr 02 01:45:07 PM PDT 24
Peak memory 214628 kb
Host smart-1deb46e2-c2fb-4a44-80a0-7b7fda1b4901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=365403941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.365403941
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3955662898
Short name T96
Test name
Test status
Simulation time 445821397 ps
CPU time 4.75 seconds
Started Apr 02 01:42:41 PM PDT 24
Finished Apr 02 01:42:46 PM PDT 24
Peak memory 221536 kb
Host smart-dfab7412-ae4d-4a79-8b99-48d0f0162709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955662898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3955662898
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.389089410
Short name T421
Test name
Test status
Simulation time 948079037 ps
CPU time 12.55 seconds
Started Apr 02 01:46:22 PM PDT 24
Finished Apr 02 01:46:35 PM PDT 24
Peak memory 222872 kb
Host smart-6648b56a-1504-4f25-b361-a29d9a6671e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389089410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.389089410
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.4049361473
Short name T58
Test name
Test status
Simulation time 749419530 ps
CPU time 29.62 seconds
Started Apr 02 01:43:57 PM PDT 24
Finished Apr 02 01:44:27 PM PDT 24
Peak memory 217836 kb
Host smart-4cc1f386-1a6b-4b7a-99db-952a8bde5e84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049361473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4049361473
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.236341221
Short name T115
Test name
Test status
Simulation time 504536985 ps
CPU time 5.51 seconds
Started Apr 02 01:43:26 PM PDT 24
Finished Apr 02 01:43:31 PM PDT 24
Peak memory 215516 kb
Host smart-a188270c-f089-4936-9331-dd86e487999e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236341221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.236341221
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1338766712
Short name T306
Test name
Test status
Simulation time 399085541 ps
CPU time 5.24 seconds
Started Apr 02 01:46:57 PM PDT 24
Finished Apr 02 01:47:03 PM PDT 24
Peak memory 214592 kb
Host smart-8c77b73c-b04c-4669-94d3-bd4320fb58a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1338766712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1338766712
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2200316569
Short name T97
Test name
Test status
Simulation time 60031510 ps
CPU time 3.68 seconds
Started Apr 02 01:44:09 PM PDT 24
Finished Apr 02 01:44:12 PM PDT 24
Peak memory 214660 kb
Host smart-f49b28e5-caea-41b4-bc11-95eec5179ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200316569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2200316569
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.406592590
Short name T319
Test name
Test status
Simulation time 200615596 ps
CPU time 10.32 seconds
Started Apr 02 01:47:05 PM PDT 24
Finished Apr 02 01:47:15 PM PDT 24
Peak memory 215680 kb
Host smart-1b9d3586-3335-48a0-8bc4-d5fa378d16fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406592590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.406592590
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1129799513
Short name T13
Test name
Test status
Simulation time 208711406 ps
CPU time 2.33 seconds
Started Apr 02 01:41:47 PM PDT 24
Finished Apr 02 01:41:50 PM PDT 24
Peak memory 209620 kb
Host smart-d1968118-684b-4c72-bc8c-875dff5ffd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129799513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1129799513
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2446065720
Short name T909
Test name
Test status
Simulation time 193609133 ps
CPU time 2.38 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 214304 kb
Host smart-77f2c110-2315-42de-bab6-803591fc657d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446065720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2446065720
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.456872335
Short name T258
Test name
Test status
Simulation time 53019443891 ps
CPU time 322.46 seconds
Started Apr 02 01:47:00 PM PDT 24
Finished Apr 02 01:52:22 PM PDT 24
Peak memory 221928 kb
Host smart-959de371-3e46-4728-b435-a0d548f78bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456872335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.456872335
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3656189560
Short name T104
Test name
Test status
Simulation time 13856499 ps
CPU time 0.77 seconds
Started Apr 02 01:41:47 PM PDT 24
Finished Apr 02 01:41:48 PM PDT 24
Peak memory 206236 kb
Host smart-5f65cb5d-02d4-4473-8c41-4b1f301f64b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656189560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3656189560
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3480711266
Short name T25
Test name
Test status
Simulation time 449778506 ps
CPU time 4.24 seconds
Started Apr 02 01:43:35 PM PDT 24
Finished Apr 02 01:43:39 PM PDT 24
Peak memory 220764 kb
Host smart-459152b8-7241-4a96-a42a-20a909e116d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480711266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3480711266
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2751787071
Short name T144
Test name
Test status
Simulation time 304752701 ps
CPU time 16.06 seconds
Started Apr 02 01:45:24 PM PDT 24
Finished Apr 02 01:45:40 PM PDT 24
Peak memory 214616 kb
Host smart-67b69e67-76ad-4e22-ad01-2680ffb09160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751787071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2751787071
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1909191855
Short name T317
Test name
Test status
Simulation time 6124166224 ps
CPU time 36.52 seconds
Started Apr 02 01:45:28 PM PDT 24
Finished Apr 02 01:46:04 PM PDT 24
Peak memory 216436 kb
Host smart-2875b444-0402-498f-af08-32066dbc1578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909191855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1909191855
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3058503908
Short name T155
Test name
Test status
Simulation time 156449889 ps
CPU time 5.29 seconds
Started Apr 02 01:46:55 PM PDT 24
Finished Apr 02 01:47:01 PM PDT 24
Peak memory 223040 kb
Host smart-e3c8f2b5-592e-4013-874c-e8f36d78a886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058503908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3058503908
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1917889221
Short name T55
Test name
Test status
Simulation time 64333146 ps
CPU time 2.21 seconds
Started Apr 02 01:46:54 PM PDT 24
Finished Apr 02 01:46:56 PM PDT 24
Peak memory 210496 kb
Host smart-d03e51af-fa44-41b3-8448-057b48c07c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917889221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1917889221
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1939014667
Short name T22
Test name
Test status
Simulation time 268473964 ps
CPU time 3.03 seconds
Started Apr 02 01:45:27 PM PDT 24
Finished Apr 02 01:45:30 PM PDT 24
Peak memory 217084 kb
Host smart-55eb02cc-5c61-4f88-b8b5-c5b2daeadfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939014667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1939014667
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1847222656
Short name T59
Test name
Test status
Simulation time 87247848450 ps
CPU time 421.83 seconds
Started Apr 02 01:46:39 PM PDT 24
Finished Apr 02 01:53:41 PM PDT 24
Peak memory 220360 kb
Host smart-3f1a57c1-7390-4019-a195-2c7792cf8dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847222656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1847222656
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1864168581
Short name T142
Test name
Test status
Simulation time 129372348 ps
CPU time 7 seconds
Started Apr 02 01:46:41 PM PDT 24
Finished Apr 02 01:46:48 PM PDT 24
Peak memory 216056 kb
Host smart-9dcc1aff-5f24-4dde-b0cf-b71f9c8e8393
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864168581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1864168581
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.349963277
Short name T172
Test name
Test status
Simulation time 275737144 ps
CPU time 9.96 seconds
Started Apr 02 12:30:49 PM PDT 24
Finished Apr 02 12:30:59 PM PDT 24
Peak memory 209272 kb
Host smart-34f1f098-02d2-4d52-bca2-c8783510982e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349963277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.349963277
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2596270957
Short name T109
Test name
Test status
Simulation time 2271282839 ps
CPU time 24.62 seconds
Started Apr 02 01:44:34 PM PDT 24
Finished Apr 02 01:44:59 PM PDT 24
Peak memory 223068 kb
Host smart-af8dc94a-5eb5-4d08-b886-89cc34706f0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596270957 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2596270957
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2532976047
Short name T279
Test name
Test status
Simulation time 193746371 ps
CPU time 7.31 seconds
Started Apr 02 01:43:54 PM PDT 24
Finished Apr 02 01:44:01 PM PDT 24
Peak memory 222860 kb
Host smart-765cea4b-5974-40ba-a65f-e35921e51084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532976047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2532976047
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3668721170
Short name T291
Test name
Test status
Simulation time 1712836425 ps
CPU time 17.68 seconds
Started Apr 02 01:44:24 PM PDT 24
Finished Apr 02 01:44:41 PM PDT 24
Peak memory 215532 kb
Host smart-33c8f4fc-9691-4d10-8792-dcdedd3480b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668721170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3668721170
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2062629973
Short name T436
Test name
Test status
Simulation time 296716713 ps
CPU time 15.3 seconds
Started Apr 02 01:47:44 PM PDT 24
Finished Apr 02 01:47:59 PM PDT 24
Peak memory 215036 kb
Host smart-4a061956-fdd6-4944-a0b1-a32053b2a4c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2062629973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2062629973
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3647439148
Short name T302
Test name
Test status
Simulation time 9570134858 ps
CPU time 173.57 seconds
Started Apr 02 01:42:29 PM PDT 24
Finished Apr 02 01:45:23 PM PDT 24
Peak memory 217440 kb
Host smart-572bc5cf-9123-4345-bbbc-b50629950608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647439148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3647439148
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2505509622
Short name T209
Test name
Test status
Simulation time 3900358089 ps
CPU time 98.9 seconds
Started Apr 02 01:43:12 PM PDT 24
Finished Apr 02 01:44:52 PM PDT 24
Peak memory 215612 kb
Host smart-edd6cfd8-2c96-4d6e-9b1d-e9bf5d4673af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505509622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2505509622
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1705426934
Short name T329
Test name
Test status
Simulation time 600893992 ps
CPU time 12.72 seconds
Started Apr 02 01:42:16 PM PDT 24
Finished Apr 02 01:42:28 PM PDT 24
Peak memory 222792 kb
Host smart-72f09780-4503-4928-bc7c-3cd650e1f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705426934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1705426934
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.36024982
Short name T165
Test name
Test status
Simulation time 904164050 ps
CPU time 5.03 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:44 PM PDT 24
Peak memory 219592 kb
Host smart-c424c2be-f187-40b8-9cb2-7ee1de81d5f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.36024982
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1964915751
Short name T162
Test name
Test status
Simulation time 319250570 ps
CPU time 10.94 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:53 PM PDT 24
Peak memory 209436 kb
Host smart-e22671a2-1bb7-467d-83fb-c19e0f38ea77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964915751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1964915751
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3859286863
Short name T152
Test name
Test status
Simulation time 173079254 ps
CPU time 3.96 seconds
Started Apr 02 01:44:22 PM PDT 24
Finished Apr 02 01:44:27 PM PDT 24
Peak memory 223068 kb
Host smart-3623f186-05f9-4b29-b425-5a2907ac4dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859286863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3859286863
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1412688163
Short name T154
Test name
Test status
Simulation time 90082312 ps
CPU time 2.36 seconds
Started Apr 02 01:41:53 PM PDT 24
Finished Apr 02 01:41:57 PM PDT 24
Peak memory 222956 kb
Host smart-57dffb73-1a49-4390-9f1e-9dc83c6414b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412688163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1412688163
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1906675873
Short name T259
Test name
Test status
Simulation time 1411829064 ps
CPU time 29.31 seconds
Started Apr 02 01:44:48 PM PDT 24
Finished Apr 02 01:45:19 PM PDT 24
Peak memory 217200 kb
Host smart-a6b3c0f2-f0cb-4f90-8c95-7c71d6bb19e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906675873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1906675873
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2179252757
Short name T69
Test name
Test status
Simulation time 1423123432 ps
CPU time 19.64 seconds
Started Apr 02 01:44:59 PM PDT 24
Finished Apr 02 01:45:19 PM PDT 24
Peak memory 216772 kb
Host smart-f9fbc782-8286-4945-a7f2-4d6cf4973c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179252757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2179252757
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2514403897
Short name T432
Test name
Test status
Simulation time 285215571 ps
CPU time 14.15 seconds
Started Apr 02 01:45:38 PM PDT 24
Finished Apr 02 01:45:52 PM PDT 24
Peak memory 214628 kb
Host smart-da761f58-fefd-4675-8b3e-01be292aeee0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514403897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2514403897
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3174585294
Short name T249
Test name
Test status
Simulation time 3280637513 ps
CPU time 28.13 seconds
Started Apr 02 01:46:25 PM PDT 24
Finished Apr 02 01:46:53 PM PDT 24
Peak memory 222980 kb
Host smart-54994123-a234-4200-8599-e9c2e2b430dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174585294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3174585294
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3798322260
Short name T245
Test name
Test status
Simulation time 13686917367 ps
CPU time 28 seconds
Started Apr 02 01:47:12 PM PDT 24
Finished Apr 02 01:47:40 PM PDT 24
Peak memory 222896 kb
Host smart-86cf1c33-3652-4088-926c-c2b19ed1d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798322260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3798322260
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2872180853
Short name T180
Test name
Test status
Simulation time 86466216 ps
CPU time 2.5 seconds
Started Apr 02 01:43:31 PM PDT 24
Finished Apr 02 01:43:33 PM PDT 24
Peak memory 210408 kb
Host smart-46b39fa0-07dd-4576-82c8-22d04facec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872180853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2872180853
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1070651775
Short name T93
Test name
Test status
Simulation time 243457201 ps
CPU time 7.58 seconds
Started Apr 02 01:43:37 PM PDT 24
Finished Apr 02 01:43:45 PM PDT 24
Peak memory 209276 kb
Host smart-c4a0f47e-25fe-46bc-9815-40dbb2334eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070651775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1070651775
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4232572486
Short name T177
Test name
Test status
Simulation time 2456825521 ps
CPU time 17.46 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:51 PM PDT 24
Peak memory 209416 kb
Host smart-7186157d-9ec5-4dec-a99b-5c11a519e25d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232572486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.4232572486
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2681201390
Short name T60
Test name
Test status
Simulation time 642548699 ps
CPU time 3.08 seconds
Started Apr 02 01:47:30 PM PDT 24
Finished Apr 02 01:47:33 PM PDT 24
Peak memory 223060 kb
Host smart-e35270d6-4674-4054-9fe2-87cce8526734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681201390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2681201390
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2971910138
Short name T268
Test name
Test status
Simulation time 4704709590 ps
CPU time 102.35 seconds
Started Apr 02 01:41:35 PM PDT 24
Finished Apr 02 01:43:18 PM PDT 24
Peak memory 217296 kb
Host smart-12c8ad50-50cf-412a-bd74-01052a56a4bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971910138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2971910138
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.239000751
Short name T389
Test name
Test status
Simulation time 108230009 ps
CPU time 2.71 seconds
Started Apr 02 01:41:51 PM PDT 24
Finished Apr 02 01:41:54 PM PDT 24
Peak memory 214604 kb
Host smart-84336233-aaf7-4412-84ba-94385cce3192
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239000751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.239000751
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_random.795066194
Short name T88
Test name
Test status
Simulation time 2346636813 ps
CPU time 8.35 seconds
Started Apr 02 01:45:03 PM PDT 24
Finished Apr 02 01:45:11 PM PDT 24
Peak memory 208620 kb
Host smart-67e63916-68d7-4426-aaca-8e16e2058989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795066194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.795066194
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2137125325
Short name T398
Test name
Test status
Simulation time 388107643 ps
CPU time 4.92 seconds
Started Apr 02 01:45:14 PM PDT 24
Finished Apr 02 01:45:19 PM PDT 24
Peak memory 222808 kb
Host smart-4820d9e6-48e1-4f18-89ef-bc3c0e183801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137125325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2137125325
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1621904864
Short name T376
Test name
Test status
Simulation time 162952686 ps
CPU time 5.03 seconds
Started Apr 02 01:42:34 PM PDT 24
Finished Apr 02 01:42:39 PM PDT 24
Peak memory 215140 kb
Host smart-16974e03-7a38-4439-b95d-caea50ecf35c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621904864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1621904864
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2835817662
Short name T178
Test name
Test status
Simulation time 458801580 ps
CPU time 7.55 seconds
Started Apr 02 12:30:40 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 213908 kb
Host smart-1aa8a692-2509-416b-95d0-e5d8ea83ff17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835817662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2835817662
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2627042284
Short name T175
Test name
Test status
Simulation time 185873252 ps
CPU time 6.62 seconds
Started Apr 02 12:31:00 PM PDT 24
Finished Apr 02 12:31:06 PM PDT 24
Peak memory 213852 kb
Host smart-cded094c-7bad-490b-a030-b3386487a05e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627042284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2627042284
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2606682720
Short name T76
Test name
Test status
Simulation time 278945856 ps
CPU time 12.61 seconds
Started Apr 02 01:44:39 PM PDT 24
Finished Apr 02 01:44:52 PM PDT 24
Peak memory 221252 kb
Host smart-cff3d10b-cbac-491f-a4a1-88a8d9861056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606682720 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2606682720
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2272064972
Short name T363
Test name
Test status
Simulation time 359001539 ps
CPU time 3.58 seconds
Started Apr 02 01:43:47 PM PDT 24
Finished Apr 02 01:43:51 PM PDT 24
Peak memory 211700 kb
Host smart-97c6d623-7fde-4561-adf2-766437119856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272064972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2272064972
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.805271157
Short name T501
Test name
Test status
Simulation time 625170049 ps
CPU time 17.78 seconds
Started Apr 02 01:43:58 PM PDT 24
Finished Apr 02 01:44:16 PM PDT 24
Peak memory 211028 kb
Host smart-56111e21-a631-4473-81bc-f77ca671afc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805271157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.805271157
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1465016023
Short name T664
Test name
Test status
Simulation time 473451185 ps
CPU time 3.73 seconds
Started Apr 02 01:44:21 PM PDT 24
Finished Apr 02 01:44:25 PM PDT 24
Peak memory 222900 kb
Host smart-7b6540a5-7b02-4261-ad1a-dfc0b6a663e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465016023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1465016023
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3182762703
Short name T597
Test name
Test status
Simulation time 7422803099 ps
CPU time 56.55 seconds
Started Apr 02 01:45:16 PM PDT 24
Finished Apr 02 01:46:13 PM PDT 24
Peak memory 215224 kb
Host smart-1a6b5730-37a6-4584-b9b3-8cd4decc60ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182762703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3182762703
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3001590358
Short name T418
Test name
Test status
Simulation time 528314602 ps
CPU time 3.72 seconds
Started Apr 02 01:46:19 PM PDT 24
Finished Apr 02 01:46:23 PM PDT 24
Peak memory 208944 kb
Host smart-efb23cf4-ad9a-429a-acb2-7a9100581458
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001590358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3001590358
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3708408156
Short name T360
Test name
Test status
Simulation time 89968999 ps
CPU time 3.97 seconds
Started Apr 02 01:46:49 PM PDT 24
Finished Apr 02 01:46:53 PM PDT 24
Peak memory 215524 kb
Host smart-4ae53063-826c-41e1-bfbe-f5a0bdb0252a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708408156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3708408156
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2355924348
Short name T228
Test name
Test status
Simulation time 332243934 ps
CPU time 10.28 seconds
Started Apr 02 01:46:50 PM PDT 24
Finished Apr 02 01:47:01 PM PDT 24
Peak memory 214616 kb
Host smart-a0edec13-f4b4-45ff-a6bb-a54110437ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355924348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2355924348
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1343427147
Short name T372
Test name
Test status
Simulation time 2156096286 ps
CPU time 13.95 seconds
Started Apr 02 01:47:10 PM PDT 24
Finished Apr 02 01:47:24 PM PDT 24
Peak memory 216440 kb
Host smart-05913b5f-9d18-4f4d-95f7-0b5b4558d2da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343427147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1343427147
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.34283793
Short name T395
Test name
Test status
Simulation time 1008452126 ps
CPU time 6.01 seconds
Started Apr 02 01:47:15 PM PDT 24
Finished Apr 02 01:47:21 PM PDT 24
Peak memory 214664 kb
Host smart-bced8dd6-055a-4227-9c9b-d2e7d4044fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34283793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.34283793
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2349687198
Short name T364
Test name
Test status
Simulation time 224453152 ps
CPU time 4.02 seconds
Started Apr 02 01:47:18 PM PDT 24
Finished Apr 02 01:47:22 PM PDT 24
Peak memory 222836 kb
Host smart-c0b0bd56-cf3c-4b75-a9e7-13b071c9ad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349687198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2349687198
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2103696686
Short name T316
Test name
Test status
Simulation time 1898819532 ps
CPU time 54.16 seconds
Started Apr 02 01:42:35 PM PDT 24
Finished Apr 02 01:43:29 PM PDT 24
Peak memory 222764 kb
Host smart-387785bf-9bfc-4cdf-8ac1-350714f0c117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103696686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2103696686
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.735058927
Short name T183
Test name
Test status
Simulation time 57559745 ps
CPU time 3.4 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:11 PM PDT 24
Peak memory 209188 kb
Host smart-1f051470-dabb-4bba-b9cb-dc133dc4d9d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735058927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
735058927
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2500517152
Short name T12
Test name
Test status
Simulation time 686170770 ps
CPU time 14.88 seconds
Started Apr 02 01:41:34 PM PDT 24
Finished Apr 02 01:41:50 PM PDT 24
Peak memory 234848 kb
Host smart-6681a3c7-f390-4e1d-9a1e-c64bf4320557
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500517152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2500517152
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2770688588
Short name T20
Test name
Test status
Simulation time 46225546 ps
CPU time 2.71 seconds
Started Apr 02 01:44:34 PM PDT 24
Finished Apr 02 01:44:37 PM PDT 24
Peak memory 223064 kb
Host smart-97bfc2c8-f23a-4fca-845c-faacc22e50e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770688588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2770688588
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3957990875
Short name T153
Test name
Test status
Simulation time 263837494 ps
CPU time 3.5 seconds
Started Apr 02 01:42:06 PM PDT 24
Finished Apr 02 01:42:10 PM PDT 24
Peak memory 217768 kb
Host smart-79ff51be-c57a-437f-a700-078a176d4eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957990875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3957990875
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3906909308
Short name T44
Test name
Test status
Simulation time 185242873 ps
CPU time 3.29 seconds
Started Apr 02 01:46:47 PM PDT 24
Finished Apr 02 01:46:50 PM PDT 24
Peak memory 217872 kb
Host smart-73f55918-1dc3-47da-9663-39541d9e9f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906909308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3906909308
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3506936667
Short name T903
Test name
Test status
Simulation time 762401559 ps
CPU time 10.12 seconds
Started Apr 02 12:30:57 PM PDT 24
Finished Apr 02 12:31:07 PM PDT 24
Peak memory 205764 kb
Host smart-ba679ae9-6014-4579-965a-e627f2e899de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506936667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
506936667
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/default/0.keymgr_sideload.4047716684
Short name T129
Test name
Test status
Simulation time 22953576 ps
CPU time 1.87 seconds
Started Apr 02 01:41:26 PM PDT 24
Finished Apr 02 01:41:28 PM PDT 24
Peak memory 207032 kb
Host smart-ce2c5359-88af-4a77-9b1c-760eb2a54c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047716684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.4047716684
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.927808428
Short name T396
Test name
Test status
Simulation time 387002495 ps
CPU time 4.38 seconds
Started Apr 02 01:43:15 PM PDT 24
Finished Apr 02 01:43:20 PM PDT 24
Peak memory 209616 kb
Host smart-0dcc3ac7-b585-43e2-8691-e7e76dda6f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927808428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.927808428
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2430084487
Short name T101
Test name
Test status
Simulation time 102367261 ps
CPU time 4.5 seconds
Started Apr 02 01:43:31 PM PDT 24
Finished Apr 02 01:43:36 PM PDT 24
Peak memory 210152 kb
Host smart-73477d63-0b52-4be8-87d7-474b6d20a935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430084487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2430084487
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1062467612
Short name T330
Test name
Test status
Simulation time 537827892 ps
CPU time 6.43 seconds
Started Apr 02 01:43:32 PM PDT 24
Finished Apr 02 01:43:39 PM PDT 24
Peak memory 214632 kb
Host smart-ca0d6d0f-acf7-4aa1-b110-a47b6fe9236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062467612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1062467612
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2746563091
Short name T23
Test name
Test status
Simulation time 68896771 ps
CPU time 1.93 seconds
Started Apr 02 01:43:56 PM PDT 24
Finished Apr 02 01:43:58 PM PDT 24
Peak memory 223144 kb
Host smart-72b482d6-e12c-4b65-a8af-9423f3f328af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746563091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2746563091
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2682290108
Short name T338
Test name
Test status
Simulation time 37698623 ps
CPU time 2.56 seconds
Started Apr 02 01:43:53 PM PDT 24
Finished Apr 02 01:43:56 PM PDT 24
Peak memory 214696 kb
Host smart-824dd909-cda0-4574-8111-98e983b66f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682290108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2682290108
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2214530333
Short name T270
Test name
Test status
Simulation time 177132217 ps
CPU time 3.32 seconds
Started Apr 02 01:43:59 PM PDT 24
Finished Apr 02 01:44:02 PM PDT 24
Peak memory 214680 kb
Host smart-0be97e14-fb58-4460-87ee-c790f18dc614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214530333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2214530333
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2112599812
Short name T341
Test name
Test status
Simulation time 78258609 ps
CPU time 4.58 seconds
Started Apr 02 01:44:10 PM PDT 24
Finished Apr 02 01:44:15 PM PDT 24
Peak memory 215480 kb
Host smart-65856cf4-c1ab-423b-a650-3a97c00571bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112599812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2112599812
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2459975832
Short name T264
Test name
Test status
Simulation time 16212490100 ps
CPU time 45.99 seconds
Started Apr 02 01:44:13 PM PDT 24
Finished Apr 02 01:45:00 PM PDT 24
Peak memory 222888 kb
Host smart-ccd54bc7-b872-4d8c-beac-ce0a0db5083c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459975832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2459975832
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.474332910
Short name T638
Test name
Test status
Simulation time 1006925024 ps
CPU time 9.31 seconds
Started Apr 02 01:44:10 PM PDT 24
Finished Apr 02 01:44:19 PM PDT 24
Peak memory 210848 kb
Host smart-48615880-4498-48a0-9ff2-1fd205a20a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474332910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.474332910
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2378583120
Short name T335
Test name
Test status
Simulation time 61961720 ps
CPU time 4 seconds
Started Apr 02 01:41:53 PM PDT 24
Finished Apr 02 01:41:58 PM PDT 24
Peak memory 211060 kb
Host smart-677262e3-63d0-426b-be0d-92488a4f6097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378583120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2378583120
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3750963753
Short name T277
Test name
Test status
Simulation time 71787184 ps
CPU time 4.27 seconds
Started Apr 02 01:44:55 PM PDT 24
Finished Apr 02 01:44:59 PM PDT 24
Peak memory 222704 kb
Host smart-62014a94-1fd2-4dd8-9637-685c0318f11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750963753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3750963753
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1343653975
Short name T81
Test name
Test status
Simulation time 22524230190 ps
CPU time 197.82 seconds
Started Apr 02 01:45:15 PM PDT 24
Finished Apr 02 01:48:32 PM PDT 24
Peak memory 223008 kb
Host smart-d20e7173-4caa-4ea6-aad4-4e983479bb77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343653975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1343653975
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2733644407
Short name T198
Test name
Test status
Simulation time 770282140 ps
CPU time 6.82 seconds
Started Apr 02 01:46:07 PM PDT 24
Finished Apr 02 01:46:14 PM PDT 24
Peak memory 217788 kb
Host smart-de03d8a0-3863-4423-943d-2b7d75c501b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733644407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2733644407
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.499265209
Short name T392
Test name
Test status
Simulation time 3798899786 ps
CPU time 15.41 seconds
Started Apr 02 01:46:09 PM PDT 24
Finished Apr 02 01:46:25 PM PDT 24
Peak memory 210964 kb
Host smart-59249923-76f8-4089-983e-249c69d30184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499265209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.499265209
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2227719280
Short name T203
Test name
Test status
Simulation time 438100016 ps
CPU time 6.47 seconds
Started Apr 02 01:46:34 PM PDT 24
Finished Apr 02 01:46:40 PM PDT 24
Peak memory 211064 kb
Host smart-c5dbb79d-f5ec-4b0f-bd11-ddb7ff60f0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227719280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2227719280
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.99557928
Short name T222
Test name
Test status
Simulation time 430317789 ps
CPU time 15.19 seconds
Started Apr 02 01:46:52 PM PDT 24
Finished Apr 02 01:47:07 PM PDT 24
Peak memory 217308 kb
Host smart-a352deba-ce5e-45d0-a8d2-1704fcc72fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99557928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.99557928
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3877004722
Short name T265
Test name
Test status
Simulation time 231267361 ps
CPU time 3 seconds
Started Apr 02 01:42:18 PM PDT 24
Finished Apr 02 01:42:22 PM PDT 24
Peak memory 210136 kb
Host smart-e8805b16-3da6-4e10-97d7-98a43e3025f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877004722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3877004722
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3971693287
Short name T390
Test name
Test status
Simulation time 158501733 ps
CPU time 4.54 seconds
Started Apr 02 01:47:08 PM PDT 24
Finished Apr 02 01:47:13 PM PDT 24
Peak memory 214964 kb
Host smart-bfae0719-3d21-4d52-ba6a-fec643a07e85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971693287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3971693287
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2052898559
Short name T269
Test name
Test status
Simulation time 287934734 ps
CPU time 4.76 seconds
Started Apr 02 01:42:57 PM PDT 24
Finished Apr 02 01:43:02 PM PDT 24
Peak memory 210248 kb
Host smart-e35aa36b-ee18-4fe4-81d6-58cdf155ebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052898559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2052898559
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3379954632
Short name T157
Test name
Test status
Simulation time 123844466 ps
CPU time 4.39 seconds
Started Apr 02 01:45:05 PM PDT 24
Finished Apr 02 01:45:10 PM PDT 24
Peak memory 217924 kb
Host smart-8e664632-9e5a-4265-9cf9-f4d567222778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379954632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3379954632
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1549786419
Short name T156
Test name
Test status
Simulation time 49944036 ps
CPU time 2.78 seconds
Started Apr 02 01:47:16 PM PDT 24
Finished Apr 02 01:47:19 PM PDT 24
Peak memory 223016 kb
Host smart-6001aeb4-b32a-4d80-ae3f-5271ef77d56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549786419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1549786419
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1797404068
Short name T918
Test name
Test status
Simulation time 136750731 ps
CPU time 6.03 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 205784 kb
Host smart-0328d447-a92a-49c2-aa47-e3db6b190e22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797404068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
797404068
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1335322063
Short name T942
Test name
Test status
Simulation time 65933131 ps
CPU time 1.23 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205680 kb
Host smart-816bb1a4-e4f9-4b2d-bb47-3702c005f321
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335322063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
335322063
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3104998918
Short name T943
Test name
Test status
Simulation time 111555506 ps
CPU time 1.84 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 218688 kb
Host smart-daa5531f-6610-436d-9a2d-7564ca23f433
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104998918 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3104998918
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4181578696
Short name T1045
Test name
Test status
Simulation time 43870986 ps
CPU time 0.79 seconds
Started Apr 02 12:30:40 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 205436 kb
Host smart-dadd15ac-6102-4d8d-9a21-b4406bd80b57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181578696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4181578696
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.770540294
Short name T979
Test name
Test status
Simulation time 34755643 ps
CPU time 0.79 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 205192 kb
Host smart-a1c63d16-69b1-4db8-861c-bab62b07003e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770540294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.770540294
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3727471064
Short name T1038
Test name
Test status
Simulation time 263830216 ps
CPU time 2.42 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 205552 kb
Host smart-32103f8a-5313-464c-a794-672a3e43da41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727471064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3727471064
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.296302916
Short name T1015
Test name
Test status
Simulation time 209611531 ps
CPU time 8.93 seconds
Started Apr 02 12:30:46 PM PDT 24
Finished Apr 02 12:30:55 PM PDT 24
Peak memory 214232 kb
Host smart-f6f37137-0d4e-4985-83d0-8674ad079d12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296302916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.296302916
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.505921529
Short name T961
Test name
Test status
Simulation time 102344701 ps
CPU time 2.28 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 214068 kb
Host smart-83ddd1dd-6c16-468d-baa6-22eadc40a426
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505921529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.505921529
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3258221313
Short name T1032
Test name
Test status
Simulation time 264639319 ps
CPU time 8.73 seconds
Started Apr 02 12:31:09 PM PDT 24
Finished Apr 02 12:31:18 PM PDT 24
Peak memory 205760 kb
Host smart-ec8482b6-bbc8-4226-9416-fcc6c52ad1b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258221313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
258221313
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.29542643
Short name T981
Test name
Test status
Simulation time 12761553660 ps
CPU time 24.14 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:31:00 PM PDT 24
Peak memory 205908 kb
Host smart-18a532b4-fd7e-4381-b95e-1e698a923708
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29542643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.29542643
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.301030178
Short name T923
Test name
Test status
Simulation time 66172986 ps
CPU time 1.21 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:44 PM PDT 24
Peak memory 205628 kb
Host smart-77c952aa-1584-45fe-acd3-4f1d6d946486
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301030178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.301030178
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2370092006
Short name T1056
Test name
Test status
Simulation time 201903372 ps
CPU time 2.16 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 213904 kb
Host smart-4968f63a-a340-4b0f-a25b-c5d82a847dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370092006 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2370092006
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3153008917
Short name T1060
Test name
Test status
Simulation time 13248065 ps
CPU time 1.03 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:33 PM PDT 24
Peak memory 205608 kb
Host smart-10616082-ff7d-4ebf-94d6-ad0f35185af1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153008917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3153008917
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1418866653
Short name T959
Test name
Test status
Simulation time 11379457 ps
CPU time 0.8 seconds
Started Apr 02 12:31:01 PM PDT 24
Finished Apr 02 12:31:02 PM PDT 24
Peak memory 205468 kb
Host smart-3a700b0d-4f92-4cb3-a6c3-5c5ecc6dd023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418866653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1418866653
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3045753794
Short name T1052
Test name
Test status
Simulation time 109954679 ps
CPU time 2.4 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 205820 kb
Host smart-cd1fccb1-f7be-4168-80a5-56b9fa6e706f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045753794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3045753794
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.384066793
Short name T119
Test name
Test status
Simulation time 651786365 ps
CPU time 2.32 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:10 PM PDT 24
Peak memory 214276 kb
Host smart-81716144-df32-4b1d-8caf-6484ef8dd5d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384066793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.384066793
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2787249185
Short name T957
Test name
Test status
Simulation time 1313409268 ps
CPU time 6.84 seconds
Started Apr 02 12:30:43 PM PDT 24
Finished Apr 02 12:30:49 PM PDT 24
Peak memory 214288 kb
Host smart-b300e26c-e939-40ca-8400-2d33dd7f3423
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787249185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2787249185
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4277944339
Short name T199
Test name
Test status
Simulation time 147240396 ps
CPU time 3.99 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 214008 kb
Host smart-65667b1b-4c38-4674-a865-14cb0bf917b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277944339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4277944339
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4104775563
Short name T171
Test name
Test status
Simulation time 80900338 ps
CPU time 3.39 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 213816 kb
Host smart-6c09dbb1-277b-4801-8d80-0eaeaeb22a25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104775563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.4104775563
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1087247388
Short name T994
Test name
Test status
Simulation time 31912987 ps
CPU time 1.16 seconds
Started Apr 02 12:30:50 PM PDT 24
Finished Apr 02 12:30:51 PM PDT 24
Peak memory 205820 kb
Host smart-1a8d4e90-9b30-47cf-bedc-31d828e50b9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087247388 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1087247388
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4091447147
Short name T1034
Test name
Test status
Simulation time 32961290 ps
CPU time 0.9 seconds
Started Apr 02 12:30:40 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 205540 kb
Host smart-80e9c4b2-3dce-465b-af63-f62c0d30cb4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091447147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4091447147
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3533379104
Short name T967
Test name
Test status
Simulation time 15047113 ps
CPU time 0.75 seconds
Started Apr 02 12:30:53 PM PDT 24
Finished Apr 02 12:30:54 PM PDT 24
Peak memory 205332 kb
Host smart-430c9e4f-5e4c-493b-82ee-8c34d098bced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533379104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3533379104
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1132003788
Short name T1010
Test name
Test status
Simulation time 32504875 ps
CPU time 1.85 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205748 kb
Host smart-7fb15cbe-cc78-414b-ade4-66adb302bfc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132003788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1132003788
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4178222110
Short name T1054
Test name
Test status
Simulation time 1108263894 ps
CPU time 4.28 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 214212 kb
Host smart-ace01f92-aad9-4df9-b7ca-4dc15f25d37c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178222110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4178222110
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2172644538
Short name T121
Test name
Test status
Simulation time 170549417 ps
CPU time 3.8 seconds
Started Apr 02 12:31:13 PM PDT 24
Finished Apr 02 12:31:17 PM PDT 24
Peak memory 214288 kb
Host smart-b19ebf6f-ce54-445d-a3f3-164c03dc3254
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172644538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2172644538
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2114002832
Short name T978
Test name
Test status
Simulation time 675528382 ps
CPU time 2.46 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 213924 kb
Host smart-c7967ccd-e054-4dc3-87b2-92b9931ee8c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114002832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2114002832
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.4160228708
Short name T181
Test name
Test status
Simulation time 8997952586 ps
CPU time 41.76 seconds
Started Apr 02 12:30:53 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 216344 kb
Host smart-52167aec-490f-46ae-8124-83f8c3c59292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160228708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.4160228708
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2141109657
Short name T1026
Test name
Test status
Simulation time 38029327 ps
CPU time 1.23 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:50 PM PDT 24
Peak memory 204280 kb
Host smart-cdc69d7f-1729-4b0f-8cc5-93d176385980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141109657 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2141109657
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1807999191
Short name T1029
Test name
Test status
Simulation time 55579260 ps
CPU time 1.17 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 205640 kb
Host smart-8d1d4d39-0cc7-450b-8fb4-ab4d1c8be558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807999191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1807999191
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3947768425
Short name T990
Test name
Test status
Simulation time 31214201 ps
CPU time 0.79 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 205396 kb
Host smart-d8e94e9e-8ef0-4a14-a28b-c491294458a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947768425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3947768425
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.980863553
Short name T1001
Test name
Test status
Simulation time 58425932 ps
CPU time 2.52 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 205772 kb
Host smart-a4de4643-b8e4-4d6d-85f0-a426de122142
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980863553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.980863553
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2215209017
Short name T950
Test name
Test status
Simulation time 1407353320 ps
CPU time 6.02 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:49 PM PDT 24
Peak memory 214284 kb
Host smart-4d98cc5c-0946-4240-8402-dff7f7d3fe96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215209017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2215209017
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2352902477
Short name T1007
Test name
Test status
Simulation time 1282778566 ps
CPU time 6.49 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 220200 kb
Host smart-cadb3cf4-528d-44c4-b9d9-596cbba0db9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352902477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2352902477
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3977005174
Short name T983
Test name
Test status
Simulation time 152825932 ps
CPU time 2.38 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 215056 kb
Host smart-60f26bb7-4b5b-4000-9a9c-b5842b0c50ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977005174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3977005174
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3043591777
Short name T1040
Test name
Test status
Simulation time 536262499 ps
CPU time 11.23 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:49 PM PDT 24
Peak memory 213744 kb
Host smart-c0dc2cd0-db6f-471d-bf1d-f808186c6c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043591777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3043591777
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.441349477
Short name T1042
Test name
Test status
Simulation time 53267980 ps
CPU time 1.56 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205796 kb
Host smart-b6de3065-bc8a-43e5-8018-e3b28e09daf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441349477 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.441349477
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1324288522
Short name T937
Test name
Test status
Simulation time 69565116 ps
CPU time 0.92 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 205496 kb
Host smart-dc3bdffc-564e-4fa2-9659-9181b3468fcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324288522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1324288522
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3910207517
Short name T948
Test name
Test status
Simulation time 11815212 ps
CPU time 0.71 seconds
Started Apr 02 12:30:46 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 205488 kb
Host smart-185f1a80-c3c1-48f2-b420-053f1a0c896c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910207517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3910207517
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.985868758
Short name T931
Test name
Test status
Simulation time 92007541 ps
CPU time 2.5 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205768 kb
Host smart-ae382a52-a0b4-493d-9cc9-37f746ef3916
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985868758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.985868758
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2707645926
Short name T940
Test name
Test status
Simulation time 170866083 ps
CPU time 3.19 seconds
Started Apr 02 12:31:49 PM PDT 24
Finished Apr 02 12:31:52 PM PDT 24
Peak memory 212684 kb
Host smart-0a959898-bf8b-4642-b379-2d8622180240
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707645926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2707645926
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2494827926
Short name T954
Test name
Test status
Simulation time 359332238 ps
CPU time 7.54 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:46 PM PDT 24
Peak memory 214312 kb
Host smart-c73c2e78-b3ae-4c84-94b3-9ac6b227e1bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494827926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2494827926
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1158661517
Short name T968
Test name
Test status
Simulation time 101191631 ps
CPU time 2.14 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 214020 kb
Host smart-80c13f9b-2394-4ab1-92d6-01e28a4e289f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158661517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1158661517
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.516352663
Short name T1053
Test name
Test status
Simulation time 295669076 ps
CPU time 1.64 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 214100 kb
Host smart-9a4318f4-93d2-4ba6-9fc0-f1ee1deeaf2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516352663 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.516352663
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2289047533
Short name T1020
Test name
Test status
Simulation time 15754377 ps
CPU time 1.16 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 205760 kb
Host smart-bfadc689-0786-4509-9d3d-c4344bf60439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289047533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2289047533
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4169387341
Short name T935
Test name
Test status
Simulation time 21275560 ps
CPU time 0.74 seconds
Started Apr 02 12:30:52 PM PDT 24
Finished Apr 02 12:30:53 PM PDT 24
Peak memory 205400 kb
Host smart-f8d2c96a-b691-4917-a247-def0a7bb6391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169387341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4169387341
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1292217598
Short name T1049
Test name
Test status
Simulation time 144229097 ps
CPU time 2.73 seconds
Started Apr 02 12:30:48 PM PDT 24
Finished Apr 02 12:30:51 PM PDT 24
Peak memory 205712 kb
Host smart-5fd8f37c-d8b7-47c1-a8d6-d4641065a03e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292217598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1292217598
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1308574109
Short name T1044
Test name
Test status
Simulation time 477291948 ps
CPU time 3.48 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 214388 kb
Host smart-4bb584a3-f539-4fa8-a9b1-a39d575c7379
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308574109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1308574109
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2990704873
Short name T927
Test name
Test status
Simulation time 234273461 ps
CPU time 5.08 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 220760 kb
Host smart-9cf617c7-bf8f-475b-8320-a1af913bf530
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990704873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2990704873
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.374973234
Short name T908
Test name
Test status
Simulation time 616552837 ps
CPU time 4.21 seconds
Started Apr 02 12:31:05 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 217108 kb
Host smart-55096bdb-edf8-44a3-a726-8907300989f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374973234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.374973234
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.957033682
Short name T179
Test name
Test status
Simulation time 1078041001 ps
CPU time 5.23 seconds
Started Apr 02 12:31:04 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 209248 kb
Host smart-504e99cf-4f80-4e78-9288-c9a99d5e69f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957033682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.957033682
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1726677375
Short name T926
Test name
Test status
Simulation time 160382191 ps
CPU time 1.46 seconds
Started Apr 02 12:30:55 PM PDT 24
Finished Apr 02 12:30:57 PM PDT 24
Peak memory 213908 kb
Host smart-94f07980-e87e-4e0b-a190-87f7088f1d98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726677375 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1726677375
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1984021959
Short name T963
Test name
Test status
Simulation time 35068372 ps
CPU time 0.92 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 205524 kb
Host smart-24fa7138-426b-44a3-a4de-4d40cb63f68a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984021959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1984021959
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.632200784
Short name T897
Test name
Test status
Simulation time 17297988 ps
CPU time 0.71 seconds
Started Apr 02 12:30:54 PM PDT 24
Finished Apr 02 12:30:55 PM PDT 24
Peak memory 205296 kb
Host smart-25ac857d-0850-43fa-80f6-0667d641c8e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632200784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.632200784
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.434255341
Short name T993
Test name
Test status
Simulation time 100478761 ps
CPU time 2.61 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 205832 kb
Host smart-c8bc5148-cbd2-412a-ab01-887e8ab0ac5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434255341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.434255341
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2183669813
Short name T117
Test name
Test status
Simulation time 209837815 ps
CPU time 4.86 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:12 PM PDT 24
Peak memory 214180 kb
Host smart-200a4bf4-90b9-4205-8cfd-9ab2632d4869
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183669813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2183669813
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1044496517
Short name T116
Test name
Test status
Simulation time 148058546 ps
CPU time 7.96 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 214088 kb
Host smart-9eaf6e08-4846-48c4-a778-69e91adb9d94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044496517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1044496517
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1902769842
Short name T916
Test name
Test status
Simulation time 27712053 ps
CPU time 1.72 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 213940 kb
Host smart-70b0aa78-09ac-404e-96b4-879a5ad1b464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902769842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1902769842
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1177764519
Short name T189
Test name
Test status
Simulation time 117430217 ps
CPU time 1.13 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 205804 kb
Host smart-348adf30-3f5f-412a-8fa4-4ce8a571035f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177764519 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1177764519
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.494385144
Short name T956
Test name
Test status
Simulation time 16031253 ps
CPU time 1.09 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 205760 kb
Host smart-99d7ab13-2b29-4d70-9f3f-7f7e526d09be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494385144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.494385144
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3799693953
Short name T1039
Test name
Test status
Simulation time 15915665 ps
CPU time 0.9 seconds
Started Apr 02 12:30:55 PM PDT 24
Finished Apr 02 12:30:56 PM PDT 24
Peak memory 205608 kb
Host smart-3202de69-e899-4c9a-b7e4-e801a06b301f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799693953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3799693953
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3108180018
Short name T1014
Test name
Test status
Simulation time 50219913 ps
CPU time 1.63 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 205756 kb
Host smart-9f2d07a6-faea-4690-ad3a-83e6699d65c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108180018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3108180018
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.752201679
Short name T945
Test name
Test status
Simulation time 384464637 ps
CPU time 2.35 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 214180 kb
Host smart-88778104-89df-4f8d-80db-0c20e0b44f0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752201679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.752201679
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2652248579
Short name T110
Test name
Test status
Simulation time 228913536 ps
CPU time 4.57 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 214216 kb
Host smart-815d35f6-4028-4aae-981b-d3f5293f1154
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652248579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2652248579
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2800159229
Short name T1036
Test name
Test status
Simulation time 124522714 ps
CPU time 2.17 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 214032 kb
Host smart-39b56b27-269e-4044-91d6-4a04fa58279f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800159229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2800159229
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4164491627
Short name T161
Test name
Test status
Simulation time 173713552 ps
CPU time 5.12 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 213968 kb
Host smart-2cd9e053-a81a-4557-bd2b-0db94dae636f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164491627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4164491627
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.191593003
Short name T939
Test name
Test status
Simulation time 35294691 ps
CPU time 1.22 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 214052 kb
Host smart-fd28ae09-23df-4a2a-a814-8e36ea4039ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191593003 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.191593003
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2867474429
Short name T953
Test name
Test status
Simulation time 28189890 ps
CPU time 1.19 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205704 kb
Host smart-ed42c8c2-c57e-4fe7-a12c-65a8eb7bf462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867474429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2867474429
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3106099441
Short name T1031
Test name
Test status
Simulation time 28446162 ps
CPU time 0.75 seconds
Started Apr 02 12:30:59 PM PDT 24
Finished Apr 02 12:31:00 PM PDT 24
Peak memory 205440 kb
Host smart-2737a66a-44b0-45bd-947f-978a5cbaacaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106099441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3106099441
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.950867616
Short name T921
Test name
Test status
Simulation time 88490758 ps
CPU time 2.67 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 205792 kb
Host smart-e9fc0ffc-1acf-463f-80fb-d36020bc44ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950867616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.950867616
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3409159866
Short name T118
Test name
Test status
Simulation time 311947959 ps
CPU time 3.02 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 214232 kb
Host smart-c7cb31b2-6cd3-4317-87d8-c90701a67dcb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409159866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3409159866
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3095607858
Short name T1012
Test name
Test status
Simulation time 232857553 ps
CPU time 6.62 seconds
Started Apr 02 12:30:47 PM PDT 24
Finished Apr 02 12:30:54 PM PDT 24
Peak memory 214376 kb
Host smart-62253732-f26a-4fea-9a03-1de48602377b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095607858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3095607858
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.471781467
Short name T971
Test name
Test status
Simulation time 167315464 ps
CPU time 4.84 seconds
Started Apr 02 12:31:09 PM PDT 24
Finished Apr 02 12:31:14 PM PDT 24
Peak memory 213940 kb
Host smart-72a35778-afac-4580-abe3-53871b00b7d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471781467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.471781467
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2992619865
Short name T174
Test name
Test status
Simulation time 841145883 ps
CPU time 25.23 seconds
Started Apr 02 12:31:00 PM PDT 24
Finished Apr 02 12:31:25 PM PDT 24
Peak memory 213840 kb
Host smart-8311d615-c288-4c6a-8b12-dd8241982be0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992619865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2992619865
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2977008863
Short name T1021
Test name
Test status
Simulation time 66020419 ps
CPU time 1.53 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 214280 kb
Host smart-3cf2d061-09c9-4a32-9416-62ddcbd79a15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977008863 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2977008863
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1507734468
Short name T1028
Test name
Test status
Simulation time 47308615 ps
CPU time 1.41 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 205344 kb
Host smart-842aeafe-991d-4ce4-a739-583947f03ecf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507734468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1507734468
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.640682427
Short name T941
Test name
Test status
Simulation time 41463799 ps
CPU time 0.73 seconds
Started Apr 02 12:30:40 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 205384 kb
Host smart-0a342438-a232-4395-99aa-139d7ccd394d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640682427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.640682427
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3331930860
Short name T915
Test name
Test status
Simulation time 305016115 ps
CPU time 2.6 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 205832 kb
Host smart-3a926324-9088-4cdc-ba2d-f2e02d8d419d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331930860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3331930860
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2413894678
Short name T980
Test name
Test status
Simulation time 103081578 ps
CPU time 3.07 seconds
Started Apr 02 12:31:01 PM PDT 24
Finished Apr 02 12:31:04 PM PDT 24
Peak memory 218920 kb
Host smart-e0b45736-3b77-439b-af34-79efec53117a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413894678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2413894678
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.525891171
Short name T952
Test name
Test status
Simulation time 843340024 ps
CPU time 13.98 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:48 PM PDT 24
Peak memory 214368 kb
Host smart-4bd3f99d-6fbf-4ea2-a07e-63d868396928
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525891171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.525891171
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3306232435
Short name T1018
Test name
Test status
Simulation time 556462106 ps
CPU time 3.83 seconds
Started Apr 02 12:30:44 PM PDT 24
Finished Apr 02 12:30:48 PM PDT 24
Peak memory 214072 kb
Host smart-3ed28969-0fe4-43e7-8657-e38a18ce65aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306232435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3306232435
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1580950818
Short name T188
Test name
Test status
Simulation time 653590555 ps
CPU time 4.9 seconds
Started Apr 02 12:31:19 PM PDT 24
Finished Apr 02 12:31:24 PM PDT 24
Peak memory 209276 kb
Host smart-57fe8c32-9064-49bf-a7cc-bad81013d445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580950818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1580950818
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1631430924
Short name T919
Test name
Test status
Simulation time 27210442 ps
CPU time 1.43 seconds
Started Apr 02 12:30:46 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 213944 kb
Host smart-a2bc6e90-1eae-48c6-afc6-f6e172a1bf89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631430924 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1631430924
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1934576595
Short name T1008
Test name
Test status
Simulation time 22433788 ps
CPU time 0.9 seconds
Started Apr 02 12:30:46 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 205536 kb
Host smart-600f8a92-af4e-40d2-8ff4-93210292cd21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934576595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1934576595
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3814099281
Short name T947
Test name
Test status
Simulation time 47701303 ps
CPU time 0.77 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 205444 kb
Host smart-a637342d-21a7-4deb-b4fe-9377bf759c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814099281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3814099281
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.190302367
Short name T1063
Test name
Test status
Simulation time 119168612 ps
CPU time 2.27 seconds
Started Apr 02 12:31:19 PM PDT 24
Finished Apr 02 12:31:22 PM PDT 24
Peak memory 205784 kb
Host smart-9add4a27-5fb8-4d8b-8900-a17da0ec4a35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190302367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.190302367
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1851047706
Short name T946
Test name
Test status
Simulation time 329107848 ps
CPU time 5.37 seconds
Started Apr 02 12:30:40 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 214212 kb
Host smart-e173e380-659e-432a-9459-c71c89cf4996
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851047706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1851047706
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.665112491
Short name T111
Test name
Test status
Simulation time 251280245 ps
CPU time 7.96 seconds
Started Apr 02 12:30:46 PM PDT 24
Finished Apr 02 12:30:54 PM PDT 24
Peak memory 214316 kb
Host smart-8b5a2b64-b88a-4d83-9e33-6cdcba008350
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665112491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.665112491
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1698198834
Short name T977
Test name
Test status
Simulation time 535447854 ps
CPU time 2.06 seconds
Started Apr 02 12:30:54 PM PDT 24
Finished Apr 02 12:30:56 PM PDT 24
Peak memory 214004 kb
Host smart-147c411c-a9d3-4e94-a7b8-04e6ab585ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698198834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1698198834
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2320254177
Short name T1016
Test name
Test status
Simulation time 110783915 ps
CPU time 3.19 seconds
Started Apr 02 12:31:14 PM PDT 24
Finished Apr 02 12:31:17 PM PDT 24
Peak memory 213964 kb
Host smart-8bc369ff-3316-480c-95ce-c316eb8bded5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320254177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2320254177
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2587498158
Short name T1046
Test name
Test status
Simulation time 75893454 ps
CPU time 1.62 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 213964 kb
Host smart-9fca735a-fa15-4ff1-87ae-900e856a6344
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587498158 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2587498158
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.4253275446
Short name T949
Test name
Test status
Simulation time 114687224 ps
CPU time 1.56 seconds
Started Apr 02 12:31:11 PM PDT 24
Finished Apr 02 12:31:13 PM PDT 24
Peak memory 205764 kb
Host smart-2db3bf65-fdf9-458e-b4b8-0a8109e33c23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253275446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4253275446
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4289933330
Short name T899
Test name
Test status
Simulation time 17364457 ps
CPU time 0.87 seconds
Started Apr 02 12:30:45 PM PDT 24
Finished Apr 02 12:30:46 PM PDT 24
Peak memory 205352 kb
Host smart-aaaac230-8611-451e-a1fe-9d299c49e906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289933330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4289933330
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3757323308
Short name T1013
Test name
Test status
Simulation time 119829508 ps
CPU time 4.29 seconds
Started Apr 02 12:30:53 PM PDT 24
Finished Apr 02 12:30:58 PM PDT 24
Peak memory 205648 kb
Host smart-3f4a0737-6171-4a7d-955b-42857bce13d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757323308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3757323308
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3410297427
Short name T1048
Test name
Test status
Simulation time 93937346 ps
CPU time 3.6 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 222456 kb
Host smart-871c5d8c-f179-4857-8aa4-3ad5ff8b72e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410297427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3410297427
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3486472092
Short name T1037
Test name
Test status
Simulation time 3429297785 ps
CPU time 9.68 seconds
Started Apr 02 12:30:43 PM PDT 24
Finished Apr 02 12:30:53 PM PDT 24
Peak memory 214136 kb
Host smart-6defb9c8-9d26-40e7-abfa-f58e5a894bea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486472092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3486472092
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.243742118
Short name T1055
Test name
Test status
Simulation time 125415407 ps
CPU time 3.99 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 213972 kb
Host smart-0e3f31f5-b66a-43dd-96d9-55b77987c9d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243742118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.243742118
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3875657986
Short name T1005
Test name
Test status
Simulation time 1558497599 ps
CPU time 5.58 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 205820 kb
Host smart-7bc8f269-6c56-47b8-bdc1-69556cd027c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875657986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
875657986
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3331756439
Short name T995
Test name
Test status
Simulation time 8012647834 ps
CPU time 21.12 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:58 PM PDT 24
Peak memory 206032 kb
Host smart-a19990f1-3337-49fa-8103-3eae1015f189
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331756439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
331756439
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2291068290
Short name T1062
Test name
Test status
Simulation time 13863742 ps
CPU time 1.01 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 205740 kb
Host smart-858785b1-acfa-486b-84ee-8007ed696e94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291068290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
291068290
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.330824383
Short name T1047
Test name
Test status
Simulation time 18096592 ps
CPU time 1.5 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:44 PM PDT 24
Peak memory 214100 kb
Host smart-8a6318c3-551a-49f3-af98-1cbfe76ae14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330824383 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.330824383
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2406944044
Short name T958
Test name
Test status
Simulation time 10161290 ps
CPU time 0.97 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 205600 kb
Host smart-6f05a7bf-362d-44b0-9d9a-3cce2231c118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406944044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2406944044
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3782560831
Short name T904
Test name
Test status
Simulation time 16470210 ps
CPU time 0.82 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 205468 kb
Host smart-e73178cb-977e-4a10-b70c-6ab3392768e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782560831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3782560831
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.208704482
Short name T976
Test name
Test status
Simulation time 34417277 ps
CPU time 1.88 seconds
Started Apr 02 12:30:41 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 205800 kb
Host smart-f9ee4de7-b13c-4eb6-a38d-aa2735308fae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208704482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.208704482
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3502305368
Short name T992
Test name
Test status
Simulation time 68572449 ps
CPU time 2.23 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 214292 kb
Host smart-b8846e08-51db-446e-a480-83fd96ae1ba9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502305368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3502305368
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.55245682
Short name T1051
Test name
Test status
Simulation time 468649444 ps
CPU time 7.5 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:44 PM PDT 24
Peak memory 214272 kb
Host smart-12484142-7372-42c5-ae3e-b7762c6eddf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55245682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.ke
ymgr_shadow_reg_errors_with_csr_rw.55245682
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2753801912
Short name T895
Test name
Test status
Simulation time 42681336 ps
CPU time 2.43 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 213996 kb
Host smart-3b58bce7-02f2-468d-8414-1c2349612cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753801912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2753801912
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.878333851
Short name T170
Test name
Test status
Simulation time 525911086 ps
CPU time 10.21 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:53 PM PDT 24
Peak memory 213972 kb
Host smart-3f063892-0342-4296-9e6f-ad45cf1a6039
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878333851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
878333851
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2159192902
Short name T911
Test name
Test status
Simulation time 38508081 ps
CPU time 0.77 seconds
Started Apr 02 12:30:57 PM PDT 24
Finished Apr 02 12:30:58 PM PDT 24
Peak memory 205472 kb
Host smart-73719660-abde-4857-b61f-490ff367ca87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159192902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2159192902
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.88161687
Short name T898
Test name
Test status
Simulation time 15996941 ps
CPU time 0.94 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:10 PM PDT 24
Peak memory 205556 kb
Host smart-03aca085-bfca-4d8b-aa03-e3eb27e5af82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88161687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.88161687
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1854247167
Short name T1061
Test name
Test status
Simulation time 34173698 ps
CPU time 0.83 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 205488 kb
Host smart-a1a41320-4728-4dac-a9a0-fbf4ec31aad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854247167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1854247167
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.801160887
Short name T902
Test name
Test status
Simulation time 16215358 ps
CPU time 0.71 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 205388 kb
Host smart-15ffe170-6c98-4bac-9e3f-887db0186575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801160887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.801160887
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1710417978
Short name T962
Test name
Test status
Simulation time 17170135 ps
CPU time 0.82 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 205264 kb
Host smart-5d180fa7-3d1c-4440-87f8-ce9f02567aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710417978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1710417978
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1561611477
Short name T966
Test name
Test status
Simulation time 17442017 ps
CPU time 0.95 seconds
Started Apr 02 12:30:57 PM PDT 24
Finished Apr 02 12:30:58 PM PDT 24
Peak memory 205548 kb
Host smart-fd925987-6cd7-4b04-ae8a-1596aeae455e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561611477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1561611477
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3830745106
Short name T987
Test name
Test status
Simulation time 46738995 ps
CPU time 0.68 seconds
Started Apr 02 12:30:44 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 205368 kb
Host smart-e44fdc6e-af77-44a9-8f17-eaa3486bba14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830745106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3830745106
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2799095798
Short name T960
Test name
Test status
Simulation time 14521686 ps
CPU time 0.7 seconds
Started Apr 02 12:30:57 PM PDT 24
Finished Apr 02 12:30:58 PM PDT 24
Peak memory 205360 kb
Host smart-8e9f9d9c-0d29-49dc-94e6-6857f623da06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799095798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2799095798
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1503482716
Short name T920
Test name
Test status
Simulation time 10668154 ps
CPU time 0.7 seconds
Started Apr 02 12:31:04 PM PDT 24
Finished Apr 02 12:31:05 PM PDT 24
Peak memory 205456 kb
Host smart-b262950e-ef04-4ff3-8927-f52346283e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503482716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1503482716
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.342758602
Short name T900
Test name
Test status
Simulation time 93460139 ps
CPU time 0.78 seconds
Started Apr 02 12:30:49 PM PDT 24
Finished Apr 02 12:30:50 PM PDT 24
Peak memory 205428 kb
Host smart-49ded9ec-f080-40a2-bcde-13e8a09b5ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342758602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.342758602
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2370568425
Short name T148
Test name
Test status
Simulation time 5983371399 ps
CPU time 9.87 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:18 PM PDT 24
Peak memory 205928 kb
Host smart-dcc14959-db4f-4018-b94a-2b23bfc2bae9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370568425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
370568425
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3870037289
Short name T1059
Test name
Test status
Simulation time 133993874 ps
CPU time 7.59 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 205716 kb
Host smart-b13f7d78-2b23-46fd-8ae2-11ccf8f38444
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870037289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
870037289
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.301039594
Short name T1027
Test name
Test status
Simulation time 28059989 ps
CPU time 1.13 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 213940 kb
Host smart-3cfca17a-5187-4346-96f2-5c7e83a223b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301039594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.301039594
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2517990491
Short name T1019
Test name
Test status
Simulation time 87224320 ps
CPU time 1.61 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 213880 kb
Host smart-e011e6c9-429b-4362-822d-e6be66b271be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517990491 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2517990491
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1150650371
Short name T972
Test name
Test status
Simulation time 20640352 ps
CPU time 1.18 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 205616 kb
Host smart-637b0e9b-8b0a-4afb-90f3-11c40f65a5ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150650371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1150650371
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.776908889
Short name T944
Test name
Test status
Simulation time 12404408 ps
CPU time 0.75 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205412 kb
Host smart-a42d9286-0db2-49d3-9d85-100f743dbae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776908889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.776908889
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3790424705
Short name T147
Test name
Test status
Simulation time 61281839 ps
CPU time 2.14 seconds
Started Apr 02 12:31:04 PM PDT 24
Finished Apr 02 12:31:06 PM PDT 24
Peak memory 205792 kb
Host smart-6022812d-9284-47f1-a8ee-c5649a709098
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790424705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3790424705
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.968312069
Short name T964
Test name
Test status
Simulation time 125692725 ps
CPU time 2.87 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 214352 kb
Host smart-0938daf0-1d13-4915-b967-5f87c0e66afd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968312069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.968312069
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1737855040
Short name T1043
Test name
Test status
Simulation time 1182425474 ps
CPU time 8.2 seconds
Started Apr 02 12:31:04 PM PDT 24
Finished Apr 02 12:31:12 PM PDT 24
Peak memory 214292 kb
Host smart-489c9759-7746-447f-aa7c-1ce7d04e44fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737855040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1737855040
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.880625601
Short name T905
Test name
Test status
Simulation time 157026700 ps
CPU time 3.28 seconds
Started Apr 02 12:30:57 PM PDT 24
Finished Apr 02 12:31:01 PM PDT 24
Peak memory 215940 kb
Host smart-9606c22c-4e53-4de3-8ba3-df1e002e60cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880625601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.880625601
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.251751107
Short name T399
Test name
Test status
Simulation time 122556119 ps
CPU time 3.57 seconds
Started Apr 02 12:31:01 PM PDT 24
Finished Apr 02 12:31:05 PM PDT 24
Peak memory 209196 kb
Host smart-1218af17-f9a2-405e-9de6-f61761c148f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251751107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
251751107
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3637491586
Short name T930
Test name
Test status
Simulation time 103335442 ps
CPU time 0.75 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 205424 kb
Host smart-a0873b53-aa07-45b4-ba63-33206dd6756e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637491586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3637491586
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1957209075
Short name T955
Test name
Test status
Simulation time 40375142 ps
CPU time 0.81 seconds
Started Apr 02 12:31:06 PM PDT 24
Finished Apr 02 12:31:07 PM PDT 24
Peak memory 205384 kb
Host smart-5153c4ce-c008-435a-9836-2b791b6c87fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957209075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1957209075
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2034978715
Short name T1006
Test name
Test status
Simulation time 25817438 ps
CPU time 0.68 seconds
Started Apr 02 12:31:05 PM PDT 24
Finished Apr 02 12:31:06 PM PDT 24
Peak memory 205456 kb
Host smart-c840ce04-7d5a-4ec7-aed9-8d040454c5c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034978715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2034978715
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3319678462
Short name T1033
Test name
Test status
Simulation time 10722219 ps
CPU time 0.78 seconds
Started Apr 02 12:31:14 PM PDT 24
Finished Apr 02 12:31:15 PM PDT 24
Peak memory 205380 kb
Host smart-e29747a5-52c7-4ce5-8b6c-567daf1d4961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319678462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3319678462
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2397974505
Short name T974
Test name
Test status
Simulation time 60457848 ps
CPU time 0.75 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:08 PM PDT 24
Peak memory 205392 kb
Host smart-24a92386-837c-4ff0-8d1e-7d44a099b5a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397974505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2397974505
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2877222833
Short name T984
Test name
Test status
Simulation time 15802997 ps
CPU time 0.87 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:07 PM PDT 24
Peak memory 205616 kb
Host smart-5ce4d78b-f069-4b18-9d37-8c330699aa17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877222833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2877222833
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3604717575
Short name T932
Test name
Test status
Simulation time 9993643 ps
CPU time 0.68 seconds
Started Apr 02 12:31:02 PM PDT 24
Finished Apr 02 12:31:03 PM PDT 24
Peak memory 205464 kb
Host smart-2cae6999-e79d-4c5e-b28d-cade9183e93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604717575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3604717575
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.516158343
Short name T973
Test name
Test status
Simulation time 14652162 ps
CPU time 0.82 seconds
Started Apr 02 12:30:58 PM PDT 24
Finished Apr 02 12:30:59 PM PDT 24
Peak memory 205388 kb
Host smart-d5d3c2d6-c764-49bf-9c95-aef2b46e6a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516158343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.516158343
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2160863532
Short name T928
Test name
Test status
Simulation time 12862768 ps
CPU time 0.94 seconds
Started Apr 02 12:30:57 PM PDT 24
Finished Apr 02 12:30:58 PM PDT 24
Peak memory 205428 kb
Host smart-b1b6cd8a-c1df-4da4-8de6-23e3352b7342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160863532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2160863532
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.265316106
Short name T997
Test name
Test status
Simulation time 23321441 ps
CPU time 0.68 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 205380 kb
Host smart-846fbba8-cdad-426d-ab3b-a3e32aa0a6f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265316106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.265316106
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3718652910
Short name T938
Test name
Test status
Simulation time 127659403 ps
CPU time 7.21 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:46 PM PDT 24
Peak memory 205788 kb
Host smart-0580b1ef-5e94-40ae-9d22-b34b91f940ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718652910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
718652910
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1751402090
Short name T1009
Test name
Test status
Simulation time 1659241468 ps
CPU time 7.81 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 205524 kb
Host smart-a5238f0c-db97-462d-906c-05c3fbc61583
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751402090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
751402090
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1562712150
Short name T1022
Test name
Test status
Simulation time 20984744 ps
CPU time 0.93 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 205732 kb
Host smart-a70766ba-3890-49d5-8f1d-b2fcca455292
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562712150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
562712150
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2373394215
Short name T1058
Test name
Test status
Simulation time 154131440 ps
CPU time 1.33 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 214096 kb
Host smart-6e2d90ef-30e9-41d4-bf8c-baeeee87d7cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373394215 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2373394215
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1148802961
Short name T989
Test name
Test status
Simulation time 16953832 ps
CPU time 1.03 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205708 kb
Host smart-79a33cfe-5308-406a-a182-87b551145461
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148802961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1148802961
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2303361632
Short name T1002
Test name
Test status
Simulation time 8453690 ps
CPU time 0.77 seconds
Started Apr 02 12:30:50 PM PDT 24
Finished Apr 02 12:30:56 PM PDT 24
Peak memory 205436 kb
Host smart-5c4dd1bb-0b07-407a-88a3-0239617669bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303361632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2303361632
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2605367103
Short name T146
Test name
Test status
Simulation time 399044754 ps
CPU time 3.76 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205856 kb
Host smart-42da0d6e-e5da-412e-9a9b-5a2bd39f4405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605367103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2605367103
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2092744206
Short name T925
Test name
Test status
Simulation time 245217743 ps
CPU time 2.36 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 214200 kb
Host smart-c66ea252-2593-403f-b185-353f4e34e6eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092744206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2092744206
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2532057474
Short name T1023
Test name
Test status
Simulation time 81419992 ps
CPU time 3.69 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 214144 kb
Host smart-410ef324-0e82-47f8-a5df-eb0dc320b1a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532057474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2532057474
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3054858897
Short name T907
Test name
Test status
Simulation time 610803602 ps
CPU time 3.89 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 213984 kb
Host smart-8001e93a-daaf-4c65-8220-660479fd662b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054858897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3054858897
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2012015013
Short name T173
Test name
Test status
Simulation time 216622238 ps
CPU time 8.53 seconds
Started Apr 02 12:30:41 PM PDT 24
Finished Apr 02 12:30:50 PM PDT 24
Peak memory 209024 kb
Host smart-eb15c331-341e-4318-8aae-f6a48706a1e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012015013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2012015013
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3707736308
Short name T936
Test name
Test status
Simulation time 10443223 ps
CPU time 0.69 seconds
Started Apr 02 12:31:02 PM PDT 24
Finished Apr 02 12:31:03 PM PDT 24
Peak memory 205376 kb
Host smart-54904b74-2a9e-49ce-99e9-0d442a29eb8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707736308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3707736308
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2128736141
Short name T912
Test name
Test status
Simulation time 36026136 ps
CPU time 0.69 seconds
Started Apr 02 12:31:02 PM PDT 24
Finished Apr 02 12:31:03 PM PDT 24
Peak memory 205476 kb
Host smart-d0c8af05-2c37-4e07-b0d2-e67c9a505077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128736141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2128736141
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.393674740
Short name T933
Test name
Test status
Simulation time 9104448 ps
CPU time 0.8 seconds
Started Apr 02 12:31:05 PM PDT 24
Finished Apr 02 12:31:06 PM PDT 24
Peak memory 205412 kb
Host smart-a1c0797b-bba1-44f9-8997-1681efcf3135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393674740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.393674740
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1407281847
Short name T913
Test name
Test status
Simulation time 10396817 ps
CPU time 0.77 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:08 PM PDT 24
Peak memory 205472 kb
Host smart-34115e98-c5bb-49ec-9b4c-27dd0c32962a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407281847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1407281847
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.964683230
Short name T901
Test name
Test status
Simulation time 16849649 ps
CPU time 0.74 seconds
Started Apr 02 12:31:11 PM PDT 24
Finished Apr 02 12:31:12 PM PDT 24
Peak memory 205276 kb
Host smart-82ecf8f3-e7e8-4a14-9861-7edcf467447c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964683230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.964683230
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2483750501
Short name T996
Test name
Test status
Simulation time 11662103 ps
CPU time 0.86 seconds
Started Apr 02 12:31:09 PM PDT 24
Finished Apr 02 12:31:10 PM PDT 24
Peak memory 205372 kb
Host smart-ccf5f8b4-c39a-4a70-9e9d-10175b63ca15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483750501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2483750501
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.154864472
Short name T924
Test name
Test status
Simulation time 17821784 ps
CPU time 0.68 seconds
Started Apr 02 12:31:05 PM PDT 24
Finished Apr 02 12:31:05 PM PDT 24
Peak memory 205444 kb
Host smart-f7dd6ebf-9f55-4937-b4a8-4a77dbb69bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154864472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.154864472
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3806995599
Short name T934
Test name
Test status
Simulation time 10330995 ps
CPU time 0.84 seconds
Started Apr 02 12:31:03 PM PDT 24
Finished Apr 02 12:31:04 PM PDT 24
Peak memory 205348 kb
Host smart-e860b9a2-0fb8-4140-ac6a-658ba358066f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806995599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3806995599
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.52601630
Short name T894
Test name
Test status
Simulation time 24249320 ps
CPU time 0.73 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:08 PM PDT 24
Peak memory 205396 kb
Host smart-a8565459-3e3b-412c-850f-c52dcfe7bdee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52601630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.52601630
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4039786294
Short name T969
Test name
Test status
Simulation time 85249877 ps
CPU time 0.7 seconds
Started Apr 02 12:31:03 PM PDT 24
Finished Apr 02 12:31:04 PM PDT 24
Peak memory 205468 kb
Host smart-8e151bb9-5de5-44eb-9508-64077569eb91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039786294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4039786294
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.989493699
Short name T1003
Test name
Test status
Simulation time 117938931 ps
CPU time 1.16 seconds
Started Apr 02 12:30:56 PM PDT 24
Finished Apr 02 12:30:58 PM PDT 24
Peak memory 213992 kb
Host smart-3ff1ce86-d6e0-43d2-9113-67a12797e695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989493699 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.989493699
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1022597864
Short name T1030
Test name
Test status
Simulation time 35036319 ps
CPU time 0.93 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 205516 kb
Host smart-528d5463-c1e7-41c5-8924-e9e770af966a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022597864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1022597864
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3190910979
Short name T1025
Test name
Test status
Simulation time 29277123 ps
CPU time 0.69 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 205368 kb
Host smart-a44d26a9-6adc-499c-8a82-e8cc8cbf5f82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190910979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3190910979
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4253921668
Short name T149
Test name
Test status
Simulation time 125850340 ps
CPU time 1.89 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:51 PM PDT 24
Peak memory 203268 kb
Host smart-5c27a4fe-9817-4d8d-a684-f3278878994a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253921668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4253921668
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.366318380
Short name T1011
Test name
Test status
Simulation time 664847277 ps
CPU time 16.14 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:53 PM PDT 24
Peak memory 214588 kb
Host smart-06e15f4f-860a-4802-a9c7-782f4e98bf3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366318380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.366318380
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1921769
Short name T991
Test name
Test status
Simulation time 100062883 ps
CPU time 1.7 seconds
Started Apr 02 12:31:02 PM PDT 24
Finished Apr 02 12:31:04 PM PDT 24
Peak memory 216016 kb
Host smart-334c746b-5139-44e8-a0fb-6d89a8899861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1921769
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3348041297
Short name T1050
Test name
Test status
Simulation time 254212591 ps
CPU time 5.59 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 213912 kb
Host smart-6c0a755d-4f7f-4e55-b260-88cd47e502f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348041297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3348041297
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2736601830
Short name T965
Test name
Test status
Simulation time 210636865 ps
CPU time 1.45 seconds
Started Apr 02 12:30:53 PM PDT 24
Finished Apr 02 12:30:54 PM PDT 24
Peak memory 213992 kb
Host smart-90cfb900-f886-41de-af43-0b8b6d68dd6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736601830 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2736601830
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.137537955
Short name T982
Test name
Test status
Simulation time 15352478 ps
CPU time 1.18 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 205832 kb
Host smart-b89a59b4-9f5c-4123-96ad-98138c2ad8f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137537955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.137537955
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3077102866
Short name T1035
Test name
Test status
Simulation time 25943102 ps
CPU time 0.94 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:32 PM PDT 24
Peak memory 205628 kb
Host smart-fea08b77-a8a6-4bd7-b495-5473f76d2f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077102866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3077102866
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2525040412
Short name T1024
Test name
Test status
Simulation time 43566487 ps
CPU time 1.3 seconds
Started Apr 02 12:31:49 PM PDT 24
Finished Apr 02 12:31:51 PM PDT 24
Peak memory 205372 kb
Host smart-8e3629a3-8de7-4d67-af8b-7be1e3bad343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525040412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2525040412
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1512428250
Short name T951
Test name
Test status
Simulation time 458318502 ps
CPU time 5.11 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:54 PM PDT 24
Peak memory 220260 kb
Host smart-be07f06e-edb5-4bf6-897a-de3a709a7ad0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512428250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1512428250
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4030765287
Short name T114
Test name
Test status
Simulation time 704627688 ps
CPU time 9.39 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:58 PM PDT 24
Peak memory 211804 kb
Host smart-2d8b9669-6682-4f4e-bbb4-0f1716be1a3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030765287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.4030765287
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.839694726
Short name T906
Test name
Test status
Simulation time 222206048 ps
CPU time 1.72 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:51 PM PDT 24
Peak memory 212360 kb
Host smart-6b40d39c-a4ff-4213-aff9-1cbf1849143a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839694726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.839694726
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2667087336
Short name T1041
Test name
Test status
Simulation time 46719835 ps
CPU time 1.68 seconds
Started Apr 02 12:31:17 PM PDT 24
Finished Apr 02 12:31:20 PM PDT 24
Peak memory 214024 kb
Host smart-c9d4e642-d3b1-41cb-b724-f6bb3829faee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667087336 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2667087336
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.508009818
Short name T999
Test name
Test status
Simulation time 47880805 ps
CPU time 1.15 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205712 kb
Host smart-e4596acc-44cd-4da1-a56c-ae5820df1dfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508009818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.508009818
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.194196233
Short name T922
Test name
Test status
Simulation time 12991734 ps
CPU time 0.86 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 205352 kb
Host smart-7a9915aa-65ae-49b2-83e9-cf27d33e9a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194196233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.194196233
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1629484984
Short name T1000
Test name
Test status
Simulation time 314857954 ps
CPU time 2.79 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:52 PM PDT 24
Peak memory 203624 kb
Host smart-26bf015c-afc5-42c5-b70f-7c8f1b7394cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629484984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1629484984
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4155029959
Short name T120
Test name
Test status
Simulation time 629082823 ps
CPU time 4.91 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 214288 kb
Host smart-19c88a9b-774d-4a8d-ba47-0f944f0fedce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155029959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.4155029959
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1580284651
Short name T985
Test name
Test status
Simulation time 157666406 ps
CPU time 7.03 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:56 PM PDT 24
Peak memory 212176 kb
Host smart-20a8fbf4-6e90-4f18-b45b-7bd19090a256
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580284651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1580284651
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3372776212
Short name T988
Test name
Test status
Simulation time 386794069 ps
CPU time 6.37 seconds
Started Apr 02 12:30:44 PM PDT 24
Finished Apr 02 12:30:51 PM PDT 24
Peak memory 214000 kb
Host smart-4b039376-c5e4-4868-8534-23846c65dd26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372776212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3372776212
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.950731791
Short name T910
Test name
Test status
Simulation time 99876355 ps
CPU time 1.49 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 217152 kb
Host smart-7dc6c192-fb53-4de1-96da-e8ba08c79c88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950731791 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.950731791
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.255023116
Short name T1017
Test name
Test status
Simulation time 23762947 ps
CPU time 1.19 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 205552 kb
Host smart-28ff9da1-6e98-42ba-9e4d-1d83f429151f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255023116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.255023116
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2321540881
Short name T917
Test name
Test status
Simulation time 16376068 ps
CPU time 0.75 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 205444 kb
Host smart-06781f9b-4f9b-4aec-8e7b-4450d6f1db48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321540881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2321540881
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3263527443
Short name T929
Test name
Test status
Simulation time 31108803 ps
CPU time 2.4 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 205812 kb
Host smart-9dc447f3-bf8f-44d8-ab82-3cb01e31bad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263527443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3263527443
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1012610405
Short name T975
Test name
Test status
Simulation time 1131622845 ps
CPU time 6.49 seconds
Started Apr 02 12:30:56 PM PDT 24
Finished Apr 02 12:31:03 PM PDT 24
Peak memory 214260 kb
Host smart-7f0392c8-f812-4333-b707-38981d4992bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012610405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1012610405
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2057381633
Short name T970
Test name
Test status
Simulation time 790729120 ps
CPU time 7.29 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 214308 kb
Host smart-e51eea7a-ff6a-4dcc-8c20-be37f63a330f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057381633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2057381633
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1664103115
Short name T998
Test name
Test status
Simulation time 51690460 ps
CPU time 2.51 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:46 PM PDT 24
Peak memory 213896 kb
Host smart-3df6ebf9-0e11-42cd-aa98-c0f30522d37b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664103115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1664103115
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1526118127
Short name T163
Test name
Test status
Simulation time 741676332 ps
CPU time 2.24 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 213936 kb
Host smart-14f10568-279a-4bb0-9f07-036f8098a61c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526118127 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1526118127
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1849246731
Short name T200
Test name
Test status
Simulation time 181251363 ps
CPU time 1.32 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:50 PM PDT 24
Peak memory 203460 kb
Host smart-8f560b18-873f-4cde-9169-49422a786828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849246731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1849246731
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.683457024
Short name T1004
Test name
Test status
Simulation time 25234885 ps
CPU time 0.9 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 205260 kb
Host smart-5d5b9c43-15b1-4bbd-a339-3e290c5f44d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683457024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.683457024
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1759587635
Short name T1057
Test name
Test status
Simulation time 484007220 ps
CPU time 3.01 seconds
Started Apr 02 12:31:48 PM PDT 24
Finished Apr 02 12:31:52 PM PDT 24
Peak memory 204216 kb
Host smart-d159ff90-d7c8-4752-9b3f-2a84fd70cf36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759587635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1759587635
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2288531714
Short name T986
Test name
Test status
Simulation time 193794380 ps
CPU time 2.11 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 214252 kb
Host smart-4cafddb0-7799-434e-916b-5f9571117f0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288531714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2288531714
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1521314848
Short name T914
Test name
Test status
Simulation time 1336348738 ps
CPU time 8.54 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:46 PM PDT 24
Peak memory 214228 kb
Host smart-0637c295-6b5a-4f5a-965a-7811264cce89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521314848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1521314848
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1893021169
Short name T896
Test name
Test status
Simulation time 78725794 ps
CPU time 1.85 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 213804 kb
Host smart-490c92a5-3137-4209-9922-4ad84dea456a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893021169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1893021169
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3093367713
Short name T185
Test name
Test status
Simulation time 263183085 ps
CPU time 5.16 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 208956 kb
Host smart-dc551742-03e8-4178-9c22-2a6e140c12ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093367713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3093367713
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.692708671
Short name T830
Test name
Test status
Simulation time 51900429 ps
CPU time 0.72 seconds
Started Apr 02 01:41:36 PM PDT 24
Finished Apr 02 01:41:37 PM PDT 24
Peak memory 206324 kb
Host smart-cbc7b935-e54c-40a9-a5e5-4e15f22841f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692708671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.692708671
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.750465872
Short name T406
Test name
Test status
Simulation time 47114746 ps
CPU time 3.3 seconds
Started Apr 02 01:41:33 PM PDT 24
Finished Apr 02 01:41:37 PM PDT 24
Peak memory 214636 kb
Host smart-b2c084f7-6347-4380-821c-0061bfe5ebd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750465872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.750465872
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.4075624204
Short name T9
Test name
Test status
Simulation time 207373002 ps
CPU time 4.35 seconds
Started Apr 02 01:41:32 PM PDT 24
Finished Apr 02 01:41:36 PM PDT 24
Peak memory 222052 kb
Host smart-98b276eb-5de7-44f3-bcd8-40ea25704288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075624204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.4075624204
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.55694836
Short name T417
Test name
Test status
Simulation time 17305731 ps
CPU time 1.36 seconds
Started Apr 02 01:41:32 PM PDT 24
Finished Apr 02 01:41:34 PM PDT 24
Peak memory 207896 kb
Host smart-3dc74d93-fa42-471e-92e7-4a2530314a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55694836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.55694836
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.721342256
Short name T858
Test name
Test status
Simulation time 316118199 ps
CPU time 3.43 seconds
Started Apr 02 01:41:33 PM PDT 24
Finished Apr 02 01:41:37 PM PDT 24
Peak memory 214696 kb
Host smart-50f988d7-aa8c-453c-88e6-01982f2abe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721342256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.721342256
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.798412225
Short name T234
Test name
Test status
Simulation time 150498838 ps
CPU time 3.09 seconds
Started Apr 02 01:41:34 PM PDT 24
Finished Apr 02 01:41:37 PM PDT 24
Peak memory 222792 kb
Host smart-1683cc10-fe36-4142-9b71-a93a2cd41d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798412225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.798412225
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2131301418
Short name T763
Test name
Test status
Simulation time 123057708 ps
CPU time 3.2 seconds
Started Apr 02 01:41:33 PM PDT 24
Finished Apr 02 01:41:37 PM PDT 24
Peak memory 214688 kb
Host smart-cbc6dfa1-e925-42eb-8c96-cfbae19a50a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131301418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2131301418
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3648464059
Short name T371
Test name
Test status
Simulation time 196812346 ps
CPU time 5.71 seconds
Started Apr 02 01:41:29 PM PDT 24
Finished Apr 02 01:41:35 PM PDT 24
Peak memory 209676 kb
Host smart-3702580f-7124-4f81-b00c-a9f4ef22de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648464059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3648464059
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2353166790
Short name T795
Test name
Test status
Simulation time 279008982 ps
CPU time 3.62 seconds
Started Apr 02 01:41:29 PM PDT 24
Finished Apr 02 01:41:33 PM PDT 24
Peak memory 208828 kb
Host smart-6ab23b10-f2f8-481d-a5bb-68ce29b15995
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353166790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2353166790
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.4043773014
Short name T493
Test name
Test status
Simulation time 837648388 ps
CPU time 9 seconds
Started Apr 02 01:41:27 PM PDT 24
Finished Apr 02 01:41:36 PM PDT 24
Peak memory 207224 kb
Host smart-26de7ea5-fa25-4ddd-8995-2cd131ff5cc2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043773014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4043773014
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2252953363
Short name T702
Test name
Test status
Simulation time 467143050 ps
CPU time 6.27 seconds
Started Apr 02 01:41:33 PM PDT 24
Finished Apr 02 01:41:40 PM PDT 24
Peak memory 209096 kb
Host smart-038963bc-f1fe-434f-a310-177b693288bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252953363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2252953363
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.374222222
Short name T478
Test name
Test status
Simulation time 428911960 ps
CPU time 3.48 seconds
Started Apr 02 01:41:35 PM PDT 24
Finished Apr 02 01:41:39 PM PDT 24
Peak memory 209488 kb
Host smart-f23bf2c3-d001-485e-adda-f98a20d72b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374222222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.374222222
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2402151252
Short name T653
Test name
Test status
Simulation time 237223041 ps
CPU time 3.16 seconds
Started Apr 02 01:41:26 PM PDT 24
Finished Apr 02 01:41:29 PM PDT 24
Peak memory 206816 kb
Host smart-2500e388-cc41-4c43-a224-4dda97ca7458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402151252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2402151252
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.865236867
Short name T166
Test name
Test status
Simulation time 6437581622 ps
CPU time 25.46 seconds
Started Apr 02 01:41:36 PM PDT 24
Finished Apr 02 01:42:02 PM PDT 24
Peak memory 223076 kb
Host smart-9accdb3a-28f0-4a1a-93de-720332b37198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865236867 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.865236867
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1817338474
Short name T239
Test name
Test status
Simulation time 92045390 ps
CPU time 4.57 seconds
Started Apr 02 01:41:33 PM PDT 24
Finished Apr 02 01:41:38 PM PDT 24
Peak memory 209488 kb
Host smart-6c4a0a4a-a9ae-48b0-8751-a7e6e3bc6fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817338474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1817338474
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3410757968
Short name T50
Test name
Test status
Simulation time 104595300 ps
CPU time 2.03 seconds
Started Apr 02 01:41:35 PM PDT 24
Finished Apr 02 01:41:38 PM PDT 24
Peak memory 210144 kb
Host smart-484bd4a6-57c1-4913-bd1c-0177f5556583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410757968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3410757968
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1355210367
Short name T407
Test name
Test status
Simulation time 113786012 ps
CPU time 2.76 seconds
Started Apr 02 01:41:42 PM PDT 24
Finished Apr 02 01:41:45 PM PDT 24
Peak memory 214632 kb
Host smart-164d8a6b-5a39-467d-8655-a007c0a10fc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355210367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1355210367
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3539037214
Short name T827
Test name
Test status
Simulation time 226426857 ps
CPU time 2.7 seconds
Started Apr 02 01:41:40 PM PDT 24
Finished Apr 02 01:41:43 PM PDT 24
Peak memory 210264 kb
Host smart-332dce6d-6c65-4e7c-ae95-ea67099764b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539037214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3539037214
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2940076739
Short name T383
Test name
Test status
Simulation time 228145279 ps
CPU time 3.9 seconds
Started Apr 02 01:41:44 PM PDT 24
Finished Apr 02 01:41:48 PM PDT 24
Peak memory 209664 kb
Host smart-d9f258be-eb61-4e60-b03a-f23cd0f8ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940076739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2940076739
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1033563748
Short name T290
Test name
Test status
Simulation time 304587375 ps
CPU time 10.22 seconds
Started Apr 02 01:41:42 PM PDT 24
Finished Apr 02 01:41:52 PM PDT 24
Peak memory 214608 kb
Host smart-7c41f86a-1193-429f-895c-566f54dbfb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033563748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1033563748
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.23144664
Short name T257
Test name
Test status
Simulation time 399862846 ps
CPU time 2.9 seconds
Started Apr 02 01:41:40 PM PDT 24
Finished Apr 02 01:41:43 PM PDT 24
Peak memory 209452 kb
Host smart-94a88fdd-81d3-423f-889f-d889489b45db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23144664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.23144664
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2898700213
Short name T549
Test name
Test status
Simulation time 417628559 ps
CPU time 3.61 seconds
Started Apr 02 01:41:40 PM PDT 24
Finished Apr 02 01:41:43 PM PDT 24
Peak memory 207848 kb
Host smart-eb80c279-db1a-4fe5-a3a1-6a19196051f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898700213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2898700213
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3654673910
Short name T36
Test name
Test status
Simulation time 1706913307 ps
CPU time 14.33 seconds
Started Apr 02 01:41:48 PM PDT 24
Finished Apr 02 01:42:02 PM PDT 24
Peak memory 230720 kb
Host smart-cc4be20c-df72-43ed-818d-a6b2543d4e00
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654673910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3654673910
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4245020759
Short name T695
Test name
Test status
Simulation time 456974237 ps
CPU time 5.48 seconds
Started Apr 02 01:41:37 PM PDT 24
Finished Apr 02 01:41:43 PM PDT 24
Peak memory 208784 kb
Host smart-a252ce36-b567-4345-9d46-8fc4c4d763aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245020759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4245020759
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3824719579
Short name T658
Test name
Test status
Simulation time 134089412 ps
CPU time 4.26 seconds
Started Apr 02 01:41:37 PM PDT 24
Finished Apr 02 01:41:42 PM PDT 24
Peak memory 208652 kb
Host smart-136e9a3e-6f7b-4028-a5ab-0003e19b3b47
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824719579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3824719579
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1821454106
Short name T700
Test name
Test status
Simulation time 452363867 ps
CPU time 6.55 seconds
Started Apr 02 01:41:37 PM PDT 24
Finished Apr 02 01:41:44 PM PDT 24
Peak memory 208700 kb
Host smart-8e23ff9a-bd73-4d73-8da8-541ca97fb982
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821454106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1821454106
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1145506954
Short name T606
Test name
Test status
Simulation time 787100944 ps
CPU time 10.02 seconds
Started Apr 02 01:41:38 PM PDT 24
Finished Apr 02 01:41:48 PM PDT 24
Peak memory 208348 kb
Host smart-faa26caa-2382-461e-9b67-6a2483d58313
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145506954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1145506954
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2954186952
Short name T863
Test name
Test status
Simulation time 441328387 ps
CPU time 3.11 seconds
Started Apr 02 01:41:44 PM PDT 24
Finished Apr 02 01:41:47 PM PDT 24
Peak memory 207500 kb
Host smart-7738f418-d131-4b71-8a85-af260a3ffee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954186952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2954186952
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2138740301
Short name T37
Test name
Test status
Simulation time 180956648 ps
CPU time 3.23 seconds
Started Apr 02 01:41:37 PM PDT 24
Finished Apr 02 01:41:40 PM PDT 24
Peak memory 208744 kb
Host smart-e78bbac3-3a57-48db-bc92-0609fc04b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138740301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2138740301
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3739592759
Short name T831
Test name
Test status
Simulation time 67527016 ps
CPU time 3.6 seconds
Started Apr 02 01:41:43 PM PDT 24
Finished Apr 02 01:41:46 PM PDT 24
Peak memory 208264 kb
Host smart-aef56d80-7217-40ae-a06d-e86a32c06b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739592759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3739592759
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2229972106
Short name T210
Test name
Test status
Simulation time 526363063 ps
CPU time 3.47 seconds
Started Apr 02 01:41:43 PM PDT 24
Finished Apr 02 01:41:47 PM PDT 24
Peak memory 210432 kb
Host smart-0ec3a606-655b-45f9-979d-9ef52fdd7e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229972106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2229972106
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2876683606
Short name T851
Test name
Test status
Simulation time 12580545 ps
CPU time 0.9 seconds
Started Apr 02 01:43:22 PM PDT 24
Finished Apr 02 01:43:23 PM PDT 24
Peak memory 206308 kb
Host smart-15ea9684-7573-403a-a1c7-7f36215564ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876683606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2876683606
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2463441857
Short name T139
Test name
Test status
Simulation time 166397975 ps
CPU time 3.95 seconds
Started Apr 02 01:43:15 PM PDT 24
Finished Apr 02 01:43:19 PM PDT 24
Peak memory 215768 kb
Host smart-4691c7e0-d03b-4c9f-a79d-ab83632c3a7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463441857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2463441857
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1276791678
Short name T673
Test name
Test status
Simulation time 736319358 ps
CPU time 3.2 seconds
Started Apr 02 01:43:20 PM PDT 24
Finished Apr 02 01:43:24 PM PDT 24
Peak memory 221192 kb
Host smart-39673faa-509d-4c04-8398-2c9e72e1672f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276791678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1276791678
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2017392771
Short name T72
Test name
Test status
Simulation time 124553610 ps
CPU time 2.3 seconds
Started Apr 02 01:43:15 PM PDT 24
Finished Apr 02 01:43:17 PM PDT 24
Peak memory 210592 kb
Host smart-604ca1f9-4736-4b4a-b399-28691a5dced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017392771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2017392771
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3742044522
Short name T31
Test name
Test status
Simulation time 318716604 ps
CPU time 3.59 seconds
Started Apr 02 01:43:15 PM PDT 24
Finished Apr 02 01:43:20 PM PDT 24
Peak memory 222832 kb
Host smart-9d46ece7-66ac-4e92-a43b-093ab86fcd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742044522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3742044522
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2477532183
Short name T867
Test name
Test status
Simulation time 275264724 ps
CPU time 2.59 seconds
Started Apr 02 01:43:20 PM PDT 24
Finished Apr 02 01:43:23 PM PDT 24
Peak memory 219996 kb
Host smart-f4fd96e3-cf20-4a70-91cc-d6381b35a156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477532183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2477532183
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1412176237
Short name T758
Test name
Test status
Simulation time 792161292 ps
CPU time 5.35 seconds
Started Apr 02 01:43:16 PM PDT 24
Finished Apr 02 01:43:22 PM PDT 24
Peak memory 208424 kb
Host smart-183a2ce3-718b-4bd0-a2db-e3f2697275a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412176237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1412176237
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.739927027
Short name T498
Test name
Test status
Simulation time 85339987 ps
CPU time 1.98 seconds
Started Apr 02 01:43:12 PM PDT 24
Finished Apr 02 01:43:15 PM PDT 24
Peak memory 208764 kb
Host smart-e134db8f-cb96-4126-821c-7c427657e196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739927027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.739927027
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.691975677
Short name T521
Test name
Test status
Simulation time 72778146 ps
CPU time 3.79 seconds
Started Apr 02 01:43:12 PM PDT 24
Finished Apr 02 01:43:16 PM PDT 24
Peak memory 209216 kb
Host smart-817640e1-083d-4d9a-bce3-be6739b606ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691975677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.691975677
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2647656754
Short name T755
Test name
Test status
Simulation time 64155040 ps
CPU time 3.19 seconds
Started Apr 02 01:43:11 PM PDT 24
Finished Apr 02 01:43:15 PM PDT 24
Peak memory 208504 kb
Host smart-89cfcffe-efa9-4b11-b013-27f2e02d8cf8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647656754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2647656754
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3285451062
Short name T769
Test name
Test status
Simulation time 68058158 ps
CPU time 2.71 seconds
Started Apr 02 01:43:20 PM PDT 24
Finished Apr 02 01:43:23 PM PDT 24
Peak memory 209076 kb
Host smart-844b308f-9066-4bca-aaa3-5ead1153d91a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285451062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3285451062
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2443164051
Short name T607
Test name
Test status
Simulation time 646476447 ps
CPU time 6.92 seconds
Started Apr 02 01:43:19 PM PDT 24
Finished Apr 02 01:43:26 PM PDT 24
Peak memory 214668 kb
Host smart-0894433b-6713-4be4-a239-9e7c9fdaea0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443164051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2443164051
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2521183102
Short name T505
Test name
Test status
Simulation time 787293387 ps
CPU time 2.87 seconds
Started Apr 02 01:43:10 PM PDT 24
Finished Apr 02 01:43:14 PM PDT 24
Peak memory 206948 kb
Host smart-f6cfa58d-60a0-40b8-add8-a776d9bef4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521183102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2521183102
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1842377884
Short name T263
Test name
Test status
Simulation time 7343716330 ps
CPU time 74.29 seconds
Started Apr 02 01:43:18 PM PDT 24
Finished Apr 02 01:44:32 PM PDT 24
Peak memory 215552 kb
Host smart-122cb5cf-d43c-4091-ba5c-f6fcb40bd982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842377884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1842377884
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3746290054
Short name T186
Test name
Test status
Simulation time 569691882 ps
CPU time 3.32 seconds
Started Apr 02 01:43:21 PM PDT 24
Finished Apr 02 01:43:25 PM PDT 24
Peak memory 210540 kb
Host smart-c4a2b052-2bed-491d-a938-955386c6ead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746290054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3746290054
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.4268702535
Short name T542
Test name
Test status
Simulation time 11065335 ps
CPU time 0.72 seconds
Started Apr 02 01:43:32 PM PDT 24
Finished Apr 02 01:43:33 PM PDT 24
Peak memory 206316 kb
Host smart-ff0432b5-1eda-42ef-a41e-3c6abdf2cd38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268702535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.4268702535
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3298703811
Short name T829
Test name
Test status
Simulation time 51133605 ps
CPU time 2.51 seconds
Started Apr 02 01:43:30 PM PDT 24
Finished Apr 02 01:43:32 PM PDT 24
Peak memory 209960 kb
Host smart-933c9493-257b-4f15-9b64-752df1d1618c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298703811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3298703811
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.571811456
Short name T647
Test name
Test status
Simulation time 161182287 ps
CPU time 2.19 seconds
Started Apr 02 01:43:25 PM PDT 24
Finished Apr 02 01:43:27 PM PDT 24
Peak memory 209320 kb
Host smart-98501008-7186-4a9b-b849-6f1deb5c8326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571811456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.571811456
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1972695833
Short name T52
Test name
Test status
Simulation time 166278659 ps
CPU time 6.99 seconds
Started Apr 02 01:43:27 PM PDT 24
Finished Apr 02 01:43:34 PM PDT 24
Peak memory 210304 kb
Host smart-63bc1711-3d62-47b6-bdbd-2c241ba68657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972695833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1972695833
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1637879827
Short name T240
Test name
Test status
Simulation time 3115520173 ps
CPU time 31.64 seconds
Started Apr 02 01:43:22 PM PDT 24
Finished Apr 02 01:43:54 PM PDT 24
Peak memory 218736 kb
Host smart-0fdd0e17-a4f4-4edf-ae59-354afb415dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637879827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1637879827
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1302473779
Short name T445
Test name
Test status
Simulation time 84802387 ps
CPU time 1.83 seconds
Started Apr 02 01:43:22 PM PDT 24
Finished Apr 02 01:43:24 PM PDT 24
Peak memory 207448 kb
Host smart-a9320a7b-5a9c-42b7-a4da-2b99431e99d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302473779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1302473779
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3771943171
Short name T799
Test name
Test status
Simulation time 160408480 ps
CPU time 3.72 seconds
Started Apr 02 01:43:23 PM PDT 24
Finished Apr 02 01:43:27 PM PDT 24
Peak memory 209044 kb
Host smart-e1a9aaa5-ef91-4dd0-8795-1a3904d2e4bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771943171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3771943171
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3277906697
Short name T749
Test name
Test status
Simulation time 2921851192 ps
CPU time 21.39 seconds
Started Apr 02 01:43:24 PM PDT 24
Finished Apr 02 01:43:45 PM PDT 24
Peak memory 208216 kb
Host smart-8577810d-1769-497c-b9f7-ee9732e5234d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277906697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3277906697
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.472402880
Short name T633
Test name
Test status
Simulation time 2441099329 ps
CPU time 41.19 seconds
Started Apr 02 01:43:23 PM PDT 24
Finished Apr 02 01:44:04 PM PDT 24
Peak memory 208968 kb
Host smart-8c973a6a-0bcf-46ab-ba67-7f1129196c4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472402880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.472402880
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3288132983
Short name T382
Test name
Test status
Simulation time 117246640 ps
CPU time 4.73 seconds
Started Apr 02 01:43:29 PM PDT 24
Finished Apr 02 01:43:33 PM PDT 24
Peak memory 210264 kb
Host smart-74f6ad92-a3b5-4dda-a020-32c2ff0ad4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288132983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3288132983
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1376679144
Short name T135
Test name
Test status
Simulation time 206664331 ps
CPU time 2.73 seconds
Started Apr 02 01:43:24 PM PDT 24
Finished Apr 02 01:43:27 PM PDT 24
Peak memory 207544 kb
Host smart-d7edd227-e558-4f36-bb83-c431a7fefae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376679144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1376679144
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3531838292
Short name T584
Test name
Test status
Simulation time 601499663 ps
CPU time 13.56 seconds
Started Apr 02 01:43:32 PM PDT 24
Finished Apr 02 01:43:46 PM PDT 24
Peak memory 216400 kb
Host smart-9cb42ec6-69a8-4a23-9e31-a6a1ab57d882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531838292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3531838292
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2000902572
Short name T778
Test name
Test status
Simulation time 1642436587 ps
CPU time 58.63 seconds
Started Apr 02 01:43:25 PM PDT 24
Finished Apr 02 01:44:24 PM PDT 24
Peak memory 214652 kb
Host smart-c65ea280-a401-489e-ade0-195982fdea6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000902572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2000902572
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.906934786
Short name T555
Test name
Test status
Simulation time 282209183 ps
CPU time 0.83 seconds
Started Apr 02 01:43:40 PM PDT 24
Finished Apr 02 01:43:41 PM PDT 24
Peak memory 206224 kb
Host smart-06fba7bf-ae9f-4b4d-a305-af63d1fc15cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906934786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.906934786
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1859736454
Short name T303
Test name
Test status
Simulation time 196626569 ps
CPU time 3.65 seconds
Started Apr 02 01:43:31 PM PDT 24
Finished Apr 02 01:43:34 PM PDT 24
Peak memory 214520 kb
Host smart-7d413510-0496-447c-831f-ea6035c84785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859736454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1859736454
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2322575277
Short name T774
Test name
Test status
Simulation time 58098363 ps
CPU time 1.85 seconds
Started Apr 02 01:43:33 PM PDT 24
Finished Apr 02 01:43:35 PM PDT 24
Peak memory 214680 kb
Host smart-5ce7f4b5-95a8-4558-90e1-527b9de396f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322575277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2322575277
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2704526516
Short name T323
Test name
Test status
Simulation time 1205165507 ps
CPU time 34.83 seconds
Started Apr 02 01:43:38 PM PDT 24
Finished Apr 02 01:44:13 PM PDT 24
Peak memory 214520 kb
Host smart-351ce4d5-7088-4399-976f-59365c65103d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704526516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2704526516
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.184560412
Short name T796
Test name
Test status
Simulation time 83138993 ps
CPU time 3.06 seconds
Started Apr 02 01:43:33 PM PDT 24
Finished Apr 02 01:43:37 PM PDT 24
Peak memory 215060 kb
Host smart-c0156947-a41d-4220-ad43-d0f0cc5e9fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184560412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.184560412
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1783463192
Short name T377
Test name
Test status
Simulation time 348169332 ps
CPU time 9.4 seconds
Started Apr 02 01:43:33 PM PDT 24
Finished Apr 02 01:43:43 PM PDT 24
Peak memory 214616 kb
Host smart-bd358056-299c-4712-b0ab-af4572bc60cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783463192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1783463192
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3872376231
Short name T640
Test name
Test status
Simulation time 236674040 ps
CPU time 6.55 seconds
Started Apr 02 01:43:32 PM PDT 24
Finished Apr 02 01:43:39 PM PDT 24
Peak memory 208340 kb
Host smart-711d7333-6d9d-4e6b-b8f0-a9321611ba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872376231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3872376231
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2284426247
Short name T637
Test name
Test status
Simulation time 197354674 ps
CPU time 6.32 seconds
Started Apr 02 01:43:36 PM PDT 24
Finished Apr 02 01:43:42 PM PDT 24
Peak memory 208848 kb
Host smart-2a6632fb-a092-4166-91e2-047d48f10854
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284426247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2284426247
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3872648767
Short name T750
Test name
Test status
Simulation time 1045127447 ps
CPU time 33.44 seconds
Started Apr 02 01:43:38 PM PDT 24
Finished Apr 02 01:44:12 PM PDT 24
Peak memory 208396 kb
Host smart-22a5e394-6326-49b3-8ed1-4f7d994f47a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872648767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3872648767
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2832249572
Short name T346
Test name
Test status
Simulation time 121573483 ps
CPU time 4.43 seconds
Started Apr 02 01:43:33 PM PDT 24
Finished Apr 02 01:43:38 PM PDT 24
Peak memory 209128 kb
Host smart-5717cde1-12aa-4336-a148-7b66834d603f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832249572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2832249572
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.224125408
Short name T762
Test name
Test status
Simulation time 109395383 ps
CPU time 2.67 seconds
Started Apr 02 01:43:35 PM PDT 24
Finished Apr 02 01:43:38 PM PDT 24
Peak memory 210432 kb
Host smart-69684a0d-2c69-4875-b5d3-345a9dbce87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224125408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.224125408
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2116452845
Short name T655
Test name
Test status
Simulation time 24341102 ps
CPU time 1.76 seconds
Started Apr 02 01:43:32 PM PDT 24
Finished Apr 02 01:43:34 PM PDT 24
Peak memory 207052 kb
Host smart-dc77882e-ae85-4324-acae-18b546769026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116452845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2116452845
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3035757799
Short name T809
Test name
Test status
Simulation time 1394854701 ps
CPU time 11.26 seconds
Started Apr 02 01:43:35 PM PDT 24
Finished Apr 02 01:43:46 PM PDT 24
Peak memory 208452 kb
Host smart-c0cd4616-6324-48d9-8796-7e516bf4bb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035757799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3035757799
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.583246925
Short name T539
Test name
Test status
Simulation time 36881020 ps
CPU time 1.68 seconds
Started Apr 02 01:43:40 PM PDT 24
Finished Apr 02 01:43:42 PM PDT 24
Peak memory 209932 kb
Host smart-1400c1bc-a226-4dcb-8872-40053f83490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583246925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.583246925
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2336789326
Short name T439
Test name
Test status
Simulation time 45356050 ps
CPU time 0.84 seconds
Started Apr 02 01:43:49 PM PDT 24
Finished Apr 02 01:43:50 PM PDT 24
Peak memory 206228 kb
Host smart-5e7dffc0-9c5c-46b1-b23f-821f3f63afce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336789326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2336789326
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2880973364
Short name T379
Test name
Test status
Simulation time 42559887 ps
CPU time 3.21 seconds
Started Apr 02 01:43:44 PM PDT 24
Finished Apr 02 01:43:47 PM PDT 24
Peak memory 214684 kb
Host smart-1a3152d5-2304-4d9a-9a5a-6132aad8ed93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880973364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2880973364
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2625804774
Short name T506
Test name
Test status
Simulation time 50908081 ps
CPU time 2.57 seconds
Started Apr 02 01:43:48 PM PDT 24
Finished Apr 02 01:43:51 PM PDT 24
Peak memory 223132 kb
Host smart-63d07623-d335-4cf9-b493-418959398f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625804774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2625804774
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4219263463
Short name T285
Test name
Test status
Simulation time 52199243 ps
CPU time 2.02 seconds
Started Apr 02 01:43:41 PM PDT 24
Finished Apr 02 01:43:43 PM PDT 24
Peak memory 210016 kb
Host smart-f4f57429-de24-438a-a0dc-af3f21e1ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219263463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4219263463
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1911610403
Short name T386
Test name
Test status
Simulation time 398462293 ps
CPU time 6.54 seconds
Started Apr 02 01:43:48 PM PDT 24
Finished Apr 02 01:43:55 PM PDT 24
Peak memory 221136 kb
Host smart-2da6d5ca-9753-4eac-af8c-e87ffaea7a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911610403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1911610403
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1746843781
Short name T741
Test name
Test status
Simulation time 375433092 ps
CPU time 4.24 seconds
Started Apr 02 01:43:44 PM PDT 24
Finished Apr 02 01:43:49 PM PDT 24
Peak memory 210164 kb
Host smart-43fcb33d-b52a-4dc4-9d83-6e1663b3d8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746843781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1746843781
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3966538031
Short name T708
Test name
Test status
Simulation time 511686203 ps
CPU time 4.43 seconds
Started Apr 02 01:43:43 PM PDT 24
Finished Apr 02 01:43:48 PM PDT 24
Peak memory 214704 kb
Host smart-4c52162c-48e0-42a8-be69-1572e833245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966538031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3966538031
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1497338266
Short name T301
Test name
Test status
Simulation time 204182728 ps
CPU time 3.17 seconds
Started Apr 02 01:43:42 PM PDT 24
Finished Apr 02 01:43:45 PM PDT 24
Peak memory 209208 kb
Host smart-26fd11eb-0a66-4a29-8131-6e88240176cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497338266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1497338266
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3804688905
Short name T575
Test name
Test status
Simulation time 233031157 ps
CPU time 3.98 seconds
Started Apr 02 01:43:43 PM PDT 24
Finished Apr 02 01:43:47 PM PDT 24
Peak memory 207084 kb
Host smart-e7e2b4cd-9181-45a1-ae08-dbe5da39cb9f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804688905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3804688905
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.429131245
Short name T352
Test name
Test status
Simulation time 85875072 ps
CPU time 3.32 seconds
Started Apr 02 01:43:42 PM PDT 24
Finished Apr 02 01:43:45 PM PDT 24
Peak memory 208668 kb
Host smart-6dc8b79e-a1d4-4d68-8d26-46e68947abd6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429131245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.429131245
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.413259254
Short name T551
Test name
Test status
Simulation time 128725822 ps
CPU time 3.37 seconds
Started Apr 02 01:43:43 PM PDT 24
Finished Apr 02 01:43:46 PM PDT 24
Peak memory 207180 kb
Host smart-d8ff5ae5-61a7-47cd-9c35-31512d49122e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413259254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.413259254
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3941674775
Short name T746
Test name
Test status
Simulation time 140458789 ps
CPU time 3.84 seconds
Started Apr 02 01:43:47 PM PDT 24
Finished Apr 02 01:43:51 PM PDT 24
Peak memory 210124 kb
Host smart-f618fb10-f877-46d9-b515-d2f903b4904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941674775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3941674775
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.956861896
Short name T822
Test name
Test status
Simulation time 32495899 ps
CPU time 2.14 seconds
Started Apr 02 01:43:41 PM PDT 24
Finished Apr 02 01:43:43 PM PDT 24
Peak memory 206888 kb
Host smart-d63a24d9-45a9-4bb6-aa84-7474a1f4c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956861896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.956861896
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2035194053
Short name T353
Test name
Test status
Simulation time 711357333 ps
CPU time 28.38 seconds
Started Apr 02 01:43:49 PM PDT 24
Finished Apr 02 01:44:17 PM PDT 24
Peak memory 222588 kb
Host smart-76a8db51-ffcf-4c47-aa29-519075db5a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035194053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2035194053
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1750183924
Short name T137
Test name
Test status
Simulation time 1172507693 ps
CPU time 7.32 seconds
Started Apr 02 01:43:49 PM PDT 24
Finished Apr 02 01:43:57 PM PDT 24
Peak memory 210464 kb
Host smart-584e6b5c-63dd-4cc7-ab43-1a7fbbf4b67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750183924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1750183924
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2396109767
Short name T176
Test name
Test status
Simulation time 41507747 ps
CPU time 1.51 seconds
Started Apr 02 01:43:48 PM PDT 24
Finished Apr 02 01:43:50 PM PDT 24
Peak memory 209868 kb
Host smart-8e24a3ef-620e-4101-9798-494bc52e047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396109767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2396109767
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1362507412
Short name T461
Test name
Test status
Simulation time 20868631 ps
CPU time 0.75 seconds
Started Apr 02 01:43:56 PM PDT 24
Finished Apr 02 01:43:57 PM PDT 24
Peak memory 206288 kb
Host smart-6dd6bcf6-abf5-469c-8ffb-4d245b7ae3a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362507412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1362507412
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.4095189155
Short name T405
Test name
Test status
Simulation time 149721022 ps
CPU time 2.82 seconds
Started Apr 02 01:43:54 PM PDT 24
Finished Apr 02 01:43:57 PM PDT 24
Peak memory 214716 kb
Host smart-a692c7d2-b7be-41a5-b1d1-60b01ce008eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095189155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.4095189155
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.944957326
Short name T794
Test name
Test status
Simulation time 352045731 ps
CPU time 3.95 seconds
Started Apr 02 01:43:57 PM PDT 24
Finished Apr 02 01:44:01 PM PDT 24
Peak memory 208808 kb
Host smart-ef49e083-f87f-40dc-ba7f-d17cd44675ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944957326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.944957326
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3767224861
Short name T409
Test name
Test status
Simulation time 392886315 ps
CPU time 3.38 seconds
Started Apr 02 01:43:53 PM PDT 24
Finished Apr 02 01:43:57 PM PDT 24
Peak memory 218580 kb
Host smart-f0008f12-d1ac-4c70-a2ab-796a50c4d366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767224861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3767224861
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3856300596
Short name T566
Test name
Test status
Simulation time 67262457 ps
CPU time 3.51 seconds
Started Apr 02 01:43:53 PM PDT 24
Finished Apr 02 01:43:57 PM PDT 24
Peak memory 208988 kb
Host smart-f06feda0-e4cd-4bfe-b9bf-5ac13fae44ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856300596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3856300596
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1294368001
Short name T503
Test name
Test status
Simulation time 279260020 ps
CPU time 2.73 seconds
Started Apr 02 01:43:49 PM PDT 24
Finished Apr 02 01:43:52 PM PDT 24
Peak memory 207088 kb
Host smart-e203ec09-032b-4f7f-80ef-0542b7a0c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294368001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1294368001
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.4098683647
Short name T615
Test name
Test status
Simulation time 849217329 ps
CPU time 6.7 seconds
Started Apr 02 01:43:53 PM PDT 24
Finished Apr 02 01:44:00 PM PDT 24
Peak memory 208248 kb
Host smart-c3b37184-6133-46c6-86b0-5844fc88855f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098683647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.4098683647
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1962856779
Short name T515
Test name
Test status
Simulation time 93510710 ps
CPU time 2.43 seconds
Started Apr 02 01:43:57 PM PDT 24
Finished Apr 02 01:44:00 PM PDT 24
Peak memory 207120 kb
Host smart-7916dd57-7e65-4f31-94a6-fd06ae3ff442
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962856779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1962856779
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2569077278
Short name T710
Test name
Test status
Simulation time 94485572 ps
CPU time 3.16 seconds
Started Apr 02 01:43:53 PM PDT 24
Finished Apr 02 01:43:57 PM PDT 24
Peak memory 207264 kb
Host smart-74515a8b-5f06-4799-9c97-0d91fa57dbb4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569077278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2569077278
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4017991312
Short name T274
Test name
Test status
Simulation time 96814565 ps
CPU time 1.95 seconds
Started Apr 02 01:43:58 PM PDT 24
Finished Apr 02 01:44:00 PM PDT 24
Peak memory 215784 kb
Host smart-a6458eb1-da85-4b8f-8642-b7b5bb2853bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017991312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4017991312
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.503607066
Short name T760
Test name
Test status
Simulation time 75856207 ps
CPU time 2.83 seconds
Started Apr 02 01:43:50 PM PDT 24
Finished Apr 02 01:43:53 PM PDT 24
Peak memory 208516 kb
Host smart-cc5dc471-eae2-4527-ad9d-d9652e6e7b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503607066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.503607066
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3486271066
Short name T485
Test name
Test status
Simulation time 178291171 ps
CPU time 5.53 seconds
Started Apr 02 01:43:53 PM PDT 24
Finished Apr 02 01:43:59 PM PDT 24
Peak memory 218664 kb
Host smart-5ef33ced-7564-4ee4-b900-dfe8bdbb6340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486271066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3486271066
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3944984065
Short name T460
Test name
Test status
Simulation time 31362840 ps
CPU time 0.81 seconds
Started Apr 02 01:44:10 PM PDT 24
Finished Apr 02 01:44:11 PM PDT 24
Peak memory 206296 kb
Host smart-88462ce3-35a9-4c15-96c3-d6221608f6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944984065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3944984065
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.44560657
Short name T201
Test name
Test status
Simulation time 211015720 ps
CPU time 3.48 seconds
Started Apr 02 01:44:08 PM PDT 24
Finished Apr 02 01:44:12 PM PDT 24
Peak memory 210224 kb
Host smart-f8fb385d-b2ea-4b59-8957-cb0a4251491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44560657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.44560657
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3272398393
Short name T476
Test name
Test status
Simulation time 101209660 ps
CPU time 1.59 seconds
Started Apr 02 01:44:03 PM PDT 24
Finished Apr 02 01:44:05 PM PDT 24
Peak memory 208100 kb
Host smart-3a491808-c11f-4362-9d65-b4a5d1280f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272398393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3272398393
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2406125696
Short name T603
Test name
Test status
Simulation time 104187202 ps
CPU time 4.63 seconds
Started Apr 02 01:44:05 PM PDT 24
Finished Apr 02 01:44:10 PM PDT 24
Peak memory 210664 kb
Host smart-5fa84429-853b-4a21-8e4c-963e0c4b7110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406125696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2406125696
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1831802979
Short name T266
Test name
Test status
Simulation time 254424264 ps
CPU time 3.91 seconds
Started Apr 02 01:44:03 PM PDT 24
Finished Apr 02 01:44:07 PM PDT 24
Peak memory 208804 kb
Host smart-0c52c8bd-000c-43df-9e93-2387eacab67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831802979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1831802979
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1066349408
Short name T674
Test name
Test status
Simulation time 470388933 ps
CPU time 7.88 seconds
Started Apr 02 01:44:01 PM PDT 24
Finished Apr 02 01:44:09 PM PDT 24
Peak memory 209532 kb
Host smart-89ef04f0-e67f-44ad-be10-ab8ec4054174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066349408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1066349408
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1050851271
Short name T709
Test name
Test status
Simulation time 527593840 ps
CPU time 17.91 seconds
Started Apr 02 01:44:00 PM PDT 24
Finished Apr 02 01:44:18 PM PDT 24
Peak memory 208888 kb
Host smart-897356f8-3c5c-49c5-bf01-049432cdeb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050851271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1050851271
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2355246257
Short name T876
Test name
Test status
Simulation time 2478240861 ps
CPU time 17.72 seconds
Started Apr 02 01:44:02 PM PDT 24
Finished Apr 02 01:44:20 PM PDT 24
Peak memory 209592 kb
Host smart-c355b75e-6e04-48aa-b026-88e5d58aaff8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355246257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2355246257
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1575299794
Short name T879
Test name
Test status
Simulation time 428118673 ps
CPU time 4.04 seconds
Started Apr 02 01:44:00 PM PDT 24
Finished Apr 02 01:44:04 PM PDT 24
Peak memory 208832 kb
Host smart-7d6bc775-8c42-4562-80c7-6c7767dbace7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575299794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1575299794
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3062075080
Short name T828
Test name
Test status
Simulation time 84541531 ps
CPU time 2.61 seconds
Started Apr 02 01:44:00 PM PDT 24
Finished Apr 02 01:44:02 PM PDT 24
Peak memory 207212 kb
Host smart-ae40d593-a951-41c0-903f-3ec52a168459
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062075080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3062075080
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1236586865
Short name T448
Test name
Test status
Simulation time 122249246 ps
CPU time 2.07 seconds
Started Apr 02 01:44:06 PM PDT 24
Finished Apr 02 01:44:08 PM PDT 24
Peak memory 209528 kb
Host smart-09c56cf8-7c4b-4a27-a3df-f5428f4c6d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236586865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1236586865
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2647475145
Short name T798
Test name
Test status
Simulation time 637051349 ps
CPU time 6.44 seconds
Started Apr 02 01:43:56 PM PDT 24
Finished Apr 02 01:44:02 PM PDT 24
Peak memory 208092 kb
Host smart-f2ed88d8-6d23-4671-a424-6868b8c66e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647475145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2647475145
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.470181960
Short name T373
Test name
Test status
Simulation time 1465622988 ps
CPU time 31.1 seconds
Started Apr 02 01:44:08 PM PDT 24
Finished Apr 02 01:44:39 PM PDT 24
Peak memory 215424 kb
Host smart-f02eb83f-e13b-46c7-befc-7c85fb7852c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470181960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.470181960
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1786755360
Short name T187
Test name
Test status
Simulation time 1161443211 ps
CPU time 11.47 seconds
Started Apr 02 01:44:07 PM PDT 24
Finished Apr 02 01:44:19 PM PDT 24
Peak memory 222968 kb
Host smart-5e8d70c5-09b5-4106-9f14-0d5d4e012ae0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786755360 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1786755360
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1150586361
Short name T312
Test name
Test status
Simulation time 232607674 ps
CPU time 3.48 seconds
Started Apr 02 01:44:05 PM PDT 24
Finished Apr 02 01:44:09 PM PDT 24
Peak memory 210128 kb
Host smart-4c1c92bb-bdd0-4700-bad4-b5c0eb7c4623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150586361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1150586361
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.923587357
Short name T629
Test name
Test status
Simulation time 83463701 ps
CPU time 1.4 seconds
Started Apr 02 01:44:07 PM PDT 24
Finished Apr 02 01:44:09 PM PDT 24
Peak memory 210028 kb
Host smart-27bbd102-444f-40bf-907e-01f1cbd1c1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923587357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.923587357
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1096887118
Short name T581
Test name
Test status
Simulation time 95024657 ps
CPU time 0.73 seconds
Started Apr 02 01:44:17 PM PDT 24
Finished Apr 02 01:44:18 PM PDT 24
Peak memory 206320 kb
Host smart-583637ea-43b5-4420-b381-b51d2bac7ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096887118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1096887118
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3398298367
Short name T33
Test name
Test status
Simulation time 1284221943 ps
CPU time 37.24 seconds
Started Apr 02 01:44:13 PM PDT 24
Finished Apr 02 01:44:50 PM PDT 24
Peak memory 221512 kb
Host smart-c2f13731-a851-410b-9957-9a62b8056465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398298367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3398298367
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2983767905
Short name T580
Test name
Test status
Simulation time 170988878 ps
CPU time 2.31 seconds
Started Apr 02 01:44:12 PM PDT 24
Finished Apr 02 01:44:14 PM PDT 24
Peak memory 209796 kb
Host smart-b153f9ec-03bc-40a0-a9a4-5e84f12b7b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983767905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2983767905
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1528527272
Short name T339
Test name
Test status
Simulation time 335789149 ps
CPU time 8.28 seconds
Started Apr 02 01:44:12 PM PDT 24
Finished Apr 02 01:44:21 PM PDT 24
Peak memory 214620 kb
Host smart-6718b5b2-78d0-4100-aade-2c8cda2afe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528527272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1528527272
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3706609091
Short name T462
Test name
Test status
Simulation time 146652736 ps
CPU time 2.37 seconds
Started Apr 02 01:44:13 PM PDT 24
Finished Apr 02 01:44:15 PM PDT 24
Peak memory 208556 kb
Host smart-9838257c-9cd3-4219-9c47-b7ba2ac87a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706609091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3706609091
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.81751444
Short name T715
Test name
Test status
Simulation time 4851656559 ps
CPU time 69.5 seconds
Started Apr 02 01:44:10 PM PDT 24
Finished Apr 02 01:45:20 PM PDT 24
Peak memory 209524 kb
Host smart-b46e502e-d9fd-4846-998e-1b48f7687149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81751444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.81751444
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.487470306
Short name T469
Test name
Test status
Simulation time 58218069 ps
CPU time 2.5 seconds
Started Apr 02 01:44:07 PM PDT 24
Finished Apr 02 01:44:10 PM PDT 24
Peak memory 207072 kb
Host smart-9b827fac-7da7-4677-8710-5cad6af4073c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487470306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.487470306
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3207203126
Short name T491
Test name
Test status
Simulation time 777382708 ps
CPU time 8.66 seconds
Started Apr 02 01:44:11 PM PDT 24
Finished Apr 02 01:44:20 PM PDT 24
Peak memory 208996 kb
Host smart-2ba3e49e-b6bd-43a3-b9ac-f5237166e2d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207203126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3207203126
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1951605138
Short name T543
Test name
Test status
Simulation time 103004529 ps
CPU time 3.53 seconds
Started Apr 02 01:44:08 PM PDT 24
Finished Apr 02 01:44:12 PM PDT 24
Peak memory 208788 kb
Host smart-dd42ac2d-86f8-4df1-a8a0-c73c63573d5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951605138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1951605138
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.213083137
Short name T556
Test name
Test status
Simulation time 34325468 ps
CPU time 1.83 seconds
Started Apr 02 01:44:09 PM PDT 24
Finished Apr 02 01:44:11 PM PDT 24
Peak memory 207056 kb
Host smart-dc190a23-e379-456d-80fd-499d310d6dba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213083137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.213083137
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2715674863
Short name T811
Test name
Test status
Simulation time 192502601 ps
CPU time 2.76 seconds
Started Apr 02 01:44:13 PM PDT 24
Finished Apr 02 01:44:16 PM PDT 24
Peak memory 209388 kb
Host smart-1603df1f-b7ed-4a14-990f-2c57ed56be11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715674863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2715674863
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1631475566
Short name T821
Test name
Test status
Simulation time 164994959 ps
CPU time 2.87 seconds
Started Apr 02 01:44:09 PM PDT 24
Finished Apr 02 01:44:11 PM PDT 24
Peak memory 207100 kb
Host smart-28edbe40-0f6c-41ce-b38c-41c99f731812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631475566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1631475566
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1356061842
Short name T132
Test name
Test status
Simulation time 66386809 ps
CPU time 2.34 seconds
Started Apr 02 01:44:20 PM PDT 24
Finished Apr 02 01:44:22 PM PDT 24
Peak memory 210488 kb
Host smart-4fb332cc-b5ca-45a1-8773-d6b6e1735d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356061842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1356061842
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1243421068
Short name T577
Test name
Test status
Simulation time 40125073 ps
CPU time 0.85 seconds
Started Apr 02 01:44:25 PM PDT 24
Finished Apr 02 01:44:27 PM PDT 24
Peak memory 206152 kb
Host smart-e5c54b08-a4e6-4485-96e0-817621ef02fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243421068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1243421068
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.373811487
Short name T433
Test name
Test status
Simulation time 238848626 ps
CPU time 3.88 seconds
Started Apr 02 01:44:24 PM PDT 24
Finished Apr 02 01:44:28 PM PDT 24
Peak memory 214988 kb
Host smart-afab4921-7700-468d-8872-d80a2ea29127
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373811487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.373811487
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.351810433
Short name T573
Test name
Test status
Simulation time 527818183 ps
CPU time 4.21 seconds
Started Apr 02 01:44:20 PM PDT 24
Finished Apr 02 01:44:25 PM PDT 24
Peak memory 209384 kb
Host smart-4ae95b83-daeb-4e3d-a6c6-ab1aaa2f54a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351810433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.351810433
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.93863815
Short name T412
Test name
Test status
Simulation time 340258024 ps
CPU time 4.77 seconds
Started Apr 02 01:44:20 PM PDT 24
Finished Apr 02 01:44:25 PM PDT 24
Peak memory 209572 kb
Host smart-e9645204-434e-4638-bc08-182076f382b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93863815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.93863815
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2605689682
Short name T237
Test name
Test status
Simulation time 112835899 ps
CPU time 2.63 seconds
Started Apr 02 01:44:22 PM PDT 24
Finished Apr 02 01:44:25 PM PDT 24
Peak memory 209392 kb
Host smart-921a7e95-ad0a-4b78-8ee4-29d365dfd4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605689682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2605689682
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.943938659
Short name T797
Test name
Test status
Simulation time 164311851 ps
CPU time 5.05 seconds
Started Apr 02 01:44:22 PM PDT 24
Finished Apr 02 01:44:27 PM PDT 24
Peak memory 208068 kb
Host smart-a56bd403-62bc-48e9-9a6a-e58c8614ceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943938659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.943938659
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3058128576
Short name T225
Test name
Test status
Simulation time 51472523 ps
CPU time 2.78 seconds
Started Apr 02 01:44:16 PM PDT 24
Finished Apr 02 01:44:19 PM PDT 24
Peak memory 207112 kb
Host smart-e1839fb4-d6b0-4c6b-924d-7b61168b28c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058128576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3058128576
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3624364694
Short name T784
Test name
Test status
Simulation time 365770400 ps
CPU time 5.85 seconds
Started Apr 02 01:44:21 PM PDT 24
Finished Apr 02 01:44:27 PM PDT 24
Peak memory 208980 kb
Host smart-1fcf7c73-5890-4f5d-a78a-c4fd20b66bde
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624364694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3624364694
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1369108127
Short name T500
Test name
Test status
Simulation time 32847120 ps
CPU time 2.44 seconds
Started Apr 02 01:44:18 PM PDT 24
Finished Apr 02 01:44:21 PM PDT 24
Peak memory 207248 kb
Host smart-cec4358e-c60b-45e6-9918-a0b5c68be405
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369108127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1369108127
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.839095420
Short name T659
Test name
Test status
Simulation time 38914192 ps
CPU time 1.8 seconds
Started Apr 02 01:44:18 PM PDT 24
Finished Apr 02 01:44:20 PM PDT 24
Peak memory 207156 kb
Host smart-f0300eb9-58b4-4d2b-b6ff-448d7fd08713
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839095420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.839095420
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2576995778
Short name T559
Test name
Test status
Simulation time 39788171 ps
CPU time 2.27 seconds
Started Apr 02 01:44:22 PM PDT 24
Finished Apr 02 01:44:25 PM PDT 24
Peak memory 215900 kb
Host smart-77b4f0ad-8aaa-4b51-9247-5c6575574b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576995778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2576995778
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.4285216192
Short name T214
Test name
Test status
Simulation time 49349371 ps
CPU time 2.47 seconds
Started Apr 02 01:44:20 PM PDT 24
Finished Apr 02 01:44:23 PM PDT 24
Peak memory 208372 kb
Host smart-5b583a3f-516a-4615-b4f8-ff870b1e48a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285216192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.4285216192
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1481947684
Short name T520
Test name
Test status
Simulation time 12147936665 ps
CPU time 25.25 seconds
Started Apr 02 01:44:22 PM PDT 24
Finished Apr 02 01:44:47 PM PDT 24
Peak memory 209428 kb
Host smart-36f709a0-78ac-41e7-9bbc-55edc5070143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481947684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1481947684
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1660143168
Short name T402
Test name
Test status
Simulation time 437465112 ps
CPU time 6.6 seconds
Started Apr 02 01:44:24 PM PDT 24
Finished Apr 02 01:44:31 PM PDT 24
Peak memory 210576 kb
Host smart-01ad70dd-2fb9-4c36-aa6a-a20b70ae4bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660143168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1660143168
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2200399635
Short name T2
Test name
Test status
Simulation time 27251544 ps
CPU time 1.11 seconds
Started Apr 02 01:44:36 PM PDT 24
Finished Apr 02 01:44:37 PM PDT 24
Peak memory 206488 kb
Host smart-8f538531-8a87-4664-aa63-b5742eec9c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200399635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2200399635
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3617752018
Short name T404
Test name
Test status
Simulation time 337911008 ps
CPU time 9.03 seconds
Started Apr 02 01:44:37 PM PDT 24
Finished Apr 02 01:44:47 PM PDT 24
Peak memory 214952 kb
Host smart-4c506713-0a43-4b5b-83b8-149094082add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3617752018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3617752018
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3992235617
Short name T315
Test name
Test status
Simulation time 458007365 ps
CPU time 3.72 seconds
Started Apr 02 01:44:30 PM PDT 24
Finished Apr 02 01:44:34 PM PDT 24
Peak memory 207496 kb
Host smart-48652470-3707-4dba-8d3f-f0008ba348ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992235617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3992235617
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1405406333
Short name T100
Test name
Test status
Simulation time 2217822435 ps
CPU time 6.14 seconds
Started Apr 02 01:44:30 PM PDT 24
Finished Apr 02 01:44:36 PM PDT 24
Peak memory 214800 kb
Host smart-9caa2839-b6a5-4b99-8dfc-11086ddca358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405406333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1405406333
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1540699626
Short name T318
Test name
Test status
Simulation time 1047814053 ps
CPU time 8.47 seconds
Started Apr 02 01:44:32 PM PDT 24
Finished Apr 02 01:44:41 PM PDT 24
Peak memory 214568 kb
Host smart-36801c39-5f8b-48c1-9e02-ae38f59ab840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540699626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1540699626
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2904474540
Short name T804
Test name
Test status
Simulation time 314581002 ps
CPU time 3.91 seconds
Started Apr 02 01:44:30 PM PDT 24
Finished Apr 02 01:44:34 PM PDT 24
Peak memory 214632 kb
Host smart-37195e57-0ee5-4b66-8f25-2d1138f6bfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904474540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2904474540
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.321606108
Short name T282
Test name
Test status
Simulation time 331350492 ps
CPU time 8.94 seconds
Started Apr 02 01:44:27 PM PDT 24
Finished Apr 02 01:44:36 PM PDT 24
Peak memory 218920 kb
Host smart-6f5e57c5-a975-4302-9f89-af885c009e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321606108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.321606108
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.443823673
Short name T639
Test name
Test status
Simulation time 104657327 ps
CPU time 3.88 seconds
Started Apr 02 01:44:24 PM PDT 24
Finished Apr 02 01:44:28 PM PDT 24
Peak memory 208944 kb
Host smart-4276e64a-ce76-4d7e-a44e-68ca3280e60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443823673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.443823673
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2631996824
Short name T583
Test name
Test status
Simulation time 344202509 ps
CPU time 3.84 seconds
Started Apr 02 01:44:26 PM PDT 24
Finished Apr 02 01:44:30 PM PDT 24
Peak memory 209052 kb
Host smart-58998b67-23ce-4f02-b4b4-dab7abafb63d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631996824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2631996824
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1923713785
Short name T544
Test name
Test status
Simulation time 1092255635 ps
CPU time 7.36 seconds
Started Apr 02 01:44:27 PM PDT 24
Finished Apr 02 01:44:34 PM PDT 24
Peak memory 209056 kb
Host smart-4e8dc895-cfb6-487d-aa01-d7b0cc125f55
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923713785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1923713785
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2882753900
Short name T893
Test name
Test status
Simulation time 37609943 ps
CPU time 1.77 seconds
Started Apr 02 01:44:26 PM PDT 24
Finished Apr 02 01:44:28 PM PDT 24
Peak memory 207104 kb
Host smart-adbde2b6-947f-4acd-87b1-ea018ace1033
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882753900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2882753900
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4000919349
Short name T529
Test name
Test status
Simulation time 907981513 ps
CPU time 8.31 seconds
Started Apr 02 01:44:30 PM PDT 24
Finished Apr 02 01:44:39 PM PDT 24
Peak memory 209604 kb
Host smart-1dd6cf10-1f92-4e2d-a7cf-d1f88511acab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000919349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4000919349
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4195132406
Short name T415
Test name
Test status
Simulation time 126762369 ps
CPU time 2.28 seconds
Started Apr 02 01:44:25 PM PDT 24
Finished Apr 02 01:44:27 PM PDT 24
Peak memory 207180 kb
Host smart-b4d1b953-e11e-4b84-a84d-6e45a5eb0041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195132406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4195132406
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.840242867
Short name T43
Test name
Test status
Simulation time 292057708 ps
CPU time 2.72 seconds
Started Apr 02 01:44:28 PM PDT 24
Finished Apr 02 01:44:31 PM PDT 24
Peak memory 214680 kb
Host smart-06688ec5-65d0-44b5-84d2-99370f668370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840242867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.840242867
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2001997311
Short name T311
Test name
Test status
Simulation time 282041273 ps
CPU time 3.61 seconds
Started Apr 02 01:44:31 PM PDT 24
Finished Apr 02 01:44:35 PM PDT 24
Peak memory 214672 kb
Host smart-ecd028f8-4e46-414e-a338-944720a33153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001997311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2001997311
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3580338956
Short name T840
Test name
Test status
Simulation time 577340417 ps
CPU time 9.47 seconds
Started Apr 02 01:44:33 PM PDT 24
Finished Apr 02 01:44:42 PM PDT 24
Peak memory 210772 kb
Host smart-a9cf291f-59df-41d2-a452-64378c3478a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580338956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3580338956
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2476806161
Short name T873
Test name
Test status
Simulation time 30022898 ps
CPU time 0.75 seconds
Started Apr 02 01:44:41 PM PDT 24
Finished Apr 02 01:44:42 PM PDT 24
Peak memory 206268 kb
Host smart-9a2fabcc-24bf-4829-b386-45d1305ea759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476806161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2476806161
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1933017012
Short name T408
Test name
Test status
Simulation time 284683273 ps
CPU time 4.04 seconds
Started Apr 02 01:44:38 PM PDT 24
Finished Apr 02 01:44:43 PM PDT 24
Peak memory 214600 kb
Host smart-47932460-6a56-4de0-a8d8-bd29f515d60d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933017012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1933017012
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1775576684
Short name T622
Test name
Test status
Simulation time 170004868 ps
CPU time 3.25 seconds
Started Apr 02 01:44:38 PM PDT 24
Finished Apr 02 01:44:42 PM PDT 24
Peak memory 209316 kb
Host smart-b120d804-f683-48f1-a81c-9e3dd992b878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775576684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1775576684
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1868914067
Short name T71
Test name
Test status
Simulation time 69216377 ps
CPU time 2.08 seconds
Started Apr 02 01:44:36 PM PDT 24
Finished Apr 02 01:44:38 PM PDT 24
Peak memory 209668 kb
Host smart-51de1829-3a20-40d1-b5b2-21c17289b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868914067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1868914067
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3369755589
Short name T578
Test name
Test status
Simulation time 125484805 ps
CPU time 4.33 seconds
Started Apr 02 01:44:37 PM PDT 24
Finished Apr 02 01:44:42 PM PDT 24
Peak memory 209048 kb
Host smart-bcee3a06-93d5-4d88-8c8b-021dfeca12ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369755589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3369755589
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1978345949
Short name T65
Test name
Test status
Simulation time 260485224 ps
CPU time 3.51 seconds
Started Apr 02 01:44:37 PM PDT 24
Finished Apr 02 01:44:42 PM PDT 24
Peak memory 220656 kb
Host smart-61a926c3-6184-4eb7-bc9f-17fa46e91186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978345949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1978345949
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.157656939
Short name T295
Test name
Test status
Simulation time 82600846 ps
CPU time 4.4 seconds
Started Apr 02 01:44:35 PM PDT 24
Finished Apr 02 01:44:40 PM PDT 24
Peak memory 219276 kb
Host smart-d5b6e4c9-7c15-44f8-8b28-f497c054443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157656939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.157656939
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3928047281
Short name T494
Test name
Test status
Simulation time 66804868 ps
CPU time 3.02 seconds
Started Apr 02 01:44:36 PM PDT 24
Finished Apr 02 01:44:40 PM PDT 24
Peak memory 207072 kb
Host smart-24f45055-0f97-49e3-aaaa-e4622e744c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928047281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3928047281
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.604318503
Short name T599
Test name
Test status
Simulation time 92109441 ps
CPU time 2.76 seconds
Started Apr 02 01:44:33 PM PDT 24
Finished Apr 02 01:44:36 PM PDT 24
Peak memory 209140 kb
Host smart-7c0cd909-20b3-412a-9773-927c75ad7132
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604318503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.604318503
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4184823875
Short name T679
Test name
Test status
Simulation time 120433710 ps
CPU time 2.87 seconds
Started Apr 02 01:44:35 PM PDT 24
Finished Apr 02 01:44:39 PM PDT 24
Peak memory 208928 kb
Host smart-2a25ada9-9af5-4b42-a3bd-eca16e8edfab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184823875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4184823875
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3739682643
Short name T761
Test name
Test status
Simulation time 126745016 ps
CPU time 2.52 seconds
Started Apr 02 01:44:35 PM PDT 24
Finished Apr 02 01:44:38 PM PDT 24
Peak memory 208948 kb
Host smart-93d7aae1-c88e-4ff1-b617-86e3af0ed39a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739682643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3739682643
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4143976482
Short name T839
Test name
Test status
Simulation time 64325188 ps
CPU time 3.05 seconds
Started Apr 02 01:44:42 PM PDT 24
Finished Apr 02 01:44:45 PM PDT 24
Peak memory 209944 kb
Host smart-e8ca042d-e9a9-41aa-9847-9c0ea00b1cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143976482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4143976482
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1672552600
Short name T518
Test name
Test status
Simulation time 297903385 ps
CPU time 6.91 seconds
Started Apr 02 01:44:35 PM PDT 24
Finished Apr 02 01:44:43 PM PDT 24
Peak memory 207992 kb
Host smart-85cca930-3b1b-4f3c-ac0f-11c8b876a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672552600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1672552600
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1408872107
Short name T792
Test name
Test status
Simulation time 280038457 ps
CPU time 11.37 seconds
Started Apr 02 01:44:41 PM PDT 24
Finished Apr 02 01:44:52 PM PDT 24
Peak memory 219364 kb
Host smart-3c6a7323-c7b3-4ee9-8910-2b6eb7255018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408872107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1408872107
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4277955122
Short name T548
Test name
Test status
Simulation time 1256698658 ps
CPU time 10.93 seconds
Started Apr 02 01:44:35 PM PDT 24
Finished Apr 02 01:44:47 PM PDT 24
Peak memory 218828 kb
Host smart-e747df21-b8ca-47da-b668-121dcf360209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277955122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4277955122
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1225081319
Short name T677
Test name
Test status
Simulation time 64049635 ps
CPU time 2.15 seconds
Started Apr 02 01:44:39 PM PDT 24
Finished Apr 02 01:44:42 PM PDT 24
Peak memory 210364 kb
Host smart-35a41ffa-05c9-4a9d-beba-6cee53fe7d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225081319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1225081319
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.668948405
Short name T667
Test name
Test status
Simulation time 44810340 ps
CPU time 0.89 seconds
Started Apr 02 01:42:01 PM PDT 24
Finished Apr 02 01:42:02 PM PDT 24
Peak memory 206304 kb
Host smart-a6c417b6-7fa4-46dd-ae2e-e106f7eda238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668948405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.668948405
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1989044651
Short name T299
Test name
Test status
Simulation time 443449170 ps
CPU time 3.14 seconds
Started Apr 02 01:41:50 PM PDT 24
Finished Apr 02 01:41:53 PM PDT 24
Peak memory 207612 kb
Host smart-e7897867-61fb-4d36-89f4-443828459277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989044651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1989044651
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.861784055
Short name T853
Test name
Test status
Simulation time 105046815 ps
CPU time 2.33 seconds
Started Apr 02 01:41:54 PM PDT 24
Finished Apr 02 01:41:57 PM PDT 24
Peak memory 209364 kb
Host smart-ce229fe2-f9ef-468f-9a3c-454a9e6dbd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861784055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.861784055
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3799550185
Short name T481
Test name
Test status
Simulation time 292352503 ps
CPU time 2.04 seconds
Started Apr 02 01:41:50 PM PDT 24
Finished Apr 02 01:41:52 PM PDT 24
Peak memory 206620 kb
Host smart-c14ca117-8d59-46fd-882b-aca20b473817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799550185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3799550185
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3046966539
Short name T825
Test name
Test status
Simulation time 90048712 ps
CPU time 4.29 seconds
Started Apr 02 01:41:51 PM PDT 24
Finished Apr 02 01:41:56 PM PDT 24
Peak memory 210096 kb
Host smart-24104b00-631d-4a89-85ef-8629b5e6270d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046966539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3046966539
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3753167812
Short name T420
Test name
Test status
Simulation time 615212735 ps
CPU time 5.08 seconds
Started Apr 02 01:41:47 PM PDT 24
Finished Apr 02 01:41:52 PM PDT 24
Peak memory 208696 kb
Host smart-7efc2753-ce4e-45a5-9abb-f7b7e6be8816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753167812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3753167812
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1817796114
Short name T651
Test name
Test status
Simulation time 48704856 ps
CPU time 2.82 seconds
Started Apr 02 01:41:47 PM PDT 24
Finished Apr 02 01:41:50 PM PDT 24
Peak memory 207128 kb
Host smart-5d1c9512-c09b-4bcb-927b-7cbe9998e123
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817796114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1817796114
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2422812324
Short name T666
Test name
Test status
Simulation time 93376354 ps
CPU time 2.48 seconds
Started Apr 02 01:41:45 PM PDT 24
Finished Apr 02 01:41:48 PM PDT 24
Peak memory 207176 kb
Host smart-e9c98d07-10a2-450c-9a89-8fa609cbe92b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422812324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2422812324
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2332495771
Short name T630
Test name
Test status
Simulation time 153661789 ps
CPU time 6.27 seconds
Started Apr 02 01:41:49 PM PDT 24
Finished Apr 02 01:41:55 PM PDT 24
Peak memory 208708 kb
Host smart-4cbaa83e-5c51-41c2-9cdc-a8b2de96f728
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332495771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2332495771
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2375667927
Short name T590
Test name
Test status
Simulation time 136512268 ps
CPU time 2.48 seconds
Started Apr 02 01:41:55 PM PDT 24
Finished Apr 02 01:41:58 PM PDT 24
Peak memory 210052 kb
Host smart-20054f18-bb4d-416a-8f03-61143e576ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375667927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2375667927
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.422236357
Short name T510
Test name
Test status
Simulation time 1658043345 ps
CPU time 19.36 seconds
Started Apr 02 01:41:48 PM PDT 24
Finished Apr 02 01:42:07 PM PDT 24
Peak memory 208264 kb
Host smart-a69205a1-1c03-4b73-a19b-fc06218e4c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422236357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.422236357
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3997330046
Short name T294
Test name
Test status
Simulation time 11870395343 ps
CPU time 85.87 seconds
Started Apr 02 01:41:56 PM PDT 24
Finished Apr 02 01:43:22 PM PDT 24
Peak memory 218140 kb
Host smart-194d910f-42c5-4662-a1c2-0d522fb4e718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997330046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3997330046
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2690298211
Short name T133
Test name
Test status
Simulation time 105663464 ps
CPU time 3.1 seconds
Started Apr 02 01:41:56 PM PDT 24
Finished Apr 02 01:41:59 PM PDT 24
Peak memory 210284 kb
Host smart-d76b9152-23fb-402b-86b1-b9e05e910f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690298211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2690298211
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1640928008
Short name T563
Test name
Test status
Simulation time 12851860 ps
CPU time 0.94 seconds
Started Apr 02 01:44:51 PM PDT 24
Finished Apr 02 01:44:52 PM PDT 24
Peak memory 206280 kb
Host smart-65676881-a9e6-4ba8-ab5e-e2dae663acd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640928008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1640928008
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2209143617
Short name T425
Test name
Test status
Simulation time 122727362 ps
CPU time 7.19 seconds
Started Apr 02 01:44:44 PM PDT 24
Finished Apr 02 01:44:51 PM PDT 24
Peak memory 215896 kb
Host smart-c60f0371-1ac2-416c-82bd-2e79c654b00a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209143617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2209143617
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1975096782
Short name T605
Test name
Test status
Simulation time 429528083 ps
CPU time 9.75 seconds
Started Apr 02 01:44:47 PM PDT 24
Finished Apr 02 01:44:57 PM PDT 24
Peak memory 223112 kb
Host smart-953f6cc5-2a00-4b80-a751-9623580af443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975096782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1975096782
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2512380763
Short name T574
Test name
Test status
Simulation time 136084582 ps
CPU time 2.23 seconds
Started Apr 02 01:44:43 PM PDT 24
Finished Apr 02 01:44:45 PM PDT 24
Peak memory 218452 kb
Host smart-02d6db22-1c3a-43ae-854a-3c1e50d43a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512380763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2512380763
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3332258378
Short name T321
Test name
Test status
Simulation time 1745323099 ps
CPU time 6.86 seconds
Started Apr 02 01:44:48 PM PDT 24
Finished Apr 02 01:44:55 PM PDT 24
Peak memory 214616 kb
Host smart-f6d51f48-d23c-46dd-8346-03bbb0676d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332258378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3332258378
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.650638127
Short name T862
Test name
Test status
Simulation time 227445272 ps
CPU time 8.78 seconds
Started Apr 02 01:44:47 PM PDT 24
Finished Apr 02 01:44:57 PM PDT 24
Peak memory 214580 kb
Host smart-7e7767d2-a99b-46b0-a839-31ddf2b2e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650638127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.650638127
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.202319764
Short name T759
Test name
Test status
Simulation time 165122147 ps
CPU time 2.54 seconds
Started Apr 02 01:44:44 PM PDT 24
Finished Apr 02 01:44:46 PM PDT 24
Peak memory 220408 kb
Host smart-e65d2a47-463a-4d9b-9d6a-86ac849d686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202319764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.202319764
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2248397239
Short name T688
Test name
Test status
Simulation time 260882744 ps
CPU time 6.85 seconds
Started Apr 02 01:44:46 PM PDT 24
Finished Apr 02 01:44:53 PM PDT 24
Peak memory 209960 kb
Host smart-d019fcb0-0d85-45e9-9013-5478de2ce30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248397239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2248397239
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2038497592
Short name T557
Test name
Test status
Simulation time 911786168 ps
CPU time 2.51 seconds
Started Apr 02 01:44:44 PM PDT 24
Finished Apr 02 01:44:47 PM PDT 24
Peak memory 207040 kb
Host smart-9de9b8e6-52ab-4b45-86b8-6d2bda1766d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038497592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2038497592
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1264178451
Short name T85
Test name
Test status
Simulation time 196450581 ps
CPU time 2.61 seconds
Started Apr 02 01:44:44 PM PDT 24
Finished Apr 02 01:44:47 PM PDT 24
Peak memory 207032 kb
Host smart-073b4690-70da-42f2-936f-91c70e5ba65b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264178451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1264178451
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3350252577
Short name T293
Test name
Test status
Simulation time 42384337 ps
CPU time 2.59 seconds
Started Apr 02 01:44:45 PM PDT 24
Finished Apr 02 01:44:47 PM PDT 24
Peak memory 208836 kb
Host smart-0af1c342-d227-4083-8983-cf7209c8cf5a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350252577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3350252577
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2309572960
Short name T287
Test name
Test status
Simulation time 660503303 ps
CPU time 23.52 seconds
Started Apr 02 01:44:45 PM PDT 24
Finished Apr 02 01:45:09 PM PDT 24
Peak memory 209340 kb
Host smart-c1db651a-7839-49be-b22b-6785abecdd55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309572960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2309572960
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1825755568
Short name T416
Test name
Test status
Simulation time 386227614 ps
CPU time 2.13 seconds
Started Apr 02 01:44:54 PM PDT 24
Finished Apr 02 01:44:56 PM PDT 24
Peak memory 216104 kb
Host smart-2a174e4e-6d25-40a4-893d-5927704245d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825755568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1825755568
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3557041796
Short name T468
Test name
Test status
Simulation time 83217714 ps
CPU time 1.81 seconds
Started Apr 02 01:44:43 PM PDT 24
Finished Apr 02 01:44:45 PM PDT 24
Peak memory 207020 kb
Host smart-c514aea2-2e1c-44b6-a0da-78e6871f82fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557041796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3557041796
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.902728823
Short name T624
Test name
Test status
Simulation time 169393994 ps
CPU time 5.84 seconds
Started Apr 02 01:44:48 PM PDT 24
Finished Apr 02 01:44:54 PM PDT 24
Peak memory 210252 kb
Host smart-8663e740-3fc5-4981-9afb-8e9a55146d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902728823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.902728823
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3839340557
Short name T558
Test name
Test status
Simulation time 639801300 ps
CPU time 6.29 seconds
Started Apr 02 01:44:47 PM PDT 24
Finished Apr 02 01:44:54 PM PDT 24
Peak memory 211296 kb
Host smart-7adfca2c-992a-4a97-bd05-cc749bff7310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839340557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3839340557
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1023638555
Short name T103
Test name
Test status
Simulation time 11236120 ps
CPU time 0.76 seconds
Started Apr 02 01:45:02 PM PDT 24
Finished Apr 02 01:45:04 PM PDT 24
Peak memory 206292 kb
Host smart-07df4000-c47a-4370-8b90-e2f40873072d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023638555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1023638555
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1939338128
Short name T587
Test name
Test status
Simulation time 114214607 ps
CPU time 2.06 seconds
Started Apr 02 01:44:58 PM PDT 24
Finished Apr 02 01:45:00 PM PDT 24
Peak memory 214928 kb
Host smart-c369f114-a4f9-4214-a92e-f3f6a188a897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939338128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1939338128
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3164947171
Short name T532
Test name
Test status
Simulation time 117880053 ps
CPU time 3.04 seconds
Started Apr 02 01:44:55 PM PDT 24
Finished Apr 02 01:44:58 PM PDT 24
Peak memory 208944 kb
Host smart-02c13570-377e-422b-8e61-e6abef95828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164947171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3164947171
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3429164207
Short name T413
Test name
Test status
Simulation time 765315792 ps
CPU time 21.81 seconds
Started Apr 02 01:44:54 PM PDT 24
Finished Apr 02 01:45:16 PM PDT 24
Peak memory 214440 kb
Host smart-5b38544f-10ba-43d8-9900-038a6315cfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429164207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3429164207
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1753081848
Short name T253
Test name
Test status
Simulation time 50276570 ps
CPU time 3.34 seconds
Started Apr 02 01:44:55 PM PDT 24
Finished Apr 02 01:44:59 PM PDT 24
Peak memory 220264 kb
Host smart-8e60ea7c-e06c-4cdb-a92e-61148bcbbc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753081848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1753081848
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2148612379
Short name T857
Test name
Test status
Simulation time 1308593730 ps
CPU time 5.1 seconds
Started Apr 02 01:44:52 PM PDT 24
Finished Apr 02 01:44:58 PM PDT 24
Peak memory 207556 kb
Host smart-961229ac-08ac-4aae-9381-c4dd16740aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148612379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2148612379
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3927447409
Short name T685
Test name
Test status
Simulation time 289417173 ps
CPU time 3.62 seconds
Started Apr 02 01:44:51 PM PDT 24
Finished Apr 02 01:44:55 PM PDT 24
Peak memory 208784 kb
Host smart-51e431fb-59fb-407c-b47d-bf2ce52b34dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927447409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3927447409
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2785790662
Short name T190
Test name
Test status
Simulation time 131753031 ps
CPU time 4.09 seconds
Started Apr 02 01:44:52 PM PDT 24
Finished Apr 02 01:44:56 PM PDT 24
Peak memory 208860 kb
Host smart-8f671c9f-3540-458c-86ea-f752d3545b94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785790662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2785790662
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.188752576
Short name T834
Test name
Test status
Simulation time 69181764 ps
CPU time 2.36 seconds
Started Apr 02 01:44:56 PM PDT 24
Finished Apr 02 01:44:59 PM PDT 24
Peak memory 207196 kb
Host smart-51178c70-6214-4811-87cc-90099675f305
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188752576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.188752576
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.4026050631
Short name T885
Test name
Test status
Simulation time 3302740255 ps
CPU time 22.28 seconds
Started Apr 02 01:44:52 PM PDT 24
Finished Apr 02 01:45:14 PM PDT 24
Peak memory 209152 kb
Host smart-46b3bf87-5aa8-4eed-aedc-999297184340
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026050631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.4026050631
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4160084927
Short name T645
Test name
Test status
Simulation time 62410231 ps
CPU time 2.88 seconds
Started Apr 02 01:45:00 PM PDT 24
Finished Apr 02 01:45:03 PM PDT 24
Peak memory 210028 kb
Host smart-79e21bcd-cccb-4cb8-b800-57dc76ec2c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160084927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4160084927
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3689332792
Short name T565
Test name
Test status
Simulation time 169925801 ps
CPU time 4.39 seconds
Started Apr 02 01:44:50 PM PDT 24
Finished Apr 02 01:44:54 PM PDT 24
Peak memory 208232 kb
Host smart-96b9ba03-e7d6-4f0d-8c60-398501dceafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689332792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3689332792
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.42023399
Short name T806
Test name
Test status
Simulation time 267948753 ps
CPU time 5.52 seconds
Started Apr 02 01:44:55 PM PDT 24
Finished Apr 02 01:45:01 PM PDT 24
Peak memory 209944 kb
Host smart-8c1709f0-d007-4068-9234-faa86bd0321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42023399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.42023399
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2594100157
Short name T403
Test name
Test status
Simulation time 74229294 ps
CPU time 2.66 seconds
Started Apr 02 01:45:02 PM PDT 24
Finished Apr 02 01:45:04 PM PDT 24
Peak memory 210484 kb
Host smart-898b9874-5419-419a-a9a1-a200199d738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594100157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2594100157
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1692974622
Short name T567
Test name
Test status
Simulation time 30592036 ps
CPU time 0.82 seconds
Started Apr 02 01:45:08 PM PDT 24
Finished Apr 02 01:45:09 PM PDT 24
Peak memory 206176 kb
Host smart-39da5882-fec7-4cfc-a759-a22525869222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692974622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1692974622
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1366301500
Short name T384
Test name
Test status
Simulation time 68138393 ps
CPU time 4.56 seconds
Started Apr 02 01:45:07 PM PDT 24
Finished Apr 02 01:45:12 PM PDT 24
Peak memory 215344 kb
Host smart-76db5147-9980-4483-ac70-931c9a9c4b51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1366301500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1366301500
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.723735993
Short name T429
Test name
Test status
Simulation time 654561270 ps
CPU time 6.88 seconds
Started Apr 02 01:45:02 PM PDT 24
Finished Apr 02 01:45:10 PM PDT 24
Peak memory 214720 kb
Host smart-f1b3eac2-17f2-4594-8687-13f1f7d52990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723735993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.723735993
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3688002278
Short name T370
Test name
Test status
Simulation time 69434290 ps
CPU time 2.65 seconds
Started Apr 02 01:45:04 PM PDT 24
Finished Apr 02 01:45:07 PM PDT 24
Peak memory 214668 kb
Host smart-7534d09b-5f73-453b-a544-53c0119892a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688002278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3688002278
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2370640589
Short name T66
Test name
Test status
Simulation time 103431206 ps
CPU time 5.21 seconds
Started Apr 02 01:45:03 PM PDT 24
Finished Apr 02 01:45:09 PM PDT 24
Peak memory 222724 kb
Host smart-889153b9-d1e3-4fb4-87e1-05261ebd2be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370640589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2370640589
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1861944661
Short name T541
Test name
Test status
Simulation time 217266413 ps
CPU time 3.44 seconds
Started Apr 02 01:45:01 PM PDT 24
Finished Apr 02 01:45:05 PM PDT 24
Peak memory 208620 kb
Host smart-a2a9efb6-81bb-4e70-a20f-925b13b45d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861944661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1861944661
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3332330686
Short name T782
Test name
Test status
Simulation time 19521541 ps
CPU time 1.82 seconds
Started Apr 02 01:44:57 PM PDT 24
Finished Apr 02 01:44:59 PM PDT 24
Peak memory 207148 kb
Host smart-44bac85d-03c9-4a0f-bf90-ee8ce661933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332330686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3332330686
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2075098209
Short name T644
Test name
Test status
Simulation time 1493716555 ps
CPU time 49.42 seconds
Started Apr 02 01:44:58 PM PDT 24
Finished Apr 02 01:45:48 PM PDT 24
Peak memory 208872 kb
Host smart-31b40a08-0cfe-487f-9f87-2c97c1608c4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075098209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2075098209
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2286631354
Short name T777
Test name
Test status
Simulation time 88376709 ps
CPU time 3.26 seconds
Started Apr 02 01:44:58 PM PDT 24
Finished Apr 02 01:45:02 PM PDT 24
Peak memory 207072 kb
Host smart-8f07f4b9-3dc3-497c-b2e0-9b4909b6f9c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286631354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2286631354
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2328307351
Short name T108
Test name
Test status
Simulation time 27296640 ps
CPU time 2.23 seconds
Started Apr 02 01:45:00 PM PDT 24
Finished Apr 02 01:45:02 PM PDT 24
Peak memory 208708 kb
Host smart-a72a2297-ca5c-4298-9e5c-ec5a5323ec8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328307351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2328307351
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.884897672
Short name T307
Test name
Test status
Simulation time 128763251 ps
CPU time 2.56 seconds
Started Apr 02 01:45:05 PM PDT 24
Finished Apr 02 01:45:08 PM PDT 24
Peak memory 209496 kb
Host smart-afc4dd60-fb5d-4603-b054-ddcbbe7e39e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884897672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.884897672
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.134489457
Short name T627
Test name
Test status
Simulation time 147033200 ps
CPU time 2.32 seconds
Started Apr 02 01:45:02 PM PDT 24
Finished Apr 02 01:45:05 PM PDT 24
Peak memory 206852 kb
Host smart-d52ec8ac-7629-4eb3-9302-d627eb068be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134489457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.134489457
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3917541522
Short name T73
Test name
Test status
Simulation time 5583358453 ps
CPU time 52.39 seconds
Started Apr 02 01:45:07 PM PDT 24
Finished Apr 02 01:45:59 PM PDT 24
Peak memory 221908 kb
Host smart-ce7b891c-6ea5-4ede-b145-cacf5b7417ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917541522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3917541522
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3811497168
Short name T790
Test name
Test status
Simulation time 121147646 ps
CPU time 5.7 seconds
Started Apr 02 01:45:01 PM PDT 24
Finished Apr 02 01:45:07 PM PDT 24
Peak memory 214636 kb
Host smart-e3ece621-436c-4d92-b81c-e98f0a37745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811497168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3811497168
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3665935427
Short name T772
Test name
Test status
Simulation time 118931806 ps
CPU time 2.26 seconds
Started Apr 02 01:45:06 PM PDT 24
Finished Apr 02 01:45:08 PM PDT 24
Peak memory 211140 kb
Host smart-d23a384e-a1a7-4ed5-9f56-5e50290af6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665935427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3665935427
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1249366366
Short name T705
Test name
Test status
Simulation time 34310400 ps
CPU time 0.71 seconds
Started Apr 02 01:45:13 PM PDT 24
Finished Apr 02 01:45:13 PM PDT 24
Peak memory 206224 kb
Host smart-78aa5941-2643-4839-aede-a76053bf47a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249366366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1249366366
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2987322528
Short name T143
Test name
Test status
Simulation time 484125646 ps
CPU time 3.43 seconds
Started Apr 02 01:45:12 PM PDT 24
Finished Apr 02 01:45:16 PM PDT 24
Peak memory 214660 kb
Host smart-7e16ffd0-4b1e-401a-8dd3-d54fb3b12b63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2987322528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2987322528
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.870984907
Short name T17
Test name
Test status
Simulation time 687586685 ps
CPU time 4.37 seconds
Started Apr 02 01:45:14 PM PDT 24
Finished Apr 02 01:45:18 PM PDT 24
Peak memory 210472 kb
Host smart-63e9bc45-ba45-4543-b09b-dfd22fc361d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870984907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.870984907
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3699867062
Short name T347
Test name
Test status
Simulation time 82627677 ps
CPU time 3.61 seconds
Started Apr 02 01:45:09 PM PDT 24
Finished Apr 02 01:45:13 PM PDT 24
Peak memory 208620 kb
Host smart-5712224d-b08d-47f3-873f-b7f293be2725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699867062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3699867062
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1389985495
Short name T805
Test name
Test status
Simulation time 7606758703 ps
CPU time 35.62 seconds
Started Apr 02 01:45:14 PM PDT 24
Finished Apr 02 01:45:50 PM PDT 24
Peak memory 220932 kb
Host smart-b58fb8a1-0448-4638-b464-d53d7ff96368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389985495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1389985495
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1214070240
Short name T767
Test name
Test status
Simulation time 53778443 ps
CPU time 1.6 seconds
Started Apr 02 01:45:09 PM PDT 24
Finished Apr 02 01:45:10 PM PDT 24
Peak memory 209412 kb
Host smart-47923d45-090a-416a-ba7e-05a419079e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214070240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1214070240
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1260007875
Short name T465
Test name
Test status
Simulation time 130815971 ps
CPU time 4.55 seconds
Started Apr 02 01:45:11 PM PDT 24
Finished Apr 02 01:45:15 PM PDT 24
Peak memory 207456 kb
Host smart-5ea06c53-77b8-446a-acd7-aa39d14b4c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260007875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1260007875
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1117908893
Short name T698
Test name
Test status
Simulation time 678785650 ps
CPU time 5.32 seconds
Started Apr 02 01:45:05 PM PDT 24
Finished Apr 02 01:45:11 PM PDT 24
Peak memory 208124 kb
Host smart-8499ca87-c9da-4b4d-84ab-897c5f950d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117908893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1117908893
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.789359587
Short name T697
Test name
Test status
Simulation time 29148420 ps
CPU time 2.29 seconds
Started Apr 02 01:45:09 PM PDT 24
Finished Apr 02 01:45:11 PM PDT 24
Peak memory 207064 kb
Host smart-29a8fde9-88cc-40f3-bfd8-644a3e59181d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789359587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.789359587
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3070582138
Short name T776
Test name
Test status
Simulation time 138369299 ps
CPU time 4.31 seconds
Started Apr 02 01:45:06 PM PDT 24
Finished Apr 02 01:45:10 PM PDT 24
Peak memory 207224 kb
Host smart-1598bd7b-38d9-4aa8-ba09-74ce29c6079e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070582138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3070582138
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1778479173
Short name T850
Test name
Test status
Simulation time 77130406 ps
CPU time 3.21 seconds
Started Apr 02 01:45:10 PM PDT 24
Finished Apr 02 01:45:14 PM PDT 24
Peak memory 207212 kb
Host smart-02a559fb-127a-40b5-95ce-234206a84128
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778479173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1778479173
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1717477379
Short name T699
Test name
Test status
Simulation time 47396602 ps
CPU time 2.35 seconds
Started Apr 02 01:45:13 PM PDT 24
Finished Apr 02 01:45:15 PM PDT 24
Peak memory 209916 kb
Host smart-a32268f7-9733-486a-b16d-0e1768bf820c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717477379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1717477379
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1120679503
Short name T888
Test name
Test status
Simulation time 204467812 ps
CPU time 6.84 seconds
Started Apr 02 01:45:05 PM PDT 24
Finished Apr 02 01:45:12 PM PDT 24
Peak memory 206956 kb
Host smart-705eb3a7-bbe5-492b-b8a3-5aeff6f036de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120679503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1120679503
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1365652621
Short name T598
Test name
Test status
Simulation time 214691688 ps
CPU time 2.79 seconds
Started Apr 02 01:45:11 PM PDT 24
Finished Apr 02 01:45:14 PM PDT 24
Peak memory 218564 kb
Host smart-f55b4e28-3b5e-402e-99a7-c5a5d2a5ab58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365652621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1365652621
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1333072617
Short name T164
Test name
Test status
Simulation time 354910705 ps
CPU time 2.49 seconds
Started Apr 02 01:45:18 PM PDT 24
Finished Apr 02 01:45:20 PM PDT 24
Peak memory 210084 kb
Host smart-a58ec29e-699d-4be6-9f71-62aa1fbfb1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333072617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1333072617
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.739325572
Short name T507
Test name
Test status
Simulation time 12263723 ps
CPU time 0.74 seconds
Started Apr 02 01:45:20 PM PDT 24
Finished Apr 02 01:45:21 PM PDT 24
Peak memory 206260 kb
Host smart-f75c12d8-79ee-45d4-a007-6f1abc488036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739325572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.739325572
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1956643466
Short name T394
Test name
Test status
Simulation time 550701581 ps
CPU time 7.39 seconds
Started Apr 02 01:45:21 PM PDT 24
Finished Apr 02 01:45:29 PM PDT 24
Peak memory 214664 kb
Host smart-4e3af721-e1a8-4b8d-8ba2-636e0f32bbf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956643466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1956643466
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2072156048
Short name T205
Test name
Test status
Simulation time 372525419 ps
CPU time 6.92 seconds
Started Apr 02 01:45:18 PM PDT 24
Finished Apr 02 01:45:25 PM PDT 24
Peak memory 209680 kb
Host smart-5e5ce420-b817-4cf6-abe3-db6683367640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072156048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2072156048
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3364984024
Short name T787
Test name
Test status
Simulation time 161960199 ps
CPU time 6.29 seconds
Started Apr 02 01:45:18 PM PDT 24
Finished Apr 02 01:45:24 PM PDT 24
Peak memory 219820 kb
Host smart-0b55d601-969d-4f1f-b75f-0e111048112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364984024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3364984024
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2203180249
Short name T281
Test name
Test status
Simulation time 401675869 ps
CPU time 4.2 seconds
Started Apr 02 01:45:15 PM PDT 24
Finished Apr 02 01:45:19 PM PDT 24
Peak memory 211532 kb
Host smart-f6f6b81f-92a4-48c1-ac29-8783cde6b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203180249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2203180249
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3998402243
Short name T803
Test name
Test status
Simulation time 224798716 ps
CPU time 3.31 seconds
Started Apr 02 01:45:19 PM PDT 24
Finished Apr 02 01:45:23 PM PDT 24
Peak memory 214648 kb
Host smart-c0531580-fcb6-47bb-b637-3a02db31591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998402243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3998402243
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.828018890
Short name T682
Test name
Test status
Simulation time 431840197 ps
CPU time 5.1 seconds
Started Apr 02 01:45:18 PM PDT 24
Finished Apr 02 01:45:23 PM PDT 24
Peak memory 208864 kb
Host smart-e204418b-d747-4b6f-983b-806ccb2f5d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828018890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.828018890
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.59634034
Short name T231
Test name
Test status
Simulation time 91650199 ps
CPU time 2.43 seconds
Started Apr 02 01:45:13 PM PDT 24
Finished Apr 02 01:45:16 PM PDT 24
Peak memory 207896 kb
Host smart-c0b38ec6-e5a9-4154-aaf7-dca2071a7f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59634034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.59634034
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3679511413
Short name T717
Test name
Test status
Simulation time 1971499844 ps
CPU time 66.85 seconds
Started Apr 02 01:45:17 PM PDT 24
Finished Apr 02 01:46:24 PM PDT 24
Peak memory 208408 kb
Host smart-899e8425-08e2-4048-8322-618e6bdd7f96
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679511413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3679511413
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3969863021
Short name T496
Test name
Test status
Simulation time 104231521 ps
CPU time 4.29 seconds
Started Apr 02 01:45:21 PM PDT 24
Finished Apr 02 01:45:25 PM PDT 24
Peak memory 208940 kb
Host smart-119bcae1-506d-4d8a-b44c-0f9ab925ee56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969863021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3969863021
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.163096798
Short name T545
Test name
Test status
Simulation time 1658285358 ps
CPU time 47.96 seconds
Started Apr 02 01:45:16 PM PDT 24
Finished Apr 02 01:46:05 PM PDT 24
Peak memory 209208 kb
Host smart-668a5fce-31e8-4327-a299-25b9ade12c26
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163096798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.163096798
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.614163138
Short name T247
Test name
Test status
Simulation time 246317840 ps
CPU time 1.98 seconds
Started Apr 02 01:45:22 PM PDT 24
Finished Apr 02 01:45:24 PM PDT 24
Peak memory 216032 kb
Host smart-85a7f047-18d9-40a3-a058-15d45c0cfcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614163138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.614163138
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2969210098
Short name T856
Test name
Test status
Simulation time 94680194 ps
CPU time 1.69 seconds
Started Apr 02 01:45:13 PM PDT 24
Finished Apr 02 01:45:15 PM PDT 24
Peak memory 207048 kb
Host smart-6a30af0f-03e9-4755-ac79-40083d777b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969210098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2969210098
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2988458862
Short name T47
Test name
Test status
Simulation time 1555050472 ps
CPU time 19.71 seconds
Started Apr 02 01:45:20 PM PDT 24
Finished Apr 02 01:45:40 PM PDT 24
Peak memory 214636 kb
Host smart-e14d9e49-70cd-4663-866f-78d52e08d6f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988458862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2988458862
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.428687676
Short name T650
Test name
Test status
Simulation time 197385996 ps
CPU time 6.65 seconds
Started Apr 02 01:45:24 PM PDT 24
Finished Apr 02 01:45:31 PM PDT 24
Peak memory 208176 kb
Host smart-ae3a3695-404a-4d3f-8a13-50bec871b904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428687676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.428687676
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1559776896
Short name T123
Test name
Test status
Simulation time 25242760 ps
CPU time 1.71 seconds
Started Apr 02 01:45:20 PM PDT 24
Finished Apr 02 01:45:22 PM PDT 24
Peak memory 210120 kb
Host smart-e47da23e-6992-4fc8-999c-5d9466196ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559776896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1559776896
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.4172447082
Short name T735
Test name
Test status
Simulation time 14559521 ps
CPU time 0.79 seconds
Started Apr 02 01:45:28 PM PDT 24
Finished Apr 02 01:45:29 PM PDT 24
Peak memory 206152 kb
Host smart-076470d0-4829-4a29-83ae-47f246bb6c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172447082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.4172447082
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.325927324
Short name T74
Test name
Test status
Simulation time 208110459 ps
CPU time 3.02 seconds
Started Apr 02 01:45:24 PM PDT 24
Finished Apr 02 01:45:27 PM PDT 24
Peak memory 209408 kb
Host smart-e46d8564-2121-4943-895b-5bef98daa420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325927324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.325927324
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1798141624
Short name T99
Test name
Test status
Simulation time 748666225 ps
CPU time 6.14 seconds
Started Apr 02 01:45:30 PM PDT 24
Finished Apr 02 01:45:36 PM PDT 24
Peak memory 214652 kb
Host smart-fea02fcd-8af8-448b-989f-f3b9d8307c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798141624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1798141624
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2559804026
Short name T39
Test name
Test status
Simulation time 479421963 ps
CPU time 3.18 seconds
Started Apr 02 01:45:27 PM PDT 24
Finished Apr 02 01:45:31 PM PDT 24
Peak memory 208912 kb
Host smart-b0d22540-dc33-4b42-852a-18239816f9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559804026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2559804026
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3818629013
Short name T380
Test name
Test status
Simulation time 80707882 ps
CPU time 3.89 seconds
Started Apr 02 01:45:24 PM PDT 24
Finished Apr 02 01:45:28 PM PDT 24
Peak memory 218488 kb
Host smart-ebd412e8-8f25-46c2-a6f7-94306f78f7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818629013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3818629013
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3744568239
Short name T779
Test name
Test status
Simulation time 148466273 ps
CPU time 2.28 seconds
Started Apr 02 01:45:25 PM PDT 24
Finished Apr 02 01:45:28 PM PDT 24
Peak memory 207024 kb
Host smart-45ec3504-588e-4237-890e-8c47a61fa403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744568239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3744568239
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3143534794
Short name T678
Test name
Test status
Simulation time 512387621 ps
CPU time 2.6 seconds
Started Apr 02 01:45:25 PM PDT 24
Finished Apr 02 01:45:28 PM PDT 24
Peak memory 207820 kb
Host smart-6c36c42a-ddc1-410b-93aa-79c5eff0e95e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143534794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3143534794
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.403801756
Short name T686
Test name
Test status
Simulation time 7721293913 ps
CPU time 60.28 seconds
Started Apr 02 01:45:25 PM PDT 24
Finished Apr 02 01:46:25 PM PDT 24
Peak memory 208872 kb
Host smart-5cfeaca5-9532-4dd3-a14b-fd2676fab06d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403801756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.403801756
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3231521517
Short name T618
Test name
Test status
Simulation time 468758992 ps
CPU time 6.87 seconds
Started Apr 02 01:45:23 PM PDT 24
Finished Apr 02 01:45:30 PM PDT 24
Peak memory 208720 kb
Host smart-f3713a61-2314-4d2d-83f9-1de6b0938c93
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231521517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3231521517
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2710305852
Short name T881
Test name
Test status
Simulation time 298617307 ps
CPU time 2.23 seconds
Started Apr 02 01:45:27 PM PDT 24
Finished Apr 02 01:45:30 PM PDT 24
Peak memory 208124 kb
Host smart-98024996-12d7-46c4-b098-26ae40cce5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710305852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2710305852
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2661308050
Short name T788
Test name
Test status
Simulation time 567688704 ps
CPU time 4.7 seconds
Started Apr 02 01:45:24 PM PDT 24
Finished Apr 02 01:45:29 PM PDT 24
Peak memory 208848 kb
Host smart-9b2a975d-0573-4c01-a141-68a6f6a7bace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661308050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2661308050
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2073977842
Short name T192
Test name
Test status
Simulation time 675400252 ps
CPU time 12.46 seconds
Started Apr 02 01:45:30 PM PDT 24
Finished Apr 02 01:45:43 PM PDT 24
Peak memory 216220 kb
Host smart-42031569-d27f-45db-b6e5-1a601f42c03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073977842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2073977842
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2150308385
Short name T124
Test name
Test status
Simulation time 439192866 ps
CPU time 8.14 seconds
Started Apr 02 01:45:29 PM PDT 24
Finished Apr 02 01:45:37 PM PDT 24
Peak memory 220336 kb
Host smart-ad39326c-f754-4180-a5af-ffc3bdaf89f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150308385 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2150308385
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1073312455
Short name T530
Test name
Test status
Simulation time 188999098 ps
CPU time 7.65 seconds
Started Apr 02 01:45:29 PM PDT 24
Finished Apr 02 01:45:37 PM PDT 24
Peak memory 209788 kb
Host smart-6e980137-64ad-4ab2-85b7-3b506f0e04ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073312455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1073312455
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2003481290
Short name T168
Test name
Test status
Simulation time 309043980 ps
CPU time 5.14 seconds
Started Apr 02 01:45:30 PM PDT 24
Finished Apr 02 01:45:35 PM PDT 24
Peak memory 210812 kb
Host smart-5211e6a0-7fa0-4fbc-a48b-4ac301c8a118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003481290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2003481290
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3876171224
Short name T546
Test name
Test status
Simulation time 129200271 ps
CPU time 0.94 seconds
Started Apr 02 01:45:38 PM PDT 24
Finished Apr 02 01:45:39 PM PDT 24
Peak memory 206368 kb
Host smart-fa1b84ce-2003-4a9c-8bbb-c89d31b8b45f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876171224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3876171224
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2941191165
Short name T422
Test name
Test status
Simulation time 207657430 ps
CPU time 4.65 seconds
Started Apr 02 01:45:32 PM PDT 24
Finished Apr 02 01:45:37 PM PDT 24
Peak memory 215768 kb
Host smart-ea7e8aca-3c41-4bd3-867e-4809a85cb858
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2941191165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2941191165
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.482531121
Short name T419
Test name
Test status
Simulation time 141687465 ps
CPU time 1.87 seconds
Started Apr 02 01:45:33 PM PDT 24
Finished Apr 02 01:45:34 PM PDT 24
Peak memory 209028 kb
Host smart-8b46979e-bca1-49ec-8ecf-81f938038434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482531121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.482531121
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3051070563
Short name T595
Test name
Test status
Simulation time 1364384148 ps
CPU time 7.77 seconds
Started Apr 02 01:45:35 PM PDT 24
Finished Apr 02 01:45:43 PM PDT 24
Peak memory 222792 kb
Host smart-f9a388fe-a8e2-4008-81d9-94209cf28353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051070563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3051070563
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3857556964
Short name T300
Test name
Test status
Simulation time 752138807 ps
CPU time 8.8 seconds
Started Apr 02 01:45:37 PM PDT 24
Finished Apr 02 01:45:46 PM PDT 24
Peak memory 222864 kb
Host smart-56431e87-0c9d-4808-9f54-8ef04849fe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857556964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3857556964
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3773629379
Short name T254
Test name
Test status
Simulation time 43445297 ps
CPU time 2.39 seconds
Started Apr 02 01:45:34 PM PDT 24
Finished Apr 02 01:45:36 PM PDT 24
Peak memory 209164 kb
Host smart-5c95e634-8ef5-4381-b918-b4db2d8fbe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773629379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3773629379
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.366441747
Short name T823
Test name
Test status
Simulation time 51287648 ps
CPU time 3.28 seconds
Started Apr 02 01:45:31 PM PDT 24
Finished Apr 02 01:45:35 PM PDT 24
Peak memory 207508 kb
Host smart-a5a370e1-84b4-4cf4-8dd8-3079b4fe4c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366441747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.366441747
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2545879762
Short name T623
Test name
Test status
Simulation time 2936064262 ps
CPU time 38.52 seconds
Started Apr 02 01:45:32 PM PDT 24
Finished Apr 02 01:46:10 PM PDT 24
Peak memory 208936 kb
Host smart-a02b4648-49f9-4432-9b60-6005cf23f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545879762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2545879762
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.603587988
Short name T83
Test name
Test status
Simulation time 186583019 ps
CPU time 7.1 seconds
Started Apr 02 01:45:32 PM PDT 24
Finished Apr 02 01:45:39 PM PDT 24
Peak memory 208184 kb
Host smart-77bfd373-82d8-4fcf-982a-5e8b951e07ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603587988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.603587988
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1952199893
Short name T841
Test name
Test status
Simulation time 76782672 ps
CPU time 2.79 seconds
Started Apr 02 01:45:31 PM PDT 24
Finished Apr 02 01:45:34 PM PDT 24
Peak memory 207208 kb
Host smart-da900f12-2832-45cf-888a-4b3824496f1b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952199893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1952199893
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.4034138596
Short name T883
Test name
Test status
Simulation time 117850707 ps
CPU time 3.09 seconds
Started Apr 02 01:45:31 PM PDT 24
Finished Apr 02 01:45:35 PM PDT 24
Peak memory 209020 kb
Host smart-f215904a-b1b5-41c7-a168-d90f6e16ddb4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034138596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4034138596
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2567696566
Short name T248
Test name
Test status
Simulation time 46512169 ps
CPU time 2.4 seconds
Started Apr 02 01:45:38 PM PDT 24
Finished Apr 02 01:45:40 PM PDT 24
Peak memory 216088 kb
Host smart-dd89f7c0-c085-4713-b8d9-d19d11fd4ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567696566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2567696566
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2637968717
Short name T536
Test name
Test status
Simulation time 168195309 ps
CPU time 2.24 seconds
Started Apr 02 01:45:26 PM PDT 24
Finished Apr 02 01:45:29 PM PDT 24
Peak memory 207008 kb
Host smart-6dde1e57-9a84-4dbe-ac77-0051dcb468d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637968717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2637968717
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1775096484
Short name T127
Test name
Test status
Simulation time 539429029 ps
CPU time 22.7 seconds
Started Apr 02 01:45:35 PM PDT 24
Finished Apr 02 01:45:58 PM PDT 24
Peak memory 222992 kb
Host smart-255d01d5-0aea-4ec4-aafb-b98aec950d93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775096484 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1775096484
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.316273700
Short name T729
Test name
Test status
Simulation time 459512289 ps
CPU time 3.87 seconds
Started Apr 02 01:45:36 PM PDT 24
Finished Apr 02 01:45:41 PM PDT 24
Peak memory 210228 kb
Host smart-20f48abd-bd59-4067-992b-7c5df821417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316273700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.316273700
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2617427879
Short name T586
Test name
Test status
Simulation time 51232680 ps
CPU time 1.99 seconds
Started Apr 02 01:45:38 PM PDT 24
Finished Apr 02 01:45:40 PM PDT 24
Peak memory 210016 kb
Host smart-c479929b-15ac-4182-8e57-d048a218aef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617427879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2617427879
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2155795302
Short name T614
Test name
Test status
Simulation time 41061049 ps
CPU time 0.76 seconds
Started Apr 02 01:45:47 PM PDT 24
Finished Apr 02 01:45:48 PM PDT 24
Peak memory 206336 kb
Host smart-06d1ac6d-6959-44bd-8803-79c7f2ab4956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155795302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2155795302
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2213184059
Short name T28
Test name
Test status
Simulation time 111995914 ps
CPU time 3.57 seconds
Started Apr 02 01:45:44 PM PDT 24
Finished Apr 02 01:45:48 PM PDT 24
Peak memory 221992 kb
Host smart-d0e554e6-78a0-4f1e-afd7-4d08b0f1260f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213184059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2213184059
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1535969400
Short name T42
Test name
Test status
Simulation time 135678516 ps
CPU time 2.55 seconds
Started Apr 02 01:45:43 PM PDT 24
Finished Apr 02 01:45:46 PM PDT 24
Peak memory 214696 kb
Host smart-2971b4da-1153-426f-87ee-0438a12ff792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535969400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1535969400
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4174797756
Short name T343
Test name
Test status
Simulation time 465543151 ps
CPU time 6.13 seconds
Started Apr 02 01:45:43 PM PDT 24
Finished Apr 02 01:45:49 PM PDT 24
Peak memory 219848 kb
Host smart-0440778b-cf4f-406f-88a9-dede82aafad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174797756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4174797756
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.794555207
Short name T53
Test name
Test status
Simulation time 105498208 ps
CPU time 3.2 seconds
Started Apr 02 01:45:41 PM PDT 24
Finished Apr 02 01:45:45 PM PDT 24
Peak memory 220300 kb
Host smart-ea9a3ae5-c63e-4b1b-8411-6cc15d3742f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794555207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.794555207
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.929814900
Short name T276
Test name
Test status
Simulation time 249611013 ps
CPU time 4.1 seconds
Started Apr 02 01:45:40 PM PDT 24
Finished Apr 02 01:45:44 PM PDT 24
Peak memory 218868 kb
Host smart-c41cd2ca-e7c5-4b30-a462-75311c39dd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929814900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.929814900
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1056567334
Short name T661
Test name
Test status
Simulation time 43020780 ps
CPU time 2.56 seconds
Started Apr 02 01:45:38 PM PDT 24
Finished Apr 02 01:45:40 PM PDT 24
Peak memory 206456 kb
Host smart-2281aed7-5183-45b5-b63d-9fd7f976ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056567334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1056567334
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1581515476
Short name T612
Test name
Test status
Simulation time 87368037 ps
CPU time 2.26 seconds
Started Apr 02 01:45:40 PM PDT 24
Finished Apr 02 01:45:42 PM PDT 24
Peak memory 207172 kb
Host smart-8dc3c31d-994f-4993-a81b-912b2f6d7f3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581515476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1581515476
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.421736134
Short name T807
Test name
Test status
Simulation time 161432501 ps
CPU time 5.43 seconds
Started Apr 02 01:45:38 PM PDT 24
Finished Apr 02 01:45:44 PM PDT 24
Peak memory 209416 kb
Host smart-b01c841b-1af2-4a65-9969-eb01b78f43e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421736134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.421736134
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2465188926
Short name T275
Test name
Test status
Simulation time 129405174 ps
CPU time 4.94 seconds
Started Apr 02 01:45:38 PM PDT 24
Finished Apr 02 01:45:43 PM PDT 24
Peak memory 208192 kb
Host smart-12543401-e6a2-4296-8822-e883d97bae58
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465188926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2465188926
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.672039951
Short name T511
Test name
Test status
Simulation time 836311667 ps
CPU time 10.81 seconds
Started Apr 02 01:45:44 PM PDT 24
Finished Apr 02 01:45:55 PM PDT 24
Peak memory 209380 kb
Host smart-58425888-5ff4-453f-a26b-99bddf82fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672039951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.672039951
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2313185116
Short name T531
Test name
Test status
Simulation time 114487949 ps
CPU time 3.44 seconds
Started Apr 02 01:45:39 PM PDT 24
Finished Apr 02 01:45:43 PM PDT 24
Peak memory 207104 kb
Host smart-be06e919-64ed-4f17-84a3-536c3a1699d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313185116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2313185116
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3668128235
Short name T692
Test name
Test status
Simulation time 2148508441 ps
CPU time 34.8 seconds
Started Apr 02 01:45:43 PM PDT 24
Finished Apr 02 01:46:18 PM PDT 24
Peak memory 223016 kb
Host smart-29398ec6-d964-4dc9-a78e-03bc9e03536a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668128235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3668128235
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1356293568
Short name T272
Test name
Test status
Simulation time 905896773 ps
CPU time 7.1 seconds
Started Apr 02 01:45:41 PM PDT 24
Finished Apr 02 01:45:48 PM PDT 24
Peak memory 208384 kb
Host smart-fad00458-d4c6-42f0-a43b-845ddd0153f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356293568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1356293568
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.437766800
Short name T61
Test name
Test status
Simulation time 1136866058 ps
CPU time 3.73 seconds
Started Apr 02 01:45:45 PM PDT 24
Finished Apr 02 01:45:49 PM PDT 24
Peak memory 210496 kb
Host smart-d914b7dd-2eb6-42ed-8edf-ad90b1cc567f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437766800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.437766800
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1815857338
Short name T453
Test name
Test status
Simulation time 221635340 ps
CPU time 0.91 seconds
Started Apr 02 01:45:58 PM PDT 24
Finished Apr 02 01:46:00 PM PDT 24
Peak memory 206336 kb
Host smart-a506bb0e-a196-4917-8fa7-d3145f3f2339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815857338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1815857338
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3706592475
Short name T141
Test name
Test status
Simulation time 558737520 ps
CPU time 9.15 seconds
Started Apr 02 01:45:47 PM PDT 24
Finished Apr 02 01:45:56 PM PDT 24
Peak memory 214692 kb
Host smart-7ae3b160-ad4f-4b81-a569-845e7482e01e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3706592475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3706592475
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3353725397
Short name T864
Test name
Test status
Simulation time 73222417 ps
CPU time 3.93 seconds
Started Apr 02 01:45:49 PM PDT 24
Finished Apr 02 01:45:53 PM PDT 24
Peak memory 215064 kb
Host smart-89a556a2-2245-447e-9762-ff8b57c56272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353725397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3353725397
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3181900062
Short name T631
Test name
Test status
Simulation time 118167497 ps
CPU time 4.81 seconds
Started Apr 02 01:45:50 PM PDT 24
Finished Apr 02 01:45:55 PM PDT 24
Peak memory 218692 kb
Host smart-c6a3899e-db65-403e-9c5f-f72afb1a1718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181900062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3181900062
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.696659685
Short name T92
Test name
Test status
Simulation time 196586850 ps
CPU time 5.33 seconds
Started Apr 02 01:45:48 PM PDT 24
Finished Apr 02 01:45:53 PM PDT 24
Peak memory 209472 kb
Host smart-97d5de24-41e7-465f-8a82-6715dd1c0bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696659685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.696659685
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2960663855
Short name T887
Test name
Test status
Simulation time 80564238 ps
CPU time 3.73 seconds
Started Apr 02 01:45:48 PM PDT 24
Finished Apr 02 01:45:52 PM PDT 24
Peak memory 211576 kb
Host smart-e9e817dc-3679-4c00-a24b-bc25e249e6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960663855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2960663855
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1953193577
Short name T855
Test name
Test status
Simulation time 538643485 ps
CPU time 7.61 seconds
Started Apr 02 01:45:48 PM PDT 24
Finished Apr 02 01:45:56 PM PDT 24
Peak memory 222856 kb
Host smart-ac8076ac-0034-4a22-99c2-1f99fa51b288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953193577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1953193577
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1121237436
Short name T736
Test name
Test status
Simulation time 566813707 ps
CPU time 5.54 seconds
Started Apr 02 01:46:10 PM PDT 24
Finished Apr 02 01:46:16 PM PDT 24
Peak memory 210072 kb
Host smart-d6f834da-e3c7-41f4-b318-7836a1ef86d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121237436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1121237436
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3763765916
Short name T842
Test name
Test status
Simulation time 117798223 ps
CPU time 4.74 seconds
Started Apr 02 01:45:46 PM PDT 24
Finished Apr 02 01:45:51 PM PDT 24
Peak memory 209112 kb
Host smart-dd81303d-ed63-4752-9c4f-e85442df9ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763765916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3763765916
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2113932006
Short name T351
Test name
Test status
Simulation time 251456371 ps
CPU time 3.29 seconds
Started Apr 02 01:45:51 PM PDT 24
Finished Apr 02 01:45:54 PM PDT 24
Peak memory 208812 kb
Host smart-4b59539d-c766-448d-be58-e265835eab34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113932006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2113932006
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.412042303
Short name T512
Test name
Test status
Simulation time 58476706 ps
CPU time 2.89 seconds
Started Apr 02 01:45:44 PM PDT 24
Finished Apr 02 01:45:47 PM PDT 24
Peak memory 206972 kb
Host smart-78fabed3-80b3-412d-a0fc-fdd412868d96
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412042303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.412042303
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.475125146
Short name T617
Test name
Test status
Simulation time 118790557 ps
CPU time 1.97 seconds
Started Apr 02 01:45:49 PM PDT 24
Finished Apr 02 01:45:51 PM PDT 24
Peak memory 208996 kb
Host smart-9f39a0f1-4cd5-4d5f-94e0-9cb4fadc90e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475125146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.475125146
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2568620585
Short name T672
Test name
Test status
Simulation time 435644190 ps
CPU time 4.19 seconds
Started Apr 02 01:45:59 PM PDT 24
Finished Apr 02 01:46:04 PM PDT 24
Peak memory 209444 kb
Host smart-c92f271b-5152-425c-a46a-2168f8a84700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568620585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2568620585
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4031003169
Short name T438
Test name
Test status
Simulation time 448643901 ps
CPU time 5.81 seconds
Started Apr 02 01:45:47 PM PDT 24
Finished Apr 02 01:45:53 PM PDT 24
Peak memory 208720 kb
Host smart-0f33b9f7-5dde-40f4-b491-5170a4935767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031003169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4031003169
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2225048195
Short name T261
Test name
Test status
Simulation time 4697172956 ps
CPU time 59.36 seconds
Started Apr 02 01:45:51 PM PDT 24
Finished Apr 02 01:46:51 PM PDT 24
Peak memory 216148 kb
Host smart-0326f273-cb68-43c5-9fa8-8331028042bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225048195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2225048195
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3426057910
Short name T869
Test name
Test status
Simulation time 72660301 ps
CPU time 4.41 seconds
Started Apr 02 01:45:49 PM PDT 24
Finished Apr 02 01:45:53 PM PDT 24
Peak memory 222816 kb
Host smart-3b624acc-d02d-472c-a7ce-fc0b0c7c9b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426057910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3426057910
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2530624754
Short name T159
Test name
Test status
Simulation time 203828330 ps
CPU time 2.62 seconds
Started Apr 02 01:45:57 PM PDT 24
Finished Apr 02 01:46:00 PM PDT 24
Peak memory 210436 kb
Host smart-dd27f7da-fd38-4fe4-a81d-c2e5c305082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530624754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2530624754
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2315786040
Short name T537
Test name
Test status
Simulation time 37259040 ps
CPU time 0.72 seconds
Started Apr 02 01:46:00 PM PDT 24
Finished Apr 02 01:46:02 PM PDT 24
Peak memory 206324 kb
Host smart-657b23c3-23ce-4131-903a-a40622753816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315786040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2315786040
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1905086027
Short name T340
Test name
Test status
Simulation time 70424709 ps
CPU time 4.81 seconds
Started Apr 02 01:46:01 PM PDT 24
Finished Apr 02 01:46:06 PM PDT 24
Peak memory 216104 kb
Host smart-9e4bcc9c-aef6-4d10-b055-fc70b02f9283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905086027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1905086027
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1483076585
Short name T27
Test name
Test status
Simulation time 176715419 ps
CPU time 3.37 seconds
Started Apr 02 01:45:59 PM PDT 24
Finished Apr 02 01:46:03 PM PDT 24
Peak memory 218304 kb
Host smart-ab47908f-926c-4674-8c6d-bbb7f412956b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483076585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1483076585
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.908554118
Short name T681
Test name
Test status
Simulation time 260296598 ps
CPU time 3.46 seconds
Started Apr 02 01:46:00 PM PDT 24
Finished Apr 02 01:46:04 PM PDT 24
Peak memory 209436 kb
Host smart-89f07e89-4dcf-41dc-a347-c13cfd53cba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908554118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.908554118
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.998011862
Short name T197
Test name
Test status
Simulation time 46149785 ps
CPU time 2.48 seconds
Started Apr 02 01:45:59 PM PDT 24
Finished Apr 02 01:46:02 PM PDT 24
Peak memory 209688 kb
Host smart-5b585606-e258-4bd3-baec-5948c5b99988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998011862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.998011862
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3216079873
Short name T381
Test name
Test status
Simulation time 1251511651 ps
CPU time 6.61 seconds
Started Apr 02 01:45:59 PM PDT 24
Finished Apr 02 01:46:06 PM PDT 24
Peak memory 222724 kb
Host smart-86712ce3-57a6-4829-b899-c01fc144ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216079873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3216079873
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.4267360344
Short name T67
Test name
Test status
Simulation time 251324816 ps
CPU time 4.29 seconds
Started Apr 02 01:45:58 PM PDT 24
Finished Apr 02 01:46:03 PM PDT 24
Peak memory 220572 kb
Host smart-95c0b60b-0aa5-4264-bc7c-9ebeb579b75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267360344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.4267360344
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1054221973
Short name T4
Test name
Test status
Simulation time 1160984513 ps
CPU time 5.63 seconds
Started Apr 02 01:45:58 PM PDT 24
Finished Apr 02 01:46:04 PM PDT 24
Peak memory 207728 kb
Host smart-3922899c-fb82-4272-b28c-4c85ab62a6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054221973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1054221973
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3403598584
Short name T504
Test name
Test status
Simulation time 164836196 ps
CPU time 3.71 seconds
Started Apr 02 01:45:57 PM PDT 24
Finished Apr 02 01:46:01 PM PDT 24
Peak memory 208872 kb
Host smart-feceed00-dcb9-4d40-a016-a92843e6cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403598584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3403598584
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2054827206
Short name T519
Test name
Test status
Simulation time 67840771 ps
CPU time 2.54 seconds
Started Apr 02 01:45:58 PM PDT 24
Finished Apr 02 01:46:01 PM PDT 24
Peak memory 207684 kb
Host smart-e2c0f9c7-4167-49ad-a14a-5405a438d85b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054827206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2054827206
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1829928474
Short name T466
Test name
Test status
Simulation time 56551383 ps
CPU time 3.14 seconds
Started Apr 02 01:45:58 PM PDT 24
Finished Apr 02 01:46:01 PM PDT 24
Peak memory 207024 kb
Host smart-407b3cb9-b51f-4cd9-ad7a-49a2729dfd5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829928474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1829928474
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4140042687
Short name T616
Test name
Test status
Simulation time 105150189 ps
CPU time 2.8 seconds
Started Apr 02 01:45:58 PM PDT 24
Finished Apr 02 01:46:01 PM PDT 24
Peak memory 208560 kb
Host smart-3dd1b0c0-9673-4361-8744-d0f1df27137a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140042687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4140042687
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.510618737
Short name T560
Test name
Test status
Simulation time 251724680 ps
CPU time 3.29 seconds
Started Apr 02 01:46:00 PM PDT 24
Finished Apr 02 01:46:04 PM PDT 24
Peak memory 218776 kb
Host smart-93e8be64-d790-44ae-bd90-84d9fc4a2950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510618737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.510618737
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2917449225
Short name T742
Test name
Test status
Simulation time 3833437591 ps
CPU time 23.08 seconds
Started Apr 02 01:45:57 PM PDT 24
Finished Apr 02 01:46:21 PM PDT 24
Peak memory 208632 kb
Host smart-2ceca22c-ec2a-4366-bb4d-f0032aa8329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917449225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2917449225
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3101703185
Short name T706
Test name
Test status
Simulation time 747650390 ps
CPU time 20.32 seconds
Started Apr 02 01:46:05 PM PDT 24
Finished Apr 02 01:46:25 PM PDT 24
Peak memory 222848 kb
Host smart-c1d7dd22-1c0a-4693-94f5-03a43fe411dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101703185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3101703185
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3778992945
Short name T882
Test name
Test status
Simulation time 483045935 ps
CPU time 6.61 seconds
Started Apr 02 01:46:00 PM PDT 24
Finished Apr 02 01:46:08 PM PDT 24
Peak memory 209368 kb
Host smart-3e3a7588-ebf3-4359-a4cf-1af03d7b67ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778992945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3778992945
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1202486176
Short name T472
Test name
Test status
Simulation time 166504557 ps
CPU time 2.01 seconds
Started Apr 02 01:46:05 PM PDT 24
Finished Apr 02 01:46:07 PM PDT 24
Peak memory 210208 kb
Host smart-e40656e5-68b5-42b0-a078-bf3e86e9917a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202486176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1202486176
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.169273698
Short name T696
Test name
Test status
Simulation time 11170875 ps
CPU time 0.79 seconds
Started Apr 02 01:42:15 PM PDT 24
Finished Apr 02 01:42:16 PM PDT 24
Peak memory 206244 kb
Host smart-a5524ab8-a77e-4722-817d-99071adcc7f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169273698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.169273698
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2527665296
Short name T145
Test name
Test status
Simulation time 40139942 ps
CPU time 3.28 seconds
Started Apr 02 01:42:02 PM PDT 24
Finished Apr 02 01:42:05 PM PDT 24
Peak memory 214696 kb
Host smart-e0b7f113-22ba-4bdb-bfbd-996acc26348a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527665296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2527665296
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3703620873
Short name T48
Test name
Test status
Simulation time 38344521 ps
CPU time 2.06 seconds
Started Apr 02 01:42:04 PM PDT 24
Finished Apr 02 01:42:07 PM PDT 24
Peak memory 209164 kb
Host smart-85f6da6b-df46-4ace-b8eb-f75d6c461456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703620873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3703620873
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1431406508
Short name T98
Test name
Test status
Simulation time 168262628 ps
CPU time 2.89 seconds
Started Apr 02 01:42:03 PM PDT 24
Finished Apr 02 01:42:07 PM PDT 24
Peak memory 209792 kb
Host smart-5376b2e4-b9de-4ce8-8e3a-aae24652a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431406508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1431406508
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3129055902
Short name T691
Test name
Test status
Simulation time 207434028 ps
CPU time 5.91 seconds
Started Apr 02 01:42:07 PM PDT 24
Finished Apr 02 01:42:13 PM PDT 24
Peak memory 222716 kb
Host smart-af4e07d5-2adc-4f73-ad95-40b1da979607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129055902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3129055902
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.730007656
Short name T138
Test name
Test status
Simulation time 89217130 ps
CPU time 3.17 seconds
Started Apr 02 01:42:02 PM PDT 24
Finished Apr 02 01:42:06 PM PDT 24
Peak memory 207372 kb
Host smart-0514e742-b42a-43f9-9ad8-94e6a9fb8523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730007656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.730007656
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3603992674
Short name T725
Test name
Test status
Simulation time 28672406 ps
CPU time 2.3 seconds
Started Apr 02 01:42:04 PM PDT 24
Finished Apr 02 01:42:07 PM PDT 24
Peak memory 207672 kb
Host smart-a49cb1b7-0c51-43e0-add1-560e3fab8b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603992674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3603992674
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2059791116
Short name T11
Test name
Test status
Simulation time 1578588276 ps
CPU time 26.96 seconds
Started Apr 02 01:42:18 PM PDT 24
Finished Apr 02 01:42:46 PM PDT 24
Peak memory 241508 kb
Host smart-16608915-3e2d-448f-9ede-6298983a2d6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059791116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2059791116
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3813132284
Short name T458
Test name
Test status
Simulation time 3235209237 ps
CPU time 22.1 seconds
Started Apr 02 01:41:58 PM PDT 24
Finished Apr 02 01:42:21 PM PDT 24
Peak memory 208528 kb
Host smart-8123b0de-7e55-4552-9c67-308fe7244d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813132284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3813132284
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1369333528
Short name T106
Test name
Test status
Simulation time 110134046 ps
CPU time 2.64 seconds
Started Apr 02 01:42:03 PM PDT 24
Finished Apr 02 01:42:06 PM PDT 24
Peak memory 206916 kb
Host smart-222127c7-3949-480c-8f70-4442b1111b7e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369333528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1369333528
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1052061447
Short name T693
Test name
Test status
Simulation time 51041864 ps
CPU time 2.68 seconds
Started Apr 02 01:42:01 PM PDT 24
Finished Apr 02 01:42:04 PM PDT 24
Peak memory 207176 kb
Host smart-bdef5adf-6ecf-48f2-a626-4139f2d049d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052061447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1052061447
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3926411709
Short name T492
Test name
Test status
Simulation time 170705669 ps
CPU time 2.73 seconds
Started Apr 02 01:42:02 PM PDT 24
Finished Apr 02 01:42:05 PM PDT 24
Peak memory 207236 kb
Host smart-f530fecf-b887-4fc6-84e9-7cd43315c3d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926411709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3926411709
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2838806237
Short name T656
Test name
Test status
Simulation time 80296962 ps
CPU time 1.73 seconds
Started Apr 02 01:42:06 PM PDT 24
Finished Apr 02 01:42:08 PM PDT 24
Peak memory 207632 kb
Host smart-ad6d4ef9-d810-48fa-9c5e-14e904accb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838806237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2838806237
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.730054868
Short name T446
Test name
Test status
Simulation time 180291946 ps
CPU time 3.02 seconds
Started Apr 02 01:41:57 PM PDT 24
Finished Apr 02 01:42:00 PM PDT 24
Peak memory 206916 kb
Host smart-489f8ae5-f7a9-4ba3-a77d-09705f7ffaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730054868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.730054868
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1401656821
Short name T79
Test name
Test status
Simulation time 9380800662 ps
CPU time 97.28 seconds
Started Apr 02 01:42:11 PM PDT 24
Finished Apr 02 01:43:49 PM PDT 24
Peak memory 217764 kb
Host smart-bfc157e0-cace-4b3e-a927-975ab0899f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401656821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1401656821
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.162701115
Short name T292
Test name
Test status
Simulation time 366621182 ps
CPU time 4.83 seconds
Started Apr 02 01:42:04 PM PDT 24
Finished Apr 02 01:42:09 PM PDT 24
Peak memory 207824 kb
Host smart-7a5f737c-b117-4eff-96b7-0987384afaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162701115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.162701115
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.704597377
Short name T51
Test name
Test status
Simulation time 141018085 ps
CPU time 1.42 seconds
Started Apr 02 01:42:07 PM PDT 24
Finished Apr 02 01:42:09 PM PDT 24
Peak memory 210176 kb
Host smart-966dad5b-cc45-4797-8a26-033139a759e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704597377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.704597377
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.4096240975
Short name T459
Test name
Test status
Simulation time 31447479 ps
CPU time 0.79 seconds
Started Apr 02 01:46:09 PM PDT 24
Finished Apr 02 01:46:10 PM PDT 24
Peak memory 206260 kb
Host smart-1f04c9cb-e1ff-4fdd-be64-be738688817b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096240975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4096240975
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3993127580
Short name T424
Test name
Test status
Simulation time 409329832 ps
CPU time 4.74 seconds
Started Apr 02 01:46:10 PM PDT 24
Finished Apr 02 01:46:15 PM PDT 24
Peak memory 215260 kb
Host smart-869046c2-2236-4c70-aa35-8358c64c3bfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993127580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3993127580
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3867764623
Short name T801
Test name
Test status
Simulation time 182919105 ps
CPU time 2.64 seconds
Started Apr 02 01:46:04 PM PDT 24
Finished Apr 02 01:46:07 PM PDT 24
Peak memory 214688 kb
Host smart-0f7ed6f9-7e6b-43fc-a44d-f787234979d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867764623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3867764623
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1237223197
Short name T102
Test name
Test status
Simulation time 5072570104 ps
CPU time 81.57 seconds
Started Apr 02 01:46:06 PM PDT 24
Finished Apr 02 01:47:28 PM PDT 24
Peak memory 218348 kb
Host smart-cfbf4d84-8ddb-4d63-bc3f-dcb0d4e1d3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237223197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1237223197
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3064375862
Short name T204
Test name
Test status
Simulation time 150294270 ps
CPU time 3.34 seconds
Started Apr 02 01:46:06 PM PDT 24
Finished Apr 02 01:46:10 PM PDT 24
Peak memory 220516 kb
Host smart-bc3508eb-a87f-4005-97ff-b7797e73bd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064375862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3064375862
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2809583528
Short name T230
Test name
Test status
Simulation time 265618717 ps
CPU time 5.78 seconds
Started Apr 02 01:46:04 PM PDT 24
Finished Apr 02 01:46:10 PM PDT 24
Peak memory 209624 kb
Host smart-17bf073a-860f-4d4b-81e7-0b78986eb709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809583528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2809583528
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1827433103
Short name T579
Test name
Test status
Simulation time 182158847 ps
CPU time 3.26 seconds
Started Apr 02 01:46:01 PM PDT 24
Finished Apr 02 01:46:05 PM PDT 24
Peak memory 207100 kb
Host smart-6a7061c0-139d-44cf-bd5e-15767b163b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827433103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1827433103
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.950924852
Short name T522
Test name
Test status
Simulation time 65093758 ps
CPU time 2.11 seconds
Started Apr 02 01:46:00 PM PDT 24
Finished Apr 02 01:46:03 PM PDT 24
Peak memory 207224 kb
Host smart-0521e4c3-c897-4c45-bd51-bb083c43ec4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950924852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.950924852
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1169052024
Short name T745
Test name
Test status
Simulation time 360610921 ps
CPU time 3.82 seconds
Started Apr 02 01:46:01 PM PDT 24
Finished Apr 02 01:46:05 PM PDT 24
Peak memory 208888 kb
Host smart-3527d810-76ac-4ee8-a837-f3d9b5000c6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169052024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1169052024
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.978458670
Short name T569
Test name
Test status
Simulation time 186029628 ps
CPU time 4.37 seconds
Started Apr 02 01:46:04 PM PDT 24
Finished Apr 02 01:46:09 PM PDT 24
Peak memory 208800 kb
Host smart-8bf67849-cbb4-45d7-b091-060d41671a20
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978458670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.978458670
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.4144011267
Short name T206
Test name
Test status
Simulation time 821080586 ps
CPU time 7.7 seconds
Started Apr 02 01:46:09 PM PDT 24
Finished Apr 02 01:46:17 PM PDT 24
Peak memory 209656 kb
Host smart-5e4a644f-54a1-4e85-803f-a3a76837c8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144011267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4144011267
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4184546510
Short name T600
Test name
Test status
Simulation time 71453315 ps
CPU time 2.49 seconds
Started Apr 02 01:46:02 PM PDT 24
Finished Apr 02 01:46:05 PM PDT 24
Peak memory 208636 kb
Host smart-c56e85ac-8cdd-416b-a652-9d3641370b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184546510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4184546510
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3592466611
Short name T671
Test name
Test status
Simulation time 115735346 ps
CPU time 3.66 seconds
Started Apr 02 01:46:07 PM PDT 24
Finished Apr 02 01:46:11 PM PDT 24
Peak memory 208588 kb
Host smart-f7558d9f-19bf-458b-9040-5ab407cfb70a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592466611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3592466611
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1928293257
Short name T246
Test name
Test status
Simulation time 32218674 ps
CPU time 2.43 seconds
Started Apr 02 01:46:05 PM PDT 24
Finished Apr 02 01:46:08 PM PDT 24
Peak memory 209464 kb
Host smart-00a2e84a-552e-483f-babb-8bfa7c46a5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928293257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1928293257
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3606516867
Short name T634
Test name
Test status
Simulation time 41643253 ps
CPU time 2.32 seconds
Started Apr 02 01:46:07 PM PDT 24
Finished Apr 02 01:46:10 PM PDT 24
Peak memory 209952 kb
Host smart-e311295b-f7df-4fc6-acdc-038732a92575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606516867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3606516867
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1233049236
Short name T844
Test name
Test status
Simulation time 48029006 ps
CPU time 0.74 seconds
Started Apr 02 01:46:16 PM PDT 24
Finished Apr 02 01:46:17 PM PDT 24
Peak memory 206212 kb
Host smart-8491d5b4-f3f7-4b95-b8c4-79c935a238f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233049236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1233049236
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4217164653
Short name T865
Test name
Test status
Simulation time 121613758 ps
CPU time 2.61 seconds
Started Apr 02 01:46:18 PM PDT 24
Finished Apr 02 01:46:22 PM PDT 24
Peak memory 214604 kb
Host smart-a69a6273-d078-4b8b-a4d8-8330be29a255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217164653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4217164653
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3134550401
Short name T26
Test name
Test status
Simulation time 62155001 ps
CPU time 2.28 seconds
Started Apr 02 01:46:14 PM PDT 24
Finished Apr 02 01:46:17 PM PDT 24
Peak memory 210192 kb
Host smart-638ffed6-7b05-440b-bf7f-d5d7cb3b9fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134550401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3134550401
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.132747927
Short name T626
Test name
Test status
Simulation time 242069028 ps
CPU time 4.01 seconds
Started Apr 02 01:46:17 PM PDT 24
Finished Apr 02 01:46:22 PM PDT 24
Peak memory 210316 kb
Host smart-6b2f57a8-4eeb-4f14-9ed7-3568e13b02a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132747927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.132747927
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.684904852
Short name T94
Test name
Test status
Simulation time 143496695 ps
CPU time 4.7 seconds
Started Apr 02 01:46:13 PM PDT 24
Finished Apr 02 01:46:18 PM PDT 24
Peak memory 208780 kb
Host smart-e0d550ba-1d5a-4cd2-b7e6-99d3553354e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684904852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.684904852
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1731040863
Short name T820
Test name
Test status
Simulation time 1285549755 ps
CPU time 9.15 seconds
Started Apr 02 01:46:13 PM PDT 24
Finished Apr 02 01:46:23 PM PDT 24
Peak memory 222852 kb
Host smart-ad2e3828-7b00-47df-a71c-74fe79e23531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731040863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1731040863
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3084168808
Short name T849
Test name
Test status
Simulation time 292957580 ps
CPU time 3.74 seconds
Started Apr 02 01:46:18 PM PDT 24
Finished Apr 02 01:46:23 PM PDT 24
Peak memory 220924 kb
Host smart-586eb798-fbed-48f5-af01-b122e0148bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084168808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3084168808
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2015742640
Short name T642
Test name
Test status
Simulation time 154127872 ps
CPU time 5.22 seconds
Started Apr 02 01:46:11 PM PDT 24
Finished Apr 02 01:46:17 PM PDT 24
Peak memory 207640 kb
Host smart-eb4582b2-339f-487f-b67d-bd21ebe9a5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015742640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2015742640
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3748383040
Short name T608
Test name
Test status
Simulation time 109278216 ps
CPU time 2.93 seconds
Started Apr 02 01:46:11 PM PDT 24
Finished Apr 02 01:46:14 PM PDT 24
Peak memory 207180 kb
Host smart-6568e1fe-830b-46d3-8c8a-e103882db071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748383040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3748383040
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3848010397
Short name T669
Test name
Test status
Simulation time 1835749027 ps
CPU time 35.61 seconds
Started Apr 02 01:46:11 PM PDT 24
Finished Apr 02 01:46:47 PM PDT 24
Peak memory 209212 kb
Host smart-f0d90240-1a7f-4b9c-982b-33790662c495
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848010397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3848010397
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3353466875
Short name T388
Test name
Test status
Simulation time 175428121 ps
CPU time 2.79 seconds
Started Apr 02 01:46:12 PM PDT 24
Finished Apr 02 01:46:15 PM PDT 24
Peak memory 207112 kb
Host smart-1fdb16d5-7ec5-4874-9848-0e8a5e5d0e0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353466875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3353466875
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2245276527
Short name T733
Test name
Test status
Simulation time 213679604 ps
CPU time 2.62 seconds
Started Apr 02 01:46:17 PM PDT 24
Finished Apr 02 01:46:20 PM PDT 24
Peak memory 208284 kb
Host smart-a894945a-b09e-4172-ab2f-ef17c238048e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245276527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2245276527
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3497830087
Short name T687
Test name
Test status
Simulation time 155994598 ps
CPU time 2.57 seconds
Started Apr 02 01:46:14 PM PDT 24
Finished Apr 02 01:46:17 PM PDT 24
Peak memory 209340 kb
Host smart-e6a12aed-104c-4c4e-b725-4dec64db389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497830087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3497830087
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2369746200
Short name T791
Test name
Test status
Simulation time 834120183 ps
CPU time 17.5 seconds
Started Apr 02 01:46:08 PM PDT 24
Finished Apr 02 01:46:26 PM PDT 24
Peak memory 208400 kb
Host smart-63d05698-77a3-49c0-9301-35fd7f8988c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369746200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2369746200
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3312829407
Short name T726
Test name
Test status
Simulation time 591816170 ps
CPU time 7.15 seconds
Started Apr 02 01:46:18 PM PDT 24
Finished Apr 02 01:46:26 PM PDT 24
Peak memory 214636 kb
Host smart-fa2c02a8-40e8-4b87-8832-0ccfd0e98cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312829407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3312829407
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2904727572
Short name T354
Test name
Test status
Simulation time 717390130 ps
CPU time 3.59 seconds
Started Apr 02 01:46:11 PM PDT 24
Finished Apr 02 01:46:14 PM PDT 24
Peak memory 214712 kb
Host smart-facde0d1-db29-40cb-87e1-539aaa8074cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904727572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2904727572
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3549500671
Short name T401
Test name
Test status
Simulation time 36363817 ps
CPU time 2.2 seconds
Started Apr 02 01:46:14 PM PDT 24
Finished Apr 02 01:46:17 PM PDT 24
Peak memory 210164 kb
Host smart-750a422c-459b-4b13-baf3-a1e0fe4a7b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549500671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3549500671
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2692380474
Short name T747
Test name
Test status
Simulation time 21470240 ps
CPU time 0.75 seconds
Started Apr 02 01:46:24 PM PDT 24
Finished Apr 02 01:46:25 PM PDT 24
Peak memory 206312 kb
Host smart-126e838e-c55b-4b34-9098-b1ad2ba95f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692380474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2692380474
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1349922664
Short name T24
Test name
Test status
Simulation time 1381158590 ps
CPU time 9.52 seconds
Started Apr 02 01:46:24 PM PDT 24
Finished Apr 02 01:46:34 PM PDT 24
Peak memory 214908 kb
Host smart-04579287-c832-46c5-89ac-f0e24d5237ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349922664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1349922664
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3791921601
Short name T572
Test name
Test status
Simulation time 191745846 ps
CPU time 5.11 seconds
Started Apr 02 01:46:23 PM PDT 24
Finished Apr 02 01:46:28 PM PDT 24
Peak memory 209932 kb
Host smart-63712b48-bf2a-4dba-a694-7454b0c642bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791921601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3791921601
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.723603787
Short name T397
Test name
Test status
Simulation time 382381425 ps
CPU time 4.65 seconds
Started Apr 02 01:46:24 PM PDT 24
Finished Apr 02 01:46:29 PM PDT 24
Peak memory 214628 kb
Host smart-df82f6e9-46ec-4ceb-a151-6449fb493b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723603787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.723603787
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1253827122
Short name T229
Test name
Test status
Simulation time 943866087 ps
CPU time 11.82 seconds
Started Apr 02 01:46:21 PM PDT 24
Finished Apr 02 01:46:33 PM PDT 24
Peak memory 210216 kb
Host smart-3be527ab-bad9-4892-beb3-8f64bc821be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253827122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1253827122
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.480636981
Short name T711
Test name
Test status
Simulation time 267415903 ps
CPU time 2.3 seconds
Started Apr 02 01:46:21 PM PDT 24
Finished Apr 02 01:46:23 PM PDT 24
Peak memory 215784 kb
Host smart-8a619be5-29dc-4971-b212-1dd197d2d1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480636981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.480636981
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4289510812
Short name T837
Test name
Test status
Simulation time 609335592 ps
CPU time 6.74 seconds
Started Apr 02 01:46:19 PM PDT 24
Finished Apr 02 01:46:26 PM PDT 24
Peak memory 218620 kb
Host smart-1e4df034-90b1-4fe0-bebf-3b7e5fe3f923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289510812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4289510812
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4137688969
Short name T528
Test name
Test status
Simulation time 32464781 ps
CPU time 2.19 seconds
Started Apr 02 01:46:19 PM PDT 24
Finished Apr 02 01:46:21 PM PDT 24
Peak memory 208964 kb
Host smart-9ef0009d-f0fc-4810-845b-2de2895b1ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137688969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4137688969
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1594821897
Short name T754
Test name
Test status
Simulation time 143130168 ps
CPU time 4.34 seconds
Started Apr 02 01:46:16 PM PDT 24
Finished Apr 02 01:46:21 PM PDT 24
Peak memory 207192 kb
Host smart-d98dfca3-1ed0-4d08-8c96-614214b19968
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594821897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1594821897
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1928188418
Short name T288
Test name
Test status
Simulation time 121467575 ps
CPU time 2.32 seconds
Started Apr 02 01:46:26 PM PDT 24
Finished Apr 02 01:46:30 PM PDT 24
Peak memory 209096 kb
Host smart-df50eee2-f81b-4351-954b-6353f5ab8859
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928188418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1928188418
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.4131379167
Short name T547
Test name
Test status
Simulation time 50025166 ps
CPU time 2.75 seconds
Started Apr 02 01:46:25 PM PDT 24
Finished Apr 02 01:46:28 PM PDT 24
Peak memory 215856 kb
Host smart-0f849f26-3d8a-43a0-8dda-13e25f62563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131379167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.4131379167
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.859126516
Short name T533
Test name
Test status
Simulation time 1008097887 ps
CPU time 6.66 seconds
Started Apr 02 01:46:16 PM PDT 24
Finished Apr 02 01:46:23 PM PDT 24
Peak memory 208552 kb
Host smart-881f23fa-d90b-4317-89ae-d2000f9af5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859126516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.859126516
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.895726402
Short name T169
Test name
Test status
Simulation time 1375797397 ps
CPU time 10.62 seconds
Started Apr 02 01:46:26 PM PDT 24
Finished Apr 02 01:46:37 PM PDT 24
Peak memory 222932 kb
Host smart-ecda7680-cd62-4faa-b1f2-bace6f982b17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895726402 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.895726402
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.4204458422
Short name T564
Test name
Test status
Simulation time 94606311 ps
CPU time 4.58 seconds
Started Apr 02 01:46:23 PM PDT 24
Finished Apr 02 01:46:28 PM PDT 24
Peak memory 218816 kb
Host smart-b1986782-41f5-413a-9554-4a42f98c8bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204458422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4204458422
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3880563057
Short name T721
Test name
Test status
Simulation time 76303818 ps
CPU time 2.49 seconds
Started Apr 02 01:46:24 PM PDT 24
Finished Apr 02 01:46:27 PM PDT 24
Peak memory 210008 kb
Host smart-427f9b39-5b12-4d33-b5a8-99a74787932d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880563057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3880563057
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1981574821
Short name T486
Test name
Test status
Simulation time 37997483 ps
CPU time 0.74 seconds
Started Apr 02 01:46:37 PM PDT 24
Finished Apr 02 01:46:38 PM PDT 24
Peak memory 206092 kb
Host smart-53c08d25-1086-4028-a58e-4c20a5f85a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981574821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1981574821
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.121382962
Short name T423
Test name
Test status
Simulation time 2544140213 ps
CPU time 9.88 seconds
Started Apr 02 01:46:32 PM PDT 24
Finished Apr 02 01:46:43 PM PDT 24
Peak memory 216108 kb
Host smart-cc64f4b6-fa64-48a5-8f1c-e155668fd8e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=121382962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.121382962
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3781945803
Short name T10
Test name
Test status
Simulation time 154366976 ps
CPU time 2.07 seconds
Started Apr 02 01:46:33 PM PDT 24
Finished Apr 02 01:46:35 PM PDT 24
Peak memory 217416 kb
Host smart-0233beab-978e-43c9-91be-0fb450eba486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781945803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3781945803
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.4140936594
Short name T601
Test name
Test status
Simulation time 83782337 ps
CPU time 3.88 seconds
Started Apr 02 01:46:29 PM PDT 24
Finished Apr 02 01:46:33 PM PDT 24
Peak memory 207820 kb
Host smart-5af81ebc-8749-4269-881c-9ca1aa42f1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140936594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.4140936594
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2806047838
Short name T89
Test name
Test status
Simulation time 604001594 ps
CPU time 6.2 seconds
Started Apr 02 01:46:30 PM PDT 24
Finished Apr 02 01:46:37 PM PDT 24
Peak memory 215460 kb
Host smart-abc1931f-f065-4334-a872-2f4f60877c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806047838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2806047838
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2414872666
Short name T852
Test name
Test status
Simulation time 936315496 ps
CPU time 9.22 seconds
Started Apr 02 01:46:33 PM PDT 24
Finished Apr 02 01:46:42 PM PDT 24
Peak memory 214680 kb
Host smart-0d037eba-f3c3-42a3-9995-00903b12e2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414872666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2414872666
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1905562037
Short name T854
Test name
Test status
Simulation time 830674845 ps
CPU time 5.78 seconds
Started Apr 02 01:46:27 PM PDT 24
Finished Apr 02 01:46:33 PM PDT 24
Peak memory 220540 kb
Host smart-3da7fe6a-3479-4969-974e-a3554ffd7e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905562037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1905562037
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1551517662
Short name T768
Test name
Test status
Simulation time 171758314 ps
CPU time 5.53 seconds
Started Apr 02 01:46:25 PM PDT 24
Finished Apr 02 01:46:30 PM PDT 24
Peak memory 209172 kb
Host smart-4ac75ac6-cbdf-4529-a488-732b83f425a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551517662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1551517662
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.760940426
Short name T385
Test name
Test status
Simulation time 1174030753 ps
CPU time 5.78 seconds
Started Apr 02 01:46:28 PM PDT 24
Finished Apr 02 01:46:35 PM PDT 24
Peak memory 208424 kb
Host smart-49fd1e03-843d-4db9-8177-17df3ece69d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760940426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.760940426
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1555897795
Short name T513
Test name
Test status
Simulation time 61707782 ps
CPU time 2.93 seconds
Started Apr 02 01:46:24 PM PDT 24
Finished Apr 02 01:46:27 PM PDT 24
Peak memory 207220 kb
Host smart-e7efe71d-7a1b-4954-9695-6cc51d20cd74
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555897795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1555897795
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2963980414
Short name T636
Test name
Test status
Simulation time 300913113 ps
CPU time 3.38 seconds
Started Apr 02 01:46:27 PM PDT 24
Finished Apr 02 01:46:31 PM PDT 24
Peak memory 209132 kb
Host smart-9fe129e3-3d32-4a5c-b5a1-4fa0b0e729fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963980414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2963980414
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.959899652
Short name T845
Test name
Test status
Simulation time 130392862 ps
CPU time 2.36 seconds
Started Apr 02 01:46:27 PM PDT 24
Finished Apr 02 01:46:30 PM PDT 24
Peak memory 207460 kb
Host smart-59c7b3fe-93f3-45aa-9026-8f67a4cbd4f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959899652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.959899652
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1759051857
Short name T218
Test name
Test status
Simulation time 107056424 ps
CPU time 4.39 seconds
Started Apr 02 01:46:33 PM PDT 24
Finished Apr 02 01:46:38 PM PDT 24
Peak memory 210492 kb
Host smart-0c539b9d-1874-436a-8c2d-0ec33b5a7d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759051857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1759051857
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2915802497
Short name T632
Test name
Test status
Simulation time 291539045 ps
CPU time 2.97 seconds
Started Apr 02 01:46:26 PM PDT 24
Finished Apr 02 01:46:29 PM PDT 24
Peak memory 206880 kb
Host smart-7b3388b9-fe3f-4123-aefd-fe082ba151a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915802497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2915802497
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.567847362
Short name T221
Test name
Test status
Simulation time 6889793941 ps
CPU time 46.79 seconds
Started Apr 02 01:46:33 PM PDT 24
Finished Apr 02 01:47:20 PM PDT 24
Peak memory 217324 kb
Host smart-e56b73de-e486-433b-b13d-61cc56ee1e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567847362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.567847362
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1791139810
Short name T877
Test name
Test status
Simulation time 2410432105 ps
CPU time 43.26 seconds
Started Apr 02 01:46:29 PM PDT 24
Finished Apr 02 01:47:13 PM PDT 24
Peak memory 208856 kb
Host smart-65a25030-2b1b-4194-a5e8-5737737a36e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791139810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1791139810
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3050467656
Short name T224
Test name
Test status
Simulation time 408364052 ps
CPU time 3.67 seconds
Started Apr 02 01:46:29 PM PDT 24
Finished Apr 02 01:46:33 PM PDT 24
Peak memory 210600 kb
Host smart-d926e064-a0d3-4ab0-b59c-18249eeed555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050467656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3050467656
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.4165828624
Short name T467
Test name
Test status
Simulation time 61056850 ps
CPU time 0.87 seconds
Started Apr 02 01:46:37 PM PDT 24
Finished Apr 02 01:46:38 PM PDT 24
Peak memory 206312 kb
Host smart-d2908bec-38ec-4185-824e-da2bec06ef07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165828624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4165828624
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3440012878
Short name T434
Test name
Test status
Simulation time 208784221 ps
CPU time 4.59 seconds
Started Apr 02 01:46:36 PM PDT 24
Finished Apr 02 01:46:40 PM PDT 24
Peak memory 214692 kb
Host smart-4ab4e09e-5450-456b-bd05-b744e10b2ad7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440012878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3440012878
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2357951865
Short name T588
Test name
Test status
Simulation time 221711450 ps
CPU time 2.32 seconds
Started Apr 02 01:46:37 PM PDT 24
Finished Apr 02 01:46:39 PM PDT 24
Peak memory 210228 kb
Host smart-fb4b6278-25da-4f11-bdba-22e883f5e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357951865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2357951865
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4048604117
Short name T808
Test name
Test status
Simulation time 237595583 ps
CPU time 7.09 seconds
Started Apr 02 01:46:34 PM PDT 24
Finished Apr 02 01:46:42 PM PDT 24
Peak memory 218536 kb
Host smart-6e51f825-ea49-48be-966b-46772be16a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048604117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4048604117
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4125067195
Short name T728
Test name
Test status
Simulation time 51984141 ps
CPU time 3.5 seconds
Started Apr 02 01:46:49 PM PDT 24
Finished Apr 02 01:46:53 PM PDT 24
Peak memory 222000 kb
Host smart-49578ddb-01f6-4452-88fe-0d98ea160568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125067195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4125067195
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3449713286
Short name T262
Test name
Test status
Simulation time 80665392 ps
CPU time 2.47 seconds
Started Apr 02 01:46:35 PM PDT 24
Finished Apr 02 01:46:38 PM PDT 24
Peak memory 214676 kb
Host smart-32987872-3c9c-4a0a-b91a-36d6e8210961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449713286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3449713286
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3393303478
Short name T16
Test name
Test status
Simulation time 113470730 ps
CPU time 5.42 seconds
Started Apr 02 01:46:34 PM PDT 24
Finished Apr 02 01:46:40 PM PDT 24
Peak memory 208464 kb
Host smart-1d5383e4-33f0-4af4-a6cf-15627dd6ec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393303478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3393303478
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.6554824
Short name T191
Test name
Test status
Simulation time 683782911 ps
CPU time 5.25 seconds
Started Apr 02 01:46:35 PM PDT 24
Finished Apr 02 01:46:41 PM PDT 24
Peak memory 209028 kb
Host smart-cb2f7280-9239-45f3-981f-876a92df2abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6554824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.6554824
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3071494766
Short name T344
Test name
Test status
Simulation time 8161773062 ps
CPU time 53.94 seconds
Started Apr 02 01:46:36 PM PDT 24
Finished Apr 02 01:47:30 PM PDT 24
Peak memory 209304 kb
Host smart-ba0f43bd-8acc-45f5-a6ae-9ba749eca92d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071494766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3071494766
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1438775611
Short name T474
Test name
Test status
Simulation time 1557369749 ps
CPU time 38.58 seconds
Started Apr 02 01:46:34 PM PDT 24
Finished Apr 02 01:47:13 PM PDT 24
Peak memory 208304 kb
Host smart-abebab8f-8d16-4573-b9d9-01094d332f0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438775611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1438775611
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1060402145
Short name T848
Test name
Test status
Simulation time 2905712890 ps
CPU time 34.59 seconds
Started Apr 02 01:46:35 PM PDT 24
Finished Apr 02 01:47:09 PM PDT 24
Peak memory 208332 kb
Host smart-d86a46ad-a720-4aff-8ea7-e34af93e509d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060402145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1060402145
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4259041234
Short name T284
Test name
Test status
Simulation time 231210191 ps
CPU time 2.91 seconds
Started Apr 02 01:46:39 PM PDT 24
Finished Apr 02 01:46:42 PM PDT 24
Peak memory 210328 kb
Host smart-1ba7a39e-4caf-44e1-ac33-805677872034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259041234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4259041234
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1681771984
Short name T487
Test name
Test status
Simulation time 107354237 ps
CPU time 3.57 seconds
Started Apr 02 01:46:37 PM PDT 24
Finished Apr 02 01:46:40 PM PDT 24
Peak memory 208980 kb
Host smart-dda0683a-2009-4213-bd16-6f89ea37ca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681771984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1681771984
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2230883643
Short name T122
Test name
Test status
Simulation time 171249525 ps
CPU time 6.19 seconds
Started Apr 02 01:46:38 PM PDT 24
Finished Apr 02 01:46:45 PM PDT 24
Peak memory 222988 kb
Host smart-a63c9b08-d22c-4bb8-8a86-633a3f5c6bdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230883643 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2230883643
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.932974226
Short name T313
Test name
Test status
Simulation time 79533034 ps
CPU time 2.69 seconds
Started Apr 02 01:46:36 PM PDT 24
Finished Apr 02 01:46:39 PM PDT 24
Peak memory 208952 kb
Host smart-1902316b-7f16-4680-a4d9-64f351b7b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932974226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.932974226
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3005127726
Short name T482
Test name
Test status
Simulation time 42976700 ps
CPU time 2.3 seconds
Started Apr 02 01:46:39 PM PDT 24
Finished Apr 02 01:46:42 PM PDT 24
Peak memory 210276 kb
Host smart-e41071b7-6a50-4cb7-829b-a0b9fe76f800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005127726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3005127726
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1228449697
Short name T738
Test name
Test status
Simulation time 15130145 ps
CPU time 0.79 seconds
Started Apr 02 01:46:44 PM PDT 24
Finished Apr 02 01:46:44 PM PDT 24
Peak memory 206336 kb
Host smart-67cbbe74-6c21-4dc4-b1db-e66d5356dbb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228449697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1228449697
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.218062598
Short name T878
Test name
Test status
Simulation time 2328268021 ps
CPU time 10.04 seconds
Started Apr 02 01:46:38 PM PDT 24
Finished Apr 02 01:46:48 PM PDT 24
Peak memory 209848 kb
Host smart-f1d1f031-1b6c-4c0c-be1d-22dc9ab18513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218062598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.218062598
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1613088787
Short name T818
Test name
Test status
Simulation time 287282052 ps
CPU time 5.01 seconds
Started Apr 02 01:46:40 PM PDT 24
Finished Apr 02 01:46:45 PM PDT 24
Peak memory 208984 kb
Host smart-23a7cd93-3259-4676-827e-4279cbdc277a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613088787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1613088787
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3982892781
Short name T328
Test name
Test status
Simulation time 247477779 ps
CPU time 8.83 seconds
Started Apr 02 01:46:41 PM PDT 24
Finished Apr 02 01:46:50 PM PDT 24
Peak memory 210828 kb
Host smart-9f8e38aa-18c6-4c32-bdfe-7252f4bcc6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982892781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3982892781
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2505897455
Short name T320
Test name
Test status
Simulation time 94408337 ps
CPU time 3.02 seconds
Started Apr 02 01:46:40 PM PDT 24
Finished Apr 02 01:46:43 PM PDT 24
Peak memory 214776 kb
Host smart-74ce12d6-f87a-476a-928a-ebbea60e18da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505897455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2505897455
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.507825740
Short name T730
Test name
Test status
Simulation time 1239928033 ps
CPU time 5.58 seconds
Started Apr 02 01:46:38 PM PDT 24
Finished Apr 02 01:46:44 PM PDT 24
Peak memory 210408 kb
Host smart-c0a6578e-455e-4cf2-904e-0b6f5eb9829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507825740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.507825740
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.739820256
Short name T304
Test name
Test status
Simulation time 7713556561 ps
CPU time 16.15 seconds
Started Apr 02 01:46:39 PM PDT 24
Finished Apr 02 01:46:55 PM PDT 24
Peak memory 208528 kb
Host smart-57bb740c-ba7e-4587-980e-48c6586812de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739820256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.739820256
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1870279803
Short name T707
Test name
Test status
Simulation time 81755106 ps
CPU time 2.36 seconds
Started Apr 02 01:46:38 PM PDT 24
Finished Apr 02 01:46:40 PM PDT 24
Peak memory 207188 kb
Host smart-7b8b5f92-4d29-4dc6-b144-05367766eb88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870279803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1870279803
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.292063040
Short name T592
Test name
Test status
Simulation time 80447679 ps
CPU time 3.68 seconds
Started Apr 02 01:46:37 PM PDT 24
Finished Apr 02 01:46:41 PM PDT 24
Peak memory 208724 kb
Host smart-982130f0-f1db-4175-a001-1560fa1fe31d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292063040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.292063040
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.753098470
Short name T625
Test name
Test status
Simulation time 339361094 ps
CPU time 7.31 seconds
Started Apr 02 01:46:39 PM PDT 24
Finished Apr 02 01:46:46 PM PDT 24
Peak memory 208788 kb
Host smart-a80dff5c-c0fd-4599-9a86-b6e807a6ee61
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753098470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.753098470
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3787851538
Short name T739
Test name
Test status
Simulation time 4328107075 ps
CPU time 35.83 seconds
Started Apr 02 01:46:41 PM PDT 24
Finished Apr 02 01:47:17 PM PDT 24
Peak memory 209436 kb
Host smart-3a7e6c92-795d-41d1-84a2-322d2a73bf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787851538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3787851538
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1569249482
Short name T815
Test name
Test status
Simulation time 597775219 ps
CPU time 4.62 seconds
Started Apr 02 01:46:38 PM PDT 24
Finished Apr 02 01:46:43 PM PDT 24
Peak memory 206944 kb
Host smart-80d3379e-8e91-44be-8259-c95c28640fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569249482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1569249482
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2353800387
Short name T734
Test name
Test status
Simulation time 871698225 ps
CPU time 20.9 seconds
Started Apr 02 01:46:42 PM PDT 24
Finished Apr 02 01:47:03 PM PDT 24
Peak memory 215224 kb
Host smart-9a1d7a17-33bd-4a15-a8eb-e264b54bb96f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353800387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2353800387
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2884504988
Short name T550
Test name
Test status
Simulation time 252566811 ps
CPU time 6.83 seconds
Started Apr 02 01:46:42 PM PDT 24
Finished Apr 02 01:46:49 PM PDT 24
Peak memory 208500 kb
Host smart-221cbd1a-80c6-4143-9144-138c60db339c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884504988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2884504988
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.277432691
Short name T509
Test name
Test status
Simulation time 1289046110 ps
CPU time 2.86 seconds
Started Apr 02 01:46:42 PM PDT 24
Finished Apr 02 01:46:45 PM PDT 24
Peak memory 210680 kb
Host smart-4203547f-8f62-438b-b8ef-208d91496948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277432691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.277432691
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2972250683
Short name T447
Test name
Test status
Simulation time 14735126 ps
CPU time 0.72 seconds
Started Apr 02 01:46:47 PM PDT 24
Finished Apr 02 01:46:48 PM PDT 24
Peak memory 206192 kb
Host smart-d0dda7b1-20f2-44d4-8b45-8cc4417a9b75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972250683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2972250683
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2068694377
Short name T368
Test name
Test status
Simulation time 61456878 ps
CPU time 2.64 seconds
Started Apr 02 01:46:47 PM PDT 24
Finished Apr 02 01:46:50 PM PDT 24
Peak memory 214660 kb
Host smart-88d3cef1-651f-495e-b6af-119ed0531b96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068694377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2068694377
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3398091017
Short name T534
Test name
Test status
Simulation time 59246773 ps
CPU time 2.94 seconds
Started Apr 02 01:46:47 PM PDT 24
Finished Apr 02 01:46:50 PM PDT 24
Peak memory 214628 kb
Host smart-9ba8154f-950e-479e-9070-c94a27849bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398091017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3398091017
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3371819798
Short name T374
Test name
Test status
Simulation time 104239998 ps
CPU time 4.48 seconds
Started Apr 02 01:46:47 PM PDT 24
Finished Apr 02 01:46:52 PM PDT 24
Peak memory 215076 kb
Host smart-7267ac97-68a3-4350-b217-cf0bd0d42742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371819798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3371819798
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.152634691
Short name T30
Test name
Test status
Simulation time 733151030 ps
CPU time 5.4 seconds
Started Apr 02 01:46:47 PM PDT 24
Finished Apr 02 01:46:53 PM PDT 24
Peak memory 211752 kb
Host smart-091bf6d9-e535-45fa-8135-5f685de6677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152634691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.152634691
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3616459366
Short name T255
Test name
Test status
Simulation time 323490081 ps
CPU time 2.91 seconds
Started Apr 02 01:46:44 PM PDT 24
Finished Apr 02 01:46:47 PM PDT 24
Peak memory 214700 kb
Host smart-7018e236-4791-4515-a88b-9d952ac221b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616459366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3616459366
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1703507231
Short name T325
Test name
Test status
Simulation time 112527635 ps
CPU time 4.86 seconds
Started Apr 02 01:46:45 PM PDT 24
Finished Apr 02 01:46:50 PM PDT 24
Peak memory 208532 kb
Host smart-008ad9f5-cf4a-4255-a572-1e38293abd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703507231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1703507231
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2573579534
Short name T480
Test name
Test status
Simulation time 1670707174 ps
CPU time 30.14 seconds
Started Apr 02 01:46:41 PM PDT 24
Finished Apr 02 01:47:11 PM PDT 24
Peak memory 208496 kb
Host smart-cbeb504d-3f12-4ce8-9b0d-4f8c2a62592e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573579534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2573579534
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2834690021
Short name T387
Test name
Test status
Simulation time 50232142 ps
CPU time 2.54 seconds
Started Apr 02 01:46:42 PM PDT 24
Finished Apr 02 01:46:45 PM PDT 24
Peak memory 208148 kb
Host smart-4da09a25-c4dd-4496-904e-9491ab1ee5b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834690021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2834690021
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1137947211
Short name T215
Test name
Test status
Simulation time 38876022 ps
CPU time 2.72 seconds
Started Apr 02 01:46:42 PM PDT 24
Finished Apr 02 01:46:45 PM PDT 24
Peak memory 209032 kb
Host smart-df3194f5-7402-4793-8ec5-c6c1b0b38306
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137947211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1137947211
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1423231370
Short name T297
Test name
Test status
Simulation time 329416101 ps
CPU time 3.14 seconds
Started Apr 02 01:46:41 PM PDT 24
Finished Apr 02 01:46:44 PM PDT 24
Peak memory 208992 kb
Host smart-613d3580-a026-4eae-9607-e832dca053c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423231370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1423231370
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3711005813
Short name T499
Test name
Test status
Simulation time 32628321 ps
CPU time 2.04 seconds
Started Apr 02 01:46:44 PM PDT 24
Finished Apr 02 01:46:46 PM PDT 24
Peak memory 207696 kb
Host smart-9e479e6e-ac3b-46b7-a07e-c7932afef4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711005813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3711005813
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1719357150
Short name T136
Test name
Test status
Simulation time 125366832 ps
CPU time 3.04 seconds
Started Apr 02 01:46:42 PM PDT 24
Finished Apr 02 01:46:45 PM PDT 24
Peak memory 208056 kb
Host smart-5bf1c456-b58b-4f2f-a1cf-c5a5179deb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719357150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1719357150
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1125172730
Short name T232
Test name
Test status
Simulation time 211742659 ps
CPU time 4.84 seconds
Started Apr 02 01:46:43 PM PDT 24
Finished Apr 02 01:46:48 PM PDT 24
Peak memory 208876 kb
Host smart-6bd79908-2554-44bc-800f-1692088d624f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125172730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1125172730
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1808538430
Short name T817
Test name
Test status
Simulation time 60412230 ps
CPU time 2.06 seconds
Started Apr 02 01:46:44 PM PDT 24
Finished Apr 02 01:46:46 PM PDT 24
Peak memory 210404 kb
Host smart-d6e3defd-03b7-4be7-b3bd-75007ff9fbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808538430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1808538430
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2049781713
Short name T211
Test name
Test status
Simulation time 67051627 ps
CPU time 0.99 seconds
Started Apr 02 01:46:50 PM PDT 24
Finished Apr 02 01:46:51 PM PDT 24
Peak memory 206388 kb
Host smart-7fa1cf18-ed96-4148-8536-af00b9895e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049781713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2049781713
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1911479297
Short name T29
Test name
Test status
Simulation time 113706311 ps
CPU time 4.65 seconds
Started Apr 02 01:46:55 PM PDT 24
Finished Apr 02 01:47:00 PM PDT 24
Peak memory 209616 kb
Host smart-b312d4ed-3c35-41d6-af9f-c4fa3a6b8ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911479297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1911479297
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4087375734
Short name T75
Test name
Test status
Simulation time 135742900 ps
CPU time 3.35 seconds
Started Apr 02 01:46:47 PM PDT 24
Finished Apr 02 01:46:50 PM PDT 24
Peak memory 219920 kb
Host smart-ca7edfae-5a45-4bc8-9e7d-0b194f0df15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087375734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4087375734
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.393184121
Short name T620
Test name
Test status
Simulation time 89212130 ps
CPU time 4.28 seconds
Started Apr 02 01:46:51 PM PDT 24
Finished Apr 02 01:46:55 PM PDT 24
Peak memory 208800 kb
Host smart-1f49063d-ac33-49b0-bb77-e28efd522082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393184121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.393184121
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2234807002
Short name T260
Test name
Test status
Simulation time 295137406 ps
CPU time 3.73 seconds
Started Apr 02 01:46:50 PM PDT 24
Finished Apr 02 01:46:54 PM PDT 24
Peak memory 214716 kb
Host smart-e9fdb469-cb2c-4ceb-baa1-1622da541493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234807002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2234807002
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.308464588
Short name T757
Test name
Test status
Simulation time 87728095 ps
CPU time 3.16 seconds
Started Apr 02 01:46:48 PM PDT 24
Finished Apr 02 01:46:51 PM PDT 24
Peak memory 209288 kb
Host smart-8351df49-fa36-412c-818a-662e2f35916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308464588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.308464588
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1517301824
Short name T613
Test name
Test status
Simulation time 460559376 ps
CPU time 4.21 seconds
Started Apr 02 01:46:47 PM PDT 24
Finished Apr 02 01:46:51 PM PDT 24
Peak memory 207040 kb
Host smart-5ac400bb-81df-4f4a-8201-2b3263677372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517301824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1517301824
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.694955263
Short name T452
Test name
Test status
Simulation time 25272011 ps
CPU time 1.91 seconds
Started Apr 02 01:46:50 PM PDT 24
Finished Apr 02 01:46:52 PM PDT 24
Peak memory 207664 kb
Host smart-fbe9e345-3394-4e96-97d2-8647abd268a7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694955263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.694955263
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1842963662
Short name T874
Test name
Test status
Simulation time 870659127 ps
CPU time 29.63 seconds
Started Apr 02 01:46:48 PM PDT 24
Finished Apr 02 01:47:17 PM PDT 24
Peak memory 208896 kb
Host smart-8bf41f78-1de0-44e8-9e58-a6274c08779f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842963662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1842963662
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2143749779
Short name T527
Test name
Test status
Simulation time 226902385 ps
CPU time 7.28 seconds
Started Apr 02 01:46:48 PM PDT 24
Finished Apr 02 01:46:55 PM PDT 24
Peak memory 208092 kb
Host smart-7abcd73a-b819-419e-91d7-e7c3b37a7285
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143749779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2143749779
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2622878036
Short name T324
Test name
Test status
Simulation time 330709056 ps
CPU time 2.84 seconds
Started Apr 02 01:46:50 PM PDT 24
Finished Apr 02 01:46:53 PM PDT 24
Peak memory 214696 kb
Host smart-41d9a5a0-5791-4ded-bbb9-cf6f324b7119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622878036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2622878036
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1346403219
Short name T410
Test name
Test status
Simulation time 6260236565 ps
CPU time 52.16 seconds
Started Apr 02 01:46:48 PM PDT 24
Finished Apr 02 01:47:40 PM PDT 24
Peak memory 208704 kb
Host smart-a5b305da-79ab-4fef-9b27-ca481a837fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346403219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1346403219
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3266976347
Short name T727
Test name
Test status
Simulation time 3804915694 ps
CPU time 24.43 seconds
Started Apr 02 01:46:48 PM PDT 24
Finished Apr 02 01:47:13 PM PDT 24
Peak memory 214876 kb
Host smart-865c3925-23eb-4a0b-aa9c-5c30b6fc870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266976347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3266976347
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1009048122
Short name T497
Test name
Test status
Simulation time 68676132 ps
CPU time 2.65 seconds
Started Apr 02 01:46:49 PM PDT 24
Finished Apr 02 01:46:52 PM PDT 24
Peak memory 210204 kb
Host smart-fc1164be-45c2-4c3f-b062-8f33737a2d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009048122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1009048122
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.652659392
Short name T479
Test name
Test status
Simulation time 20297475 ps
CPU time 0.76 seconds
Started Apr 02 01:46:54 PM PDT 24
Finished Apr 02 01:46:55 PM PDT 24
Peak memory 206324 kb
Host smart-6e2d20f1-b9ac-43ea-9722-77230f2f2f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652659392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.652659392
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2000065950
Short name T308
Test name
Test status
Simulation time 1758458788 ps
CPU time 27.74 seconds
Started Apr 02 01:46:55 PM PDT 24
Finished Apr 02 01:47:22 PM PDT 24
Peak memory 222792 kb
Host smart-dba95ab4-5a43-469b-b88e-0b43932e91fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000065950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2000065950
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1903054971
Short name T675
Test name
Test status
Simulation time 371071010 ps
CPU time 4.7 seconds
Started Apr 02 01:46:54 PM PDT 24
Finished Apr 02 01:46:59 PM PDT 24
Peak memory 210700 kb
Host smart-13743265-04f4-46a7-a5d2-9234bfa07d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903054971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1903054971
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2891400346
Short name T712
Test name
Test status
Simulation time 95923554 ps
CPU time 4.08 seconds
Started Apr 02 01:46:56 PM PDT 24
Finished Apr 02 01:47:00 PM PDT 24
Peak memory 214620 kb
Host smart-800848d3-643a-4712-8af4-8b7dd8626aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891400346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2891400346
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2897663635
Short name T140
Test name
Test status
Simulation time 101485746 ps
CPU time 4.58 seconds
Started Apr 02 01:46:54 PM PDT 24
Finished Apr 02 01:46:59 PM PDT 24
Peak memory 210200 kb
Host smart-1460f84c-511c-4680-9da9-d1d8f6f41450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897663635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2897663635
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.101143411
Short name T361
Test name
Test status
Simulation time 115751349 ps
CPU time 3.98 seconds
Started Apr 02 01:46:55 PM PDT 24
Finished Apr 02 01:46:59 PM PDT 24
Peak memory 218668 kb
Host smart-16a379c3-1581-47c1-8429-ad4111a82e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101143411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.101143411
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3903222739
Short name T87
Test name
Test status
Simulation time 177376053 ps
CPU time 2.69 seconds
Started Apr 02 01:46:54 PM PDT 24
Finished Apr 02 01:46:57 PM PDT 24
Peak memory 207184 kb
Host smart-11837c62-22c8-4b41-be19-bbb3e248c571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903222739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3903222739
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.34848019
Short name T365
Test name
Test status
Simulation time 405385014 ps
CPU time 5.09 seconds
Started Apr 02 01:46:51 PM PDT 24
Finished Apr 02 01:46:56 PM PDT 24
Peak memory 209248 kb
Host smart-1ec7d38c-a2d4-4bb3-8c64-679d4a136aab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34848019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.34848019
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.334973573
Short name T477
Test name
Test status
Simulation time 587957407 ps
CPU time 7.74 seconds
Started Apr 02 01:46:51 PM PDT 24
Finished Apr 02 01:46:59 PM PDT 24
Peak memory 208360 kb
Host smart-cc08d93a-42d2-4f39-b79f-8e64e50eb97e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334973573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.334973573
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2449005353
Short name T628
Test name
Test status
Simulation time 1626627061 ps
CPU time 37.87 seconds
Started Apr 02 01:46:54 PM PDT 24
Finished Apr 02 01:47:32 PM PDT 24
Peak memory 209496 kb
Host smart-c0850d90-9657-4ec0-bf25-c87123043bd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449005353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2449005353
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2324665801
Short name T875
Test name
Test status
Simulation time 58848152 ps
CPU time 1.91 seconds
Started Apr 02 01:46:54 PM PDT 24
Finished Apr 02 01:46:56 PM PDT 24
Peak memory 208268 kb
Host smart-64434227-8053-42b4-9ab8-14bec76ec9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324665801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2324665801
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2078469716
Short name T84
Test name
Test status
Simulation time 61349568 ps
CPU time 2.8 seconds
Started Apr 02 01:46:50 PM PDT 24
Finished Apr 02 01:46:53 PM PDT 24
Peak memory 207036 kb
Host smart-7de09a11-f299-447f-93ca-2c14878d1534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078469716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2078469716
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.967951539
Short name T223
Test name
Test status
Simulation time 696889643 ps
CPU time 12.74 seconds
Started Apr 02 01:46:54 PM PDT 24
Finished Apr 02 01:47:07 PM PDT 24
Peak memory 220296 kb
Host smart-23d5f6aa-0233-4a0f-bdaf-9f4705c20d88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967951539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.967951539
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.353258942
Short name T305
Test name
Test status
Simulation time 251720404 ps
CPU time 8.86 seconds
Started Apr 02 01:46:53 PM PDT 24
Finished Apr 02 01:47:02 PM PDT 24
Peak memory 208720 kb
Host smart-055adaa9-bc6a-4729-b344-c48c4877d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353258942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.353258942
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.223561525
Short name T193
Test name
Test status
Simulation time 95669282 ps
CPU time 0.96 seconds
Started Apr 02 01:47:04 PM PDT 24
Finished Apr 02 01:47:05 PM PDT 24
Peak memory 206468 kb
Host smart-61b26371-976c-47ce-b47d-b52b9d76af53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223561525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.223561525
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.291754670
Short name T783
Test name
Test status
Simulation time 188897770 ps
CPU time 5.9 seconds
Started Apr 02 01:46:59 PM PDT 24
Finished Apr 02 01:47:05 PM PDT 24
Peak memory 220276 kb
Host smart-ec95e080-48ea-4a35-a44c-36d92936f3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291754670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.291754670
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.907312688
Short name T713
Test name
Test status
Simulation time 3129633904 ps
CPU time 19.19 seconds
Started Apr 02 01:47:00 PM PDT 24
Finished Apr 02 01:47:19 PM PDT 24
Peak memory 208780 kb
Host smart-35f9f914-167e-457c-b7ee-de6f86850c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907312688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.907312688
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4164748268
Short name T369
Test name
Test status
Simulation time 1245594859 ps
CPU time 5.39 seconds
Started Apr 02 01:46:55 PM PDT 24
Finished Apr 02 01:47:01 PM PDT 24
Peak memory 209768 kb
Host smart-9fb4f601-58a9-4d17-ab58-e9292c55aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164748268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4164748268
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.319259106
Short name T890
Test name
Test status
Simulation time 228905108 ps
CPU time 4.01 seconds
Started Apr 02 01:46:59 PM PDT 24
Finished Apr 02 01:47:03 PM PDT 24
Peak memory 222816 kb
Host smart-2edc78a4-0f19-4259-954b-8145dd209e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319259106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.319259106
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.739000982
Short name T859
Test name
Test status
Simulation time 71355817 ps
CPU time 3.83 seconds
Started Apr 02 01:46:59 PM PDT 24
Finished Apr 02 01:47:03 PM PDT 24
Peak memory 214844 kb
Host smart-3c998634-3553-4a09-a38e-b963cc52709c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739000982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.739000982
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1859708634
Short name T226
Test name
Test status
Simulation time 415596978 ps
CPU time 11.7 seconds
Started Apr 02 01:46:56 PM PDT 24
Finished Apr 02 01:47:08 PM PDT 24
Peak memory 214696 kb
Host smart-3938c7e8-129f-4229-90e4-3706e1dde719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859708634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1859708634
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.750312954
Short name T552
Test name
Test status
Simulation time 1091735913 ps
CPU time 3.54 seconds
Started Apr 02 01:46:57 PM PDT 24
Finished Apr 02 01:47:01 PM PDT 24
Peak memory 207300 kb
Host smart-c9b64b3f-5b3a-4fd7-b6bb-82daaf8a7158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750312954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.750312954
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1259122700
Short name T212
Test name
Test status
Simulation time 409128438 ps
CPU time 5.05 seconds
Started Apr 02 01:46:58 PM PDT 24
Finished Apr 02 01:47:03 PM PDT 24
Peak memory 208724 kb
Host smart-ba7ed614-3145-4f9f-a2c3-6bdd9dde2a1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259122700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1259122700
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.906434050
Short name T322
Test name
Test status
Simulation time 129676453 ps
CPU time 2.5 seconds
Started Apr 02 01:46:56 PM PDT 24
Finished Apr 02 01:46:59 PM PDT 24
Peak memory 207856 kb
Host smart-62c89e59-c29c-40ee-be39-bfebdae533ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906434050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.906434050
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.275116392
Short name T456
Test name
Test status
Simulation time 2627776312 ps
CPU time 17.76 seconds
Started Apr 02 01:46:56 PM PDT 24
Finished Apr 02 01:47:14 PM PDT 24
Peak memory 208452 kb
Host smart-9bc3558a-975a-466e-99a6-ee46021ee8f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275116392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.275116392
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.201872549
Short name T540
Test name
Test status
Simulation time 144786697 ps
CPU time 2.19 seconds
Started Apr 02 01:46:59 PM PDT 24
Finished Apr 02 01:47:01 PM PDT 24
Peak memory 207668 kb
Host smart-bfbd4727-d5e6-4418-860a-d71bef62ec9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201872549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.201872549
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3667047811
Short name T889
Test name
Test status
Simulation time 141334397 ps
CPU time 3.76 seconds
Started Apr 02 01:46:58 PM PDT 24
Finished Apr 02 01:47:02 PM PDT 24
Peak memory 207104 kb
Host smart-3d66f951-0fbd-4393-b4b6-efb07455b03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667047811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3667047811
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.494356600
Short name T475
Test name
Test status
Simulation time 855550137 ps
CPU time 7.13 seconds
Started Apr 02 01:46:58 PM PDT 24
Finished Apr 02 01:47:05 PM PDT 24
Peak memory 209420 kb
Host smart-65a30e67-27b1-445d-afcd-1d4cb3c118e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494356600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.494356600
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2795220167
Short name T62
Test name
Test status
Simulation time 1070989218 ps
CPU time 26.61 seconds
Started Apr 02 01:46:59 PM PDT 24
Finished Apr 02 01:47:26 PM PDT 24
Peak memory 210748 kb
Host smart-bd1e3942-3df0-4aee-97fb-b2ebeca952cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795220167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2795220167
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3199516587
Short name T786
Test name
Test status
Simulation time 51733545 ps
CPU time 0.94 seconds
Started Apr 02 01:42:19 PM PDT 24
Finished Apr 02 01:42:20 PM PDT 24
Peak memory 206480 kb
Host smart-2c23ef76-0182-476c-9064-d7e435fb34b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199516587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3199516587
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3460312757
Short name T427
Test name
Test status
Simulation time 214924154 ps
CPU time 7.86 seconds
Started Apr 02 01:42:15 PM PDT 24
Finished Apr 02 01:42:23 PM PDT 24
Peak memory 214744 kb
Host smart-7385eca7-07d4-4733-a5b7-307434fe1d39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460312757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3460312757
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1860823129
Short name T800
Test name
Test status
Simulation time 77316756 ps
CPU time 2.24 seconds
Started Apr 02 01:42:13 PM PDT 24
Finished Apr 02 01:42:15 PM PDT 24
Peak memory 209272 kb
Host smart-7369590b-9793-40d5-ac3e-60edaf04f538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860823129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1860823129
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2467163047
Short name T95
Test name
Test status
Simulation time 364841285 ps
CPU time 4.39 seconds
Started Apr 02 01:42:17 PM PDT 24
Finished Apr 02 01:42:21 PM PDT 24
Peak memory 214808 kb
Host smart-8f3ffc15-d6aa-4810-9c2d-be631bdacb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467163047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2467163047
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3216066902
Short name T68
Test name
Test status
Simulation time 44758990 ps
CPU time 2.78 seconds
Started Apr 02 01:42:16 PM PDT 24
Finished Apr 02 01:42:19 PM PDT 24
Peak memory 208984 kb
Host smart-0a68736d-528b-40c9-b226-6b65bb4b2552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216066902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3216066902
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1664935259
Short name T273
Test name
Test status
Simulation time 36114413 ps
CPU time 2.49 seconds
Started Apr 02 01:42:14 PM PDT 24
Finished Apr 02 01:42:16 PM PDT 24
Peak memory 209952 kb
Host smart-86b98134-92f5-4306-98f8-ea443519ca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664935259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1664935259
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3955035094
Short name T107
Test name
Test status
Simulation time 2542315523 ps
CPU time 22.07 seconds
Started Apr 02 01:42:17 PM PDT 24
Finished Apr 02 01:42:39 PM PDT 24
Peak memory 240956 kb
Host smart-e3c03339-f8ea-41ea-b3b4-c1455d112e93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955035094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3955035094
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.962779828
Short name T619
Test name
Test status
Simulation time 126150207 ps
CPU time 3.5 seconds
Started Apr 02 01:42:15 PM PDT 24
Finished Apr 02 01:42:18 PM PDT 24
Peak memory 209280 kb
Host smart-9217cb97-c64d-4ed5-b358-e4c02e742a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962779828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.962779828
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1466403669
Short name T662
Test name
Test status
Simulation time 59467496 ps
CPU time 2.95 seconds
Started Apr 02 01:42:19 PM PDT 24
Finished Apr 02 01:42:22 PM PDT 24
Peak memory 208276 kb
Host smart-b24d7719-efff-4c2e-8eed-50813e0e52c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466403669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1466403669
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4176457392
Short name T517
Test name
Test status
Simulation time 61757412 ps
CPU time 3.12 seconds
Started Apr 02 01:42:10 PM PDT 24
Finished Apr 02 01:42:13 PM PDT 24
Peak memory 209188 kb
Host smart-122d615b-8f0f-496b-a178-7e172f743521
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176457392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4176457392
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4262534624
Short name T356
Test name
Test status
Simulation time 168219142 ps
CPU time 5.12 seconds
Started Apr 02 01:42:18 PM PDT 24
Finished Apr 02 01:42:24 PM PDT 24
Peak memory 208908 kb
Host smart-bf15e5fe-b075-4397-9059-4b876e9ee0a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262534624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4262534624
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3087042939
Short name T785
Test name
Test status
Simulation time 101094927 ps
CPU time 3.25 seconds
Started Apr 02 01:42:15 PM PDT 24
Finished Apr 02 01:42:19 PM PDT 24
Peak memory 209284 kb
Host smart-09ee42e5-143b-4b9a-8af1-d7c7091d1ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087042939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3087042939
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.526847981
Short name T676
Test name
Test status
Simulation time 41295151 ps
CPU time 1.67 seconds
Started Apr 02 01:42:10 PM PDT 24
Finished Apr 02 01:42:11 PM PDT 24
Peak memory 207064 kb
Host smart-e5c8b84e-bd49-45cd-ae36-217e70ef99f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526847981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.526847981
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2011733884
Short name T348
Test name
Test status
Simulation time 6352411726 ps
CPU time 42.31 seconds
Started Apr 02 01:42:17 PM PDT 24
Finished Apr 02 01:43:00 PM PDT 24
Peak memory 222932 kb
Host smart-f2a02c61-5986-4673-82fb-6eff014f6e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011733884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2011733884
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.387775879
Short name T125
Test name
Test status
Simulation time 260948451 ps
CPU time 5.68 seconds
Started Apr 02 01:42:18 PM PDT 24
Finished Apr 02 01:42:24 PM PDT 24
Peak memory 223080 kb
Host smart-1a11b908-9934-4116-8545-dab4a54f1ac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387775879 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.387775879
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2166812257
Short name T718
Test name
Test status
Simulation time 713400223 ps
CPU time 9.39 seconds
Started Apr 02 01:42:15 PM PDT 24
Finished Apr 02 01:42:25 PM PDT 24
Peak memory 214708 kb
Host smart-ad727025-0ce1-4c4a-adba-c2a08433030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166812257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2166812257
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.908968666
Short name T131
Test name
Test status
Simulation time 109233386 ps
CPU time 2.91 seconds
Started Apr 02 01:42:21 PM PDT 24
Finished Apr 02 01:42:24 PM PDT 24
Peak memory 210000 kb
Host smart-758145bc-812a-498a-88bb-18073bf85265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908968666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.908968666
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3790276254
Short name T793
Test name
Test status
Simulation time 16904610 ps
CPU time 0.78 seconds
Started Apr 02 01:47:09 PM PDT 24
Finished Apr 02 01:47:10 PM PDT 24
Peak memory 206200 kb
Host smart-71b8a269-554f-459d-84ce-0c5b365bfb21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790276254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3790276254
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1127564087
Short name T884
Test name
Test status
Simulation time 68077525 ps
CPU time 2.81 seconds
Started Apr 02 01:47:05 PM PDT 24
Finished Apr 02 01:47:08 PM PDT 24
Peak memory 214968 kb
Host smart-42a69a45-1ab1-445f-a0d4-8e0fda5788e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127564087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1127564087
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3433987872
Short name T484
Test name
Test status
Simulation time 424375917 ps
CPU time 5.22 seconds
Started Apr 02 01:46:59 PM PDT 24
Finished Apr 02 01:47:04 PM PDT 24
Peak memory 209312 kb
Host smart-12d30da7-d3bb-4df9-9db3-aee5d3d78f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433987872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3433987872
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1841968002
Short name T21
Test name
Test status
Simulation time 232211976 ps
CPU time 5.49 seconds
Started Apr 02 01:47:04 PM PDT 24
Finished Apr 02 01:47:09 PM PDT 24
Peak memory 220728 kb
Host smart-63799fb4-7813-4874-9b4a-0a2459c2bb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841968002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1841968002
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3407347471
Short name T393
Test name
Test status
Simulation time 373478755 ps
CPU time 5.3 seconds
Started Apr 02 01:47:04 PM PDT 24
Finished Apr 02 01:47:10 PM PDT 24
Peak memory 211080 kb
Host smart-aae5c5a4-1aee-4db6-a8ef-d5b236921f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407347471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3407347471
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2370874085
Short name T267
Test name
Test status
Simulation time 464296974 ps
CPU time 3.94 seconds
Started Apr 02 01:47:04 PM PDT 24
Finished Apr 02 01:47:08 PM PDT 24
Peak memory 209996 kb
Host smart-a00ae505-99f9-4dd8-a757-80e0b5b997b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370874085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2370874085
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1940023929
Short name T649
Test name
Test status
Simulation time 1177360693 ps
CPU time 12.3 seconds
Started Apr 02 01:47:00 PM PDT 24
Finished Apr 02 01:47:12 PM PDT 24
Peak memory 209036 kb
Host smart-f39624b9-1a8c-4f15-aeef-7d08c5d2eccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940023929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1940023929
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1185700248
Short name T641
Test name
Test status
Simulation time 455055004 ps
CPU time 2.95 seconds
Started Apr 02 01:46:59 PM PDT 24
Finished Apr 02 01:47:02 PM PDT 24
Peak memory 207088 kb
Host smart-00693dae-1f4d-499a-8e63-6f79964a6627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185700248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1185700248
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3872781452
Short name T134
Test name
Test status
Simulation time 495841577 ps
CPU time 4.54 seconds
Started Apr 02 01:46:58 PM PDT 24
Finished Apr 02 01:47:03 PM PDT 24
Peak memory 207192 kb
Host smart-2e918bb4-ea4f-46f2-b677-9f9be95f8560
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872781452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3872781452
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.962053982
Short name T751
Test name
Test status
Simulation time 365104692 ps
CPU time 2.92 seconds
Started Apr 02 01:47:05 PM PDT 24
Finished Apr 02 01:47:08 PM PDT 24
Peak memory 208920 kb
Host smart-1644c43c-df47-4f8a-a1b3-36875956d15c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962053982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.962053982
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1500744408
Short name T680
Test name
Test status
Simulation time 4322559289 ps
CPU time 23.83 seconds
Started Apr 02 01:47:00 PM PDT 24
Finished Apr 02 01:47:24 PM PDT 24
Peak memory 208224 kb
Host smart-886308b8-2b93-43b5-8a45-58b1e49da76b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500744408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1500744408
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.347691046
Short name T327
Test name
Test status
Simulation time 36614720 ps
CPU time 2.61 seconds
Started Apr 02 01:47:06 PM PDT 24
Finished Apr 02 01:47:08 PM PDT 24
Peak memory 218348 kb
Host smart-1cd03b02-749c-43ba-9f37-a9b65e9e9e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347691046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.347691046
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.779480709
Short name T463
Test name
Test status
Simulation time 5982348861 ps
CPU time 30.73 seconds
Started Apr 02 01:47:01 PM PDT 24
Finished Apr 02 01:47:32 PM PDT 24
Peak memory 208480 kb
Host smart-3e57753a-5370-4205-8ccd-5e34b739cb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779480709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.779480709
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.549639210
Short name T296
Test name
Test status
Simulation time 121763152 ps
CPU time 4.24 seconds
Started Apr 02 01:47:04 PM PDT 24
Finished Apr 02 01:47:09 PM PDT 24
Peak memory 218668 kb
Host smart-1d7dee03-7381-4627-bd68-a51fbb0bcba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549639210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.549639210
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1611046383
Short name T802
Test name
Test status
Simulation time 112396073 ps
CPU time 3.64 seconds
Started Apr 02 01:47:02 PM PDT 24
Finished Apr 02 01:47:06 PM PDT 24
Peak memory 210880 kb
Host smart-60d5a1fe-e30e-4a90-9c8b-2964f9e859ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611046383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1611046383
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3592550798
Short name T441
Test name
Test status
Simulation time 36284940 ps
CPU time 0.75 seconds
Started Apr 02 01:47:13 PM PDT 24
Finished Apr 02 01:47:15 PM PDT 24
Peak memory 206336 kb
Host smart-61e3e57e-2224-4700-a905-44a5b88a6d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592550798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3592550798
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.82672504
Short name T207
Test name
Test status
Simulation time 2490493760 ps
CPU time 16.23 seconds
Started Apr 02 01:47:10 PM PDT 24
Finished Apr 02 01:47:26 PM PDT 24
Peak memory 222920 kb
Host smart-994b8ed1-60eb-4596-a409-8a13bfea6356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82672504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.82672504
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1839766109
Short name T535
Test name
Test status
Simulation time 178427694 ps
CPU time 2.54 seconds
Started Apr 02 01:47:13 PM PDT 24
Finished Apr 02 01:47:16 PM PDT 24
Peak memory 214692 kb
Host smart-949b99c8-fd6c-4fb1-868c-adab043f1e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839766109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1839766109
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.578909091
Short name T892
Test name
Test status
Simulation time 114002865 ps
CPU time 4.08 seconds
Started Apr 02 01:47:11 PM PDT 24
Finished Apr 02 01:47:16 PM PDT 24
Peak memory 208500 kb
Host smart-3064555b-d41f-4dd0-9eba-d8670f9efa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578909091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.578909091
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1840442791
Short name T252
Test name
Test status
Simulation time 277231923 ps
CPU time 3.33 seconds
Started Apr 02 01:47:10 PM PDT 24
Finished Apr 02 01:47:14 PM PDT 24
Peak memory 216480 kb
Host smart-b81a5475-e88f-41f7-a824-cdb8f9252915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840442791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1840442791
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3823472413
Short name T816
Test name
Test status
Simulation time 1493227974 ps
CPU time 6.92 seconds
Started Apr 02 01:47:07 PM PDT 24
Finished Apr 02 01:47:14 PM PDT 24
Peak memory 208588 kb
Host smart-f58b7f27-9686-4ed7-8e11-9d0eaa1700a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823472413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3823472413
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.86315939
Short name T585
Test name
Test status
Simulation time 839395580 ps
CPU time 8.11 seconds
Started Apr 02 01:47:09 PM PDT 24
Finished Apr 02 01:47:17 PM PDT 24
Peak memory 208156 kb
Host smart-eddafa5c-937a-428c-ba9a-b04dec8e0a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86315939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.86315939
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2418602898
Short name T86
Test name
Test status
Simulation time 3556287151 ps
CPU time 34.65 seconds
Started Apr 02 01:47:11 PM PDT 24
Finished Apr 02 01:47:45 PM PDT 24
Peak memory 209332 kb
Host smart-5e8666d1-181c-4eb6-aae3-d8ae676e71d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418602898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2418602898
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2990967425
Short name T880
Test name
Test status
Simulation time 132789335 ps
CPU time 4.39 seconds
Started Apr 02 01:47:11 PM PDT 24
Finished Apr 02 01:47:16 PM PDT 24
Peak memory 209132 kb
Host smart-55310f35-21dd-4a20-9608-5ab06733034c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990967425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2990967425
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1140508220
Short name T814
Test name
Test status
Simulation time 81447150 ps
CPU time 2.46 seconds
Started Apr 02 01:47:08 PM PDT 24
Finished Apr 02 01:47:11 PM PDT 24
Peak memory 208740 kb
Host smart-8958678c-8866-4a92-a61b-0c1fdd2fdf79
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140508220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1140508220
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2255480770
Short name T449
Test name
Test status
Simulation time 39520224 ps
CPU time 2.24 seconds
Started Apr 02 01:47:12 PM PDT 24
Finished Apr 02 01:47:14 PM PDT 24
Peak memory 216192 kb
Host smart-70b24f87-6fd8-4920-b0a7-a5cd9034d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255480770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2255480770
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4267932664
Short name T868
Test name
Test status
Simulation time 729024159 ps
CPU time 2.73 seconds
Started Apr 02 01:47:08 PM PDT 24
Finished Apr 02 01:47:10 PM PDT 24
Peak memory 207256 kb
Host smart-59d89bbd-cef2-4203-953f-7d1dbb796afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267932664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4267932664
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1582257258
Short name T78
Test name
Test status
Simulation time 5022993599 ps
CPU time 41.28 seconds
Started Apr 02 01:47:10 PM PDT 24
Finished Apr 02 01:47:51 PM PDT 24
Peak memory 222972 kb
Host smart-978a7d39-5951-4a2f-ae90-276c31fdba67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582257258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1582257258
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2739639965
Short name T128
Test name
Test status
Simulation time 1385651394 ps
CPU time 22.12 seconds
Started Apr 02 01:47:12 PM PDT 24
Finished Apr 02 01:47:34 PM PDT 24
Peak memory 220660 kb
Host smart-77987f32-6a84-4bb1-86d5-8f84650566ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739639965 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2739639965
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1574635374
Short name T310
Test name
Test status
Simulation time 1786689609 ps
CPU time 31.12 seconds
Started Apr 02 01:47:14 PM PDT 24
Finished Apr 02 01:47:46 PM PDT 24
Peak memory 209484 kb
Host smart-55c5ce28-3949-4037-be26-0850e875c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574635374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1574635374
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3353257170
Short name T113
Test name
Test status
Simulation time 33793531 ps
CPU time 1.64 seconds
Started Apr 02 01:47:13 PM PDT 24
Finished Apr 02 01:47:16 PM PDT 24
Peak memory 210328 kb
Host smart-dc889012-b5a1-45bd-85c7-d478945bc547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353257170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3353257170
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.383467649
Short name T826
Test name
Test status
Simulation time 38607737 ps
CPU time 0.73 seconds
Started Apr 02 01:47:18 PM PDT 24
Finished Apr 02 01:47:19 PM PDT 24
Peak memory 206208 kb
Host smart-0971d66c-7925-49d0-9702-cfc1d0d43d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383467649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.383467649
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.104086326
Short name T357
Test name
Test status
Simulation time 61023346 ps
CPU time 4.65 seconds
Started Apr 02 01:47:13 PM PDT 24
Finished Apr 02 01:47:18 PM PDT 24
Peak memory 214680 kb
Host smart-723c59b4-0c5e-496c-9927-175d0a419d69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104086326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.104086326
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1115427861
Short name T202
Test name
Test status
Simulation time 96210141 ps
CPU time 3.5 seconds
Started Apr 02 01:47:18 PM PDT 24
Finished Apr 02 01:47:22 PM PDT 24
Peak memory 222020 kb
Host smart-e46e857d-f71f-4644-b837-57791808b9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115427861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1115427861
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3629530515
Short name T571
Test name
Test status
Simulation time 41120399 ps
CPU time 2.64 seconds
Started Apr 02 01:47:15 PM PDT 24
Finished Apr 02 01:47:18 PM PDT 24
Peak memory 214636 kb
Host smart-e2b36b7c-b369-42aa-8686-dd668c591aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629530515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3629530515
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.375423842
Short name T241
Test name
Test status
Simulation time 49077787 ps
CPU time 3.06 seconds
Started Apr 02 01:47:15 PM PDT 24
Finished Apr 02 01:47:18 PM PDT 24
Peak memory 214692 kb
Host smart-ed044ac0-1235-4b48-82d1-348293de3265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375423842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.375423842
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4000034700
Short name T6
Test name
Test status
Simulation time 236854822 ps
CPU time 2.37 seconds
Started Apr 02 01:47:17 PM PDT 24
Finished Apr 02 01:47:20 PM PDT 24
Peak memory 220040 kb
Host smart-431509e9-7c4a-46e6-b692-29450dda73e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000034700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4000034700
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1417148214
Short name T660
Test name
Test status
Simulation time 372675798 ps
CPU time 4.73 seconds
Started Apr 02 01:47:14 PM PDT 24
Finished Apr 02 01:47:19 PM PDT 24
Peak memory 210512 kb
Host smart-3a14873b-b403-4c31-abd4-8bb8af602cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417148214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1417148214
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.521720899
Short name T766
Test name
Test status
Simulation time 198359203 ps
CPU time 4.3 seconds
Started Apr 02 01:47:12 PM PDT 24
Finished Apr 02 01:47:17 PM PDT 24
Peak memory 207232 kb
Host smart-fc658ef9-e0cf-4e41-846d-cb088f88e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521720899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.521720899
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.329724739
Short name T824
Test name
Test status
Simulation time 875346728 ps
CPU time 10.7 seconds
Started Apr 02 01:47:13 PM PDT 24
Finished Apr 02 01:47:24 PM PDT 24
Peak memory 208988 kb
Host smart-d5b28f0e-34d0-4a72-b1da-d1985b9a6879
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329724739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.329724739
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3097153059
Short name T812
Test name
Test status
Simulation time 453243494 ps
CPU time 3.05 seconds
Started Apr 02 01:47:14 PM PDT 24
Finished Apr 02 01:47:17 PM PDT 24
Peak memory 208620 kb
Host smart-88e17987-631d-47e6-8ffe-fb70134034c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097153059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3097153059
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1648788434
Short name T442
Test name
Test status
Simulation time 101676617 ps
CPU time 2.2 seconds
Started Apr 02 01:47:15 PM PDT 24
Finished Apr 02 01:47:17 PM PDT 24
Peak memory 207072 kb
Host smart-465c09d6-0a13-408d-a7f7-a85c973dac0a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648788434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1648788434
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3972486114
Short name T283
Test name
Test status
Simulation time 1181074399 ps
CPU time 6.67 seconds
Started Apr 02 01:47:13 PM PDT 24
Finished Apr 02 01:47:21 PM PDT 24
Peak memory 218700 kb
Host smart-0dda50b2-cb7d-4924-b8d6-61920bc5e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972486114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3972486114
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4024383924
Short name T744
Test name
Test status
Simulation time 3189291206 ps
CPU time 29.94 seconds
Started Apr 02 01:47:11 PM PDT 24
Finished Apr 02 01:47:42 PM PDT 24
Peak memory 208648 kb
Host smart-ed64e592-c109-4334-8df4-2f43bd0d70d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024383924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4024383924
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1806919979
Short name T350
Test name
Test status
Simulation time 877874887 ps
CPU time 35.33 seconds
Started Apr 02 01:47:15 PM PDT 24
Finished Apr 02 01:47:51 PM PDT 24
Peak memory 222252 kb
Host smart-12ca738d-2de0-48fd-8b36-f608c4c71b0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806919979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1806919979
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3451782169
Short name T756
Test name
Test status
Simulation time 116893167 ps
CPU time 4.74 seconds
Started Apr 02 01:47:16 PM PDT 24
Finished Apr 02 01:47:22 PM PDT 24
Peak memory 209292 kb
Host smart-df34d184-3629-4a29-9a7e-a557b7a5c4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451782169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3451782169
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.968132474
Short name T213
Test name
Test status
Simulation time 344132914 ps
CPU time 2.37 seconds
Started Apr 02 01:47:14 PM PDT 24
Finished Apr 02 01:47:17 PM PDT 24
Peak memory 210584 kb
Host smart-af3f9d44-0a50-4021-b555-e8ab30c6bf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968132474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.968132474
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4019827130
Short name T838
Test name
Test status
Simulation time 9573671 ps
CPU time 0.79 seconds
Started Apr 02 01:47:22 PM PDT 24
Finished Apr 02 01:47:23 PM PDT 24
Peak memory 206252 kb
Host smart-c819b65a-9b71-476c-a149-6a529e5c2a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019827130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4019827130
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.240834364
Short name T342
Test name
Test status
Simulation time 645917007 ps
CPU time 11.1 seconds
Started Apr 02 01:47:23 PM PDT 24
Finished Apr 02 01:47:35 PM PDT 24
Peak memory 214588 kb
Host smart-26398521-83d5-4221-af12-3a6becc0d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240834364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.240834364
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.798254654
Short name T582
Test name
Test status
Simulation time 699750940 ps
CPU time 8.22 seconds
Started Apr 02 01:47:18 PM PDT 24
Finished Apr 02 01:47:26 PM PDT 24
Peak memory 214608 kb
Host smart-4eb0b7ae-2866-4132-8c35-32ef1b0a5287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798254654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.798254654
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4075504737
Short name T7
Test name
Test status
Simulation time 65473999 ps
CPU time 2.8 seconds
Started Apr 02 01:47:20 PM PDT 24
Finished Apr 02 01:47:23 PM PDT 24
Peak memory 220552 kb
Host smart-fb4a98e6-c125-42e0-be6d-b18438ac728c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075504737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4075504737
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2971310581
Short name T508
Test name
Test status
Simulation time 486615856 ps
CPU time 4.54 seconds
Started Apr 02 01:47:23 PM PDT 24
Finished Apr 02 01:47:29 PM PDT 24
Peak memory 218780 kb
Host smart-841447f9-a1ac-415c-807f-e27d6c0ecdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971310581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2971310581
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2027846240
Short name T819
Test name
Test status
Simulation time 104490876 ps
CPU time 4.17 seconds
Started Apr 02 01:47:23 PM PDT 24
Finished Apr 02 01:47:29 PM PDT 24
Peak memory 208692 kb
Host smart-94cafc94-eadc-49c3-9025-e066d3af95a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027846240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2027846240
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4072424902
Short name T704
Test name
Test status
Simulation time 1045938843 ps
CPU time 5.95 seconds
Started Apr 02 01:47:18 PM PDT 24
Finished Apr 02 01:47:25 PM PDT 24
Peak memory 208936 kb
Host smart-a2062ce9-55f9-489f-8adf-a9c11f2f24c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072424902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4072424902
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2997498935
Short name T464
Test name
Test status
Simulation time 32730156 ps
CPU time 2.32 seconds
Started Apr 02 01:47:19 PM PDT 24
Finished Apr 02 01:47:22 PM PDT 24
Peak memory 207140 kb
Host smart-0a7f1b4a-ecbd-4020-926a-5ab4d7f5c29d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997498935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2997498935
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.60887543
Short name T355
Test name
Test status
Simulation time 432547925 ps
CPU time 3.21 seconds
Started Apr 02 01:47:20 PM PDT 24
Finished Apr 02 01:47:23 PM PDT 24
Peak memory 208776 kb
Host smart-a4ee5cc3-08e1-4c0e-acb3-cf76313f0534
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60887543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.60887543
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1961452234
Short name T194
Test name
Test status
Simulation time 274408163 ps
CPU time 3.22 seconds
Started Apr 02 01:47:19 PM PDT 24
Finished Apr 02 01:47:23 PM PDT 24
Peak memory 218672 kb
Host smart-2cc8c6b7-5ec4-4929-9f37-e2055c7b0ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961452234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1961452234
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2681800991
Short name T703
Test name
Test status
Simulation time 99473018 ps
CPU time 2.74 seconds
Started Apr 02 01:47:17 PM PDT 24
Finished Apr 02 01:47:20 PM PDT 24
Peak memory 207016 kb
Host smart-76a167c4-046f-4d9a-ac57-50d19ca4a837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681800991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2681800991
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3597262319
Short name T160
Test name
Test status
Simulation time 142713828 ps
CPU time 3.35 seconds
Started Apr 02 01:47:23 PM PDT 24
Finished Apr 02 01:47:27 PM PDT 24
Peak memory 207748 kb
Host smart-c80a4321-a03a-4b07-9e8a-7422b89b807e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597262319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3597262319
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.461498891
Short name T516
Test name
Test status
Simulation time 6400613037 ps
CPU time 56.43 seconds
Started Apr 02 01:47:18 PM PDT 24
Finished Apr 02 01:48:15 PM PDT 24
Peak memory 219208 kb
Host smart-36544dd9-207a-44f2-babe-7645ab0a788e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461498891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.461498891
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1015396861
Short name T195
Test name
Test status
Simulation time 82025861 ps
CPU time 2.66 seconds
Started Apr 02 01:47:19 PM PDT 24
Finished Apr 02 01:47:22 PM PDT 24
Peak memory 210408 kb
Host smart-61200808-b546-4e27-9afa-63fe00e75bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015396861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1015396861
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.251378273
Short name T591
Test name
Test status
Simulation time 85411283 ps
CPU time 0.85 seconds
Started Apr 02 01:47:24 PM PDT 24
Finished Apr 02 01:47:26 PM PDT 24
Peak memory 206200 kb
Host smart-d6b4fa44-1f1b-4d3b-b738-39d04ebde4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251378273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.251378273
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.892542257
Short name T332
Test name
Test status
Simulation time 230366146 ps
CPU time 3.64 seconds
Started Apr 02 01:47:20 PM PDT 24
Finished Apr 02 01:47:25 PM PDT 24
Peak memory 221976 kb
Host smart-1ed6c183-8636-49d0-9475-e7beec758c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892542257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.892542257
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.677109691
Short name T471
Test name
Test status
Simulation time 65780224 ps
CPU time 1.34 seconds
Started Apr 02 01:47:21 PM PDT 24
Finished Apr 02 01:47:22 PM PDT 24
Peak memory 207344 kb
Host smart-7bb7b99a-eef9-4e39-b098-4f5ff5531bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677109691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.677109691
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1782039362
Short name T298
Test name
Test status
Simulation time 174841241 ps
CPU time 3.19 seconds
Started Apr 02 01:47:21 PM PDT 24
Finished Apr 02 01:47:25 PM PDT 24
Peak memory 214684 kb
Host smart-f3aac668-7747-4f60-b442-b04ef12aae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782039362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1782039362
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3211186982
Short name T331
Test name
Test status
Simulation time 349618015 ps
CPU time 10.03 seconds
Started Apr 02 01:47:21 PM PDT 24
Finished Apr 02 01:47:32 PM PDT 24
Peak memory 222788 kb
Host smart-23b819b8-a444-4a6d-96e6-bbea83a36ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211186982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3211186982
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.797341439
Short name T54
Test name
Test status
Simulation time 531626403 ps
CPU time 4.45 seconds
Started Apr 02 01:47:20 PM PDT 24
Finished Apr 02 01:47:25 PM PDT 24
Peak memory 220688 kb
Host smart-dd6b3695-b773-49e7-894d-f3d412ac4442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797341439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.797341439
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1105948006
Short name T689
Test name
Test status
Simulation time 51163479 ps
CPU time 2.21 seconds
Started Apr 02 01:47:22 PM PDT 24
Finished Apr 02 01:47:25 PM PDT 24
Peak memory 207888 kb
Host smart-7973e122-6172-4af4-83cf-76208998d996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105948006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1105948006
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2801111952
Short name T309
Test name
Test status
Simulation time 155813502 ps
CPU time 2.79 seconds
Started Apr 02 01:47:23 PM PDT 24
Finished Apr 02 01:47:27 PM PDT 24
Peak memory 209072 kb
Host smart-d27ddd2b-5da3-4a99-9de7-bb8c43424821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801111952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2801111952
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.4131320036
Short name T593
Test name
Test status
Simulation time 423368093 ps
CPU time 2.11 seconds
Started Apr 02 01:47:21 PM PDT 24
Finished Apr 02 01:47:24 PM PDT 24
Peak memory 209060 kb
Host smart-2977c59f-8a45-4d06-b0a0-79f37a8eb751
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131320036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4131320036
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3446917677
Short name T654
Test name
Test status
Simulation time 217733605 ps
CPU time 2.99 seconds
Started Apr 02 01:47:21 PM PDT 24
Finished Apr 02 01:47:25 PM PDT 24
Peak memory 207612 kb
Host smart-8c0d8f7e-a6e1-4d04-8096-312a37687915
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446917677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3446917677
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2475358544
Short name T753
Test name
Test status
Simulation time 447185582 ps
CPU time 11.57 seconds
Started Apr 02 01:47:24 PM PDT 24
Finished Apr 02 01:47:36 PM PDT 24
Peak memory 208336 kb
Host smart-181d6995-96a5-4808-9ec4-71d2e6008cac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475358544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2475358544
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2605544409
Short name T872
Test name
Test status
Simulation time 146356281 ps
CPU time 1.9 seconds
Started Apr 02 01:47:22 PM PDT 24
Finished Apr 02 01:47:24 PM PDT 24
Peak memory 207672 kb
Host smart-c1a2fe08-e7fd-474d-b561-91ffecf7cb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605544409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2605544409
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.584770785
Short name T444
Test name
Test status
Simulation time 129333525 ps
CPU time 4.33 seconds
Started Apr 02 01:47:22 PM PDT 24
Finished Apr 02 01:47:27 PM PDT 24
Peak memory 208384 kb
Host smart-58b958c2-b9df-41cb-80a4-c6bc18a9945c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584770785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.584770785
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2762143036
Short name T836
Test name
Test status
Simulation time 1123682569 ps
CPU time 8.45 seconds
Started Apr 02 01:47:21 PM PDT 24
Finished Apr 02 01:47:31 PM PDT 24
Peak memory 214620 kb
Host smart-5d394dc1-cd01-4368-be7d-000718882126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762143036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2762143036
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3547749988
Short name T488
Test name
Test status
Simulation time 266056276 ps
CPU time 3.04 seconds
Started Apr 02 01:47:22 PM PDT 24
Finished Apr 02 01:47:26 PM PDT 24
Peak memory 210336 kb
Host smart-32915295-80d2-4df4-93e7-0e2131bf03bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547749988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3547749988
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.331803926
Short name T781
Test name
Test status
Simulation time 44615372 ps
CPU time 0.79 seconds
Started Apr 02 01:47:33 PM PDT 24
Finished Apr 02 01:47:34 PM PDT 24
Peak memory 206288 kb
Host smart-b772bd2a-bdb7-429e-8195-8131cb1ec313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331803926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.331803926
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2310475474
Short name T426
Test name
Test status
Simulation time 321565604 ps
CPU time 17 seconds
Started Apr 02 01:47:26 PM PDT 24
Finished Apr 02 01:47:43 PM PDT 24
Peak memory 215888 kb
Host smart-46c55395-63ae-49bf-a69e-7a39a5227944
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310475474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2310475474
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3315936119
Short name T604
Test name
Test status
Simulation time 493496457 ps
CPU time 4.81 seconds
Started Apr 02 01:47:23 PM PDT 24
Finished Apr 02 01:47:29 PM PDT 24
Peak memory 214576 kb
Host smart-429626a7-fbc4-4176-9fae-aaef8fe951d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315936119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3315936119
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1795296966
Short name T337
Test name
Test status
Simulation time 1596293704 ps
CPU time 17.62 seconds
Started Apr 02 01:47:24 PM PDT 24
Finished Apr 02 01:47:43 PM PDT 24
Peak memory 222088 kb
Host smart-b98556ce-b88c-4f43-9bd2-f22989dda362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795296966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1795296966
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.156869249
Short name T278
Test name
Test status
Simulation time 361212655 ps
CPU time 4.83 seconds
Started Apr 02 01:47:25 PM PDT 24
Finished Apr 02 01:47:30 PM PDT 24
Peak memory 211492 kb
Host smart-0d95a321-b424-43f1-8916-b00134b8e8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156869249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.156869249
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1751990040
Short name T64
Test name
Test status
Simulation time 178622233 ps
CPU time 4.2 seconds
Started Apr 02 01:47:23 PM PDT 24
Finished Apr 02 01:47:28 PM PDT 24
Peak memory 221028 kb
Host smart-cd38433a-8784-461b-8a81-851a8a72ee64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751990040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1751990040
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3588941721
Short name T286
Test name
Test status
Simulation time 786838994 ps
CPU time 5.93 seconds
Started Apr 02 01:47:22 PM PDT 24
Finished Apr 02 01:47:28 PM PDT 24
Peak memory 209348 kb
Host smart-312d802e-8718-4998-b91e-8e8673b8c89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588941721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3588941721
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.4030814417
Short name T714
Test name
Test status
Simulation time 80177126 ps
CPU time 2.79 seconds
Started Apr 02 01:47:25 PM PDT 24
Finished Apr 02 01:47:28 PM PDT 24
Peak memory 206904 kb
Host smart-5cbe01c8-8d37-4d54-ad73-049bb2dc1e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030814417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4030814417
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1642998665
Short name T473
Test name
Test status
Simulation time 71740530 ps
CPU time 2.92 seconds
Started Apr 02 01:47:23 PM PDT 24
Finished Apr 02 01:47:27 PM PDT 24
Peak memory 207196 kb
Host smart-d002f33b-66e7-4830-984f-e1b3f1558cb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642998665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1642998665
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3485287094
Short name T683
Test name
Test status
Simulation time 1162207662 ps
CPU time 6.57 seconds
Started Apr 02 01:47:26 PM PDT 24
Finished Apr 02 01:47:33 PM PDT 24
Peak memory 208688 kb
Host smart-eba235fd-6800-4b70-95b6-c32259267300
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485287094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3485287094
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4208909248
Short name T495
Test name
Test status
Simulation time 100132309 ps
CPU time 2.96 seconds
Started Apr 02 01:47:24 PM PDT 24
Finished Apr 02 01:47:28 PM PDT 24
Peak memory 209112 kb
Host smart-f92fc4de-0587-48a1-a775-1c2385511b1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208909248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4208909248
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2411806008
Short name T430
Test name
Test status
Simulation time 128106504 ps
CPU time 4.96 seconds
Started Apr 02 01:47:28 PM PDT 24
Finished Apr 02 01:47:33 PM PDT 24
Peak memory 214640 kb
Host smart-f6efbc22-eb96-44ba-b78e-ef681c1f62ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411806008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2411806008
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.408812443
Short name T235
Test name
Test status
Simulation time 66231147 ps
CPU time 2.34 seconds
Started Apr 02 01:47:26 PM PDT 24
Finished Apr 02 01:47:29 PM PDT 24
Peak memory 206848 kb
Host smart-36c36654-cd14-42d8-a93d-8e239c50875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408812443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.408812443
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3821755236
Short name T610
Test name
Test status
Simulation time 1149872679 ps
CPU time 39.18 seconds
Started Apr 02 01:47:34 PM PDT 24
Finished Apr 02 01:48:13 PM PDT 24
Peak memory 222880 kb
Host smart-945af330-4e3c-47d4-b0f9-afaf0d849ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821755236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3821755236
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2107473816
Short name T723
Test name
Test status
Simulation time 147713315 ps
CPU time 2.85 seconds
Started Apr 02 01:47:25 PM PDT 24
Finished Apr 02 01:47:28 PM PDT 24
Peak memory 207176 kb
Host smart-75f7f1cf-b320-4395-95a5-07a670222814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107473816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2107473816
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3484270945
Short name T158
Test name
Test status
Simulation time 411603596 ps
CPU time 10.19 seconds
Started Apr 02 01:47:30 PM PDT 24
Finished Apr 02 01:47:41 PM PDT 24
Peak memory 211348 kb
Host smart-050a2f11-32c6-47d6-b8f1-7d4c210a6c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484270945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3484270945
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1241187377
Short name T451
Test name
Test status
Simulation time 61328863 ps
CPU time 0.8 seconds
Started Apr 02 01:47:37 PM PDT 24
Finished Apr 02 01:47:38 PM PDT 24
Peak memory 206260 kb
Host smart-9c156765-e338-4077-9961-d456b6c37a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241187377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1241187377
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.731937516
Short name T196
Test name
Test status
Simulation time 206535476 ps
CPU time 3.79 seconds
Started Apr 02 01:47:26 PM PDT 24
Finished Apr 02 01:47:30 PM PDT 24
Peak memory 215704 kb
Host smart-11adb11c-93d1-410c-bad4-7779bb9d403d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731937516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.731937516
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3044662576
Short name T780
Test name
Test status
Simulation time 312377906 ps
CPU time 11.03 seconds
Started Apr 02 01:47:32 PM PDT 24
Finished Apr 02 01:47:43 PM PDT 24
Peak memory 210072 kb
Host smart-774f42fd-1ddd-4810-a545-d19458407e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044662576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3044662576
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.844572347
Short name T414
Test name
Test status
Simulation time 201984945 ps
CPU time 3.28 seconds
Started Apr 02 01:47:33 PM PDT 24
Finished Apr 02 01:47:37 PM PDT 24
Peak memory 210100 kb
Host smart-6ac7fb31-526d-465f-8488-3ecbbad6d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844572347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.844572347
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3066098334
Short name T724
Test name
Test status
Simulation time 57223066 ps
CPU time 3.65 seconds
Started Apr 02 01:47:30 PM PDT 24
Finished Apr 02 01:47:34 PM PDT 24
Peak memory 219968 kb
Host smart-0405a5b8-94cc-4933-98e5-9d41f0fad1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066098334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3066098334
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2518638356
Short name T217
Test name
Test status
Simulation time 50726565 ps
CPU time 3.19 seconds
Started Apr 02 01:47:35 PM PDT 24
Finished Apr 02 01:47:39 PM PDT 24
Peak memory 208532 kb
Host smart-d1112ad4-8484-4af2-b083-cad1f33a3419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518638356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2518638356
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.875555445
Short name T428
Test name
Test status
Simulation time 318084651 ps
CPU time 3.89 seconds
Started Apr 02 01:47:33 PM PDT 24
Finished Apr 02 01:47:37 PM PDT 24
Peak memory 207808 kb
Host smart-b4821751-ccfe-45b6-97ac-5a0ea73d09c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875555445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.875555445
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1715376851
Short name T489
Test name
Test status
Simulation time 141903870 ps
CPU time 2.84 seconds
Started Apr 02 01:47:33 PM PDT 24
Finished Apr 02 01:47:36 PM PDT 24
Peak memory 207064 kb
Host smart-71ea541d-bc98-4cc9-a19b-1622c6bfe654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715376851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1715376851
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3499310957
Short name T333
Test name
Test status
Simulation time 210984431 ps
CPU time 6.51 seconds
Started Apr 02 01:47:30 PM PDT 24
Finished Apr 02 01:47:37 PM PDT 24
Peak memory 209064 kb
Host smart-1323c8a2-4a5c-42d9-bc54-ef47f42295d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499310957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3499310957
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3573698120
Short name T764
Test name
Test status
Simulation time 164700724 ps
CPU time 3.84 seconds
Started Apr 02 01:47:29 PM PDT 24
Finished Apr 02 01:47:33 PM PDT 24
Peak memory 208844 kb
Host smart-88c34cbb-5ede-4500-adf2-e1ff4d0ea244
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573698120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3573698120
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3891475095
Short name T490
Test name
Test status
Simulation time 30495042 ps
CPU time 2.45 seconds
Started Apr 02 01:47:31 PM PDT 24
Finished Apr 02 01:47:33 PM PDT 24
Peak memory 209204 kb
Host smart-391a21fd-19d7-43c7-9814-378c5293702f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891475095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3891475095
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4118315242
Short name T568
Test name
Test status
Simulation time 38788666 ps
CPU time 2.63 seconds
Started Apr 02 01:47:28 PM PDT 24
Finished Apr 02 01:47:30 PM PDT 24
Peak memory 209448 kb
Host smart-1e1a14dd-3e6e-40e8-9b46-bc776cb34864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118315242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4118315242
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1536014437
Short name T238
Test name
Test status
Simulation time 388677385 ps
CPU time 3.21 seconds
Started Apr 02 01:47:30 PM PDT 24
Finished Apr 02 01:47:33 PM PDT 24
Peak memory 209044 kb
Host smart-54264056-e870-4090-907c-595c6ba61ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536014437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1536014437
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1565475085
Short name T219
Test name
Test status
Simulation time 881614149 ps
CPU time 33.46 seconds
Started Apr 02 01:47:32 PM PDT 24
Finished Apr 02 01:48:06 PM PDT 24
Peak memory 216692 kb
Host smart-fdb5f4dd-cb8c-40b0-a05f-fa853f0aa1b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565475085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1565475085
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2087115494
Short name T326
Test name
Test status
Simulation time 200551556 ps
CPU time 2.91 seconds
Started Apr 02 01:47:31 PM PDT 24
Finished Apr 02 01:47:34 PM PDT 24
Peak memory 207780 kb
Host smart-ddc29d1a-7421-4f16-b0b8-4067f0287ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087115494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2087115494
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3297810304
Short name T621
Test name
Test status
Simulation time 278612541 ps
CPU time 2.14 seconds
Started Apr 02 01:47:32 PM PDT 24
Finished Apr 02 01:47:34 PM PDT 24
Peak memory 210544 kb
Host smart-de23183a-3304-4e4c-a4a8-f2e5dcd52701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297810304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3297810304
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.430552852
Short name T690
Test name
Test status
Simulation time 8861614 ps
CPU time 0.79 seconds
Started Apr 02 01:47:38 PM PDT 24
Finished Apr 02 01:47:39 PM PDT 24
Peak memory 206332 kb
Host smart-5b88aa74-119e-495a-8e9f-ce778269c4d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430552852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.430552852
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2009837069
Short name T435
Test name
Test status
Simulation time 165273984 ps
CPU time 8.51 seconds
Started Apr 02 01:47:38 PM PDT 24
Finished Apr 02 01:47:47 PM PDT 24
Peak memory 214640 kb
Host smart-097a3e7f-833a-4572-8936-d35525974275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009837069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2009837069
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2853455915
Short name T256
Test name
Test status
Simulation time 2360384020 ps
CPU time 9.19 seconds
Started Apr 02 01:47:35 PM PDT 24
Finished Apr 02 01:47:44 PM PDT 24
Peak memory 217928 kb
Host smart-dc527dbb-38c2-4a62-9361-70f3288a6a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853455915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2853455915
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3753524358
Short name T77
Test name
Test status
Simulation time 52493063 ps
CPU time 2.42 seconds
Started Apr 02 01:47:34 PM PDT 24
Finished Apr 02 01:47:37 PM PDT 24
Peak memory 209016 kb
Host smart-f7e73704-5c46-4366-a8d5-bc22492ec306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753524358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3753524358
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3245533205
Short name T90
Test name
Test status
Simulation time 76230663 ps
CPU time 2.81 seconds
Started Apr 02 01:47:36 PM PDT 24
Finished Apr 02 01:47:40 PM PDT 24
Peak memory 214684 kb
Host smart-0b363179-38e9-4b82-8f5c-f990980d606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245533205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3245533205
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2336326937
Short name T250
Test name
Test status
Simulation time 63747493 ps
CPU time 2.91 seconds
Started Apr 02 01:47:37 PM PDT 24
Finished Apr 02 01:47:41 PM PDT 24
Peak memory 210300 kb
Host smart-5060850a-e0c0-4173-bd51-c682cbd6d6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336326937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2336326937
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2577377545
Short name T657
Test name
Test status
Simulation time 1225848006 ps
CPU time 11.23 seconds
Started Apr 02 01:47:33 PM PDT 24
Finished Apr 02 01:47:45 PM PDT 24
Peak memory 209024 kb
Host smart-9b09c5d1-289c-4fd6-9a94-51e1e60cc0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577377545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2577377545
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.310415116
Short name T570
Test name
Test status
Simulation time 128600799 ps
CPU time 2.55 seconds
Started Apr 02 01:47:34 PM PDT 24
Finished Apr 02 01:47:37 PM PDT 24
Peak memory 208924 kb
Host smart-df76bbcf-b13f-4b94-b6bb-52fda4946f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310415116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.310415116
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2046438006
Short name T576
Test name
Test status
Simulation time 627646872 ps
CPU time 3.61 seconds
Started Apr 02 01:47:33 PM PDT 24
Finished Apr 02 01:47:36 PM PDT 24
Peak memory 207220 kb
Host smart-7a674650-f8ed-4070-8630-f5625753d17d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046438006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2046438006
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1431274690
Short name T366
Test name
Test status
Simulation time 28599240 ps
CPU time 2.06 seconds
Started Apr 02 01:47:39 PM PDT 24
Finished Apr 02 01:47:41 PM PDT 24
Peak memory 208960 kb
Host smart-006ec1be-1186-4a3b-9b83-4e6b0ca73f8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431274690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1431274690
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2639267919
Short name T765
Test name
Test status
Simulation time 142448719 ps
CPU time 4.38 seconds
Started Apr 02 01:47:33 PM PDT 24
Finished Apr 02 01:47:38 PM PDT 24
Peak memory 207008 kb
Host smart-0a472ea7-b567-4476-9a62-04cb94b47608
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639267919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2639267919
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2574425732
Short name T643
Test name
Test status
Simulation time 82867022 ps
CPU time 2.9 seconds
Started Apr 02 01:47:35 PM PDT 24
Finished Apr 02 01:47:38 PM PDT 24
Peak memory 208812 kb
Host smart-311ffbfb-7b8a-499b-99ee-d5fbf126ce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574425732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2574425732
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3431869687
Short name T526
Test name
Test status
Simulation time 189760635 ps
CPU time 2.68 seconds
Started Apr 02 01:47:35 PM PDT 24
Finished Apr 02 01:47:38 PM PDT 24
Peak memory 207128 kb
Host smart-bb566c29-3c07-4f2a-9d98-e9a88e245bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431869687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3431869687
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3717822088
Short name T80
Test name
Test status
Simulation time 2044086087 ps
CPU time 26.48 seconds
Started Apr 02 01:47:37 PM PDT 24
Finished Apr 02 01:48:03 PM PDT 24
Peak memory 216220 kb
Host smart-d3f276cb-7d55-4b3d-80f9-2b8c0556ff4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717822088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3717822088
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4252173673
Short name T35
Test name
Test status
Simulation time 306310141 ps
CPU time 7.02 seconds
Started Apr 02 01:47:33 PM PDT 24
Finished Apr 02 01:47:40 PM PDT 24
Peak memory 208228 kb
Host smart-c6a289b2-989a-4203-86b0-9498659510fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252173673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4252173673
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2320054364
Short name T56
Test name
Test status
Simulation time 211105982 ps
CPU time 3.95 seconds
Started Apr 02 01:47:32 PM PDT 24
Finished Apr 02 01:47:37 PM PDT 24
Peak memory 210628 kb
Host smart-9ed11ff0-6220-49e3-9463-9c9c49c49eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320054364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2320054364
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3473058325
Short name T437
Test name
Test status
Simulation time 9559144 ps
CPU time 0.81 seconds
Started Apr 02 01:47:42 PM PDT 24
Finished Apr 02 01:47:43 PM PDT 24
Peak memory 206324 kb
Host smart-f0796b90-7dfe-4c68-b571-9a2a32088281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473058325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3473058325
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1872998118
Short name T32
Test name
Test status
Simulation time 7341083897 ps
CPU time 51.42 seconds
Started Apr 02 01:47:43 PM PDT 24
Finished Apr 02 01:48:35 PM PDT 24
Peak memory 218936 kb
Host smart-5e5965af-1fed-44ad-9826-de356d0acb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872998118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1872998118
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2143105665
Short name T411
Test name
Test status
Simulation time 61619080 ps
CPU time 2.23 seconds
Started Apr 02 01:47:40 PM PDT 24
Finished Apr 02 01:47:42 PM PDT 24
Peak memory 210648 kb
Host smart-1d96ea1a-ca93-46c6-8862-494df3beccaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143105665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2143105665
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3248605356
Short name T716
Test name
Test status
Simulation time 85734948 ps
CPU time 3.01 seconds
Started Apr 02 01:47:41 PM PDT 24
Finished Apr 02 01:47:44 PM PDT 24
Peak memory 210000 kb
Host smart-407ebfb1-cd3e-4283-a2b3-6669bcaefb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248605356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3248605356
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2912875190
Short name T562
Test name
Test status
Simulation time 178965379 ps
CPU time 3.28 seconds
Started Apr 02 01:47:42 PM PDT 24
Finished Apr 02 01:47:45 PM PDT 24
Peak memory 208484 kb
Host smart-0203234d-1b6e-4bd5-9f5e-c787fa4d191c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912875190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2912875190
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3826549461
Short name T538
Test name
Test status
Simulation time 297934889 ps
CPU time 4.11 seconds
Started Apr 02 01:47:38 PM PDT 24
Finished Apr 02 01:47:42 PM PDT 24
Peak memory 208044 kb
Host smart-67a1ab1d-fb58-47d9-8871-78852eac0eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826549461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3826549461
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1843261823
Short name T684
Test name
Test status
Simulation time 106905433 ps
CPU time 3.18 seconds
Started Apr 02 01:47:38 PM PDT 24
Finished Apr 02 01:47:41 PM PDT 24
Peak memory 208820 kb
Host smart-379eb421-8825-4506-bb71-686f052288bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843261823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1843261823
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3679902121
Short name T720
Test name
Test status
Simulation time 76043180 ps
CPU time 2.44 seconds
Started Apr 02 01:47:38 PM PDT 24
Finished Apr 02 01:47:40 PM PDT 24
Peak memory 207132 kb
Host smart-814e34f9-ea9b-4828-972c-0a337f9753b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679902121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3679902121
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4183041479
Short name T244
Test name
Test status
Simulation time 184279262 ps
CPU time 2.45 seconds
Started Apr 02 01:47:35 PM PDT 24
Finished Apr 02 01:47:37 PM PDT 24
Peak memory 207264 kb
Host smart-07e3e645-f3ce-46a1-a371-0f10dc33d989
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183041479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4183041479
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3628445620
Short name T15
Test name
Test status
Simulation time 117721902 ps
CPU time 4.5 seconds
Started Apr 02 01:47:36 PM PDT 24
Finished Apr 02 01:47:41 PM PDT 24
Peak memory 208732 kb
Host smart-c78b5a6e-273c-45eb-91af-0113c02b8431
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628445620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3628445620
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3920369535
Short name T554
Test name
Test status
Simulation time 211039353 ps
CPU time 3.2 seconds
Started Apr 02 01:47:40 PM PDT 24
Finished Apr 02 01:47:43 PM PDT 24
Peak memory 209268 kb
Host smart-8757204a-bd21-4d39-9a7c-66d4b1cb5bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920369535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3920369535
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2716552809
Short name T18
Test name
Test status
Simulation time 1205341758 ps
CPU time 11.17 seconds
Started Apr 02 01:47:39 PM PDT 24
Finished Apr 02 01:47:51 PM PDT 24
Peak memory 207032 kb
Host smart-f37f7b64-b885-4ec9-a0b8-9a2186d12403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716552809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2716552809
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.630685315
Short name T362
Test name
Test status
Simulation time 1765675405 ps
CPU time 42.85 seconds
Started Apr 02 01:47:42 PM PDT 24
Finished Apr 02 01:48:25 PM PDT 24
Peak memory 217976 kb
Host smart-be96baa2-81ac-478b-8a3e-0164d97e3f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630685315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.630685315
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2556845326
Short name T289
Test name
Test status
Simulation time 206358139 ps
CPU time 3.89 seconds
Started Apr 02 01:47:40 PM PDT 24
Finished Apr 02 01:47:44 PM PDT 24
Peak memory 218652 kb
Host smart-8ae40eb8-7132-4c16-99e5-162a0788533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556845326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2556845326
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2080317851
Short name T771
Test name
Test status
Simulation time 70422344 ps
CPU time 2.95 seconds
Started Apr 02 01:47:43 PM PDT 24
Finished Apr 02 01:47:46 PM PDT 24
Peak memory 210192 kb
Host smart-2e6330af-d564-4974-a63e-c8fa81ab491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080317851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2080317851
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1301401697
Short name T752
Test name
Test status
Simulation time 44674661 ps
CPU time 0.82 seconds
Started Apr 02 01:47:47 PM PDT 24
Finished Apr 02 01:47:48 PM PDT 24
Peak memory 206236 kb
Host smart-f3d7a54e-6f2e-4360-a150-787643064962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301401697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1301401697
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2825046517
Short name T251
Test name
Test status
Simulation time 435193385 ps
CPU time 2.9 seconds
Started Apr 02 01:47:47 PM PDT 24
Finished Apr 02 01:47:51 PM PDT 24
Peak memory 223068 kb
Host smart-862d9c0f-645a-4764-b973-94ecf9b4911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825046517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2825046517
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.4199059450
Short name T502
Test name
Test status
Simulation time 47111728 ps
CPU time 2.33 seconds
Started Apr 02 01:47:42 PM PDT 24
Finished Apr 02 01:47:45 PM PDT 24
Peak memory 208844 kb
Host smart-ed271da3-21c7-4ac4-8cba-c1875e030a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199059450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.4199059450
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.961385138
Short name T336
Test name
Test status
Simulation time 373182573 ps
CPU time 5.59 seconds
Started Apr 02 01:47:43 PM PDT 24
Finished Apr 02 01:47:49 PM PDT 24
Peak memory 214676 kb
Host smart-87dbb425-5c42-41cf-83fb-c1a3873633a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961385138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.961385138
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.774651714
Short name T208
Test name
Test status
Simulation time 96391827 ps
CPU time 4.07 seconds
Started Apr 02 01:47:49 PM PDT 24
Finished Apr 02 01:47:53 PM PDT 24
Peak memory 214560 kb
Host smart-bd844128-07b9-499b-89f7-446e17ed8aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774651714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.774651714
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1457432537
Short name T40
Test name
Test status
Simulation time 762759807 ps
CPU time 4.82 seconds
Started Apr 02 01:47:43 PM PDT 24
Finished Apr 02 01:47:48 PM PDT 24
Peak memory 222772 kb
Host smart-5690e899-10bd-4d32-ba58-cb19ed54caa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457432537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1457432537
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2091588351
Short name T722
Test name
Test status
Simulation time 421057489 ps
CPU time 4.74 seconds
Started Apr 02 01:47:43 PM PDT 24
Finished Apr 02 01:47:48 PM PDT 24
Peak memory 209748 kb
Host smart-956170bf-2b73-4573-8214-31d21419fb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091588351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2091588351
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.63033985
Short name T236
Test name
Test status
Simulation time 63432153 ps
CPU time 3.24 seconds
Started Apr 02 01:47:42 PM PDT 24
Finished Apr 02 01:47:46 PM PDT 24
Peak memory 208616 kb
Host smart-87294553-80b6-4276-b432-7dcc845ba197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63033985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.63033985
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3743191966
Short name T870
Test name
Test status
Simulation time 54301919 ps
CPU time 2.89 seconds
Started Apr 02 01:47:43 PM PDT 24
Finished Apr 02 01:47:46 PM PDT 24
Peak memory 207160 kb
Host smart-36e54297-af21-4ae9-b3a7-35571f92bd8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743191966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3743191966
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3507994169
Short name T561
Test name
Test status
Simulation time 505432443 ps
CPU time 4.39 seconds
Started Apr 02 01:47:43 PM PDT 24
Finished Apr 02 01:47:48 PM PDT 24
Peak memory 209240 kb
Host smart-9a24da5f-936c-442d-ba6d-62674868efd0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507994169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3507994169
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.725659177
Short name T770
Test name
Test status
Simulation time 572614434 ps
CPU time 5.03 seconds
Started Apr 02 01:47:44 PM PDT 24
Finished Apr 02 01:47:49 PM PDT 24
Peak memory 207020 kb
Host smart-738f54b8-0439-48f2-a34d-141b2e26a00a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725659177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.725659177
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3532683702
Short name T886
Test name
Test status
Simulation time 119398561 ps
CPU time 3.82 seconds
Started Apr 02 01:47:46 PM PDT 24
Finished Apr 02 01:47:50 PM PDT 24
Peak memory 210000 kb
Host smart-b86498d7-8f12-4285-bfbd-52640fc2afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532683702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3532683702
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2279202026
Short name T514
Test name
Test status
Simulation time 48820222 ps
CPU time 2.58 seconds
Started Apr 02 01:47:39 PM PDT 24
Finished Apr 02 01:47:42 PM PDT 24
Peak memory 208508 kb
Host smart-d834618e-91d5-4f8d-bd56-5368178db059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279202026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2279202026
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.4160881865
Short name T732
Test name
Test status
Simulation time 418494131 ps
CPU time 4.76 seconds
Started Apr 02 01:47:44 PM PDT 24
Finished Apr 02 01:47:49 PM PDT 24
Peak memory 210000 kb
Host smart-277cde08-cab0-4a4f-ae83-0a1659941b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160881865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4160881865
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2742259296
Short name T57
Test name
Test status
Simulation time 96764879 ps
CPU time 2.76 seconds
Started Apr 02 01:47:46 PM PDT 24
Finished Apr 02 01:47:49 PM PDT 24
Peak memory 210612 kb
Host smart-1b567d50-a77b-48d7-892e-f3cadca1fef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742259296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2742259296
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1869737881
Short name T775
Test name
Test status
Simulation time 13875257 ps
CPU time 0.76 seconds
Started Apr 02 01:42:38 PM PDT 24
Finished Apr 02 01:42:39 PM PDT 24
Peak memory 206296 kb
Host smart-0f699509-0172-43f2-82ca-cfa2f90cce87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869737881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1869737881
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.4001461858
Short name T151
Test name
Test status
Simulation time 237760559 ps
CPU time 4.22 seconds
Started Apr 02 01:42:26 PM PDT 24
Finished Apr 02 01:42:30 PM PDT 24
Peak memory 214592 kb
Host smart-9ef786d8-e380-4817-aa68-afb988ebe087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4001461858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.4001461858
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3818545867
Short name T19
Test name
Test status
Simulation time 120803163 ps
CPU time 2.01 seconds
Started Apr 02 01:42:28 PM PDT 24
Finished Apr 02 01:42:30 PM PDT 24
Peak memory 221132 kb
Host smart-1fdd3102-241f-44f5-9278-f9a80bcd919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818545867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3818545867
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3825313654
Short name T737
Test name
Test status
Simulation time 154228902 ps
CPU time 4.59 seconds
Started Apr 02 01:42:27 PM PDT 24
Finished Apr 02 01:42:32 PM PDT 24
Peak memory 218844 kb
Host smart-6e791c86-0e7a-4594-9a73-03c2cff4fc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825313654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3825313654
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1175292364
Short name T91
Test name
Test status
Simulation time 202024005 ps
CPU time 7.11 seconds
Started Apr 02 01:42:26 PM PDT 24
Finished Apr 02 01:42:33 PM PDT 24
Peak memory 222908 kb
Host smart-f2f59b4f-5541-4dd2-8d1a-e88dbc4b8844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175292364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1175292364
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4104797951
Short name T280
Test name
Test status
Simulation time 175161751 ps
CPU time 5.92 seconds
Started Apr 02 01:42:25 PM PDT 24
Finished Apr 02 01:42:31 PM PDT 24
Peak memory 211436 kb
Host smart-3190b5fe-801a-4b38-a140-1605c8b26f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104797951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4104797951
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2365027725
Short name T813
Test name
Test status
Simulation time 90728964 ps
CPU time 3.26 seconds
Started Apr 02 01:42:25 PM PDT 24
Finished Apr 02 01:42:29 PM PDT 24
Peak memory 222840 kb
Host smart-51ae8b5f-132d-494a-b1fb-a61410496988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365027725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2365027725
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.337932274
Short name T130
Test name
Test status
Simulation time 66660253 ps
CPU time 3.33 seconds
Started Apr 02 01:42:22 PM PDT 24
Finished Apr 02 01:42:25 PM PDT 24
Peak memory 218572 kb
Host smart-3fc7af78-2320-4c26-b944-647299a2d405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337932274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.337932274
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1453374346
Short name T596
Test name
Test status
Simulation time 92802024 ps
CPU time 2.08 seconds
Started Apr 02 01:42:19 PM PDT 24
Finished Apr 02 01:42:21 PM PDT 24
Peak memory 209040 kb
Host smart-a1ba6ab2-21d7-4c49-990c-17abade7b35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453374346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1453374346
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1849483276
Short name T648
Test name
Test status
Simulation time 150604931 ps
CPU time 2.79 seconds
Started Apr 02 01:42:22 PM PDT 24
Finished Apr 02 01:42:25 PM PDT 24
Peak memory 208664 kb
Host smart-63462077-e496-4001-9681-f2aaaee766d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849483276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1849483276
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3094344963
Short name T524
Test name
Test status
Simulation time 98008519 ps
CPU time 1.77 seconds
Started Apr 02 01:42:22 PM PDT 24
Finished Apr 02 01:42:24 PM PDT 24
Peak memory 207204 kb
Host smart-27509fe8-b5e5-4caa-88b9-f7f3f91a0106
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094344963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3094344963
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.968696058
Short name T665
Test name
Test status
Simulation time 89777216 ps
CPU time 2.54 seconds
Started Apr 02 01:42:22 PM PDT 24
Finished Apr 02 01:42:25 PM PDT 24
Peak memory 209024 kb
Host smart-aed5cf50-36e9-47b4-8936-d2ec819082b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968696058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.968696058
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2922017007
Short name T670
Test name
Test status
Simulation time 264906633 ps
CPU time 3.92 seconds
Started Apr 02 01:42:28 PM PDT 24
Finished Apr 02 01:42:32 PM PDT 24
Peak memory 210400 kb
Host smart-1145d5c6-adfe-40ac-9558-09d95c244e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922017007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2922017007
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1183129550
Short name T470
Test name
Test status
Simulation time 3888280886 ps
CPU time 23.85 seconds
Started Apr 02 01:42:20 PM PDT 24
Finished Apr 02 01:42:44 PM PDT 24
Peak memory 209352 kb
Host smart-0f415acc-f0d4-4eef-9ef8-e9578b834a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183129550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1183129550
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.571373480
Short name T847
Test name
Test status
Simulation time 69214952 ps
CPU time 2.46 seconds
Started Apr 02 01:42:26 PM PDT 24
Finished Apr 02 01:42:28 PM PDT 24
Peak memory 207532 kb
Host smart-eec88df9-775d-4451-8eaf-058efcfd9eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571373480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.571373480
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.461857683
Short name T833
Test name
Test status
Simulation time 582814141 ps
CPU time 6.92 seconds
Started Apr 02 01:42:31 PM PDT 24
Finished Apr 02 01:42:38 PM PDT 24
Peak memory 211216 kb
Host smart-3a65ec55-47bf-4176-8471-b11b6e6c223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461857683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.461857683
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.823006945
Short name T440
Test name
Test status
Simulation time 9700061 ps
CPU time 0.8 seconds
Started Apr 02 01:42:40 PM PDT 24
Finished Apr 02 01:42:41 PM PDT 24
Peak memory 206260 kb
Host smart-b9d583d1-5c59-43de-8d5a-1f102a0c868d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823006945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.823006945
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2371832210
Short name T740
Test name
Test status
Simulation time 1552855257 ps
CPU time 58.13 seconds
Started Apr 02 01:42:36 PM PDT 24
Finished Apr 02 01:43:34 PM PDT 24
Peak memory 222668 kb
Host smart-7ed75f9b-1e2b-4ae2-89fa-00724e19e7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371832210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2371832210
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.606331200
Short name T525
Test name
Test status
Simulation time 396180516 ps
CPU time 3.16 seconds
Started Apr 02 01:42:33 PM PDT 24
Finished Apr 02 01:42:37 PM PDT 24
Peak memory 209276 kb
Host smart-18bb9c0e-1153-4276-8fda-5faff09211a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606331200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.606331200
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1476443775
Short name T719
Test name
Test status
Simulation time 673863691 ps
CPU time 2.37 seconds
Started Apr 02 01:42:38 PM PDT 24
Finished Apr 02 01:42:40 PM PDT 24
Peak memory 222800 kb
Host smart-249e7308-7ced-4af1-aa88-8f07d2cb38c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476443775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1476443775
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2102246967
Short name T773
Test name
Test status
Simulation time 1948767857 ps
CPU time 10.11 seconds
Started Apr 02 01:42:31 PM PDT 24
Finished Apr 02 01:42:42 PM PDT 24
Peak memory 210084 kb
Host smart-dbcc3695-e09c-4089-a61e-bae034cf2cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102246967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2102246967
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3758712757
Short name T375
Test name
Test status
Simulation time 31502121 ps
CPU time 2.19 seconds
Started Apr 02 01:42:38 PM PDT 24
Finished Apr 02 01:42:41 PM PDT 24
Peak memory 206948 kb
Host smart-d643b814-cd6c-4276-8e11-41ec0c1f0b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758712757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3758712757
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3419712803
Short name T358
Test name
Test status
Simulation time 701391627 ps
CPU time 6.26 seconds
Started Apr 02 01:42:33 PM PDT 24
Finished Apr 02 01:42:40 PM PDT 24
Peak memory 208260 kb
Host smart-ece87ca6-b09e-4523-8bff-f9d0e5393934
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419712803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3419712803
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2324512337
Short name T378
Test name
Test status
Simulation time 207390723 ps
CPU time 3.18 seconds
Started Apr 02 01:42:31 PM PDT 24
Finished Apr 02 01:42:34 PM PDT 24
Peak memory 207168 kb
Host smart-f17b941e-c298-4879-ab7e-1b944046efa8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324512337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2324512337
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2472145547
Short name T589
Test name
Test status
Simulation time 1161381437 ps
CPU time 9.06 seconds
Started Apr 02 01:42:32 PM PDT 24
Finished Apr 02 01:42:42 PM PDT 24
Peak memory 207012 kb
Host smart-d0d9d9dc-dd41-48da-b205-3bdc7554c8d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472145547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2472145547
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3559087628
Short name T242
Test name
Test status
Simulation time 343322096 ps
CPU time 4.57 seconds
Started Apr 02 01:42:34 PM PDT 24
Finished Apr 02 01:42:39 PM PDT 24
Peak memory 209352 kb
Host smart-bb4710f4-d859-4016-90a9-82df86d55b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559087628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3559087628
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1650669129
Short name T891
Test name
Test status
Simulation time 3216959260 ps
CPU time 19.36 seconds
Started Apr 02 01:42:29 PM PDT 24
Finished Apr 02 01:42:49 PM PDT 24
Peak memory 208820 kb
Host smart-54a2ba87-dfbe-4b0e-880e-0eb38152c158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650669129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1650669129
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3689965266
Short name T668
Test name
Test status
Simulation time 4411950460 ps
CPU time 42.3 seconds
Started Apr 02 01:42:38 PM PDT 24
Finished Apr 02 01:43:21 PM PDT 24
Peak memory 216908 kb
Host smart-c2a781f7-ae5a-4f29-adf9-3e9855b9c4cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689965266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3689965266
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2225469701
Short name T359
Test name
Test status
Simulation time 1113179803 ps
CPU time 4.38 seconds
Started Apr 02 01:42:38 PM PDT 24
Finished Apr 02 01:42:43 PM PDT 24
Peak memory 209480 kb
Host smart-0fe40f48-0e4e-4187-8b4f-bb0ecfbbc104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225469701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2225469701
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1397107798
Short name T184
Test name
Test status
Simulation time 95608234 ps
CPU time 3.02 seconds
Started Apr 02 01:42:40 PM PDT 24
Finished Apr 02 01:42:43 PM PDT 24
Peak memory 210180 kb
Host smart-9ed4249d-5f3e-4967-9016-2e1861d3b6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397107798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1397107798
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3397398422
Short name T82
Test name
Test status
Simulation time 39587085 ps
CPU time 0.71 seconds
Started Apr 02 01:42:51 PM PDT 24
Finished Apr 02 01:42:52 PM PDT 24
Peak memory 206252 kb
Host smart-f4576b44-d462-4049-81c4-c4c8793d8088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397398422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3397398422
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3091930247
Short name T866
Test name
Test status
Simulation time 38525124 ps
CPU time 2.72 seconds
Started Apr 02 01:42:42 PM PDT 24
Finished Apr 02 01:42:45 PM PDT 24
Peak memory 215888 kb
Host smart-e1aa1e1c-e2b5-4e77-bc26-1f2e5dba30ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091930247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3091930247
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3316722065
Short name T701
Test name
Test status
Simulation time 628929364 ps
CPU time 6.65 seconds
Started Apr 02 01:42:49 PM PDT 24
Finished Apr 02 01:42:55 PM PDT 24
Peak memory 210528 kb
Host smart-0b9a7cfa-fff2-4379-bb0d-d69e6d4f48b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316722065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3316722065
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4109104644
Short name T602
Test name
Test status
Simulation time 138882052 ps
CPU time 2.69 seconds
Started Apr 02 01:42:41 PM PDT 24
Finished Apr 02 01:42:44 PM PDT 24
Peak memory 210660 kb
Host smart-0e511540-0fcf-4f89-8639-dc0ab4786823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109104644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4109104644
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.4207030579
Short name T663
Test name
Test status
Simulation time 4244220978 ps
CPU time 27.86 seconds
Started Apr 02 01:42:45 PM PDT 24
Finished Apr 02 01:43:13 PM PDT 24
Peak memory 214784 kb
Host smart-02fa5ca4-5ef2-49e4-914f-2407e82fdedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207030579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.4207030579
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1404263371
Short name T349
Test name
Test status
Simulation time 313144842 ps
CPU time 9.16 seconds
Started Apr 02 01:42:50 PM PDT 24
Finished Apr 02 01:43:00 PM PDT 24
Peak memory 211252 kb
Host smart-db467704-59eb-4564-87ca-b58b41018727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404263371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1404263371
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.104689499
Short name T635
Test name
Test status
Simulation time 70429805 ps
CPU time 1.96 seconds
Started Apr 02 01:42:44 PM PDT 24
Finished Apr 02 01:42:46 PM PDT 24
Peak memory 216448 kb
Host smart-7c9ec97b-3842-4c94-83bb-f881483d1475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104689499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.104689499
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2375222895
Short name T345
Test name
Test status
Simulation time 5559941584 ps
CPU time 55.97 seconds
Started Apr 02 01:42:42 PM PDT 24
Finished Apr 02 01:43:38 PM PDT 24
Peak memory 210764 kb
Host smart-0c703033-a78f-4ea8-9b66-dc462a24e535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375222895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2375222895
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2836867651
Short name T871
Test name
Test status
Simulation time 928715824 ps
CPU time 5.57 seconds
Started Apr 02 01:42:38 PM PDT 24
Finished Apr 02 01:42:44 PM PDT 24
Peak memory 206984 kb
Host smart-ded03407-87c4-4261-bbac-c9fd915e8cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836867651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2836867651
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1957414048
Short name T652
Test name
Test status
Simulation time 30629648 ps
CPU time 2.24 seconds
Started Apr 02 01:42:43 PM PDT 24
Finished Apr 02 01:42:45 PM PDT 24
Peak memory 206980 kb
Host smart-c3a6fe1a-fe73-46c6-a777-3001b877d23f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957414048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1957414048
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3117925169
Short name T271
Test name
Test status
Simulation time 1307135262 ps
CPU time 6.82 seconds
Started Apr 02 01:42:43 PM PDT 24
Finished Apr 02 01:42:50 PM PDT 24
Peak memory 208712 kb
Host smart-81da73a9-9d87-4088-a9d3-d9cdb9b51c9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117925169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3117925169
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3955341211
Short name T391
Test name
Test status
Simulation time 219999810 ps
CPU time 7.51 seconds
Started Apr 02 01:42:40 PM PDT 24
Finished Apr 02 01:42:48 PM PDT 24
Peak memory 208152 kb
Host smart-a4303949-08f9-48c6-aaae-3f5332a4ef15
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955341211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3955341211
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4128570416
Short name T457
Test name
Test status
Simulation time 117626876 ps
CPU time 2.18 seconds
Started Apr 02 01:42:47 PM PDT 24
Finished Apr 02 01:42:49 PM PDT 24
Peak memory 210112 kb
Host smart-bc533f53-a473-4c73-bd86-e4dc071b9cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128570416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4128570416
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1894321815
Short name T443
Test name
Test status
Simulation time 741587659 ps
CPU time 16.17 seconds
Started Apr 02 01:42:39 PM PDT 24
Finished Apr 02 01:42:56 PM PDT 24
Peak memory 208748 kb
Host smart-29f64464-0c8d-4301-af6b-e487b4076042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894321815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1894321815
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2019173137
Short name T220
Test name
Test status
Simulation time 6842323323 ps
CPU time 148.13 seconds
Started Apr 02 01:42:48 PM PDT 24
Finished Apr 02 01:45:17 PM PDT 24
Peak memory 217452 kb
Host smart-88366f0c-f670-40e0-99a6-9412d12c6e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019173137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2019173137
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.4106391289
Short name T167
Test name
Test status
Simulation time 1242063693 ps
CPU time 20.98 seconds
Started Apr 02 01:42:52 PM PDT 24
Finished Apr 02 01:43:13 PM PDT 24
Peak memory 222900 kb
Host smart-b69fabd3-f8d8-4fb6-97b4-6f2619e519ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106391289 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.4106391289
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2669270389
Short name T835
Test name
Test status
Simulation time 866179755 ps
CPU time 16.73 seconds
Started Apr 02 01:42:47 PM PDT 24
Finished Apr 02 01:43:03 PM PDT 24
Peak memory 222824 kb
Host smart-97214b6c-e5c0-4af1-9752-8c1e9205e43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669270389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2669270389
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1747117209
Short name T789
Test name
Test status
Simulation time 45629750 ps
CPU time 2.78 seconds
Started Apr 02 01:42:47 PM PDT 24
Finished Apr 02 01:42:50 PM PDT 24
Peak memory 210632 kb
Host smart-22ae454f-6c79-4a97-b863-a88004a609d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747117209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1747117209
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1363724390
Short name T216
Test name
Test status
Simulation time 51553374 ps
CPU time 0.91 seconds
Started Apr 02 01:43:00 PM PDT 24
Finished Apr 02 01:43:02 PM PDT 24
Peak memory 206472 kb
Host smart-3d138c5d-4e6e-463e-8246-3e0130e616d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363724390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1363724390
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.534691797
Short name T860
Test name
Test status
Simulation time 55920817 ps
CPU time 3.8 seconds
Started Apr 02 01:42:54 PM PDT 24
Finished Apr 02 01:42:58 PM PDT 24
Peak memory 214644 kb
Host smart-37a0d0d8-d2da-4abe-89cb-c12e1739cbf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534691797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.534691797
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4067071107
Short name T694
Test name
Test status
Simulation time 38732836 ps
CPU time 1.36 seconds
Started Apr 02 01:42:54 PM PDT 24
Finished Apr 02 01:42:56 PM PDT 24
Peak memory 209540 kb
Host smart-98f6986d-30ac-4ac8-9508-42f5c7aed391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067071107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4067071107
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3852248049
Short name T1
Test name
Test status
Simulation time 106097582 ps
CPU time 2.67 seconds
Started Apr 02 01:42:56 PM PDT 24
Finished Apr 02 01:42:59 PM PDT 24
Peak memory 214664 kb
Host smart-039d0c64-b5f0-4ffe-8663-d3b095d199c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852248049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3852248049
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.281427140
Short name T233
Test name
Test status
Simulation time 319565138 ps
CPU time 12.72 seconds
Started Apr 02 01:42:58 PM PDT 24
Finished Apr 02 01:43:11 PM PDT 24
Peak memory 210364 kb
Host smart-58580b75-ee79-44a7-a4f1-252768de6ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281427140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.281427140
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4092589315
Short name T46
Test name
Test status
Simulation time 74673481 ps
CPU time 2.55 seconds
Started Apr 02 01:42:58 PM PDT 24
Finished Apr 02 01:43:01 PM PDT 24
Peak memory 213916 kb
Host smart-0c329fe5-2680-4ce6-b7f1-b726c1eb4cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092589315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4092589315
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.182555645
Short name T861
Test name
Test status
Simulation time 238683205 ps
CPU time 5.99 seconds
Started Apr 02 01:42:58 PM PDT 24
Finished Apr 02 01:43:04 PM PDT 24
Peak memory 218736 kb
Host smart-2786d12f-1d62-4ba4-a14b-e7b97f2838c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182555645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.182555645
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.603604018
Short name T611
Test name
Test status
Simulation time 230790127 ps
CPU time 5.95 seconds
Started Apr 02 01:42:52 PM PDT 24
Finished Apr 02 01:42:58 PM PDT 24
Peak memory 208212 kb
Host smart-d60ac5ae-ed01-48b0-92fd-b7c7990cc39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603604018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.603604018
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3704689872
Short name T243
Test name
Test status
Simulation time 109400690 ps
CPU time 2.26 seconds
Started Apr 02 01:42:52 PM PDT 24
Finished Apr 02 01:42:54 PM PDT 24
Peak memory 207136 kb
Host smart-5041b938-cb37-420c-af84-f3f6a6ab5890
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704689872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3704689872
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.991378653
Short name T743
Test name
Test status
Simulation time 233144279 ps
CPU time 3.28 seconds
Started Apr 02 01:42:53 PM PDT 24
Finished Apr 02 01:42:56 PM PDT 24
Peak memory 208940 kb
Host smart-dd3a2036-6d03-40b7-936e-bf7a8d8020e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991378653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.991378653
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1215985735
Short name T748
Test name
Test status
Simulation time 5588133246 ps
CPU time 43.93 seconds
Started Apr 02 01:42:58 PM PDT 24
Finished Apr 02 01:43:42 PM PDT 24
Peak memory 207776 kb
Host smart-cb5f99be-2794-4d03-abc2-1933c9c13219
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215985735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1215985735
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3003950371
Short name T609
Test name
Test status
Simulation time 36781422 ps
CPU time 1.82 seconds
Started Apr 02 01:42:59 PM PDT 24
Finished Apr 02 01:43:01 PM PDT 24
Peak memory 209800 kb
Host smart-0d7b4684-b10a-4713-bf89-58e45f7b6c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003950371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3003950371
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3161216998
Short name T455
Test name
Test status
Simulation time 206218364 ps
CPU time 2.95 seconds
Started Apr 02 01:42:53 PM PDT 24
Finished Apr 02 01:42:57 PM PDT 24
Peak memory 208704 kb
Host smart-69626b26-32f6-48e9-b44c-778094ad52bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161216998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3161216998
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2688725520
Short name T314
Test name
Test status
Simulation time 819356167 ps
CPU time 10.92 seconds
Started Apr 02 01:42:59 PM PDT 24
Finished Apr 02 01:43:10 PM PDT 24
Peak memory 215892 kb
Host smart-b714243d-4815-4963-8229-1f7031b63462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688725520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2688725520
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1998070611
Short name T454
Test name
Test status
Simulation time 593399313 ps
CPU time 3.63 seconds
Started Apr 02 01:42:59 PM PDT 24
Finished Apr 02 01:43:03 PM PDT 24
Peak memory 207680 kb
Host smart-3c2f0455-7514-45af-9359-d1363656e3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998070611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1998070611
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1733877708
Short name T182
Test name
Test status
Simulation time 246174509 ps
CPU time 1.41 seconds
Started Apr 02 01:42:58 PM PDT 24
Finished Apr 02 01:42:59 PM PDT 24
Peak memory 208832 kb
Host smart-21a0da6c-9048-482f-9b78-8b4ca6a55bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733877708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1733877708
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.956152322
Short name T450
Test name
Test status
Simulation time 18120853 ps
CPU time 1.03 seconds
Started Apr 02 01:43:18 PM PDT 24
Finished Apr 02 01:43:19 PM PDT 24
Peak memory 206380 kb
Host smart-e6ccf775-7fee-4f3f-909e-b7d68301b854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956152322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.956152322
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.693330337
Short name T843
Test name
Test status
Simulation time 47887372 ps
CPU time 3.11 seconds
Started Apr 02 01:43:05 PM PDT 24
Finished Apr 02 01:43:08 PM PDT 24
Peak memory 215724 kb
Host smart-e4e7986d-10a0-4b22-be34-71b6e9ed68b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693330337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.693330337
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.4089818458
Short name T70
Test name
Test status
Simulation time 6402496080 ps
CPU time 76.31 seconds
Started Apr 02 01:43:09 PM PDT 24
Finished Apr 02 01:44:26 PM PDT 24
Peak memory 223212 kb
Host smart-1831ab5b-f22f-4ae4-9296-056a6983f177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089818458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.4089818458
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3955999222
Short name T594
Test name
Test status
Simulation time 230609049 ps
CPU time 2.93 seconds
Started Apr 02 01:43:03 PM PDT 24
Finished Apr 02 01:43:06 PM PDT 24
Peak memory 214616 kb
Host smart-61185ae5-bb47-43b5-9429-7f18d993c6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955999222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3955999222
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.790985738
Short name T483
Test name
Test status
Simulation time 52012690 ps
CPU time 3.19 seconds
Started Apr 02 01:43:04 PM PDT 24
Finished Apr 02 01:43:08 PM PDT 24
Peak memory 208988 kb
Host smart-e4decd0f-a329-42bb-b3b9-3637424af2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790985738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.790985738
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.759394496
Short name T367
Test name
Test status
Simulation time 506685264 ps
CPU time 8.81 seconds
Started Apr 02 01:43:07 PM PDT 24
Finished Apr 02 01:43:17 PM PDT 24
Peak memory 222732 kb
Host smart-6e9a380c-53b0-460d-a5d3-2d2c6f1ac82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759394496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.759394496
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.773714388
Short name T810
Test name
Test status
Simulation time 134346265 ps
CPU time 3.08 seconds
Started Apr 02 01:43:07 PM PDT 24
Finished Apr 02 01:43:10 PM PDT 24
Peak memory 217080 kb
Host smart-93e924dc-956f-4b06-b320-b6c0d57ab4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773714388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.773714388
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1011119779
Short name T846
Test name
Test status
Simulation time 90285444 ps
CPU time 4.96 seconds
Started Apr 02 01:43:05 PM PDT 24
Finished Apr 02 01:43:10 PM PDT 24
Peak memory 210684 kb
Host smart-724c93df-a9b0-4fa1-a9e2-7914350983cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011119779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1011119779
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.921978068
Short name T523
Test name
Test status
Simulation time 88088055 ps
CPU time 3.15 seconds
Started Apr 02 01:43:03 PM PDT 24
Finished Apr 02 01:43:06 PM PDT 24
Peak memory 207132 kb
Host smart-264cc094-f317-4846-8e2e-149ea4b9da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921978068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.921978068
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.301094116
Short name T334
Test name
Test status
Simulation time 32597025 ps
CPU time 2.21 seconds
Started Apr 02 01:43:01 PM PDT 24
Finished Apr 02 01:43:03 PM PDT 24
Peak memory 209144 kb
Host smart-c8d8f593-841d-494e-b3ca-371ca25779eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301094116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.301094116
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.964519408
Short name T731
Test name
Test status
Simulation time 25081872 ps
CPU time 1.95 seconds
Started Apr 02 01:43:06 PM PDT 24
Finished Apr 02 01:43:09 PM PDT 24
Peak memory 207140 kb
Host smart-5fb908a2-40d6-4d2c-ac66-76f745fe4f14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964519408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.964519408
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2262524278
Short name T553
Test name
Test status
Simulation time 96088741 ps
CPU time 3.72 seconds
Started Apr 02 01:43:06 PM PDT 24
Finished Apr 02 01:43:10 PM PDT 24
Peak memory 207164 kb
Host smart-e3dca67d-16ac-420f-b853-3b2fb9d3cd96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262524278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2262524278
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1665804897
Short name T646
Test name
Test status
Simulation time 77339739 ps
CPU time 2.23 seconds
Started Apr 02 01:43:09 PM PDT 24
Finished Apr 02 01:43:12 PM PDT 24
Peak memory 207920 kb
Host smart-c7addb63-2854-4d3c-a1c5-0a6b2f1f6cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665804897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1665804897
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.702377246
Short name T832
Test name
Test status
Simulation time 426057047 ps
CPU time 3.81 seconds
Started Apr 02 01:43:01 PM PDT 24
Finished Apr 02 01:43:05 PM PDT 24
Peak memory 207268 kb
Host smart-c802d466-ceec-41de-9def-8b5658aa7f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702377246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.702377246
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3633075089
Short name T227
Test name
Test status
Simulation time 1273823242 ps
CPU time 6.52 seconds
Started Apr 02 01:43:04 PM PDT 24
Finished Apr 02 01:43:11 PM PDT 24
Peak memory 208476 kb
Host smart-b4373f8c-dfa5-4119-b515-27fb4c0073cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633075089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3633075089
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.829572424
Short name T400
Test name
Test status
Simulation time 144755965 ps
CPU time 2.65 seconds
Started Apr 02 01:43:09 PM PDT 24
Finished Apr 02 01:43:14 PM PDT 24
Peak memory 210268 kb
Host smart-e8a6f6a9-3ed8-486d-8da1-01f2d077217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829572424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.829572424
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%