Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	80	250	75.76

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	61	219	78.21	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4647

1

T1

3

T3

1

T4

10

auto[1]

556

1

T13

1

T14

2

T40

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4647

1

T1

3

T3

1

T4

10

auto[1]

556

1

T13

1

T14

2

T40

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4677

1

T1

3

T3

1

T4

10

auto[1]

526

1

T14

3

T23

1

T24

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4677

1

T1

3

T3

1

T4

10

auto[1]

526

1

T14

3

T23

1

T24

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	393	1			T14	3		T23	1		T24	1
auto[OpGenId]	1087	1			T5	1		T14	4		T15	3
auto[OpGenSwOut]	1139	1			T1	2		T5	1		T14	2
auto[OpGenHwOut]	2518	1			T1	1		T3	1		T4	10
auto[OpDisable]	66	1			T13	1		T45	1		T67	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	393	1			T14	3		T23	1		T24	1
auto[OpGenId]	1087	1			T5	1		T14	4		T15	3
auto[OpGenSwOut]	1139	1			T1	2		T5	1		T14	2
auto[OpGenHwOut]	2518	1			T1	1		T3	1		T4	10
auto[OpDisable]	66	1			T13	1		T45	1		T67	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4686

1

T1

3

T3

1

T4

5

auto[1]

517

1

T4

5

T40

1

T85

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4686

1

T1

3

T3

1

T4

5

auto[1]

517

1

T4

5

T40

1

T85

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4972

1

T1

3

T3

1

T4

10

auto[1]

231

1

T14

3

T126

5

T136

1

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1779	1			T1	1		T3	1		T4	4
auto[1]	689	1			T4	2		T40	1		T199	1
auto[2]	663	1			T4	1		T5	1		T14	2
auto[3]	640	1			T1	1		T4	1		T5	1
auto[4]	323	1			T15	1		T40	1		T195	1
auto[5]	387	1			T5	1		T14	1		T23	2
auto[6]	372	1			T1	1		T14	1		T85	1
auto[7]	350	1			T4	2		T197	4		T200	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1432	1			T1	1		T4	2		T5	1
clear_one[1]	689	1			T4	2		T40	1		T199	1
clear_one[2]	663	1			T4	1		T5	1		T14	2
clear_one[3]	640	1			T1	1		T4	1		T5	1
clear_none	1779	1			T1	1		T3	1		T4	4

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	993	1			T1	2		T3	1		T4	2
auto[StInit]	777	1			T1	1		T4	1		T5	5
auto[StCreatorRootKey]	575	1			T4	1		T14	1		T23	1
auto[StOwnerIntKey]	498	1			T4	1		T14	1		T85	1
auto[StOwnerKey]	445	1			T4	1		T14	1		T15	1
auto[StDisabled]	1765	1			T4	4		T13	1		T14	5
auto[StInvalid]	150	1			T21	1		T36	3		T82	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	993	1			T1	2		T3	1		T4	2
auto[StInit]	777	1			T1	1		T4	1		T5	5
auto[StCreatorRootKey]	575	1			T4	1		T14	1		T23	1
auto[StOwnerIntKey]	498	1			T4	1		T14	1		T85	1
auto[StOwnerKey]	445	1			T4	1		T14	1		T15	1
auto[StDisabled]	1765	1			T4	4		T13	1		T14	5
auto[StInvalid]	150	1			T21	1		T36	3		T82	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	61	219	78.21	61

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[3]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpAdvance] , auto[OpGenId]]	--	--	2
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	7	1			T237	1		T238	1		T176	2
auto[0]	auto[StReset]	auto[OpGenId]	135	1			T22	1		T72	2		T57	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	179	1			T1	1		T199	1		T195	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	254	1			T3	1		T4	1		T23	1
auto[0]	auto[StInit]	auto[OpAdvance]	46	1			T40	1		T196	1		T36	1
auto[0]	auto[StInit]	auto[OpGenId]	114	1			T14	1		T15	1		T44	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	96	1			T14	1		T86	1		T21	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	185	1			T5	2		T24	1		T211	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	23	1			T81	1		T210	1		T63	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	55	1			T71	1		T93	1		T239	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	40	1			T44	1		T126	1		T8	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	62	1			T4	1		T24	1		T209	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T204	1		T240	1		T241	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	24	1			T126	1		T93	1		T64	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	22	1			T86	1		T200	1		T201	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T85	1		T104	1		T242	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T243	1		T219	1		T77	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	24	1			T44	1		T183	1		T43	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T8	1		T54	1		T119	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T4	1		T8	2		T55	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	16	1			T14	1		T23	1		T8	1
auto[0]	auto[StDisabled]	auto[OpGenId]	59	1			T14	2		T44	1		T64	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T14	1		T15	1		T23	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	172	1			T4	1		T104	1		T80	1
auto[0]	auto[StDisabled]	auto[OpDisable]	26	1			T13	1		T67	1		T150	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	6	1			T101	1		T244	1		T245	1
auto[0]	auto[StInvalid]	auto[OpGenId]	12	1			T94	1		T207	1		T246	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T82	1		T207	1		T247	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T82	1		T248	1		T249	1
auto[1]	auto[StReset]	auto[OpGenId]	23	1			T48	1		T71	1		T247	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	21	1			T22	2		T56	1		T55	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	46	1			T4	1		T199	1		T104	1
auto[1]	auto[StInit]	auto[OpAdvance]	9	1			T22	1		T192	1		T66	1
auto[1]	auto[StInit]	auto[OpGenId]	14	1			T44	1		T97	1		T219	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T192	1		T246	1		T250	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	16	1			T251	1		T54	1		T117	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	14	1			T92	1		T252	1		T253	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T8	1		T42	1		T54	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T254	1		T255	1		T119	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T41	1		T8	1		T182	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T137	1		T256	1		-	-
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	28	1			T209	1		T213	1		T64	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T257	1		T258	1		T252	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T196	1		T251	1		T259	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T137	1		T79	1		T253	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T42	1		T260	1		T261	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T44	1		T8	1		T262	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T211	1		T263	1		T251	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	28	1			T92	1		T137	2		T64	1
auto[1]	auto[StDisabled]	auto[OpGenId]	42	1			T44	1		T45	1		T205	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T206	1		T8	2		T202	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T4	1		T40	1		T211	1
auto[1]	auto[StDisabled]	auto[OpDisable]	3	1			T219	1		T264	1		T265	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	4	1			T72	1		T266	1		T267	1
auto[1]	auto[StInvalid]	auto[OpGenId]	7	1			T36	1		T72	1		T248	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T207	1		T268	1		T269	2
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T101	1		T270	1		T271	1
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T44	1		T257	2		T272	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T8	1		T273	1		T119	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	49	1			T104	1		T90	1		T8	2
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T274	1		T275	1		T276	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T210	1		T54	1		T39	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	21	1			T5	1		T203	1		T277	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	38	1			T83	1		T89	1		T254	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T75	1		T278	1		T279	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T86	1		T195	1		T137	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T203	1		T137	1		T280	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T40	1		T104	1		T281	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T282	1		T253	1		T283	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T14	1		T92	1		T137	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T195	1		T8	1		T73	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T4	1		T197	1		T284	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T14	1		T75	1		T285	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	11	1			T105	1		T257	1		T55	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T205	1		T286	1		T287	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T57	1		T281	1		T288	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	14	1			T216	1		T76	1		T289	1
auto[2]	auto[StDisabled]	auto[OpGenId]	61	1			T15	1		T195	1		T111	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	43	1			T8	1		T54	1		T117	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T40	1		T51	1		T80	2
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T57	1		T219	1		T216	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	2	1			T244	1		T290	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenId]	5	1			T52	1		T291	1		T292	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T21	1		T207	1		T247	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T82	1		T94	1		T249	1
auto[3]	auto[StReset]	auto[OpGenId]	16	1			T8	1		T94	1		T38	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	19	1			T44	1		T72	1		T192	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	36	1			T83	1		T90	1		T293	1
auto[3]	auto[StInit]	auto[OpAdvance]	13	1			T294	1		T295	2		T296	1
auto[3]	auto[StInit]	auto[OpGenId]	13	1			T90	1		T192	1		T297	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	14	1			T23	1		T22	1		T192	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	21	1			T1	1		T4	1		T5	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T43	1		T269	1		T77	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T213	1		T298	1		T225	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	20	1			T44	1		T42	1		T277	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T23	1		T299	1		T293	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T300	1		T301	1		-	-
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T117	1		T302	1		T303	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T304	1		T43	1		T75	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T305	1		T306	1		T307	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T64	1		T308	1		T309	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T310	1		T311	1		T184	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T312	1		T313	1		T123	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T83	1		T254	1		T259	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	20	1			T24	1		T44	1		T198	1
auto[3]	auto[StDisabled]	auto[OpGenId]	41	1			T136	1		T91	1		T8	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	44	1			T44	1		T210	1		T8	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T195	1		T209	1		T211	2
auto[3]	auto[StDisabled]	auto[OpDisable]	11	1			T73	1		T70	1		T75	1
auto[3]	auto[StInvalid]	auto[OpGenId]	2	1			T292	1		T314	1		-	-
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T36	1		T82	1		T101	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T212	1		T249	1		T315	1
auto[4]	auto[StReset]	auto[OpGenId]	11	1			T25	1		T90	1		T192	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T44	1		T316	1		T317	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	20	1			T90	1		T64	1		T305	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T216	1		T318	1		T319	1
auto[4]	auto[StInit]	auto[OpGenId]	8	1			T192	1		T42	1		T320	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T321	1		T119	1		T216	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	14	1			T92	1		T322	1		T43	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T228	1		T47	1		T323	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T105	1		T55	1		T184	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T324	1		T75	1		T78	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T64	1		T325	1		T75	2
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T326	1		T327	1		T328	2
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T198	1		T76	1		T329	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T105	1		T55	1		T219	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T211	1		T80	1		T330	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T184	1		T331	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T15	1		T250	1		T332	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T250	1		T276	1		T333	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	11	1			T293	1		T8	1		T54	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	13	1			T8	1		T219	1		T43	1
auto[4]	auto[StDisabled]	auto[OpGenId]	15	1			T40	1		T111	1		T128	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T254	1		T334	1		T190	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T195	1		T198	1		T93	1
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T68	1		T76	1		T335	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T207	1		T247	1		T275	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T336	1		T337	1		T338	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T197	1		T183	1		T303	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T219	1		T216	1		T250	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	20	1			T104	1		T203	1		T105	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T339	1		T340	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	12	1			T5	1		T136	1		T120	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	11	1			T55	1		T341	1		T342	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	15	1			T97	1		T8	1		T183	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T136	1		T343	1		T344	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T97	1		T54	1		T55	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T326	1		T345	1		T77	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	29	1			T14	1		T211	1		T187	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T344	1		T333	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	2	1			T210	1		T43	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T71	1		T205	1		T75	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	30	1			T44	1		T281	1		T91	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T346	1		T331	1		T252	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	8	1			T8	1		T43	1		T75	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T196	1		T64	1		T347	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T80	1		T187	1		T306	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T346	1		T105	1		T183	1
auto[5]	auto[StDisabled]	auto[OpGenId]	23	1			T23	1		T24	1		T204	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T85	1		T197	1		T200	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T23	1		T195	1		T44	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T348	1		T317	1		T349	1
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T94	2		T337	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T100	1		T212	1		T246	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T244	1		T292	1		-	-
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T8	2		T54	1		T216	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T1	1		T199	1		T254	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	18	1			T104	1		T42	1		T350	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T351	1		T352	1		T353	1
auto[6]	auto[StInit]	auto[OpGenId]	8	1			T22	1		T88	1		T43	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	12	1			T137	2		T212	1		T43	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	13	1			T354	1		T305	1		T355	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T356	1		T357	1		T358	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T55	1		T359	1		T320	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T25	1		T321	1		T183	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T111	1		T251	1		T259	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T8	1		T38	1		T357	2
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T42	1		T55	1		T253	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T54	2		T119	1		T360	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T51	1		T83	1		T263	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T361	1		T129	1		T351	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T8	1		T360	1		T362	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T363	1		T8	1		T364	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T111	1		T104	1		T305	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	19	1			T14	1		T129	2		T219	1
auto[6]	auto[StDisabled]	auto[OpGenId]	30	1			T85	1		T191	1		T105	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T44	1		T137	1		T214	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T200	1		T204	1		T8	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T58	1		T365	1		T308	1
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T247	1		T366	1		T266	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T72	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T101	1		T367	1		T270	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T260	1		T246	1		T219	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	13	1			T111	1		T182	1		T55	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	22	1			T195	1		T82	1		T182	1
auto[7]	auto[StInit]	auto[OpAdvance]	7	1			T197	1		T51	1		T28	1
auto[7]	auto[StInit]	auto[OpGenId]	11	1			T88	1		T341	1		T324	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T332	1		T368	1		T167	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	13	1			T369	1		T370	1		T327	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T225	1		T371	1		T372	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T183	1		T43	2		T373	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T51	1		T260	1		T374	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T44	1		T80	1		T83	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T128	1		T371	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T254	1		T64	1		T375	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T58	1		T120	1		T376	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T187	1		T299	1		T54	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T183	1		T344	1		T377	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T378	1		T230	1		T379	2
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T202	1		T380	1		T232	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T197	1		T242	1		T136	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	17	1			T197	1		T200	1		T137	1
auto[7]	auto[StDisabled]	auto[OpGenId]	25	1			T203	1		T254	1		T137	3
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T44	1		T137	1		T58	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T4	2		T197	1		T104	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T45	1		T381	1		T157	1
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T36	1		T100	1		T207	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T207	1		T247	1		T244	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T367	1		T382	1		-	-

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1432

1

T1

1

T4

2

T5

1

clear_one[1]

auto[0]

auto[0]

auto[0]

390

1

T4

1

T199

1

T209

1

clear_one[1]

auto[0]

auto[0]

auto[1]

122

1

T4

1

T198

1

T41

1

clear_one[1]

auto[0]

auto[1]

auto[0]

123

1

T83

2

T263

2

T93

1

clear_one[1]

auto[0]

auto[1]

auto[1]

54

1

T40

1

T8

3

T54

1

clear_one[2]

auto[0]

auto[0]

auto[0]

394

1

T5

1

T15

1

T40

1

clear_one[2]

auto[0]

auto[0]

auto[1]

107

1

T4

1

T203

1

T92

2

clear_one[2]

auto[1]

auto[0]

auto[0]

123

1

T14

2

T40

1

T195

1

clear_one[2]

auto[1]

auto[0]

auto[1]

39

1

T205

2

T257

1

T55

1

clear_one[3]

auto[0]

auto[0]

auto[0]

365

1

T1

1

T4

1

T5

1

clear_one[3]

auto[0]

auto[1]

auto[0]

106

1

T24

1

T44

2

T83

1

clear_one[3]

auto[1]

auto[0]

auto[0]

132

1

T209

1

T44

1

T211

2

clear_one[3]

auto[1]

auto[1]

auto[0]

37

1

T195

1

T55

1

T304

1

clear_none

auto[0]

auto[0]

auto[0]

1283

1

T1

1

T3

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

125

1

T4

3

T204

1

T346

1

clear_none

auto[0]

auto[1]

auto[0]

122

1

T14

3

T23

1

T24

1

clear_none

auto[0]

auto[1]

auto[1]

24

1

T203

1

T8

3

T383

1

clear_none

auto[1]

auto[0]

auto[0]

141

1

T13

1

T200

1

T209

1

clear_none

auto[1]

auto[0]

auto[1]

24

1

T85

1

T91

1

T8

1

clear_none

auto[1]

auto[1]

auto[0]

38

1

T44

1

T45

1

T126

1

clear_none

auto[1]

auto[1]

auto[1]

22

1

T55

1

T384

2

T76

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1348	1			T1	1		T4	2		T5	1
clear_all	auto[1]	84	1			T126	1		T136	1		T137	8
clear_one[1]	auto[0]	652	1			T4	2		T40	1		T199	1
clear_one[1]	auto[1]	37	1			T137	3		T243	1		T300	1
clear_one[2]	auto[0]	633	1			T4	1		T5	1		T14	2
clear_one[2]	auto[1]	30	1			T137	3		T282	7		T385	1
clear_one[3]	auto[0]	621	1			T1	1		T4	1		T5	1
clear_one[3]	auto[1]	19	1			T128	1		T300	1		T386	2
clear_none	auto[0]	1718	1			T1	1		T3	1		T4	4
clear_none	auto[1]	61	1			T14	3		T126	4		T257	1