Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11657

1

T1

8

T3

4

T4

8

auto[Attestation]

8197

1

T1

3

T4

5

T5

15

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3001	1			T1	2		T5	6		T13	3
auto[Aes]	3567	1			T1	2		T3	1		T5	4
auto[Kmac]	3581	1			T1	1		T3	1		T5	4
auto[Otbn]	3496	1			T1	2		T4	13		T5	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7918	1			T1	2		T3	1		T4	8
auto[OpGenId]	6209	1			T1	4		T3	2		T5	9
auto[OpGenSwOut]	6247	1			T1	5		T3	1		T5	10
auto[OpGenHwOut]	7398	1			T1	2		T3	1		T4	13
auto[OpDisable]	114	1			T13	1		T44	1		T45	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10309

1

T1

2

T3

1

T4

8

auto[OpDoneFail]

17577

1

T1

11

T3

4

T4

13

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6376	1			T1	8		T3	3		T4	6
auto[StInit]	4479	1			T1	5		T3	2		T4	2
auto[StCreatorRootKey]	3076	1			T4	2		T13	4		T14	3
auto[StOwnerIntKey]	2677	1			T4	2		T13	5		T14	6
auto[StOwnerKey]	2459	1			T4	2		T14	1		T15	2
auto[StDisabled]	7784	1			T4	7		T13	2		T14	11
auto[StInvalid]	1035	1			T21	21		T36	21		T82	29

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	343	1			T1	2		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	132	1			T5	3		T13	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T195	1		T35	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T33	1		T23	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	65	1			T23	1		T40	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	220	1			T23	1		T197	2		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T82	1		T52	1		T94	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	307	1			T1	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	130	1			T5	2		T17	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	83	1			T13	1		T23	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	63	1			T14	1		T16	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	54	1			T93	1		T64	1		T8	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	218	1			T14	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T21	1		T82	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	351	1			T16	2		T23	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	106	1			T23	1		T22	1		T90	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T44	1		T25	1		T126	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T200	1		T44	1		T201	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T16	1		T202	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	213	1			T23	1		T86	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	36	1			T21	1		T82	2		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	336	1			T1	1		T17	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	128	1			T1	1		T5	2		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T203	1		T56	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	62	1			T13	1		T8	2		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	54	1			T197	1		T44	3		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	207	1			T40	1		T197	2		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	37	1			T21	1		T36	1		T82	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	61	1			T8	2		T42	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	134	1			T5	1		T21	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T67	1		T64	2		T8	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	56	1			T44	1		T205	1		T8	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T40	1		T203	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	210	1			T15	1		T85	1		T200	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	30	1			T82	2		T100	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	84	1			T51	2		T8	2		T54	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	115	1			T16	1		T200	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	103	1			T16	1		T24	1		T44	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	64	1			T14	1		T195	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	45	1			T196	1		T8	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	200	1			T16	1		T33	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T36	1		T94	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	90	1			T44	2		T8	2		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	113	1			T5	1		T13	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T24	1		T34	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T14	1		T200	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	68	1			T33	1		T197	1		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	228	1			T14	1		T33	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	36	1			T21	1		T36	2		T82	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	74	1			T8	2		T42	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	135	1			T5	1		T22	2		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	73	1			T13	1		T24	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T86	1		T97	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	67	1			T44	1		T111	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	210	1			T16	2		T40	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	24	1			T21	1		T82	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	294	1			T17	1		T199	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	127	1			T21	1		T201	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	72	1			T23	1		T209	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	64	1			T13	2		T24	1		T197	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	64	1			T40	1		T197	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	206	1			T195	2		T51	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	33	1			T36	1		T82	1		T100	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	462	1			T199	1		T21	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	140	1			T5	2		T85	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	114	1			T195	1		T44	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	105	1			T13	1		T14	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	90	1			T40	1		T196	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	276	1			T14	1		T23	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	31	1			T21	2		T36	1		T100	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	430	1			T1	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	143	1			T200	1		T44	2		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T40	1		T199	3		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T24	1		T44	2		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	102	1			T23	2		T196	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	272	1			T40	1		T195	1		T44	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	24	1			T82	2		T52	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	480	1			T4	5		T17	2		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	136	1			T5	1		T195	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	101	1			T85	1		T199	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T44	1		T201	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	75	1			T4	1		T204	1		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	291	1			T4	2		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	23	1			T21	1		T36	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	81	1			T44	1		T64	1		T8	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	112	1			T5	2		T21	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T40	2		T44	3		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	59	1			T15	1		T213	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T44	1		T204	2		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	166	1			T24	1		T86	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	32	1			T100	2		T101	1		T52	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	59	1			T44	3		T51	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	142	1			T1	1		T199	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	112	1			T14	1		T24	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T85	1		T200	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	99	1			T209	1		T211	1		T196	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	286	1			T197	2		T44	1		T211	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	33	1			T36	1		T72	1		T101	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T64	1		T42	4		T54	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	129	1			T5	3		T24	1		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T14	1		T24	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T201	1		T198	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	92	1			T197	1		T198	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	288	1			T13	1		T14	2		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	40	1			T36	1		T82	1		T72	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	49	1			T8	1		T42	4		T54	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	117	1			T4	1		T22	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	96	1			T4	1		T198	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T4	1		T23	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	95	1			T23	1		T111	2		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	264	1			T4	2		T40	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	39	1			T21	2		T36	1		T82	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	190	1			T33	1		T23	2		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	732	1			T1	2		T5	3		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	181	1			T13	1		T14	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	706	1			T1	1		T3	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	218	1			T16	1		T200	1		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	722	1			T16	2		T23	3		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	181	1			T13	1		T197	1		T44	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	718	1			T1	2		T5	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	176	1			T40	1		T44	1		T67	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	449	1			T5	1		T15	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	184	1			T14	1		T16	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	457	1			T16	2		T33	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	191	1			T14	1		T33	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	487	1			T5	1		T13	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T13	1		T24	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	459	1			T5	1		T16	2		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	181	1			T13	2		T23	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	679	1			T17	1		T24	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	293	1			T13	1		T14	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	925	1			T5	2		T14	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	285	1			T23	2		T24	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	880	1			T1	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	244	1			T4	1		T85	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	947	1			T4	7		T5	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	189	1			T15	1		T40	2		T44	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	405	1			T5	2		T24	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	280	1			T14	1		T85	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	541	1			T1	1		T24	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	260	1			T14	1		T24	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	538	1			T5	3		T13	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	266	1			T4	2		T23	2		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	485	1			T4	3		T40	1		T200	1