Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31877

1

T1

16

T3

5

T4

26

auto[1]

264

1

T14

3

T111

2

T126

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31889	1			T1	16		T3	5		T4	26
auto[134217728:268435455]	8	1			T250	1		T385	2		T406	1
auto[268435456:402653183]	14	1			T126	1		T407	1		T237	1
auto[402653184:536870911]	7	1			T14	1		T129	1		T406	1
auto[536870912:671088639]	12	1			T137	1		T128	1		T300	1
auto[671088640:805306367]	6	1			T137	1		T300	1		T406	1
auto[805306368:939524095]	8	1			T137	1		T250	1		T331	2
auto[939524096:1073741823]	7	1			T137	1		T331	1		T282	1
auto[1073741824:1207959551]	11	1			T250	1		T252	1		T282	1
auto[1207959552:1342177279]	12	1			T137	1		T128	1		T129	2
auto[1342177280:1476395007]	8	1			T257	1		T300	1		T282	1
auto[1476395008:1610612735]	2	1			T129	1		T176	1		-	-
auto[1610612736:1744830463]	8	1			T282	1		T406	1		T408	1
auto[1744830464:1879048191]	6	1			T331	1		T237	1		T406	1
auto[1879048192:2013265919]	10	1			T111	1		T257	1		T129	1
auto[2013265920:2147483647]	9	1			T137	1		T129	1		T331	1
auto[2147483648:2281701375]	7	1			T126	1		T386	2		T371	1
auto[2281701376:2415919103]	7	1			T126	1		T137	1		T128	1
auto[2415919104:2550136831]	13	1			T137	1		T300	1		T250	1
auto[2550136832:2684354559]	9	1			T126	1		T392	1		T371	2
auto[2684354560:2818572287]	7	1			T137	1		T252	1		T386	1
auto[2818572288:2952790015]	8	1			T14	1		T250	1		T409	1
auto[2952790016:3087007743]	12	1			T129	1		T300	2		T331	2
auto[3087007744:3221225471]	6	1			T362	1		T282	2		T276	1
auto[3221225472:3355443199]	7	1			T128	1		T129	1		T300	1
auto[3355443200:3489660927]	4	1			T14	1		T409	1		T344	1
auto[3489660928:3623878655]	8	1			T257	2		T331	1		T407	2
auto[3623878656:3758096383]	5	1			T252	1		T282	1		T408	1
auto[3758096384:3892314111]	9	1			T257	1		T250	2		T371	1
auto[3892314112:4026531839]	10	1			T137	1		T331	1		T282	1
auto[4026531840:4160749567]	5	1			T137	1		T300	1		T410	1
auto[4160749568:4294967295]	7	1			T111	1		T252	1		T282	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31877	1			T1	16		T3	5		T4	26
auto[0:134217727]	auto[1]	12	1			T126	2		T137	1		T250	1
auto[134217728:268435455]	auto[1]	8	1			T250	1		T385	2		T406	1
auto[268435456:402653183]	auto[1]	14	1			T126	1		T407	1		T237	1
auto[402653184:536870911]	auto[1]	7	1			T14	1		T129	1		T406	1
auto[536870912:671088639]	auto[1]	12	1			T137	1		T128	1		T300	1
auto[671088640:805306367]	auto[1]	6	1			T137	1		T300	1		T406	1
auto[805306368:939524095]	auto[1]	8	1			T137	1		T250	1		T331	2
auto[939524096:1073741823]	auto[1]	7	1			T137	1		T331	1		T282	1
auto[1073741824:1207959551]	auto[1]	11	1			T250	1		T252	1		T282	1
auto[1207959552:1342177279]	auto[1]	12	1			T137	1		T128	1		T129	2
auto[1342177280:1476395007]	auto[1]	8	1			T257	1		T300	1		T282	1
auto[1476395008:1610612735]	auto[1]	2	1			T129	1		T176	1		-	-
auto[1610612736:1744830463]	auto[1]	8	1			T282	1		T406	1		T408	1
auto[1744830464:1879048191]	auto[1]	6	1			T331	1		T237	1		T406	1
auto[1879048192:2013265919]	auto[1]	10	1			T111	1		T257	1		T129	1
auto[2013265920:2147483647]	auto[1]	9	1			T137	1		T129	1		T331	1
auto[2147483648:2281701375]	auto[1]	7	1			T126	1		T386	2		T371	1
auto[2281701376:2415919103]	auto[1]	7	1			T126	1		T137	1		T128	1
auto[2415919104:2550136831]	auto[1]	13	1			T137	1		T300	1		T250	1
auto[2550136832:2684354559]	auto[1]	9	1			T126	1		T392	1		T371	2
auto[2684354560:2818572287]	auto[1]	7	1			T137	1		T252	1		T386	1
auto[2818572288:2952790015]	auto[1]	8	1			T14	1		T250	1		T409	1
auto[2952790016:3087007743]	auto[1]	12	1			T129	1		T300	2		T331	2
auto[3087007744:3221225471]	auto[1]	6	1			T362	1		T282	2		T276	1
auto[3221225472:3355443199]	auto[1]	7	1			T128	1		T129	1		T300	1
auto[3355443200:3489660927]	auto[1]	4	1			T14	1		T409	1		T344	1
auto[3489660928:3623878655]	auto[1]	8	1			T257	2		T331	1		T407	2
auto[3623878656:3758096383]	auto[1]	5	1			T252	1		T282	1		T408	1
auto[3758096384:3892314111]	auto[1]	9	1			T257	1		T250	2		T371	1
auto[3892314112:4026531839]	auto[1]	10	1			T137	1		T331	1		T282	1
auto[4026531840:4160749567]	auto[1]	5	1			T137	1		T300	1		T410	1
auto[4160749568:4294967295]	auto[1]	7	1			T111	1		T252	1		T282	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1556

1

T1

3

T3

1

T5

2

auto[1]

1726

1

T1

5

T3

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T3	1		T23	1		T198	1
auto[134217728:268435455]	103	1			T1	1		T199	1		T195	1
auto[268435456:402653183]	105	1			T200	1		T22	1		T111	1
auto[402653184:536870911]	104	1			T51	2		T72	1		T210	1
auto[536870912:671088639]	119	1			T5	2		T111	1		T41	1
auto[671088640:805306367]	104	1			T200	1		T195	1		T44	1
auto[805306368:939524095]	114	1			T24	1		T21	1		T44	1
auto[939524096:1073741823]	100	1			T1	1		T195	1		T48	1
auto[1073741824:1207959551]	102	1			T199	1		T200	1		T204	1
auto[1207959552:1342177279]	103	1			T201	1		T22	1		T51	1
auto[1342177280:1476395007]	106	1			T197	1		T21	1		T44	1
auto[1476395008:1610612735]	123	1			T44	2		T51	2		T48	2
auto[1610612736:1744830463]	96	1			T24	1		T21	1		T89	1
auto[1744830464:1879048191]	98	1			T197	1		T195	1		T44	1
auto[1879048192:2013265919]	103	1			T1	1		T195	1		T44	1
auto[2013265920:2147483647]	101	1			T1	1		T5	1		T23	1
auto[2147483648:2281701375]	112	1			T23	1		T24	1		T195	1
auto[2281701376:2415919103]	91	1			T21	2		T22	1		T72	1
auto[2415919104:2550136831]	110	1			T197	1		T195	1		T198	2
auto[2550136832:2684354559]	100	1			T1	1		T23	1		T40	1
auto[2684354560:2818572287]	99	1			T1	1		T23	1		T24	1
auto[2818572288:2952790015]	102	1			T23	1		T40	1		T111	1
auto[2952790016:3087007743]	90	1			T1	2		T111	1		T51	1
auto[3087007744:3221225471]	110	1			T44	1		T22	1		T71	1
auto[3221225472:3355443199]	88	1			T24	1		T197	1		T195	1
auto[3355443200:3489660927]	118	1			T3	1		T200	2		T21	2
auto[3489660928:3623878655]	88	1			T44	1		T111	1		T196	1
auto[3623878656:3758096383]	104	1			T13	1		T198	1		T36	1
auto[3758096384:3892314111]	112	1			T197	1		T21	1		T22	1
auto[3892314112:4026531839]	91	1			T21	1		T198	1		T45	1
auto[4026531840:4160749567]	86	1			T14	1		T44	1		T196	1
auto[4160749568:4294967295]	90	1			T13	1		T195	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T23	1		T82	1		T346	1
auto[0:134217727]	auto[1]	59	1			T3	1		T198	1		T82	1
auto[134217728:268435455]	auto[0]	44	1			T199	1		T51	1		T36	1
auto[134217728:268435455]	auto[1]	59	1			T1	1		T195	1		T44	1
auto[268435456:402653183]	auto[0]	44	1			T22	1		T111	1		T71	1
auto[268435456:402653183]	auto[1]	61	1			T200	1		T51	1		T56	1
auto[402653184:536870911]	auto[0]	44	1			T51	2		T210	1		T192	1
auto[402653184:536870911]	auto[1]	60	1			T72	1		T63	1		T64	1
auto[536870912:671088639]	auto[0]	60	1			T5	1		T41	1		T82	1
auto[536870912:671088639]	auto[1]	59	1			T5	1		T111	1		T51	1
auto[671088640:805306367]	auto[0]	49	1			T201	1		T22	1		T210	1
auto[671088640:805306367]	auto[1]	55	1			T200	1		T195	1		T44	1
auto[805306368:939524095]	auto[0]	62	1			T21	1		T22	1		T89	1
auto[805306368:939524095]	auto[1]	52	1			T24	1		T44	1		T45	1
auto[939524096:1073741823]	auto[0]	53	1			T1	1		T72	1		T56	1
auto[939524096:1073741823]	auto[1]	47	1			T195	1		T48	1		T64	1
auto[1073741824:1207959551]	auto[0]	51	1			T405	1		T101	1		T334	1
auto[1073741824:1207959551]	auto[1]	51	1			T199	1		T200	1		T204	1
auto[1207959552:1342177279]	auto[0]	48	1			T201	1		T22	1		T51	1
auto[1207959552:1342177279]	auto[1]	55	1			T48	1		T92	1		T93	1
auto[1342177280:1476395007]	auto[0]	43	1			T197	1		T21	1		T41	1
auto[1342177280:1476395007]	auto[1]	63	1			T44	1		T51	1		T56	1
auto[1476395008:1610612735]	auto[0]	60	1			T44	1		T51	1		T48	2
auto[1476395008:1610612735]	auto[1]	63	1			T44	1		T51	1		T346	1
auto[1610612736:1744830463]	auto[0]	49	1			T21	1		T89	1		T405	1
auto[1610612736:1744830463]	auto[1]	47	1			T24	1		T64	1		T8	1
auto[1744830464:1879048191]	auto[0]	45	1			T197	1		T48	1		T71	1
auto[1744830464:1879048191]	auto[1]	53	1			T195	1		T44	1		T45	1
auto[1879048192:2013265919]	auto[0]	51	1			T195	1		T44	1		T203	1
auto[1879048192:2013265919]	auto[1]	52	1			T1	1		T89	1		T92	1
auto[2013265920:2147483647]	auto[0]	53	1			T1	1		T5	1		T23	1
auto[2013265920:2147483647]	auto[1]	48	1			T197	1		T126	1		T213	1
auto[2147483648:2281701375]	auto[0]	61	1			T23	1		T24	1		T25	1
auto[2147483648:2281701375]	auto[1]	51	1			T195	1		T111	1		T45	1
auto[2281701376:2415919103]	auto[0]	48	1			T21	1		T22	1		T72	1
auto[2281701376:2415919103]	auto[1]	43	1			T21	1		T203	1		T137	1
auto[2415919104:2550136831]	auto[0]	50	1			T195	1		T198	1		T137	1
auto[2415919104:2550136831]	auto[1]	60	1			T197	1		T198	1		T203	1
auto[2550136832:2684354559]	auto[0]	49	1			T1	1		T41	1		T82	1
auto[2550136832:2684354559]	auto[1]	51	1			T23	1		T40	1		T44	2
auto[2684354560:2818572287]	auto[0]	47	1			T24	1		T111	1		T56	1
auto[2684354560:2818572287]	auto[1]	52	1			T1	1		T23	1		T51	1
auto[2818572288:2952790015]	auto[0]	37	1			T23	1		T25	1		T36	1
auto[2818572288:2952790015]	auto[1]	65	1			T40	1		T111	1		T41	1
auto[2952790016:3087007743]	auto[0]	46	1			T111	1		T51	1		T36	1
auto[2952790016:3087007743]	auto[1]	44	1			T1	2		T71	1		T93	1
auto[3087007744:3221225471]	auto[0]	59	1			T22	1		T71	1		T92	1
auto[3087007744:3221225471]	auto[1]	51	1			T44	1		T54	1		T55	1
auto[3221225472:3355443199]	auto[0]	39	1			T24	1		T197	1		T195	1
auto[3221225472:3355443199]	auto[1]	49	1			T51	1		T126	1		T239	1
auto[3355443200:3489660927]	auto[0]	53	1			T3	1		T51	1		T71	1
auto[3355443200:3489660927]	auto[1]	65	1			T200	2		T21	2		T51	1
auto[3489660928:3623878655]	auto[0]	37	1			T111	1		T196	1		T72	1
auto[3489660928:3623878655]	auto[1]	51	1			T44	1		T93	1		T57	1
auto[3623878656:3758096383]	auto[0]	43	1			T198	1		T36	1		T18	1
auto[3623878656:3758096383]	auto[1]	61	1			T13	1		T8	1		T105	1
auto[3758096384:3892314111]	auto[0]	54	1			T197	1		T21	1		T22	1
auto[3758096384:3892314111]	auto[1]	58	1			T210	1		T405	1		T137	1
auto[3892314112:4026531839]	auto[0]	47	1			T21	1		T198	1		T48	1
auto[3892314112:4026531839]	auto[1]	44	1			T45	1		T239	1		T42	1
auto[4026531840:4160749567]	auto[0]	36	1			T82	1		T150	1		T105	1
auto[4026531840:4160749567]	auto[1]	50	1			T14	1		T44	1		T196	1
auto[4160749568:4294967295]	auto[0]	43	1			T13	1		T195	1		T44	1
auto[4160749568:4294967295]	auto[1]	47	1			T210	1		T97	1		T64	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1558

1

T1

3

T3

1

T5

2

auto[1]

1724

1

T1

5

T3

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T200	2		T51	3		T203	1
auto[134217728:268435455]	112	1			T23	1		T21	1		T44	1
auto[268435456:402653183]	99	1			T3	1		T21	1		T41	1
auto[402653184:536870911]	101	1			T3	1		T13	1		T195	1
auto[536870912:671088639]	86	1			T197	1		T22	1		T111	1
auto[671088640:805306367]	118	1			T195	1		T51	1		T82	2
auto[805306368:939524095]	93	1			T1	1		T24	1		T195	2
auto[939524096:1073741823]	106	1			T5	1		T199	1		T44	1
auto[1073741824:1207959551]	104	1			T13	1		T197	1		T21	1
auto[1207959552:1342177279]	112	1			T197	1		T201	1		T51	1
auto[1342177280:1476395007]	115	1			T24	1		T197	1		T82	1
auto[1476395008:1610612735]	75	1			T1	1		T23	1		T25	1
auto[1610612736:1744830463]	106	1			T1	1		T5	1		T22	1
auto[1744830464:1879048191]	110	1			T1	1		T5	1		T24	1
auto[1879048192:2013265919]	109	1			T1	1		T111	1		T45	1
auto[2013265920:2147483647]	108	1			T23	1		T111	1		T100	1
auto[2147483648:2281701375]	91	1			T45	1		T81	1		T56	1
auto[2281701376:2415919103]	109	1			T200	1		T44	1		T22	1
auto[2415919104:2550136831]	113	1			T195	1		T22	1		T111	1
auto[2550136832:2684354559]	102	1			T200	2		T111	1		T25	1
auto[2684354560:2818572287]	103	1			T197	1		T21	1		T195	2
auto[2818572288:2952790015]	89	1			T199	1		T197	1		T44	1
auto[2952790016:3087007743]	111	1			T1	1		T14	1		T23	1
auto[3087007744:3221225471]	107	1			T1	1		T23	1		T198	1
auto[3221225472:3355443199]	112	1			T1	1		T21	3		T195	1
auto[3355443200:3489660927]	114	1			T201	1		T196	1		T51	2
auto[3489660928:3623878655]	105	1			T44	1		T36	1		T82	1
auto[3623878656:3758096383]	92	1			T23	1		T24	1		T40	1
auto[3758096384:3892314111]	92	1			T40	1		T21	1		T195	1
auto[3892314112:4026531839]	104	1			T195	1		T48	1		T203	1
auto[4026531840:4160749567]	93	1			T21	1		T51	1		T82	1
auto[4160749568:4294967295]	93	1			T24	1		T71	1		T210	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T200	1		T51	1		T210	1
auto[0:134217727]	auto[1]	53	1			T200	1		T51	2		T203	1
auto[134217728:268435455]	auto[0]	46	1			T36	1		T72	1		T210	1
auto[134217728:268435455]	auto[1]	66	1			T23	1		T21	1		T44	1
auto[268435456:402653183]	auto[0]	43	1			T21	1		T41	1		T210	1
auto[268435456:402653183]	auto[1]	56	1			T3	1		T36	1		T56	1
auto[402653184:536870911]	auto[0]	51	1			T3	1		T13	1		T195	1
auto[402653184:536870911]	auto[1]	50	1			T44	1		T48	1		T126	1
auto[536870912:671088639]	auto[0]	30	1			T197	1		T22	1		T41	1
auto[536870912:671088639]	auto[1]	56	1			T111	1		T51	1		T57	1
auto[671088640:805306367]	auto[0]	44	1			T82	2		T71	1		T210	1
auto[671088640:805306367]	auto[1]	74	1			T195	1		T51	1		T136	1
auto[805306368:939524095]	auto[0]	48	1			T195	2		T68	1		T136	1
auto[805306368:939524095]	auto[1]	45	1			T1	1		T24	1		T71	1
auto[939524096:1073741823]	auto[0]	45	1			T5	1		T51	1		T100	1
auto[939524096:1073741823]	auto[1]	61	1			T199	1		T44	1		T137	1
auto[1073741824:1207959551]	auto[0]	59	1			T197	1		T21	1		T44	1
auto[1073741824:1207959551]	auto[1]	45	1			T13	1		T44	2		T105	1
auto[1207959552:1342177279]	auto[0]	54	1			T201	1		T51	1		T188	1
auto[1207959552:1342177279]	auto[1]	58	1			T197	1		T92	1		T239	1
auto[1342177280:1476395007]	auto[0]	51	1			T24	1		T82	1		T89	1
auto[1342177280:1476395007]	auto[1]	64	1			T197	1		T68	1		T191	1
auto[1476395008:1610612735]	auto[0]	38	1			T1	1		T23	1		T25	1
auto[1476395008:1610612735]	auto[1]	37	1			T57	1		T239	1		T8	2
auto[1610612736:1744830463]	auto[0]	52	1			T5	1		T22	1		T36	1
auto[1610612736:1744830463]	auto[1]	54	1			T1	1		T72	1		T203	1
auto[1744830464:1879048191]	auto[0]	50	1			T72	1		T92	1		T136	1
auto[1744830464:1879048191]	auto[1]	60	1			T1	1		T5	1		T24	1
auto[1879048192:2013265919]	auto[0]	53	1			T71	1		T63	1		T54	1
auto[1879048192:2013265919]	auto[1]	56	1			T1	1		T111	1		T45	1
auto[2013265920:2147483647]	auto[0]	48	1			T111	1		T100	1		T346	1
auto[2013265920:2147483647]	auto[1]	60	1			T23	1		T64	2		T361	1
auto[2147483648:2281701375]	auto[0]	36	1			T81	1		T97	1		T411	1
auto[2147483648:2281701375]	auto[1]	55	1			T45	1		T56	1		T192	1
auto[2281701376:2415919103]	auto[0]	44	1			T22	1		T71	1		T203	1
auto[2281701376:2415919103]	auto[1]	65	1			T200	1		T44	1		T203	1
auto[2415919104:2550136831]	auto[0]	66	1			T195	1		T22	1		T111	1
auto[2415919104:2550136831]	auto[1]	47	1			T51	1		T8	2		T383	1
auto[2550136832:2684354559]	auto[0]	48	1			T111	1		T25	1		T41	1
auto[2550136832:2684354559]	auto[1]	54	1			T200	2		T56	2		T239	1
auto[2684354560:2818572287]	auto[0]	53	1			T197	1		T21	1		T195	1
auto[2684354560:2818572287]	auto[1]	50	1			T195	1		T198	1		T57	1
auto[2818572288:2952790015]	auto[0]	47	1			T199	1		T197	1		T89	1
auto[2818572288:2952790015]	auto[1]	42	1			T44	1		T196	1		T51	1
auto[2952790016:3087007743]	auto[0]	64	1			T1	1		T14	1		T23	1
auto[2952790016:3087007743]	auto[1]	47	1			T44	1		T45	1		T72	1
auto[3087007744:3221225471]	auto[0]	53	1			T23	1		T198	1		T89	1
auto[3087007744:3221225471]	auto[1]	54	1			T1	1		T203	1		T89	1
auto[3221225472:3355443199]	auto[0]	54	1			T1	1		T21	1		T41	1
auto[3221225472:3355443199]	auto[1]	58	1			T21	2		T195	1		T44	1
auto[3355443200:3489660927]	auto[0]	49	1			T89	1		T405	1		T8	1
auto[3355443200:3489660927]	auto[1]	65	1			T201	1		T196	1		T51	2
auto[3489660928:3623878655]	auto[0]	55	1			T44	1		T36	1		T82	1
auto[3489660928:3623878655]	auto[1]	50	1			T8	2		T321	1		T28	1
auto[3623878656:3758096383]	auto[0]	47	1			T23	1		T24	1		T41	1
auto[3623878656:3758096383]	auto[1]	45	1			T40	1		T44	1		T37	1
auto[3758096384:3892314111]	auto[0]	47	1			T21	1		T195	1		T89	1
auto[3758096384:3892314111]	auto[1]	45	1			T40	1		T205	1		T91	1
auto[3892314112:4026531839]	auto[0]	54	1			T195	1		T48	1		T203	1
auto[3892314112:4026531839]	auto[1]	50	1			T204	1		T326	1		T205	1
auto[4026531840:4160749567]	auto[0]	46	1			T21	1		T82	1		T334	1
auto[4026531840:4160749567]	auto[1]	47	1			T51	1		T48	1		T210	1
auto[4160749568:4294967295]	auto[0]	38	1			T71	1		T210	1		T346	1
auto[4160749568:4294967295]	auto[1]	55	1			T24	1		T63	1		T192	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1571

1

T1

3

T3

1

T5

2

auto[1]

1710

1

T1

5

T3

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T81	1		T48	1		T72	1
auto[134217728:268435455]	98	1			T200	1		T22	1		T51	1
auto[268435456:402653183]	94	1			T5	1		T40	1		T51	1
auto[402653184:536870911]	109	1			T199	1		T41	1		T196	1
auto[536870912:671088639]	99	1			T197	1		T200	1		T195	1
auto[671088640:805306367]	105	1			T1	1		T21	1		T51	2
auto[805306368:939524095]	80	1			T111	1		T198	1		T82	1
auto[939524096:1073741823]	100	1			T197	1		T21	1		T56	1
auto[1073741824:1207959551]	104	1			T22	1		T51	1		T36	1
auto[1207959552:1342177279]	109	1			T1	1		T197	1		T200	1
auto[1342177280:1476395007]	111	1			T1	1		T40	1		T22	1
auto[1476395008:1610612735]	99	1			T21	1		T44	1		T111	1
auto[1610612736:1744830463]	93	1			T44	2		T198	1		T71	1
auto[1744830464:1879048191]	106	1			T5	1		T23	1		T198	1
auto[1879048192:2013265919]	117	1			T23	1		T111	1		T51	1
auto[2013265920:2147483647]	87	1			T1	1		T21	1		T195	1
auto[2147483648:2281701375]	110	1			T1	1		T23	1		T195	1
auto[2281701376:2415919103]	100	1			T111	1		T36	1		T405	1
auto[2415919104:2550136831]	109	1			T200	1		T22	1		T51	1
auto[2550136832:2684354559]	111	1			T13	1		T23	1		T24	1
auto[2684354560:2818572287]	111	1			T3	1		T24	1		T197	1
auto[2818572288:2952790015]	86	1			T200	1		T44	2		T36	1
auto[2952790016:3087007743]	99	1			T23	1		T24	1		T195	1
auto[3087007744:3221225471]	106	1			T3	1		T197	1		T195	2
auto[3221225472:3355443199]	116	1			T14	1		T24	1		T197	1
auto[3355443200:3489660927]	102	1			T1	1		T201	1		T22	1
auto[3489660928:3623878655]	97	1			T1	1		T21	1		T195	2
auto[3623878656:3758096383]	114	1			T1	1		T111	1		T51	1
auto[3758096384:3892314111]	97	1			T5	1		T21	1		T44	1
auto[3892314112:4026531839]	104	1			T23	1		T199	1		T21	1
auto[4026531840:4160749567]	101	1			T201	1		T196	1		T36	1
auto[4160749568:4294967295]	106	1			T13	1		T24	1		T21	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T81	1		T72	1		T89	1
auto[0:134217727]	auto[1]	52	1			T48	1		T57	1		T405	1
auto[134217728:268435455]	auto[0]	50	1			T22	1		T51	1		T82	1
auto[134217728:268435455]	auto[1]	48	1			T200	1		T137	1		T8	2
auto[268435456:402653183]	auto[0]	52	1			T5	1		T51	1		T100	2
auto[268435456:402653183]	auto[1]	42	1			T40	1		T72	1		T203	1
auto[402653184:536870911]	auto[0]	61	1			T199	1		T41	1		T196	1
auto[402653184:536870911]	auto[1]	48	1			T239	1		T37	1		T243	1
auto[536870912:671088639]	auto[0]	39	1			T195	1		T92	1		T93	1
auto[536870912:671088639]	auto[1]	60	1			T197	1		T200	1		T346	1
auto[671088640:805306367]	auto[0]	45	1			T1	1		T21	1		T203	1
auto[671088640:805306367]	auto[1]	60	1			T51	2		T203	1		T56	1
auto[805306368:939524095]	auto[0]	43	1			T111	1		T198	1		T82	1
auto[805306368:939524095]	auto[1]	37	1			T137	1		T8	1		T105	2
auto[939524096:1073741823]	auto[0]	60	1			T197	1		T21	1		T56	1
auto[939524096:1073741823]	auto[1]	40	1			T136	1		T8	4		T257	1
auto[1073741824:1207959551]	auto[0]	52	1			T22	1		T51	1		T36	1
auto[1073741824:1207959551]	auto[1]	52	1			T203	2		T255	1		T54	1
auto[1207959552:1342177279]	auto[0]	44	1			T197	1		T51	1		T150	1
auto[1207959552:1342177279]	auto[1]	65	1			T1	1		T200	1		T41	1
auto[1342177280:1476395007]	auto[0]	46	1			T22	1		T136	1		T8	2
auto[1342177280:1476395007]	auto[1]	65	1			T1	1		T40	1		T72	1
auto[1476395008:1610612735]	auto[0]	53	1			T21	1		T111	1		T82	1
auto[1476395008:1610612735]	auto[1]	46	1			T44	1		T45	1		T82	1
auto[1610612736:1744830463]	auto[0]	43	1			T44	1		T71	1		T101	1
auto[1610612736:1744830463]	auto[1]	50	1			T44	1		T198	1		T192	1
auto[1744830464:1879048191]	auto[0]	53	1			T23	1		T82	2		T71	1
auto[1744830464:1879048191]	auto[1]	53	1			T5	1		T198	1		T205	1
auto[1879048192:2013265919]	auto[0]	56	1			T23	1		T51	1		T82	1
auto[1879048192:2013265919]	auto[1]	61	1			T111	1		T8	1		T117	1
auto[2013265920:2147483647]	auto[0]	41	1			T21	1		T195	1		T22	1
auto[2013265920:2147483647]	auto[1]	46	1			T1	1		T92	1		T57	1
auto[2147483648:2281701375]	auto[0]	54	1			T23	1		T195	1		T48	2
auto[2147483648:2281701375]	auto[1]	56	1			T1	1		T198	1		T56	1
auto[2281701376:2415919103]	auto[0]	43	1			T405	1		T101	1		T97	1
auto[2281701376:2415919103]	auto[1]	57	1			T111	1		T36	1		T64	1
auto[2415919104:2550136831]	auto[0]	51	1			T200	1		T22	1		T51	1
auto[2415919104:2550136831]	auto[1]	58	1			T126	2		T93	2		T105	1
auto[2550136832:2684354559]	auto[0]	45	1			T22	1		T8	1		T127	1
auto[2550136832:2684354559]	auto[1]	66	1			T13	1		T23	1		T24	1
auto[2684354560:2818572287]	auto[0]	56	1			T24	1		T197	1		T21	1
auto[2684354560:2818572287]	auto[1]	55	1			T3	1		T51	1		T45	1
auto[2818572288:2952790015]	auto[0]	41	1			T36	1		T210	2		T100	1
auto[2818572288:2952790015]	auto[1]	45	1			T200	1		T44	2		T204	1
auto[2952790016:3087007743]	auto[0]	42	1			T23	1		T24	1		T195	1
auto[2952790016:3087007743]	auto[1]	57	1			T51	1		T64	1		T8	5
auto[3087007744:3221225471]	auto[0]	55	1			T3	1		T197	1		T198	1
auto[3087007744:3221225471]	auto[1]	51	1			T195	2		T136	1		T205	1
auto[3221225472:3355443199]	auto[0]	54	1			T197	1		T41	1		T89	1
auto[3221225472:3355443199]	auto[1]	62	1			T14	1		T24	1		T44	2
auto[3355443200:3489660927]	auto[0]	46	1			T1	1		T201	1		T22	1
auto[3355443200:3489660927]	auto[1]	56	1			T41	1		T51	1		T126	1
auto[3489660928:3623878655]	auto[0]	54	1			T195	2		T25	1		T56	1
auto[3489660928:3623878655]	auto[1]	43	1			T1	1		T21	1		T44	1
auto[3623878656:3758096383]	auto[0]	59	1			T1	1		T72	1		T405	1
auto[3623878656:3758096383]	auto[1]	55	1			T111	1		T51	1		T204	1
auto[3758096384:3892314111]	auto[0]	50	1			T5	1		T21	1		T44	1
auto[3758096384:3892314111]	auto[1]	47	1			T45	1		T210	1		T93	1
auto[3892314112:4026531839]	auto[0]	44	1			T199	1		T195	1		T89	2
auto[3892314112:4026531839]	auto[1]	60	1			T23	1		T21	1		T44	2
auto[4026531840:4160749567]	auto[0]	43	1			T36	1		T346	1		T192	1
auto[4026531840:4160749567]	auto[1]	58	1			T201	1		T196	1		T203	1
auto[4160749568:4294967295]	auto[0]	47	1			T13	1		T195	1		T44	1
auto[4160749568:4294967295]	auto[1]	59	1			T24	1		T21	1		T44	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1565

1

T1

3

T3

1

T5

2

auto[1]

1717

1

T1

5

T3

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	85	1			T195	1		T198	1		T51	1
auto[134217728:268435455]	90	1			T24	1		T22	1		T196	1
auto[268435456:402653183]	101	1			T44	2		T89	1		T101	1
auto[402653184:536870911]	112	1			T1	1		T3	1		T51	1
auto[536870912:671088639]	117	1			T14	1		T23	1		T111	1
auto[671088640:805306367]	96	1			T1	1		T199	1		T25	1
auto[805306368:939524095]	90	1			T200	1		T44	1		T48	1
auto[939524096:1073741823]	101	1			T1	1		T197	1		T44	1
auto[1073741824:1207959551]	91	1			T23	2		T195	1		T44	1
auto[1207959552:1342177279]	104	1			T40	1		T198	1		T196	1
auto[1342177280:1476395007]	97	1			T82	1		T100	1		T89	1
auto[1476395008:1610612735]	93	1			T44	1		T51	2		T346	1
auto[1610612736:1744830463]	103	1			T40	1		T48	1		T93	1
auto[1744830464:1879048191]	102	1			T1	1		T23	1		T44	1
auto[1879048192:2013265919]	107	1			T24	1		T21	2		T201	1
auto[2013265920:2147483647]	120	1			T13	1		T21	1		T195	1
auto[2147483648:2281701375]	91	1			T5	1		T21	1		T346	1
auto[2281701376:2415919103]	109	1			T199	1		T200	1		T111	1
auto[2415919104:2550136831]	101	1			T1	1		T41	1		T82	1
auto[2550136832:2684354559]	98	1			T195	1		T25	1		T51	1
auto[2684354560:2818572287]	107	1			T24	1		T21	1		T195	1
auto[2818572288:2952790015]	106	1			T200	1		T195	1		T22	1
auto[2952790016:3087007743]	108	1			T23	1		T21	1		T44	1
auto[3087007744:3221225471]	112	1			T3	1		T5	1		T13	1
auto[3221225472:3355443199]	96	1			T197	1		T71	1		T210	1
auto[3355443200:3489660927]	112	1			T24	1		T197	1		T195	1
auto[3489660928:3623878655]	99	1			T21	1		T195	1		T22	1
auto[3623878656:3758096383]	110	1			T1	1		T197	1		T45	1
auto[3758096384:3892314111]	126	1			T1	1		T5	1		T21	2
auto[3892314112:4026531839]	99	1			T44	1		T111	1		T36	1
auto[4026531840:4160749567]	102	1			T1	1		T197	1		T200	1
auto[4160749568:4294967295]	97	1			T23	1		T200	1		T195	1