Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2912

1

T1

3

T3

1

T5

3

auto[1]

254

1

T14

4

T111

7

T126

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T23	1		T21	2		T111	1
auto[134217728:268435455]	100	1			T40	1		T21	1		T195	2
auto[268435456:402653183]	102	1			T13	1		T23	1		T44	1
auto[402653184:536870911]	108	1			T24	1		T200	1		T44	1
auto[536870912:671088639]	107	1			T1	1		T24	1		T199	1
auto[671088640:805306367]	102	1			T21	1		T195	2		T22	1
auto[805306368:939524095]	94	1			T25	1		T89	1		T346	1
auto[939524096:1073741823]	102	1			T23	1		T44	1		T72	1
auto[1073741824:1207959551]	93	1			T24	1		T195	2		T111	1
auto[1207959552:1342177279]	96	1			T5	2		T201	1		T198	1
auto[1342177280:1476395007]	113	1			T197	1		T21	1		T71	1
auto[1476395008:1610612735]	107	1			T111	1		T82	1		T93	1
auto[1610612736:1744830463]	95	1			T5	1		T23	1		T195	1
auto[1744830464:1879048191]	90	1			T1	1		T200	1		T22	1
auto[1879048192:2013265919]	84	1			T14	1		T111	1		T72	1
auto[2013265920:2147483647]	93	1			T199	1		T197	1		T51	1
auto[2147483648:2281701375]	104	1			T14	1		T21	1		T51	1
auto[2281701376:2415919103]	95	1			T23	1		T111	2		T82	1
auto[2415919104:2550136831]	108	1			T14	1		T197	1		T21	1
auto[2550136832:2684354559]	114	1			T197	1		T44	2		T111	1
auto[2684354560:2818572287]	101	1			T1	1		T23	1		T40	1
auto[2818572288:2952790015]	86	1			T44	1		T111	1		T196	1
auto[2952790016:3087007743]	106	1			T3	1		T200	1		T21	1
auto[3087007744:3221225471]	103	1			T82	1		T203	1		T89	1
auto[3221225472:3355443199]	107	1			T200	1		T82	1		T71	1
auto[3355443200:3489660927]	93	1			T14	1		T197	1		T21	1
auto[3489660928:3623878655]	93	1			T200	1		T195	1		T44	1
auto[3623878656:3758096383]	90	1			T14	1		T44	1		T22	1
auto[3758096384:3892314111]	92	1			T13	1		T195	1		T22	1
auto[3892314112:4026531839]	90	1			T44	1		T198	1		T45	1
auto[4026531840:4160749567]	93	1			T22	1		T41	1		T45	1
auto[4160749568:4294967295]	105	1			T24	2		T111	2		T196	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	94	1			T23	1		T21	2		T111	1
auto[0:134217727]	auto[1]	6	1			T126	1		T250	1		T282	1
auto[134217728:268435455]	auto[0]	92	1			T40	1		T21	1		T195	2
auto[134217728:268435455]	auto[1]	8	1			T126	1		T137	1		T128	1
auto[268435456:402653183]	auto[0]	92	1			T13	1		T23	1		T44	1
auto[268435456:402653183]	auto[1]	10	1			T331	2		T261	1		T392	1
auto[402653184:536870911]	auto[0]	104	1			T24	1		T200	1		T44	1
auto[402653184:536870911]	auto[1]	4	1			T126	1		T136	1		T392	1
auto[536870912:671088639]	auto[0]	95	1			T1	1		T24	1		T199	1
auto[536870912:671088639]	auto[1]	12	1			T136	1		T128	2		T252	1
auto[671088640:805306367]	auto[0]	94	1			T21	1		T195	2		T22	1
auto[671088640:805306367]	auto[1]	8	1			T331	1		T385	1		T407	2
auto[805306368:939524095]	auto[0]	85	1			T25	1		T89	1		T346	1
auto[805306368:939524095]	auto[1]	9	1			T137	2		T128	2		T408	1
auto[939524096:1073741823]	auto[0]	93	1			T23	1		T44	1		T72	1
auto[939524096:1073741823]	auto[1]	9	1			T137	1		T257	1		T129	1
auto[1073741824:1207959551]	auto[0]	86	1			T24	1		T195	2		T198	1
auto[1073741824:1207959551]	auto[1]	7	1			T111	1		T276	1		T328	1
auto[1207959552:1342177279]	auto[0]	89	1			T5	2		T201	1		T198	1
auto[1207959552:1342177279]	auto[1]	7	1			T385	1		T407	1		T408	2
auto[1342177280:1476395007]	auto[0]	104	1			T197	1		T21	1		T71	1
auto[1342177280:1476395007]	auto[1]	9	1			T137	2		T128	1		T300	1
auto[1476395008:1610612735]	auto[0]	94	1			T82	1		T93	1		T346	1
auto[1476395008:1610612735]	auto[1]	13	1			T111	1		T128	1		T300	1
auto[1610612736:1744830463]	auto[0]	92	1			T5	1		T23	1		T195	1
auto[1610612736:1744830463]	auto[1]	3	1			T111	1		T406	1		T419	1
auto[1744830464:1879048191]	auto[0]	88	1			T1	1		T200	1		T22	1
auto[1744830464:1879048191]	auto[1]	2	1			T331	2		-	-		-	-
auto[1879048192:2013265919]	auto[0]	73	1			T72	1		T92	1		T334	1
auto[1879048192:2013265919]	auto[1]	11	1			T14	1		T111	1		T137	1
auto[2013265920:2147483647]	auto[0]	83	1			T199	1		T197	1		T51	1
auto[2013265920:2147483647]	auto[1]	10	1			T126	1		T129	1		T331	1
auto[2147483648:2281701375]	auto[0]	94	1			T21	1		T51	1		T82	1
auto[2147483648:2281701375]	auto[1]	10	1			T14	1		T128	2		T300	1
auto[2281701376:2415919103]	auto[0]	88	1			T23	1		T111	2		T82	1
auto[2281701376:2415919103]	auto[1]	7	1			T137	1		T128	1		T250	1
auto[2415919104:2550136831]	auto[0]	102	1			T14	1		T197	1		T21	1
auto[2415919104:2550136831]	auto[1]	6	1			T129	1		T250	1		T422	1
auto[2550136832:2684354559]	auto[0]	100	1			T197	1		T44	2		T111	1
auto[2550136832:2684354559]	auto[1]	14	1			T257	1		T250	1		T331	2
auto[2684354560:2818572287]	auto[0]	94	1			T1	1		T23	1		T40	1
auto[2684354560:2818572287]	auto[1]	7	1			T111	1		T362	1		T407	1
auto[2818572288:2952790015]	auto[0]	79	1			T44	1		T111	1		T196	1
auto[2818572288:2952790015]	auto[1]	7	1			T136	1		T128	1		T282	2
auto[2952790016:3087007743]	auto[0]	97	1			T3	1		T200	1		T21	1
auto[2952790016:3087007743]	auto[1]	9	1			T362	1		T282	1		T406	2
auto[3087007744:3221225471]	auto[0]	96	1			T82	1		T203	1		T89	1
auto[3087007744:3221225471]	auto[1]	7	1			T128	2		T406	1		T408	2
auto[3221225472:3355443199]	auto[0]	97	1			T200	1		T82	1		T71	1
auto[3221225472:3355443199]	auto[1]	10	1			T126	1		T252	1		T386	1
auto[3355443200:3489660927]	auto[0]	84	1			T197	1		T21	1		T195	1
auto[3355443200:3489660927]	auto[1]	9	1			T14	1		T111	1		T137	1
auto[3489660928:3623878655]	auto[0]	89	1			T200	1		T195	1		T44	1
auto[3489660928:3623878655]	auto[1]	4	1			T407	1		T238	1		T371	1
auto[3623878656:3758096383]	auto[0]	77	1			T44	1		T22	1		T203	1
auto[3623878656:3758096383]	auto[1]	13	1			T14	1		T250	2		T331	2
auto[3758096384:3892314111]	auto[0]	87	1			T13	1		T195	1		T22	1
auto[3758096384:3892314111]	auto[1]	5	1			T129	1		T406	1		T408	1
auto[3892314112:4026531839]	auto[0]	85	1			T44	1		T198	1		T45	1
auto[3892314112:4026531839]	auto[1]	5	1			T331	1		T252	1		T237	1
auto[4026531840:4160749567]	auto[0]	87	1			T22	1		T41	1		T45	1
auto[4026531840:4160749567]	auto[1]	6	1			T137	2		T129	1		T250	1
auto[4160749568:4294967295]	auto[0]	98	1			T24	2		T111	1		T196	1
auto[4160749568:4294967295]	auto[1]	7	1			T111	1		T137	1		T331	1