Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6933

1

T1

6

T3

2

T5

12

auto[1]

264

1

T14

4

T111

1

T126

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2948	1			T1	3		T3	1		T5	7
auto[134217728:268435455]	176	1			T14	1		T23	2		T24	1
auto[268435456:402653183]	163	1			T1	1		T23	1		T21	2
auto[402653184:536870911]	143	1			T44	1		T82	1		T203	2
auto[536870912:671088639]	150	1			T5	1		T13	1		T23	1
auto[671088640:805306367]	152	1			T21	1		T195	1		T44	1
auto[805306368:939524095]	135	1			T21	1		T198	1		T51	2
auto[939524096:1073741823]	125	1			T24	1		T40	1		T41	1
auto[1073741824:1207959551]	138	1			T1	1		T44	1		T111	1
auto[1207959552:1342177279]	128	1			T13	1		T23	1		T197	1
auto[1342177280:1476395007]	135	1			T14	1		T195	1		T44	1
auto[1476395008:1610612735]	140	1			T14	2		T24	1		T195	1
auto[1610612736:1744830463]	137	1			T3	1		T13	1		T200	1
auto[1744830464:1879048191]	127	1			T5	1		T23	1		T44	2
auto[1879048192:2013265919]	120	1			T23	1		T24	1		T198	1
auto[2013265920:2147483647]	126	1			T197	1		T200	1		T22	1
auto[2147483648:2281701375]	125	1			T199	2		T195	2		T44	2
auto[2281701376:2415919103]	121	1			T1	1		T21	1		T195	2
auto[2415919104:2550136831]	139	1			T5	1		T14	1		T24	1
auto[2550136832:2684354559]	133	1			T23	1		T40	1		T21	2
auto[2684354560:2818572287]	124	1			T195	2		T44	1		T36	1
auto[2818572288:2952790015]	119	1			T23	2		T197	1		T198	2
auto[2952790016:3087007743]	138	1			T23	1		T195	1		T44	1
auto[3087007744:3221225471]	126	1			T200	1		T195	1		T41	1
auto[3221225472:3355443199]	141	1			T200	1		T22	1		T25	1
auto[3355443200:3489660927]	124	1			T5	1		T23	1		T197	1
auto[3489660928:3623878655]	123	1			T197	1		T21	1		T22	1
auto[3623878656:3758096383]	167	1			T200	1		T195	1		T198	2
auto[3758096384:3892314111]	128	1			T44	1		T201	1		T51	1
auto[3892314112:4026531839]	140	1			T24	1		T197	1		T51	1
auto[4026531840:4160749567]	156	1			T14	1		T195	2		T44	1
auto[4160749568:4294967295]	150	1			T5	1		T21	1		T51	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2942	1			T1	3		T3	1		T5	7
auto[0:134217727]	auto[1]	6	1			T111	1		T128	1		T252	1
auto[134217728:268435455]	auto[0]	169	1			T14	1		T23	2		T24	1
auto[134217728:268435455]	auto[1]	7	1			T126	1		T261	1		T252	1
auto[268435456:402653183]	auto[0]	154	1			T1	1		T23	1		T21	2
auto[268435456:402653183]	auto[1]	9	1			T126	1		T137	1		T257	1
auto[402653184:536870911]	auto[0]	129	1			T44	1		T82	1		T203	2
auto[402653184:536870911]	auto[1]	14	1			T136	1		T137	1		T243	1
auto[536870912:671088639]	auto[0]	143	1			T5	1		T13	1		T23	1
auto[536870912:671088639]	auto[1]	7	1			T137	1		T128	1		T408	1
auto[671088640:805306367]	auto[0]	143	1			T21	1		T195	1		T44	1
auto[671088640:805306367]	auto[1]	9	1			T136	1		T300	1		T331	2
auto[805306368:939524095]	auto[0]	124	1			T21	1		T198	1		T51	2
auto[805306368:939524095]	auto[1]	11	1			T243	1		T128	2		T129	2
auto[939524096:1073741823]	auto[0]	122	1			T24	1		T40	1		T41	1
auto[939524096:1073741823]	auto[1]	3	1			T300	1		T344	1		T357	1
auto[1073741824:1207959551]	auto[0]	128	1			T1	1		T44	1		T111	1
auto[1073741824:1207959551]	auto[1]	10	1			T137	1		T128	1		T250	1
auto[1207959552:1342177279]	auto[0]	120	1			T13	1		T23	1		T197	1
auto[1207959552:1342177279]	auto[1]	8	1			T126	1		T300	2		T385	1
auto[1342177280:1476395007]	auto[0]	127	1			T195	1		T44	1		T45	1
auto[1342177280:1476395007]	auto[1]	8	1			T14	1		T137	1		T300	1
auto[1476395008:1610612735]	auto[0]	136	1			T14	1		T24	1		T195	1
auto[1476395008:1610612735]	auto[1]	4	1			T14	1		T129	1		T407	1
auto[1610612736:1744830463]	auto[0]	130	1			T3	1		T13	1		T200	1
auto[1610612736:1744830463]	auto[1]	7	1			T137	1		T300	1		T331	1
auto[1744830464:1879048191]	auto[0]	119	1			T5	1		T23	1		T44	2
auto[1744830464:1879048191]	auto[1]	8	1			T250	1		T385	1		T407	1
auto[1879048192:2013265919]	auto[0]	111	1			T23	1		T24	1		T198	1
auto[1879048192:2013265919]	auto[1]	9	1			T137	1		T243	1		T331	1
auto[2013265920:2147483647]	auto[0]	114	1			T197	1		T200	1		T22	1
auto[2013265920:2147483647]	auto[1]	12	1			T137	1		T300	1		T331	2
auto[2147483648:2281701375]	auto[0]	114	1			T199	2		T195	2		T44	2
auto[2147483648:2281701375]	auto[1]	11	1			T250	1		T331	1		T386	1
auto[2281701376:2415919103]	auto[0]	114	1			T1	1		T21	1		T195	2
auto[2281701376:2415919103]	auto[1]	7	1			T243	1		T408	1		T276	1
auto[2415919104:2550136831]	auto[0]	136	1			T5	1		T24	1		T21	1
auto[2415919104:2550136831]	auto[1]	3	1			T14	1		T407	1		T414	1
auto[2550136832:2684354559]	auto[0]	126	1			T23	1		T40	1		T21	2
auto[2550136832:2684354559]	auto[1]	7	1			T408	1		T372	1		T323	1
auto[2684354560:2818572287]	auto[0]	120	1			T195	2		T44	1		T36	1
auto[2684354560:2818572287]	auto[1]	4	1			T128	1		T409	1		T406	1
auto[2818572288:2952790015]	auto[0]	111	1			T23	2		T197	1		T198	2
auto[2818572288:2952790015]	auto[1]	8	1			T126	1		T129	1		T331	1
auto[2952790016:3087007743]	auto[0]	130	1			T23	1		T195	1		T44	1
auto[2952790016:3087007743]	auto[1]	8	1			T300	1		T362	1		T252	2
auto[3087007744:3221225471]	auto[0]	118	1			T200	1		T195	1		T41	1
auto[3087007744:3221225471]	auto[1]	8	1			T137	1		T129	1		T282	1
auto[3221225472:3355443199]	auto[0]	133	1			T200	1		T22	1		T25	1
auto[3221225472:3355443199]	auto[1]	8	1			T252	1		T282	1		T409	1
auto[3355443200:3489660927]	auto[0]	118	1			T5	1		T23	1		T197	1
auto[3355443200:3489660927]	auto[1]	6	1			T137	1		T128	1		T406	1
auto[3489660928:3623878655]	auto[0]	110	1			T197	1		T21	1		T22	1
auto[3489660928:3623878655]	auto[1]	13	1			T137	1		T257	2		T128	1
auto[3623878656:3758096383]	auto[0]	152	1			T200	1		T195	1		T198	2
auto[3623878656:3758096383]	auto[1]	15	1			T137	1		T300	1		T250	1
auto[3758096384:3892314111]	auto[0]	117	1			T44	1		T201	1		T51	1
auto[3758096384:3892314111]	auto[1]	11	1			T385	2		T386	1		T371	1
auto[3892314112:4026531839]	auto[0]	133	1			T24	1		T197	1		T51	1
auto[3892314112:4026531839]	auto[1]	7	1			T252	1		T408	1		T371	1
auto[4026531840:4160749567]	auto[0]	149	1			T195	2		T44	1		T111	1
auto[4026531840:4160749567]	auto[1]	7	1			T14	1		T126	1		T136	1
auto[4160749568:4294967295]	auto[0]	141	1			T5	1		T21	1		T51	1
auto[4160749568:4294967295]	auto[1]	9	1			T126	1		T300	1		T331	1