dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4604 1 T1 10 T3 2 T5 6
auto[1] 1958 1 T1 6 T3 2 T13 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 206 1 T1 2 T23 2 T197 2
auto[134217728:268435455] 240 1 T14 2 T23 2 T24 2
auto[268435456:402653183] 198 1 T1 2 T25 2 T196 2
auto[402653184:536870911] 232 1 T13 2 T23 2 T201 2
auto[536870912:671088639] 184 1 T195 4 T22 2 T36 2
auto[671088640:805306367] 198 1 T197 4 T44 2 T22 2
auto[805306368:939524095] 182 1 T1 4 T44 2 T198 2
auto[939524096:1073741823] 236 1 T1 2 T13 2 T23 2
auto[1073741824:1207959551] 218 1 T44 2 T111 2 T25 2
auto[1207959552:1342177279] 210 1 T111 2 T48 4 T56 2
auto[1342177280:1476395007] 178 1 T5 2 T21 2 T44 2
auto[1476395008:1610612735] 194 1 T1 2 T199 2 T44 2
auto[1610612736:1744830463] 196 1 T44 2 T22 2 T51 2
auto[1744830464:1879048191] 202 1 T5 2 T24 2 T36 2
auto[1879048192:2013265919] 230 1 T71 2 T72 2 T239 2
auto[2013265920:2147483647] 198 1 T24 2 T48 2 T72 2
auto[2147483648:2281701375] 212 1 T5 2 T21 2 T44 2
auto[2281701376:2415919103] 216 1 T24 2 T195 2 T51 2
auto[2415919104:2550136831] 206 1 T22 2 T71 2 T72 4
auto[2550136832:2684354559] 202 1 T3 2 T197 2 T195 2
auto[2684354560:2818572287] 196 1 T1 2 T21 4 T195 2
auto[2818572288:2952790015] 190 1 T23 2 T40 2 T21 2
auto[2952790016:3087007743] 194 1 T82 2 T203 2 T100 2
auto[3087007744:3221225471] 244 1 T23 2 T195 4 T111 4
auto[3221225472:3355443199] 200 1 T1 2 T3 2 T24 2
auto[3355443200:3489660927] 226 1 T200 2 T21 2 T198 2
auto[3489660928:3623878655] 180 1 T44 2 T48 2 T72 2
auto[3623878656:3758096383] 220 1 T199 2 T44 2 T196 2
auto[3758096384:3892314111] 200 1 T44 4 T51 2 T36 2
auto[3892314112:4026531839] 222 1 T200 2 T21 2 T111 2
auto[4026531840:4160749567] 166 1 T197 2 T195 2 T44 2
auto[4160749568:4294967295] 186 1 T197 2 T22 2 T198 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 154 1 T197 2 T195 2 T82 4
auto[0:134217727] auto[1] 52 1 T1 2 T23 2 T200 2
auto[134217728:268435455] auto[0] 150 1 T21 2 T82 2 T90 2
auto[134217728:268435455] auto[1] 90 1 T14 2 T23 2 T24 2
auto[268435456:402653183] auto[0] 122 1 T1 2 T196 2 T56 2
auto[268435456:402653183] auto[1] 76 1 T25 2 T71 2 T93 2
auto[402653184:536870911] auto[0] 156 1 T201 2 T51 2 T48 2
auto[402653184:536870911] auto[1] 76 1 T13 2 T23 2 T111 2
auto[536870912:671088639] auto[0] 138 1 T195 4 T22 2 T82 2
auto[536870912:671088639] auto[1] 46 1 T36 2 T398 2 T296 2
auto[671088640:805306367] auto[0] 148 1 T197 4 T44 2 T22 2
auto[671088640:805306367] auto[1] 50 1 T82 2 T8 8 T52 2
auto[805306368:939524095] auto[0] 132 1 T1 4 T44 2 T198 2
auto[805306368:939524095] auto[1] 50 1 T41 2 T405 2 T105 2
auto[939524096:1073741823] auto[0] 184 1 T1 2 T13 2 T200 4
auto[939524096:1073741823] auto[1] 52 1 T23 2 T41 2 T51 2
auto[1073741824:1207959551] auto[0] 156 1 T111 2 T48 2 T346 2
auto[1073741824:1207959551] auto[1] 62 1 T44 2 T25 2 T41 2
auto[1207959552:1342177279] auto[0] 148 1 T111 2 T48 4 T56 2
auto[1207959552:1342177279] auto[1] 62 1 T42 2 T321 2 T118 2
auto[1342177280:1476395007] auto[0] 124 1 T5 2 T21 2 T44 2
auto[1342177280:1476395007] auto[1] 54 1 T54 2 T19 2 T273 2
auto[1476395008:1610612735] auto[0] 114 1 T44 2 T82 2 T100 2
auto[1476395008:1610612735] auto[1] 80 1 T1 2 T199 2 T41 2
auto[1610612736:1744830463] auto[0] 132 1 T22 2 T326 2 T205 2
auto[1610612736:1744830463] auto[1] 64 1 T44 2 T51 2 T204 2
auto[1744830464:1879048191] auto[0] 146 1 T5 2 T24 2 T36 2
auto[1744830464:1879048191] auto[1] 56 1 T150 2 T105 2 T294 2
auto[1879048192:2013265919] auto[0] 156 1 T136 2 T97 2 T64 2
auto[1879048192:2013265919] auto[1] 74 1 T71 2 T72 2 T239 2
auto[2013265920:2147483647] auto[0] 140 1 T24 2 T405 2 T136 2
auto[2013265920:2147483647] auto[1] 58 1 T48 2 T72 2 T54 2
auto[2147483648:2281701375] auto[0] 152 1 T5 2 T44 2 T22 2
auto[2147483648:2281701375] auto[1] 60 1 T21 2 T8 2 T255 2
auto[2281701376:2415919103] auto[0] 178 1 T24 2 T195 2 T51 2
auto[2281701376:2415919103] auto[1] 38 1 T246 2 T380 2 T415 2
auto[2415919104:2550136831] auto[0] 144 1 T22 2 T92 2 T93 2
auto[2415919104:2550136831] auto[1] 62 1 T71 2 T72 4 T205 2
auto[2550136832:2684354559] auto[0] 148 1 T195 2 T44 2 T56 2
auto[2550136832:2684354559] auto[1] 54 1 T3 2 T197 2 T183 2
auto[2684354560:2818572287] auto[0] 130 1 T21 2 T45 2 T137 2
auto[2684354560:2818572287] auto[1] 66 1 T1 2 T21 2 T195 2
auto[2818572288:2952790015] auto[0] 136 1 T23 2 T21 2 T201 2
auto[2818572288:2952790015] auto[1] 54 1 T40 2 T101 2 T91 2
auto[2952790016:3087007743] auto[0] 126 1 T203 2 T100 2 T92 2
auto[2952790016:3087007743] auto[1] 68 1 T82 2 T8 8 T105 2
auto[3087007744:3221225471] auto[0] 178 1 T195 4 T111 4 T51 4
auto[3087007744:3221225471] auto[1] 66 1 T23 2 T41 2 T51 2
auto[3221225472:3355443199] auto[0] 148 1 T1 2 T3 2 T24 2
auto[3221225472:3355443199] auto[1] 52 1 T126 2 T37 2 T117 2
auto[3355443200:3489660927] auto[0] 150 1 T200 2 T71 4 T205 2
auto[3355443200:3489660927] auto[1] 76 1 T21 2 T198 2 T192 2
auto[3489660928:3623878655] auto[0] 132 1 T44 2 T89 2 T101 2
auto[3489660928:3623878655] auto[1] 48 1 T48 2 T72 2 T312 2
auto[3623878656:3758096383] auto[0] 156 1 T196 2 T45 2 T71 2
auto[3623878656:3758096383] auto[1] 64 1 T199 2 T44 2 T72 2
auto[3758096384:3892314111] auto[0] 148 1 T44 4 T51 2 T36 2
auto[3758096384:3892314111] auto[1] 52 1 T117 2 T304 2 T183 2
auto[3892314112:4026531839] auto[0] 142 1 T21 2 T111 2 T56 2
auto[3892314112:4026531839] auto[1] 80 1 T200 2 T8 4 T105 2
auto[4026531840:4160749567] auto[0] 108 1 T197 2 T195 2 T51 4
auto[4026531840:4160749567] auto[1] 58 1 T44 2 T210 2 T204 2
auto[4160749568:4294967295] auto[0] 128 1 T22 2 T198 2 T51 4
auto[4160749568:4294967295] auto[1] 58 1 T197 2 T405 2 T243 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%