Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.81 99.07 98.03 98.61 100.00 99.11 98.41 91.49


Total test records in report: 1078
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1007 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.398919900 Apr 04 03:37:07 PM PDT 24 Apr 04 03:37:09 PM PDT 24 553569584 ps
T1008 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1605598969 Apr 04 03:37:25 PM PDT 24 Apr 04 03:37:27 PM PDT 24 106697459 ps
T1009 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2695459010 Apr 04 03:37:39 PM PDT 24 Apr 04 03:37:42 PM PDT 24 62154782 ps
T1010 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1705896557 Apr 04 03:37:21 PM PDT 24 Apr 04 03:37:22 PM PDT 24 34702084 ps
T1011 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2532267504 Apr 04 03:37:10 PM PDT 24 Apr 04 03:37:11 PM PDT 24 14878424 ps
T1012 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3584646998 Apr 04 03:37:40 PM PDT 24 Apr 04 03:37:56 PM PDT 24 497597582 ps
T1013 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1130181913 Apr 04 03:37:40 PM PDT 24 Apr 04 03:37:41 PM PDT 24 40988405 ps
T1014 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3115863819 Apr 04 03:37:52 PM PDT 24 Apr 04 03:37:53 PM PDT 24 59034089 ps
T165 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3647176679 Apr 04 03:37:23 PM PDT 24 Apr 04 03:37:28 PM PDT 24 196906219 ps
T1015 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.68805051 Apr 04 03:37:39 PM PDT 24 Apr 04 03:37:40 PM PDT 24 113307436 ps
T1016 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1454472121 Apr 04 03:37:39 PM PDT 24 Apr 04 03:37:45 PM PDT 24 160626422 ps
T1017 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1119148734 Apr 04 03:37:55 PM PDT 24 Apr 04 03:37:56 PM PDT 24 18078036 ps
T1018 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3181299739 Apr 04 03:37:09 PM PDT 24 Apr 04 03:37:16 PM PDT 24 431686704 ps
T1019 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2559148117 Apr 04 03:37:07 PM PDT 24 Apr 04 03:37:13 PM PDT 24 204441788 ps
T1020 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.964872376 Apr 04 03:37:29 PM PDT 24 Apr 04 03:37:44 PM PDT 24 3202474126 ps
T160 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.589469247 Apr 04 03:37:23 PM PDT 24 Apr 04 03:37:34 PM PDT 24 1475034710 ps
T1021 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2739335178 Apr 04 03:37:44 PM PDT 24 Apr 04 03:37:46 PM PDT 24 153158602 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.689702644 Apr 04 03:37:07 PM PDT 24 Apr 04 03:37:08 PM PDT 24 78867883 ps
T1023 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3257548674 Apr 04 03:37:13 PM PDT 24 Apr 04 03:37:25 PM PDT 24 505343082 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.4056444321 Apr 04 03:37:11 PM PDT 24 Apr 04 03:37:16 PM PDT 24 487486619 ps
T1025 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4073517053 Apr 04 03:37:24 PM PDT 24 Apr 04 03:37:25 PM PDT 24 28388149 ps
T1026 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2557654771 Apr 04 03:37:00 PM PDT 24 Apr 04 03:37:02 PM PDT 24 34444052 ps
T1027 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2582991029 Apr 04 03:36:56 PM PDT 24 Apr 04 03:36:59 PM PDT 24 31445527 ps
T1028 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3048512908 Apr 04 03:37:54 PM PDT 24 Apr 04 03:37:55 PM PDT 24 11546164 ps
T1029 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1798236775 Apr 04 03:37:00 PM PDT 24 Apr 04 03:37:03 PM PDT 24 694431239 ps
T1030 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.603796270 Apr 04 03:37:56 PM PDT 24 Apr 04 03:37:57 PM PDT 24 10541882 ps
T1031 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3560896077 Apr 04 03:37:10 PM PDT 24 Apr 04 03:37:15 PM PDT 24 556186298 ps
T1032 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2306890690 Apr 04 03:37:50 PM PDT 24 Apr 04 03:37:50 PM PDT 24 8010480 ps
T1033 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.719591941 Apr 04 03:36:59 PM PDT 24 Apr 04 03:37:00 PM PDT 24 19130493 ps
T1034 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3776252883 Apr 04 03:36:56 PM PDT 24 Apr 04 03:37:02 PM PDT 24 381724381 ps
T1035 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3398982226 Apr 04 03:37:00 PM PDT 24 Apr 04 03:37:02 PM PDT 24 38147391 ps
T1036 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3448345885 Apr 04 03:37:54 PM PDT 24 Apr 04 03:37:54 PM PDT 24 17448558 ps
T1037 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3484291237 Apr 04 03:37:52 PM PDT 24 Apr 04 03:37:56 PM PDT 24 311000259 ps
T163 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.660273080 Apr 04 03:36:59 PM PDT 24 Apr 04 03:37:06 PM PDT 24 269033922 ps
T1038 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2755760930 Apr 04 03:36:59 PM PDT 24 Apr 04 03:37:06 PM PDT 24 343044623 ps
T1039 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1081042407 Apr 04 03:37:11 PM PDT 24 Apr 04 03:37:12 PM PDT 24 64190951 ps
T1040 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3260036610 Apr 04 03:37:00 PM PDT 24 Apr 04 03:37:05 PM PDT 24 164956145 ps
T1041 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1960763660 Apr 04 03:37:07 PM PDT 24 Apr 04 03:37:10 PM PDT 24 127246231 ps
T1042 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1692928477 Apr 04 03:37:50 PM PDT 24 Apr 04 03:37:51 PM PDT 24 38478760 ps
T1043 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.172886643 Apr 04 03:37:41 PM PDT 24 Apr 04 03:37:45 PM PDT 24 119610656 ps
T1044 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.472750432 Apr 04 03:37:39 PM PDT 24 Apr 04 03:37:41 PM PDT 24 28156564 ps
T1045 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.479711500 Apr 04 03:37:20 PM PDT 24 Apr 04 03:37:21 PM PDT 24 11579049 ps
T1046 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1219974358 Apr 04 03:37:06 PM PDT 24 Apr 04 03:37:26 PM PDT 24 2242136915 ps
T1047 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1623718346 Apr 04 03:37:50 PM PDT 24 Apr 04 03:37:53 PM PDT 24 212641318 ps
T1048 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.969454565 Apr 04 03:37:39 PM PDT 24 Apr 04 03:37:43 PM PDT 24 596158039 ps
T1049 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1290355481 Apr 04 03:37:40 PM PDT 24 Apr 04 03:37:43 PM PDT 24 61651202 ps
T1050 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1254861945 Apr 04 03:37:06 PM PDT 24 Apr 04 03:37:12 PM PDT 24 229213712 ps
T1051 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.319668334 Apr 04 03:37:48 PM PDT 24 Apr 04 03:37:53 PM PDT 24 598846831 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.614584715 Apr 04 03:36:55 PM PDT 24 Apr 04 03:36:58 PM PDT 24 106153146 ps
T1053 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3604725050 Apr 04 03:37:48 PM PDT 24 Apr 04 03:37:50 PM PDT 24 85626754 ps
T1054 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2274027441 Apr 04 03:37:11 PM PDT 24 Apr 04 03:37:17 PM PDT 24 253973825 ps
T1055 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3846062445 Apr 04 03:37:10 PM PDT 24 Apr 04 03:37:12 PM PDT 24 147935735 ps
T1056 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3576840657 Apr 04 03:37:13 PM PDT 24 Apr 04 03:37:16 PM PDT 24 187418111 ps
T151 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3505146810 Apr 04 03:37:38 PM PDT 24 Apr 04 03:37:47 PM PDT 24 716244365 ps
T1057 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1399360691 Apr 04 03:37:52 PM PDT 24 Apr 04 03:37:54 PM PDT 24 118335734 ps
T1058 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2105244757 Apr 04 03:37:10 PM PDT 24 Apr 04 03:37:17 PM PDT 24 290199620 ps
T1059 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3254962772 Apr 04 03:37:20 PM PDT 24 Apr 04 03:38:10 PM PDT 24 5261063174 ps
T1060 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1869631025 Apr 04 03:37:28 PM PDT 24 Apr 04 03:37:31 PM PDT 24 26372580 ps
T162 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1119314839 Apr 04 03:37:14 PM PDT 24 Apr 04 03:37:39 PM PDT 24 2078388663 ps
T1061 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3698260215 Apr 04 03:37:52 PM PDT 24 Apr 04 03:37:54 PM PDT 24 355560752 ps
T1062 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1693647240 Apr 04 03:37:51 PM PDT 24 Apr 04 03:37:52 PM PDT 24 34304264 ps
T1063 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.705343504 Apr 04 03:37:27 PM PDT 24 Apr 04 03:37:31 PM PDT 24 71937869 ps
T1064 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4038575422 Apr 04 03:37:25 PM PDT 24 Apr 04 03:37:26 PM PDT 24 33042988 ps
T1065 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2293666756 Apr 04 03:37:40 PM PDT 24 Apr 04 03:37:43 PM PDT 24 275334452 ps
T1066 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2032551639 Apr 04 03:37:27 PM PDT 24 Apr 04 03:37:32 PM PDT 24 67633154 ps
T1067 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2783040959 Apr 04 03:37:25 PM PDT 24 Apr 04 03:37:28 PM PDT 24 372229176 ps
T1068 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4122262875 Apr 04 03:37:54 PM PDT 24 Apr 04 03:37:55 PM PDT 24 23946950 ps
T1069 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1646978082 Apr 04 03:37:13 PM PDT 24 Apr 04 03:37:14 PM PDT 24 19170973 ps
T1070 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.677992162 Apr 04 03:37:09 PM PDT 24 Apr 04 03:37:10 PM PDT 24 27324744 ps
T1071 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3379719018 Apr 04 03:37:40 PM PDT 24 Apr 04 03:37:42 PM PDT 24 70065359 ps
T1072 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3328762128 Apr 04 03:37:23 PM PDT 24 Apr 04 03:37:25 PM PDT 24 234612317 ps
T1073 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3636797134 Apr 04 03:37:29 PM PDT 24 Apr 04 03:37:31 PM PDT 24 50704935 ps
T155 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2106113761 Apr 04 03:37:08 PM PDT 24 Apr 04 03:37:12 PM PDT 24 370589214 ps
T1074 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2448900961 Apr 04 03:37:50 PM PDT 24 Apr 04 03:37:51 PM PDT 24 71251264 ps
T1075 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.125058974 Apr 04 03:37:11 PM PDT 24 Apr 04 03:37:14 PM PDT 24 48453994 ps
T1076 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2274700824 Apr 04 03:37:56 PM PDT 24 Apr 04 03:37:56 PM PDT 24 22824273 ps
T1077 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.280840144 Apr 04 03:37:20 PM PDT 24 Apr 04 03:37:22 PM PDT 24 82080390 ps
T1078 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.64622577 Apr 04 03:36:58 PM PDT 24 Apr 04 03:37:08 PM PDT 24 504991554 ps

Test location /workspace/coverage/default/22.keymgr_lc_disable.570251638
Short name T1
Test name
Test status
Simulation time 250616618 ps
CPU time 4.08 seconds
Started Apr 04 12:46:08 PM PDT 24
Finished Apr 04 12:46:13 PM PDT 24
Peak memory 220520 kb
Host smart-e78cd08c-056c-4590-87f6-27cb2a7f4bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570251638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.570251638
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1172081107
Short name T8
Test name
Test status
Simulation time 10886938153 ps
CPU time 55.43 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:47:01 PM PDT 24
Peak memory 222852 kb
Host smart-26e40705-1f83-4838-b0a6-dc00201306ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172081107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1172081107
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2313340525
Short name T23
Test name
Test status
Simulation time 102609541 ps
CPU time 5.83 seconds
Started Apr 04 12:46:45 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 214700 kb
Host smart-bea05f39-3605-45c6-876c-e7d6cf4e3c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313340525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2313340525
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3262865578
Short name T54
Test name
Test status
Simulation time 1523844210 ps
CPU time 22.88 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:59 PM PDT 24
Peak memory 223012 kb
Host smart-4102bf3c-b73a-4841-876a-c909d5175302
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262865578 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3262865578
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.690351130
Short name T6
Test name
Test status
Simulation time 1279315878 ps
CPU time 22.35 seconds
Started Apr 04 12:45:08 PM PDT 24
Finished Apr 04 12:45:31 PM PDT 24
Peak memory 241060 kb
Host smart-54aa57c4-11aa-4abb-b87d-e0fa6a832af6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690351130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.690351130
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.970332882
Short name T195
Test name
Test status
Simulation time 659636492 ps
CPU time 9.4 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:11 PM PDT 24
Peak memory 210636 kb
Host smart-c3cdd072-023e-42b0-92eb-46592f607e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970332882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.970332882
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.609274837
Short name T110
Test name
Test status
Simulation time 179628545 ps
CPU time 7.07 seconds
Started Apr 04 03:37:22 PM PDT 24
Finished Apr 04 03:37:30 PM PDT 24
Peak memory 214604 kb
Host smart-43e5c920-325b-43f7-b51e-58d48fdfc0ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609274837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.609274837
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1839887756
Short name T21
Test name
Test status
Simulation time 340348989 ps
CPU time 7.22 seconds
Started Apr 04 12:45:27 PM PDT 24
Finished Apr 04 12:45:34 PM PDT 24
Peak memory 222668 kb
Host smart-b68ce2e2-8622-4a11-8676-50e5899aa018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839887756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1839887756
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3750426249
Short name T43
Test name
Test status
Simulation time 11689280196 ps
CPU time 51.19 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:46:03 PM PDT 24
Peak memory 216440 kb
Host smart-fde7d312-8273-4f95-9933-7651cff3e1fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750426249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3750426249
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3770548483
Short name T137
Test name
Test status
Simulation time 426133323 ps
CPU time 11.68 seconds
Started Apr 04 12:45:56 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 215708 kb
Host smart-568a4a04-74c5-4695-98b2-0839578bbd4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770548483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3770548483
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2550870569
Short name T120
Test name
Test status
Simulation time 401410786 ps
CPU time 22.83 seconds
Started Apr 04 12:45:36 PM PDT 24
Finished Apr 04 12:45:59 PM PDT 24
Peak memory 222972 kb
Host smart-66cf7868-5871-48fc-812b-80db9c4483c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550870569 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2550870569
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.776124851
Short name T9
Test name
Test status
Simulation time 291849284 ps
CPU time 4.15 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:14 PM PDT 24
Peak memory 221484 kb
Host smart-7a47f870-4ff3-497d-851c-7b2e7d65f2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776124851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.776124851
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2416151224
Short name T47
Test name
Test status
Simulation time 3249658914 ps
CPU time 32.1 seconds
Started Apr 04 12:47:03 PM PDT 24
Finished Apr 04 12:47:36 PM PDT 24
Peak memory 221624 kb
Host smart-af4bb6b9-d873-4483-9ed7-9a69047b287e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416151224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2416151224
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2707142323
Short name T44
Test name
Test status
Simulation time 377979193 ps
CPU time 17.17 seconds
Started Apr 04 12:47:16 PM PDT 24
Finished Apr 04 12:47:34 PM PDT 24
Peak memory 220712 kb
Host smart-53120ad3-4ce0-4fc2-94c5-b3eaf37af2c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707142323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2707142323
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1039639592
Short name T344
Test name
Test status
Simulation time 2084277063 ps
CPU time 99.38 seconds
Started Apr 04 12:46:01 PM PDT 24
Finished Apr 04 12:47:41 PM PDT 24
Peak memory 219400 kb
Host smart-0752eaab-9067-4024-a805-b089001ad5b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039639592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1039639592
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.933956362
Short name T22
Test name
Test status
Simulation time 943193096 ps
CPU time 8.46 seconds
Started Apr 04 12:47:18 PM PDT 24
Finished Apr 04 12:47:27 PM PDT 24
Peak memory 214648 kb
Host smart-43a5788a-cffc-4533-bc1b-011c717b71ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933956362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.933956362
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2355583312
Short name T128
Test name
Test status
Simulation time 790942908 ps
CPU time 11.03 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:46:03 PM PDT 24
Peak memory 215388 kb
Host smart-b08e9c8b-ad07-4c84-8e48-752416b58180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355583312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2355583312
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.640058103
Short name T51
Test name
Test status
Simulation time 268911682 ps
CPU time 11.57 seconds
Started Apr 04 12:45:22 PM PDT 24
Finished Apr 04 12:45:33 PM PDT 24
Peak memory 222824 kb
Host smart-51da833b-474d-4a58-9b80-cac9286a9afa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640058103 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.640058103
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2664414234
Short name T114
Test name
Test status
Simulation time 543102250 ps
CPU time 4.57 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:44 PM PDT 24
Peak memory 214308 kb
Host smart-f6cc212d-2b1b-42a6-9ac0-9b7a86ad1617
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664414234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2664414234
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.638574416
Short name T331
Test name
Test status
Simulation time 920493990 ps
CPU time 25 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:46:14 PM PDT 24
Peak memory 214764 kb
Host smart-c41e9262-c8a3-4bfb-9cdb-f81f70c385c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=638574416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.638574416
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1034481820
Short name T75
Test name
Test status
Simulation time 1148079094 ps
CPU time 44.13 seconds
Started Apr 04 12:46:36 PM PDT 24
Finished Apr 04 12:47:20 PM PDT 24
Peak memory 215616 kb
Host smart-e787b40a-e04c-4caf-84b6-b68d6bbcb4ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034481820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1034481820
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.472053719
Short name T192
Test name
Test status
Simulation time 132064090 ps
CPU time 5.62 seconds
Started Apr 04 12:47:15 PM PDT 24
Finished Apr 04 12:47:21 PM PDT 24
Peak memory 221200 kb
Host smart-4ac94095-2b5e-472c-90c3-8cdd8bf0c378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472053719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.472053719
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3280594838
Short name T406
Test name
Test status
Simulation time 4347105445 ps
CPU time 112.27 seconds
Started Apr 04 12:45:55 PM PDT 24
Finished Apr 04 12:47:47 PM PDT 24
Peak memory 222720 kb
Host smart-c85d16a9-c40b-4783-8047-3f71e63d201a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280594838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3280594838
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3509283805
Short name T64
Test name
Test status
Simulation time 1200100133 ps
CPU time 16.9 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 222792 kb
Host smart-15be7562-a638-497a-85db-a488785ef1cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509283805 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3509283805
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.795792839
Short name T282
Test name
Test status
Simulation time 477618608 ps
CPU time 7.35 seconds
Started Apr 04 12:45:17 PM PDT 24
Finished Apr 04 12:45:25 PM PDT 24
Peak memory 214652 kb
Host smart-2a38e682-1145-433b-b341-9e2da92d4161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795792839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.795792839
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2281580103
Short name T94
Test name
Test status
Simulation time 204417304 ps
CPU time 3.34 seconds
Started Apr 04 12:46:39 PM PDT 24
Finished Apr 04 12:46:43 PM PDT 24
Peak memory 214584 kb
Host smart-77451706-6338-44fc-a46c-b57b9928c040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281580103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2281580103
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.546575697
Short name T37
Test name
Test status
Simulation time 91059762 ps
CPU time 2.8 seconds
Started Apr 04 12:46:21 PM PDT 24
Finished Apr 04 12:46:23 PM PDT 24
Peak memory 217196 kb
Host smart-3bd40d23-5a80-4487-a0b9-3b8f30dfe9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546575697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.546575697
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_random.4075210921
Short name T40
Test name
Test status
Simulation time 117615522 ps
CPU time 2.67 seconds
Started Apr 04 12:45:25 PM PDT 24
Finished Apr 04 12:45:28 PM PDT 24
Peak memory 208184 kb
Host smart-8a2ed89e-3a56-47b4-b105-af3e8391dc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075210921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4075210921
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1441949743
Short name T55
Test name
Test status
Simulation time 2501273368 ps
CPU time 20.87 seconds
Started Apr 04 12:47:03 PM PDT 24
Finished Apr 04 12:47:30 PM PDT 24
Peak memory 216544 kb
Host smart-c18b15d8-7097-46f1-96a3-92f45493f632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441949743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1441949743
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1713869151
Short name T28
Test name
Test status
Simulation time 1204433389 ps
CPU time 8.39 seconds
Started Apr 04 12:47:17 PM PDT 24
Finished Apr 04 12:47:26 PM PDT 24
Peak memory 214512 kb
Host smart-15c0b69e-40f7-4296-8bce-7a7e1e72caa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713869151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1713869151
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.344231035
Short name T99
Test name
Test status
Simulation time 15567557 ps
CPU time 0.76 seconds
Started Apr 04 12:45:04 PM PDT 24
Finished Apr 04 12:45:05 PM PDT 24
Peak memory 206176 kb
Host smart-5f3e6df1-1dcc-41c3-aa51-b6010228238f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344231035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.344231035
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2107054712
Short name T96
Test name
Test status
Simulation time 135425500 ps
CPU time 4.31 seconds
Started Apr 04 12:46:40 PM PDT 24
Finished Apr 04 12:46:44 PM PDT 24
Peak memory 221340 kb
Host smart-415670c4-1df6-4100-90b7-345a6afa5542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107054712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2107054712
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1879742183
Short name T129
Test name
Test status
Simulation time 883779811 ps
CPU time 43.43 seconds
Started Apr 04 12:46:26 PM PDT 24
Finished Apr 04 12:47:10 PM PDT 24
Peak memory 215580 kb
Host smart-7b6d8dc6-8cbb-4024-9630-a38a5e56fb1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879742183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1879742183
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1053924256
Short name T152
Test name
Test status
Simulation time 1002633183 ps
CPU time 12.24 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:12 PM PDT 24
Peak memory 214004 kb
Host smart-da6a3e72-fdbf-4d95-9312-ace2fc21905c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053924256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1053924256
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3241080509
Short name T126
Test name
Test status
Simulation time 210224993 ps
CPU time 3.9 seconds
Started Apr 04 12:46:48 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 214612 kb
Host smart-587dc238-bf57-40ea-9ffc-8ba32be61023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241080509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3241080509
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2867677039
Short name T3
Test name
Test status
Simulation time 1178130700 ps
CPU time 8.9 seconds
Started Apr 04 12:45:45 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 218004 kb
Host smart-1fbdedae-9f86-4939-8a1c-7fde8e8c97a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867677039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2867677039
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2519922258
Short name T183
Test name
Test status
Simulation time 10283746914 ps
CPU time 85.89 seconds
Started Apr 04 12:46:58 PM PDT 24
Finished Apr 04 12:48:24 PM PDT 24
Peak memory 222980 kb
Host smart-d4e69b22-3b47-45f9-98de-a1dfd9ddd298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519922258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2519922258
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.914922422
Short name T76
Test name
Test status
Simulation time 3942324472 ps
CPU time 73.66 seconds
Started Apr 04 12:46:56 PM PDT 24
Finished Apr 04 12:48:10 PM PDT 24
Peak memory 217096 kb
Host smart-be6b5fbf-a8d4-43a2-b24b-4c69a8768b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914922422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.914922422
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.653193270
Short name T20
Test name
Test status
Simulation time 382728773 ps
CPU time 2.74 seconds
Started Apr 04 12:46:40 PM PDT 24
Finished Apr 04 12:46:43 PM PDT 24
Peak memory 221816 kb
Host smart-c5bf9ed2-1cf1-4fce-a90d-59b12fcc1ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653193270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.653193270
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.926961140
Short name T408
Test name
Test status
Simulation time 3642146815 ps
CPU time 88.47 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:48:17 PM PDT 24
Peak memory 214668 kb
Host smart-7dcd01ca-a7e0-4e31-88ae-c5966b69d93a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=926961140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.926961140
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3653841139
Short name T34
Test name
Test status
Simulation time 553053935 ps
CPU time 4.29 seconds
Started Apr 04 12:46:15 PM PDT 24
Finished Apr 04 12:46:19 PM PDT 24
Peak memory 210948 kb
Host smart-4b9789a4-01c7-47ca-b5f3-dcf4a79e0174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653841139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3653841139
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1241116702
Short name T82
Test name
Test status
Simulation time 490917012 ps
CPU time 6.78 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 214604 kb
Host smart-67ef531b-8eb4-4ac8-ac8e-9e8d319678c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241116702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1241116702
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4120406274
Short name T967
Test name
Test status
Simulation time 262043908 ps
CPU time 4.43 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:04 PM PDT 24
Peak memory 214440 kb
Host smart-9876ac87-adb5-479c-a0cd-ccb4997524c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120406274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.4120406274
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3505146810
Short name T151
Test name
Test status
Simulation time 716244365 ps
CPU time 9.49 seconds
Started Apr 04 03:37:38 PM PDT 24
Finished Apr 04 03:37:47 PM PDT 24
Peak memory 214064 kb
Host smart-644210f5-7441-4ea9-87c6-5086a9165cbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505146810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3505146810
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3682455557
Short name T78
Test name
Test status
Simulation time 863712595 ps
CPU time 32.36 seconds
Started Apr 04 12:46:21 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 215236 kb
Host smart-a4018f04-c180-420f-a291-0ed6c27bcba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682455557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3682455557
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1379349846
Short name T371
Test name
Test status
Simulation time 4656019392 ps
CPU time 152.41 seconds
Started Apr 04 12:45:26 PM PDT 24
Finished Apr 04 12:47:59 PM PDT 24
Peak memory 216872 kb
Host smart-9fb77347-21cc-480a-980b-d132cf152255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379349846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1379349846
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3663638882
Short name T72
Test name
Test status
Simulation time 215233790 ps
CPU time 3.89 seconds
Started Apr 04 12:47:27 PM PDT 24
Finished Apr 04 12:47:31 PM PDT 24
Peak memory 214528 kb
Host smart-7685a71f-499b-4947-87ef-990e26267930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663638882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3663638882
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1758692370
Short name T154
Test name
Test status
Simulation time 2748498685 ps
CPU time 10.68 seconds
Started Apr 04 03:37:21 PM PDT 24
Finished Apr 04 03:37:32 PM PDT 24
Peak memory 209532 kb
Host smart-4d85a85b-4010-48ef-8784-01df0e72f48a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758692370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1758692370
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2487382459
Short name T138
Test name
Test status
Simulation time 321776340 ps
CPU time 5.44 seconds
Started Apr 04 12:46:04 PM PDT 24
Finished Apr 04 12:46:09 PM PDT 24
Peak memory 218004 kb
Host smart-f4fea160-63ae-45e2-9d53-909dec926b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487382459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2487382459
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3913961412
Short name T101
Test name
Test status
Simulation time 82972421 ps
CPU time 2.51 seconds
Started Apr 04 12:46:14 PM PDT 24
Finished Apr 04 12:46:17 PM PDT 24
Peak memory 211624 kb
Host smart-94179974-a079-4c17-8741-918606bc1653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913961412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3913961412
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3021697556
Short name T207
Test name
Test status
Simulation time 758364546 ps
CPU time 15.36 seconds
Started Apr 04 12:47:35 PM PDT 24
Finished Apr 04 12:47:51 PM PDT 24
Peak memory 210868 kb
Host smart-ff93d8a1-105d-415a-b149-d73beef338c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021697556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3021697556
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3950406669
Short name T308
Test name
Test status
Simulation time 6082025699 ps
CPU time 60.06 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:46:32 PM PDT 24
Peak memory 222716 kb
Host smart-d3240f46-9dfa-48ac-8b4d-7ff9a030126d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950406669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3950406669
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3538214973
Short name T10
Test name
Test status
Simulation time 859887333 ps
CPU time 11.48 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:46:04 PM PDT 24
Peak memory 222908 kb
Host smart-74979a6d-8e46-42a6-bc46-9e5b26ebd596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538214973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3538214973
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3085072570
Short name T414
Test name
Test status
Simulation time 9276959649 ps
CPU time 31.75 seconds
Started Apr 04 12:46:15 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 215736 kb
Host smart-9fd3d0d2-8001-466b-87f1-e17894920635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3085072570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3085072570
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3011922882
Short name T60
Test name
Test status
Simulation time 39174703 ps
CPU time 2.33 seconds
Started Apr 04 12:46:39 PM PDT 24
Finished Apr 04 12:46:42 PM PDT 24
Peak memory 210468 kb
Host smart-7ce14bd3-1e4a-42c8-bdef-58b096485c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011922882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3011922882
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2459687004
Short name T352
Test name
Test status
Simulation time 107152739 ps
CPU time 4.67 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:04 PM PDT 24
Peak memory 219208 kb
Host smart-925c93b2-7260-4e17-b92d-b19586fe6c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459687004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2459687004
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.273843879
Short name T218
Test name
Test status
Simulation time 97083813 ps
CPU time 4.22 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:10 PM PDT 24
Peak memory 209296 kb
Host smart-ecc937f2-2cb8-4184-b5e2-015f109d19e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273843879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.273843879
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.589469247
Short name T160
Test name
Test status
Simulation time 1475034710 ps
CPU time 10.73 seconds
Started Apr 04 03:37:23 PM PDT 24
Finished Apr 04 03:37:34 PM PDT 24
Peak memory 209396 kb
Host smart-61aa78b2-895f-4b16-8f0d-a5cf5111f4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589469247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.589469247
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3643620035
Short name T143
Test name
Test status
Simulation time 1487615904 ps
CPU time 18.27 seconds
Started Apr 04 12:45:57 PM PDT 24
Finished Apr 04 12:46:15 PM PDT 24
Peak memory 217360 kb
Host smart-e29fd9bd-d787-4f8c-aaad-e79c61a83b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643620035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3643620035
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1425832192
Short name T157
Test name
Test status
Simulation time 354530582 ps
CPU time 21.66 seconds
Started Apr 04 12:46:32 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 222904 kb
Host smart-2a350690-0c6c-402a-b7d4-6e9f380d6402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425832192 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1425832192
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1420232902
Short name T340
Test name
Test status
Simulation time 1964357937 ps
CPU time 56.71 seconds
Started Apr 04 12:46:54 PM PDT 24
Finished Apr 04 12:47:51 PM PDT 24
Peak memory 210044 kb
Host smart-238391d1-abb1-4c12-8736-e02a21b4825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420232902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1420232902
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.4237156988
Short name T201
Test name
Test status
Simulation time 2772428734 ps
CPU time 17.13 seconds
Started Apr 04 12:46:55 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 209324 kb
Host smart-9e4ef76c-3c54-49ba-a4e6-b311f1f5497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237156988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.4237156988
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.157922792
Short name T407
Test name
Test status
Simulation time 233602300 ps
CPU time 12.85 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 215020 kb
Host smart-6d25b5cc-9854-4ab1-a377-d1b3e851b313
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157922792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.157922792
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1065373728
Short name T292
Test name
Test status
Simulation time 8221739679 ps
CPU time 59.1 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:46:31 PM PDT 24
Peak memory 223608 kb
Host smart-a7c8b4f5-e273-4f34-b617-8005b952dd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065373728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1065373728
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.4174442933
Short name T139
Test name
Test status
Simulation time 302874812 ps
CPU time 3.18 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 217680 kb
Host smart-f01f57ee-2ff4-4343-9736-b9434ab02754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174442933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4174442933
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1887414066
Short name T147
Test name
Test status
Simulation time 2427946301 ps
CPU time 7.94 seconds
Started Apr 04 12:45:57 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 217968 kb
Host smart-babe6dcb-ae62-4544-9ee2-e64f502441d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887414066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1887414066
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1071082536
Short name T141
Test name
Test status
Simulation time 338196922 ps
CPU time 5.8 seconds
Started Apr 04 12:46:08 PM PDT 24
Finished Apr 04 12:46:14 PM PDT 24
Peak memory 222964 kb
Host smart-5b9d342b-0863-4b44-b8c2-95b8da551ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071082536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1071082536
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1563230331
Short name T145
Test name
Test status
Simulation time 323675041 ps
CPU time 3.62 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:46:51 PM PDT 24
Peak memory 218488 kb
Host smart-2e92ea89-8944-4f31-b9b7-920b22fcd4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563230331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1563230331
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.848362554
Short name T142
Test name
Test status
Simulation time 91388069 ps
CPU time 2.98 seconds
Started Apr 04 12:46:35 PM PDT 24
Finished Apr 04 12:46:39 PM PDT 24
Peak memory 216876 kb
Host smart-5906a895-0bff-4218-a02c-c2d6d6dd0ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848362554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.848362554
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.868575822
Short name T328
Test name
Test status
Simulation time 978637665 ps
CPU time 9.9 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:45:22 PM PDT 24
Peak memory 214636 kb
Host smart-0e7d76bf-48d2-4fca-a3c7-71f9fa0ac31e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868575822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.868575822
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2276698873
Short name T230
Test name
Test status
Simulation time 4842543905 ps
CPU time 95.77 seconds
Started Apr 04 12:45:06 PM PDT 24
Finished Apr 04 12:46:42 PM PDT 24
Peak memory 217580 kb
Host smart-ef0c6711-b0e2-476c-b8d5-e20db4aa01e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276698873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2276698873
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.375394310
Short name T104
Test name
Test status
Simulation time 860004142 ps
CPU time 9.48 seconds
Started Apr 04 12:45:05 PM PDT 24
Finished Apr 04 12:45:15 PM PDT 24
Peak memory 208796 kb
Host smart-401571dd-e25c-4da3-9835-af2d26e8bf4f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375394310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.375394310
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3070598868
Short name T83
Test name
Test status
Simulation time 81495338 ps
CPU time 3.66 seconds
Started Apr 04 12:45:53 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 209116 kb
Host smart-53b49bec-f02a-4e49-902b-770637a9eb16
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070598868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3070598868
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.967108497
Short name T247
Test name
Test status
Simulation time 465815211 ps
CPU time 6.29 seconds
Started Apr 04 12:46:03 PM PDT 24
Finished Apr 04 12:46:09 PM PDT 24
Peak memory 222692 kb
Host smart-131c658a-c8d5-4858-86d1-e77968831e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967108497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.967108497
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2877224165
Short name T250
Test name
Test status
Simulation time 1201306277 ps
CPU time 16.21 seconds
Started Apr 04 12:46:40 PM PDT 24
Finished Apr 04 12:46:57 PM PDT 24
Peak memory 215460 kb
Host smart-13811298-dbe4-4527-85c6-4d6d863d0253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2877224165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2877224165
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1009700373
Short name T301
Test name
Test status
Simulation time 96139071 ps
CPU time 2.39 seconds
Started Apr 04 12:46:53 PM PDT 24
Finished Apr 04 12:46:56 PM PDT 24
Peak memory 214496 kb
Host smart-7fc399f6-42d5-450d-9567-a35d4652478b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1009700373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1009700373
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.660273080
Short name T163
Test name
Test status
Simulation time 269033922 ps
CPU time 5.96 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:06 PM PDT 24
Peak memory 209336 kb
Host smart-18bfba28-dcc5-44fa-bb2a-2a38db6d4b46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660273080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
660273080
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1875342910
Short name T156
Test name
Test status
Simulation time 2206841345 ps
CPU time 5.7 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:57 PM PDT 24
Peak memory 209048 kb
Host smart-411da04b-3031-4c6d-9957-8b0aec7e8558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875342910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1875342910
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1119314839
Short name T162
Test name
Test status
Simulation time 2078388663 ps
CPU time 25.5 seconds
Started Apr 04 03:37:14 PM PDT 24
Finished Apr 04 03:37:39 PM PDT 24
Peak memory 214176 kb
Host smart-fbf64154-dcb5-4672-9fc9-b6ad61f0d093
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119314839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1119314839
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3359157810
Short name T149
Test name
Test status
Simulation time 243165520 ps
CPU time 5.73 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:16 PM PDT 24
Peak memory 214108 kb
Host smart-965b0ea6-cc03-4047-88c2-314ff15579a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359157810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3359157810
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2838208310
Short name T31
Test name
Test status
Simulation time 603378386 ps
CPU time 7.01 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 216680 kb
Host smart-cec7ad92-c034-465b-82a6-9f29372c4b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838208310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2838208310
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.928160150
Short name T148
Test name
Test status
Simulation time 111349172 ps
CPU time 4.14 seconds
Started Apr 04 12:45:03 PM PDT 24
Finished Apr 04 12:45:07 PM PDT 24
Peak memory 222956 kb
Host smart-f06b17f9-eaca-43ce-aedc-450e2e29ea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928160150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.928160150
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1575737640
Short name T140
Test name
Test status
Simulation time 69182239 ps
CPU time 2.75 seconds
Started Apr 04 12:47:20 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 218072 kb
Host smart-e0bcb623-4f11-4b0d-8708-45c5e561377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575737640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1575737640
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1374442047
Short name T314
Test name
Test status
Simulation time 75268298 ps
CPU time 4.93 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:25 PM PDT 24
Peak memory 212076 kb
Host smart-f396a079-bf2a-424e-8729-b7e6ebbbfe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374442047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1374442047
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2379701821
Short name T124
Test name
Test status
Simulation time 65951262 ps
CPU time 2.94 seconds
Started Apr 04 12:45:17 PM PDT 24
Finished Apr 04 12:45:21 PM PDT 24
Peak memory 210276 kb
Host smart-688d7c0b-b69d-45d9-9e8b-2cda10d51532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379701821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2379701821
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1764843671
Short name T233
Test name
Test status
Simulation time 1327614442 ps
CPU time 51.74 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:46:40 PM PDT 24
Peak memory 222752 kb
Host smart-eb3415e9-7968-48db-a10a-770132951f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764843671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1764843671
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1323621578
Short name T62
Test name
Test status
Simulation time 158476190 ps
CPU time 5.21 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 221608 kb
Host smart-b181589c-51b4-44cc-92fb-49563685f2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323621578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1323621578
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2888950562
Short name T56
Test name
Test status
Simulation time 422109412 ps
CPU time 6.72 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 214636 kb
Host smart-f1c9e26b-bfbe-4488-95f4-90053be07163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888950562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2888950562
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1274696519
Short name T671
Test name
Test status
Simulation time 460144389 ps
CPU time 9.62 seconds
Started Apr 04 12:45:40 PM PDT 24
Finished Apr 04 12:45:50 PM PDT 24
Peak memory 219744 kb
Host smart-a744b7d7-9a29-4688-8103-aeb87397986b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274696519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1274696519
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1027336419
Short name T224
Test name
Test status
Simulation time 3786354019 ps
CPU time 25.87 seconds
Started Apr 04 12:45:53 PM PDT 24
Finished Apr 04 12:46:19 PM PDT 24
Peak memory 216944 kb
Host smart-70938627-4804-44e3-9f37-a3739c92f286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027336419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1027336419
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1298747935
Short name T367
Test name
Test status
Simulation time 259300027 ps
CPU time 5.54 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:03 PM PDT 24
Peak memory 214508 kb
Host smart-0ac79846-6dda-4786-b127-b2ac74abad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298747935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1298747935
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2182493005
Short name T136
Test name
Test status
Simulation time 42349045 ps
CPU time 3.35 seconds
Started Apr 04 12:45:53 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 215688 kb
Host smart-ea8b574b-8f20-4dc1-aa03-3463c0574610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2182493005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2182493005
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2342133661
Short name T178
Test name
Test status
Simulation time 715454906 ps
CPU time 7.71 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:06 PM PDT 24
Peak memory 219244 kb
Host smart-616ff02b-3111-42a6-8606-e2657134a795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342133661 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2342133661
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.868851666
Short name T356
Test name
Test status
Simulation time 48461076 ps
CPU time 2.72 seconds
Started Apr 04 12:45:55 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 207840 kb
Host smart-7fb575d5-669a-4fd2-8c5e-0ce10324aa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868851666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.868851666
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3730506000
Short name T580
Test name
Test status
Simulation time 189830305 ps
CPU time 2.64 seconds
Started Apr 04 12:46:08 PM PDT 24
Finished Apr 04 12:46:10 PM PDT 24
Peak memory 209112 kb
Host smart-b0754b59-2744-4f94-81a9-b2809793d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730506000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3730506000
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1762752436
Short name T236
Test name
Test status
Simulation time 484460073 ps
CPU time 24 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:37 PM PDT 24
Peak memory 222784 kb
Host smart-46f92fcd-5ba9-412e-a64f-5ebef8455439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762752436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1762752436
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3017892159
Short name T332
Test name
Test status
Simulation time 583870567 ps
CPU time 4.77 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:18 PM PDT 24
Peak memory 208196 kb
Host smart-5db38276-7848-4f92-bacf-dbd5c56667cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017892159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3017892159
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1792909550
Short name T392
Test name
Test status
Simulation time 176820478 ps
CPU time 3.96 seconds
Started Apr 04 12:46:18 PM PDT 24
Finished Apr 04 12:46:22 PM PDT 24
Peak memory 214640 kb
Host smart-853b3a37-9256-4d82-99c9-1177bf973cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1792909550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1792909550
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3771401105
Short name T336
Test name
Test status
Simulation time 14690985846 ps
CPU time 72.83 seconds
Started Apr 04 12:46:36 PM PDT 24
Finished Apr 04 12:47:49 PM PDT 24
Peak memory 230224 kb
Host smart-2c192f44-eeda-4593-803a-a74146e4e4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771401105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3771401105
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.371491617
Short name T423
Test name
Test status
Simulation time 69304953 ps
CPU time 4.75 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:49 PM PDT 24
Peak memory 215808 kb
Host smart-ad005508-808e-4e5c-a961-4a450960d676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371491617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.371491617
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1637424078
Short name T317
Test name
Test status
Simulation time 44720777 ps
CPU time 2.59 seconds
Started Apr 04 12:45:23 PM PDT 24
Finished Apr 04 12:45:25 PM PDT 24
Peak memory 210644 kb
Host smart-8dd292a1-e8a9-45b8-917a-26e64f41b587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637424078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1637424078
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3555364472
Short name T235
Test name
Test status
Simulation time 3549991469 ps
CPU time 19.46 seconds
Started Apr 04 12:46:40 PM PDT 24
Finished Apr 04 12:46:59 PM PDT 24
Peak memory 221956 kb
Host smart-799c42e7-b29e-48bb-be46-4c67298e5fd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555364472 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3555364472
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3139070909
Short name T219
Test name
Test status
Simulation time 1012687575 ps
CPU time 25.47 seconds
Started Apr 04 12:46:35 PM PDT 24
Finished Apr 04 12:47:01 PM PDT 24
Peak memory 220700 kb
Host smart-0a61ce6a-e751-48bd-8c3e-b916c4c0b798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139070909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3139070909
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3773121113
Short name T290
Test name
Test status
Simulation time 656868540 ps
CPU time 6.7 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:08 PM PDT 24
Peak memory 214512 kb
Host smart-416fde33-ed73-4020-9567-5c783b253cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773121113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3773121113
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.421365917
Short name T146
Test name
Test status
Simulation time 47199516 ps
CPU time 1.76 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:15 PM PDT 24
Peak memory 216164 kb
Host smart-e6113373-b910-43ce-82b5-5232107066b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421365917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.421365917
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3318810836
Short name T144
Test name
Test status
Simulation time 576429176 ps
CPU time 6.6 seconds
Started Apr 04 12:45:31 PM PDT 24
Finished Apr 04 12:45:37 PM PDT 24
Peak memory 222980 kb
Host smart-734874ff-6221-4c6e-ad59-c751327b3740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318810836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3318810836
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.64622577
Short name T1078
Test name
Test status
Simulation time 504991554 ps
CPU time 8.23 seconds
Started Apr 04 03:36:58 PM PDT 24
Finished Apr 04 03:37:08 PM PDT 24
Peak memory 205872 kb
Host smart-f8872e5c-1d2d-40bf-b36b-8c579cd39fcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64622577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.64622577
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.528096153
Short name T965
Test name
Test status
Simulation time 144983705 ps
CPU time 6.51 seconds
Started Apr 04 03:37:00 PM PDT 24
Finished Apr 04 03:37:07 PM PDT 24
Peak memory 205836 kb
Host smart-62c48647-8598-4238-a031-8d703d87fc15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528096153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.528096153
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3738176355
Short name T912
Test name
Test status
Simulation time 16973995 ps
CPU time 1.13 seconds
Started Apr 04 03:37:00 PM PDT 24
Finished Apr 04 03:37:02 PM PDT 24
Peak memory 205976 kb
Host smart-627b41da-bbcc-4256-8e10-8976c0ab108a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738176355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
738176355
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4071413460
Short name T948
Test name
Test status
Simulation time 28885203 ps
CPU time 1.78 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:01 PM PDT 24
Peak memory 218704 kb
Host smart-9361089c-da5c-40e2-9b20-f751066b8cb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071413460 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.4071413460
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2557654771
Short name T1026
Test name
Test status
Simulation time 34444052 ps
CPU time 1.11 seconds
Started Apr 04 03:37:00 PM PDT 24
Finished Apr 04 03:37:02 PM PDT 24
Peak memory 205888 kb
Host smart-5467f78c-3b11-4646-a89c-1205edf21c38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557654771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2557654771
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.719591941
Short name T1033
Test name
Test status
Simulation time 19130493 ps
CPU time 0.78 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:00 PM PDT 24
Peak memory 205628 kb
Host smart-2aca6205-3943-4829-9842-a93cf5700bcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719591941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.719591941
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1798236775
Short name T1029
Test name
Test status
Simulation time 694431239 ps
CPU time 2.61 seconds
Started Apr 04 03:37:00 PM PDT 24
Finished Apr 04 03:37:03 PM PDT 24
Peak memory 205892 kb
Host smart-2b5d82c9-bb0f-432b-adf5-86c086ff1ca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798236775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1798236775
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3570157659
Short name T979
Test name
Test status
Simulation time 1533076909 ps
CPU time 7.19 seconds
Started Apr 04 03:37:00 PM PDT 24
Finished Apr 04 03:37:08 PM PDT 24
Peak memory 214416 kb
Host smart-edadf4ae-1b4c-435a-b048-662b6fdee917
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570157659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3570157659
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3260036610
Short name T1040
Test name
Test status
Simulation time 164956145 ps
CPU time 3.78 seconds
Started Apr 04 03:37:00 PM PDT 24
Finished Apr 04 03:37:05 PM PDT 24
Peak memory 214164 kb
Host smart-128270dd-81e4-489c-aea7-b3f0e45a47c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260036610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3260036610
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1382466124
Short name T980
Test name
Test status
Simulation time 5073372437 ps
CPU time 10.81 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 206116 kb
Host smart-79ab9568-de8c-4fed-b4f8-3d4ff2b25080
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382466124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
382466124
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3266126709
Short name T169
Test name
Test status
Simulation time 662144195 ps
CPU time 8.74 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:08 PM PDT 24
Peak memory 205908 kb
Host smart-e578a573-9da2-4577-a4e9-4ac9b5a4fe5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266126709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
266126709
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3105714040
Short name T946
Test name
Test status
Simulation time 86377642 ps
CPU time 0.86 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:01 PM PDT 24
Peak memory 205656 kb
Host smart-bb1fd05d-1e4c-4334-b389-301ce66480e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105714040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
105714040
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.614584715
Short name T1052
Test name
Test status
Simulation time 106153146 ps
CPU time 1.72 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 214108 kb
Host smart-ec8685af-c3ce-4479-a340-9f67f81b892e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614584715 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.614584715
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3398982226
Short name T1035
Test name
Test status
Simulation time 38147391 ps
CPU time 1.25 seconds
Started Apr 04 03:37:00 PM PDT 24
Finished Apr 04 03:37:02 PM PDT 24
Peak memory 205972 kb
Host smart-bc17eb06-d724-4c03-aca9-440c1dafd6ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398982226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3398982226
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4126214704
Short name T923
Test name
Test status
Simulation time 166045645 ps
CPU time 0.76 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:00 PM PDT 24
Peak memory 205600 kb
Host smart-c7cbca42-56b9-4ddd-980a-98f5f45d544d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126214704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4126214704
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2582991029
Short name T1027
Test name
Test status
Simulation time 31445527 ps
CPU time 2.08 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:36:59 PM PDT 24
Peak memory 206008 kb
Host smart-de2262ae-f173-4249-8b9c-e3295b5dd065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582991029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2582991029
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2755760930
Short name T1038
Test name
Test status
Simulation time 343044623 ps
CPU time 6.12 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:06 PM PDT 24
Peak memory 214416 kb
Host smart-1fc393e1-33fa-45c6-824d-77087fafcc10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755760930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2755760930
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2435203931
Short name T1000
Test name
Test status
Simulation time 723870193 ps
CPU time 14.31 seconds
Started Apr 04 03:36:57 PM PDT 24
Finished Apr 04 03:37:14 PM PDT 24
Peak memory 214464 kb
Host smart-2319ab67-ae45-4831-b9d2-66aad744a3e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435203931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2435203931
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3909732331
Short name T181
Test name
Test status
Simulation time 140593974 ps
CPU time 4.68 seconds
Started Apr 04 03:37:00 PM PDT 24
Finished Apr 04 03:37:05 PM PDT 24
Peak memory 214220 kb
Host smart-f13be67d-ca30-47b3-a836-cc931dd376e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909732331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3909732331
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1869631025
Short name T1060
Test name
Test status
Simulation time 26372580 ps
CPU time 1.35 seconds
Started Apr 04 03:37:28 PM PDT 24
Finished Apr 04 03:37:31 PM PDT 24
Peak memory 214084 kb
Host smart-7d161bcd-a1db-4078-bd86-784301cb3728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869631025 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1869631025
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4038575422
Short name T1064
Test name
Test status
Simulation time 33042988 ps
CPU time 0.94 seconds
Started Apr 04 03:37:25 PM PDT 24
Finished Apr 04 03:37:26 PM PDT 24
Peak memory 205724 kb
Host smart-0264f3e4-9259-45c5-beb7-985ebbde457e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038575422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4038575422
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.479711500
Short name T1045
Test name
Test status
Simulation time 11579049 ps
CPU time 0.68 seconds
Started Apr 04 03:37:20 PM PDT 24
Finished Apr 04 03:37:21 PM PDT 24
Peak memory 205644 kb
Host smart-bc5970d3-211b-4d35-b401-460dc7571cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479711500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.479711500
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2028036158
Short name T132
Test name
Test status
Simulation time 190600676 ps
CPU time 2.06 seconds
Started Apr 04 03:37:21 PM PDT 24
Finished Apr 04 03:37:23 PM PDT 24
Peak memory 205864 kb
Host smart-e1165e4e-c06f-4be4-aab8-c8ffefd92ca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028036158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2028036158
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3948985595
Short name T113
Test name
Test status
Simulation time 184970165 ps
CPU time 2.32 seconds
Started Apr 04 03:37:19 PM PDT 24
Finished Apr 04 03:37:22 PM PDT 24
Peak memory 222532 kb
Host smart-7d2323af-4bc0-4a3b-b37a-61f37dcc75f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948985595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3948985595
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1605598969
Short name T1008
Test name
Test status
Simulation time 106697459 ps
CPU time 1.84 seconds
Started Apr 04 03:37:25 PM PDT 24
Finished Apr 04 03:37:27 PM PDT 24
Peak memory 215124 kb
Host smart-a6b2bf3b-144a-44f5-9434-0411e9739ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605598969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1605598969
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1414790196
Short name T944
Test name
Test status
Simulation time 206811366 ps
CPU time 5.35 seconds
Started Apr 04 03:37:19 PM PDT 24
Finished Apr 04 03:37:24 PM PDT 24
Peak memory 214136 kb
Host smart-3cc85f9f-aabb-431d-a08e-37874505b021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414790196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1414790196
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2032551639
Short name T1066
Test name
Test status
Simulation time 67633154 ps
CPU time 1.71 seconds
Started Apr 04 03:37:27 PM PDT 24
Finished Apr 04 03:37:32 PM PDT 24
Peak memory 205864 kb
Host smart-f86257b6-d189-4f2a-9517-ce430ec16325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032551639 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2032551639
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4251583773
Short name T135
Test name
Test status
Simulation time 57257441 ps
CPU time 0.9 seconds
Started Apr 04 03:37:18 PM PDT 24
Finished Apr 04 03:37:19 PM PDT 24
Peak memory 205656 kb
Host smart-58091638-f3b5-4ea0-9d94-f1f00f70cdd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251583773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4251583773
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3377453534
Short name T968
Test name
Test status
Simulation time 14173479 ps
CPU time 0.76 seconds
Started Apr 04 03:37:19 PM PDT 24
Finished Apr 04 03:37:20 PM PDT 24
Peak memory 205568 kb
Host smart-524485c5-5bc8-4aed-b089-b18ce38bc62e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377453534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3377453534
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3704169380
Short name T134
Test name
Test status
Simulation time 133228708 ps
CPU time 1.83 seconds
Started Apr 04 03:37:25 PM PDT 24
Finished Apr 04 03:37:26 PM PDT 24
Peak memory 205924 kb
Host smart-5798db9a-8d0c-4153-b84b-e36ffd4e6abf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704169380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3704169380
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.793533160
Short name T116
Test name
Test status
Simulation time 169069800 ps
CPU time 4.92 seconds
Started Apr 04 03:37:19 PM PDT 24
Finished Apr 04 03:37:24 PM PDT 24
Peak memory 214436 kb
Host smart-fe7093ea-0a15-4607-a6f2-d40906e4d893
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793533160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.793533160
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.360316628
Short name T107
Test name
Test status
Simulation time 1145909458 ps
CPU time 7.47 seconds
Started Apr 04 03:37:22 PM PDT 24
Finished Apr 04 03:37:29 PM PDT 24
Peak memory 220468 kb
Host smart-7ff7be40-94c2-4c8b-a260-a6363d5eac24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360316628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.360316628
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.956026369
Short name T942
Test name
Test status
Simulation time 45521112 ps
CPU time 1.84 seconds
Started Apr 04 03:37:23 PM PDT 24
Finished Apr 04 03:37:25 PM PDT 24
Peak memory 217176 kb
Host smart-44523152-f90b-40fb-a3a6-6b301ea4d4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956026369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.956026369
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.498808109
Short name T932
Test name
Test status
Simulation time 205261316 ps
CPU time 1.76 seconds
Started Apr 04 03:37:27 PM PDT 24
Finished Apr 04 03:37:32 PM PDT 24
Peak memory 214108 kb
Host smart-9bd4f530-74f8-48c1-b860-acad1442e818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498808109 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.498808109
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3961924661
Short name T939
Test name
Test status
Simulation time 90539934 ps
CPU time 1.2 seconds
Started Apr 04 03:37:23 PM PDT 24
Finished Apr 04 03:37:25 PM PDT 24
Peak memory 205956 kb
Host smart-587d1cba-14f1-4d83-998d-689ecc9056c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961924661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3961924661
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.59831718
Short name T953
Test name
Test status
Simulation time 45876859 ps
CPU time 0.87 seconds
Started Apr 04 03:37:28 PM PDT 24
Finished Apr 04 03:37:31 PM PDT 24
Peak memory 205528 kb
Host smart-51be7b3e-a5be-4ef0-9c68-05a26e9822b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59831718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.59831718
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3636797134
Short name T1073
Test name
Test status
Simulation time 50704935 ps
CPU time 1.57 seconds
Started Apr 04 03:37:29 PM PDT 24
Finished Apr 04 03:37:31 PM PDT 24
Peak memory 206008 kb
Host smart-60946cb2-7ccf-4479-9f4e-8c6cea3d3ce5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636797134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3636797134
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.814097004
Short name T971
Test name
Test status
Simulation time 186472433 ps
CPU time 1.99 seconds
Started Apr 04 03:37:19 PM PDT 24
Finished Apr 04 03:37:22 PM PDT 24
Peak memory 214512 kb
Host smart-62a04672-70c1-48ef-88bc-a35ee6dd22ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814097004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.814097004
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3189629217
Short name T977
Test name
Test status
Simulation time 197946274 ps
CPU time 3.85 seconds
Started Apr 04 03:37:22 PM PDT 24
Finished Apr 04 03:37:26 PM PDT 24
Peak memory 214496 kb
Host smart-f5799d9a-c187-43d7-b373-e1ec762bb3b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189629217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3189629217
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2783040959
Short name T1067
Test name
Test status
Simulation time 372229176 ps
CPU time 3.15 seconds
Started Apr 04 03:37:25 PM PDT 24
Finished Apr 04 03:37:28 PM PDT 24
Peak memory 214096 kb
Host smart-cfe36574-af9d-4097-855f-034e3c744f22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783040959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2783040959
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2027935570
Short name T970
Test name
Test status
Simulation time 32430257 ps
CPU time 1.54 seconds
Started Apr 04 03:37:42 PM PDT 24
Finished Apr 04 03:37:43 PM PDT 24
Peak memory 205984 kb
Host smart-c71d2135-e49a-4e28-9048-f3b3ff27ee0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027935570 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2027935570
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4073517053
Short name T1025
Test name
Test status
Simulation time 28388149 ps
CPU time 1.51 seconds
Started Apr 04 03:37:24 PM PDT 24
Finished Apr 04 03:37:25 PM PDT 24
Peak memory 205908 kb
Host smart-33accd3c-e8d3-4454-bb31-75062d0fb00c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073517053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4073517053
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1032658844
Short name T974
Test name
Test status
Simulation time 66060949 ps
CPU time 0.75 seconds
Started Apr 04 03:37:28 PM PDT 24
Finished Apr 04 03:37:31 PM PDT 24
Peak memory 205520 kb
Host smart-8061bfb8-9328-475f-af03-97ffad5cdebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032658844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1032658844
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3328762128
Short name T1072
Test name
Test status
Simulation time 234612317 ps
CPU time 1.48 seconds
Started Apr 04 03:37:23 PM PDT 24
Finished Apr 04 03:37:25 PM PDT 24
Peak memory 205984 kb
Host smart-62e6c713-be15-4ffc-a724-2788d83139db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328762128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3328762128
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1879441600
Short name T956
Test name
Test status
Simulation time 61134429 ps
CPU time 1.54 seconds
Started Apr 04 03:37:20 PM PDT 24
Finished Apr 04 03:37:22 PM PDT 24
Peak memory 214464 kb
Host smart-e6f5d436-5f81-4b7a-8229-892b5d7f8915
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879441600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1879441600
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3167169615
Short name T947
Test name
Test status
Simulation time 202139006 ps
CPU time 5.03 seconds
Started Apr 04 03:37:28 PM PDT 24
Finished Apr 04 03:37:35 PM PDT 24
Peak memory 214440 kb
Host smart-db45c965-4817-47fe-bfd4-bee02c1be1ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167169615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3167169615
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.83245008
Short name T935
Test name
Test status
Simulation time 887026817 ps
CPU time 5.46 seconds
Started Apr 04 03:37:23 PM PDT 24
Finished Apr 04 03:37:29 PM PDT 24
Peak memory 214076 kb
Host smart-85d87e9d-4f55-4e25-a1b9-9a5bbf33ed25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83245008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.83245008
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3254962772
Short name T1059
Test name
Test status
Simulation time 5261063174 ps
CPU time 50.29 seconds
Started Apr 04 03:37:20 PM PDT 24
Finished Apr 04 03:38:10 PM PDT 24
Peak memory 222384 kb
Host smart-1e80b463-da78-4b57-b4d3-d01dfca552c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254962772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3254962772
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1145572961
Short name T913
Test name
Test status
Simulation time 21304901 ps
CPU time 1.33 seconds
Started Apr 04 03:37:37 PM PDT 24
Finished Apr 04 03:37:39 PM PDT 24
Peak memory 214244 kb
Host smart-01f9286f-5af2-48f6-abc4-3ba7df2326f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145572961 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1145572961
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2289895997
Short name T975
Test name
Test status
Simulation time 136440554 ps
CPU time 1.56 seconds
Started Apr 04 03:37:42 PM PDT 24
Finished Apr 04 03:37:44 PM PDT 24
Peak memory 205860 kb
Host smart-f31dff5a-ade9-4118-9b63-387a6eff077b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289895997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2289895997
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1130181913
Short name T1013
Test name
Test status
Simulation time 40988405 ps
CPU time 0.77 seconds
Started Apr 04 03:37:40 PM PDT 24
Finished Apr 04 03:37:41 PM PDT 24
Peak memory 205596 kb
Host smart-0112cc98-f33d-4de3-ab2d-2fa195bc7ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130181913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1130181913
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4047168838
Short name T976
Test name
Test status
Simulation time 2177579831 ps
CPU time 3.96 seconds
Started Apr 04 03:37:38 PM PDT 24
Finished Apr 04 03:37:43 PM PDT 24
Peak memory 205872 kb
Host smart-e6481e14-874f-48f0-9ab9-e03601713072
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047168838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4047168838
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2267959765
Short name T982
Test name
Test status
Simulation time 364859324 ps
CPU time 7.22 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:47 PM PDT 24
Peak memory 220552 kb
Host smart-152a3478-d337-4d08-81c4-8a960adf22bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267959765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2267959765
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2739335178
Short name T1021
Test name
Test status
Simulation time 153158602 ps
CPU time 1.81 seconds
Started Apr 04 03:37:44 PM PDT 24
Finished Apr 04 03:37:46 PM PDT 24
Peak memory 214188 kb
Host smart-0eda8102-d3ad-4ff4-aa75-51ad4b1a961c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739335178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2739335178
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2179776952
Short name T973
Test name
Test status
Simulation time 21546056 ps
CPU time 1.69 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:41 PM PDT 24
Peak memory 205980 kb
Host smart-36a691b5-f8d8-48e4-96f9-93f328dcf93b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179776952 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2179776952
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4059929451
Short name T936
Test name
Test status
Simulation time 16180870 ps
CPU time 1.1 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:41 PM PDT 24
Peak memory 205800 kb
Host smart-5d08a602-8dc2-4e3b-990f-54538d537b61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059929451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4059929451
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.886844921
Short name T996
Test name
Test status
Simulation time 42951764 ps
CPU time 0.87 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:40 PM PDT 24
Peak memory 205592 kb
Host smart-cdabf520-334c-4d29-bb0a-434bec8e2b30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886844921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.886844921
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2695459010
Short name T1009
Test name
Test status
Simulation time 62154782 ps
CPU time 2.07 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:42 PM PDT 24
Peak memory 205992 kb
Host smart-94aafe02-83a9-4749-b8c6-3b1d8439ea53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695459010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2695459010
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3898358330
Short name T964
Test name
Test status
Simulation time 150719663 ps
CPU time 4.88 seconds
Started Apr 04 03:37:40 PM PDT 24
Finished Apr 04 03:37:45 PM PDT 24
Peak memory 214452 kb
Host smart-d5252a18-ba7b-4cb3-920b-31a3bef876ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898358330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3898358330
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1454472121
Short name T1016
Test name
Test status
Simulation time 160626422 ps
CPU time 6.57 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:45 PM PDT 24
Peak memory 220260 kb
Host smart-e85c3af2-19a0-4f7c-b0bf-9489ba463600
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454472121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1454472121
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.969454565
Short name T1048
Test name
Test status
Simulation time 596158039 ps
CPU time 3.38 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:43 PM PDT 24
Peak memory 214188 kb
Host smart-c541a6df-f015-4e54-ac84-7be5b440e835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969454565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.969454565
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2009346835
Short name T161
Test name
Test status
Simulation time 1362852799 ps
CPU time 9.25 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:49 PM PDT 24
Peak memory 209188 kb
Host smart-2603aa12-475d-477b-8318-a0d4e69c5a02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009346835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2009346835
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2635809364
Short name T959
Test name
Test status
Simulation time 60742828 ps
CPU time 1.22 seconds
Started Apr 04 03:37:38 PM PDT 24
Finished Apr 04 03:37:40 PM PDT 24
Peak memory 214172 kb
Host smart-508454a8-c7ac-4100-b9cc-d10699806734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635809364 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2635809364
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.472750432
Short name T1044
Test name
Test status
Simulation time 28156564 ps
CPU time 1.01 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:41 PM PDT 24
Peak memory 205636 kb
Host smart-9ab9b782-2ec4-4bf5-8787-5665cbaf7e77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472750432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.472750432
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.68805051
Short name T1015
Test name
Test status
Simulation time 113307436 ps
CPU time 0.78 seconds
Started Apr 04 03:37:39 PM PDT 24
Finished Apr 04 03:37:40 PM PDT 24
Peak memory 205528 kb
Host smart-47ea0a35-fdc3-4bf8-a19f-3149750552f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68805051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.68805051
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1290355481
Short name T1049
Test name
Test status
Simulation time 61651202 ps
CPU time 2.42 seconds
Started Apr 04 03:37:40 PM PDT 24
Finished Apr 04 03:37:43 PM PDT 24
Peak memory 205812 kb
Host smart-8849d219-fa87-48cf-b01a-f1c46e69929d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290355481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1290355481
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3379719018
Short name T1071
Test name
Test status
Simulation time 70065359 ps
CPU time 1.73 seconds
Started Apr 04 03:37:40 PM PDT 24
Finished Apr 04 03:37:42 PM PDT 24
Peak memory 214424 kb
Host smart-132b9eec-e5b8-4238-9d90-cb501bb58b31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379719018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3379719018
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3584646998
Short name T1012
Test name
Test status
Simulation time 497597582 ps
CPU time 16.22 seconds
Started Apr 04 03:37:40 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 214424 kb
Host smart-258c3835-9d19-4b5b-b096-183c4e95e397
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584646998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3584646998
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1324735947
Short name T966
Test name
Test status
Simulation time 141740551 ps
CPU time 3 seconds
Started Apr 04 03:37:43 PM PDT 24
Finished Apr 04 03:37:46 PM PDT 24
Peak memory 222272 kb
Host smart-2f7fa539-c8b5-4363-9e2b-7dca0139d7bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324735947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1324735947
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.715608552
Short name T159
Test name
Test status
Simulation time 2766354769 ps
CPU time 47.81 seconds
Started Apr 04 03:37:41 PM PDT 24
Finished Apr 04 03:38:29 PM PDT 24
Peak memory 211952 kb
Host smart-d274194d-5b41-4d16-9b03-fa26c0a949e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715608552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.715608552
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3698260215
Short name T1061
Test name
Test status
Simulation time 355560752 ps
CPU time 1.28 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 205940 kb
Host smart-e451c7c4-567c-4195-9ba3-7ba1c000b197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698260215 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3698260215
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.796333918
Short name T949
Test name
Test status
Simulation time 18927307 ps
CPU time 1.24 seconds
Started Apr 04 03:37:47 PM PDT 24
Finished Apr 04 03:37:48 PM PDT 24
Peak memory 205852 kb
Host smart-60db9df5-6e71-41db-a106-f4d30315f18a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796333918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.796333918
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.171133196
Short name T930
Test name
Test status
Simulation time 42400414 ps
CPU time 0.86 seconds
Started Apr 04 03:37:43 PM PDT 24
Finished Apr 04 03:37:44 PM PDT 24
Peak memory 205600 kb
Host smart-ff581fd2-a126-4800-95f3-267da67884e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171133196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.171133196
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3604725050
Short name T1053
Test name
Test status
Simulation time 85626754 ps
CPU time 1.35 seconds
Started Apr 04 03:37:48 PM PDT 24
Finished Apr 04 03:37:50 PM PDT 24
Peak memory 205888 kb
Host smart-9f3f6086-0e9e-4a21-9c0e-0ca5fe1583b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604725050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3604725050
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.571908268
Short name T960
Test name
Test status
Simulation time 381468446 ps
CPU time 3.6 seconds
Started Apr 04 03:37:40 PM PDT 24
Finished Apr 04 03:37:44 PM PDT 24
Peak memory 214436 kb
Host smart-f52a69d4-58a6-4b6f-a9f4-dcd7082561e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571908268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.571908268
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1280981088
Short name T963
Test name
Test status
Simulation time 1421882064 ps
CPU time 13.43 seconds
Started Apr 04 03:37:42 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 214560 kb
Host smart-43010141-4504-49f3-a0b6-548dddcce9c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280981088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1280981088
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2293666756
Short name T1065
Test name
Test status
Simulation time 275334452 ps
CPU time 2.1 seconds
Started Apr 04 03:37:40 PM PDT 24
Finished Apr 04 03:37:43 PM PDT 24
Peak memory 214116 kb
Host smart-35928cb1-6623-4b5c-94d3-9026f302b3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293666756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2293666756
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.172886643
Short name T1043
Test name
Test status
Simulation time 119610656 ps
CPU time 4.76 seconds
Started Apr 04 03:37:41 PM PDT 24
Finished Apr 04 03:37:45 PM PDT 24
Peak memory 209540 kb
Host smart-fc60eada-9ac9-4f0f-9e99-99b1e698447f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172886643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.172886643
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1399360691
Short name T1057
Test name
Test status
Simulation time 118335734 ps
CPU time 1.92 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 214160 kb
Host smart-e4db8a65-628d-41c0-883e-fd7fe8fd4b3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399360691 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1399360691
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.738276045
Short name T943
Test name
Test status
Simulation time 26372739 ps
CPU time 1.48 seconds
Started Apr 04 03:37:50 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205924 kb
Host smart-5ddedd55-a514-41dc-9df6-3cd2f5f4f16f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738276045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.738276045
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.603796270
Short name T1030
Test name
Test status
Simulation time 10541882 ps
CPU time 0.69 seconds
Started Apr 04 03:37:56 PM PDT 24
Finished Apr 04 03:37:57 PM PDT 24
Peak memory 205464 kb
Host smart-075da4f1-bdcd-4595-b3f4-8bcf45f7c3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603796270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.603796270
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.696136567
Short name T941
Test name
Test status
Simulation time 67599364 ps
CPU time 2.23 seconds
Started Apr 04 03:37:49 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205888 kb
Host smart-8548f203-a974-41b6-b0c1-ecc7b091ff45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696136567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.696136567
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1455611743
Short name T1004
Test name
Test status
Simulation time 76095344 ps
CPU time 2.65 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 214364 kb
Host smart-99da2e7d-3844-45cb-865c-273de238f060
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455611743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1455611743
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2172433296
Short name T951
Test name
Test status
Simulation time 331642955 ps
CPU time 5.07 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:57 PM PDT 24
Peak memory 214328 kb
Host smart-2173128f-8616-43c8-83a9-ace06695d133
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172433296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2172433296
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3264495859
Short name T925
Test name
Test status
Simulation time 47925983 ps
CPU time 2 seconds
Started Apr 04 03:37:50 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 214012 kb
Host smart-f0639c32-bc75-420d-9c78-bc5f24684302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264495859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3264495859
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1383386936
Short name T153
Test name
Test status
Simulation time 221013150 ps
CPU time 3.44 seconds
Started Apr 04 03:37:50 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 214140 kb
Host smart-0fa36c7a-aaad-4f3d-9fc9-0e870319eab4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383386936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1383386936
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2638191083
Short name T180
Test name
Test status
Simulation time 66413331 ps
CPU time 1.38 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 206100 kb
Host smart-a2811d67-c894-4e07-9cdd-fa859658db84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638191083 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2638191083
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2039754018
Short name T997
Test name
Test status
Simulation time 57801836 ps
CPU time 1.09 seconds
Started Apr 04 03:37:49 PM PDT 24
Finished Apr 04 03:37:50 PM PDT 24
Peak memory 205788 kb
Host smart-d9dd3f47-63e9-4eb9-bfcc-7fbdff09ea80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039754018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2039754018
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2715746363
Short name T934
Test name
Test status
Simulation time 42825555 ps
CPU time 0.8 seconds
Started Apr 04 03:37:53 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 205588 kb
Host smart-cce3960f-61a6-44b5-9c1e-cde3e29a704f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715746363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2715746363
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1623718346
Short name T1047
Test name
Test status
Simulation time 212641318 ps
CPU time 2.61 seconds
Started Apr 04 03:37:50 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 205904 kb
Host smart-fa764917-ce4b-4250-8045-f4be46d85b66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623718346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1623718346
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.319668334
Short name T1051
Test name
Test status
Simulation time 598846831 ps
CPU time 4.69 seconds
Started Apr 04 03:37:48 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 214364 kb
Host smart-42cd3dc2-0d79-4658-a64e-b659cba8bd9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319668334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.319668334
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3484291237
Short name T1037
Test name
Test status
Simulation time 311000259 ps
CPU time 3.72 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 214524 kb
Host smart-14743ea3-5e44-4eb0-8368-6ae58d139e0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484291237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3484291237
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.876769784
Short name T987
Test name
Test status
Simulation time 44903066 ps
CPU time 2.17 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 214112 kb
Host smart-3673f393-c598-41f4-890d-bde075ac6dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876769784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.876769784
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2274027441
Short name T1054
Test name
Test status
Simulation time 253973825 ps
CPU time 5.88 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:17 PM PDT 24
Peak memory 205856 kb
Host smart-5170e407-5b21-4c8e-8607-2833a6cb859b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274027441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
274027441
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3257548674
Short name T1023
Test name
Test status
Simulation time 505343082 ps
CPU time 11.7 seconds
Started Apr 04 03:37:13 PM PDT 24
Finished Apr 04 03:37:25 PM PDT 24
Peak memory 205928 kb
Host smart-de7d4a8f-a60a-41b6-a20e-5129a988d00f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257548674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
257548674
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1081042407
Short name T1039
Test name
Test status
Simulation time 64190951 ps
CPU time 1.1 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:12 PM PDT 24
Peak memory 205924 kb
Host smart-1617de22-8f73-4ed4-9022-ca2ea612932e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081042407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
081042407
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1388203120
Short name T961
Test name
Test status
Simulation time 82959455 ps
CPU time 0.98 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 205624 kb
Host smart-70e17d0f-2c74-45db-8119-4e4250537911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388203120 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1388203120
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1638865524
Short name T984
Test name
Test status
Simulation time 13642524 ps
CPU time 0.93 seconds
Started Apr 04 03:37:07 PM PDT 24
Finished Apr 04 03:37:08 PM PDT 24
Peak memory 205740 kb
Host smart-fe53ec7b-114f-400b-9e53-86f9822ebd5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638865524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1638865524
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3020953805
Short name T909
Test name
Test status
Simulation time 12559107 ps
CPU time 0.73 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:12 PM PDT 24
Peak memory 205548 kb
Host smart-a070fc25-ffd8-4821-a2fe-10c666c0bdd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020953805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3020953805
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.388570047
Short name T1006
Test name
Test status
Simulation time 59534597 ps
CPU time 2.11 seconds
Started Apr 04 03:37:07 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 205856 kb
Host smart-9966316b-48b5-4fa7-b39f-bc22faebb68c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388570047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.388570047
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3776252883
Short name T1034
Test name
Test status
Simulation time 381724381 ps
CPU time 5.39 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:02 PM PDT 24
Peak memory 214360 kb
Host smart-104c43a5-df2e-42d6-a108-23d5f6cff348
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776252883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3776252883
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1730919861
Short name T981
Test name
Test status
Simulation time 587764770 ps
CPU time 5.05 seconds
Started Apr 04 03:37:08 PM PDT 24
Finished Apr 04 03:37:13 PM PDT 24
Peak memory 214356 kb
Host smart-634dafa9-5b77-49a8-a057-5e47626f0c2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730919861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1730919861
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4078788911
Short name T915
Test name
Test status
Simulation time 85786684 ps
CPU time 3.03 seconds
Started Apr 04 03:37:06 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 216160 kb
Host smart-0514d4cd-eadc-45ae-9d4b-429551c07156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078788911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.4078788911
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2105244757
Short name T1058
Test name
Test status
Simulation time 290199620 ps
CPU time 7.57 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:17 PM PDT 24
Peak memory 214040 kb
Host smart-506c791e-645a-474c-a432-5b471dec1bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105244757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2105244757
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3943794143
Short name T918
Test name
Test status
Simulation time 8787248 ps
CPU time 0.78 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205600 kb
Host smart-0d11256a-ba8e-40f4-abc1-58743a398483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943794143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3943794143
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2545074795
Short name T972
Test name
Test status
Simulation time 41912406 ps
CPU time 0.85 seconds
Started Apr 04 03:37:55 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 205536 kb
Host smart-5f6a84b3-a953-4aaa-9511-722d42fffebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545074795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2545074795
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1693647240
Short name T1062
Test name
Test status
Simulation time 34304264 ps
CPU time 0.76 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205588 kb
Host smart-261e6a13-b6a2-4669-96e5-c9b469d394b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693647240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1693647240
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1352506977
Short name T998
Test name
Test status
Simulation time 92589974 ps
CPU time 0.72 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 205536 kb
Host smart-7630b458-b94f-4eb1-b6b6-c188c9d318ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352506977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1352506977
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1119148734
Short name T1017
Test name
Test status
Simulation time 18078036 ps
CPU time 0.81 seconds
Started Apr 04 03:37:55 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 205460 kb
Host smart-9b528624-18fc-4ba4-9ac4-e34ca6f50748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119148734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1119148734
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2306890690
Short name T1032
Test name
Test status
Simulation time 8010480 ps
CPU time 0.73 seconds
Started Apr 04 03:37:50 PM PDT 24
Finished Apr 04 03:37:50 PM PDT 24
Peak memory 205532 kb
Host smart-33c7e03e-6b65-48d6-90c5-9830750ba697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306890690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2306890690
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2290369899
Short name T957
Test name
Test status
Simulation time 13272019 ps
CPU time 0.69 seconds
Started Apr 04 03:37:49 PM PDT 24
Finished Apr 04 03:37:49 PM PDT 24
Peak memory 205564 kb
Host smart-4385eb0d-093b-4e53-98da-4ab0597a10de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290369899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2290369899
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2091265194
Short name T919
Test name
Test status
Simulation time 14913928 ps
CPU time 0.79 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205596 kb
Host smart-fa3b16af-cad0-4ad4-a9b3-211314cabd37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091265194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2091265194
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2084815388
Short name T983
Test name
Test status
Simulation time 11380477 ps
CPU time 0.83 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205552 kb
Host smart-9fde4025-0b49-482e-a1ac-7ce0922cc793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084815388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2084815388
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1417830557
Short name T926
Test name
Test status
Simulation time 16393552 ps
CPU time 0.71 seconds
Started Apr 04 03:37:50 PM PDT 24
Finished Apr 04 03:37:51 PM PDT 24
Peak memory 205628 kb
Host smart-3fee7205-580b-43b3-b625-11cc8d2f7cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417830557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1417830557
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2631563293
Short name T920
Test name
Test status
Simulation time 263983856 ps
CPU time 5.04 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:16 PM PDT 24
Peak memory 205840 kb
Host smart-1026226a-dc4f-4fb7-8bff-f48ef521778d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631563293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
631563293
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3086757444
Short name T1005
Test name
Test status
Simulation time 1664648382 ps
CPU time 8.29 seconds
Started Apr 04 03:37:08 PM PDT 24
Finished Apr 04 03:37:16 PM PDT 24
Peak memory 205912 kb
Host smart-31c46003-b01c-431d-8371-8bb004cf1000
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086757444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
086757444
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.378390569
Short name T914
Test name
Test status
Simulation time 82542725 ps
CPU time 0.91 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 205664 kb
Host smart-32f575fa-0926-4f54-8e81-e87b4c60e4b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378390569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.378390569
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.14835853
Short name T950
Test name
Test status
Simulation time 323059289 ps
CPU time 1.56 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:11 PM PDT 24
Peak memory 205976 kb
Host smart-73018c57-8443-4225-9dac-cf6503c03bdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14835853 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.14835853
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1403408723
Short name T1002
Test name
Test status
Simulation time 32726865 ps
CPU time 0.94 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:11 PM PDT 24
Peak memory 205732 kb
Host smart-f06bd380-c88d-4b52-b0d9-33bd7f56415a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403408723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1403408723
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2027853728
Short name T991
Test name
Test status
Simulation time 11867009 ps
CPU time 0.73 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:11 PM PDT 24
Peak memory 205628 kb
Host smart-c6e80e90-ac7d-4dc8-829d-ca9f2815b441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027853728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2027853728
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2043602407
Short name T171
Test name
Test status
Simulation time 209708238 ps
CPU time 1.42 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 205132 kb
Host smart-0aee6402-cb34-4d5f-ad31-5ccb756f39f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043602407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2043602407
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1219974358
Short name T1046
Test name
Test status
Simulation time 2242136915 ps
CPU time 19.46 seconds
Started Apr 04 03:37:06 PM PDT 24
Finished Apr 04 03:37:26 PM PDT 24
Peak memory 215432 kb
Host smart-c30506bf-1f63-49ea-b959-47927f8bf823
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219974358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1219974358
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2607352530
Short name T193
Test name
Test status
Simulation time 1208084074 ps
CPU time 8.02 seconds
Started Apr 04 03:37:06 PM PDT 24
Finished Apr 04 03:37:14 PM PDT 24
Peak memory 214436 kb
Host smart-bfba1e17-4181-4e32-841b-b488355e152c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607352530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2607352530
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3466553079
Short name T945
Test name
Test status
Simulation time 271433576 ps
CPU time 5.17 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:16 PM PDT 24
Peak memory 214184 kb
Host smart-a7a40822-a59c-461d-b36b-6e2ede363c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466553079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3466553079
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2106113761
Short name T155
Test name
Test status
Simulation time 370589214 ps
CPU time 4.55 seconds
Started Apr 04 03:37:08 PM PDT 24
Finished Apr 04 03:37:12 PM PDT 24
Peak memory 209636 kb
Host smart-f0bef437-27e5-47cb-b5d0-838e6bef617b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106113761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2106113761
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3833298570
Short name T910
Test name
Test status
Simulation time 10801724 ps
CPU time 0.73 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 205600 kb
Host smart-ba87ede1-3540-4c91-bb01-c0df9b2ce0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833298570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3833298570
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3115863819
Short name T1014
Test name
Test status
Simulation time 59034089 ps
CPU time 0.72 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 205572 kb
Host smart-6b94ad82-7cd8-4746-942e-e9de69e6d3d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115863819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3115863819
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2525227820
Short name T937
Test name
Test status
Simulation time 45844018 ps
CPU time 0.85 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205596 kb
Host smart-d73af457-884c-4871-8910-3f854bbd8713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525227820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2525227820
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4122262875
Short name T1068
Test name
Test status
Simulation time 23946950 ps
CPU time 0.78 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 205512 kb
Host smart-19b5a079-dae1-4393-965c-9e5fad74c8a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122262875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4122262875
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3048512908
Short name T1028
Test name
Test status
Simulation time 11546164 ps
CPU time 0.75 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 205620 kb
Host smart-aaf500dc-4fee-423c-8371-301f49272ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048512908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3048512908
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3448345885
Short name T1036
Test name
Test status
Simulation time 17448558 ps
CPU time 0.72 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 205600 kb
Host smart-74779537-5eb3-4a60-a80e-0d019ddcbcda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448345885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3448345885
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2914960053
Short name T952
Test name
Test status
Simulation time 21488147 ps
CPU time 0.83 seconds
Started Apr 04 03:37:53 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 205588 kb
Host smart-116663de-5294-463c-90a1-1f9de0162157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914960053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2914960053
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2274700824
Short name T1076
Test name
Test status
Simulation time 22824273 ps
CPU time 0.74 seconds
Started Apr 04 03:37:56 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 205460 kb
Host smart-32bc23e8-105d-4c16-81a0-f5df36e5208b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274700824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2274700824
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.5363923
Short name T933
Test name
Test status
Simulation time 30098448 ps
CPU time 0.81 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 205608 kb
Host smart-46b40522-1cce-4932-b15d-033db6f8eaa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5363923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.5363923
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2180058025
Short name T969
Test name
Test status
Simulation time 28332946 ps
CPU time 0.77 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 205544 kb
Host smart-c4cdc378-01a4-4297-a8cb-251365fa5f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180058025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2180058025
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1601323058
Short name T917
Test name
Test status
Simulation time 1657899992 ps
CPU time 5.7 seconds
Started Apr 04 03:37:06 PM PDT 24
Finished Apr 04 03:37:11 PM PDT 24
Peak memory 205788 kb
Host smart-1fe8236f-45ae-46d6-84b2-d7c848719574
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601323058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
601323058
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2652580493
Short name T929
Test name
Test status
Simulation time 517023118 ps
CPU time 8.57 seconds
Started Apr 04 03:37:08 PM PDT 24
Finished Apr 04 03:37:17 PM PDT 24
Peak memory 205876 kb
Host smart-87baeee9-704b-4aae-9c47-3c641126e0ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652580493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
652580493
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.689702644
Short name T1022
Test name
Test status
Simulation time 78867883 ps
CPU time 1.04 seconds
Started Apr 04 03:37:07 PM PDT 24
Finished Apr 04 03:37:08 PM PDT 24
Peak memory 205756 kb
Host smart-ec45ac62-dffc-4308-95bd-49d86a692b5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689702644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.689702644
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4030003200
Short name T986
Test name
Test status
Simulation time 61610371 ps
CPU time 2.22 seconds
Started Apr 04 03:37:05 PM PDT 24
Finished Apr 04 03:37:08 PM PDT 24
Peak memory 214232 kb
Host smart-46d28dcf-2382-4539-a1e8-784d7c0deb44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030003200 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4030003200
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1458192110
Short name T955
Test name
Test status
Simulation time 51753838 ps
CPU time 1.52 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:11 PM PDT 24
Peak memory 205868 kb
Host smart-dc4c0571-3bb0-49aa-969a-79b3dfeafe37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458192110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1458192110
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3770543653
Short name T940
Test name
Test status
Simulation time 51140550 ps
CPU time 0.78 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:11 PM PDT 24
Peak memory 205584 kb
Host smart-f314e582-8327-4655-ab4f-87da3fb2d9d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770543653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3770543653
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.398919900
Short name T1007
Test name
Test status
Simulation time 553569584 ps
CPU time 2.35 seconds
Started Apr 04 03:37:07 PM PDT 24
Finished Apr 04 03:37:09 PM PDT 24
Peak memory 205876 kb
Host smart-58c8852e-b197-430e-8508-f2dbdcc414db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398919900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.398919900
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3560896077
Short name T1031
Test name
Test status
Simulation time 556186298 ps
CPU time 4.15 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:15 PM PDT 24
Peak memory 214408 kb
Host smart-e89f4506-ad29-4ff8-9db8-673e2f6cd1d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560896077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3560896077
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.517724790
Short name T108
Test name
Test status
Simulation time 78638707 ps
CPU time 3.76 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:15 PM PDT 24
Peak memory 222576 kb
Host smart-8d47a7a1-b459-4952-b7dd-06c72047abbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517724790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.517724790
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.125058974
Short name T1075
Test name
Test status
Simulation time 48453994 ps
CPU time 3.14 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:14 PM PDT 24
Peak memory 214108 kb
Host smart-884bfc25-0d3b-4be3-8bda-143e90f00b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125058974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.125058974
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3181299739
Short name T1018
Test name
Test status
Simulation time 431686704 ps
CPU time 7.09 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:16 PM PDT 24
Peak memory 208896 kb
Host smart-d27626a7-3993-4151-9eff-91cd360e5f00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181299739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3181299739
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4095022275
Short name T921
Test name
Test status
Simulation time 53173046 ps
CPU time 0.78 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205540 kb
Host smart-64751eba-b110-4980-8de3-1383ae6ae759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095022275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4095022275
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.438465165
Short name T927
Test name
Test status
Simulation time 51527963 ps
CPU time 0.83 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205644 kb
Host smart-8773d596-7732-418c-a066-a2c36c19bc2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438465165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.438465165
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.226074076
Short name T993
Test name
Test status
Simulation time 54564777 ps
CPU time 0.79 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205536 kb
Host smart-ed26e3c0-1d8f-4861-a6e6-d61eb9f8fc5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226074076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.226074076
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2393817770
Short name T938
Test name
Test status
Simulation time 7896336 ps
CPU time 0.76 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 205524 kb
Host smart-f1b13fa3-52df-4104-b728-1bc10a353e78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393817770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2393817770
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3644804583
Short name T962
Test name
Test status
Simulation time 21975550 ps
CPU time 0.87 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 205524 kb
Host smart-7a22640d-4c8e-4642-a4ca-bd0774e1589c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644804583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3644804583
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1692928477
Short name T1042
Test name
Test status
Simulation time 38478760 ps
CPU time 0.75 seconds
Started Apr 04 03:37:50 PM PDT 24
Finished Apr 04 03:37:51 PM PDT 24
Peak memory 205632 kb
Host smart-78876294-2473-4fc0-94dd-e80053d72eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692928477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1692928477
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2125065086
Short name T999
Test name
Test status
Simulation time 63092209 ps
CPU time 0.73 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 205496 kb
Host smart-e6bc9a65-988c-4c2e-aa90-368cb67004ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125065086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2125065086
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2448900961
Short name T1074
Test name
Test status
Simulation time 71251264 ps
CPU time 0.81 seconds
Started Apr 04 03:37:50 PM PDT 24
Finished Apr 04 03:37:51 PM PDT 24
Peak memory 205556 kb
Host smart-660c901e-8b42-4531-a664-0e59875a4a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448900961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2448900961
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.894939339
Short name T931
Test name
Test status
Simulation time 21290201 ps
CPU time 0.79 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 205576 kb
Host smart-2e92b69d-bf4b-473b-8111-50c4e83725ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894939339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.894939339
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.107546903
Short name T995
Test name
Test status
Simulation time 35004131 ps
CPU time 0.84 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 205508 kb
Host smart-d42c55a7-4dec-46b6-9c8b-33b1a0f02523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107546903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.107546903
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.805566068
Short name T954
Test name
Test status
Simulation time 50788383 ps
CPU time 1.58 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:13 PM PDT 24
Peak memory 214112 kb
Host smart-1f4cd961-27f9-4459-9c23-501f16762cd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805566068 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.805566068
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.213134006
Short name T990
Test name
Test status
Simulation time 24673782 ps
CPU time 1.25 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:11 PM PDT 24
Peak memory 205976 kb
Host smart-d5092dae-7739-4e5b-81eb-051de81638f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213134006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.213134006
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2532267504
Short name T1011
Test name
Test status
Simulation time 14878424 ps
CPU time 0.9 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:11 PM PDT 24
Peak memory 205724 kb
Host smart-92840de5-ecab-4038-83ed-69deba6164cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532267504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2532267504
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1899456869
Short name T133
Test name
Test status
Simulation time 149713923 ps
CPU time 1.34 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:13 PM PDT 24
Peak memory 205872 kb
Host smart-cf249a88-a343-4af7-b5fe-4eac92f17de8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899456869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1899456869
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1254861945
Short name T1050
Test name
Test status
Simulation time 229213712 ps
CPU time 5.33 seconds
Started Apr 04 03:37:06 PM PDT 24
Finished Apr 04 03:37:12 PM PDT 24
Peak memory 214472 kb
Host smart-8360677b-8141-4aed-b663-17daa496f6de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254861945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1254861945
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1361713008
Short name T109
Test name
Test status
Simulation time 396310544 ps
CPU time 13.15 seconds
Started Apr 04 03:37:06 PM PDT 24
Finished Apr 04 03:37:19 PM PDT 24
Peak memory 214436 kb
Host smart-6dfce7c2-1b1b-4905-afdd-f0453b89c325
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361713008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1361713008
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2561764358
Short name T1001
Test name
Test status
Simulation time 46844497 ps
CPU time 2.88 seconds
Started Apr 04 03:37:07 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 214140 kb
Host smart-4e0106af-9b6a-44ee-837e-b6c672052a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561764358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2561764358
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1646978082
Short name T1069
Test name
Test status
Simulation time 19170973 ps
CPU time 1.5 seconds
Started Apr 04 03:37:13 PM PDT 24
Finished Apr 04 03:37:14 PM PDT 24
Peak memory 214088 kb
Host smart-c258fb7e-b32c-49d3-8059-f7b53bd7fd5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646978082 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1646978082
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.786468137
Short name T994
Test name
Test status
Simulation time 75836649 ps
CPU time 1.28 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 205780 kb
Host smart-682df10e-0a8a-4fea-a120-f9a5f4f1eb40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786468137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.786468137
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.677992162
Short name T1070
Test name
Test status
Simulation time 27324744 ps
CPU time 0.67 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 205588 kb
Host smart-698fe2c8-8b8c-4448-ab33-df25e09cd391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677992162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.677992162
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1622538977
Short name T130
Test name
Test status
Simulation time 392484677 ps
CPU time 2.68 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:13 PM PDT 24
Peak memory 205892 kb
Host smart-ae4e7918-23cb-4aea-a73c-55417d495167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622538977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1622538977
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2559148117
Short name T1019
Test name
Test status
Simulation time 204441788 ps
CPU time 5.96 seconds
Started Apr 04 03:37:07 PM PDT 24
Finished Apr 04 03:37:13 PM PDT 24
Peak memory 222596 kb
Host smart-6089944f-9e1a-49ec-93ec-dfb36d37769b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559148117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2559148117
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.206381208
Short name T978
Test name
Test status
Simulation time 4651493259 ps
CPU time 8.65 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:17 PM PDT 24
Peak memory 214596 kb
Host smart-7a78b1b1-9c26-49fb-9ad9-a70c630241ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206381208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.206381208
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1960763660
Short name T1041
Test name
Test status
Simulation time 127246231 ps
CPU time 3.33 seconds
Started Apr 04 03:37:07 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 214132 kb
Host smart-2ab1dfaa-5666-4ce1-956f-b9cfc5b00a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960763660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1960763660
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.4056444321
Short name T1024
Test name
Test status
Simulation time 487486619 ps
CPU time 4.75 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:16 PM PDT 24
Peak memory 214172 kb
Host smart-cffd4772-a14f-4d3e-85c4-1de4f887d12d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056444321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.4056444321
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3846062445
Short name T1055
Test name
Test status
Simulation time 147935735 ps
CPU time 1.34 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:12 PM PDT 24
Peak memory 205876 kb
Host smart-1cedea6a-43fe-4d55-93d2-127717e7ca94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846062445 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3846062445
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3313374208
Short name T131
Test name
Test status
Simulation time 48307897 ps
CPU time 0.91 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 205724 kb
Host smart-1f6c62de-03c9-4e84-8aba-8983735ce4d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313374208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3313374208
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1730370445
Short name T916
Test name
Test status
Simulation time 13546700 ps
CPU time 0.71 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:12 PM PDT 24
Peak memory 205540 kb
Host smart-8aa725c6-5957-46da-8ad7-adc82baf728e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730370445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1730370445
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3811555194
Short name T989
Test name
Test status
Simulation time 20975090 ps
CPU time 1.63 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:13 PM PDT 24
Peak memory 205892 kb
Host smart-e79e870a-ffb5-4ebe-8d44-accad6b5bfd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811555194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3811555194
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.195835965
Short name T958
Test name
Test status
Simulation time 477740072 ps
CPU time 3.68 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:13 PM PDT 24
Peak memory 214404 kb
Host smart-e4cc573a-375b-438a-aa86-226f5b7462f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195835965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.195835965
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.382112672
Short name T988
Test name
Test status
Simulation time 503784625 ps
CPU time 9.91 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:20 PM PDT 24
Peak memory 214428 kb
Host smart-a26b6e23-3201-42c8-bcae-3cc29c1d1057
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382112672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.382112672
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3576840657
Short name T1056
Test name
Test status
Simulation time 187418111 ps
CPU time 2.93 seconds
Started Apr 04 03:37:13 PM PDT 24
Finished Apr 04 03:37:16 PM PDT 24
Peak memory 217168 kb
Host smart-14097e5f-09cb-4b22-83cd-6e0f28293e20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576840657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3576840657
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.425177630
Short name T992
Test name
Test status
Simulation time 124303363 ps
CPU time 1.68 seconds
Started Apr 04 03:37:22 PM PDT 24
Finished Apr 04 03:37:24 PM PDT 24
Peak memory 214252 kb
Host smart-62ac2643-55ba-402f-899c-4d0010d19567
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425177630 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.425177630
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1791911635
Short name T928
Test name
Test status
Simulation time 24137449 ps
CPU time 0.94 seconds
Started Apr 04 03:37:25 PM PDT 24
Finished Apr 04 03:37:26 PM PDT 24
Peak memory 205664 kb
Host smart-eaf2563f-1206-4f2b-8209-20c5d84b924a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791911635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1791911635
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1066736365
Short name T1003
Test name
Test status
Simulation time 33868990 ps
CPU time 0.73 seconds
Started Apr 04 03:37:21 PM PDT 24
Finished Apr 04 03:37:22 PM PDT 24
Peak memory 205640 kb
Host smart-b358fbb9-8424-4b2f-8f75-dae814f9ebf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066736365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1066736365
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.887682169
Short name T922
Test name
Test status
Simulation time 45782548 ps
CPU time 1.68 seconds
Started Apr 04 03:37:18 PM PDT 24
Finished Apr 04 03:37:20 PM PDT 24
Peak memory 205888 kb
Host smart-7b4cb14e-8112-4a84-99be-f95f4f856598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887682169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.887682169
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.91639414
Short name T112
Test name
Test status
Simulation time 413493340 ps
CPU time 9.33 seconds
Started Apr 04 03:37:11 PM PDT 24
Finished Apr 04 03:37:21 PM PDT 24
Peak memory 214400 kb
Host smart-07ebd025-f528-49c5-abb6-2b8332a48596
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91639414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_
reg_errors.91639414
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.698617307
Short name T115
Test name
Test status
Simulation time 228706695 ps
CPU time 7.21 seconds
Started Apr 04 03:37:10 PM PDT 24
Finished Apr 04 03:37:17 PM PDT 24
Peak memory 214332 kb
Host smart-cc1f1198-1e38-4d01-8194-2678b8373043
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698617307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.698617307
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1501868900
Short name T170
Test name
Test status
Simulation time 322202795 ps
CPU time 2.26 seconds
Started Apr 04 03:37:09 PM PDT 24
Finished Apr 04 03:37:11 PM PDT 24
Peak memory 214100 kb
Host smart-f3b1bae0-6b79-4b42-8fc5-010186cc2f96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501868900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1501868900
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.557860474
Short name T166
Test name
Test status
Simulation time 471573647 ps
CPU time 5.66 seconds
Started Apr 04 03:37:21 PM PDT 24
Finished Apr 04 03:37:27 PM PDT 24
Peak memory 214068 kb
Host smart-b480ed22-fa5f-40a5-8af0-6d6cc898701d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557860474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
557860474
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1621731534
Short name T911
Test name
Test status
Simulation time 69826974 ps
CPU time 2.2 seconds
Started Apr 04 03:37:20 PM PDT 24
Finished Apr 04 03:37:23 PM PDT 24
Peak memory 214112 kb
Host smart-70664f0b-ddd0-434a-9306-94cbe8c76f6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621731534 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1621731534
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1705896557
Short name T1010
Test name
Test status
Simulation time 34702084 ps
CPU time 1.17 seconds
Started Apr 04 03:37:21 PM PDT 24
Finished Apr 04 03:37:22 PM PDT 24
Peak memory 205856 kb
Host smart-50636aef-c8ec-4f54-a7f8-f192bcf0f2b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705896557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1705896557
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3749495453
Short name T924
Test name
Test status
Simulation time 8859251 ps
CPU time 0.77 seconds
Started Apr 04 03:37:23 PM PDT 24
Finished Apr 04 03:37:24 PM PDT 24
Peak memory 205536 kb
Host smart-aa09fcfa-603d-4e32-940f-ee3e46b6a20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749495453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3749495453
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.705343504
Short name T1063
Test name
Test status
Simulation time 71937869 ps
CPU time 1.35 seconds
Started Apr 04 03:37:27 PM PDT 24
Finished Apr 04 03:37:31 PM PDT 24
Peak memory 205880 kb
Host smart-41fe97a7-5dba-4752-b457-271579e4a53c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705343504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.705343504
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.280840144
Short name T1077
Test name
Test status
Simulation time 82080390 ps
CPU time 1.51 seconds
Started Apr 04 03:37:20 PM PDT 24
Finished Apr 04 03:37:22 PM PDT 24
Peak memory 214492 kb
Host smart-d6b73801-10bd-4969-b92a-a73d78f7be1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280840144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.280840144
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.964872376
Short name T1020
Test name
Test status
Simulation time 3202474126 ps
CPU time 13.88 seconds
Started Apr 04 03:37:29 PM PDT 24
Finished Apr 04 03:37:44 PM PDT 24
Peak memory 221136 kb
Host smart-33bda6da-50fb-4920-879c-e407aa1a2667
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964872376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.964872376
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1422657547
Short name T985
Test name
Test status
Simulation time 307949181 ps
CPU time 4.11 seconds
Started Apr 04 03:37:24 PM PDT 24
Finished Apr 04 03:37:28 PM PDT 24
Peak memory 214100 kb
Host smart-a9fc2d37-e77f-4136-a34e-23972558f456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422657547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1422657547
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3647176679
Short name T165
Test name
Test status
Simulation time 196906219 ps
CPU time 4.94 seconds
Started Apr 04 03:37:23 PM PDT 24
Finished Apr 04 03:37:28 PM PDT 24
Peak memory 209208 kb
Host smart-a734e9df-1def-4dec-8c6e-3f7d75181ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647176679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3647176679
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.307034996
Short name T215
Test name
Test status
Simulation time 1677188807 ps
CPU time 9.69 seconds
Started Apr 04 12:45:10 PM PDT 24
Finished Apr 04 12:45:19 PM PDT 24
Peak memory 214840 kb
Host smart-ee64e00a-0279-4d8b-835c-5e3b04ffce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307034996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.307034996
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2539039555
Short name T483
Test name
Test status
Simulation time 114656000 ps
CPU time 2.14 seconds
Started Apr 04 12:45:07 PM PDT 24
Finished Apr 04 12:45:09 PM PDT 24
Peak memory 206936 kb
Host smart-5f06e1c0-4536-418d-a16a-0cc6ad0e0622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539039555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2539039555
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3674608889
Short name T295
Test name
Test status
Simulation time 760771199 ps
CPU time 7.64 seconds
Started Apr 04 12:45:25 PM PDT 24
Finished Apr 04 12:45:33 PM PDT 24
Peak memory 222740 kb
Host smart-23c84b7a-0aac-4549-a2ad-1f2e65fe1ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674608889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3674608889
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.707439037
Short name T547
Test name
Test status
Simulation time 101589193 ps
CPU time 4.42 seconds
Started Apr 04 12:45:08 PM PDT 24
Finished Apr 04 12:45:13 PM PDT 24
Peak memory 220516 kb
Host smart-5c0b8e87-2001-4ac8-ab0e-f6092394bd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707439037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.707439037
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.512670956
Short name T727
Test name
Test status
Simulation time 1232410105 ps
CPU time 9.8 seconds
Started Apr 04 12:45:07 PM PDT 24
Finished Apr 04 12:45:17 PM PDT 24
Peak memory 210176 kb
Host smart-1bc4f8ca-61f7-4479-a061-8be2ddd513e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512670956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.512670956
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2849249316
Short name T103
Test name
Test status
Simulation time 2421286028 ps
CPU time 20.46 seconds
Started Apr 04 12:45:11 PM PDT 24
Finished Apr 04 12:45:32 PM PDT 24
Peak memory 237572 kb
Host smart-6e55e1d6-fabc-49ff-a664-043da2a0817e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849249316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2849249316
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.741894296
Short name T563
Test name
Test status
Simulation time 4183204891 ps
CPU time 26.59 seconds
Started Apr 04 12:45:08 PM PDT 24
Finished Apr 04 12:45:35 PM PDT 24
Peak memory 208556 kb
Host smart-8a616dd0-4efe-4c81-9b33-7a5262f64aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741894296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.741894296
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3835502951
Short name T754
Test name
Test status
Simulation time 427360974 ps
CPU time 5.05 seconds
Started Apr 04 12:45:15 PM PDT 24
Finished Apr 04 12:45:20 PM PDT 24
Peak memory 208820 kb
Host smart-bf1302d5-d02c-4be3-90ec-5503c447abc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835502951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3835502951
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1901338121
Short name T400
Test name
Test status
Simulation time 911738952 ps
CPU time 9.85 seconds
Started Apr 04 12:45:13 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 207076 kb
Host smart-588f7a07-c00e-45e1-ae36-d05be2f10e4b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901338121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1901338121
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.437131705
Short name T642
Test name
Test status
Simulation time 961330679 ps
CPU time 32.48 seconds
Started Apr 04 12:45:11 PM PDT 24
Finished Apr 04 12:45:44 PM PDT 24
Peak memory 208816 kb
Host smart-df068d1a-3317-4431-a929-18f4d6d9e7e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437131705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.437131705
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.392341614
Short name T728
Test name
Test status
Simulation time 69425791 ps
CPU time 2.36 seconds
Started Apr 04 12:45:13 PM PDT 24
Finished Apr 04 12:45:16 PM PDT 24
Peak memory 208444 kb
Host smart-e5e5163d-126a-46bd-b3fb-cdc0d36c8c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392341614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.392341614
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3174871368
Short name T466
Test name
Test status
Simulation time 4047574355 ps
CPU time 25 seconds
Started Apr 04 12:45:19 PM PDT 24
Finished Apr 04 12:45:44 PM PDT 24
Peak memory 207856 kb
Host smart-65114c85-d26a-411d-bcb3-f815e6dfbe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174871368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3174871368
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2496396422
Short name T651
Test name
Test status
Simulation time 338226742 ps
CPU time 5.3 seconds
Started Apr 04 12:45:22 PM PDT 24
Finished Apr 04 12:45:27 PM PDT 24
Peak memory 208020 kb
Host smart-b416db7c-31ea-4a8f-8294-c791a69a462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496396422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2496396422
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2328715399
Short name T487
Test name
Test status
Simulation time 14495188 ps
CPU time 0.93 seconds
Started Apr 04 12:45:04 PM PDT 24
Finished Apr 04 12:45:05 PM PDT 24
Peak memory 206280 kb
Host smart-da1c4ab8-bb5a-43f3-a1ca-bcfa07e916ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328715399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2328715399
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1940729561
Short name T237
Test name
Test status
Simulation time 45510051 ps
CPU time 2.97 seconds
Started Apr 04 12:45:06 PM PDT 24
Finished Apr 04 12:45:09 PM PDT 24
Peak memory 215288 kb
Host smart-c6b3fd05-f4da-4592-9a1b-0265ac0c5fbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940729561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1940729561
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1829758832
Short name T304
Test name
Test status
Simulation time 154441667 ps
CPU time 3.89 seconds
Started Apr 04 12:45:08 PM PDT 24
Finished Apr 04 12:45:12 PM PDT 24
Peak memory 214732 kb
Host smart-8531aa0a-9453-4a51-88af-366502383621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829758832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1829758832
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1976114068
Short name T294
Test name
Test status
Simulation time 199863826 ps
CPU time 3.3 seconds
Started Apr 04 12:45:09 PM PDT 24
Finished Apr 04 12:45:12 PM PDT 24
Peak memory 208488 kb
Host smart-712afc9f-8526-48d3-89b8-394dab69487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976114068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1976114068
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3954890650
Short name T315
Test name
Test status
Simulation time 506480238 ps
CPU time 7.87 seconds
Started Apr 04 12:45:00 PM PDT 24
Finished Apr 04 12:45:08 PM PDT 24
Peak memory 214540 kb
Host smart-62ac12ed-cbef-41ab-a16a-bdc71e13446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954890650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3954890650
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3211008379
Short name T755
Test name
Test status
Simulation time 71681031 ps
CPU time 3.82 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:45:16 PM PDT 24
Peak memory 209748 kb
Host smart-5f0a0300-6ce6-4ce1-bcd5-2e50afcafa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211008379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3211008379
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1010329377
Short name T785
Test name
Test status
Simulation time 679822950 ps
CPU time 13.95 seconds
Started Apr 04 12:45:09 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 210704 kb
Host smart-3ea02075-a298-45a3-8997-40cab65c1e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010329377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1010329377
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4250285092
Short name T85
Test name
Test status
Simulation time 556352849 ps
CPU time 4.24 seconds
Started Apr 04 12:45:09 PM PDT 24
Finished Apr 04 12:45:14 PM PDT 24
Peak memory 208040 kb
Host smart-4c482ef2-164f-4c60-b881-323e8a9ef5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250285092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4250285092
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.342819924
Short name T704
Test name
Test status
Simulation time 151532401 ps
CPU time 5.68 seconds
Started Apr 04 12:45:09 PM PDT 24
Finished Apr 04 12:45:15 PM PDT 24
Peak memory 208080 kb
Host smart-53f311f8-84a8-4bf4-9f93-0e080814e4af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342819924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.342819924
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2403544962
Short name T514
Test name
Test status
Simulation time 21751120 ps
CPU time 1.75 seconds
Started Apr 04 12:45:04 PM PDT 24
Finished Apr 04 12:45:06 PM PDT 24
Peak memory 207004 kb
Host smart-aefdd743-1249-477d-a8a8-2bcc1645995f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403544962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2403544962
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.442840916
Short name T606
Test name
Test status
Simulation time 466923148 ps
CPU time 2.86 seconds
Started Apr 04 12:45:02 PM PDT 24
Finished Apr 04 12:45:05 PM PDT 24
Peak memory 209096 kb
Host smart-1724a07f-89e7-485d-9f1e-714ac278673e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442840916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.442840916
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3392872162
Short name T793
Test name
Test status
Simulation time 192259181 ps
CPU time 2.4 seconds
Started Apr 04 12:45:04 PM PDT 24
Finished Apr 04 12:45:06 PM PDT 24
Peak memory 206788 kb
Host smart-406702dd-3e5c-4a9e-aea2-43bb35b03481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392872162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3392872162
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1932240601
Short name T70
Test name
Test status
Simulation time 310630592 ps
CPU time 12.03 seconds
Started Apr 04 12:45:04 PM PDT 24
Finished Apr 04 12:45:17 PM PDT 24
Peak memory 222660 kb
Host smart-3325d930-c3e3-43e8-93dc-749476b63cc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932240601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1932240601
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3040118983
Short name T733
Test name
Test status
Simulation time 14422987384 ps
CPU time 45.33 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 210812 kb
Host smart-05572bbb-139e-4bb5-b275-2aacacbea82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040118983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3040118983
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4056340424
Short name T798
Test name
Test status
Simulation time 85817722 ps
CPU time 1.84 seconds
Started Apr 04 12:45:15 PM PDT 24
Finished Apr 04 12:45:17 PM PDT 24
Peak memory 210000 kb
Host smart-802567cc-4d3a-4132-868a-093d457c6212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056340424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4056340424
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.399566092
Short name T598
Test name
Test status
Simulation time 33322897 ps
CPU time 0.72 seconds
Started Apr 04 12:45:43 PM PDT 24
Finished Apr 04 12:45:44 PM PDT 24
Peak memory 206216 kb
Host smart-197e262b-c5d3-4ec2-9865-47f624815c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399566092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.399566092
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3344536375
Short name T420
Test name
Test status
Simulation time 161817805 ps
CPU time 3.27 seconds
Started Apr 04 12:45:44 PM PDT 24
Finished Apr 04 12:45:48 PM PDT 24
Peak memory 215300 kb
Host smart-6ef51ef0-bb40-4a48-a643-ad1337f3e4bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344536375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3344536375
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.4183417828
Short name T413
Test name
Test status
Simulation time 183691182 ps
CPU time 3.67 seconds
Started Apr 04 12:45:45 PM PDT 24
Finished Apr 04 12:45:50 PM PDT 24
Peak memory 209448 kb
Host smart-19fbb73c-1b0c-4f27-a4fc-91a2aae12819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183417828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4183417828
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1904091978
Short name T771
Test name
Test status
Simulation time 9445980834 ps
CPU time 65.55 seconds
Started Apr 04 12:45:45 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 210580 kb
Host smart-afc40dab-84e4-4698-819a-df6eccd7b5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904091978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1904091978
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1008663300
Short name T821
Test name
Test status
Simulation time 56761905 ps
CPU time 3.25 seconds
Started Apr 04 12:45:56 PM PDT 24
Finished Apr 04 12:45:59 PM PDT 24
Peak memory 214888 kb
Host smart-a29acaaa-1075-4abe-a174-95318afd0f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008663300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1008663300
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2970888363
Short name T493
Test name
Test status
Simulation time 118319180 ps
CPU time 5.29 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 214568 kb
Host smart-dcff9bd0-626c-4881-befa-94154781b3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970888363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2970888363
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1655592085
Short name T687
Test name
Test status
Simulation time 174743781 ps
CPU time 3.62 seconds
Started Apr 04 12:45:40 PM PDT 24
Finished Apr 04 12:45:43 PM PDT 24
Peak memory 209524 kb
Host smart-dff996ef-2a2c-46ef-ac33-597f4dbffff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655592085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1655592085
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2323702210
Short name T373
Test name
Test status
Simulation time 559207619 ps
CPU time 4.68 seconds
Started Apr 04 12:45:55 PM PDT 24
Finished Apr 04 12:46:00 PM PDT 24
Peak memory 207000 kb
Host smart-73d3c8b2-9d8f-4901-9143-c8ebcbb196b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323702210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2323702210
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.574560537
Short name T806
Test name
Test status
Simulation time 123114183 ps
CPU time 4.21 seconds
Started Apr 04 12:45:46 PM PDT 24
Finished Apr 04 12:45:51 PM PDT 24
Peak memory 206876 kb
Host smart-70fafc9e-916d-4801-815f-090c11673313
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574560537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.574560537
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4180867831
Short name T187
Test name
Test status
Simulation time 118533817 ps
CPU time 2.5 seconds
Started Apr 04 12:45:42 PM PDT 24
Finished Apr 04 12:45:46 PM PDT 24
Peak memory 207220 kb
Host smart-04ef7cf1-e437-4aa6-b57b-be6b2052a7ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180867831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4180867831
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3678862257
Short name T355
Test name
Test status
Simulation time 51406417 ps
CPU time 2.08 seconds
Started Apr 04 12:45:47 PM PDT 24
Finished Apr 04 12:45:50 PM PDT 24
Peak memory 208884 kb
Host smart-45d063f1-2e54-42c5-8bec-55ca63c7dad8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678862257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3678862257
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1218329637
Short name T528
Test name
Test status
Simulation time 75947942 ps
CPU time 2.14 seconds
Started Apr 04 12:45:46 PM PDT 24
Finished Apr 04 12:45:50 PM PDT 24
Peak memory 209356 kb
Host smart-4e586515-ba74-4928-868d-1d37cc7aa415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218329637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1218329637
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2618165057
Short name T557
Test name
Test status
Simulation time 49881798 ps
CPU time 2.63 seconds
Started Apr 04 12:45:53 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 208512 kb
Host smart-8e1e4c44-3e42-4424-9144-15ccd5f8b3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618165057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2618165057
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3926337226
Short name T889
Test name
Test status
Simulation time 572899490 ps
CPU time 8.12 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 218524 kb
Host smart-7deb7aa5-9a21-4e84-835a-1970ae9f18e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926337226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3926337226
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2636428898
Short name T521
Test name
Test status
Simulation time 526339650 ps
CPU time 6.31 seconds
Started Apr 04 12:45:47 PM PDT 24
Finished Apr 04 12:45:54 PM PDT 24
Peak memory 210468 kb
Host smart-0a15cd01-db14-48ca-b132-649380907c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636428898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2636428898
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.784748948
Short name T516
Test name
Test status
Simulation time 15639394 ps
CPU time 0.94 seconds
Started Apr 04 12:45:47 PM PDT 24
Finished Apr 04 12:45:49 PM PDT 24
Peak memory 206352 kb
Host smart-525d13d7-2aa0-4333-8f2a-d94cb96db97a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784748948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.784748948
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1044780133
Short name T421
Test name
Test status
Simulation time 56815535 ps
CPU time 3.37 seconds
Started Apr 04 12:45:43 PM PDT 24
Finished Apr 04 12:45:48 PM PDT 24
Peak memory 214560 kb
Host smart-c82372fa-f9a5-4ac5-93e7-29c0b0e944b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044780133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1044780133
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3885517565
Short name T310
Test name
Test status
Simulation time 193653024 ps
CPU time 5.18 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 208980 kb
Host smart-18a63fad-2449-4a1b-9a20-14e0d44c14c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885517565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3885517565
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3966650619
Short name T98
Test name
Test status
Simulation time 337598155 ps
CPU time 4.13 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 222456 kb
Host smart-35314829-1f08-40a5-ad63-3495c09821a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966650619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3966650619
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_random.2712159163
Short name T743
Test name
Test status
Simulation time 54518539 ps
CPU time 3.67 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 208508 kb
Host smart-590b62c6-2670-4c83-8d12-40da9dd3fd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712159163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2712159163
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1329959607
Short name T587
Test name
Test status
Simulation time 50336329 ps
CPU time 2.97 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 207040 kb
Host smart-55057079-33d7-4376-88b9-35ac23154d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329959607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1329959607
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.285479366
Short name T211
Test name
Test status
Simulation time 155634948 ps
CPU time 5.93 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 207928 kb
Host smart-3655bc1f-8528-4630-a4bf-758f48aff186
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285479366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.285479366
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1573037758
Short name T468
Test name
Test status
Simulation time 285045233 ps
CPU time 2.88 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 207068 kb
Host smart-8544aec4-baa5-43f8-9c04-df6faf1adcf2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573037758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1573037758
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.465489057
Short name T605
Test name
Test status
Simulation time 347397662 ps
CPU time 3.48 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:45:52 PM PDT 24
Peak memory 210460 kb
Host smart-ac14f2bb-34d8-4e51-b1bd-a3c21202d095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465489057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.465489057
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.703028822
Short name T645
Test name
Test status
Simulation time 159148417 ps
CPU time 2.27 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:53 PM PDT 24
Peak memory 206876 kb
Host smart-24e164c1-2b1d-404a-b88c-df47c9bbd0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703028822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.703028822
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.163893768
Short name T42
Test name
Test status
Simulation time 548626867 ps
CPU time 18.88 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:46:10 PM PDT 24
Peak memory 217072 kb
Host smart-b5426ee6-f654-4321-acae-d88a8cccc0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163893768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.163893768
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3526185546
Short name T262
Test name
Test status
Simulation time 559946528 ps
CPU time 4.52 seconds
Started Apr 04 12:45:44 PM PDT 24
Finished Apr 04 12:45:49 PM PDT 24
Peak memory 218732 kb
Host smart-77ce96c3-1952-460c-8011-ba29fae11aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526185546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3526185546
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.810571455
Short name T164
Test name
Test status
Simulation time 154314027 ps
CPU time 2.14 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:45:51 PM PDT 24
Peak memory 210260 kb
Host smart-f1d5d93c-304b-4ae8-9db7-a22826a525a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810571455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.810571455
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2177277900
Short name T636
Test name
Test status
Simulation time 33558861 ps
CPU time 0.81 seconds
Started Apr 04 12:45:39 PM PDT 24
Finished Apr 04 12:45:40 PM PDT 24
Peak memory 206284 kb
Host smart-aea5e8f3-a0c1-4281-b976-dcf64c89a176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177277900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2177277900
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.469330085
Short name T891
Test name
Test status
Simulation time 124759342 ps
CPU time 3.99 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 210364 kb
Host smart-1fe7f1f9-f9ef-415d-8cbe-91b865e7e063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469330085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.469330085
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.22012486
Short name T672
Test name
Test status
Simulation time 60263428 ps
CPU time 2.59 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 209288 kb
Host smart-d15a3019-4049-4b67-b784-23f30a6a9687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22012486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.22012486
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3261050303
Short name T353
Test name
Test status
Simulation time 840092987 ps
CPU time 21.87 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:46:13 PM PDT 24
Peak memory 214512 kb
Host smart-66b85c1f-d609-4758-b626-1a9181a273d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261050303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3261050303
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.478711697
Short name T46
Test name
Test status
Simulation time 512661532 ps
CPU time 2.55 seconds
Started Apr 04 12:45:47 PM PDT 24
Finished Apr 04 12:45:50 PM PDT 24
Peak memory 214584 kb
Host smart-c1c1e91f-6e4f-43da-85d0-c8602f2ac76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478711697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.478711697
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3809158774
Short name T412
Test name
Test status
Simulation time 648918427 ps
CPU time 5.55 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 208472 kb
Host smart-b4a28621-fe0b-4692-ace3-4468ec624a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809158774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3809158774
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.945273287
Short name T565
Test name
Test status
Simulation time 212965870 ps
CPU time 7.58 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:46:00 PM PDT 24
Peak memory 208720 kb
Host smart-638679c2-c147-47f6-be0f-2bc41339b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945273287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.945273287
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1181600852
Short name T550
Test name
Test status
Simulation time 43886689 ps
CPU time 2.7 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 209008 kb
Host smart-749f8a31-f734-456c-aa99-bbf3d815faa7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181600852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1181600852
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2189254446
Short name T452
Test name
Test status
Simulation time 629401476 ps
CPU time 3.28 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:54 PM PDT 24
Peak memory 207068 kb
Host smart-b60f0b9b-bda7-4f79-a45a-514edf5bc06e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189254446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2189254446
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1110777455
Short name T752
Test name
Test status
Simulation time 4497397917 ps
CPU time 43.61 seconds
Started Apr 04 12:45:47 PM PDT 24
Finished Apr 04 12:46:32 PM PDT 24
Peak memory 208220 kb
Host smart-a682a127-534f-427a-be36-1ab5e4ae9414
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110777455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1110777455
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3549127049
Short name T906
Test name
Test status
Simulation time 35717408 ps
CPU time 1.95 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:45:51 PM PDT 24
Peak memory 208932 kb
Host smart-f725a689-632b-41bf-9173-677e8d1f951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549127049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3549127049
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3839438932
Short name T194
Test name
Test status
Simulation time 207753939 ps
CPU time 2.36 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:54 PM PDT 24
Peak memory 206984 kb
Host smart-4db3b284-d70f-4052-8f09-34d49335eb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839438932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3839438932
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3184502026
Short name T775
Test name
Test status
Simulation time 812948348 ps
CPU time 12.39 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:46:04 PM PDT 24
Peak memory 210504 kb
Host smart-bd1fbda0-d087-4742-ac87-42a361b96ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184502026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3184502026
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1163326535
Short name T564
Test name
Test status
Simulation time 114891355 ps
CPU time 2.47 seconds
Started Apr 04 12:45:43 PM PDT 24
Finished Apr 04 12:45:46 PM PDT 24
Peak memory 210268 kb
Host smart-35c79a71-3748-472a-9647-566a29af3206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163326535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1163326535
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2573129975
Short name T474
Test name
Test status
Simulation time 94960969 ps
CPU time 0.78 seconds
Started Apr 04 12:45:47 PM PDT 24
Finished Apr 04 12:45:49 PM PDT 24
Peak memory 206128 kb
Host smart-a1744b9b-3b8c-4e42-96bd-1f651d4d3a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573129975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2573129975
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.69769012
Short name T670
Test name
Test status
Simulation time 249289642 ps
CPU time 5.49 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:45:54 PM PDT 24
Peak memory 209640 kb
Host smart-96c44a23-d9ea-4d62-9304-b675db66fde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69769012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.69769012
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4191624942
Short name T339
Test name
Test status
Simulation time 137683761 ps
CPU time 5.7 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 214672 kb
Host smart-af67e7b4-2938-4bfe-a624-1f34ad770ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191624942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4191624942
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4269264336
Short name T450
Test name
Test status
Simulation time 63920818 ps
CPU time 2.34 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:54 PM PDT 24
Peak memory 208500 kb
Host smart-a2bb2cde-6a0f-494a-9df3-751c367ade31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269264336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4269264336
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3174715169
Short name T900
Test name
Test status
Simulation time 256961812 ps
CPU time 8.39 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:59 PM PDT 24
Peak memory 214496 kb
Host smart-648a0291-bd9b-4c69-a9b5-dae531461181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174715169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3174715169
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.488115131
Short name T345
Test name
Test status
Simulation time 98744365 ps
CPU time 4.23 seconds
Started Apr 04 12:45:46 PM PDT 24
Finished Apr 04 12:45:52 PM PDT 24
Peak memory 209080 kb
Host smart-3b6edda7-7b26-4aa9-b7d4-4459c52d4192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488115131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.488115131
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.567114634
Short name T774
Test name
Test status
Simulation time 255532827 ps
CPU time 3.12 seconds
Started Apr 04 12:45:41 PM PDT 24
Finished Apr 04 12:45:44 PM PDT 24
Peak memory 209024 kb
Host smart-f462efc7-a9f2-49cc-b7b2-dd6ba98239b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567114634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.567114634
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2261266100
Short name T545
Test name
Test status
Simulation time 280279942 ps
CPU time 6.31 seconds
Started Apr 04 12:45:46 PM PDT 24
Finished Apr 04 12:45:54 PM PDT 24
Peak memory 208248 kb
Host smart-aaff7264-9250-4710-83cc-650f941e5acd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261266100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2261266100
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1631609406
Short name T633
Test name
Test status
Simulation time 3970770169 ps
CPU time 7.61 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 208284 kb
Host smart-dd9991fb-30f8-40aa-a7a1-72165aef1edc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631609406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1631609406
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2388658727
Short name T554
Test name
Test status
Simulation time 152113564 ps
CPU time 4.31 seconds
Started Apr 04 12:45:53 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 209448 kb
Host smart-f38e4735-027c-4f1b-a498-ea528698ae0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388658727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2388658727
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1050221788
Short name T438
Test name
Test status
Simulation time 757670947 ps
CPU time 13.49 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:46:06 PM PDT 24
Peak memory 206916 kb
Host smart-618f9f3f-c340-485e-bc6f-fbe5f3189ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050221788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1050221788
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3008890714
Short name T188
Test name
Test status
Simulation time 785656137 ps
CPU time 5.55 seconds
Started Apr 04 12:45:47 PM PDT 24
Finished Apr 04 12:45:53 PM PDT 24
Peak memory 208316 kb
Host smart-deec4341-c3e7-4eb9-adf7-bd61c3a20e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008890714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3008890714
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.650534922
Short name T583
Test name
Test status
Simulation time 141565467 ps
CPU time 1.47 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:51 PM PDT 24
Peak memory 210088 kb
Host smart-7a6d69d5-7acf-4bb5-995b-db90989b1262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650534922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.650534922
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1731863768
Short name T525
Test name
Test status
Simulation time 21912587 ps
CPU time 1 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:52 PM PDT 24
Peak memory 206404 kb
Host smart-c647638f-d02a-4b9a-91b9-d216727c35d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731863768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1731863768
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2030166035
Short name T409
Test name
Test status
Simulation time 56483045 ps
CPU time 3.6 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:45:52 PM PDT 24
Peak memory 214476 kb
Host smart-e360be04-4bb2-4c06-b24a-b7356acf5dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030166035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2030166035
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2086669962
Short name T777
Test name
Test status
Simulation time 88997129 ps
CPU time 1.75 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:51 PM PDT 24
Peak memory 207764 kb
Host smart-99a49226-b30f-4411-acd7-02e16f9447b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086669962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2086669962
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.11063403
Short name T342
Test name
Test status
Simulation time 348678092 ps
CPU time 4.04 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:53 PM PDT 24
Peak memory 221416 kb
Host smart-031aac50-b7c0-40f2-86ca-b7725fc95db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11063403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.11063403
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3817198192
Short name T862
Test name
Test status
Simulation time 742455742 ps
CPU time 31.03 seconds
Started Apr 04 12:45:45 PM PDT 24
Finished Apr 04 12:46:17 PM PDT 24
Peak memory 222856 kb
Host smart-63659d02-9006-47eb-8cc2-5fd0acdc33c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817198192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3817198192
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1209554572
Short name T835
Test name
Test status
Simulation time 161153815 ps
CPU time 6.55 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 210112 kb
Host smart-d765fbf8-4336-417d-b49a-b917cc2ca4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209554572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1209554572
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2460390482
Short name T374
Test name
Test status
Simulation time 2443485490 ps
CPU time 47.45 seconds
Started Apr 04 12:45:46 PM PDT 24
Finished Apr 04 12:46:34 PM PDT 24
Peak memory 209672 kb
Host smart-8c3e25bc-2fe7-41ab-8797-6032c637e709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460390482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2460390482
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2779300584
Short name T359
Test name
Test status
Simulation time 12267700244 ps
CPU time 43 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:46:32 PM PDT 24
Peak memory 208496 kb
Host smart-64d86d29-158c-4a06-b383-f9107e65ed5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779300584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2779300584
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.25748236
Short name T838
Test name
Test status
Simulation time 34024078 ps
CPU time 2.47 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 207052 kb
Host smart-c0079b46-f63a-431f-af62-d5745fabcd85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25748236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.25748236
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2575719138
Short name T683
Test name
Test status
Simulation time 215341408 ps
CPU time 3.04 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 208856 kb
Host smart-5e68c768-c68a-4500-b076-c9f3807574a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575719138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2575719138
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2160139387
Short name T681
Test name
Test status
Simulation time 71722790 ps
CPU time 3.05 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 207024 kb
Host smart-9951264f-feff-42ca-bcaa-7e3d4e70bf00
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160139387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2160139387
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.408668751
Short name T81
Test name
Test status
Simulation time 105730251 ps
CPU time 3.29 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 215792 kb
Host smart-37dd9f4a-f6f2-435f-aece-8298b339eff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408668751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.408668751
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1219114900
Short name T432
Test name
Test status
Simulation time 8452381891 ps
CPU time 70.39 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:46:59 PM PDT 24
Peak memory 208532 kb
Host smart-4a2db1ba-ac8f-44b3-8171-bd798236e016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219114900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1219114900
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.340224418
Short name T186
Test name
Test status
Simulation time 3907089151 ps
CPU time 52.15 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:46:43 PM PDT 24
Peak memory 216248 kb
Host smart-05fd59b5-d7b9-464b-af79-91a3a9185307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340224418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.340224418
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1811380762
Short name T668
Test name
Test status
Simulation time 343166318 ps
CPU time 13.03 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 220032 kb
Host smart-cc73ce15-a50c-4302-a887-cdcdd587bf31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811380762 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1811380762
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1163327817
Short name T620
Test name
Test status
Simulation time 76932495 ps
CPU time 3.71 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 210040 kb
Host smart-72d669ea-2fc2-4a0c-99fe-8efb8b8ed469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163327817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1163327817
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1950268530
Short name T551
Test name
Test status
Simulation time 464158152 ps
CPU time 3.72 seconds
Started Apr 04 12:45:53 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 210476 kb
Host smart-c9f5346b-5ee5-4a2e-ac87-f776465ea50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950268530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1950268530
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.113026886
Short name T696
Test name
Test status
Simulation time 17654886 ps
CPU time 0.85 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:45:50 PM PDT 24
Peak memory 206136 kb
Host smart-e688c6c5-7a25-4c87-a702-6e473cb171ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113026886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.113026886
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2381495829
Short name T592
Test name
Test status
Simulation time 29557152 ps
CPU time 1.42 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:53 PM PDT 24
Peak memory 207088 kb
Host smart-fbd4bba8-67d1-473f-8ba5-635a01e73279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381495829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2381495829
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1752169260
Short name T333
Test name
Test status
Simulation time 3369888482 ps
CPU time 34.26 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:46:26 PM PDT 24
Peak memory 222756 kb
Host smart-6500656a-7025-4e70-80e2-b38bebbf8066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752169260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1752169260
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1011104981
Short name T886
Test name
Test status
Simulation time 106238704 ps
CPU time 4.96 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 218700 kb
Host smart-950c2727-4609-438f-9b7d-5f01125be09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011104981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1011104981
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3305548293
Short name T902
Test name
Test status
Simulation time 85795740 ps
CPU time 3.35 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 218528 kb
Host smart-20790f4d-4d1c-48ff-a86d-a2d1b698d8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305548293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3305548293
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.435586790
Short name T260
Test name
Test status
Simulation time 303326028 ps
CPU time 3.82 seconds
Started Apr 04 12:45:47 PM PDT 24
Finished Apr 04 12:45:52 PM PDT 24
Peak memory 208608 kb
Host smart-7a102368-e6ac-4301-b588-d407fbff6f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435586790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.435586790
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.4052355219
Short name T596
Test name
Test status
Simulation time 137791001 ps
CPU time 4.71 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 207068 kb
Host smart-b8483842-29b1-489d-bc66-46d5018faad9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052355219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4052355219
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3062317258
Short name T839
Test name
Test status
Simulation time 1727545100 ps
CPU time 30.93 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:46:20 PM PDT 24
Peak memory 209204 kb
Host smart-3f8ca8da-6bf8-4753-9b4c-9f3b66bd6885
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062317258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3062317258
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1278588311
Short name T496
Test name
Test status
Simulation time 425456882 ps
CPU time 3.42 seconds
Started Apr 04 12:45:55 PM PDT 24
Finished Apr 04 12:45:59 PM PDT 24
Peak memory 208980 kb
Host smart-fc2a0d5b-1ad5-4240-ab21-6e15fb48eb36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278588311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1278588311
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1950481500
Short name T781
Test name
Test status
Simulation time 62803087 ps
CPU time 2.35 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:53 PM PDT 24
Peak memory 207656 kb
Host smart-4f322209-2061-4091-bff8-225a0b164e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950481500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1950481500
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2408433813
Short name T16
Test name
Test status
Simulation time 12574886709 ps
CPU time 44.39 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:46:36 PM PDT 24
Peak memory 209080 kb
Host smart-9ed1efc5-3018-4e2b-b474-bc6cd898749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408433813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2408433813
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2688483261
Short name T216
Test name
Test status
Simulation time 1579207218 ps
CPU time 30.86 seconds
Started Apr 04 12:45:55 PM PDT 24
Finished Apr 04 12:46:26 PM PDT 24
Peak memory 216068 kb
Host smart-b2e4bad8-391a-472a-905c-2736933265d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688483261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2688483261
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1177919725
Short name T641
Test name
Test status
Simulation time 235802310 ps
CPU time 7.11 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 218520 kb
Host smart-d78570b4-f2e1-4402-90da-ea6d2429542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177919725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1177919725
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3178578564
Short name T469
Test name
Test status
Simulation time 34257102 ps
CPU time 1.44 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:00 PM PDT 24
Peak memory 209824 kb
Host smart-0d02694a-33f0-4bbd-9034-d85054617915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178578564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3178578564
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3951826567
Short name T766
Test name
Test status
Simulation time 71822474 ps
CPU time 0.88 seconds
Started Apr 04 12:45:55 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 206224 kb
Host smart-8390c34b-bc1b-4e4b-a2c1-05ea6b029f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951826567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3951826567
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3624662876
Short name T593
Test name
Test status
Simulation time 93620368 ps
CPU time 1.55 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:54 PM PDT 24
Peak memory 209420 kb
Host smart-a15e7060-be03-4212-85a7-f44a9a744472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624662876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3624662876
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.742433570
Short name T376
Test name
Test status
Simulation time 316541365 ps
CPU time 6.61 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 209900 kb
Host smart-075164d6-a31c-4d97-9d81-270bc80aecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742433570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.742433570
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2303837462
Short name T271
Test name
Test status
Simulation time 592062365 ps
CPU time 7.19 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:09 PM PDT 24
Peak memory 214416 kb
Host smart-17f9a856-158e-42f5-ad42-897b6451655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303837462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2303837462
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2606368802
Short name T715
Test name
Test status
Simulation time 350299162 ps
CPU time 3.62 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 222736 kb
Host smart-1c1b373c-09f5-4e47-9b67-02674a825142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606368802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2606368802
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3018291658
Short name T711
Test name
Test status
Simulation time 181141588 ps
CPU time 7.57 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 214640 kb
Host smart-2db3251a-7f07-4ec1-a247-533435cbc6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018291658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3018291658
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2956961582
Short name T876
Test name
Test status
Simulation time 269609764 ps
CPU time 3 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 208804 kb
Host smart-afe90176-de81-442e-a8b1-b9db792e0e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956961582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2956961582
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.63034705
Short name T539
Test name
Test status
Simulation time 226919253 ps
CPU time 3.86 seconds
Started Apr 04 12:45:51 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 208484 kb
Host smart-ba8497f6-c02f-4fcb-baf5-839e071d9482
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63034705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.63034705
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.4092302927
Short name T858
Test name
Test status
Simulation time 43284535 ps
CPU time 1.78 seconds
Started Apr 04 12:45:57 PM PDT 24
Finished Apr 04 12:45:59 PM PDT 24
Peak memory 207072 kb
Host smart-ca5d7726-00a0-4131-bc08-09863f19ca42
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092302927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.4092302927
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2029464297
Short name T449
Test name
Test status
Simulation time 30015293 ps
CPU time 2.21 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:00 PM PDT 24
Peak memory 208456 kb
Host smart-aeae03e6-bc12-4cd9-a121-a133b916f948
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029464297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2029464297
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2339655895
Short name T199
Test name
Test status
Simulation time 4359231325 ps
CPU time 9.27 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:46:04 PM PDT 24
Peak memory 209992 kb
Host smart-754f1394-cdad-4824-991e-4ba32335c5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339655895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2339655895
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.426759607
Short name T570
Test name
Test status
Simulation time 50839484 ps
CPU time 2.42 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:00 PM PDT 24
Peak memory 206880 kb
Host smart-2efacb81-25b4-4311-a5cf-99ab159aa7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426759607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.426759607
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1358468715
Short name T694
Test name
Test status
Simulation time 491396737 ps
CPU time 7.95 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:46:02 PM PDT 24
Peak memory 210288 kb
Host smart-10894ac2-f83e-473c-af51-6d8c88c44082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358468715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1358468715
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4050058698
Short name T634
Test name
Test status
Simulation time 288424019 ps
CPU time 3.86 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 208348 kb
Host smart-208cfb8c-c8f5-4c82-9e9d-592126da96d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050058698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4050058698
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3977887434
Short name T817
Test name
Test status
Simulation time 64302270 ps
CPU time 2.65 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 210308 kb
Host smart-2d696eaa-232a-499a-9ab2-8bfb3ff7ea97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977887434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3977887434
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3045585561
Short name T2
Test name
Test status
Simulation time 14479381 ps
CPU time 0.83 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 206172 kb
Host smart-b70353d6-f502-4a55-9972-9096122e3ea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045585561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3045585561
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.571418538
Short name T417
Test name
Test status
Simulation time 47388706 ps
CPU time 3.43 seconds
Started Apr 04 12:45:47 PM PDT 24
Finished Apr 04 12:45:51 PM PDT 24
Peak memory 214536 kb
Host smart-38a130d9-dcfb-41e1-8067-4a09f7e73657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571418538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.571418538
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1713972365
Short name T29
Test name
Test status
Simulation time 33931996 ps
CPU time 1.55 seconds
Started Apr 04 12:45:52 PM PDT 24
Finished Apr 04 12:45:54 PM PDT 24
Peak memory 214580 kb
Host smart-c8475fc8-bc68-4192-83f8-b74c88fcd696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713972365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1713972365
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1180892622
Short name T381
Test name
Test status
Simulation time 52241385 ps
CPU time 2.35 seconds
Started Apr 04 12:45:53 PM PDT 24
Finished Apr 04 12:45:55 PM PDT 24
Peak memory 218636 kb
Host smart-d275eeb5-295a-4ede-928e-80703f41b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180892622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1180892622
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2082729447
Short name T97
Test name
Test status
Simulation time 123884844 ps
CPU time 5.06 seconds
Started Apr 04 12:45:49 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 214648 kb
Host smart-ec6c90bf-d12c-4dca-bfdc-630d68f01c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082729447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2082729447
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.19984810
Short name T673
Test name
Test status
Simulation time 74259581 ps
CPU time 3.67 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:01 PM PDT 24
Peak memory 222812 kb
Host smart-9123c8a6-625f-4ea2-9f91-5c0c15c78f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19984810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.19984810
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2365660844
Short name T312
Test name
Test status
Simulation time 3030892648 ps
CPU time 30.49 seconds
Started Apr 04 12:45:55 PM PDT 24
Finished Apr 04 12:46:26 PM PDT 24
Peak memory 218628 kb
Host smart-6ebad761-09cd-46d9-9584-428328803ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365660844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2365660844
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.762613154
Short name T396
Test name
Test status
Simulation time 399552678 ps
CPU time 2.72 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 207188 kb
Host smart-381ef151-bb8a-4ec9-aa6e-803912bd05a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762613154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.762613154
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3182547526
Short name T669
Test name
Test status
Simulation time 129375644 ps
CPU time 4.78 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:03 PM PDT 24
Peak memory 208204 kb
Host smart-d638b8e1-a89b-47e3-8fa0-a68db506706b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182547526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3182547526
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2892714271
Short name T768
Test name
Test status
Simulation time 493501992 ps
CPU time 3.95 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:56 PM PDT 24
Peak memory 209188 kb
Host smart-87ad2997-777a-4e9d-9d60-0a0ccff62f2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892714271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2892714271
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1095755027
Short name T369
Test name
Test status
Simulation time 426941552 ps
CPU time 2 seconds
Started Apr 04 12:45:50 PM PDT 24
Finished Apr 04 12:45:53 PM PDT 24
Peak memory 208764 kb
Host smart-9f2563d2-80f2-4846-97f5-ad72992046b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095755027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1095755027
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2007495640
Short name T416
Test name
Test status
Simulation time 136427365 ps
CPU time 3.04 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 209736 kb
Host smart-e104b3d6-85d2-4411-8580-9ea7b906de91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007495640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2007495640
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2829782471
Short name T786
Test name
Test status
Simulation time 1055068503 ps
CPU time 8.08 seconds
Started Apr 04 12:45:57 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 207024 kb
Host smart-c44f18e6-ca66-4cac-8512-1f06659052d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829782471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2829782471
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.92413172
Short name T742
Test name
Test status
Simulation time 19260791853 ps
CPU time 560.31 seconds
Started Apr 04 12:45:54 PM PDT 24
Finished Apr 04 12:55:15 PM PDT 24
Peak memory 222788 kb
Host smart-620977b9-22ab-4f8e-9d64-1febb9b2f446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92413172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.92413172
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.887134482
Short name T105
Test name
Test status
Simulation time 269739378 ps
CPU time 14.98 seconds
Started Apr 04 12:45:55 PM PDT 24
Finished Apr 04 12:46:10 PM PDT 24
Peak memory 221320 kb
Host smart-3577a6dd-6724-4bd6-8ffd-2442ca1fc46a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887134482 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.887134482
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3653527145
Short name T852
Test name
Test status
Simulation time 291888589 ps
CPU time 3.58 seconds
Started Apr 04 12:45:48 PM PDT 24
Finished Apr 04 12:45:53 PM PDT 24
Peak memory 210740 kb
Host smart-3f1eee64-10f0-4b80-aded-04f370a52465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653527145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3653527145
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3945244358
Short name T745
Test name
Test status
Simulation time 17647928 ps
CPU time 1 seconds
Started Apr 04 12:46:00 PM PDT 24
Finished Apr 04 12:46:01 PM PDT 24
Peak memory 206380 kb
Host smart-97c27699-a102-4815-883f-8d864bb61b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945244358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3945244358
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.683249020
Short name T872
Test name
Test status
Simulation time 70653447 ps
CPU time 2.15 seconds
Started Apr 04 12:45:59 PM PDT 24
Finished Apr 04 12:46:01 PM PDT 24
Peak memory 214836 kb
Host smart-0dae60db-3114-4c76-9c43-f416b6b6c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683249020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.683249020
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2900989159
Short name T890
Test name
Test status
Simulation time 120529294 ps
CPU time 2.02 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:00 PM PDT 24
Peak memory 214612 kb
Host smart-86d5854d-ed2c-4441-aa9c-d44468a48fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900989159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2900989159
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2145307886
Short name T712
Test name
Test status
Simulation time 42107945 ps
CPU time 2.82 seconds
Started Apr 04 12:46:01 PM PDT 24
Finished Apr 04 12:46:04 PM PDT 24
Peak memory 221944 kb
Host smart-f0a4c242-d5e4-4ed2-bf28-61a33450afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145307886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2145307886
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3356457003
Short name T249
Test name
Test status
Simulation time 249978915 ps
CPU time 3.69 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:09 PM PDT 24
Peak memory 211712 kb
Host smart-f3ff4ec4-2676-42f2-8350-ed3b013afdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356457003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3356457003
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2906460971
Short name T751
Test name
Test status
Simulation time 223356685 ps
CPU time 3.02 seconds
Started Apr 04 12:46:03 PM PDT 24
Finished Apr 04 12:46:06 PM PDT 24
Peak memory 218032 kb
Host smart-a3c49f09-a454-4137-950c-06cbc4688b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906460971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2906460971
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3039356913
Short name T867
Test name
Test status
Simulation time 48840244 ps
CPU time 2.84 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 214536 kb
Host smart-1082e2e1-a6ce-4d28-a23e-651833234fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039356913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3039356913
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.769435625
Short name T724
Test name
Test status
Simulation time 261159572 ps
CPU time 3.12 seconds
Started Apr 04 12:46:00 PM PDT 24
Finished Apr 04 12:46:04 PM PDT 24
Peak memory 208360 kb
Host smart-ff69dd07-20b4-4299-9873-8625af8d9841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769435625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.769435625
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1170534638
Short name T529
Test name
Test status
Simulation time 44178935 ps
CPU time 1.98 seconds
Started Apr 04 12:46:00 PM PDT 24
Finished Apr 04 12:46:02 PM PDT 24
Peak memory 207040 kb
Host smart-288eaf1a-709a-4ca0-90b1-4cce2cfd438f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170534638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1170534638
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3502493820
Short name T809
Test name
Test status
Simulation time 834293355 ps
CPU time 4.65 seconds
Started Apr 04 12:46:03 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 208832 kb
Host smart-6359129a-2216-4b9a-9bc7-99aa78e76cf7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502493820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3502493820
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1519491678
Short name T875
Test name
Test status
Simulation time 4614905657 ps
CPU time 27.5 seconds
Started Apr 04 12:46:01 PM PDT 24
Finished Apr 04 12:46:29 PM PDT 24
Peak memory 208184 kb
Host smart-12d1955f-edf4-4d1b-9205-8889db30b067
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519491678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1519491678
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3756866535
Short name T709
Test name
Test status
Simulation time 36929303 ps
CPU time 1.95 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:00 PM PDT 24
Peak memory 208476 kb
Host smart-ef1e05ac-95f3-4f1f-b0f2-f7bcd691a7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756866535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3756866535
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1918866239
Short name T778
Test name
Test status
Simulation time 102510757 ps
CPU time 3.06 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:01 PM PDT 24
Peak memory 207672 kb
Host smart-180b2f7f-6bd6-42e1-83a3-b23db3fc2ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918866239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1918866239
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3408559860
Short name T223
Test name
Test status
Simulation time 12324888864 ps
CPU time 209.92 seconds
Started Apr 04 12:46:03 PM PDT 24
Finished Apr 04 12:49:33 PM PDT 24
Peak memory 222632 kb
Host smart-3b3538d2-4fd6-4ea3-9941-51663127ea68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408559860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3408559860
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.277741662
Short name T463
Test name
Test status
Simulation time 860777580 ps
CPU time 17.68 seconds
Started Apr 04 12:45:55 PM PDT 24
Finished Apr 04 12:46:13 PM PDT 24
Peak memory 209404 kb
Host smart-ccfb7bc0-cfe2-4d8a-9f15-96131ffbcad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277741662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.277741662
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3091584646
Short name T857
Test name
Test status
Simulation time 67587092 ps
CPU time 2.79 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 210212 kb
Host smart-bb755783-2f9c-4d0c-b7f3-e99dca06b0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091584646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3091584646
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2864436123
Short name T543
Test name
Test status
Simulation time 24004352 ps
CPU time 0.75 seconds
Started Apr 04 12:46:01 PM PDT 24
Finished Apr 04 12:46:02 PM PDT 24
Peak memory 206204 kb
Host smart-c2d60906-aa06-4a50-a5ab-f3d232c025bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864436123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2864436123
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2206950264
Short name T176
Test name
Test status
Simulation time 64966581 ps
CPU time 4.27 seconds
Started Apr 04 12:46:01 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 214628 kb
Host smart-7dc49407-2c4d-48c7-b734-95dd3723b684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206950264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2206950264
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.59007632
Short name T674
Test name
Test status
Simulation time 75132643 ps
CPU time 3.25 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 218712 kb
Host smart-7cfde51d-33f2-412c-9b1a-8b2212d29d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59007632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.59007632
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3776336704
Short name T608
Test name
Test status
Simulation time 1684445836 ps
CPU time 30.23 seconds
Started Apr 04 12:46:00 PM PDT 24
Finished Apr 04 12:46:30 PM PDT 24
Peak memory 222792 kb
Host smart-485d789f-1efe-45b8-953a-9154b76b6ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776336704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3776336704
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1503221383
Short name T854
Test name
Test status
Simulation time 1771599526 ps
CPU time 10.25 seconds
Started Apr 04 12:45:58 PM PDT 24
Finished Apr 04 12:46:08 PM PDT 24
Peak memory 222756 kb
Host smart-9877ac6b-e45e-49ac-9338-9c7fdd71c563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503221383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1503221383
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2040120579
Short name T874
Test name
Test status
Simulation time 313263753 ps
CPU time 2.67 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 209068 kb
Host smart-166bf329-b4b2-40f3-8aa8-21103e86b085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040120579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2040120579
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1344703669
Short name T613
Test name
Test status
Simulation time 338791664 ps
CPU time 4.78 seconds
Started Apr 04 12:45:57 PM PDT 24
Finished Apr 04 12:46:02 PM PDT 24
Peak memory 209116 kb
Host smart-2da00a0c-aad3-4da4-a854-83cda053978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344703669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1344703669
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2223014962
Short name T190
Test name
Test status
Simulation time 453740600 ps
CPU time 4.32 seconds
Started Apr 04 12:46:04 PM PDT 24
Finished Apr 04 12:46:08 PM PDT 24
Peak memory 208536 kb
Host smart-e8046dfa-b9f8-499d-9df7-8e308017cc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223014962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2223014962
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3312573278
Short name T907
Test name
Test status
Simulation time 60452290 ps
CPU time 2.17 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:08 PM PDT 24
Peak memory 207140 kb
Host smart-9e9de27f-a42c-4225-a457-6acf68a1a174
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312573278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3312573278
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4255755379
Short name T604
Test name
Test status
Simulation time 208505060 ps
CPU time 3.01 seconds
Started Apr 04 12:46:04 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 207568 kb
Host smart-01cffc61-1ff4-40e1-880a-ef77ae2c9ed1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255755379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4255755379
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1911041076
Short name T888
Test name
Test status
Simulation time 7504312933 ps
CPU time 80.31 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:47:31 PM PDT 24
Peak memory 208888 kb
Host smart-3191fc16-cadb-4f93-a098-d011caf81cd6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911041076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1911041076
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2453093866
Short name T719
Test name
Test status
Simulation time 102657751 ps
CPU time 4.45 seconds
Started Apr 04 12:46:04 PM PDT 24
Finished Apr 04 12:46:08 PM PDT 24
Peak memory 210636 kb
Host smart-eefcca6a-a90f-472c-a80c-35ac049b2822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453093866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2453093866
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3529584014
Short name T701
Test name
Test status
Simulation time 104641965 ps
CPU time 2 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:04 PM PDT 24
Peak memory 208628 kb
Host smart-69ea2d5f-931f-4145-a2fd-cf9baa03dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529584014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3529584014
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.162990322
Short name T182
Test name
Test status
Simulation time 343826859 ps
CPU time 6.5 seconds
Started Apr 04 12:46:03 PM PDT 24
Finished Apr 04 12:46:10 PM PDT 24
Peak memory 208916 kb
Host smart-9093c911-f0e1-4316-849b-dd79fb18d40a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162990322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.162990322
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3011339447
Short name T118
Test name
Test status
Simulation time 150800920 ps
CPU time 4.43 seconds
Started Apr 04 12:46:04 PM PDT 24
Finished Apr 04 12:46:08 PM PDT 24
Peak memory 220064 kb
Host smart-976fd7cc-6afa-4e48-ad18-5490587c761e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011339447 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3011339447
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.921167901
Short name T757
Test name
Test status
Simulation time 183698770 ps
CPU time 8.1 seconds
Started Apr 04 12:45:59 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 210048 kb
Host smart-885acec9-2102-4f38-8fa6-9682ca04eb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921167901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.921167901
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1537767605
Short name T125
Test name
Test status
Simulation time 118343080 ps
CPU time 1.86 seconds
Started Apr 04 12:46:04 PM PDT 24
Finished Apr 04 12:46:06 PM PDT 24
Peak memory 209804 kb
Host smart-f828428b-c65e-4c4a-bd67-3258927a24ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537767605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1537767605
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4035990544
Short name T648
Test name
Test status
Simulation time 21764149 ps
CPU time 0.74 seconds
Started Apr 04 12:45:10 PM PDT 24
Finished Apr 04 12:45:11 PM PDT 24
Peak memory 206164 kb
Host smart-8ba082aa-b366-4ad4-9227-9dc7fd280eae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035990544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4035990544
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.349740121
Short name T252
Test name
Test status
Simulation time 70125110 ps
CPU time 4.97 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:45:17 PM PDT 24
Peak memory 215708 kb
Host smart-48804dd7-770a-4719-93fa-1f46a22db8af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349740121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.349740121
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1193629553
Short name T515
Test name
Test status
Simulation time 340251584 ps
CPU time 9.32 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:45:22 PM PDT 24
Peak memory 209908 kb
Host smart-918a237e-af4f-4acc-b685-9b54d14499e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193629553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1193629553
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1216551089
Short name T769
Test name
Test status
Simulation time 119678121 ps
CPU time 2.43 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:45:15 PM PDT 24
Peak memory 214656 kb
Host smart-9f051546-f580-4d85-bd67-2d25de032527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216551089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1216551089
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3887090768
Short name T582
Test name
Test status
Simulation time 134776381 ps
CPU time 4.12 seconds
Started Apr 04 12:45:11 PM PDT 24
Finished Apr 04 12:45:15 PM PDT 24
Peak memory 209656 kb
Host smart-7a2d3b86-e296-4358-a1a5-e8fdda7a6c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887090768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3887090768
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1441201427
Short name T713
Test name
Test status
Simulation time 322497332 ps
CPU time 11.72 seconds
Started Apr 04 12:45:15 PM PDT 24
Finished Apr 04 12:45:28 PM PDT 24
Peak memory 210236 kb
Host smart-3e108c3e-b500-473e-8195-ff758534642b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441201427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1441201427
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2762699834
Short name T226
Test name
Test status
Simulation time 391887707 ps
CPU time 3.46 seconds
Started Apr 04 12:45:09 PM PDT 24
Finished Apr 04 12:45:13 PM PDT 24
Peak memory 222784 kb
Host smart-6cb39d87-9aa6-4912-afaf-d2fc9e2e079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762699834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2762699834
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3855347314
Short name T197
Test name
Test status
Simulation time 254629924 ps
CPU time 5.28 seconds
Started Apr 04 12:45:14 PM PDT 24
Finished Apr 04 12:45:20 PM PDT 24
Peak memory 210020 kb
Host smart-5c56d3c2-4f90-417d-9594-e70e510cdb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855347314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3855347314
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1421258692
Short name T7
Test name
Test status
Simulation time 17385146707 ps
CPU time 541.85 seconds
Started Apr 04 12:45:26 PM PDT 24
Finished Apr 04 12:54:28 PM PDT 24
Peak memory 377004 kb
Host smart-e9050519-7640-4acf-ade6-9b31437baf5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421258692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1421258692
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.685061132
Short name T313
Test name
Test status
Simulation time 2472810108 ps
CPU time 30.7 seconds
Started Apr 04 12:45:02 PM PDT 24
Finished Apr 04 12:45:32 PM PDT 24
Peak memory 208140 kb
Host smart-609d9971-fd79-44fb-ab5b-40f41bde6d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685061132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.685061132
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.671564794
Short name T281
Test name
Test status
Simulation time 116352327 ps
CPU time 4.68 seconds
Started Apr 04 12:45:07 PM PDT 24
Finished Apr 04 12:45:11 PM PDT 24
Peak memory 207156 kb
Host smart-dc7bd46c-0f00-4620-8fe8-0c3d1dc92f31
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671564794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.671564794
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4271323132
Short name T597
Test name
Test status
Simulation time 4180713020 ps
CPU time 76.98 seconds
Started Apr 04 12:45:07 PM PDT 24
Finished Apr 04 12:46:24 PM PDT 24
Peak memory 208812 kb
Host smart-69f40456-2028-4983-80f3-6b679f9e95e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271323132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4271323132
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3991541108
Short name T553
Test name
Test status
Simulation time 395630446 ps
CPU time 6.53 seconds
Started Apr 04 12:45:17 PM PDT 24
Finished Apr 04 12:45:24 PM PDT 24
Peak memory 207136 kb
Host smart-8fae76af-d797-40e2-acf9-e83b96027cab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991541108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3991541108
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2364705292
Short name T277
Test name
Test status
Simulation time 132284480 ps
CPU time 2.05 seconds
Started Apr 04 12:45:28 PM PDT 24
Finished Apr 04 12:45:30 PM PDT 24
Peak memory 209716 kb
Host smart-84522dbf-3ec0-4d63-a9b7-98075a6e781d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364705292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2364705292
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.84778824
Short name T397
Test name
Test status
Simulation time 1831942241 ps
CPU time 17.18 seconds
Started Apr 04 12:45:05 PM PDT 24
Finished Apr 04 12:45:22 PM PDT 24
Peak memory 208140 kb
Host smart-76640b4f-aff3-40e9-b996-50d7a64d7284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84778824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.84778824
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1545510331
Short name T296
Test name
Test status
Simulation time 508825247 ps
CPU time 10 seconds
Started Apr 04 12:45:14 PM PDT 24
Finished Apr 04 12:45:25 PM PDT 24
Peak memory 214496 kb
Host smart-4eb0fbf2-d790-44a2-b2b1-baee45b04e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545510331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1545510331
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2969460925
Short name T391
Test name
Test status
Simulation time 86991987 ps
CPU time 2.5 seconds
Started Apr 04 12:46:32 PM PDT 24
Finished Apr 04 12:46:34 PM PDT 24
Peak memory 210276 kb
Host smart-bdbb457c-076d-4c1b-9a05-f61a3e42d1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969460925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2969460925
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2647132582
Short name T859
Test name
Test status
Simulation time 10461034 ps
CPU time 0.7 seconds
Started Apr 04 12:46:10 PM PDT 24
Finished Apr 04 12:46:11 PM PDT 24
Peak memory 206144 kb
Host smart-f8c49ec1-ae1f-43ea-a042-1259c7e5d12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647132582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2647132582
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4061021078
Short name T837
Test name
Test status
Simulation time 43051618 ps
CPU time 2.14 seconds
Started Apr 04 12:46:00 PM PDT 24
Finished Apr 04 12:46:02 PM PDT 24
Peak memory 208744 kb
Host smart-08c1ef7f-e0ba-484e-9f7b-2b5285422331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061021078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4061021078
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3612664942
Short name T394
Test name
Test status
Simulation time 222049370 ps
CPU time 3.95 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:06 PM PDT 24
Peak memory 214700 kb
Host smart-447ae227-7822-47cd-b651-5d6023d24e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612664942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3612664942
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_random.1177653421
Short name T729
Test name
Test status
Simulation time 105326566 ps
CPU time 4.86 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 209184 kb
Host smart-7a72ff23-4b7c-4536-8bd7-0df78e20538b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177653421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1177653421
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1070500309
Short name T812
Test name
Test status
Simulation time 438643342 ps
CPU time 5.35 seconds
Started Apr 04 12:46:06 PM PDT 24
Finished Apr 04 12:46:11 PM PDT 24
Peak memory 207168 kb
Host smart-7f3deed3-5dfb-4b76-b0e5-529ae7c184fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070500309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1070500309
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3868114635
Short name T511
Test name
Test status
Simulation time 54140942 ps
CPU time 2.73 seconds
Started Apr 04 12:46:04 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 207052 kb
Host smart-e999a90e-6cf7-48fa-bfdf-4c957e0c17fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868114635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3868114635
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.737742645
Short name T884
Test name
Test status
Simulation time 1165178496 ps
CPU time 6.78 seconds
Started Apr 04 12:46:00 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 208460 kb
Host smart-47f4e00e-07f4-4164-a63d-3c550e2be1ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737742645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.737742645
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2760797940
Short name T656
Test name
Test status
Simulation time 21501988 ps
CPU time 1.91 seconds
Started Apr 04 12:46:03 PM PDT 24
Finished Apr 04 12:46:05 PM PDT 24
Peak memory 206944 kb
Host smart-92dc5f79-38b3-48ac-8846-0486beafcc1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760797940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2760797940
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3930945322
Short name T601
Test name
Test status
Simulation time 227225066 ps
CPU time 2.78 seconds
Started Apr 04 12:46:01 PM PDT 24
Finished Apr 04 12:46:04 PM PDT 24
Peak memory 209504 kb
Host smart-27b8c268-3175-491b-961d-1d2a3f30b62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930945322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3930945322
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3177819170
Short name T447
Test name
Test status
Simulation time 1924078557 ps
CPU time 41.36 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:44 PM PDT 24
Peak memory 208048 kb
Host smart-91e40c4e-1d17-40ab-970e-a9206b45b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177819170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3177819170
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2126881183
Short name T510
Test name
Test status
Simulation time 167481583 ps
CPU time 7.33 seconds
Started Apr 04 12:46:02 PM PDT 24
Finished Apr 04 12:46:10 PM PDT 24
Peak memory 214608 kb
Host smart-07e0cb12-db00-489c-b293-3d426ba42191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126881183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2126881183
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1534419814
Short name T717
Test name
Test status
Simulation time 269210589 ps
CPU time 16.78 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:30 PM PDT 24
Peak memory 222956 kb
Host smart-4c6b20ed-d3c3-4dc2-8d95-c2b6fe4141e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534419814 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1534419814
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1620648732
Short name T59
Test name
Test status
Simulation time 763767622 ps
CPU time 7.64 seconds
Started Apr 04 12:46:03 PM PDT 24
Finished Apr 04 12:46:11 PM PDT 24
Peak memory 210712 kb
Host smart-1a604622-6125-41c0-9fad-022f3754dc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620648732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1620648732
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3043722348
Short name T805
Test name
Test status
Simulation time 86273367 ps
CPU time 0.88 seconds
Started Apr 04 12:46:07 PM PDT 24
Finished Apr 04 12:46:08 PM PDT 24
Peak memory 206204 kb
Host smart-a8339b06-6f6e-4308-9ae8-1616da1c72d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043722348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3043722348
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1398137061
Short name T385
Test name
Test status
Simulation time 1057867779 ps
CPU time 56.66 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:47:02 PM PDT 24
Peak memory 214652 kb
Host smart-ec9dbadd-95b6-4189-8513-a0d2b65e2fa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398137061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1398137061
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3519795161
Short name T58
Test name
Test status
Simulation time 320321420 ps
CPU time 5.19 seconds
Started Apr 04 12:46:09 PM PDT 24
Finished Apr 04 12:46:14 PM PDT 24
Peak memory 214524 kb
Host smart-48187ea5-968b-4b06-a9d4-d8d2879ad163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519795161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3519795161
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.599464740
Short name T274
Test name
Test status
Simulation time 612826198 ps
CPU time 5.73 seconds
Started Apr 04 12:46:08 PM PDT 24
Finished Apr 04 12:46:14 PM PDT 24
Peak memory 214636 kb
Host smart-7b82de3a-1056-4031-8695-208a0e64fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599464740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.599464740
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.813568125
Short name T814
Test name
Test status
Simulation time 153148665 ps
CPU time 6.57 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:12 PM PDT 24
Peak memory 221756 kb
Host smart-e1f0b7ad-b699-4297-a3e5-b1f108d53b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813568125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.813568125
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.1425436723
Short name T707
Test name
Test status
Simulation time 288137186 ps
CPU time 4.11 seconds
Started Apr 04 12:46:10 PM PDT 24
Finished Apr 04 12:46:15 PM PDT 24
Peak memory 218772 kb
Host smart-fd2ff630-a293-46c6-b974-a98054d80aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425436723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1425436723
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.832303248
Short name T803
Test name
Test status
Simulation time 89893338 ps
CPU time 2.54 seconds
Started Apr 04 12:46:10 PM PDT 24
Finished Apr 04 12:46:13 PM PDT 24
Peak memory 207004 kb
Host smart-59933811-749b-4908-a00f-94477f22a968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832303248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.832303248
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1515530
Short name T506
Test name
Test status
Simulation time 1540729716 ps
CPU time 5.06 seconds
Started Apr 04 12:46:04 PM PDT 24
Finished Apr 04 12:46:09 PM PDT 24
Peak memory 207084 kb
Host smart-e0d491b4-2108-4b66-a507-3e3e8f1bd884
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1515530
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2537342668
Short name T868
Test name
Test status
Simulation time 94868847 ps
CPU time 2.84 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:08 PM PDT 24
Peak memory 207252 kb
Host smart-c445a570-8ffe-4956-8aee-21331d78f31a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537342668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2537342668
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3133011322
Short name T455
Test name
Test status
Simulation time 1886417127 ps
CPU time 36.73 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:42 PM PDT 24
Peak memory 209056 kb
Host smart-20ec2a77-7525-4872-988f-722af20f0289
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133011322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3133011322
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1604954230
Short name T659
Test name
Test status
Simulation time 101164315 ps
CPU time 2.91 seconds
Started Apr 04 12:46:23 PM PDT 24
Finished Apr 04 12:46:26 PM PDT 24
Peak memory 215984 kb
Host smart-f46b8737-784a-41a2-9427-29318b0282ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604954230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1604954230
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1128818403
Short name T772
Test name
Test status
Simulation time 205124191 ps
CPU time 6.43 seconds
Started Apr 04 12:46:07 PM PDT 24
Finished Apr 04 12:46:14 PM PDT 24
Peak memory 207072 kb
Host smart-edb4a32f-e19e-4762-964e-3d6fd076ff18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128818403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1128818403
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.164713281
Short name T725
Test name
Test status
Simulation time 283914108 ps
CPU time 3.91 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:17 PM PDT 24
Peak memory 208900 kb
Host smart-c9ea722c-fcc2-41a2-b0dd-e969288f8091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164713281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.164713281
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3371064541
Short name T383
Test name
Test status
Simulation time 450948688 ps
CPU time 9.37 seconds
Started Apr 04 12:46:06 PM PDT 24
Finished Apr 04 12:46:16 PM PDT 24
Peak memory 208472 kb
Host smart-9e15faee-413a-4072-bd98-b863c6b6afc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371064541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3371064541
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2706668204
Short name T121
Test name
Test status
Simulation time 1051294776 ps
CPU time 9.88 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:15 PM PDT 24
Peak memory 211012 kb
Host smart-6760d465-8aa6-438a-ba87-96253415a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706668204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2706668204
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.984510746
Short name T84
Test name
Test status
Simulation time 31904480 ps
CPU time 0.84 seconds
Started Apr 04 12:46:09 PM PDT 24
Finished Apr 04 12:46:10 PM PDT 24
Peak memory 206280 kb
Host smart-184d0dd4-e88d-4929-b088-9c5fd624f765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984510746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.984510746
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3411059822
Short name T840
Test name
Test status
Simulation time 23622781 ps
CPU time 1.99 seconds
Started Apr 04 12:46:12 PM PDT 24
Finished Apr 04 12:46:14 PM PDT 24
Peak memory 214500 kb
Host smart-10f410d2-09ce-4405-831b-2a00ef466e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411059822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3411059822
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1786186200
Short name T19
Test name
Test status
Simulation time 53680423 ps
CPU time 1.73 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 216572 kb
Host smart-584cdcb3-54db-42f5-b083-9cf5089c3ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786186200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1786186200
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3930831834
Short name T879
Test name
Test status
Simulation time 134450374 ps
CPU time 2.37 seconds
Started Apr 04 12:46:07 PM PDT 24
Finished Apr 04 12:46:09 PM PDT 24
Peak memory 214556 kb
Host smart-780e6410-f172-40d4-8019-14cfc1e2c553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930831834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3930831834
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.300322691
Short name T635
Test name
Test status
Simulation time 425585150 ps
CPU time 4.72 seconds
Started Apr 04 12:46:10 PM PDT 24
Finished Apr 04 12:46:15 PM PDT 24
Peak memory 214420 kb
Host smart-e7dfa771-ae4e-462e-9c61-719b2124990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300322691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.300322691
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1699685184
Short name T382
Test name
Test status
Simulation time 281652906 ps
CPU time 6.88 seconds
Started Apr 04 12:46:09 PM PDT 24
Finished Apr 04 12:46:16 PM PDT 24
Peak memory 210576 kb
Host smart-fdae999f-2900-4cfb-87f8-0dcbf2f1504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699685184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1699685184
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_random.3393368880
Short name T899
Test name
Test status
Simulation time 245121625 ps
CPU time 5.4 seconds
Started Apr 04 12:46:11 PM PDT 24
Finished Apr 04 12:46:17 PM PDT 24
Peak memory 210684 kb
Host smart-c6aabc34-72f2-4ad2-87bf-7420f59c5ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393368880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3393368880
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1567852128
Short name T855
Test name
Test status
Simulation time 129735986 ps
CPU time 4.23 seconds
Started Apr 04 12:46:14 PM PDT 24
Finished Apr 04 12:46:19 PM PDT 24
Peak memory 206836 kb
Host smart-bd48f6cd-2d33-43d3-8970-a191296a0d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567852128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1567852128
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3347404446
Short name T841
Test name
Test status
Simulation time 884451006 ps
CPU time 2.91 seconds
Started Apr 04 12:46:08 PM PDT 24
Finished Apr 04 12:46:11 PM PDT 24
Peak memory 209004 kb
Host smart-362847fc-b9cd-431b-9115-cc060e182887
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347404446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3347404446
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.454465935
Short name T512
Test name
Test status
Simulation time 508696585 ps
CPU time 6 seconds
Started Apr 04 12:46:07 PM PDT 24
Finished Apr 04 12:46:13 PM PDT 24
Peak memory 208224 kb
Host smart-4097207b-cccf-4f39-9db9-f1ff5c54975c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454465935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.454465935
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3687203637
Short name T844
Test name
Test status
Simulation time 266591166 ps
CPU time 6.9 seconds
Started Apr 04 12:46:07 PM PDT 24
Finished Apr 04 12:46:14 PM PDT 24
Peak memory 208352 kb
Host smart-7610e9d3-0247-48a4-9bf6-4ce6cec1aba1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687203637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3687203637
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2097537
Short name T834
Test name
Test status
Simulation time 194080756 ps
CPU time 3.69 seconds
Started Apr 04 12:46:07 PM PDT 24
Finished Apr 04 12:46:11 PM PDT 24
Peak memory 208980 kb
Host smart-803b3a6e-698a-40fa-95cd-e1cae974c70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2097537
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2770853767
Short name T625
Test name
Test status
Simulation time 73556032 ps
CPU time 3.35 seconds
Started Apr 04 12:46:06 PM PDT 24
Finished Apr 04 12:46:10 PM PDT 24
Peak memory 208600 kb
Host smart-977ae9c2-c16e-4b7d-8f05-39e2075e30c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770853767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2770853767
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1902018911
Short name T415
Test name
Test status
Simulation time 495058891 ps
CPU time 7.01 seconds
Started Apr 04 12:46:14 PM PDT 24
Finished Apr 04 12:46:21 PM PDT 24
Peak memory 215620 kb
Host smart-24cf74d6-7571-4b76-8d18-7a287f280eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902018911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1902018911
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.412762600
Short name T227
Test name
Test status
Simulation time 1778027367 ps
CPU time 8.39 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:21 PM PDT 24
Peak memory 219956 kb
Host smart-bc89e91b-ff2e-4d34-a18f-9ed718b54ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412762600 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.412762600
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2138834837
Short name T324
Test name
Test status
Simulation time 183668662 ps
CPU time 2.95 seconds
Started Apr 04 12:46:09 PM PDT 24
Finished Apr 04 12:46:12 PM PDT 24
Peak memory 214528 kb
Host smart-7b0cee66-7fbb-4337-86e4-af3fe9485005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138834837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2138834837
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3849438593
Short name T35
Test name
Test status
Simulation time 110746910 ps
CPU time 3.38 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:08 PM PDT 24
Peak memory 210584 kb
Host smart-2b5df4ad-b217-4239-8468-ef26c46c2426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849438593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3849438593
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3286535326
Short name T442
Test name
Test status
Simulation time 19487986 ps
CPU time 0.79 seconds
Started Apr 04 12:46:12 PM PDT 24
Finished Apr 04 12:46:13 PM PDT 24
Peak memory 206276 kb
Host smart-638109f8-cc6a-4cb9-b3db-5344e97b3183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286535326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3286535326
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2545718403
Short name T804
Test name
Test status
Simulation time 76658120 ps
CPU time 2.65 seconds
Started Apr 04 12:46:23 PM PDT 24
Finished Apr 04 12:46:26 PM PDT 24
Peak memory 215308 kb
Host smart-0b4a01ac-d809-4fe9-a14d-6b0aea88fa76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545718403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2545718403
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1829634939
Short name T555
Test name
Test status
Simulation time 70862931 ps
CPU time 2.54 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:16 PM PDT 24
Peak memory 208484 kb
Host smart-cee7f0e6-5f85-4298-aa0e-e7f4acc56786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829634939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1829634939
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4142811412
Short name T393
Test name
Test status
Simulation time 377815067 ps
CPU time 4.03 seconds
Started Apr 04 12:46:08 PM PDT 24
Finished Apr 04 12:46:13 PM PDT 24
Peak memory 220248 kb
Host smart-20bbbaec-06c5-4069-9db8-f02dd2031258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142811412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4142811412
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3908552726
Short name T36
Test name
Test status
Simulation time 182049952 ps
CPU time 6.87 seconds
Started Apr 04 12:46:14 PM PDT 24
Finished Apr 04 12:46:21 PM PDT 24
Peak memory 214528 kb
Host smart-42ae8d7c-6bca-45a7-b621-ccc1401212de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908552726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3908552726
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.711259280
Short name T692
Test name
Test status
Simulation time 135057258 ps
CPU time 3.5 seconds
Started Apr 04 12:46:10 PM PDT 24
Finished Apr 04 12:46:14 PM PDT 24
Peak memory 214428 kb
Host smart-d41b565e-98a8-4bbd-ae66-9ddc478e70ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711259280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.711259280
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.4109056225
Short name T286
Test name
Test status
Simulation time 72768309 ps
CPU time 3.92 seconds
Started Apr 04 12:46:10 PM PDT 24
Finished Apr 04 12:46:14 PM PDT 24
Peak memory 207532 kb
Host smart-064785a7-75d1-445b-8735-e72d41465ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109056225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4109056225
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3514659659
Short name T802
Test name
Test status
Simulation time 784188496 ps
CPU time 6.12 seconds
Started Apr 04 12:46:06 PM PDT 24
Finished Apr 04 12:46:13 PM PDT 24
Peak memory 207060 kb
Host smart-7876d2d5-2077-450f-bd79-6ffebf7e83d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514659659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3514659659
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4067928663
Short name T851
Test name
Test status
Simulation time 100646258 ps
CPU time 3.46 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:17 PM PDT 24
Peak memory 208760 kb
Host smart-9bd1739f-4a6b-45e7-b51b-c6b264b6b197
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067928663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4067928663
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1458146710
Short name T767
Test name
Test status
Simulation time 130589042 ps
CPU time 3.99 seconds
Started Apr 04 12:46:08 PM PDT 24
Finished Apr 04 12:46:12 PM PDT 24
Peak memory 207048 kb
Host smart-0a1dae49-b996-44a3-b68b-2bddf118c99a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458146710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1458146710
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.594278516
Short name T297
Test name
Test status
Simulation time 160949814 ps
CPU time 2.42 seconds
Started Apr 04 12:46:11 PM PDT 24
Finished Apr 04 12:46:13 PM PDT 24
Peak memory 210032 kb
Host smart-9f452a26-a8e0-465f-84ea-158cf934b3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594278516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.594278516
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1367919194
Short name T451
Test name
Test status
Simulation time 136922789 ps
CPU time 2.52 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:08 PM PDT 24
Peak memory 206928 kb
Host smart-69edea9f-5437-498a-8a47-09cfd5c7e275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367919194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1367919194
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.621992641
Short name T256
Test name
Test status
Simulation time 310170176 ps
CPU time 10.13 seconds
Started Apr 04 12:46:18 PM PDT 24
Finished Apr 04 12:46:28 PM PDT 24
Peak memory 222852 kb
Host smart-f21138bd-d078-4884-a786-f25154ceb061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621992641 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.621992641
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4195704644
Short name T198
Test name
Test status
Simulation time 141832596 ps
CPU time 2.77 seconds
Started Apr 04 12:46:06 PM PDT 24
Finished Apr 04 12:46:09 PM PDT 24
Peak memory 207632 kb
Host smart-442edf28-11ed-4eaa-be3f-7b7ae4e9404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195704644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4195704644
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3785825343
Short name T783
Test name
Test status
Simulation time 44887313 ps
CPU time 1.82 seconds
Started Apr 04 12:46:05 PM PDT 24
Finished Apr 04 12:46:07 PM PDT 24
Peak memory 210548 kb
Host smart-edc02f38-e722-428f-ac9a-1720e53aad91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785825343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3785825343
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3588342161
Short name T760
Test name
Test status
Simulation time 11272488 ps
CPU time 0.85 seconds
Started Apr 04 12:46:20 PM PDT 24
Finished Apr 04 12:46:21 PM PDT 24
Peak memory 206300 kb
Host smart-66ffb1ae-4ea3-4773-8119-11b645d634a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588342161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3588342161
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1074987001
Short name T362
Test name
Test status
Simulation time 192694222 ps
CPU time 3.21 seconds
Started Apr 04 12:46:21 PM PDT 24
Finished Apr 04 12:46:24 PM PDT 24
Peak memory 215736 kb
Host smart-2d745640-48db-464d-96f7-a560b13bfa99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074987001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1074987001
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2071996466
Short name T71
Test name
Test status
Simulation time 1971797164 ps
CPU time 3.49 seconds
Started Apr 04 12:46:23 PM PDT 24
Finished Apr 04 12:46:27 PM PDT 24
Peak memory 218456 kb
Host smart-311210ab-641e-452c-a0a9-ddfaca51b764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071996466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2071996466
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1728915518
Short name T619
Test name
Test status
Simulation time 1281985909 ps
CPU time 9.49 seconds
Started Apr 04 12:46:17 PM PDT 24
Finished Apr 04 12:46:26 PM PDT 24
Peak memory 214588 kb
Host smart-2c444316-4563-4cda-bafc-0c8e0f36bbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728915518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1728915518
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.894697621
Short name T595
Test name
Test status
Simulation time 303983225 ps
CPU time 3.13 seconds
Started Apr 04 12:46:15 PM PDT 24
Finished Apr 04 12:46:18 PM PDT 24
Peak memory 214636 kb
Host smart-a21aa773-63c8-4306-bc9d-109aee0764e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894697621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.894697621
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1259683610
Short name T518
Test name
Test status
Simulation time 79813696 ps
CPU time 4.28 seconds
Started Apr 04 12:46:12 PM PDT 24
Finished Apr 04 12:46:16 PM PDT 24
Peak memory 209260 kb
Host smart-b3205486-90ca-4dd6-bd9b-6164d8cf9f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259683610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1259683610
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.784305427
Short name T649
Test name
Test status
Simulation time 536716745 ps
CPU time 4.57 seconds
Started Apr 04 12:46:21 PM PDT 24
Finished Apr 04 12:46:25 PM PDT 24
Peak memory 207644 kb
Host smart-ed23e87b-d095-4624-8eea-3317075bc7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784305427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.784305427
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2387181216
Short name T480
Test name
Test status
Simulation time 212171932 ps
CPU time 7.9 seconds
Started Apr 04 12:46:23 PM PDT 24
Finished Apr 04 12:46:31 PM PDT 24
Peak memory 208240 kb
Host smart-c7e85ad3-c2f9-4fe3-b48a-220dec072a3f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387181216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2387181216
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.101653855
Short name T684
Test name
Test status
Simulation time 73850761 ps
CPU time 2.41 seconds
Started Apr 04 12:46:15 PM PDT 24
Finished Apr 04 12:46:18 PM PDT 24
Peak memory 207176 kb
Host smart-909d7c1c-d173-481e-8086-75387835b07f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101653855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.101653855
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3925562600
Short name T794
Test name
Test status
Simulation time 112333313 ps
CPU time 4.82 seconds
Started Apr 04 12:46:18 PM PDT 24
Finished Apr 04 12:46:23 PM PDT 24
Peak memory 207056 kb
Host smart-a229ad7a-e263-4576-a2e4-13d88eeaaaac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925562600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3925562600
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2905066304
Short name T465
Test name
Test status
Simulation time 692650510 ps
CPU time 2.69 seconds
Started Apr 04 12:46:25 PM PDT 24
Finished Apr 04 12:46:28 PM PDT 24
Peak memory 209924 kb
Host smart-25236be7-fdfa-4288-aae8-b0f9ef103d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905066304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2905066304
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1669995120
Short name T439
Test name
Test status
Simulation time 40125799 ps
CPU time 2.46 seconds
Started Apr 04 12:46:09 PM PDT 24
Finished Apr 04 12:46:11 PM PDT 24
Peak memory 207000 kb
Host smart-22261217-2f79-4acc-b778-ce155558bd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669995120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1669995120
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.160615632
Short name T473
Test name
Test status
Simulation time 3885813800 ps
CPU time 14.66 seconds
Started Apr 04 12:46:22 PM PDT 24
Finished Apr 04 12:46:37 PM PDT 24
Peak memory 208464 kb
Host smart-3cf33572-dcad-418b-90ef-c3e1c4290c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160615632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.160615632
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.438302749
Short name T287
Test name
Test status
Simulation time 1206419670 ps
CPU time 34.06 seconds
Started Apr 04 12:46:23 PM PDT 24
Finished Apr 04 12:46:57 PM PDT 24
Peak memory 208508 kb
Host smart-74070aa2-8fe4-4bb2-a0f7-3ae4d8e5179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438302749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.438302749
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3271467093
Short name T50
Test name
Test status
Simulation time 218671336 ps
CPU time 2.63 seconds
Started Apr 04 12:46:15 PM PDT 24
Finished Apr 04 12:46:18 PM PDT 24
Peak memory 210224 kb
Host smart-3e6adb9d-d344-4f0f-b8fc-76fcf9ef7259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271467093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3271467093
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3984038881
Short name T429
Test name
Test status
Simulation time 53471623 ps
CPU time 0.74 seconds
Started Apr 04 12:46:16 PM PDT 24
Finished Apr 04 12:46:17 PM PDT 24
Peak memory 206252 kb
Host smart-29c8306d-650e-4bcc-ad02-29a219c4c7f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984038881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3984038881
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1574784548
Short name T387
Test name
Test status
Simulation time 82065837 ps
CPU time 3.78 seconds
Started Apr 04 12:46:26 PM PDT 24
Finished Apr 04 12:46:30 PM PDT 24
Peak memory 222068 kb
Host smart-a737167a-ef48-4836-8631-2c0a7a8b77fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574784548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1574784548
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2188898135
Short name T700
Test name
Test status
Simulation time 955431248 ps
CPU time 27.4 seconds
Started Apr 04 12:46:15 PM PDT 24
Finished Apr 04 12:46:42 PM PDT 24
Peak memory 209860 kb
Host smart-1cade9f6-dda8-4977-9b14-76ff9a129cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188898135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2188898135
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.617303877
Short name T509
Test name
Test status
Simulation time 2098050964 ps
CPU time 6.51 seconds
Started Apr 04 12:46:21 PM PDT 24
Finished Apr 04 12:46:27 PM PDT 24
Peak memory 209476 kb
Host smart-8c149b55-791d-4e75-98da-c52b684e7e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617303877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.617303877
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.4217354730
Short name T270
Test name
Test status
Simulation time 42872076 ps
CPU time 2.73 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:15 PM PDT 24
Peak memory 209620 kb
Host smart-0d0c1002-c252-458a-81d3-c9e50456651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217354730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.4217354730
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3920402529
Short name T48
Test name
Test status
Simulation time 159889236 ps
CPU time 2.74 seconds
Started Apr 04 12:46:14 PM PDT 24
Finished Apr 04 12:46:17 PM PDT 24
Peak memory 220088 kb
Host smart-d54b6773-daa1-45ac-9ee8-66d5ea6851a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920402529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3920402529
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1598827820
Short name T384
Test name
Test status
Simulation time 4125241565 ps
CPU time 27.3 seconds
Started Apr 04 12:46:25 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 208376 kb
Host smart-4eeb8b2f-571a-4ab8-918f-112d2d0302e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598827820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1598827820
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2118284976
Short name T347
Test name
Test status
Simulation time 31506976 ps
CPU time 2.42 seconds
Started Apr 04 12:46:14 PM PDT 24
Finished Apr 04 12:46:16 PM PDT 24
Peak memory 208832 kb
Host smart-4e798ac5-c15b-4400-ba1d-0af40a4e3d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118284976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2118284976
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1843128001
Short name T399
Test name
Test status
Simulation time 646423544 ps
CPU time 7.32 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:20 PM PDT 24
Peak memory 208916 kb
Host smart-76da047c-8419-40b8-9dbd-488b41cbc3ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843128001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1843128001
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2942432435
Short name T434
Test name
Test status
Simulation time 65682899 ps
CPU time 3.27 seconds
Started Apr 04 12:46:15 PM PDT 24
Finished Apr 04 12:46:18 PM PDT 24
Peak memory 208784 kb
Host smart-d9d34af6-918c-4f3e-91c0-41841905c1a2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942432435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2942432435
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3028048509
Short name T322
Test name
Test status
Simulation time 1478967211 ps
CPU time 5.98 seconds
Started Apr 04 12:46:21 PM PDT 24
Finished Apr 04 12:46:27 PM PDT 24
Peak memory 209096 kb
Host smart-763c1463-6c60-43a2-9c60-12ea8ddd0ba5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028048509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3028048509
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3127685002
Short name T327
Test name
Test status
Simulation time 87800149 ps
CPU time 2.12 seconds
Started Apr 04 12:46:18 PM PDT 24
Finished Apr 04 12:46:20 PM PDT 24
Peak memory 210244 kb
Host smart-ed94fad5-5829-44a5-8cd4-a5f50dccde09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127685002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3127685002
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3891057235
Short name T574
Test name
Test status
Simulation time 34036280 ps
CPU time 2.28 seconds
Started Apr 04 12:46:26 PM PDT 24
Finished Apr 04 12:46:29 PM PDT 24
Peak memory 208396 kb
Host smart-c0d868c9-924b-47a8-a1b2-7a3f02f00c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891057235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3891057235
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.595783011
Short name T612
Test name
Test status
Simulation time 1495029045 ps
CPU time 14.92 seconds
Started Apr 04 12:46:24 PM PDT 24
Finished Apr 04 12:46:39 PM PDT 24
Peak memory 222880 kb
Host smart-c35799cd-41ad-4bdf-862b-066c0916097d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595783011 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.595783011
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1269675434
Short name T203
Test name
Test status
Simulation time 1031793992 ps
CPU time 24.76 seconds
Started Apr 04 12:46:24 PM PDT 24
Finished Apr 04 12:46:49 PM PDT 24
Peak memory 214720 kb
Host smart-3351e0f8-226b-4eb9-9352-80ad2e3ccd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269675434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1269675434
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.351907335
Short name T638
Test name
Test status
Simulation time 14525007 ps
CPU time 0.76 seconds
Started Apr 04 12:46:22 PM PDT 24
Finished Apr 04 12:46:23 PM PDT 24
Peak memory 206212 kb
Host smart-d525ae6b-1de4-4df6-8389-2b6266b6f3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351907335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.351907335
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2471417202
Short name T30
Test name
Test status
Simulation time 195271666 ps
CPU time 2.78 seconds
Started Apr 04 12:46:29 PM PDT 24
Finished Apr 04 12:46:31 PM PDT 24
Peak memory 210148 kb
Host smart-aa6998c9-55de-4b52-bb2e-eb69910f4a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471417202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2471417202
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3431364096
Short name T13
Test name
Test status
Simulation time 1079266459 ps
CPU time 17.81 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:31 PM PDT 24
Peak memory 214584 kb
Host smart-a99cefd1-e81e-4d50-86c5-05c99b10a44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431364096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3431364096
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4156720574
Short name T811
Test name
Test status
Simulation time 446314762 ps
CPU time 9.68 seconds
Started Apr 04 12:46:35 PM PDT 24
Finished Apr 04 12:46:45 PM PDT 24
Peak memory 219344 kb
Host smart-3b2cf0a2-fc81-4b1e-a79d-8c96cfa5cea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156720574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4156720574
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.246444085
Short name T291
Test name
Test status
Simulation time 335538815 ps
CPU time 9.13 seconds
Started Apr 04 12:46:19 PM PDT 24
Finished Apr 04 12:46:28 PM PDT 24
Peak memory 214592 kb
Host smart-88aa34aa-4a7e-4f11-b453-ac90f7a2040e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246444085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.246444085
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1652346862
Short name T453
Test name
Test status
Simulation time 247674619 ps
CPU time 3.55 seconds
Started Apr 04 12:46:25 PM PDT 24
Finished Apr 04 12:46:29 PM PDT 24
Peak memory 216212 kb
Host smart-a575f8a2-1d3e-4dd9-9ebc-3c3afc22a01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652346862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1652346862
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1726613312
Short name T622
Test name
Test status
Simulation time 299279006 ps
CPU time 6.65 seconds
Started Apr 04 12:46:14 PM PDT 24
Finished Apr 04 12:46:21 PM PDT 24
Peak memory 214692 kb
Host smart-072af19d-7a6b-44a5-bb73-c0154feca627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726613312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1726613312
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.325672925
Short name T871
Test name
Test status
Simulation time 263357361 ps
CPU time 3.64 seconds
Started Apr 04 12:46:12 PM PDT 24
Finished Apr 04 12:46:15 PM PDT 24
Peak memory 208908 kb
Host smart-664e19f6-f7ec-4720-bc32-9e7348a847d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325672925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.325672925
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1082239609
Short name T623
Test name
Test status
Simulation time 599921875 ps
CPU time 6.55 seconds
Started Apr 04 12:46:17 PM PDT 24
Finished Apr 04 12:46:23 PM PDT 24
Peak memory 208724 kb
Host smart-20e9ca20-3f00-4d20-9610-1d542e3c44bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082239609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1082239609
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2414548808
Short name T789
Test name
Test status
Simulation time 111999812 ps
CPU time 5.1 seconds
Started Apr 04 12:46:12 PM PDT 24
Finished Apr 04 12:46:17 PM PDT 24
Peak memory 206960 kb
Host smart-65b3d4a6-84e1-4119-a4af-9e5e1d9b6435
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414548808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2414548808
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.891371184
Short name T792
Test name
Test status
Simulation time 84804898 ps
CPU time 1.88 seconds
Started Apr 04 12:46:14 PM PDT 24
Finished Apr 04 12:46:17 PM PDT 24
Peak memory 207144 kb
Host smart-fcd006ae-e25c-413d-8542-92bdeeed34ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891371184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.891371184
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1541541466
Short name T654
Test name
Test status
Simulation time 25599843 ps
CPU time 1.99 seconds
Started Apr 04 12:46:23 PM PDT 24
Finished Apr 04 12:46:25 PM PDT 24
Peak memory 209284 kb
Host smart-9618cfd2-37c9-418c-b8cb-5e407917f248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541541466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1541541466
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1589845242
Short name T825
Test name
Test status
Simulation time 180565322 ps
CPU time 4.82 seconds
Started Apr 04 12:46:13 PM PDT 24
Finished Apr 04 12:46:18 PM PDT 24
Peak memory 208412 kb
Host smart-372d243b-5e7a-4690-a165-91994bf8ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589845242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1589845242
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1655516326
Short name T502
Test name
Test status
Simulation time 235602809 ps
CPU time 4.5 seconds
Started Apr 04 12:46:14 PM PDT 24
Finished Apr 04 12:46:19 PM PDT 24
Peak memory 214712 kb
Host smart-17b8b634-c1bb-40fd-91c2-e2aa07069006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655516326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1655516326
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2401524704
Short name T562
Test name
Test status
Simulation time 189661653 ps
CPU time 2.7 seconds
Started Apr 04 12:46:23 PM PDT 24
Finished Apr 04 12:46:25 PM PDT 24
Peak memory 210204 kb
Host smart-486f1ad5-0564-42ed-af59-6075e3cb1123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401524704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2401524704
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.837425717
Short name T569
Test name
Test status
Simulation time 19696006 ps
CPU time 0.81 seconds
Started Apr 04 12:46:40 PM PDT 24
Finished Apr 04 12:46:41 PM PDT 24
Peak memory 206296 kb
Host smart-f37b5f49-d75d-46b6-b03a-609982751abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837425717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.837425717
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2177376545
Short name T261
Test name
Test status
Simulation time 52177305 ps
CPU time 2.69 seconds
Started Apr 04 12:46:30 PM PDT 24
Finished Apr 04 12:46:33 PM PDT 24
Peak memory 214680 kb
Host smart-15a244bc-7e9e-4c2d-a3ba-e50438eecaee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177376545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2177376545
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2654032241
Short name T819
Test name
Test status
Simulation time 9985106068 ps
CPU time 67.16 seconds
Started Apr 04 12:46:25 PM PDT 24
Finished Apr 04 12:47:32 PM PDT 24
Peak memory 222808 kb
Host smart-8a985454-32e1-4900-8e4e-ef7f864d5b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654032241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2654032241
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.4174206232
Short name T57
Test name
Test status
Simulation time 115373154 ps
CPU time 4.47 seconds
Started Apr 04 12:46:24 PM PDT 24
Finished Apr 04 12:46:28 PM PDT 24
Peak memory 218728 kb
Host smart-6f57d04a-4e72-4e88-bec0-b6afd496f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174206232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.4174206232
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2112266409
Short name T346
Test name
Test status
Simulation time 75956815 ps
CPU time 3.95 seconds
Started Apr 04 12:46:28 PM PDT 24
Finished Apr 04 12:46:32 PM PDT 24
Peak memory 218692 kb
Host smart-853e99af-1f66-4e4d-9c84-c60d322f0848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112266409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2112266409
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1917373281
Short name T908
Test name
Test status
Simulation time 98738754 ps
CPU time 4.72 seconds
Started Apr 04 12:46:23 PM PDT 24
Finished Apr 04 12:46:28 PM PDT 24
Peak memory 222816 kb
Host smart-5e7962a4-8b24-44a2-bd18-a6cb90486c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917373281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1917373281
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3244318146
Short name T560
Test name
Test status
Simulation time 333976419 ps
CPU time 4.01 seconds
Started Apr 04 12:46:31 PM PDT 24
Finished Apr 04 12:46:35 PM PDT 24
Peak memory 214580 kb
Host smart-0e7a1162-55e4-493d-b941-5dc276cb5900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244318146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3244318146
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3031100124
Short name T208
Test name
Test status
Simulation time 2052539100 ps
CPU time 56.61 seconds
Started Apr 04 12:46:24 PM PDT 24
Finished Apr 04 12:47:21 PM PDT 24
Peak memory 208384 kb
Host smart-516969fc-d619-46e0-83a8-247997138f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031100124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3031100124
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2743438086
Short name T454
Test name
Test status
Simulation time 1609556646 ps
CPU time 5.39 seconds
Started Apr 04 12:46:32 PM PDT 24
Finished Apr 04 12:46:37 PM PDT 24
Peak memory 206896 kb
Host smart-c8fc65f9-6faa-4f68-a2be-cebbbb602db6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743438086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2743438086
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2679989526
Short name T726
Test name
Test status
Simulation time 67262039 ps
CPU time 2.48 seconds
Started Apr 04 12:46:27 PM PDT 24
Finished Apr 04 12:46:30 PM PDT 24
Peak memory 207148 kb
Host smart-f4b93303-d4f4-468c-9665-8ab2cb33a6eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679989526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2679989526
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3095531860
Short name T284
Test name
Test status
Simulation time 374106081 ps
CPU time 7.04 seconds
Started Apr 04 12:46:29 PM PDT 24
Finished Apr 04 12:46:36 PM PDT 24
Peak memory 208240 kb
Host smart-cda35d10-81f5-4370-a967-96f734540a8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095531860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3095531860
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1089456165
Short name T298
Test name
Test status
Simulation time 71391518 ps
CPU time 2.43 seconds
Started Apr 04 12:46:37 PM PDT 24
Finished Apr 04 12:46:39 PM PDT 24
Peak memory 209312 kb
Host smart-f0091e67-0819-470b-af8a-cc1e39267cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089456165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1089456165
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1795631894
Short name T427
Test name
Test status
Simulation time 35102676 ps
CPU time 2.27 seconds
Started Apr 04 12:46:23 PM PDT 24
Finished Apr 04 12:46:25 PM PDT 24
Peak memory 206988 kb
Host smart-c39dc57c-bf4d-4987-99f3-0538e72d202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795631894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1795631894
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3121573890
Short name T185
Test name
Test status
Simulation time 53111898 ps
CPU time 0.84 seconds
Started Apr 04 12:46:45 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 206232 kb
Host smart-83ebbb73-7130-4aa6-9439-ea9a3e0df76f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121573890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3121573890
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3925251854
Short name T158
Test name
Test status
Simulation time 424954376 ps
CPU time 17.87 seconds
Started Apr 04 12:46:24 PM PDT 24
Finished Apr 04 12:46:42 PM PDT 24
Peak memory 222912 kb
Host smart-7eb583fe-19ba-424a-ac2e-ab34e8dc2c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925251854 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3925251854
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1630310389
Short name T280
Test name
Test status
Simulation time 423187644 ps
CPU time 4.96 seconds
Started Apr 04 12:46:25 PM PDT 24
Finished Apr 04 12:46:30 PM PDT 24
Peak memory 209524 kb
Host smart-27805f4c-e8f4-44a6-904b-409c156fae08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630310389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1630310389
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2296257982
Short name T677
Test name
Test status
Simulation time 26726417 ps
CPU time 1.62 seconds
Started Apr 04 12:46:28 PM PDT 24
Finished Apr 04 12:46:30 PM PDT 24
Peak memory 209872 kb
Host smart-3af292e0-d9ce-4758-aa1c-529179e3c30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296257982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2296257982
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1656565010
Short name T431
Test name
Test status
Simulation time 56792784 ps
CPU time 0.78 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:46:43 PM PDT 24
Peak memory 206240 kb
Host smart-186b4de6-c0bf-48c0-9a0f-19118c3ae426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656565010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1656565010
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4147264103
Short name T73
Test name
Test status
Simulation time 146944882 ps
CPU time 3.85 seconds
Started Apr 04 12:46:22 PM PDT 24
Finished Apr 04 12:46:26 PM PDT 24
Peak memory 214692 kb
Host smart-cb89ec4b-4af5-4f84-a503-ddf9e32dce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147264103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4147264103
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2548117536
Short name T267
Test name
Test status
Simulation time 389864430 ps
CPU time 4.01 seconds
Started Apr 04 12:46:27 PM PDT 24
Finished Apr 04 12:46:31 PM PDT 24
Peak memory 214448 kb
Host smart-ee961add-c049-4e29-84a9-17e5770b36c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548117536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2548117536
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3037489455
Short name T240
Test name
Test status
Simulation time 110297360 ps
CPU time 3.3 seconds
Started Apr 04 12:46:39 PM PDT 24
Finished Apr 04 12:46:43 PM PDT 24
Peak memory 207924 kb
Host smart-d3ed5c83-f912-4214-a47d-133b6ff3943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037489455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3037489455
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.681193835
Short name T321
Test name
Test status
Simulation time 311433187 ps
CPU time 6.81 seconds
Started Apr 04 12:46:26 PM PDT 24
Finished Apr 04 12:46:33 PM PDT 24
Peak memory 214720 kb
Host smart-653edf6c-fa0c-4172-93ab-3065a25da03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681193835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.681193835
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3034733657
Short name T586
Test name
Test status
Simulation time 445114234 ps
CPU time 9.01 seconds
Started Apr 04 12:46:26 PM PDT 24
Finished Apr 04 12:46:35 PM PDT 24
Peak memory 208188 kb
Host smart-be57921d-a087-412b-bbf3-72ad37ffe77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034733657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3034733657
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4282444841
Short name T173
Test name
Test status
Simulation time 1706859108 ps
CPU time 17.65 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 208708 kb
Host smart-e3155740-3357-4f69-ac5a-c92a90d1609b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282444841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4282444841
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.370382577
Short name T491
Test name
Test status
Simulation time 274661835 ps
CPU time 6.66 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 209120 kb
Host smart-d109e795-a6ee-4a68-a00d-709dafb4f236
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370382577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.370382577
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.4192171030
Short name T354
Test name
Test status
Simulation time 110271859 ps
CPU time 2.88 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:46:45 PM PDT 24
Peak memory 208896 kb
Host smart-3d1bdc4d-3bfe-48ff-bdc6-456777c8f1b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192171030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4192171030
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.864539401
Short name T628
Test name
Test status
Simulation time 324907224 ps
CPU time 2.98 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 210056 kb
Host smart-0484ac3f-1094-485c-ad08-c17d6918e0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864539401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.864539401
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3311568803
Short name T788
Test name
Test status
Simulation time 2199329779 ps
CPU time 4.42 seconds
Started Apr 04 12:46:25 PM PDT 24
Finished Apr 04 12:46:29 PM PDT 24
Peak memory 208608 kb
Host smart-2aa30666-2460-4972-af1a-816247cdab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311568803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3311568803
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.339463923
Short name T229
Test name
Test status
Simulation time 1111042582 ps
CPU time 29.36 seconds
Started Apr 04 12:46:36 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 222868 kb
Host smart-0dd51858-a4d9-4f7b-84a3-33b9e05f2934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339463923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.339463923
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2627491603
Short name T831
Test name
Test status
Simulation time 325600402 ps
CPU time 10.94 seconds
Started Apr 04 12:46:24 PM PDT 24
Finished Apr 04 12:46:35 PM PDT 24
Peak memory 218700 kb
Host smart-6ac2c6fd-4b17-4442-80d8-d20b1e26e1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627491603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2627491603
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.676493870
Short name T731
Test name
Test status
Simulation time 293083670 ps
CPU time 2.05 seconds
Started Apr 04 12:46:38 PM PDT 24
Finished Apr 04 12:46:40 PM PDT 24
Peak memory 209952 kb
Host smart-79fce574-0e69-4ba3-aa3f-437a30e462c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676493870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.676493870
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.205999874
Short name T424
Test name
Test status
Simulation time 71323932 ps
CPU time 0.81 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:46 PM PDT 24
Peak memory 206216 kb
Host smart-7cab543e-29ac-48e0-8778-37b9e6a5d8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205999874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.205999874
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3792424102
Short name T18
Test name
Test status
Simulation time 100675692 ps
CPU time 2.25 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:45 PM PDT 24
Peak memory 210120 kb
Host smart-d2e43f8b-b2a9-4f96-9fd4-49b8ac5c2c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792424102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3792424102
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2280402016
Short name T67
Test name
Test status
Simulation time 44377167 ps
CPU time 2.16 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 207652 kb
Host smart-bafd5189-1251-41fa-a44a-ce0d5e3346e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280402016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2280402016
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.735821340
Short name T95
Test name
Test status
Simulation time 323508511 ps
CPU time 3.86 seconds
Started Apr 04 12:46:41 PM PDT 24
Finished Apr 04 12:46:45 PM PDT 24
Peak memory 221440 kb
Host smart-f48c89e6-aa42-45db-809c-fce2c21e7e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735821340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.735821340
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2558541657
Short name T485
Test name
Test status
Simulation time 49679918 ps
CPU time 3.44 seconds
Started Apr 04 12:46:34 PM PDT 24
Finished Apr 04 12:46:38 PM PDT 24
Peak memory 214648 kb
Host smart-3aae064e-1e74-4919-9c52-ab0f1cff8fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558541657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2558541657
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3599172291
Short name T784
Test name
Test status
Simulation time 2617842798 ps
CPU time 51.9 seconds
Started Apr 04 12:46:37 PM PDT 24
Finished Apr 04 12:47:29 PM PDT 24
Peak memory 209732 kb
Host smart-e3f2e784-88a2-4da3-87bb-13000948d289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599172291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3599172291
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1337151772
Short name T254
Test name
Test status
Simulation time 5665862831 ps
CPU time 31.08 seconds
Started Apr 04 12:46:37 PM PDT 24
Finished Apr 04 12:47:09 PM PDT 24
Peak memory 209008 kb
Host smart-60252342-de68-4eea-93a2-511bfdc52d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337151772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1337151772
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.496024307
Short name T305
Test name
Test status
Simulation time 183012796 ps
CPU time 5.45 seconds
Started Apr 04 12:46:39 PM PDT 24
Finished Apr 04 12:46:45 PM PDT 24
Peak memory 209236 kb
Host smart-260da7ae-0f3c-4162-b8bb-056332af763c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496024307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.496024307
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.874101115
Short name T599
Test name
Test status
Simulation time 22950592 ps
CPU time 1.96 seconds
Started Apr 04 12:46:34 PM PDT 24
Finished Apr 04 12:46:36 PM PDT 24
Peak memory 207052 kb
Host smart-76b570be-1fc2-46c6-a5d3-64655700a270
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874101115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.874101115
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.288674419
Short name T307
Test name
Test status
Simulation time 85374474 ps
CPU time 2.99 seconds
Started Apr 04 12:46:40 PM PDT 24
Finished Apr 04 12:46:43 PM PDT 24
Peak memory 207988 kb
Host smart-f2e06be3-c9d1-4c9c-b462-6598aa69e8cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288674419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.288674419
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2066690785
Short name T661
Test name
Test status
Simulation time 82603605 ps
CPU time 1.97 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 216308 kb
Host smart-d238d438-40da-4d74-bcc6-9c3908c0055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066690785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2066690785
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2964531408
Short name T33
Test name
Test status
Simulation time 74110786 ps
CPU time 3.13 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:46:45 PM PDT 24
Peak memory 207244 kb
Host smart-4c898019-7444-4f54-98f8-e7e706b0898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964531408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2964531408
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2376626880
Short name T615
Test name
Test status
Simulation time 88975679 ps
CPU time 4.97 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:49 PM PDT 24
Peak memory 220772 kb
Host smart-08328aaa-41b8-46a7-8524-928d910243e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376626880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2376626880
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3863604801
Short name T210
Test name
Test status
Simulation time 96545932 ps
CPU time 4.31 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 209668 kb
Host smart-373f8cd2-f4cc-4157-bacf-d8f9732b698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863604801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3863604801
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2214140940
Short name T435
Test name
Test status
Simulation time 14072860 ps
CPU time 0.77 seconds
Started Apr 04 12:45:11 PM PDT 24
Finished Apr 04 12:45:12 PM PDT 24
Peak memory 206136 kb
Host smart-4119900e-27a1-4d8b-85e6-e27478426e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214140940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2214140940
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1519582134
Short name T323
Test name
Test status
Simulation time 181922222 ps
CPU time 3.53 seconds
Started Apr 04 12:46:18 PM PDT 24
Finished Apr 04 12:46:23 PM PDT 24
Peak memory 213568 kb
Host smart-9fac565e-a653-4faa-a3bf-56657f2fc81c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519582134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1519582134
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2847305584
Short name T734
Test name
Test status
Simulation time 472250859 ps
CPU time 5.14 seconds
Started Apr 04 12:45:25 PM PDT 24
Finished Apr 04 12:45:30 PM PDT 24
Peak memory 208960 kb
Host smart-71f2603e-3be6-45df-9732-9002a7817111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847305584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2847305584
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3283304464
Short name T759
Test name
Test status
Simulation time 185486174 ps
CPU time 4.05 seconds
Started Apr 04 12:45:08 PM PDT 24
Finished Apr 04 12:45:13 PM PDT 24
Peak memory 222596 kb
Host smart-b130308f-f9a5-491d-859c-1eb60b4187d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283304464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3283304464
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2329747069
Short name T581
Test name
Test status
Simulation time 41661148 ps
CPU time 3 seconds
Started Apr 04 12:45:10 PM PDT 24
Finished Apr 04 12:45:14 PM PDT 24
Peak memory 222776 kb
Host smart-607fa46e-06ff-41b9-98d4-fc87caff8eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329747069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2329747069
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.785922884
Short name T861
Test name
Test status
Simulation time 366260240 ps
CPU time 8.59 seconds
Started Apr 04 12:45:19 PM PDT 24
Finished Apr 04 12:45:28 PM PDT 24
Peak memory 214544 kb
Host smart-e5711ec8-795b-4349-842a-7754127d2ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785922884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.785922884
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1237003489
Short name T102
Test name
Test status
Simulation time 10202068707 ps
CPU time 71.81 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:46:24 PM PDT 24
Peak memory 251152 kb
Host smart-fec99cd0-a4bc-49f6-9722-a9876ed5fa76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237003489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1237003489
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2872698331
Short name T303
Test name
Test status
Simulation time 21507904480 ps
CPU time 56.69 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:46:09 PM PDT 24
Peak memory 209316 kb
Host smart-80130450-0335-4030-85b1-787162bf2bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872698331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2872698331
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.4201956339
Short name T462
Test name
Test status
Simulation time 1079800315 ps
CPU time 10.49 seconds
Started Apr 04 12:45:12 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 208832 kb
Host smart-e0088d97-385c-42c8-a1d6-be55c4ef84cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201956339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.4201956339
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.968859355
Short name T567
Test name
Test status
Simulation time 979440349 ps
CPU time 6.45 seconds
Started Apr 04 12:45:09 PM PDT 24
Finished Apr 04 12:45:16 PM PDT 24
Peak memory 208780 kb
Host smart-20e241a0-7568-44ee-b6eb-437560fa3933
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968859355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.968859355
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2306511606
Short name T437
Test name
Test status
Simulation time 181712468 ps
CPU time 6.9 seconds
Started Apr 04 12:45:30 PM PDT 24
Finished Apr 04 12:45:37 PM PDT 24
Peak memory 208244 kb
Host smart-e3394ce2-26e6-407c-a59e-3fce1e792c93
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306511606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2306511606
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3243745163
Short name T326
Test name
Test status
Simulation time 466854997 ps
CPU time 12.18 seconds
Started Apr 04 12:45:10 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 209924 kb
Host smart-9b8e785d-c2ab-4eef-9dee-c12e31a4df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243745163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3243745163
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3875540437
Short name T533
Test name
Test status
Simulation time 77424135 ps
CPU time 2.75 seconds
Started Apr 04 12:45:19 PM PDT 24
Finished Apr 04 12:45:22 PM PDT 24
Peak memory 206928 kb
Host smart-2b34a576-d1d4-48f6-a25a-200bc29c8614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875540437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3875540437
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3100602643
Short name T762
Test name
Test status
Simulation time 788419505 ps
CPU time 12.35 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:32 PM PDT 24
Peak memory 222796 kb
Host smart-0b36b7b7-5ea5-4b76-b385-bfab34d5062b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100602643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3100602643
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3439551273
Short name T318
Test name
Test status
Simulation time 150964052 ps
CPU time 6.67 seconds
Started Apr 04 12:45:29 PM PDT 24
Finished Apr 04 12:45:36 PM PDT 24
Peak memory 210288 kb
Host smart-b3e21626-9c79-4cb1-a5f7-4efaaa4ff6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439551273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3439551273
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2539290077
Short name T657
Test name
Test status
Simulation time 173081886 ps
CPU time 1.72 seconds
Started Apr 04 12:45:13 PM PDT 24
Finished Apr 04 12:45:15 PM PDT 24
Peak memory 210200 kb
Host smart-5d36b188-fc9c-4e53-aa6e-4854928b5fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539290077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2539290077
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.4283812314
Short name T735
Test name
Test status
Simulation time 23860580 ps
CPU time 0.84 seconds
Started Apr 04 12:46:40 PM PDT 24
Finished Apr 04 12:46:41 PM PDT 24
Peak memory 206200 kb
Host smart-0a103779-188e-47d2-8693-29fdc2cf993c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283812314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4283812314
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2476154464
Short name T386
Test name
Test status
Simulation time 245439080 ps
CPU time 4.53 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 215488 kb
Host smart-0863811d-0579-4b9c-928b-0f4281ba61bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2476154464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2476154464
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1373829380
Short name T538
Test name
Test status
Simulation time 174929818 ps
CPU time 7.36 seconds
Started Apr 04 12:46:41 PM PDT 24
Finished Apr 04 12:46:49 PM PDT 24
Peak memory 214496 kb
Host smart-15f9fce7-e5b5-4ba2-befa-698873fb6072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373829380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1373829380
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1646477667
Short name T590
Test name
Test status
Simulation time 234925195 ps
CPU time 2.12 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 208296 kb
Host smart-b6889132-803c-4bdb-b38b-47d1dfca4446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646477667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1646477667
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1353707302
Short name T88
Test name
Test status
Simulation time 226457972 ps
CPU time 5.19 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:46:48 PM PDT 24
Peak memory 209128 kb
Host smart-0a719a90-fa20-4d83-ba79-efa6e2e45154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353707302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1353707302
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1058424019
Short name T246
Test name
Test status
Simulation time 81123214 ps
CPU time 3.2 seconds
Started Apr 04 12:46:37 PM PDT 24
Finished Apr 04 12:46:41 PM PDT 24
Peak memory 214548 kb
Host smart-e784802c-716c-45b2-a320-2f60e44c34c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058424019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1058424019
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.595391412
Short name T486
Test name
Test status
Simulation time 508932207 ps
CPU time 3.8 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:46:48 PM PDT 24
Peak memory 220228 kb
Host smart-b5335770-65eb-4869-92a5-7e8fddf75d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595391412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.595391412
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.120224411
Short name T901
Test name
Test status
Simulation time 411917365 ps
CPU time 7 seconds
Started Apr 04 12:46:38 PM PDT 24
Finished Apr 04 12:46:45 PM PDT 24
Peak memory 218504 kb
Host smart-db921a45-c886-4d07-834a-ec58f768406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120224411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.120224411
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1327083680
Short name T401
Test name
Test status
Simulation time 99729351 ps
CPU time 3.69 seconds
Started Apr 04 12:46:39 PM PDT 24
Finished Apr 04 12:46:42 PM PDT 24
Peak memory 206960 kb
Host smart-af530211-e0e0-4d81-ba89-f6989811b639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327083680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1327083680
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3588630840
Short name T459
Test name
Test status
Simulation time 202108280 ps
CPU time 3.62 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:49 PM PDT 24
Peak memory 207168 kb
Host smart-38df02be-a322-45a8-a664-594f43e847c0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588630840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3588630840
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.502168365
Short name T404
Test name
Test status
Simulation time 23537655 ps
CPU time 1.89 seconds
Started Apr 04 12:46:41 PM PDT 24
Finished Apr 04 12:46:44 PM PDT 24
Peak memory 207016 kb
Host smart-d3ef2871-2e71-4647-bb48-6db28bb591de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502168365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.502168365
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2274969659
Short name T306
Test name
Test status
Simulation time 2745940177 ps
CPU time 28.75 seconds
Started Apr 04 12:46:41 PM PDT 24
Finished Apr 04 12:47:10 PM PDT 24
Peak memory 208468 kb
Host smart-f82e08a8-e0ed-4f39-8998-0fb75eb081d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274969659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2274969659
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3125626942
Short name T740
Test name
Test status
Simulation time 803705874 ps
CPU time 2.3 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 207596 kb
Host smart-0e770a0c-d208-4462-84b7-9332a32d84c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125626942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3125626942
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1977564777
Short name T705
Test name
Test status
Simulation time 187611748 ps
CPU time 3.2 seconds
Started Apr 04 12:46:41 PM PDT 24
Finished Apr 04 12:46:44 PM PDT 24
Peak memory 208872 kb
Host smart-360777e5-16d4-447d-af4c-0a65b50fb1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977564777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1977564777
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.4142388648
Short name T378
Test name
Test status
Simulation time 10597355138 ps
CPU time 110.81 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:48:33 PM PDT 24
Peak memory 217456 kb
Host smart-f6e77cd2-1ca8-4db2-8fec-1f7ced66f296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142388648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.4142388648
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.764170571
Short name T730
Test name
Test status
Simulation time 1126999467 ps
CPU time 8.36 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 210052 kb
Host smart-0b67a26c-e3b0-4313-96e3-060052efd235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764170571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.764170571
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2008063703
Short name T860
Test name
Test status
Simulation time 29727491 ps
CPU time 1.08 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:46:45 PM PDT 24
Peak memory 206472 kb
Host smart-4046a03f-3886-4b2d-9965-f5c88fe4f8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008063703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2008063703
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.146037288
Short name T32
Test name
Test status
Simulation time 557349511 ps
CPU time 5.65 seconds
Started Apr 04 12:46:41 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 220176 kb
Host smart-c5438a2d-805e-457b-b75e-be15238c5ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146037288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.146037288
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1539319157
Short name T458
Test name
Test status
Simulation time 282023076 ps
CPU time 3.95 seconds
Started Apr 04 12:46:41 PM PDT 24
Finished Apr 04 12:46:46 PM PDT 24
Peak memory 207700 kb
Host smart-683ce014-c7e9-41ac-840e-334493c8f68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539319157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1539319157
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.725189640
Short name T5
Test name
Test status
Simulation time 737869572 ps
CPU time 4.57 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:49 PM PDT 24
Peak memory 209536 kb
Host smart-487be37c-ff36-4eb7-a3d8-60708f83c8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725189640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.725189640
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3616494045
Short name T882
Test name
Test status
Simulation time 1926136580 ps
CPU time 10.97 seconds
Started Apr 04 12:46:37 PM PDT 24
Finished Apr 04 12:46:48 PM PDT 24
Peak memory 222612 kb
Host smart-44f26145-f72a-4fd9-b014-68944baf9784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616494045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3616494045
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3976915689
Short name T61
Test name
Test status
Simulation time 237012149 ps
CPU time 5.5 seconds
Started Apr 04 12:46:41 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 210580 kb
Host smart-3ace7a5d-7d9b-4411-92ee-2344e653a861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976915689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3976915689
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1081853643
Short name T660
Test name
Test status
Simulation time 699630566 ps
CPU time 18.14 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 210060 kb
Host smart-434410e4-08b5-4d53-99c6-b3e9a231d5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081853643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1081853643
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1096565797
Short name T481
Test name
Test status
Simulation time 279691489 ps
CPU time 4.11 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:49 PM PDT 24
Peak memory 209000 kb
Host smart-abe6be8e-2a7c-44b6-85aa-c9c03e070cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096565797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1096565797
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2228150461
Short name T896
Test name
Test status
Simulation time 252538252 ps
CPU time 4.47 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:49 PM PDT 24
Peak memory 207092 kb
Host smart-68cf6c53-88b9-469f-a036-371813a745e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228150461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2228150461
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.159168283
Short name T808
Test name
Test status
Simulation time 3112780701 ps
CPU time 6.12 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 208200 kb
Host smart-88d8a160-ba0b-4416-a9a1-28d2029381ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159168283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.159168283
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.648405061
Short name T688
Test name
Test status
Simulation time 3115109294 ps
CPU time 31.31 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:47:17 PM PDT 24
Peak memory 209488 kb
Host smart-67876cb2-343e-43d2-a282-3b2a425da000
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648405061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.648405061
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1828305866
Short name T666
Test name
Test status
Simulation time 337449388 ps
CPU time 4.54 seconds
Started Apr 04 12:46:41 PM PDT 24
Finished Apr 04 12:46:46 PM PDT 24
Peak memory 210112 kb
Host smart-c9601d9d-01fd-411a-9a6c-2c72a9bb131f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828305866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1828305866
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3424554799
Short name T433
Test name
Test status
Simulation time 177104700 ps
CPU time 2.58 seconds
Started Apr 04 12:46:42 PM PDT 24
Finished Apr 04 12:46:45 PM PDT 24
Peak memory 207104 kb
Host smart-122e575f-460e-41b2-b96f-4e4e99bb04ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424554799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3424554799
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2412013342
Short name T184
Test name
Test status
Simulation time 8279098658 ps
CPU time 53.16 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:47:38 PM PDT 24
Peak memory 222980 kb
Host smart-7cb09198-752c-45db-b3f7-3a423230c09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412013342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2412013342
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2680357136
Short name T776
Test name
Test status
Simulation time 2097357272 ps
CPU time 10.69 seconds
Started Apr 04 12:46:45 PM PDT 24
Finished Apr 04 12:46:57 PM PDT 24
Peak memory 218304 kb
Host smart-31f8a3bb-8e72-4829-9120-45599644543e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680357136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2680357136
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2205711429
Short name T544
Test name
Test status
Simulation time 89391059 ps
CPU time 4.06 seconds
Started Apr 04 12:46:43 PM PDT 24
Finished Apr 04 12:46:48 PM PDT 24
Peak memory 210540 kb
Host smart-d1dd3713-8944-4bec-a731-86fbee02f838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205711429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2205711429
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2425008618
Short name T445
Test name
Test status
Simulation time 59283373 ps
CPU time 0.75 seconds
Started Apr 04 12:46:53 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 206216 kb
Host smart-e98139ea-4b9f-4bbe-89ad-3f23ebe1d378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425008618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2425008618
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1167115288
Short name T11
Test name
Test status
Simulation time 850426637 ps
CPU time 4.82 seconds
Started Apr 04 12:46:45 PM PDT 24
Finished Apr 04 12:46:51 PM PDT 24
Peak memory 216892 kb
Host smart-48b79945-39ee-4b43-875c-2789a91fe538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167115288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1167115288
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.152829486
Short name T365
Test name
Test status
Simulation time 220013321 ps
CPU time 3.79 seconds
Started Apr 04 12:46:45 PM PDT 24
Finished Apr 04 12:46:50 PM PDT 24
Peak memory 207120 kb
Host smart-6583133c-567f-41cf-8ce6-85cb71a6f3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152829486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.152829486
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.582069377
Short name T815
Test name
Test status
Simulation time 200455365 ps
CPU time 3.6 seconds
Started Apr 04 12:46:49 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 209632 kb
Host smart-f2a9c2eb-1619-454b-af8f-0219a3d37ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582069377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.582069377
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.339060288
Short name T52
Test name
Test status
Simulation time 984508041 ps
CPU time 7.3 seconds
Started Apr 04 12:46:45 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 211764 kb
Host smart-784e9009-ed72-43dd-a956-5e27e26b7a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339060288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.339060288
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1866044
Short name T904
Test name
Test status
Simulation time 317356974 ps
CPU time 4.19 seconds
Started Apr 04 12:46:48 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 220652 kb
Host smart-dff254d2-4a6b-47c6-8ff9-cf508d3f1537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1866044
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.129809793
Short name T200
Test name
Test status
Simulation time 51653471 ps
CPU time 3.14 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:48 PM PDT 24
Peak memory 209288 kb
Host smart-29b6cd16-d9d9-4b1d-b7a9-f885350ce566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129809793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.129809793
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1819577521
Short name T363
Test name
Test status
Simulation time 26936038 ps
CPU time 1.89 seconds
Started Apr 04 12:46:52 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 207188 kb
Host smart-b697c225-ec26-4ff4-a72f-f827f2b7d5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819577521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1819577521
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.125119769
Short name T644
Test name
Test status
Simulation time 157354301 ps
CPU time 2.36 seconds
Started Apr 04 12:46:46 PM PDT 24
Finished Apr 04 12:46:49 PM PDT 24
Peak memory 207120 kb
Host smart-ce9c1c9f-d04c-47c3-812e-418556183cb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125119769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.125119769
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.231212409
Short name T475
Test name
Test status
Simulation time 232677033 ps
CPU time 7.92 seconds
Started Apr 04 12:46:53 PM PDT 24
Finished Apr 04 12:47:01 PM PDT 24
Peak memory 208128 kb
Host smart-ee2cba8b-ff98-41cd-825b-05b5079d5a91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231212409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.231212409
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2824417383
Short name T690
Test name
Test status
Simulation time 9362329333 ps
CPU time 62.8 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:47:49 PM PDT 24
Peak memory 208916 kb
Host smart-bf8aa967-ea7f-4ae1-93e9-5d31f8899cd1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824417383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2824417383
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.592886896
Short name T870
Test name
Test status
Simulation time 358792589 ps
CPU time 4.37 seconds
Started Apr 04 12:46:45 PM PDT 24
Finished Apr 04 12:46:51 PM PDT 24
Peak memory 208400 kb
Host smart-9c2595d3-ea17-45eb-9896-22c862ab3f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592886896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.592886896
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2185397372
Short name T873
Test name
Test status
Simulation time 892576812 ps
CPU time 8.83 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 208608 kb
Host smart-f954fbf3-f6b9-424d-b0a9-06cee5b4f640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185397372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2185397372
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1180998136
Short name T225
Test name
Test status
Simulation time 1745941039 ps
CPU time 19.82 seconds
Started Apr 04 12:46:48 PM PDT 24
Finished Apr 04 12:47:08 PM PDT 24
Peak memory 222124 kb
Host smart-09310612-8dca-4d43-bef7-2de5b62c5b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180998136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1180998136
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3672819964
Short name T540
Test name
Test status
Simulation time 493999927 ps
CPU time 5.73 seconds
Started Apr 04 12:46:48 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 208264 kb
Host smart-403873b2-3094-4d60-809d-dea4d660bc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672819964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3672819964
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1722426911
Short name T17
Test name
Test status
Simulation time 149456452 ps
CPU time 3.87 seconds
Started Apr 04 12:46:53 PM PDT 24
Finished Apr 04 12:46:57 PM PDT 24
Peak memory 210488 kb
Host smart-0b1b4474-c236-4138-8a8e-c4779065b488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722426911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1722426911
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2131545026
Short name T682
Test name
Test status
Simulation time 26772990 ps
CPU time 0.73 seconds
Started Apr 04 12:46:52 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 206228 kb
Host smart-6129cf20-cc1b-47f2-8825-670157d39411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131545026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2131545026
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.125003756
Short name T542
Test name
Test status
Simulation time 143961186 ps
CPU time 2.99 seconds
Started Apr 04 12:46:55 PM PDT 24
Finished Apr 04 12:46:58 PM PDT 24
Peak memory 217636 kb
Host smart-f4f686dc-f026-4b03-9235-18b09ddc0eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125003756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.125003756
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1220621620
Short name T791
Test name
Test status
Simulation time 592942403 ps
CPU time 6.46 seconds
Started Apr 04 12:46:49 PM PDT 24
Finished Apr 04 12:46:56 PM PDT 24
Peak memory 208968 kb
Host smart-50b6b465-eb6c-432b-92c8-b9ef54ef4849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220621620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1220621620
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1100128207
Short name T90
Test name
Test status
Simulation time 1944382331 ps
CPU time 7.85 seconds
Started Apr 04 12:46:48 PM PDT 24
Finished Apr 04 12:46:56 PM PDT 24
Peak memory 214592 kb
Host smart-47f7c939-ea4c-49d9-a23b-76f2f3a56170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100128207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1100128207
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3584428388
Short name T723
Test name
Test status
Simulation time 2180508835 ps
CPU time 45.2 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:45 PM PDT 24
Peak memory 221828 kb
Host smart-d2fc097a-e5f3-40bb-a26f-d5acb8d56ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584428388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3584428388
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.4068407015
Short name T63
Test name
Test status
Simulation time 244896155 ps
CPU time 4.77 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 222816 kb
Host smart-242a7aae-9c1b-4d3a-990e-9882423fd891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068407015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.4068407015
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2656576650
Short name T283
Test name
Test status
Simulation time 102888696 ps
CPU time 3.72 seconds
Started Apr 04 12:46:48 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 218664 kb
Host smart-6afdc978-d50d-45c6-a8c3-b3711d85e1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656576650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2656576650
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3575130612
Short name T522
Test name
Test status
Simulation time 1054344922 ps
CPU time 23.21 seconds
Started Apr 04 12:46:52 PM PDT 24
Finished Apr 04 12:47:16 PM PDT 24
Peak memory 208660 kb
Host smart-76572988-79c3-4cb6-90b3-727660809bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575130612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3575130612
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2037693221
Short name T259
Test name
Test status
Simulation time 91965429 ps
CPU time 2.06 seconds
Started Apr 04 12:46:46 PM PDT 24
Finished Apr 04 12:46:50 PM PDT 24
Peak memory 206984 kb
Host smart-8039bba7-eed7-4bb3-b3d4-d7d3a94251bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037693221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2037693221
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2188760228
Short name T584
Test name
Test status
Simulation time 236237986 ps
CPU time 3.23 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 207064 kb
Host smart-235579f3-e410-4b8b-be3b-6854e54a4fef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188760228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2188760228
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2873311849
Short name T747
Test name
Test status
Simulation time 193824971 ps
CPU time 3.44 seconds
Started Apr 04 12:46:49 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 207128 kb
Host smart-815eb552-9aa1-4cf1-af74-613c6b2dd960
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873311849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2873311849
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1869648297
Short name T196
Test name
Test status
Simulation time 177088343 ps
CPU time 2.69 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:46:51 PM PDT 24
Peak memory 214480 kb
Host smart-d057b376-9835-492d-8a73-dd5d56d799ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869648297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1869648297
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3371491385
Short name T189
Test name
Test status
Simulation time 29881213310 ps
CPU time 57.15 seconds
Started Apr 04 12:46:50 PM PDT 24
Finished Apr 04 12:47:48 PM PDT 24
Peak memory 207884 kb
Host smart-af95bf9e-88a6-4ff4-9577-4e2bfa4047a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371491385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3371491385
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3438677004
Short name T309
Test name
Test status
Simulation time 141870124 ps
CPU time 3.75 seconds
Started Apr 04 12:46:53 PM PDT 24
Finished Apr 04 12:46:57 PM PDT 24
Peak memory 208164 kb
Host smart-0d202f56-9ffc-4b43-b1d6-bfe2df5b9f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438677004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3438677004
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.4003770619
Short name T764
Test name
Test status
Simulation time 514879570 ps
CPU time 4.77 seconds
Started Apr 04 12:46:57 PM PDT 24
Finished Apr 04 12:47:02 PM PDT 24
Peak memory 210340 kb
Host smart-b85f588f-494c-4ab1-8db7-8502e79b3b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003770619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.4003770619
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1744281038
Short name T503
Test name
Test status
Simulation time 8809326 ps
CPU time 0.73 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:46 PM PDT 24
Peak memory 206200 kb
Host smart-198fbc5e-379c-44fe-a8f5-2eb7844b45ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744281038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1744281038
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2577446121
Short name T418
Test name
Test status
Simulation time 106641728 ps
CPU time 3.93 seconds
Started Apr 04 12:46:52 PM PDT 24
Finished Apr 04 12:46:56 PM PDT 24
Peak memory 214556 kb
Host smart-09807206-d9c4-4b69-a511-cf8dc2d9e581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577446121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2577446121
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2431677401
Short name T883
Test name
Test status
Simulation time 206782149 ps
CPU time 2.62 seconds
Started Apr 04 12:47:02 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 209572 kb
Host smart-e366ad5a-07a5-4410-8551-68165dab125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431677401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2431677401
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2970544538
Short name T893
Test name
Test status
Simulation time 3048506404 ps
CPU time 38.63 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:47:24 PM PDT 24
Peak memory 222656 kb
Host smart-596c7308-085d-4bc6-9e10-2535a27004f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970544538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2970544538
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3691521104
Short name T847
Test name
Test status
Simulation time 325830957 ps
CPU time 3.17 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 214384 kb
Host smart-d5745646-0ce3-45cc-9da5-5d423f2e6c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691521104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3691521104
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1182223348
Short name T320
Test name
Test status
Simulation time 2717534393 ps
CPU time 63.9 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:48:03 PM PDT 24
Peak memory 209184 kb
Host smart-c85eb785-7923-4206-aaae-75ae4eaecd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182223348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1182223348
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2434448797
Short name T865
Test name
Test status
Simulation time 710809250 ps
CPU time 23.88 seconds
Started Apr 04 12:46:52 PM PDT 24
Finished Apr 04 12:47:16 PM PDT 24
Peak memory 209164 kb
Host smart-cc08fd4b-1853-4949-83ed-e2ad0f940da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434448797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2434448797
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1711739307
Short name T299
Test name
Test status
Simulation time 60431258 ps
CPU time 2.35 seconds
Started Apr 04 12:46:48 PM PDT 24
Finished Apr 04 12:46:51 PM PDT 24
Peak memory 207592 kb
Host smart-1201dc98-bfb0-4829-a6fe-b2fb4844e866
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711739307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1711739307
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.125712756
Short name T251
Test name
Test status
Simulation time 130344423 ps
CPU time 4.03 seconds
Started Apr 04 12:46:50 PM PDT 24
Finished Apr 04 12:46:55 PM PDT 24
Peak memory 208884 kb
Host smart-d9c23c61-50be-463e-942f-b498fb148876
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125712756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.125712756
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3740413968
Short name T756
Test name
Test status
Simulation time 142422959 ps
CPU time 3.43 seconds
Started Apr 04 12:46:50 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 208616 kb
Host smart-67d7a7fa-7f29-4c0e-b58a-6515e71af211
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740413968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3740413968
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3807544640
Short name T691
Test name
Test status
Simulation time 559659097 ps
CPU time 13.88 seconds
Started Apr 04 12:46:45 PM PDT 24
Finished Apr 04 12:47:00 PM PDT 24
Peak memory 214056 kb
Host smart-68ea64f7-d9e0-4f8d-89d6-3bedf5d296e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807544640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3807544640
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.718741793
Short name T575
Test name
Test status
Simulation time 166231742 ps
CPU time 2.19 seconds
Started Apr 04 12:46:52 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 206836 kb
Host smart-a06b7484-2e59-4857-9391-a1921a372c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718741793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.718741793
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3038722325
Short name T716
Test name
Test status
Simulation time 9379180657 ps
CPU time 66.66 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:47:52 PM PDT 24
Peak memory 214708 kb
Host smart-9ae7618b-8902-4fa5-9490-fc672914d125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038722325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3038722325
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3900344770
Short name T117
Test name
Test status
Simulation time 1205640060 ps
CPU time 12.3 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:58 PM PDT 24
Peak memory 222860 kb
Host smart-1ff5a1ca-2e44-4cf6-b9e9-668f5f1e1e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900344770 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3900344770
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4278897832
Short name T490
Test name
Test status
Simulation time 283648393 ps
CPU time 7.22 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:46:55 PM PDT 24
Peak memory 208216 kb
Host smart-878d1f79-d8d4-4e49-ba4e-852e8e87613e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278897832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4278897832
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3643159952
Short name T388
Test name
Test status
Simulation time 90646383 ps
CPU time 1.63 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 210492 kb
Host smart-1d348f15-5702-4683-a9a5-070d923c4c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643159952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3643159952
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2597747433
Short name T527
Test name
Test status
Simulation time 45938611 ps
CPU time 0.89 seconds
Started Apr 04 12:46:44 PM PDT 24
Finished Apr 04 12:46:47 PM PDT 24
Peak memory 206300 kb
Host smart-c55c448d-bd6c-4a54-b3b6-bec8d17a90a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597747433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2597747433
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1341635377
Short name T797
Test name
Test status
Simulation time 272568479 ps
CPU time 2.06 seconds
Started Apr 04 12:46:50 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 207340 kb
Host smart-1de58841-3f56-40aa-bbd3-33d709a4d6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341635377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1341635377
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3238794567
Short name T758
Test name
Test status
Simulation time 690715732 ps
CPU time 9.44 seconds
Started Apr 04 12:46:46 PM PDT 24
Finished Apr 04 12:46:56 PM PDT 24
Peak memory 210080 kb
Host smart-f8430362-7b3f-44c2-9a4f-9884edd43ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238794567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3238794567
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3161185393
Short name T245
Test name
Test status
Simulation time 247148139 ps
CPU time 5.45 seconds
Started Apr 04 12:46:46 PM PDT 24
Finished Apr 04 12:46:53 PM PDT 24
Peak memory 210532 kb
Host smart-224e3945-f789-46a6-9aff-52056a06e667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161185393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3161185393
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4205063169
Short name T637
Test name
Test status
Simulation time 1537471337 ps
CPU time 3.41 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:46:51 PM PDT 24
Peak memory 217696 kb
Host smart-d68a47f3-2dab-461c-8c5a-337e0b7f79e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205063169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4205063169
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2100835586
Short name T885
Test name
Test status
Simulation time 287452379 ps
CPU time 8.28 seconds
Started Apr 04 12:46:54 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 209500 kb
Host smart-b1b2c99e-d0dc-457b-8953-edfdde80a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100835586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2100835586
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2992366578
Short name T878
Test name
Test status
Simulation time 81619635 ps
CPU time 3.24 seconds
Started Apr 04 12:46:56 PM PDT 24
Finished Apr 04 12:47:00 PM PDT 24
Peak memory 208512 kb
Host smart-a0931e01-4be8-4362-9cb0-82c9469bb5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992366578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2992366578
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1999515119
Short name T288
Test name
Test status
Simulation time 318627059 ps
CPU time 4.95 seconds
Started Apr 04 12:46:50 PM PDT 24
Finished Apr 04 12:46:56 PM PDT 24
Peak memory 208100 kb
Host smart-be84f767-738c-42f0-88b9-365a6a90de84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999515119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1999515119
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3379086700
Short name T471
Test name
Test status
Simulation time 202761471 ps
CPU time 3.02 seconds
Started Apr 04 12:46:49 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 207220 kb
Host smart-5f24a2a0-edb6-4a43-ac82-4e8b9d39e1da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379086700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3379086700
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1799646094
Short name T482
Test name
Test status
Simulation time 5486797992 ps
CPU time 10.76 seconds
Started Apr 04 12:46:48 PM PDT 24
Finished Apr 04 12:46:59 PM PDT 24
Peak memory 208944 kb
Host smart-87d9ef7c-ca92-49b1-a2b3-1a05c929c65e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799646094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1799646094
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4189856873
Short name T343
Test name
Test status
Simulation time 96888469 ps
CPU time 2.69 seconds
Started Apr 04 12:46:46 PM PDT 24
Finished Apr 04 12:46:50 PM PDT 24
Peak memory 218460 kb
Host smart-9fc2e96c-5de9-4715-8509-ac58df62a0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189856873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4189856873
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3311801964
Short name T686
Test name
Test status
Simulation time 118977997 ps
CPU time 2.46 seconds
Started Apr 04 12:46:49 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 208536 kb
Host smart-aa99d8f8-fb09-4d7d-a329-4920a5862ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311801964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3311801964
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2138099329
Short name T150
Test name
Test status
Simulation time 360756386 ps
CPU time 5.09 seconds
Started Apr 04 12:46:46 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 219528 kb
Host smart-4ae987f2-5365-40cb-884c-bda6ec679760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138099329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2138099329
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.4276014403
Short name T898
Test name
Test status
Simulation time 2150278762 ps
CPU time 21.64 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:47:10 PM PDT 24
Peak memory 223008 kb
Host smart-53a24b5e-5ad6-4a03-a6f0-db780f823edf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276014403 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.4276014403
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1920727429
Short name T334
Test name
Test status
Simulation time 764920655 ps
CPU time 7.64 seconds
Started Apr 04 12:46:53 PM PDT 24
Finished Apr 04 12:47:01 PM PDT 24
Peak memory 208312 kb
Host smart-488252ec-3b1e-43f9-a627-9424a5b4ada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920727429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1920727429
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2135348219
Short name T389
Test name
Test status
Simulation time 960162703 ps
CPU time 14.16 seconds
Started Apr 04 12:46:49 PM PDT 24
Finished Apr 04 12:47:04 PM PDT 24
Peak memory 210724 kb
Host smart-86d4e88e-ea9c-4045-9758-b0af35b0d9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135348219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2135348219
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4077199459
Short name T741
Test name
Test status
Simulation time 15183084 ps
CPU time 0.8 seconds
Started Apr 04 12:46:55 PM PDT 24
Finished Apr 04 12:46:56 PM PDT 24
Peak memory 206232 kb
Host smart-0bf62e56-b12e-44ee-a7d5-dadbc0ce8dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077199459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4077199459
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2181940777
Short name T111
Test name
Test status
Simulation time 218371710 ps
CPU time 4 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:46:52 PM PDT 24
Peak memory 215736 kb
Host smart-348d849d-04ae-4ca4-bba1-5e8a29c82959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181940777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2181940777
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2101012274
Short name T25
Test name
Test status
Simulation time 498868902 ps
CPU time 3.41 seconds
Started Apr 04 12:46:54 PM PDT 24
Finished Apr 04 12:46:58 PM PDT 24
Peak memory 214852 kb
Host smart-d411df2a-0304-4072-bd7c-25dbf47eb2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101012274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2101012274
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.526874217
Short name T349
Test name
Test status
Simulation time 79912079 ps
CPU time 3.13 seconds
Started Apr 04 12:46:56 PM PDT 24
Finished Apr 04 12:46:59 PM PDT 24
Peak memory 218604 kb
Host smart-061218ac-882a-45c3-8cfc-5afe60359efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526874217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.526874217
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3874142512
Short name T720
Test name
Test status
Simulation time 241477854 ps
CPU time 3.39 seconds
Started Apr 04 12:46:56 PM PDT 24
Finished Apr 04 12:46:59 PM PDT 24
Peak memory 214592 kb
Host smart-6414d6e2-4ac7-4e78-9962-5ca977733739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874142512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3874142512
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1650651205
Short name T269
Test name
Test status
Simulation time 426908102 ps
CPU time 16.44 seconds
Started Apr 04 12:46:58 PM PDT 24
Finished Apr 04 12:47:15 PM PDT 24
Peak memory 221780 kb
Host smart-5abdcb86-362b-4568-a642-a211bb07a61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650651205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1650651205
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3844920011
Short name T302
Test name
Test status
Simulation time 66033665 ps
CPU time 2.57 seconds
Started Apr 04 12:46:51 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 210464 kb
Host smart-82ada6fa-341b-4419-9e6a-b5fd1e549ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844920011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3844920011
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.558256116
Short name T319
Test name
Test status
Simulation time 1650909851 ps
CPU time 5.7 seconds
Started Apr 04 12:46:47 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 218424 kb
Host smart-662205f9-255d-4d64-93b0-5744c58f3275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558256116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.558256116
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1679826390
Short name T206
Test name
Test status
Simulation time 248241789 ps
CPU time 3.22 seconds
Started Apr 04 12:46:52 PM PDT 24
Finished Apr 04 12:46:55 PM PDT 24
Peak memory 206880 kb
Host smart-3c33f9cb-3a84-4b1e-b067-9128add2d59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679826390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1679826390
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.4153756403
Short name T830
Test name
Test status
Simulation time 482747303 ps
CPU time 4.42 seconds
Started Apr 04 12:46:54 PM PDT 24
Finished Apr 04 12:46:59 PM PDT 24
Peak memory 207136 kb
Host smart-e1f2bf84-02de-4b10-aa91-535759eb2482
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153756403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.4153756403
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.905932805
Short name T530
Test name
Test status
Simulation time 618981485 ps
CPU time 11.13 seconds
Started Apr 04 12:46:46 PM PDT 24
Finished Apr 04 12:46:58 PM PDT 24
Peak memory 208092 kb
Host smart-29abea16-ead3-4be1-9179-60ff72069137
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905932805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.905932805
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3232157670
Short name T370
Test name
Test status
Simulation time 218396707 ps
CPU time 3.14 seconds
Started Apr 04 12:46:53 PM PDT 24
Finished Apr 04 12:46:56 PM PDT 24
Peak memory 209012 kb
Host smart-5455d351-97d0-4dfc-b6ab-ffdb664113bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232157670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3232157670
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.593714972
Short name T807
Test name
Test status
Simulation time 7970726676 ps
CPU time 27.31 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:29 PM PDT 24
Peak memory 219844 kb
Host smart-e190b096-a857-4b38-9e64-34b278f843d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593714972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.593714972
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3495828338
Short name T810
Test name
Test status
Simulation time 92064955 ps
CPU time 2.63 seconds
Started Apr 04 12:46:46 PM PDT 24
Finished Apr 04 12:46:50 PM PDT 24
Peak memory 206928 kb
Host smart-a068ff81-4a4f-4efd-978b-4e32218b03fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495828338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3495828338
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.82136725
Short name T167
Test name
Test status
Simulation time 591405862 ps
CPU time 18.75 seconds
Started Apr 04 12:46:54 PM PDT 24
Finished Apr 04 12:47:13 PM PDT 24
Peak memory 222852 kb
Host smart-8df2ddf0-2085-44a6-9409-f14232a92f83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82136725 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.82136725
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.984460271
Short name T507
Test name
Test status
Simulation time 241722816 ps
CPU time 3.76 seconds
Started Apr 04 12:46:50 PM PDT 24
Finished Apr 04 12:46:54 PM PDT 24
Peak memory 210036 kb
Host smart-f0a45e22-1fec-4e3b-bccf-cf8cb1a724a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984460271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.984460271
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1616089216
Short name T894
Test name
Test status
Simulation time 122881597 ps
CPU time 3.4 seconds
Started Apr 04 12:46:54 PM PDT 24
Finished Apr 04 12:46:58 PM PDT 24
Peak memory 210372 kb
Host smart-f45bea44-144a-4380-8463-0b39baf73f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616089216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1616089216
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3169723687
Short name T426
Test name
Test status
Simulation time 10744882 ps
CPU time 0.71 seconds
Started Apr 04 12:46:57 PM PDT 24
Finished Apr 04 12:46:58 PM PDT 24
Peak memory 206140 kb
Host smart-a0180a7a-8920-47f2-9a1f-79ce1b97aad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169723687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3169723687
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1397799561
Short name T238
Test name
Test status
Simulation time 73769032 ps
CPU time 2.63 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 215472 kb
Host smart-0421968a-e7a6-4b44-8855-ea57832365b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397799561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1397799561
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2037716142
Short name T887
Test name
Test status
Simulation time 161218193 ps
CPU time 2.07 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:02 PM PDT 24
Peak memory 218440 kb
Host smart-796452ef-7e0d-49fe-9055-6b2fc381f7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037716142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2037716142
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1812890648
Short name T348
Test name
Test status
Simulation time 879109249 ps
CPU time 7.23 seconds
Started Apr 04 12:47:13 PM PDT 24
Finished Apr 04 12:47:22 PM PDT 24
Peak memory 214600 kb
Host smart-b4714195-f69d-4d44-82e9-72d19cd48a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812890648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1812890648
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3637043161
Short name T248
Test name
Test status
Simulation time 558385295 ps
CPU time 12.55 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 215568 kb
Host smart-891ae86a-526d-440c-94a9-8d48da730b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637043161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3637043161
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2872059864
Short name T556
Test name
Test status
Simulation time 557644541 ps
CPU time 4.29 seconds
Started Apr 04 12:46:55 PM PDT 24
Finished Apr 04 12:46:59 PM PDT 24
Peak memory 222736 kb
Host smart-d4859335-26cc-44fd-aae1-16ce667d4b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872059864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2872059864
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.796546774
Short name T380
Test name
Test status
Simulation time 5431099652 ps
CPU time 39.28 seconds
Started Apr 04 12:46:54 PM PDT 24
Finished Apr 04 12:47:34 PM PDT 24
Peak memory 214764 kb
Host smart-2fd64244-d9a6-43c9-94fe-47be7dc61d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796546774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.796546774
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.874919718
Short name T662
Test name
Test status
Simulation time 487975693 ps
CPU time 4.11 seconds
Started Apr 04 12:46:53 PM PDT 24
Finished Apr 04 12:46:58 PM PDT 24
Peak memory 208896 kb
Host smart-dc5741fb-00c9-4096-9e8d-a8a60c22b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874919718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.874919718
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.357320790
Short name T402
Test name
Test status
Simulation time 171798896 ps
CPU time 6.19 seconds
Started Apr 04 12:46:56 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 209284 kb
Host smart-f3894982-b03e-4aad-9007-419dba07789a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357320790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.357320790
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1038810390
Short name T536
Test name
Test status
Simulation time 567282271 ps
CPU time 19.26 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:19 PM PDT 24
Peak memory 208792 kb
Host smart-47bf8f99-d6a1-49e9-8306-ba124c3940d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038810390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1038810390
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4004584633
Short name T534
Test name
Test status
Simulation time 299034872 ps
CPU time 4.26 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:04 PM PDT 24
Peak memory 208836 kb
Host smart-d906d8a9-0822-44f3-90fe-f1cc13346d0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004584633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4004584633
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2519629232
Short name T589
Test name
Test status
Simulation time 709274164 ps
CPU time 19.09 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:21 PM PDT 24
Peak memory 208856 kb
Host smart-5d9c0ff2-6e39-47f8-83ab-9922749ad09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519629232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2519629232
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3650792648
Short name T800
Test name
Test status
Simulation time 111340109 ps
CPU time 5.48 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:07 PM PDT 24
Peak memory 209404 kb
Host smart-f1a48293-b104-4f31-b82e-4e38ecc2005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650792648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3650792648
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.470194590
Short name T856
Test name
Test status
Simulation time 212760206 ps
CPU time 2.4 seconds
Started Apr 04 12:46:56 PM PDT 24
Finished Apr 04 12:46:59 PM PDT 24
Peak memory 210156 kb
Host smart-6b0780d1-726a-43ef-9200-78b553e70d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470194590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.470194590
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.256700827
Short name T850
Test name
Test status
Simulation time 78272284 ps
CPU time 0.86 seconds
Started Apr 04 12:47:04 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 206272 kb
Host smart-ba787a8d-10f2-4620-8533-887ece3ca698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256700827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.256700827
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.362563862
Short name T300
Test name
Test status
Simulation time 539829400 ps
CPU time 14.11 seconds
Started Apr 04 12:47:05 PM PDT 24
Finished Apr 04 12:47:19 PM PDT 24
Peak memory 214476 kb
Host smart-51a2aa1e-3cf6-4d8c-addc-f3f286391741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362563862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.362563862
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.162069853
Short name T679
Test name
Test status
Simulation time 151416062 ps
CPU time 3.39 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 214668 kb
Host smart-bebe7ebb-4c20-4069-af7d-59a8ef00a661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162069853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.162069853
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2303620722
Short name T627
Test name
Test status
Simulation time 1101780950 ps
CPU time 5.33 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 214556 kb
Host smart-95ef12e7-2306-4f46-b7cb-6b8d078e32d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303620722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2303620722
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2231373140
Short name T824
Test name
Test status
Simulation time 312459297 ps
CPU time 4.22 seconds
Started Apr 04 12:47:08 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 210160 kb
Host smart-1939fdde-c9ac-4ec6-8971-c886d9db091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231373140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2231373140
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.655583084
Short name T275
Test name
Test status
Simulation time 1548356806 ps
CPU time 28.85 seconds
Started Apr 04 12:47:15 PM PDT 24
Finished Apr 04 12:47:44 PM PDT 24
Peak memory 222784 kb
Host smart-31d012ae-6cdf-4919-9c3a-2e592255e7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655583084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.655583084
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.280378051
Short name T667
Test name
Test status
Simulation time 299931784 ps
CPU time 3.65 seconds
Started Apr 04 12:46:54 PM PDT 24
Finished Apr 04 12:46:58 PM PDT 24
Peak memory 214652 kb
Host smart-dec3d14e-c89d-48cb-91d5-688a51911a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280378051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.280378051
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2175148178
Short name T535
Test name
Test status
Simulation time 751354724 ps
CPU time 6.28 seconds
Started Apr 04 12:47:03 PM PDT 24
Finished Apr 04 12:47:09 PM PDT 24
Peak memory 209688 kb
Host smart-b54a9f16-4c26-41d6-be0a-90d37f09a71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175148178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2175148178
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2028781359
Short name T494
Test name
Test status
Simulation time 178000131 ps
CPU time 2.49 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 207020 kb
Host smart-ad63bedd-9bbf-4bda-8fcd-19823c9915ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028781359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2028781359
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3404689908
Short name T665
Test name
Test status
Simulation time 403562564 ps
CPU time 3.69 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:04 PM PDT 24
Peak memory 208732 kb
Host smart-23db2aff-7f08-4077-9136-af0467ffcb5c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404689908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3404689908
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3335024989
Short name T498
Test name
Test status
Simulation time 1957680848 ps
CPU time 29.21 seconds
Started Apr 04 12:47:03 PM PDT 24
Finished Apr 04 12:47:33 PM PDT 24
Peak memory 207376 kb
Host smart-e1dbeb63-ae0d-45ae-9b1d-6e1d89470d32
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335024989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3335024989
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.430413575
Short name T664
Test name
Test status
Simulation time 1719426557 ps
CPU time 11.07 seconds
Started Apr 04 12:47:05 PM PDT 24
Finished Apr 04 12:47:16 PM PDT 24
Peak memory 208040 kb
Host smart-f53492b4-4258-4903-ac5a-fd189a1accd5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430413575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.430413575
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2895669995
Short name T375
Test name
Test status
Simulation time 614889407 ps
CPU time 7.64 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:07 PM PDT 24
Peak memory 209952 kb
Host smart-0016aa35-34c9-4db8-8856-865ba723a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895669995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2895669995
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3618345850
Short name T680
Test name
Test status
Simulation time 259126490 ps
CPU time 2.8 seconds
Started Apr 04 12:47:04 PM PDT 24
Finished Apr 04 12:47:06 PM PDT 24
Peak memory 206808 kb
Host smart-0882bf2b-1819-497d-b143-6ee80c7f3f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618345850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3618345850
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1916743687
Short name T316
Test name
Test status
Simulation time 137629190 ps
CPU time 5.15 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:06 PM PDT 24
Peak memory 214584 kb
Host smart-41a05a99-7da9-4d8b-9d69-ffaf36735ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916743687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1916743687
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3845977557
Short name T443
Test name
Test status
Simulation time 70526456 ps
CPU time 1.96 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 209780 kb
Host smart-bcacccdb-2e7e-4f76-a402-3910df9f06a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845977557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3845977557
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1243352203
Short name T428
Test name
Test status
Simulation time 25181157 ps
CPU time 0.76 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:02 PM PDT 24
Peak memory 206152 kb
Host smart-62f6a3fa-a10d-44b6-94b9-f325293b920c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243352203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1243352203
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3417715334
Short name T357
Test name
Test status
Simulation time 97920081 ps
CPU time 5.77 seconds
Started Apr 04 12:47:07 PM PDT 24
Finished Apr 04 12:47:13 PM PDT 24
Peak memory 215496 kb
Host smart-4612064e-49ec-4dd0-9c88-9340e9a93f0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417715334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3417715334
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1036905567
Short name T513
Test name
Test status
Simulation time 238126747 ps
CPU time 2.01 seconds
Started Apr 04 12:47:07 PM PDT 24
Finished Apr 04 12:47:09 PM PDT 24
Peak memory 220012 kb
Host smart-a37978d0-417f-438f-aa21-6d7586e37ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036905567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1036905567
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3383076529
Short name T172
Test name
Test status
Simulation time 315362671 ps
CPU time 3.19 seconds
Started Apr 04 12:47:03 PM PDT 24
Finished Apr 04 12:47:06 PM PDT 24
Peak memory 209580 kb
Host smart-97909c4b-43ad-4211-8d0e-2b453f53230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383076529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3383076529
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1392173045
Short name T93
Test name
Test status
Simulation time 1337413192 ps
CPU time 5.01 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:06 PM PDT 24
Peak memory 209628 kb
Host smart-b6e0847d-7927-4eaa-b0b2-f93865699988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392173045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1392173045
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4246299583
Short name T823
Test name
Test status
Simulation time 137481694 ps
CPU time 2.91 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:04 PM PDT 24
Peak memory 222684 kb
Host smart-81d12d42-8334-4473-ae13-cf119d0027bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246299583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4246299583
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2976684934
Short name T519
Test name
Test status
Simulation time 364313973 ps
CPU time 2.94 seconds
Started Apr 04 12:47:02 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 209364 kb
Host smart-6de3b892-53a8-40b0-aa40-7f1f3f1f4736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976684934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2976684934
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3746663655
Short name T255
Test name
Test status
Simulation time 79701251 ps
CPU time 3.64 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 209524 kb
Host smart-252efdac-6652-4829-a4f6-19568c92857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746663655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3746663655
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2612786428
Short name T863
Test name
Test status
Simulation time 84454432 ps
CPU time 1.84 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 207072 kb
Host smart-0859580b-5970-42f2-97da-aaeb43207702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612786428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2612786428
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2785776867
Short name T293
Test name
Test status
Simulation time 1128247809 ps
CPU time 20.88 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:22 PM PDT 24
Peak memory 208908 kb
Host smart-41c3a823-d895-49ef-9c32-b5ee650d3bbf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785776867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2785776867
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2489237536
Short name T242
Test name
Test status
Simulation time 160636948 ps
CPU time 5.73 seconds
Started Apr 04 12:47:07 PM PDT 24
Finished Apr 04 12:47:13 PM PDT 24
Peak memory 208880 kb
Host smart-867f030b-6f83-474b-bf01-a6c0c8304d2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489237536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2489237536
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3365924549
Short name T880
Test name
Test status
Simulation time 176285334 ps
CPU time 2.54 seconds
Started Apr 04 12:47:02 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 207028 kb
Host smart-0b20a737-7719-49a2-a02d-b98e91bca7b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365924549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3365924549
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3831915272
Short name T377
Test name
Test status
Simulation time 67951167 ps
CPU time 2.98 seconds
Started Apr 04 12:47:06 PM PDT 24
Finished Apr 04 12:47:09 PM PDT 24
Peak memory 208828 kb
Host smart-c1d1955e-8031-4745-801a-096ada27ddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831915272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3831915272
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1924279033
Short name T179
Test name
Test status
Simulation time 37238136 ps
CPU time 1.69 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:01 PM PDT 24
Peak memory 206904 kb
Host smart-a87e71c9-102c-4894-ad36-6b03cd1dd1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924279033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1924279033
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2771516712
Short name T168
Test name
Test status
Simulation time 472830103 ps
CPU time 16.73 seconds
Started Apr 04 12:47:01 PM PDT 24
Finished Apr 04 12:47:18 PM PDT 24
Peak memory 222816 kb
Host smart-4f5d3ea9-2b5b-4554-bccf-07617ff43276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771516712 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2771516712
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2916294909
Short name T204
Test name
Test status
Simulation time 2259159150 ps
CPU time 49.03 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:48:01 PM PDT 24
Peak memory 209564 kb
Host smart-b7006612-d516-4fdf-af46-292e3543fc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916294909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2916294909
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2733076295
Short name T699
Test name
Test status
Simulation time 37982925 ps
CPU time 2.08 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 210080 kb
Host smart-b35b43be-b7e0-4a59-bebd-21ea26bdf62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733076295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2733076295
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3920500644
Short name T643
Test name
Test status
Simulation time 20051668 ps
CPU time 0.84 seconds
Started Apr 04 12:45:13 PM PDT 24
Finished Apr 04 12:45:14 PM PDT 24
Peak memory 206180 kb
Host smart-3df2043a-73ff-4a2a-beba-09a5fc958691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920500644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3920500644
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1000746601
Short name T467
Test name
Test status
Simulation time 3166576010 ps
CPU time 15.72 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:36 PM PDT 24
Peak memory 210504 kb
Host smart-181f1845-8346-4ac0-8197-0e4f8cb7f7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000746601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1000746601
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1737766320
Short name T92
Test name
Test status
Simulation time 1072809614 ps
CPU time 9.25 seconds
Started Apr 04 12:45:14 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 214652 kb
Host smart-f590f5b9-95fd-4fc1-b93e-2feca80bdb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737766320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1737766320
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3447306231
Short name T866
Test name
Test status
Simulation time 68700693 ps
CPU time 3.6 seconds
Started Apr 04 12:46:32 PM PDT 24
Finished Apr 04 12:46:36 PM PDT 24
Peak memory 214428 kb
Host smart-f9ddf287-a85d-484d-b978-03c0dccbb2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447306231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3447306231
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.4069412193
Short name T610
Test name
Test status
Simulation time 85197338 ps
CPU time 2.66 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 218040 kb
Host smart-959acc7e-edab-4d66-bb8d-9f88e03c6286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069412193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.4069412193
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3000061636
Short name T239
Test name
Test status
Simulation time 1265940826 ps
CPU time 31.89 seconds
Started Apr 04 12:45:26 PM PDT 24
Finished Apr 04 12:45:58 PM PDT 24
Peak memory 209044 kb
Host smart-5ec7750b-9814-44c7-86ee-02986ed26f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000061636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3000061636
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3608998714
Short name T12
Test name
Test status
Simulation time 1196826740 ps
CPU time 25.92 seconds
Started Apr 04 12:46:35 PM PDT 24
Finished Apr 04 12:47:02 PM PDT 24
Peak memory 239552 kb
Host smart-09de4e3d-b23e-4d85-890c-8469e78b9c40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608998714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3608998714
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.465736055
Short name T360
Test name
Test status
Simulation time 1015724259 ps
CPU time 27.65 seconds
Started Apr 04 12:45:10 PM PDT 24
Finished Apr 04 12:45:38 PM PDT 24
Peak memory 208212 kb
Host smart-50d9c6db-8fd9-4e3e-8af0-8905c5a27aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465736055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.465736055
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3664811510
Short name T877
Test name
Test status
Simulation time 70385139 ps
CPU time 2.44 seconds
Started Apr 04 12:46:35 PM PDT 24
Finished Apr 04 12:46:38 PM PDT 24
Peak memory 208676 kb
Host smart-19183bb1-25c3-4cd6-a135-d7eb9404e135
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664811510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3664811510
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1633645619
Short name T263
Test name
Test status
Simulation time 157626246 ps
CPU time 2.47 seconds
Started Apr 04 12:45:13 PM PDT 24
Finished Apr 04 12:45:16 PM PDT 24
Peak memory 206944 kb
Host smart-8c389422-a2b4-4892-b637-526e2f5e40c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633645619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1633645619
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4174107873
Short name T843
Test name
Test status
Simulation time 101614060 ps
CPU time 4.41 seconds
Started Apr 04 12:45:09 PM PDT 24
Finished Apr 04 12:45:14 PM PDT 24
Peak memory 208976 kb
Host smart-5c6ba63a-e3a3-492f-b7ad-f5b83fa8c113
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174107873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4174107873
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3872436107
Short name T829
Test name
Test status
Simulation time 3566963401 ps
CPU time 15.39 seconds
Started Apr 04 12:46:35 PM PDT 24
Finished Apr 04 12:46:51 PM PDT 24
Peak memory 210092 kb
Host smart-03cc4c7f-c207-49ed-92ce-cec60e2d75f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872436107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3872436107
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3152523843
Short name T561
Test name
Test status
Simulation time 44030377 ps
CPU time 2.37 seconds
Started Apr 04 12:45:10 PM PDT 24
Finished Apr 04 12:45:13 PM PDT 24
Peak memory 207124 kb
Host smart-42c2a817-e796-4c06-98d6-9b091797d8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152523843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3152523843
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2941022003
Short name T897
Test name
Test status
Simulation time 5223521867 ps
CPU time 31.33 seconds
Started Apr 04 12:46:35 PM PDT 24
Finished Apr 04 12:47:07 PM PDT 24
Peak memory 217784 kb
Host smart-729f1c34-0563-4bd1-87fb-6d218e689524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941022003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2941022003
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.686742085
Short name T472
Test name
Test status
Simulation time 56215341 ps
CPU time 1.75 seconds
Started Apr 04 12:45:11 PM PDT 24
Finished Apr 04 12:45:13 PM PDT 24
Peak memory 209992 kb
Host smart-9b9d7853-8f8a-4b2b-9881-1d61133cdaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686742085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.686742085
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2526300077
Short name T753
Test name
Test status
Simulation time 33962262 ps
CPU time 0.74 seconds
Started Apr 04 12:46:57 PM PDT 24
Finished Apr 04 12:46:59 PM PDT 24
Peak memory 206144 kb
Host smart-62e77cc4-4276-430d-bdb9-3852bab39bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526300077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2526300077
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.849140406
Short name T351
Test name
Test status
Simulation time 33865852 ps
CPU time 2.68 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 214640 kb
Host smart-b913f2fd-33af-460b-ab0a-df41266f660c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=849140406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.849140406
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3280637722
Short name T221
Test name
Test status
Simulation time 940339971 ps
CPU time 14.32 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:24 PM PDT 24
Peak memory 221164 kb
Host smart-92138769-1f96-4e63-bdb9-547ac74b1818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280637722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3280637722
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1083178115
Short name T546
Test name
Test status
Simulation time 889409633 ps
CPU time 16.44 seconds
Started Apr 04 12:47:13 PM PDT 24
Finished Apr 04 12:47:31 PM PDT 24
Peak memory 209588 kb
Host smart-4ab285b1-eb28-49af-b636-e603b1075178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083178115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1083178115
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3111537738
Short name T89
Test name
Test status
Simulation time 197330169 ps
CPU time 4.8 seconds
Started Apr 04 12:47:07 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 221464 kb
Host smart-ab0c91bc-79e1-4c62-803a-2fa1e47cdbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111537738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3111537738
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2054816803
Short name T594
Test name
Test status
Simulation time 59536887 ps
CPU time 3.87 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:04 PM PDT 24
Peak memory 208808 kb
Host smart-30a8c304-44ac-4bd5-9502-a01bb90f9356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054816803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2054816803
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2242872936
Short name T405
Test name
Test status
Simulation time 100024075 ps
CPU time 4.21 seconds
Started Apr 04 12:47:14 PM PDT 24
Finished Apr 04 12:47:19 PM PDT 24
Peak memory 210392 kb
Host smart-a3a07055-6066-4e5d-8cd1-c92e225fbfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242872936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2242872936
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1542112965
Short name T832
Test name
Test status
Simulation time 343124848 ps
CPU time 4.45 seconds
Started Apr 04 12:47:06 PM PDT 24
Finished Apr 04 12:47:10 PM PDT 24
Peak memory 214952 kb
Host smart-6d09a50d-0bdc-47af-9b7d-82c838216491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542112965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1542112965
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.193557825
Short name T86
Test name
Test status
Simulation time 173883402 ps
CPU time 2.08 seconds
Started Apr 04 12:47:14 PM PDT 24
Finished Apr 04 12:47:17 PM PDT 24
Peak memory 206912 kb
Host smart-1f14f42e-a272-4d48-939c-799ea6600ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193557825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.193557825
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1592359066
Short name T177
Test name
Test status
Simulation time 116712038 ps
CPU time 3 seconds
Started Apr 04 12:47:02 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 207012 kb
Host smart-a1a34134-894f-4827-a987-a7b4f6721286
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592359066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1592359066
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3965040714
Short name T903
Test name
Test status
Simulation time 5117129335 ps
CPU time 55.83 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:48:09 PM PDT 24
Peak memory 209428 kb
Host smart-63ed11ac-7c3b-46cf-9e2d-78c33305790c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965040714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3965040714
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2051955920
Short name T478
Test name
Test status
Simulation time 516288058 ps
CPU time 4.46 seconds
Started Apr 04 12:47:04 PM PDT 24
Finished Apr 04 12:47:08 PM PDT 24
Peak memory 208988 kb
Host smart-a2f96ddd-510d-4dca-b63c-2ea3c6135f63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051955920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2051955920
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1234650763
Short name T801
Test name
Test status
Simulation time 177718577 ps
CPU time 3.33 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 216132 kb
Host smart-7a6e359b-b4e3-4c8a-9ecd-29a7b36d99d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234650763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1234650763
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1175566751
Short name T721
Test name
Test status
Simulation time 185825467 ps
CPU time 5.98 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:07 PM PDT 24
Peak memory 206832 kb
Host smart-8f7f85a5-f2f6-4a78-a5cd-3132ec6c3cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175566751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1175566751
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.100847701
Short name T379
Test name
Test status
Simulation time 456526651 ps
CPU time 20.3 seconds
Started Apr 04 12:46:57 PM PDT 24
Finished Apr 04 12:47:17 PM PDT 24
Peak memory 223008 kb
Host smart-b16b4096-862f-401e-a9ff-e5c168855b94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100847701 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.100847701
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3302442481
Short name T571
Test name
Test status
Simulation time 918455473 ps
CPU time 23.69 seconds
Started Apr 04 12:47:00 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 214620 kb
Host smart-cb8be486-e361-4586-b135-97b0650c7ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302442481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3302442481
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1434727147
Short name T53
Test name
Test status
Simulation time 149814927 ps
CPU time 2.56 seconds
Started Apr 04 12:46:57 PM PDT 24
Finished Apr 04 12:47:00 PM PDT 24
Peak memory 210036 kb
Host smart-c9643fad-6d62-4521-8a8a-9984c57619a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434727147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1434727147
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1102829517
Short name T436
Test name
Test status
Simulation time 69880727 ps
CPU time 0.77 seconds
Started Apr 04 12:47:23 PM PDT 24
Finished Apr 04 12:47:24 PM PDT 24
Peak memory 206248 kb
Host smart-e3496a96-f7c9-4222-b544-21a92465fb04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102829517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1102829517
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3106479725
Short name T14
Test name
Test status
Simulation time 180591338 ps
CPU time 3.65 seconds
Started Apr 04 12:47:13 PM PDT 24
Finished Apr 04 12:47:17 PM PDT 24
Peak memory 214636 kb
Host smart-844671c8-059c-4120-a933-f5a96d0eefca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106479725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3106479725
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2267244202
Short name T264
Test name
Test status
Simulation time 208834512 ps
CPU time 2.81 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:47:13 PM PDT 24
Peak memory 219916 kb
Host smart-9bd57137-94aa-4b94-86a7-09de62089797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267244202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2267244202
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2755425755
Short name T191
Test name
Test status
Simulation time 80957063 ps
CPU time 3.83 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 214556 kb
Host smart-03352c0d-311a-4e59-8f1e-68f5be0bc596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755425755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2755425755
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1705005159
Short name T905
Test name
Test status
Simulation time 96459900 ps
CPU time 4.06 seconds
Started Apr 04 12:46:58 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 209148 kb
Host smart-69b32ad7-38e8-4d69-ac4d-17199826de64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705005159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1705005159
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2494369301
Short name T241
Test name
Test status
Simulation time 62505565 ps
CPU time 3.48 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:03 PM PDT 24
Peak memory 207804 kb
Host smart-0a0b4e3f-dfdd-44a0-b435-38bb56408896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494369301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2494369301
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3274428128
Short name T611
Test name
Test status
Simulation time 38994345 ps
CPU time 2.25 seconds
Started Apr 04 12:47:03 PM PDT 24
Finished Apr 04 12:47:05 PM PDT 24
Peak memory 207180 kb
Host smart-39c2a53a-19d7-445b-b505-8ce4db2c26a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274428128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3274428128
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.996433465
Short name T460
Test name
Test status
Simulation time 910417693 ps
CPU time 4.76 seconds
Started Apr 04 12:47:02 PM PDT 24
Finished Apr 04 12:47:06 PM PDT 24
Peak memory 208592 kb
Host smart-819a9833-c173-44a5-99e5-c54a8117ec3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996433465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.996433465
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3556664416
Short name T616
Test name
Test status
Simulation time 743587792 ps
CPU time 5.5 seconds
Started Apr 04 12:46:58 PM PDT 24
Finished Apr 04 12:47:04 PM PDT 24
Peak memory 209144 kb
Host smart-fe90283c-6825-4a98-8539-3eb54e597961
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556664416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3556664416
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3710615482
Short name T403
Test name
Test status
Simulation time 151636659 ps
CPU time 2.66 seconds
Started Apr 04 12:46:59 PM PDT 24
Finished Apr 04 12:47:02 PM PDT 24
Peak memory 206916 kb
Host smart-0e72f8cf-508e-4c2c-b14f-b4e11dbc8f63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710615482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3710615482
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2092937854
Short name T488
Test name
Test status
Simulation time 105823475 ps
CPU time 3.67 seconds
Started Apr 04 12:47:04 PM PDT 24
Finished Apr 04 12:47:07 PM PDT 24
Peak memory 209948 kb
Host smart-ed3baa90-77f3-47f7-afb0-b12f973068b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092937854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2092937854
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.207821885
Short name T658
Test name
Test status
Simulation time 122684358 ps
CPU time 2.75 seconds
Started Apr 04 12:46:58 PM PDT 24
Finished Apr 04 12:47:02 PM PDT 24
Peak memory 208104 kb
Host smart-31edc05a-1da4-4a34-aa99-bc67168de237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207821885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.207821885
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.59334422
Short name T500
Test name
Test status
Simulation time 234135015 ps
CPU time 8.84 seconds
Started Apr 04 12:47:16 PM PDT 24
Finished Apr 04 12:47:26 PM PDT 24
Peak memory 217232 kb
Host smart-509f9d32-4140-4f7e-8724-7b4a93a978a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59334422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.59334422
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1098875111
Short name T822
Test name
Test status
Simulation time 105536092 ps
CPU time 7.71 seconds
Started Apr 04 12:47:03 PM PDT 24
Finished Apr 04 12:47:11 PM PDT 24
Peak memory 220412 kb
Host smart-07372981-f1a4-4efc-848c-982c3b0075ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098875111 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1098875111
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.149457989
Short name T639
Test name
Test status
Simulation time 738341583 ps
CPU time 20.3 seconds
Started Apr 04 12:46:58 PM PDT 24
Finished Apr 04 12:47:18 PM PDT 24
Peak memory 218672 kb
Host smart-6358e43c-b5bb-4aa7-a367-62083a6e91e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149457989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.149457989
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2470562214
Short name T845
Test name
Test status
Simulation time 31259157 ps
CPU time 1.87 seconds
Started Apr 04 12:47:08 PM PDT 24
Finished Apr 04 12:47:10 PM PDT 24
Peak memory 209804 kb
Host smart-efe8942c-d6fd-41da-894f-9ed9f6ab9a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470562214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2470562214
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2265403513
Short name T607
Test name
Test status
Simulation time 13947526 ps
CPU time 0.76 seconds
Started Apr 04 12:47:08 PM PDT 24
Finished Apr 04 12:47:09 PM PDT 24
Peak memory 206208 kb
Host smart-fc78d185-fbe3-48a5-a01e-0c4cdb9d9488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265403513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2265403513
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1863780264
Short name T276
Test name
Test status
Simulation time 100271517 ps
CPU time 5.93 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:42 PM PDT 24
Peak memory 216280 kb
Host smart-9597d01e-53fe-42b3-861a-096b1f03396d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863780264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1863780264
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3756186925
Short name T39
Test name
Test status
Simulation time 1708997209 ps
CPU time 9.38 seconds
Started Apr 04 12:47:04 PM PDT 24
Finished Apr 04 12:47:14 PM PDT 24
Peak memory 218628 kb
Host smart-a79d9e49-1312-402f-a223-481aa193a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756186925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3756186925
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2010944476
Short name T68
Test name
Test status
Simulation time 110598294 ps
CPU time 2.12 seconds
Started Apr 04 12:47:18 PM PDT 24
Finished Apr 04 12:47:21 PM PDT 24
Peak memory 207120 kb
Host smart-18165fa9-d648-4370-96ee-1b5b65779303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010944476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2010944476
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.75775332
Short name T91
Test name
Test status
Simulation time 360944356 ps
CPU time 4.6 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:14 PM PDT 24
Peak memory 219340 kb
Host smart-62620b95-3baa-4fbe-967b-b144ae279fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75775332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.75775332
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.143813161
Short name T212
Test name
Test status
Simulation time 215460257 ps
CPU time 7.2 seconds
Started Apr 04 12:47:13 PM PDT 24
Finished Apr 04 12:47:22 PM PDT 24
Peak memory 222740 kb
Host smart-a02ea97f-6694-444b-bc1a-6426ceb3358a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143813161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.143813161
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4237147072
Short name T228
Test name
Test status
Simulation time 1288855969 ps
CPU time 5.42 seconds
Started Apr 04 12:47:16 PM PDT 24
Finished Apr 04 12:47:22 PM PDT 24
Peak memory 220096 kb
Host smart-f0b4756e-e244-4c99-99c8-26a07d69d0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237147072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4237147072
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1609427987
Short name T849
Test name
Test status
Simulation time 332335511 ps
CPU time 8.62 seconds
Started Apr 04 12:47:14 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 209056 kb
Host smart-b65fe61f-3b98-40b6-9667-dba95546d251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609427987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1609427987
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.314687058
Short name T749
Test name
Test status
Simulation time 8838350410 ps
CPU time 47.4 seconds
Started Apr 04 12:47:11 PM PDT 24
Finished Apr 04 12:47:59 PM PDT 24
Peak memory 208348 kb
Host smart-55c443fc-77c5-4074-a14a-8add5ddcf1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314687058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.314687058
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4279358686
Short name T820
Test name
Test status
Simulation time 183239168 ps
CPU time 5.11 seconds
Started Apr 04 12:47:07 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 208432 kb
Host smart-387e4fa9-d4f7-43ea-ada8-fab4e04db88a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279358686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4279358686
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1192313717
Short name T881
Test name
Test status
Simulation time 80708264 ps
CPU time 3.05 seconds
Started Apr 04 12:47:17 PM PDT 24
Finished Apr 04 12:47:20 PM PDT 24
Peak memory 208808 kb
Host smart-178c4f61-e47d-4391-86c9-7b9352b5a70d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192313717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1192313717
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3334730715
Short name T577
Test name
Test status
Simulation time 160530280 ps
CPU time 5.8 seconds
Started Apr 04 12:47:13 PM PDT 24
Finished Apr 04 12:47:20 PM PDT 24
Peak memory 207108 kb
Host smart-e0377695-e292-4aa1-8edc-be3af3b9d1bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334730715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3334730715
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.613029787
Short name T827
Test name
Test status
Simulation time 484722179 ps
CPU time 2.22 seconds
Started Apr 04 12:47:24 PM PDT 24
Finished Apr 04 12:47:27 PM PDT 24
Peak memory 214540 kb
Host smart-af76742b-2f20-428b-8767-0d23789791ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613029787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.613029787
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2139587203
Short name T640
Test name
Test status
Simulation time 59718390 ps
CPU time 2.84 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:47:13 PM PDT 24
Peak memory 207012 kb
Host smart-02512596-80c3-428a-a0c7-ba33164da359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139587203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2139587203
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1149922967
Short name T624
Test name
Test status
Simulation time 3305788983 ps
CPU time 22.5 seconds
Started Apr 04 12:47:31 PM PDT 24
Finished Apr 04 12:47:54 PM PDT 24
Peak memory 214712 kb
Host smart-eca63f9d-edf3-4e07-83ff-635542d7d96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149922967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1149922967
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1186014197
Short name T464
Test name
Test status
Simulation time 70925244 ps
CPU time 2.27 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 210076 kb
Host smart-9fd177d9-8143-48f7-9113-6a9be5dd8d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186014197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1186014197
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1929432091
Short name T559
Test name
Test status
Simulation time 10894790 ps
CPU time 0.82 seconds
Started Apr 04 12:47:22 PM PDT 24
Finished Apr 04 12:47:22 PM PDT 24
Peak memory 206240 kb
Host smart-ca500213-5dad-4376-9907-d710cdffa65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929432091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1929432091
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1911654075
Short name T833
Test name
Test status
Simulation time 133019800 ps
CPU time 2.7 seconds
Started Apr 04 12:47:05 PM PDT 24
Finished Apr 04 12:47:08 PM PDT 24
Peak memory 214892 kb
Host smart-7a18561b-fd72-43ab-adb6-d4c513d0d2a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911654075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1911654075
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3442229629
Short name T66
Test name
Test status
Simulation time 324948739 ps
CPU time 2.29 seconds
Started Apr 04 12:47:20 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 222936 kb
Host smart-cfaa5340-8fd9-4669-9222-cb74217c39a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442229629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3442229629
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3427810743
Short name T748
Test name
Test status
Simulation time 98936369 ps
CPU time 2.37 seconds
Started Apr 04 12:47:34 PM PDT 24
Finished Apr 04 12:47:37 PM PDT 24
Peak memory 207468 kb
Host smart-b0189096-43c9-4529-8c08-87fc5d321982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427810743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3427810743
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.501416186
Short name T338
Test name
Test status
Simulation time 53405597 ps
CPU time 3.41 seconds
Started Apr 04 12:47:19 PM PDT 24
Finished Apr 04 12:47:24 PM PDT 24
Peak memory 211160 kb
Host smart-a50efc20-33da-4ac8-a0fe-ca3025646aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501416186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.501416186
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4036320289
Short name T234
Test name
Test status
Simulation time 174024052 ps
CPU time 8.42 seconds
Started Apr 04 12:47:32 PM PDT 24
Finished Apr 04 12:47:40 PM PDT 24
Peak memory 220936 kb
Host smart-d6f0bb2a-4890-4292-9012-ed2eefbeb470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036320289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4036320289
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3128372667
Short name T311
Test name
Test status
Simulation time 370098648 ps
CPU time 4.54 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:47:16 PM PDT 24
Peak memory 207636 kb
Host smart-8cf9410d-77fd-4d2d-9463-b66caaa318fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128372667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3128372667
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1114654285
Short name T272
Test name
Test status
Simulation time 430217550 ps
CPU time 5.54 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:14 PM PDT 24
Peak memory 208928 kb
Host smart-ebc38058-e9b2-41ff-8e8f-3862af2b399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114654285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1114654285
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2015554695
Short name T655
Test name
Test status
Simulation time 73960208 ps
CPU time 3.86 seconds
Started Apr 04 12:47:13 PM PDT 24
Finished Apr 04 12:47:18 PM PDT 24
Peak memory 208700 kb
Host smart-72d17ad0-9477-4b62-8e46-58188d7393f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015554695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2015554695
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.538906695
Short name T440
Test name
Test status
Simulation time 82233912 ps
CPU time 2.14 seconds
Started Apr 04 12:47:04 PM PDT 24
Finished Apr 04 12:47:06 PM PDT 24
Peak memory 209152 kb
Host smart-bb8e68ae-0e65-494b-ae84-06df823e203f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538906695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.538906695
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1653876421
Short name T746
Test name
Test status
Simulation time 222495771 ps
CPU time 2.9 seconds
Started Apr 04 12:47:16 PM PDT 24
Finished Apr 04 12:47:20 PM PDT 24
Peak memory 207104 kb
Host smart-6d40e1aa-5a84-40a2-994a-bd1eacf3cbb1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653876421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1653876421
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3643849204
Short name T618
Test name
Test status
Simulation time 126729376 ps
CPU time 2.24 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 220684 kb
Host smart-b404cebd-31d9-4c5f-8a9b-9fd469a7a816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643849204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3643849204
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.952602217
Short name T750
Test name
Test status
Simulation time 97228879 ps
CPU time 4.23 seconds
Started Apr 04 12:47:14 PM PDT 24
Finished Apr 04 12:47:19 PM PDT 24
Peak memory 206800 kb
Host smart-07d7a75b-96fa-4eee-85a3-19cead4b4db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952602217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.952602217
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1562813282
Short name T214
Test name
Test status
Simulation time 7270490411 ps
CPU time 46.31 seconds
Started Apr 04 12:47:11 PM PDT 24
Finished Apr 04 12:47:58 PM PDT 24
Peak memory 222840 kb
Host smart-4b72186e-caa8-42e5-b307-80fbb873b7f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562813282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1562813282
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.757754400
Short name T123
Test name
Test status
Simulation time 3286202859 ps
CPU time 16.83 seconds
Started Apr 04 12:47:34 PM PDT 24
Finished Apr 04 12:47:51 PM PDT 24
Peak memory 223020 kb
Host smart-69b8afc5-cf90-4c5b-b6f5-b0407152f81d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757754400 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.757754400
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.960619764
Short name T205
Test name
Test status
Simulation time 546609475 ps
CPU time 6.9 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:47:24 PM PDT 24
Peak memory 207624 kb
Host smart-6c9cb811-07bf-49fe-9ed2-72fd7c6b10a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960619764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.960619764
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2717855526
Short name T568
Test name
Test status
Simulation time 335446599 ps
CPU time 2.75 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:12 PM PDT 24
Peak memory 210452 kb
Host smart-a367c314-fdf8-4e44-be14-87ff482210b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717855526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2717855526
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1451962316
Short name T489
Test name
Test status
Simulation time 15804369 ps
CPU time 0.75 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:47:13 PM PDT 24
Peak memory 206224 kb
Host smart-723b4396-16b6-450a-be8c-745ddaaecc95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451962316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1451962316
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4169507800
Short name T419
Test name
Test status
Simulation time 205154225 ps
CPU time 4.02 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:40 PM PDT 24
Peak memory 214632 kb
Host smart-6b286f70-f4ef-4567-befb-9283c9969afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169507800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4169507800
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2719030757
Short name T411
Test name
Test status
Simulation time 74619934 ps
CPU time 2.25 seconds
Started Apr 04 12:47:13 PM PDT 24
Finished Apr 04 12:47:17 PM PDT 24
Peak memory 214588 kb
Host smart-4f9bb0c0-4c83-496b-9d8c-a25859ebe1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719030757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2719030757
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3425695509
Short name T368
Test name
Test status
Simulation time 76886031 ps
CPU time 3.55 seconds
Started Apr 04 12:47:31 PM PDT 24
Finished Apr 04 12:47:35 PM PDT 24
Peak memory 209228 kb
Host smart-8bfe9a00-fec7-4f51-829f-63d4afb0fccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425695509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3425695509
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2068640959
Short name T268
Test name
Test status
Simulation time 2067681543 ps
CPU time 54.92 seconds
Started Apr 04 12:47:21 PM PDT 24
Finished Apr 04 12:48:17 PM PDT 24
Peak memory 222628 kb
Host smart-7ac3c9f3-1d76-4a78-9015-54aac07c022d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068640959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2068640959
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3267911378
Short name T49
Test name
Test status
Simulation time 132117244 ps
CPU time 4.25 seconds
Started Apr 04 12:47:05 PM PDT 24
Finished Apr 04 12:47:10 PM PDT 24
Peak memory 214604 kb
Host smart-ed4de922-e9d4-4f56-91b2-68c650311000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267911378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3267911378
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.943473402
Short name T576
Test name
Test status
Simulation time 320505767 ps
CPU time 7.99 seconds
Started Apr 04 12:47:21 PM PDT 24
Finished Apr 04 12:47:30 PM PDT 24
Peak memory 208944 kb
Host smart-894fda57-78e0-4721-8f50-b3e9ac3acefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943473402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.943473402
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2612955112
Short name T790
Test name
Test status
Simulation time 3276550319 ps
CPU time 21.81 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:47:32 PM PDT 24
Peak memory 208176 kb
Host smart-263c2dd2-2312-4862-81b5-bbaf8d292443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612955112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2612955112
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3509816378
Short name T499
Test name
Test status
Simulation time 250021629 ps
CPU time 3.06 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:47:14 PM PDT 24
Peak memory 208172 kb
Host smart-695bec97-2608-444c-a5f9-30b788aeebbc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509816378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3509816378
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.4137207835
Short name T739
Test name
Test status
Simulation time 111753255 ps
CPU time 1.87 seconds
Started Apr 04 12:47:11 PM PDT 24
Finished Apr 04 12:47:14 PM PDT 24
Peak memory 207128 kb
Host smart-dde1a214-eed2-4e62-bb1f-cfb8eb3191b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137207835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.4137207835
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3086636877
Short name T441
Test name
Test status
Simulation time 226030468 ps
CPU time 3.17 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:47:13 PM PDT 24
Peak memory 208636 kb
Host smart-3cedeef5-82fa-4894-a177-a42858c75fc6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086636877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3086636877
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1604088670
Short name T848
Test name
Test status
Simulation time 87446280 ps
CPU time 3.08 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:39 PM PDT 24
Peak memory 214640 kb
Host smart-80813221-6774-4e58-bd51-8a34ebf23a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604088670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1604088670
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1933651385
Short name T425
Test name
Test status
Simulation time 981413672 ps
CPU time 21.68 seconds
Started Apr 04 12:47:09 PM PDT 24
Finished Apr 04 12:47:31 PM PDT 24
Peak memory 208460 kb
Host smart-c08a107c-118e-4444-811d-cdff9851df80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933651385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1933651385
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4002005696
Short name T517
Test name
Test status
Simulation time 5916877440 ps
CPU time 55.79 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:48:09 PM PDT 24
Peak memory 215660 kb
Host smart-6f96a16b-609e-493d-a61f-f50f59de4001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002005696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4002005696
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1924385926
Short name T119
Test name
Test status
Simulation time 502438483 ps
CPU time 16.59 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:47:28 PM PDT 24
Peak memory 223572 kb
Host smart-213e19d7-6120-44be-9177-66a4d4bcaa7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924385926 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1924385926
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1799440447
Short name T869
Test name
Test status
Simulation time 313998729 ps
CPU time 7.72 seconds
Started Apr 04 12:47:33 PM PDT 24
Finished Apr 04 12:47:41 PM PDT 24
Peak memory 208632 kb
Host smart-ded4f730-525e-4450-95d1-f377f02222ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799440447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1799440447
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1831592229
Short name T813
Test name
Test status
Simulation time 100418468 ps
CPU time 2.64 seconds
Started Apr 04 12:47:20 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 210544 kb
Host smart-4999b8d3-580a-43c9-af08-bbe8b7ecc476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831592229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1831592229
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1958096485
Short name T795
Test name
Test status
Simulation time 20297627 ps
CPU time 0.73 seconds
Started Apr 04 12:47:37 PM PDT 24
Finished Apr 04 12:47:38 PM PDT 24
Peak memory 206204 kb
Host smart-1c82162e-3dd5-4e97-8cb4-eb32ba275e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958096485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1958096485
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1526980886
Short name T736
Test name
Test status
Simulation time 140938940 ps
CPU time 5.26 seconds
Started Apr 04 12:47:17 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 210520 kb
Host smart-121df1ae-2f86-4bc9-a62c-1899d3f2531e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526980886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1526980886
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1369455712
Short name T520
Test name
Test status
Simulation time 793705644 ps
CPU time 16.62 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:47:27 PM PDT 24
Peak memory 208508 kb
Host smart-b973c6a3-61aa-4f40-85b7-44fa230dba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369455712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1369455712
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1912041467
Short name T337
Test name
Test status
Simulation time 501565689 ps
CPU time 10.97 seconds
Started Apr 04 12:47:11 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 211892 kb
Host smart-9ab210ef-0552-4069-97a0-b14667f0db13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912041467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1912041467
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1154742067
Short name T799
Test name
Test status
Simulation time 103022450 ps
CPU time 5.18 seconds
Started Apr 04 12:47:18 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 209896 kb
Host smart-1fb25c9d-1865-4f50-9155-65178ac5b99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154742067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1154742067
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1965763442
Short name T678
Test name
Test status
Simulation time 425613112 ps
CPU time 4.55 seconds
Started Apr 04 12:47:13 PM PDT 24
Finished Apr 04 12:47:19 PM PDT 24
Peak memory 210604 kb
Host smart-bb085568-680e-4e11-b23a-ba89919e6403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965763442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1965763442
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.794959089
Short name T602
Test name
Test status
Simulation time 240695575 ps
CPU time 3.29 seconds
Started Apr 04 12:47:10 PM PDT 24
Finished Apr 04 12:47:14 PM PDT 24
Peak memory 209008 kb
Host smart-103fa409-4ee4-4b9a-89a3-c92789782109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794959089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.794959089
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.67615494
Short name T846
Test name
Test status
Simulation time 216832893 ps
CPU time 2.82 seconds
Started Apr 04 12:47:31 PM PDT 24
Finished Apr 04 12:47:34 PM PDT 24
Peak memory 207036 kb
Host smart-e7d0c01a-1789-40fc-ad5b-9246d8fc7aa7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67615494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.67615494
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2437662919
Short name T864
Test name
Test status
Simulation time 1114189638 ps
CPU time 11.36 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 208304 kb
Host smart-461b0a9c-d8db-4ef9-a94d-263b6d641d0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437662919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2437662919
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3313262651
Short name T457
Test name
Test status
Simulation time 3422919001 ps
CPU time 46.58 seconds
Started Apr 04 12:47:07 PM PDT 24
Finished Apr 04 12:47:54 PM PDT 24
Peak memory 208660 kb
Host smart-bdd4094a-dc9b-46ed-b401-ae20bb2add9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313262651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3313262651
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.416081784
Short name T361
Test name
Test status
Simulation time 161169227 ps
CPU time 3.58 seconds
Started Apr 04 12:47:34 PM PDT 24
Finished Apr 04 12:47:38 PM PDT 24
Peak memory 209856 kb
Host smart-7b4a1160-c599-4040-a6d8-4693ff398f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416081784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.416081784
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.4137692030
Short name T395
Test name
Test status
Simulation time 41761844 ps
CPU time 2.31 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:47:15 PM PDT 24
Peak memory 208600 kb
Host smart-231f2d37-5840-49e4-9843-cd0de59ed566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137692030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.4137692030
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2398125877
Short name T706
Test name
Test status
Simulation time 2653162044 ps
CPU time 4.82 seconds
Started Apr 04 12:47:22 PM PDT 24
Finished Apr 04 12:47:28 PM PDT 24
Peak memory 207832 kb
Host smart-cb3fa24d-2337-456d-b082-2325702f90a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398125877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2398125877
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1302573668
Short name T504
Test name
Test status
Simulation time 101974912 ps
CPU time 2.82 seconds
Started Apr 04 12:47:18 PM PDT 24
Finished Apr 04 12:47:21 PM PDT 24
Peak memory 210640 kb
Host smart-83c76d99-1285-4b85-a36b-eda6df65fa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302573668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1302573668
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.21029580
Short name T632
Test name
Test status
Simulation time 32239978 ps
CPU time 0.77 seconds
Started Apr 04 12:47:14 PM PDT 24
Finished Apr 04 12:47:15 PM PDT 24
Peak memory 206136 kb
Host smart-f5eb97d1-5f1b-4b93-9ff5-8cc277c3a77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21029580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.21029580
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.201348369
Short name T372
Test name
Test status
Simulation time 162119163 ps
CPU time 3.33 seconds
Started Apr 04 12:47:14 PM PDT 24
Finished Apr 04 12:47:18 PM PDT 24
Peak memory 215520 kb
Host smart-e6341ac7-d3f5-4677-8e91-ec5968c0d08f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201348369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.201348369
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1805042470
Short name T26
Test name
Test status
Simulation time 180930000 ps
CPU time 4.35 seconds
Started Apr 04 12:47:17 PM PDT 24
Finished Apr 04 12:47:22 PM PDT 24
Peak memory 221992 kb
Host smart-fc27f8d2-20c9-4d12-9761-84a4785ff924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805042470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1805042470
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.339865164
Short name T818
Test name
Test status
Simulation time 278661587 ps
CPU time 4.02 seconds
Started Apr 04 12:47:18 PM PDT 24
Finished Apr 04 12:47:22 PM PDT 24
Peak memory 214552 kb
Host smart-8038cb23-d92e-4c69-9fe7-0fc37a7ee6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339865164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.339865164
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1265072791
Short name T853
Test name
Test status
Simulation time 131135347 ps
CPU time 5.42 seconds
Started Apr 04 12:47:39 PM PDT 24
Finished Apr 04 12:47:45 PM PDT 24
Peak memory 222712 kb
Host smart-2ee589c4-1b22-46fa-9225-8a1ba3976435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265072791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1265072791
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1320221587
Short name T100
Test name
Test status
Simulation time 424492892 ps
CPU time 3.84 seconds
Started Apr 04 12:47:37 PM PDT 24
Finished Apr 04 12:47:41 PM PDT 24
Peak memory 214576 kb
Host smart-56ea46e4-59d5-460f-afd4-803986434c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320221587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1320221587
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.985334435
Short name T647
Test name
Test status
Simulation time 253238602 ps
CPU time 3.15 seconds
Started Apr 04 12:47:25 PM PDT 24
Finished Apr 04 12:47:29 PM PDT 24
Peak memory 222752 kb
Host smart-ec27b161-97ed-4110-9f7c-93ed60ea94be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985334435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.985334435
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1226999260
Short name T573
Test name
Test status
Simulation time 624352533 ps
CPU time 3.53 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:47:17 PM PDT 24
Peak memory 218624 kb
Host smart-4359da65-b1e8-4614-8fe7-9126e617297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226999260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1226999260
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3072613696
Short name T209
Test name
Test status
Simulation time 21460069 ps
CPU time 1.85 seconds
Started Apr 04 12:47:33 PM PDT 24
Finished Apr 04 12:47:35 PM PDT 24
Peak memory 206436 kb
Host smart-55229d94-a7df-49fe-bc62-3dd9c5f72a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072613696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3072613696
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.142994842
Short name T780
Test name
Test status
Simulation time 326902035 ps
CPU time 5.06 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:47:18 PM PDT 24
Peak memory 208176 kb
Host smart-5eb65d2c-9cf8-4b0a-8380-6fdb880a4494
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142994842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.142994842
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1364774910
Short name T330
Test name
Test status
Simulation time 504448816 ps
CPU time 2.74 seconds
Started Apr 04 12:47:16 PM PDT 24
Finished Apr 04 12:47:20 PM PDT 24
Peak memory 206984 kb
Host smart-ac249702-ad45-4abe-8da3-f4c48457b1bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364774910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1364774910
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.4195892438
Short name T552
Test name
Test status
Simulation time 93218194 ps
CPU time 1.99 seconds
Started Apr 04 12:47:18 PM PDT 24
Finished Apr 04 12:47:21 PM PDT 24
Peak memory 208696 kb
Host smart-5abdd605-3230-4c54-be26-a607977b032f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195892438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.4195892438
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3978983087
Short name T273
Test name
Test status
Simulation time 4466588378 ps
CPU time 11.56 seconds
Started Apr 04 12:47:32 PM PDT 24
Finished Apr 04 12:47:44 PM PDT 24
Peak memory 214744 kb
Host smart-090f4114-3301-42a2-a2a3-a580f774f74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978983087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3978983087
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2176819404
Short name T470
Test name
Test status
Simulation time 39076322 ps
CPU time 2.73 seconds
Started Apr 04 12:47:17 PM PDT 24
Finished Apr 04 12:47:20 PM PDT 24
Peak memory 208548 kb
Host smart-89d60aaa-9ad7-4bef-9667-694b4acfba3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176819404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2176819404
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2349382822
Short name T329
Test name
Test status
Simulation time 402164515 ps
CPU time 16.02 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:47:29 PM PDT 24
Peak memory 216624 kb
Host smart-4e38a717-dda4-4573-9a8c-842cde3c3c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349382822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2349382822
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.33270448
Short name T24
Test name
Test status
Simulation time 201689402 ps
CPU time 4.54 seconds
Started Apr 04 12:47:28 PM PDT 24
Finished Apr 04 12:47:33 PM PDT 24
Peak memory 207576 kb
Host smart-80bf374f-d84d-4b2e-a324-21bfced6699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33270448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.33270448
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2091998912
Short name T106
Test name
Test status
Simulation time 95180352 ps
CPU time 1.26 seconds
Started Apr 04 12:47:21 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 209932 kb
Host smart-2af22cff-227f-4844-b24d-f13ec6f0226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091998912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2091998912
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2580269109
Short name T430
Test name
Test status
Simulation time 12779741 ps
CPU time 0.88 seconds
Started Apr 04 12:47:29 PM PDT 24
Finished Apr 04 12:47:30 PM PDT 24
Peak memory 206120 kb
Host smart-fe6562db-c67b-4919-9956-d5ee61b3d757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580269109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2580269109
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2364617098
Short name T422
Test name
Test status
Simulation time 104937586 ps
CPU time 2.38 seconds
Started Apr 04 12:47:15 PM PDT 24
Finished Apr 04 12:47:18 PM PDT 24
Peak memory 214508 kb
Host smart-45d24ba1-a3e2-4adb-b7c8-1806ef905cfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364617098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2364617098
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3401147150
Short name T663
Test name
Test status
Simulation time 781421440 ps
CPU time 17.44 seconds
Started Apr 04 12:47:28 PM PDT 24
Finished Apr 04 12:47:45 PM PDT 24
Peak memory 209348 kb
Host smart-98e005ea-8b70-4c66-906b-e5d96af6801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401147150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3401147150
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1249181095
Short name T341
Test name
Test status
Simulation time 3634663712 ps
CPU time 7.27 seconds
Started Apr 04 12:47:28 PM PDT 24
Finished Apr 04 12:47:35 PM PDT 24
Peak memory 214700 kb
Host smart-38cd95f0-daae-4122-89e0-a6e8ecd7c813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249181095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1249181095
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3006431805
Short name T366
Test name
Test status
Simulation time 216962070 ps
CPU time 4.98 seconds
Started Apr 04 12:47:17 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 210852 kb
Host smart-85561033-8efc-4470-b602-766947de6daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006431805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3006431805
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2296008645
Short name T549
Test name
Test status
Simulation time 407064503 ps
CPU time 4.32 seconds
Started Apr 04 12:47:20 PM PDT 24
Finished Apr 04 12:47:25 PM PDT 24
Peak memory 218128 kb
Host smart-34e7eb88-a026-494b-a553-514197c4ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296008645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2296008645
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1982724481
Short name T398
Test name
Test status
Simulation time 2368332029 ps
CPU time 14.84 seconds
Started Apr 04 12:47:24 PM PDT 24
Finished Apr 04 12:47:40 PM PDT 24
Peak memory 214640 kb
Host smart-9aa6cc61-1f36-4e91-870e-0305e628525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982724481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1982724481
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2605512032
Short name T626
Test name
Test status
Simulation time 66339804 ps
CPU time 2.73 seconds
Started Apr 04 12:47:31 PM PDT 24
Finished Apr 04 12:47:34 PM PDT 24
Peak memory 207176 kb
Host smart-5f1249f0-46d2-4380-af08-f813ca5ba146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605512032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2605512032
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1326665705
Short name T350
Test name
Test status
Simulation time 29796766 ps
CPU time 2.34 seconds
Started Apr 04 12:47:35 PM PDT 24
Finished Apr 04 12:47:37 PM PDT 24
Peak memory 209076 kb
Host smart-53a5e238-259f-44d9-b5bd-fffc76b2f7b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326665705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1326665705
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3744265267
Short name T763
Test name
Test status
Simulation time 106479383 ps
CPU time 3.44 seconds
Started Apr 04 12:47:17 PM PDT 24
Finished Apr 04 12:47:21 PM PDT 24
Peak memory 208760 kb
Host smart-027e0f59-2a07-46d3-b954-31475036880c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744265267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3744265267
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.723459934
Short name T477
Test name
Test status
Simulation time 90800860 ps
CPU time 3.77 seconds
Started Apr 04 12:47:19 PM PDT 24
Finished Apr 04 12:47:23 PM PDT 24
Peak memory 208804 kb
Host smart-d8bc6c31-2099-41c6-8cff-7d14b0b21b5f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723459934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.723459934
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2630037772
Short name T703
Test name
Test status
Simulation time 781883721 ps
CPU time 16.19 seconds
Started Apr 04 12:47:16 PM PDT 24
Finished Apr 04 12:47:33 PM PDT 24
Peak memory 214712 kb
Host smart-81958aa3-073b-4225-93d3-3bf23e56572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630037772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2630037772
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1891901232
Short name T479
Test name
Test status
Simulation time 78851023 ps
CPU time 3 seconds
Started Apr 04 12:47:12 PM PDT 24
Finished Apr 04 12:47:16 PM PDT 24
Peak memory 209108 kb
Host smart-b4929b50-7a20-417e-a589-734364b9b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891901232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1891901232
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3824286913
Short name T79
Test name
Test status
Simulation time 4714745784 ps
CPU time 35.54 seconds
Started Apr 04 12:47:20 PM PDT 24
Finished Apr 04 12:47:56 PM PDT 24
Peak memory 221816 kb
Host smart-c6cf31b8-5306-414f-a6bd-537366dd76f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824286913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3824286913
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1434918913
Short name T364
Test name
Test status
Simulation time 1112644818 ps
CPU time 13.03 seconds
Started Apr 04 12:47:19 PM PDT 24
Finished Apr 04 12:47:32 PM PDT 24
Peak memory 218408 kb
Host smart-f78bff16-dd83-4c43-88be-22cb303165ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434918913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1434918913
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3295167906
Short name T476
Test name
Test status
Simulation time 46451327 ps
CPU time 1.8 seconds
Started Apr 04 12:47:19 PM PDT 24
Finished Apr 04 12:47:21 PM PDT 24
Peak memory 210012 kb
Host smart-c60f328f-e7d4-4dd5-9788-ab6830f91ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295167906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3295167906
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2338759560
Short name T484
Test name
Test status
Simulation time 133343864 ps
CPU time 0.87 seconds
Started Apr 04 12:47:24 PM PDT 24
Finished Apr 04 12:47:25 PM PDT 24
Peak memory 206272 kb
Host smart-394a925e-47cd-4774-9a84-bcfd5fc7bd3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338759560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2338759560
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.604664038
Short name T410
Test name
Test status
Simulation time 151677154 ps
CPU time 3.71 seconds
Started Apr 04 12:47:25 PM PDT 24
Finished Apr 04 12:47:29 PM PDT 24
Peak memory 215656 kb
Host smart-fd02e9e7-28f1-4b15-b443-166700bd18b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604664038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.604664038
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.996509172
Short name T278
Test name
Test status
Simulation time 149177404 ps
CPU time 1.66 seconds
Started Apr 04 12:47:30 PM PDT 24
Finished Apr 04 12:47:32 PM PDT 24
Peak memory 209276 kb
Host smart-c95972a5-eb77-4d25-bbe6-fe7d06e384bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996509172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.996509172
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2697958521
Short name T335
Test name
Test status
Simulation time 265275564 ps
CPU time 3.14 seconds
Started Apr 04 12:47:35 PM PDT 24
Finished Apr 04 12:47:39 PM PDT 24
Peak memory 218664 kb
Host smart-e48c16ca-8602-4ddb-bc78-496c36a79162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697958521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2697958521
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1213336760
Short name T87
Test name
Test status
Simulation time 377581518 ps
CPU time 6.94 seconds
Started Apr 04 12:47:38 PM PDT 24
Finished Apr 04 12:47:45 PM PDT 24
Peak memory 214572 kb
Host smart-b492efa3-62d5-462d-bc3b-35a18756c5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213336760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1213336760
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.367180372
Short name T41
Test name
Test status
Simulation time 330494682 ps
CPU time 4.15 seconds
Started Apr 04 12:47:29 PM PDT 24
Finished Apr 04 12:47:33 PM PDT 24
Peak memory 209196 kb
Host smart-24f57f2f-ebcf-4a94-8723-931903c03a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367180372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.367180372
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1430948062
Short name T708
Test name
Test status
Simulation time 115405400 ps
CPU time 2.32 seconds
Started Apr 04 12:47:32 PM PDT 24
Finished Apr 04 12:47:34 PM PDT 24
Peak memory 209980 kb
Host smart-778744d5-5b28-4b64-a850-0e0f2ce82a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430948062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1430948062
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1475799033
Short name T523
Test name
Test status
Simulation time 125705974 ps
CPU time 2.46 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:39 PM PDT 24
Peak memory 207048 kb
Host smart-3709c2c4-9ef8-4774-a7bf-9f5702602dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475799033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1475799033
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1721937229
Short name T444
Test name
Test status
Simulation time 125942263 ps
CPU time 4.17 seconds
Started Apr 04 12:47:34 PM PDT 24
Finished Apr 04 12:47:38 PM PDT 24
Peak memory 206988 kb
Host smart-790a7b3f-55c5-49bb-9708-c57d3b6a6c50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721937229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1721937229
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1963465279
Short name T591
Test name
Test status
Simulation time 324825802 ps
CPU time 3.2 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:40 PM PDT 24
Peak memory 209268 kb
Host smart-7a0e1cb1-1412-4f54-8cc9-069133a6f96e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963465279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1963465279
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2013180948
Short name T732
Test name
Test status
Simulation time 93904899 ps
CPU time 2.17 seconds
Started Apr 04 12:47:25 PM PDT 24
Finished Apr 04 12:47:27 PM PDT 24
Peak memory 208936 kb
Host smart-436b41bd-5e26-4be9-a946-b99c616a2415
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013180948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2013180948
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3917981265
Short name T842
Test name
Test status
Simulation time 188379284 ps
CPU time 2.47 seconds
Started Apr 04 12:47:41 PM PDT 24
Finished Apr 04 12:47:43 PM PDT 24
Peak memory 207700 kb
Host smart-a248ac4c-7238-4469-bc71-f9f20c000d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917981265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3917981265
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1144350098
Short name T174
Test name
Test status
Simulation time 268875194 ps
CPU time 6.89 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:43 PM PDT 24
Peak memory 208520 kb
Host smart-7054377f-27b6-4e16-91d8-5e66191486e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144350098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1144350098
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4068924295
Short name T232
Test name
Test status
Simulation time 17995111775 ps
CPU time 47.85 seconds
Started Apr 04 12:47:28 PM PDT 24
Finished Apr 04 12:48:16 PM PDT 24
Peak memory 216792 kb
Host smart-d0fd935f-c409-45fa-b0b3-f80ccece5646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068924295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4068924295
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3152101142
Short name T572
Test name
Test status
Simulation time 1289216953 ps
CPU time 5.18 seconds
Started Apr 04 12:47:28 PM PDT 24
Finished Apr 04 12:47:34 PM PDT 24
Peak memory 209852 kb
Host smart-73336015-190d-4bdc-a0ad-14f4070f9c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152101142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3152101142
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1754825536
Short name T578
Test name
Test status
Simulation time 187319020 ps
CPU time 2.87 seconds
Started Apr 04 12:47:43 PM PDT 24
Finished Apr 04 12:47:46 PM PDT 24
Peak memory 210100 kb
Host smart-e8b11946-cace-4a39-b794-14e9994b81f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754825536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1754825536
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4127675267
Short name T689
Test name
Test status
Simulation time 13231454 ps
CPU time 0.72 seconds
Started Apr 04 12:47:39 PM PDT 24
Finished Apr 04 12:47:41 PM PDT 24
Peak memory 206216 kb
Host smart-ff7ce81e-9095-420c-b619-88bae062d359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127675267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4127675267
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.4089873887
Short name T773
Test name
Test status
Simulation time 617726369 ps
CPU time 4.98 seconds
Started Apr 04 12:47:26 PM PDT 24
Finished Apr 04 12:47:31 PM PDT 24
Peak memory 215856 kb
Host smart-01b7ed58-1edd-40f5-85d3-e25de6663a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089873887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.4089873887
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1906738242
Short name T693
Test name
Test status
Simulation time 126479850 ps
CPU time 3.04 seconds
Started Apr 04 12:47:30 PM PDT 24
Finished Apr 04 12:47:33 PM PDT 24
Peak memory 218468 kb
Host smart-b114e100-3bb7-49f7-a2f5-53b941c29c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906738242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1906738242
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3991680468
Short name T74
Test name
Test status
Simulation time 267023638 ps
CPU time 2.11 seconds
Started Apr 04 12:47:31 PM PDT 24
Finished Apr 04 12:47:33 PM PDT 24
Peak memory 208536 kb
Host smart-636e1723-8b9b-429a-8eb2-3fc3d5482542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991680468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3991680468
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1433020337
Short name T646
Test name
Test status
Simulation time 899476801 ps
CPU time 3.49 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:39 PM PDT 24
Peak memory 219788 kb
Host smart-d99279ec-429c-42ae-899a-74175631335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433020337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1433020337
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1067963344
Short name T629
Test name
Test status
Simulation time 143965942 ps
CPU time 2.82 seconds
Started Apr 04 12:47:34 PM PDT 24
Finished Apr 04 12:47:37 PM PDT 24
Peak memory 216892 kb
Host smart-0297403c-fdec-4d06-b2ce-b7a7517e135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067963344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1067963344
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3943740179
Short name T631
Test name
Test status
Simulation time 3807155662 ps
CPU time 25.89 seconds
Started Apr 04 12:47:38 PM PDT 24
Finished Apr 04 12:48:04 PM PDT 24
Peak memory 209880 kb
Host smart-116488aa-78a4-4ff4-bc5b-f32ba717d4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943740179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3943740179
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.848356123
Short name T585
Test name
Test status
Simulation time 58581256 ps
CPU time 2.95 seconds
Started Apr 04 12:47:34 PM PDT 24
Finished Apr 04 12:47:38 PM PDT 24
Peak memory 207884 kb
Host smart-a352f737-9af0-46a6-8e14-0105c6da85e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848356123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.848356123
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2738685006
Short name T541
Test name
Test status
Simulation time 515712540 ps
CPU time 3.62 seconds
Started Apr 04 12:47:23 PM PDT 24
Finished Apr 04 12:47:26 PM PDT 24
Peak memory 209064 kb
Host smart-a64a6eca-5736-4201-8400-36f9938740dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738685006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2738685006
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1781799789
Short name T80
Test name
Test status
Simulation time 285727055 ps
CPU time 3.29 seconds
Started Apr 04 12:47:34 PM PDT 24
Finished Apr 04 12:47:37 PM PDT 24
Peak memory 207088 kb
Host smart-c8ed2b06-4008-48c7-b6d6-4504d9f44d78
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781799789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1781799789
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3529858904
Short name T895
Test name
Test status
Simulation time 47857966 ps
CPU time 2.59 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:38 PM PDT 24
Peak memory 206980 kb
Host smart-72f5ed89-432d-4bb8-9871-96aa9ffb3227
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529858904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3529858904
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.159476409
Short name T702
Test name
Test status
Simulation time 404707543 ps
CPU time 7.13 seconds
Started Apr 04 12:47:38 PM PDT 24
Finished Apr 04 12:47:46 PM PDT 24
Peak memory 208752 kb
Host smart-50eb9291-c920-447c-9fb1-af44468f3080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159476409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.159476409
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1874560315
Short name T600
Test name
Test status
Simulation time 916019896 ps
CPU time 6.95 seconds
Started Apr 04 12:47:28 PM PDT 24
Finished Apr 04 12:47:35 PM PDT 24
Peak memory 208024 kb
Host smart-898508a0-7311-4621-837c-b43993529f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874560315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1874560315
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1386959886
Short name T892
Test name
Test status
Simulation time 4626773953 ps
CPU time 24.26 seconds
Started Apr 04 12:47:41 PM PDT 24
Finished Apr 04 12:48:06 PM PDT 24
Peak memory 216696 kb
Host smart-9c7c54a1-f6f1-46fa-8e95-aed3c31daba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386959886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1386959886
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.338509156
Short name T738
Test name
Test status
Simulation time 1402338998 ps
CPU time 9.74 seconds
Started Apr 04 12:47:44 PM PDT 24
Finished Apr 04 12:47:54 PM PDT 24
Peak memory 222880 kb
Host smart-a8af71a8-0113-4ab9-aa5c-3ad13a0c4b11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338509156 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.338509156
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.4211287735
Short name T826
Test name
Test status
Simulation time 326741467 ps
CPU time 4.03 seconds
Started Apr 04 12:47:33 PM PDT 24
Finished Apr 04 12:47:37 PM PDT 24
Peak memory 208080 kb
Host smart-4e3e881b-1588-40ec-b67b-79f9f50871cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211287735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4211287735
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1785568285
Short name T532
Test name
Test status
Simulation time 94890283 ps
CPU time 1.83 seconds
Started Apr 04 12:47:36 PM PDT 24
Finished Apr 04 12:47:38 PM PDT 24
Peak memory 210568 kb
Host smart-f81fc0cc-123d-4bcc-be61-db2a35f2d133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785568285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1785568285
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.440340191
Short name T495
Test name
Test status
Simulation time 38124826 ps
CPU time 0.86 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:21 PM PDT 24
Peak memory 206200 kb
Host smart-6f96ed9b-ad1e-4fc3-8a84-128278079f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440340191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.440340191
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3979794730
Short name T257
Test name
Test status
Simulation time 1061202364 ps
CPU time 57.55 seconds
Started Apr 04 12:45:18 PM PDT 24
Finished Apr 04 12:46:16 PM PDT 24
Peak memory 222808 kb
Host smart-276d7052-57b2-449a-b7bc-67f3a298c0d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979794730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3979794730
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1403348192
Short name T38
Test name
Test status
Simulation time 90375774 ps
CPU time 4.14 seconds
Started Apr 04 12:45:30 PM PDT 24
Finished Apr 04 12:45:34 PM PDT 24
Peak memory 214540 kb
Host smart-9f6165c9-5da1-4677-9c2d-cda6bfb06350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403348192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1403348192
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.923553721
Short name T761
Test name
Test status
Simulation time 275614285 ps
CPU time 2.49 seconds
Started Apr 04 12:45:28 PM PDT 24
Finished Apr 04 12:45:30 PM PDT 24
Peak memory 208056 kb
Host smart-3e61de1e-5422-4914-a6ce-59ecd65f9d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923553721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.923553721
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.12613398
Short name T501
Test name
Test status
Simulation time 622823080 ps
CPU time 8.32 seconds
Started Apr 04 12:45:18 PM PDT 24
Finished Apr 04 12:45:27 PM PDT 24
Peak memory 209764 kb
Host smart-0ca986a4-ef59-4cc6-a6bd-b183f48455b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12613398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.12613398
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1961412032
Short name T588
Test name
Test status
Simulation time 143932537 ps
CPU time 4.91 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:45:37 PM PDT 24
Peak memory 214500 kb
Host smart-f2edf057-52e2-4ebd-8f4d-45bca74f0653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961412032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1961412032
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1705509782
Short name T685
Test name
Test status
Simulation time 58149905 ps
CPU time 3.46 seconds
Started Apr 04 12:45:27 PM PDT 24
Finished Apr 04 12:45:31 PM PDT 24
Peak memory 214660 kb
Host smart-ffe856cd-239a-4710-8c6b-c1a22428eb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705509782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1705509782
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1115809130
Short name T676
Test name
Test status
Simulation time 468291712 ps
CPU time 3.7 seconds
Started Apr 04 12:45:26 PM PDT 24
Finished Apr 04 12:45:30 PM PDT 24
Peak memory 207360 kb
Host smart-7517acec-a146-49af-a18e-a7f442c8835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115809130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1115809130
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3484140894
Short name T456
Test name
Test status
Simulation time 62185346 ps
CPU time 3.24 seconds
Started Apr 04 12:45:14 PM PDT 24
Finished Apr 04 12:45:17 PM PDT 24
Peak memory 208744 kb
Host smart-ff95e425-1a22-4b71-b2fe-aeeaa46cf637
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484140894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3484140894
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.646603343
Short name T609
Test name
Test status
Simulation time 204447313 ps
CPU time 2.81 seconds
Started Apr 04 12:46:35 PM PDT 24
Finished Apr 04 12:46:38 PM PDT 24
Peak memory 206944 kb
Host smart-8f4450fd-6a58-4f82-8d6b-94d283e92992
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646603343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.646603343
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3953807575
Short name T558
Test name
Test status
Simulation time 317191605 ps
CPU time 3.32 seconds
Started Apr 04 12:45:19 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 206912 kb
Host smart-b957f7e9-bd93-4628-a188-4cecc462e447
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953807575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3953807575
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3121486731
Short name T722
Test name
Test status
Simulation time 266743033 ps
CPU time 1.77 seconds
Started Apr 04 12:45:28 PM PDT 24
Finished Apr 04 12:45:31 PM PDT 24
Peak memory 206800 kb
Host smart-c298f890-e3cf-4d86-8be1-587c9afc488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121486731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3121486731
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3590871556
Short name T531
Test name
Test status
Simulation time 349239603 ps
CPU time 6.72 seconds
Started Apr 04 12:45:27 PM PDT 24
Finished Apr 04 12:45:33 PM PDT 24
Peak memory 208272 kb
Host smart-1a28f8cd-ca38-40f0-ad31-3af7fd366632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590871556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3590871556
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.126132256
Short name T231
Test name
Test status
Simulation time 3423925245 ps
CPU time 38.46 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:59 PM PDT 24
Peak memory 222888 kb
Host smart-c5a779b4-10f0-4d95-a072-49782143a47e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126132256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.126132256
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2351027185
Short name T285
Test name
Test status
Simulation time 339625498 ps
CPU time 4.41 seconds
Started Apr 04 12:45:33 PM PDT 24
Finished Apr 04 12:45:38 PM PDT 24
Peak memory 210204 kb
Host smart-5e474d3f-8ba1-43e6-97ad-9ff8215dc859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351027185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2351027185
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2536797986
Short name T718
Test name
Test status
Simulation time 58320061 ps
CPU time 2.13 seconds
Started Apr 04 12:45:19 PM PDT 24
Finished Apr 04 12:45:21 PM PDT 24
Peak memory 210128 kb
Host smart-b51d71b7-2772-4161-a543-cddd9ceee11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536797986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2536797986
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2410754336
Short name T621
Test name
Test status
Simulation time 204945128 ps
CPU time 0.75 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:45:33 PM PDT 24
Peak memory 206120 kb
Host smart-c3569b00-5071-4f7e-b073-17a9f0931bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410754336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2410754336
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3096406111
Short name T69
Test name
Test status
Simulation time 1809590491 ps
CPU time 3.74 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:24 PM PDT 24
Peak memory 206912 kb
Host smart-9fff90b5-96be-4ce9-9fa3-d31c8fb7eb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096406111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3096406111
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2451349940
Short name T816
Test name
Test status
Simulation time 119904700 ps
CPU time 4.14 seconds
Started Apr 04 12:45:28 PM PDT 24
Finished Apr 04 12:45:32 PM PDT 24
Peak memory 209488 kb
Host smart-0e4d4607-38f1-461c-829c-559f1ab0a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451349940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2451349940
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1973248517
Short name T217
Test name
Test status
Simulation time 307174364 ps
CPU time 8.26 seconds
Started Apr 04 12:45:28 PM PDT 24
Finished Apr 04 12:45:37 PM PDT 24
Peak memory 214508 kb
Host smart-0e01aec2-c817-44d2-a939-918a2ccefffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973248517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1973248517
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.613398876
Short name T653
Test name
Test status
Simulation time 2011582741 ps
CPU time 38.86 seconds
Started Apr 04 12:45:25 PM PDT 24
Finished Apr 04 12:46:04 PM PDT 24
Peak memory 210116 kb
Host smart-ce991361-d002-406f-8ee6-1ac5f9179633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613398876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.613398876
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2330996805
Short name T202
Test name
Test status
Simulation time 160828180 ps
CPU time 2.79 seconds
Started Apr 04 12:45:22 PM PDT 24
Finished Apr 04 12:45:24 PM PDT 24
Peak memory 208872 kb
Host smart-360beedf-5089-4c3f-9871-a83d461a8846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330996805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2330996805
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3270050164
Short name T650
Test name
Test status
Simulation time 51895056 ps
CPU time 2.79 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 207164 kb
Host smart-da600a8f-2392-4a67-a04d-95a6902eae94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270050164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3270050164
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1535637364
Short name T796
Test name
Test status
Simulation time 112603586 ps
CPU time 3.85 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:24 PM PDT 24
Peak memory 207056 kb
Host smart-cfcd178e-e124-4de6-84af-c5ce41da8b9e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535637364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1535637364
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1524481855
Short name T603
Test name
Test status
Simulation time 1320706837 ps
CPU time 5.03 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:25 PM PDT 24
Peak memory 208952 kb
Host smart-f8748a15-dde4-4b69-ae39-fc59a91bad5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524481855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1524481855
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2789540532
Short name T675
Test name
Test status
Simulation time 303543391 ps
CPU time 3.12 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 214524 kb
Host smart-32e4ea2d-b821-456f-ba24-8f17886ba99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789540532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2789540532
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.4196569872
Short name T446
Test name
Test status
Simulation time 350254646 ps
CPU time 3.21 seconds
Started Apr 04 12:45:18 PM PDT 24
Finished Apr 04 12:45:21 PM PDT 24
Peak memory 207444 kb
Host smart-9cfdf664-520d-42a2-98ff-d7b62ab8a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196569872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.4196569872
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1772499673
Short name T122
Test name
Test status
Simulation time 285353240 ps
CPU time 9.31 seconds
Started Apr 04 12:45:24 PM PDT 24
Finished Apr 04 12:45:33 PM PDT 24
Peak memory 222952 kb
Host smart-a66e48c4-7f3e-4553-a46a-591b9fb7d4fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772499673 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1772499673
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3448009116
Short name T770
Test name
Test status
Simulation time 322359987 ps
CPU time 7.07 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:45:39 PM PDT 24
Peak memory 208688 kb
Host smart-4026e98c-e196-45f0-b645-b01a8979e1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448009116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3448009116
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1135502704
Short name T630
Test name
Test status
Simulation time 811695759 ps
CPU time 5.02 seconds
Started Apr 04 12:45:18 PM PDT 24
Finished Apr 04 12:45:23 PM PDT 24
Peak memory 211244 kb
Host smart-0b7f75d2-4ea2-4b78-beb3-bedcfa98cfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135502704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1135502704
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.473994286
Short name T782
Test name
Test status
Simulation time 54285409 ps
CPU time 1.07 seconds
Started Apr 04 12:45:19 PM PDT 24
Finished Apr 04 12:45:20 PM PDT 24
Peak memory 206416 kb
Host smart-1e2f6516-8b6d-4dbc-9b27-bb3b6a8ef336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473994286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.473994286
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1420972511
Short name T243
Test name
Test status
Simulation time 180224966 ps
CPU time 3.02 seconds
Started Apr 04 12:45:22 PM PDT 24
Finished Apr 04 12:45:25 PM PDT 24
Peak memory 214652 kb
Host smart-fd5bcf75-7b74-45ae-936f-1e4bcf29b633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420972511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1420972511
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2517741787
Short name T27
Test name
Test status
Simulation time 164331634 ps
CPU time 2.34 seconds
Started Apr 04 12:45:33 PM PDT 24
Finished Apr 04 12:45:36 PM PDT 24
Peak memory 221792 kb
Host smart-a1557280-5ca5-4053-82cf-187b907cf5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517741787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2517741787
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2787571517
Short name T526
Test name
Test status
Simulation time 55386061 ps
CPU time 2.88 seconds
Started Apr 04 12:45:29 PM PDT 24
Finished Apr 04 12:45:32 PM PDT 24
Peak memory 214676 kb
Host smart-fede528e-a273-4ac1-b38d-33a3dbe59e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787571517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2787571517
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.480757111
Short name T744
Test name
Test status
Simulation time 102162440 ps
CPU time 4.34 seconds
Started Apr 04 12:45:30 PM PDT 24
Finished Apr 04 12:45:35 PM PDT 24
Peak memory 214648 kb
Host smart-562eb0a2-8495-4d14-a732-e433903bf21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480757111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.480757111
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3103979285
Short name T127
Test name
Test status
Simulation time 174721072 ps
CPU time 4.37 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:25 PM PDT 24
Peak memory 219416 kb
Host smart-99ebfeb0-8ad5-41a2-9653-cad1be2bd784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103979285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3103979285
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.688519054
Short name T258
Test name
Test status
Simulation time 2689408116 ps
CPU time 8.44 seconds
Started Apr 04 12:45:22 PM PDT 24
Finished Apr 04 12:45:31 PM PDT 24
Peak memory 207620 kb
Host smart-85af83ef-0e6a-4eaf-89e0-d7c7fbb13f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688519054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.688519054
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.717369381
Short name T448
Test name
Test status
Simulation time 58426710 ps
CPU time 2.95 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:45:35 PM PDT 24
Peak memory 208756 kb
Host smart-81df23d3-ab02-47b7-aabd-5a3c744ae494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717369381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.717369381
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2415383927
Short name T461
Test name
Test status
Simulation time 111009900 ps
CPU time 1.98 seconds
Started Apr 04 12:45:25 PM PDT 24
Finished Apr 04 12:45:27 PM PDT 24
Peak memory 208920 kb
Host smart-a07809e0-ed94-4d98-9596-40ed14642d7e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415383927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2415383927
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1187081035
Short name T537
Test name
Test status
Simulation time 334737865 ps
CPU time 3.38 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:45:36 PM PDT 24
Peak memory 207024 kb
Host smart-47f26129-31a5-449a-83bc-fdb30d505ce1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187081035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1187081035
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1360429078
Short name T492
Test name
Test status
Simulation time 105333752 ps
CPU time 2.38 seconds
Started Apr 04 12:45:31 PM PDT 24
Finished Apr 04 12:45:33 PM PDT 24
Peak memory 209072 kb
Host smart-23c37060-6edc-4306-8eb7-84db0837e800
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360429078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1360429078
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2843267573
Short name T548
Test name
Test status
Simulation time 137537153 ps
CPU time 3.58 seconds
Started Apr 04 12:45:18 PM PDT 24
Finished Apr 04 12:45:22 PM PDT 24
Peak memory 209984 kb
Host smart-b47dd205-3ef1-417b-a6ea-d6444a0a4866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843267573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2843267573
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3034130018
Short name T579
Test name
Test status
Simulation time 173506028 ps
CPU time 5.18 seconds
Started Apr 04 12:45:31 PM PDT 24
Finished Apr 04 12:45:36 PM PDT 24
Peak memory 206920 kb
Host smart-6429ae6b-6541-479e-862c-bf40afd4b230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034130018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3034130018
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.177098244
Short name T77
Test name
Test status
Simulation time 3690904190 ps
CPU time 36.25 seconds
Started Apr 04 12:45:30 PM PDT 24
Finished Apr 04 12:46:06 PM PDT 24
Peak memory 216560 kb
Host smart-4aa04c1c-b5e9-4e37-917b-713574b1560f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177098244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.177098244
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3148327845
Short name T695
Test name
Test status
Simulation time 1224472807 ps
CPU time 4.35 seconds
Started Apr 04 12:45:16 PM PDT 24
Finished Apr 04 12:45:22 PM PDT 24
Peak memory 209368 kb
Host smart-ebccf6ea-61c8-4a6b-844f-6dd56b8bc4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148327845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3148327845
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1600065441
Short name T828
Test name
Test status
Simulation time 54430782 ps
CPU time 3.07 seconds
Started Apr 04 12:45:19 PM PDT 24
Finished Apr 04 12:45:22 PM PDT 24
Peak memory 210536 kb
Host smart-33bcd11b-122d-4721-9b4d-14b821fd2714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600065441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1600065441
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2620297565
Short name T497
Test name
Test status
Simulation time 42966572 ps
CPU time 0.9 seconds
Started Apr 04 12:45:33 PM PDT 24
Finished Apr 04 12:45:34 PM PDT 24
Peak memory 206252 kb
Host smart-1741768a-cc66-437a-aea0-cf2915eec8ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620297565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2620297565
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2167279921
Short name T279
Test name
Test status
Simulation time 37329251 ps
CPU time 2.9 seconds
Started Apr 04 12:45:22 PM PDT 24
Finished Apr 04 12:45:25 PM PDT 24
Peak memory 215652 kb
Host smart-37116ca3-6920-4139-b889-bc168897a068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167279921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2167279921
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3012716811
Short name T65
Test name
Test status
Simulation time 210385381 ps
CPU time 3.94 seconds
Started Apr 04 12:45:37 PM PDT 24
Finished Apr 04 12:45:41 PM PDT 24
Peak memory 209640 kb
Host smart-99258804-9a77-46c9-a9a2-1e90e0603ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012716811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3012716811
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4053927480
Short name T265
Test name
Test status
Simulation time 434129502 ps
CPU time 5.29 seconds
Started Apr 04 12:45:31 PM PDT 24
Finished Apr 04 12:45:37 PM PDT 24
Peak memory 214564 kb
Host smart-15ff4199-2e44-4fc5-93ef-f2c50989e615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053927480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4053927480
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2027495636
Short name T617
Test name
Test status
Simulation time 78972862 ps
CPU time 4.62 seconds
Started Apr 04 12:45:20 PM PDT 24
Finished Apr 04 12:45:25 PM PDT 24
Peak memory 214592 kb
Host smart-c7926d8b-c03b-4c18-b30d-0f19ff09789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027495636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2027495636
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2764811007
Short name T244
Test name
Test status
Simulation time 58720931 ps
CPU time 2.32 seconds
Started Apr 04 12:45:28 PM PDT 24
Finished Apr 04 12:45:31 PM PDT 24
Peak memory 207548 kb
Host smart-c5b97f88-a994-4140-b265-3824f28e4381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764811007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2764811007
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1137928038
Short name T787
Test name
Test status
Simulation time 89834620 ps
CPU time 4.35 seconds
Started Apr 04 12:45:28 PM PDT 24
Finished Apr 04 12:45:33 PM PDT 24
Peak memory 219496 kb
Host smart-3b04733d-7e19-400a-800b-d54ca87e4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137928038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1137928038
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2246303968
Short name T737
Test name
Test status
Simulation time 159412480 ps
CPU time 7.25 seconds
Started Apr 04 12:45:22 PM PDT 24
Finished Apr 04 12:45:30 PM PDT 24
Peak memory 210592 kb
Host smart-1b9dd669-c4a7-4f41-b814-06bbb0c0098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246303968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2246303968
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1067332208
Short name T175
Test name
Test status
Simulation time 365372924 ps
CPU time 4.91 seconds
Started Apr 04 12:45:23 PM PDT 24
Finished Apr 04 12:45:28 PM PDT 24
Peak memory 208732 kb
Host smart-4c17c248-f08d-4432-98cd-a784c0089a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067332208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1067332208
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.411240473
Short name T524
Test name
Test status
Simulation time 211298074 ps
CPU time 2.99 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:45:35 PM PDT 24
Peak memory 206964 kb
Host smart-e88a6f3a-3dbe-4933-86ad-7a575ec02a6c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411240473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.411240473
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.92961744
Short name T779
Test name
Test status
Simulation time 254257343 ps
CPU time 3.24 seconds
Started Apr 04 12:45:21 PM PDT 24
Finished Apr 04 12:45:24 PM PDT 24
Peak memory 207108 kb
Host smart-e94eaa0f-e7ed-4462-bc15-61082804cf82
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92961744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.92961744
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1933317828
Short name T4
Test name
Test status
Simulation time 61656387 ps
CPU time 3.07 seconds
Started Apr 04 12:45:18 PM PDT 24
Finished Apr 04 12:45:21 PM PDT 24
Peak memory 208860 kb
Host smart-7e1bbde8-cd91-4a1a-b21b-58187308a65c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933317828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1933317828
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1803712995
Short name T213
Test name
Test status
Simulation time 65525236 ps
CPU time 2.07 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:45:35 PM PDT 24
Peak memory 214560 kb
Host smart-fa6b507a-5969-4875-9856-273518b1a75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803712995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1803712995
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3634715717
Short name T710
Test name
Test status
Simulation time 51030112 ps
CPU time 2.75 seconds
Started Apr 04 12:45:23 PM PDT 24
Finished Apr 04 12:45:26 PM PDT 24
Peak memory 206820 kb
Host smart-a4f0796b-95b0-42e1-b5df-35f07051d6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634715717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3634715717
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3872791997
Short name T508
Test name
Test status
Simulation time 382335533 ps
CPU time 15.91 seconds
Started Apr 04 12:45:33 PM PDT 24
Finished Apr 04 12:45:49 PM PDT 24
Peak memory 221524 kb
Host smart-856e28b4-0be8-41c8-9edf-c59112ef09b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872791997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3872791997
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1799847088
Short name T505
Test name
Test status
Simulation time 107287987 ps
CPU time 5.34 seconds
Started Apr 04 12:45:27 PM PDT 24
Finished Apr 04 12:45:32 PM PDT 24
Peak memory 210068 kb
Host smart-3f712cfb-2c1d-4e08-92ab-3ba6621d415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799847088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1799847088
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.666694021
Short name T390
Test name
Test status
Simulation time 66111299 ps
CPU time 2.94 seconds
Started Apr 04 12:45:36 PM PDT 24
Finished Apr 04 12:45:39 PM PDT 24
Peak memory 210392 kb
Host smart-d075fb04-2625-4d3d-8971-f25d7962e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666694021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.666694021
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.896209539
Short name T566
Test name
Test status
Simulation time 12959398 ps
CPU time 0.91 seconds
Started Apr 04 12:45:36 PM PDT 24
Finished Apr 04 12:45:37 PM PDT 24
Peak memory 206216 kb
Host smart-601553b7-6992-47df-895f-82d12c1bef91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896209539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.896209539
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1230654161
Short name T358
Test name
Test status
Simulation time 2377477590 ps
CPU time 50.02 seconds
Started Apr 04 12:45:31 PM PDT 24
Finished Apr 04 12:46:21 PM PDT 24
Peak memory 216416 kb
Host smart-5700d349-cf88-4329-8f6e-445bb6c782e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230654161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1230654161
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.21680230
Short name T220
Test name
Test status
Simulation time 2104666342 ps
CPU time 20.48 seconds
Started Apr 04 12:45:37 PM PDT 24
Finished Apr 04 12:45:57 PM PDT 24
Peak memory 223068 kb
Host smart-097ece15-e28f-4668-aa6d-226daa8ba5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21680230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.21680230
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1841203102
Short name T45
Test name
Test status
Simulation time 96905643 ps
CPU time 2.57 seconds
Started Apr 04 12:45:36 PM PDT 24
Finished Apr 04 12:45:38 PM PDT 24
Peak memory 207592 kb
Host smart-728af2d6-70f5-4391-8ba9-6eabdb86074b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841203102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1841203102
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2432625307
Short name T697
Test name
Test status
Simulation time 1721558073 ps
CPU time 5.84 seconds
Started Apr 04 12:45:31 PM PDT 24
Finished Apr 04 12:45:37 PM PDT 24
Peak memory 214620 kb
Host smart-223bf791-c7eb-4626-8415-dde6a2cc991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432625307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2432625307
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.4051080070
Short name T266
Test name
Test status
Simulation time 8925991026 ps
CPU time 106.72 seconds
Started Apr 04 12:45:37 PM PDT 24
Finished Apr 04 12:47:24 PM PDT 24
Peak memory 229884 kb
Host smart-b40a9028-a8fe-48ac-97a4-bd80fdd09c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051080070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4051080070
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2204446189
Short name T222
Test name
Test status
Simulation time 167997085 ps
CPU time 3.39 seconds
Started Apr 04 12:45:32 PM PDT 24
Finished Apr 04 12:45:36 PM PDT 24
Peak memory 215388 kb
Host smart-3055c6ca-5ab8-4613-b0aa-b5033e82a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204446189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2204446189
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2908595243
Short name T714
Test name
Test status
Simulation time 323255876 ps
CPU time 8.86 seconds
Started Apr 04 12:45:40 PM PDT 24
Finished Apr 04 12:45:49 PM PDT 24
Peak memory 209236 kb
Host smart-d8bd1ba1-2899-4a58-b7e5-429c6a33397f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908595243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2908595243
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3315136509
Short name T15
Test name
Test status
Simulation time 196187889 ps
CPU time 3.03 seconds
Started Apr 04 12:45:36 PM PDT 24
Finished Apr 04 12:45:39 PM PDT 24
Peak memory 206896 kb
Host smart-352a58e7-549a-48af-a51b-ce2517eaa0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315136509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3315136509
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2857869266
Short name T325
Test name
Test status
Simulation time 26796480 ps
CPU time 2 seconds
Started Apr 04 12:45:36 PM PDT 24
Finished Apr 04 12:45:38 PM PDT 24
Peak memory 208552 kb
Host smart-fbd9dbfa-36e5-4693-b3a2-d4c770812aed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857869266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2857869266
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1168304184
Short name T765
Test name
Test status
Simulation time 236214716 ps
CPU time 6.04 seconds
Started Apr 04 12:45:31 PM PDT 24
Finished Apr 04 12:45:37 PM PDT 24
Peak memory 208124 kb
Host smart-a7958c34-3511-4f7a-94f0-43a9ffe1363c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168304184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1168304184
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3751139969
Short name T836
Test name
Test status
Simulation time 203167031 ps
CPU time 7.19 seconds
Started Apr 04 12:45:36 PM PDT 24
Finished Apr 04 12:45:44 PM PDT 24
Peak memory 208996 kb
Host smart-b623957a-a780-4ff2-97ad-eeb412c4d564
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751139969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3751139969
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3084312078
Short name T698
Test name
Test status
Simulation time 92577676 ps
CPU time 2.4 seconds
Started Apr 04 12:45:34 PM PDT 24
Finished Apr 04 12:45:37 PM PDT 24
Peak memory 207516 kb
Host smart-2cbb778c-d437-44dd-afa2-533d71c15152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084312078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3084312078
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.788377138
Short name T614
Test name
Test status
Simulation time 388420030 ps
CPU time 5.62 seconds
Started Apr 04 12:45:43 PM PDT 24
Finished Apr 04 12:45:49 PM PDT 24
Peak memory 208608 kb
Host smart-f1a27ba8-563b-46bc-afbe-86ba20cf2309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788377138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.788377138
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.368586601
Short name T253
Test name
Test status
Simulation time 138293856648 ps
CPU time 465.41 seconds
Started Apr 04 12:45:40 PM PDT 24
Finished Apr 04 12:53:25 PM PDT 24
Peak memory 222852 kb
Host smart-18393551-b49a-4b19-a950-238c1503ab23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368586601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.368586601
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2931703443
Short name T289
Test name
Test status
Simulation time 122569757 ps
CPU time 3.74 seconds
Started Apr 04 12:45:37 PM PDT 24
Finished Apr 04 12:45:41 PM PDT 24
Peak memory 214712 kb
Host smart-76898599-d805-41c2-b483-34a53f6d3ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931703443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2931703443
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1573613850
Short name T652
Test name
Test status
Simulation time 95849252 ps
CPU time 3.37 seconds
Started Apr 04 12:45:35 PM PDT 24
Finished Apr 04 12:45:38 PM PDT 24
Peak memory 210224 kb
Host smart-a48f566c-3866-4753-95bc-e1df107fd2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573613850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1573613850
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%