Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
69.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	18	31	63.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	17	18	51.43	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	51	1			T43	1		T44	1		T45	1
auto[OpGenId]	7	1			T51	1		T53	1		T29	1
auto[OpGenSwOut]	14	1			T31	1		T237	1		T208	1
auto[OpGenHwOut]	27	1			T4	1		T5	1		T37	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1807	1			T44	1		T4	5		T114	1
auto[StInit]	87	1			T12	1		T34	1		T31	1
auto[StCreatorRootKey]	55	1			T54	1		T4	1		T55	1
auto[StOwnerIntKey]	34	1			T43	1		T45	1		T59	1
auto[StOwnerKey]	36	1			T16	1		T4	1		T63	1
auto[StDisabled]	432	1			T4	9		T114	4		T67	1
auto[StInvalid]	45	1			T35	1		T24	1		T36	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3471

1

T1

1

T2

1

T3

1

auto[1]

99

1

T43

1

T44

1

T31

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1801	1			T4	5		T114	1		T113	1
auto[StReset]	auto[1]	6	1			T44	1		T49	1		T75	1
auto[StInit]	auto[0]	31	1			T12	1		T34	1		T113	1
auto[StInit]	auto[1]	56	1			T31	1		T51	1		T52	1
auto[StCreatorRootKey]	auto[0]	36	1			T55	1		T56	1		T88	3
auto[StCreatorRootKey]	auto[1]	19	1			T54	1		T4	1		T208	1
auto[StOwnerIntKey]	auto[0]	27	1			T59	1		T60	1		T238	1
auto[StOwnerIntKey]	auto[1]	7	1			T43	1		T45	1		T66	1
auto[StOwnerKey]	auto[0]	33	1			T16	1		T63	1		T64	1
auto[StOwnerKey]	auto[1]	3	1			T4	1		T239	1		T240	1
auto[StDisabled]	auto[0]	424	1			T4	9		T114	4		T113	6
auto[StDisabled]	auto[1]	8	1			T67	1		T5	1		T72	1
auto[StInvalid]	auto[0]	45	1			T35	1		T24	1		T36	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenId]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	6	1			T44	1		T49	1		T75	1
auto[StInit]	auto[OpAdvance]	31	1			T52	1		T109	1		T66	1
auto[StInit]	auto[OpGenId]	4	1			T51	1		T53	1		T29	1
auto[StInit]	auto[OpGenSwOut]	7	1			T31	1		T237	1		T241	1
auto[StInit]	auto[OpGenHwOut]	14	1			T37	1		T242	1		T243	1
auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T54	1		T244	1		T196	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T245	1		T246	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T208	1		T73	2		T77	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	8	1			T4	1		T46	1		T247	1
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T43	1		T45	1		T66	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T248	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T249	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T250	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	2	1			T4	1		T239	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T240	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	3	1			T67	1		T251	1		T202	1
auto[StDisabled]	auto[OpGenSwOut]	2	1			T72	1		T252	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	3	1			T5	1		T143	1		T253	1