Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11173

1

T1

15

T2

7

T3

7

auto[Attestation]

8097

1

T1

15

T2

4

T3

13

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2833	1			T1	2		T2	3		T3	2
auto[Aes]	3370	1			T1	5		T2	2		T3	4
auto[Kmac]	3531	1			T1	5		T2	4		T3	5
auto[Otbn]	3441	1			T1	4		T2	1		T3	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7917	1			T1	8		T2	8		T3	8
auto[OpGenId]	6095	1			T1	14		T2	1		T3	7
auto[OpGenSwOut]	6168	1			T1	5		T2	5		T3	5
auto[OpGenHwOut]	7007	1			T1	11		T2	5		T3	8
auto[OpDisable]	128	1			T47	1		T4	3		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10352

1

T1

16

T2

8

T3

12

auto[OpDoneFail]

16963

1

T1

22

T2

11

T3

16

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5920	1			T1	1		T2	4		T3	1
auto[StInit]	4402	1			T1	6		T2	2		T3	6
auto[StCreatorRootKey]	3093	1			T1	6		T2	2		T3	1
auto[StOwnerIntKey]	2669	1			T1	6		T2	2		T3	4
auto[StOwnerKey]	2471	1			T1	2		T2	2		T3	5
auto[StDisabled]	7787	1			T1	17		T2	7		T3	11
auto[StInvalid]	973	1			T35	16		T24	20		T36	25

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	317	1			T43	1		T34	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	120	1			T18	1		T125	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	99	1			T15	1		T124	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	62	1			T221	1		T155	1		T113	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	74	1			T123	1		T4	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	230	1			T1	1		T14	1		T222	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	34	1			T35	1		T24	1		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	315	1			T2	1		T15	2		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	121	1			T23	3		T27	1		T154	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	71	1			T16	1		T222	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	53	1			T156	1		T149	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	52	1			T125	1		T64	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	213	1			T13	1		T125	1		T224	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	27	1			T24	1		T115	3		T99	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	299	1			T2	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	129	1			T2	1		T125	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T18	1		T54	2		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T27	1		T225	1		T114	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	57	1			T226	1		T227	1		T84	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	209	1			T18	2		T125	2		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	26	1			T35	1		T36	2		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	283	1			T15	2		T23	2		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	143	1			T13	1		T34	2		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T26	1		T4	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	60	1			T131	1		T221	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	64	1			T154	1		T4	2		T113	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	221	1			T3	1		T91	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	33	1			T24	1		T36	1		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	84	1			T4	8		T35	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	129	1			T18	1		T34	1		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	80	1			T228	1		T131	2		T154	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T3	1		T131	1		T154	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T4	1		T64	1		T229	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	203	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	37	1			T24	1		T36	1		T99	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	74	1			T4	3		T36	1		T88	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	126	1			T18	1		T23	1		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	76	1			T13	1		T123	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	70	1			T26	1		T228	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	61	1			T3	1		T13	1		T230	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	201	1			T14	1		T18	1		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	27	1			T24	1		T36	1		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	81	1			T4	4		T35	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	139	1			T3	1		T12	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T1	1		T18	1		T230	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	57	1			T15	1		T91	1		T125	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	64	1			T5	2		T113	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	227	1			T124	1		T26	1		T228	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	13	1			T231	1		T232	1		T233	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T4	3		T35	3		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	141	1			T14	1		T23	2		T223	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	80	1			T16	1		T27	1		T223	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T2	1		T114	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	67	1			T223	1		T154	1		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	220	1			T1	2		T15	1		T230	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	38	1			T35	2		T24	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	247	1			T2	1		T34	2		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	94	1			T125	1		T36	1		T109	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	82	1			T123	1		T224	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T230	1		T4	1		T114	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	43	1			T91	1		T27	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	162	1			T2	1		T14	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T24	1		T83	1		T120	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	376	1			T15	1		T16	1		T42	13
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	150	1			T12	1		T42	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	110	1			T2	1		T16	2		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	106	1			T1	2		T125	1		T153	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	86	1			T3	1		T123	1		T222	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	252	1			T3	2		T14	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	40	1			T24	1		T36	3		T115	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	428	1			T16	1		T23	1		T27	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	137	1			T1	2		T34	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T228	1		T4	3		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	103	1			T3	1		T222	1		T225	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	77	1			T223	1		T4	1		T114	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	296	1			T1	1		T2	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	36	1			T35	1		T24	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	394	1			T17	6		T23	1		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	123	1			T4	2		T155	1		T113	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T14	1		T17	1		T234	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	90	1			T17	1		T26	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	86	1			T223	1		T234	1		T113	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	243	1			T14	1		T17	3		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	27	1			T24	1		T115	2		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	44	1			T4	1		T36	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	96	1			T18	1		T224	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T43	1		T54	1		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	71	1			T131	1		T45	1		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T16	1		T26	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	169	1			T224	3		T47	1		T131	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	20	1			T35	1		T36	1		T99	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	66	1			T4	1		T35	2		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	109	1			T1	1		T15	1		T230	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	99	1			T43	1		T153	1		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T42	1		T230	1		T225	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	93	1			T123	1		T42	1		T153	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	278	1			T1	2		T42	3		T153	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	25	1			T36	1		T99	2		T83	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	58	1			T4	2		T35	3		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	159	1			T14	1		T23	2		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	128	1			T14	2		T27	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T1	1		T125	1		T235	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	88	1			T16	1		T125	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	281	1			T2	1		T3	3		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	30	1			T36	2		T99	3		T58	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	52	1			T35	1		T24	1		T88	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	122	1			T3	1		T17	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T47	1		T222	2		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	111	1			T1	1		T26	1		T234	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	97	1			T17	1		T228	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	292	1			T1	1		T14	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	21	1			T99	1		T236	1		T103	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	219	1			T15	1		T123	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	717	1			T1	1		T14	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	158	1			T16	1		T125	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	694	1			T2	1		T13	1		T15	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	193	1			T18	1		T54	2		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	675	1			T2	2		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	194	1			T26	1		T131	1		T221	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	697	1			T3	1		T13	1		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	188	1			T3	1		T228	1		T131	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	469	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	194	1			T3	1		T13	2		T123	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	441	1			T14	1		T18	2		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	183	1			T1	1		T15	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	472	1			T3	1		T12	1		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	198	1			T2	1		T16	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	476	1			T1	2		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	167	1			T123	1		T91	1		T224	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	544	1			T2	2		T14	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	287	1			T1	2		T2	1		T3	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	833	1			T3	2		T12	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T3	1		T228	1		T222	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	913	1			T1	3		T2	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T14	1		T17	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	809	1			T14	1		T17	9		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	184	1			T16	1		T43	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	345	1			T18	1		T26	1		T224	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	265	1			T123	1		T42	2		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	498	1			T1	3		T15	1		T42	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	274	1			T1	1		T14	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	544	1			T2	1		T3	3		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	295	1			T1	1		T17	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	505	1			T1	1		T3	1		T14	2