Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31348

1

T1

42

T2

25

T3

32

auto[1]

219

1

T1

5

T18

4

T131

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31355	1			T1	42		T2	25		T3	32
auto[134217728:268435455]	2	1			T410	1		T358	1		-	-
auto[268435456:402653183]	4	1			T155	1		T157	1		T387	1
auto[402653184:536870911]	7	1			T1	2		T154	1		T156	1
auto[536870912:671088639]	7	1			T89	1		T387	1		T411	1
auto[671088640:805306367]	6	1			T18	1		T412	2		T413	1
auto[805306368:939524095]	7	1			T292	2		T408	1		T412	2
auto[939524096:1073741823]	9	1			T89	1		T295	1		T387	1
auto[1073741824:1207959551]	8	1			T89	1		T311	1		T261	1
auto[1207959552:1342177279]	6	1			T1	1		T414	1		T276	1
auto[1342177280:1476395007]	12	1			T89	2		T387	1		T311	1
auto[1476395008:1610612735]	12	1			T155	1		T295	1		T387	1
auto[1610612736:1744830463]	10	1			T312	1		T387	1		T274	1
auto[1744830464:1879048191]	4	1			T89	1		T415	1		T321	1
auto[1879048192:2013265919]	5	1			T157	1		T274	1		T323	1
auto[2013265920:2147483647]	4	1			T321	1		T410	1		T416	1
auto[2147483648:2281701375]	5	1			T156	1		T417	1		T418	2
auto[2281701376:2415919103]	9	1			T156	1		T84	1		T321	1
auto[2415919104:2550136831]	10	1			T131	1		T155	1		T387	1
auto[2550136832:2684354559]	3	1			T292	1		T419	1		T413	1
auto[2684354560:2818572287]	7	1			T18	1		T84	1		T321	1
auto[2818572288:2952790015]	10	1			T89	1		T312	1		T292	1
auto[2952790016:3087007743]	9	1			T156	1		T292	1		T295	1
auto[3087007744:3221225471]	8	1			T1	1		T18	1		T89	1
auto[3221225472:3355443199]	5	1			T312	1		T292	1		T321	1
auto[3355443200:3489660927]	5	1			T155	1		T321	1		T276	1
auto[3489660928:3623878655]	2	1			T254	1		T418	1		-	-
auto[3623878656:3758096383]	3	1			T1	1		T413	1		T420	1
auto[3758096384:3892314111]	9	1			T155	1		T84	1		T89	1
auto[3892314112:4026531839]	6	1			T387	1		T311	1		T276	1
auto[4026531840:4160749567]	12	1			T18	1		T155	1		T157	2
auto[4160749568:4294967295]	6	1			T89	1		T387	1		T276	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31348	1			T1	42		T2	25		T3	32
auto[0:134217727]	auto[1]	7	1			T131	1		T84	2		T321	1
auto[134217728:268435455]	auto[1]	2	1			T410	1		T358	1		-	-
auto[268435456:402653183]	auto[1]	4	1			T155	1		T157	1		T387	1
auto[402653184:536870911]	auto[1]	7	1			T1	2		T154	1		T156	1
auto[536870912:671088639]	auto[1]	7	1			T89	1		T387	1		T411	1
auto[671088640:805306367]	auto[1]	6	1			T18	1		T412	2		T413	1
auto[805306368:939524095]	auto[1]	7	1			T292	2		T408	1		T412	2
auto[939524096:1073741823]	auto[1]	9	1			T89	1		T295	1		T387	1
auto[1073741824:1207959551]	auto[1]	8	1			T89	1		T311	1		T261	1
auto[1207959552:1342177279]	auto[1]	6	1			T1	1		T414	1		T276	1
auto[1342177280:1476395007]	auto[1]	12	1			T89	2		T387	1		T311	1
auto[1476395008:1610612735]	auto[1]	12	1			T155	1		T295	1		T387	1
auto[1610612736:1744830463]	auto[1]	10	1			T312	1		T387	1		T274	1
auto[1744830464:1879048191]	auto[1]	4	1			T89	1		T415	1		T321	1
auto[1879048192:2013265919]	auto[1]	5	1			T157	1		T274	1		T323	1
auto[2013265920:2147483647]	auto[1]	4	1			T321	1		T410	1		T416	1
auto[2147483648:2281701375]	auto[1]	5	1			T156	1		T417	1		T418	2
auto[2281701376:2415919103]	auto[1]	9	1			T156	1		T84	1		T321	1
auto[2415919104:2550136831]	auto[1]	10	1			T131	1		T155	1		T387	1
auto[2550136832:2684354559]	auto[1]	3	1			T292	1		T419	1		T413	1
auto[2684354560:2818572287]	auto[1]	7	1			T18	1		T84	1		T321	1
auto[2818572288:2952790015]	auto[1]	10	1			T89	1		T312	1		T292	1
auto[2952790016:3087007743]	auto[1]	9	1			T156	1		T292	1		T295	1
auto[3087007744:3221225471]	auto[1]	8	1			T1	1		T18	1		T89	1
auto[3221225472:3355443199]	auto[1]	5	1			T312	1		T292	1		T321	1
auto[3355443200:3489660927]	auto[1]	5	1			T155	1		T321	1		T276	1
auto[3489660928:3623878655]	auto[1]	2	1			T254	1		T418	1		-	-
auto[3623878656:3758096383]	auto[1]	3	1			T1	1		T413	1		T420	1
auto[3758096384:3892314111]	auto[1]	9	1			T155	1		T84	1		T89	1
auto[3892314112:4026531839]	auto[1]	6	1			T387	1		T311	1		T276	1
auto[4026531840:4160749567]	auto[1]	12	1			T18	1		T155	1		T157	2
auto[4160749568:4294967295]	auto[1]	6	1			T89	1		T387	1		T276	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2842

1

T1

5

T3

6

T14

4

auto[1]

223

1

T1

4

T18

2

T131

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T1	1		T26	1		T131	1
auto[134217728:268435455]	97	1			T26	2		T47	1		T131	1
auto[268435456:402653183]	100	1			T125	1		T47	1		T230	1
auto[402653184:536870911]	92	1			T31	1		T222	1		T155	1
auto[536870912:671088639]	83	1			T23	1		T224	1		T223	1
auto[671088640:805306367]	94	1			T14	1		T224	1		T228	1
auto[805306368:939524095]	103	1			T18	1		T4	2		T24	2
auto[939524096:1073741823]	92	1			T1	1		T44	1		T221	1
auto[1073741824:1207959551]	102	1			T47	1		T228	1		T131	1
auto[1207959552:1342177279]	89	1			T1	1		T18	2		T27	1
auto[1342177280:1476395007]	99	1			T23	1		T224	2		T255	2
auto[1476395008:1610612735]	106	1			T3	1		T16	2		T23	1
auto[1610612736:1744830463]	105	1			T1	1		T14	1		T26	1
auto[1744830464:1879048191]	76	1			T1	1		T18	1		T255	1
auto[1879048192:2013265919]	105	1			T14	1		T224	1		T45	1
auto[2013265920:2147483647]	90	1			T3	1		T221	1		T54	1
auto[2147483648:2281701375]	108	1			T26	1		T45	1		T154	1
auto[2281701376:2415919103]	110	1			T1	1		T16	1		T34	1
auto[2415919104:2550136831]	104	1			T3	3		T123	1		T4	2
auto[2550136832:2684354559]	106	1			T154	1		T4	3		T24	1
auto[2684354560:2818572287]	82	1			T123	1		T31	1		T222	1
auto[2818572288:2952790015]	110	1			T1	1		T26	1		T27	1
auto[2952790016:3087007743]	102	1			T228	1		T4	2		T48	1
auto[3087007744:3221225471]	85	1			T18	1		T43	1		T34	1
auto[3221225472:3355443199]	90	1			T27	1		T4	1		T35	1
auto[3355443200:3489660927]	87	1			T16	1		T43	1		T45	1
auto[3489660928:3623878655]	80	1			T3	1		T23	1		T47	1
auto[3623878656:3758096383]	92	1			T1	1		T154	1		T4	1
auto[3758096384:3892314111]	113	1			T18	1		T228	1		T4	1
auto[3892314112:4026531839]	96	1			T228	1		T4	1		T24	1
auto[4026531840:4160749567]	81	1			T16	1		T154	1		T4	4
auto[4160749568:4294967295]	81	1			T1	1		T14	1		T26	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	1	63	98.44	1

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[4026531840:4160749567]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	98	1			T1	1		T26	1		T131	1
auto[0:134217727]	auto[1]	7	1			T84	1		T387	2		T397	1
auto[134217728:268435455]	auto[0]	93	1			T26	2		T47	1		T131	1
auto[134217728:268435455]	auto[1]	4	1			T410	1		T254	1		T421	1
auto[268435456:402653183]	auto[0]	92	1			T125	1		T47	1		T230	1
auto[268435456:402653183]	auto[1]	8	1			T156	1		T89	3		T422	1
auto[402653184:536870911]	auto[0]	88	1			T31	1		T222	1		T155	1
auto[402653184:536870911]	auto[1]	4	1			T419	1		T421	1		T423	1
auto[536870912:671088639]	auto[0]	79	1			T23	1		T224	1		T223	1
auto[536870912:671088639]	auto[1]	4	1			T292	1		T323	1		T419	1
auto[671088640:805306367]	auto[0]	85	1			T14	1		T224	1		T228	1
auto[671088640:805306367]	auto[1]	9	1			T295	1		T387	1		T411	1
auto[805306368:939524095]	auto[0]	99	1			T18	1		T4	2		T24	2
auto[805306368:939524095]	auto[1]	4	1			T155	1		T84	1		T424	1
auto[939524096:1073741823]	auto[0]	84	1			T44	1		T221	1		T223	1
auto[939524096:1073741823]	auto[1]	8	1			T1	1		T154	1		T155	1
auto[1073741824:1207959551]	auto[0]	91	1			T47	1		T228	1		T4	1
auto[1073741824:1207959551]	auto[1]	11	1			T131	1		T157	1		T321	2
auto[1207959552:1342177279]	auto[0]	81	1			T1	1		T27	1		T228	1
auto[1207959552:1342177279]	auto[1]	8	1			T18	2		T292	1		T387	1
auto[1342177280:1476395007]	auto[0]	92	1			T23	1		T224	2		T255	2
auto[1342177280:1476395007]	auto[1]	7	1			T84	2		T411	1		T323	2
auto[1476395008:1610612735]	auto[0]	99	1			T3	1		T16	2		T23	1
auto[1476395008:1610612735]	auto[1]	7	1			T84	1		T412	1		T410	1
auto[1610612736:1744830463]	auto[0]	94	1			T14	1		T26	1		T27	1
auto[1610612736:1744830463]	auto[1]	11	1			T1	1		T154	1		T155	1
auto[1744830464:1879048191]	auto[0]	67	1			T1	1		T18	1		T255	1
auto[1744830464:1879048191]	auto[1]	9	1			T89	1		T157	1		T415	1
auto[1879048192:2013265919]	auto[0]	95	1			T14	1		T224	1		T45	1
auto[1879048192:2013265919]	auto[1]	10	1			T387	2		T397	1		T261	1
auto[2013265920:2147483647]	auto[0]	83	1			T3	1		T221	1		T54	1
auto[2013265920:2147483647]	auto[1]	7	1			T415	1		T276	1		T323	1
auto[2147483648:2281701375]	auto[0]	98	1			T26	1		T45	1		T154	1
auto[2147483648:2281701375]	auto[1]	10	1			T155	1		T84	1		T292	1
auto[2281701376:2415919103]	auto[0]	100	1			T1	1		T16	1		T34	1
auto[2281701376:2415919103]	auto[1]	10	1			T155	1		T156	1		T321	1
auto[2415919104:2550136831]	auto[0]	97	1			T3	3		T123	1		T4	2
auto[2415919104:2550136831]	auto[1]	7	1			T89	1		T321	1		T410	1
auto[2550136832:2684354559]	auto[0]	98	1			T154	1		T4	3		T24	1
auto[2550136832:2684354559]	auto[1]	8	1			T295	1		T321	1		T276	1
auto[2684354560:2818572287]	auto[0]	76	1			T123	1		T31	1		T222	1
auto[2684354560:2818572287]	auto[1]	6	1			T89	1		T411	1		T311	1
auto[2818572288:2952790015]	auto[0]	105	1			T1	1		T26	1		T27	1
auto[2818572288:2952790015]	auto[1]	5	1			T357	1		T424	1		T419	1
auto[2952790016:3087007743]	auto[0]	93	1			T228	1		T4	2		T48	1
auto[2952790016:3087007743]	auto[1]	9	1			T157	1		T411	1		T321	1
auto[3087007744:3221225471]	auto[0]	80	1			T18	1		T43	1		T34	1
auto[3087007744:3221225471]	auto[1]	5	1			T131	1		T292	1		T274	1
auto[3221225472:3355443199]	auto[0]	89	1			T27	1		T4	1		T35	1
auto[3221225472:3355443199]	auto[1]	1	1			T425	1		-	-		-	-
auto[3355443200:3489660927]	auto[0]	84	1			T16	1		T43	1		T45	1
auto[3355443200:3489660927]	auto[1]	3	1			T387	1		T426	1		T359	1
auto[3489660928:3623878655]	auto[0]	75	1			T3	1		T23	1		T47	1
auto[3489660928:3623878655]	auto[1]	5	1			T157	1		T274	1		T357	1
auto[3623878656:3758096383]	auto[0]	80	1			T154	1		T4	1		T257	1
auto[3623878656:3758096383]	auto[1]	12	1			T1	1		T155	1		T157	1
auto[3758096384:3892314111]	auto[0]	105	1			T18	1		T228	1		T4	1
auto[3758096384:3892314111]	auto[1]	8	1			T155	1		T89	1		T292	1
auto[3892314112:4026531839]	auto[0]	86	1			T228	1		T4	1		T24	1
auto[3892314112:4026531839]	auto[1]	10	1			T89	1		T157	1		T295	1
auto[4026531840:4160749567]	auto[0]	81	1			T16	1		T154	1		T4	4
auto[4160749568:4294967295]	auto[0]	75	1			T14	1		T26	1		T27	1
auto[4160749568:4294967295]	auto[1]	6	1			T1	1		T89	1		T292	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1597

1

T1

1

T3

3

T14

2

auto[1]

1665

1

T1

4

T3

3

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T43	1		T224	1		T54	1
auto[134217728:268435455]	103	1			T14	1		T16	1		T255	1
auto[268435456:402653183]	108	1			T3	1		T43	1		T26	1
auto[402653184:536870911]	110	1			T23	1		T255	1		T230	1
auto[536870912:671088639]	102	1			T16	1		T221	1		T154	1
auto[671088640:805306367]	112	1			T16	1		T223	1		T255	1
auto[805306368:939524095]	84	1			T223	1		T4	2		T67	1
auto[939524096:1073741823]	108	1			T23	1		T26	1		T44	1
auto[1073741824:1207959551]	80	1			T228	1		T222	1		T4	1
auto[1207959552:1342177279]	115	1			T26	1		T224	1		T228	1
auto[1342177280:1476395007]	120	1			T16	1		T47	1		T223	1
auto[1476395008:1610612735]	105	1			T26	1		T228	1		T223	1
auto[1610612736:1744830463]	92	1			T18	1		T27	2		T4	2
auto[1744830464:1879048191]	97	1			T26	1		T224	1		T27	1
auto[1879048192:2013265919]	99	1			T1	1		T34	1		T224	1
auto[2013265920:2147483647]	115	1			T44	1		T131	2		T4	1
auto[2147483648:2281701375]	114	1			T16	2		T43	1		T26	1
auto[2281701376:2415919103]	107	1			T14	1		T222	1		T154	1
auto[2415919104:2550136831]	101	1			T14	1		T18	1		T47	1
auto[2550136832:2684354559]	95	1			T3	1		T18	1		T44	1
auto[2684354560:2818572287]	110	1			T4	2		T35	1		T48	1
auto[2818572288:2952790015]	99	1			T18	1		T45	1		T54	1
auto[2952790016:3087007743]	109	1			T34	1		T154	1		T4	1
auto[3087007744:3221225471]	96	1			T1	1		T3	1		T14	1
auto[3221225472:3355443199]	116	1			T1	1		T3	1		T23	1
auto[3355443200:3489660927]	102	1			T26	1		T51	1		T155	1
auto[3489660928:3623878655]	95	1			T3	1		T123	1		T23	1
auto[3623878656:3758096383]	99	1			T1	1		T228	1		T31	1
auto[3758096384:3892314111]	95	1			T1	1		T26	1		T44	1
auto[3892314112:4026531839]	88	1			T3	1		T16	1		T221	1
auto[4026531840:4160749567]	95	1			T27	1		T228	1		T222	1
auto[4160749568:4294967295]	100	1			T47	1		T4	3		T53	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T114	1		T113	1		T83	1
auto[0:134217727]	auto[1]	47	1			T43	1		T224	1		T54	1
auto[134217728:268435455]	auto[0]	50	1			T14	1		T4	2		T53	1
auto[134217728:268435455]	auto[1]	53	1			T16	1		T255	1		T114	1
auto[268435456:402653183]	auto[0]	46	1			T43	1		T26	1		T47	1
auto[268435456:402653183]	auto[1]	62	1			T3	1		T4	2		T113	2
auto[402653184:536870911]	auto[0]	55	1			T23	1		T255	1		T24	1
auto[402653184:536870911]	auto[1]	55	1			T230	1		T4	2		T113	2
auto[536870912:671088639]	auto[0]	54	1			T16	1		T230	1		T4	1
auto[536870912:671088639]	auto[1]	48	1			T221	1		T154	1		T4	1
auto[671088640:805306367]	auto[0]	51	1			T16	1		T255	1		T4	1
auto[671088640:805306367]	auto[1]	61	1			T223	1		T4	1		T225	1
auto[805306368:939524095]	auto[0]	46	1			T4	2		T67	1		T157	1
auto[805306368:939524095]	auto[1]	38	1			T223	1		T7	1		T85	1
auto[939524096:1073741823]	auto[0]	49	1			T44	1		T31	1		T24	2
auto[939524096:1073741823]	auto[1]	59	1			T23	1		T26	1		T228	1
auto[1073741824:1207959551]	auto[0]	34	1			T222	1		T4	1		T35	2
auto[1073741824:1207959551]	auto[1]	46	1			T228	1		T208	1		T97	1
auto[1207959552:1342177279]	auto[0]	60	1			T224	1		T228	1		T45	1
auto[1207959552:1342177279]	auto[1]	55	1			T26	1		T222	1		T225	1
auto[1342177280:1476395007]	auto[0]	58	1			T16	1		T47	1		T154	1
auto[1342177280:1476395007]	auto[1]	62	1			T223	1		T255	1		T4	3
auto[1476395008:1610612735]	auto[0]	47	1			T26	1		T228	1		T4	1
auto[1476395008:1610612735]	auto[1]	58	1			T223	1		T4	1		T113	1
auto[1610612736:1744830463]	auto[0]	51	1			T18	1		T27	1		T4	1
auto[1610612736:1744830463]	auto[1]	41	1			T27	1		T4	1		T113	1
auto[1744830464:1879048191]	auto[0]	56	1			T224	1		T27	1		T47	1
auto[1744830464:1879048191]	auto[1]	41	1			T26	1		T230	1		T157	1
auto[1879048192:2013265919]	auto[0]	56	1			T34	1		T224	1		T44	1
auto[1879048192:2013265919]	auto[1]	43	1			T1	1		T36	1		T155	1
auto[2013265920:2147483647]	auto[0]	65	1			T44	1		T131	2		T52	1
auto[2013265920:2147483647]	auto[1]	50	1			T4	1		T52	1		T226	1
auto[2147483648:2281701375]	auto[0]	50	1			T16	1		T43	1		T228	1
auto[2147483648:2281701375]	auto[1]	64	1			T16	1		T26	1		T45	1
auto[2281701376:2415919103]	auto[0]	49	1			T222	1		T154	1		T4	1
auto[2281701376:2415919103]	auto[1]	58	1			T14	1		T114	2		T88	1
auto[2415919104:2550136831]	auto[0]	47	1			T47	1		T255	1		T35	1
auto[2415919104:2550136831]	auto[1]	54	1			T14	1		T18	1		T222	1
auto[2550136832:2684354559]	auto[0]	38	1			T3	1		T255	1		T4	1
auto[2550136832:2684354559]	auto[1]	57	1			T18	1		T44	1		T19	1
auto[2684354560:2818572287]	auto[0]	61	1			T4	2		T35	1		T5	1
auto[2684354560:2818572287]	auto[1]	49	1			T48	1		T155	1		T113	1
auto[2818572288:2952790015]	auto[0]	50	1			T45	1		T54	1		T4	1
auto[2818572288:2952790015]	auto[1]	49	1			T18	1		T113	1		T99	1
auto[2952790016:3087007743]	auto[0]	44	1			T34	1		T113	1		T99	1
auto[2952790016:3087007743]	auto[1]	65	1			T154	1		T4	1		T257	1
auto[3087007744:3221225471]	auto[0]	47	1			T3	1		T14	1		T27	1
auto[3087007744:3221225471]	auto[1]	49	1			T1	1		T123	1		T125	1
auto[3221225472:3355443199]	auto[0]	53	1			T228	1		T51	1		T67	1
auto[3221225472:3355443199]	auto[1]	63	1			T1	1		T3	1		T23	1
auto[3355443200:3489660927]	auto[0]	49	1			T26	1		T99	1		T84	1
auto[3355443200:3489660927]	auto[1]	53	1			T51	1		T155	1		T58	1
auto[3489660928:3623878655]	auto[0]	45	1			T3	1		T123	1		T4	3
auto[3489660928:3623878655]	auto[1]	50	1			T23	1		T27	1		T52	1
auto[3623878656:3758096383]	auto[0]	51	1			T228	1		T31	1		T45	2
auto[3623878656:3758096383]	auto[1]	48	1			T1	1		T4	1		T35	1
auto[3758096384:3892314111]	auto[0]	51	1			T1	1		T26	1		T228	1
auto[3758096384:3892314111]	auto[1]	44	1			T44	1		T221	1		T4	1
auto[3892314112:4026531839]	auto[0]	40	1			T16	1		T230	1		T4	1
auto[3892314112:4026531839]	auto[1]	48	1			T3	1		T221	1		T156	1
auto[4026531840:4160749567]	auto[0]	46	1			T27	1		T228	1		T24	1
auto[4026531840:4160749567]	auto[1]	49	1			T222	1		T156	1		T62	1
auto[4160749568:4294967295]	auto[0]	54	1			T4	3		T53	1		T89	1
auto[4160749568:4294967295]	auto[1]	46	1			T47	1		T5	1		T84	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1590

1

T3

4

T14

2

T16

4

auto[1]

1675

1

T1

5

T3

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T26	1		T44	1		T54	1
auto[134217728:268435455]	99	1			T1	1		T27	1		T47	1
auto[268435456:402653183]	103	1			T14	1		T18	1		T43	1
auto[402653184:536870911]	103	1			T125	1		T224	1		T47	1
auto[536870912:671088639]	85	1			T26	1		T228	1		T4	3
auto[671088640:805306367]	118	1			T14	1		T23	1		T222	1
auto[805306368:939524095]	95	1			T3	1		T4	2		T24	1
auto[939524096:1073741823]	79	1			T1	1		T222	1		T45	1
auto[1073741824:1207959551]	105	1			T1	1		T228	1		T230	1
auto[1207959552:1342177279]	111	1			T3	1		T18	1		T47	1
auto[1342177280:1476395007]	95	1			T123	1		T4	3		T114	1
auto[1476395008:1610612735]	115	1			T18	1		T34	1		T228	1
auto[1610612736:1744830463]	99	1			T1	1		T27	1		T45	1
auto[1744830464:1879048191]	113	1			T123	1		T131	1		T45	1
auto[1879048192:2013265919]	108	1			T43	1		T26	2		T4	5
auto[2013265920:2147483647]	87	1			T26	1		T27	1		T255	1
auto[2147483648:2281701375]	101	1			T16	1		T255	2		T4	2
auto[2281701376:2415919103]	96	1			T16	1		T27	1		T221	1
auto[2415919104:2550136831]	108	1			T44	1		T230	1		T4	3
auto[2550136832:2684354559]	101	1			T44	1		T222	1		T255	1
auto[2684354560:2818572287]	117	1			T14	1		T16	1		T18	1
auto[2818572288:2952790015]	98	1			T14	1		T224	1		T228	1
auto[2952790016:3087007743]	114	1			T16	1		T43	1		T31	1
auto[3087007744:3221225471]	102	1			T44	1		T228	1		T223	1
auto[3221225472:3355443199]	92	1			T3	1		T23	1		T26	1
auto[3355443200:3489660927]	118	1			T27	1		T47	1		T54	1
auto[3489660928:3623878655]	98	1			T16	1		T34	1		T26	1
auto[3623878656:3758096383]	110	1			T3	2		T228	1		T31	1
auto[3758096384:3892314111]	100	1			T1	1		T16	1		T47	1
auto[3892314112:4026531839]	89	1			T3	1		T16	1		T224	1
auto[4026531840:4160749567]	99	1			T223	1		T4	1		T35	1
auto[4160749568:4294967295]	112	1			T27	1		T222	1		T221	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T26	1		T54	1		T49	1
auto[0:134217727]	auto[1]	50	1			T44	1		T4	1		T114	1
auto[134217728:268435455]	auto[0]	42	1			T27	1		T47	1		T222	1
auto[134217728:268435455]	auto[1]	57	1			T1	1		T114	1		T219	1
auto[268435456:402653183]	auto[0]	51	1			T34	1		T45	1		T35	1
auto[268435456:402653183]	auto[1]	52	1			T14	1		T18	1		T43	1
auto[402653184:536870911]	auto[0]	49	1			T224	1		T47	1		T54	1
auto[402653184:536870911]	auto[1]	54	1			T125	1		T4	1		T36	1
auto[536870912:671088639]	auto[0]	44	1			T26	1		T228	1		T4	1
auto[536870912:671088639]	auto[1]	41	1			T4	2		T225	1		T113	1
auto[671088640:805306367]	auto[0]	63	1			T14	1		T223	1		T154	1
auto[671088640:805306367]	auto[1]	55	1			T23	1		T222	1		T155	1
auto[805306368:939524095]	auto[0]	44	1			T3	1		T4	2		T24	1
auto[805306368:939524095]	auto[1]	51	1			T113	1		T49	1		T7	1
auto[939524096:1073741823]	auto[0]	35	1			T222	1		T53	1		T113	1
auto[939524096:1073741823]	auto[1]	44	1			T1	1		T45	1		T4	1
auto[1073741824:1207959551]	auto[0]	55	1			T228	1		T4	2		T115	1
auto[1073741824:1207959551]	auto[1]	50	1			T1	1		T230	1		T67	1
auto[1207959552:1342177279]	auto[0]	54	1			T47	1		T228	1		T4	1
auto[1207959552:1342177279]	auto[1]	57	1			T3	1		T18	1		T223	1
auto[1342177280:1476395007]	auto[0]	40	1			T235	1		T5	1		T146	1
auto[1342177280:1476395007]	auto[1]	55	1			T123	1		T4	3		T114	1
auto[1476395008:1610612735]	auto[0]	52	1			T18	1		T34	1		T228	1
auto[1476395008:1610612735]	auto[1]	63	1			T4	1		T113	1		T149	1
auto[1610612736:1744830463]	auto[0]	40	1			T24	1		T213	1		T58	1
auto[1610612736:1744830463]	auto[1]	59	1			T1	1		T27	1		T45	1
auto[1744830464:1879048191]	auto[0]	58	1			T45	1		T67	1		T25	1
auto[1744830464:1879048191]	auto[1]	55	1			T123	1		T131	1		T4	1
auto[1879048192:2013265919]	auto[0]	47	1			T43	1		T26	2		T4	3
auto[1879048192:2013265919]	auto[1]	61	1			T4	2		T70	1		T122	1
auto[2013265920:2147483647]	auto[0]	40	1			T26	1		T27	1		T4	1
auto[2013265920:2147483647]	auto[1]	47	1			T255	1		T51	1		T86	1
auto[2147483648:2281701375]	auto[0]	51	1			T255	1		T4	2		T36	1
auto[2147483648:2281701375]	auto[1]	50	1			T16	1		T255	1		T225	1
auto[2281701376:2415919103]	auto[0]	45	1			T27	1		T221	1		T35	1
auto[2281701376:2415919103]	auto[1]	51	1			T16	1		T156	1		T385	1
auto[2415919104:2550136831]	auto[0]	57	1			T44	1		T230	1		T4	3
auto[2415919104:2550136831]	auto[1]	51	1			T48	1		T90	1		T61	1
auto[2550136832:2684354559]	auto[0]	45	1			T44	1		T255	1		T4	2
auto[2550136832:2684354559]	auto[1]	56	1			T222	1		T85	1		T19	1
auto[2684354560:2818572287]	auto[0]	69	1			T16	1		T31	1		T45	2
auto[2684354560:2818572287]	auto[1]	48	1			T14	1		T18	1		T23	1
auto[2818572288:2952790015]	auto[0]	55	1			T14	1		T228	1		T31	1
auto[2818572288:2952790015]	auto[1]	43	1			T224	1		T4	1		T36	1
auto[2952790016:3087007743]	auto[0]	53	1			T16	1		T43	1		T31	1
auto[2952790016:3087007743]	auto[1]	61	1			T51	1		T156	1		T100	1
auto[3087007744:3221225471]	auto[0]	54	1			T44	1		T228	1		T53	1
auto[3087007744:3221225471]	auto[1]	48	1			T223	1		T5	1		T49	1
auto[3221225472:3355443199]	auto[0]	43	1			T23	1		T224	1		T45	1
auto[3221225472:3355443199]	auto[1]	49	1			T3	1		T26	1		T156	1
auto[3355443200:3489660927]	auto[0]	49	1			T47	1		T54	1		T4	1
auto[3355443200:3489660927]	auto[1]	69	1			T27	1		T4	1		T213	1
auto[3489660928:3623878655]	auto[0]	51	1			T16	1		T34	1		T154	1
auto[3489660928:3623878655]	auto[1]	47	1			T26	1		T224	1		T35	1
auto[3623878656:3758096383]	auto[0]	58	1			T3	2		T228	1		T31	1
auto[3623878656:3758096383]	auto[1]	52	1			T230	1		T4	1		T113	2
auto[3758096384:3892314111]	auto[0]	47	1			T228	1		T4	1		T35	1
auto[3758096384:3892314111]	auto[1]	53	1			T1	1		T16	1		T47	1
auto[3892314112:4026531839]	auto[0]	48	1			T3	1		T16	1		T4	1
auto[3892314112:4026531839]	auto[1]	41	1			T224	1		T154	1		T225	1
auto[4026531840:4160749567]	auto[0]	53	1			T4	1		T35	1		T114	1
auto[4026531840:4160749567]	auto[1]	46	1			T223	1		T83	1		T62	1
auto[4160749568:4294967295]	auto[0]	53	1			T27	1		T255	1		T4	2
auto[4160749568:4294967295]	auto[1]	59	1			T222	1		T221	1		T154	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1593

1

T1

1

T3

2

T14

2

auto[1]

1671

1

T1

4

T3

4

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T43	1		T31	1		T222	1
auto[134217728:268435455]	88	1			T18	1		T27	1		T45	1
auto[268435456:402653183]	86	1			T3	1		T26	1		T47	1
auto[402653184:536870911]	95	1			T18	1		T123	1		T26	1
auto[536870912:671088639]	97	1			T3	1		T26	1		T47	1
auto[671088640:805306367]	87	1			T3	1		T26	1		T228	1
auto[805306368:939524095]	90	1			T16	1		T222	1		T255	1
auto[939524096:1073741823]	112	1			T224	1		T44	1		T31	1
auto[1073741824:1207959551]	119	1			T16	1		T26	1		T44	1
auto[1207959552:1342177279]	106	1			T16	1		T23	1		T4	2
auto[1342177280:1476395007]	118	1			T4	3		T35	1		T51	1
auto[1476395008:1610612735]	91	1			T1	2		T3	1		T16	1
auto[1610612736:1744830463]	113	1			T1	1		T16	1		T27	1
auto[1744830464:1879048191]	102	1			T228	1		T154	1		T4	2
auto[1879048192:2013265919]	94	1			T16	1		T27	1		T44	1
auto[2013265920:2147483647]	117	1			T23	1		T228	1		T255	1
auto[2147483648:2281701375]	107	1			T228	1		T31	1		T154	1
auto[2281701376:2415919103]	110	1			T14	1		T16	1		T224	1
auto[2415919104:2550136831]	93	1			T222	1		T4	2		T36	1
auto[2550136832:2684354559]	112	1			T1	1		T18	1		T26	1
auto[2684354560:2818572287]	99	1			T4	2		T114	1		T36	1
auto[2818572288:2952790015]	109	1			T14	1		T18	1		T34	1
auto[2952790016:3087007743]	106	1			T23	1		T223	1		T230	1
auto[3087007744:3221225471]	97	1			T3	1		T43	1		T26	1
auto[3221225472:3355443199]	111	1			T34	1		T26	1		T4	3
auto[3355443200:3489660927]	85	1			T14	1		T47	1		T228	1
auto[3489660928:3623878655]	100	1			T43	1		T224	1		T31	1
auto[3623878656:3758096383]	97	1			T27	1		T223	1		T35	1
auto[3758096384:3892314111]	110	1			T23	1		T47	1		T223	1
auto[3892314112:4026531839]	106	1			T1	1		T3	1		T14	1
auto[4026531840:4160749567]	103	1			T131	1		T154	1		T4	2
auto[4160749568:4294967295]	98	1			T34	1		T4	1		T114	1