Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2838

1

T1

5

T3

6

T14

4

auto[1]

211

1

T1

8

T18

2

T154

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T3	1		T14	1		T16	1
auto[134217728:268435455]	94	1			T3	1		T18	1		T23	1
auto[268435456:402653183]	97	1			T23	1		T228	1		T222	1
auto[402653184:536870911]	76	1			T131	1		T4	2		T114	1
auto[536870912:671088639]	76	1			T1	1		T224	1		T27	1
auto[671088640:805306367]	112	1			T1	1		T14	1		T47	2
auto[805306368:939524095]	103	1			T43	1		T228	1		T230	1
auto[939524096:1073741823]	101	1			T1	1		T3	1		T34	1
auto[1073741824:1207959551]	88	1			T1	1		T123	1		T27	1
auto[1207959552:1342177279]	93	1			T14	1		T16	1		T18	1
auto[1342177280:1476395007]	102	1			T3	2		T222	1		T154	1
auto[1476395008:1610612735]	87	1			T23	1		T221	1		T4	2
auto[1610612736:1744830463]	95	1			T47	1		T223	1		T4	2
auto[1744830464:1879048191]	89	1			T18	1		T123	1		T43	1
auto[1879048192:2013265919]	84	1			T1	2		T131	1		T230	1
auto[2013265920:2147483647]	111	1			T228	1		T4	1		T225	1
auto[2147483648:2281701375]	101	1			T1	1		T26	1		T27	1
auto[2281701376:2415919103]	102	1			T31	1		T222	1		T154	1
auto[2415919104:2550136831]	90	1			T18	1		T4	3		T35	2
auto[2550136832:2684354559]	73	1			T14	1		T45	2		T4	2
auto[2684354560:2818572287]	103	1			T1	2		T255	1		T4	3
auto[2818572288:2952790015]	87	1			T228	1		T154	1		T230	1
auto[2952790016:3087007743]	92	1			T222	1		T221	1		T230	1
auto[3087007744:3221225471]	87	1			T16	1		T26	1		T154	1
auto[3221225472:3355443199]	82	1			T228	1		T223	1		T154	1
auto[3355443200:3489660927]	98	1			T23	1		T223	1		T255	1
auto[3489660928:3623878655]	98	1			T1	1		T3	1		T18	1
auto[3623878656:3758096383]	119	1			T26	3		T27	1		T47	1
auto[3758096384:3892314111]	98	1			T47	1		T67	1		T48	1
auto[3892314112:4026531839]	117	1			T1	2		T16	2		T18	1
auto[4026531840:4160749567]	105	1			T26	1		T224	1		T154	2
auto[4160749568:4294967295]	92	1			T1	1		T125	1		T26	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	84	1			T3	1		T14	1		T16	1
auto[0:134217727]	auto[1]	13	1			T157	1		T387	1		T411	1
auto[134217728:268435455]	auto[0]	90	1			T3	1		T18	1		T23	1
auto[134217728:268435455]	auto[1]	4	1			T156	1		T276	1		T410	1
auto[268435456:402653183]	auto[0]	89	1			T23	1		T228	1		T222	1
auto[268435456:402653183]	auto[1]	8	1			T155	1		T89	1		T295	1
auto[402653184:536870911]	auto[0]	71	1			T131	1		T4	2		T114	1
auto[402653184:536870911]	auto[1]	5	1			T155	1		T422	1		T414	1
auto[536870912:671088639]	auto[0]	74	1			T1	1		T224	1		T27	1
auto[536870912:671088639]	auto[1]	2	1			T387	1		T419	1		-	-
auto[671088640:805306367]	auto[0]	102	1			T1	1		T14	1		T47	2
auto[671088640:805306367]	auto[1]	10	1			T155	1		T84	1		T415	2
auto[805306368:939524095]	auto[0]	97	1			T43	1		T228	1		T230	1
auto[805306368:939524095]	auto[1]	6	1			T321	1		T261	1		T254	1
auto[939524096:1073741823]	auto[0]	96	1			T3	1		T34	1		T27	1
auto[939524096:1073741823]	auto[1]	5	1			T1	1		T311	1		T410	1
auto[1073741824:1207959551]	auto[0]	80	1			T1	1		T123	1		T27	1
auto[1073741824:1207959551]	auto[1]	8	1			T415	1		T311	1		T276	1
auto[1207959552:1342177279]	auto[0]	85	1			T14	1		T16	1		T18	1
auto[1207959552:1342177279]	auto[1]	8	1			T156	1		T311	1		T276	1
auto[1342177280:1476395007]	auto[0]	93	1			T3	2		T222	1		T154	1
auto[1342177280:1476395007]	auto[1]	9	1			T312	1		T422	1		T412	2
auto[1476395008:1610612735]	auto[0]	82	1			T23	1		T221	1		T4	2
auto[1476395008:1610612735]	auto[1]	5	1			T89	1		T274	1		T323	1
auto[1610612736:1744830463]	auto[0]	92	1			T47	1		T223	1		T4	2
auto[1610612736:1744830463]	auto[1]	3	1			T157	1		T412	1		T410	1
auto[1744830464:1879048191]	auto[0]	86	1			T18	1		T123	1		T43	1
auto[1744830464:1879048191]	auto[1]	3	1			T410	1		T254	1		T430	1
auto[1879048192:2013265919]	auto[0]	81	1			T131	1		T230	1		T4	2
auto[1879048192:2013265919]	auto[1]	3	1			T1	2		T295	1		-	-
auto[2013265920:2147483647]	auto[0]	105	1			T228	1		T4	1		T225	1
auto[2013265920:2147483647]	auto[1]	6	1			T155	1		T276	1		T254	2
auto[2147483648:2281701375]	auto[0]	96	1			T26	1		T27	1		T31	1
auto[2147483648:2281701375]	auto[1]	5	1			T1	1		T156	1		T419	3
auto[2281701376:2415919103]	auto[0]	94	1			T31	1		T222	1		T154	1
auto[2281701376:2415919103]	auto[1]	8	1			T408	1		T261	1		T412	1
auto[2415919104:2550136831]	auto[0]	79	1			T4	3		T35	2		T225	1
auto[2415919104:2550136831]	auto[1]	11	1			T18	1		T156	1		T415	1
auto[2550136832:2684354559]	auto[0]	68	1			T14	1		T45	2		T4	2
auto[2550136832:2684354559]	auto[1]	5	1			T89	1		T292	1		T276	1
auto[2684354560:2818572287]	auto[0]	93	1			T1	1		T255	1		T4	3
auto[2684354560:2818572287]	auto[1]	10	1			T1	1		T84	1		T312	1
auto[2818572288:2952790015]	auto[0]	81	1			T228	1		T154	1		T230	1
auto[2818572288:2952790015]	auto[1]	6	1			T155	1		T89	1		T419	1
auto[2952790016:3087007743]	auto[0]	89	1			T222	1		T221	1		T230	1
auto[2952790016:3087007743]	auto[1]	3	1			T292	1		T254	1		T417	1
auto[3087007744:3221225471]	auto[0]	81	1			T16	1		T26	1		T67	1
auto[3087007744:3221225471]	auto[1]	6	1			T154	1		T89	1		T321	2
auto[3221225472:3355443199]	auto[0]	76	1			T228	1		T223	1		T154	1
auto[3221225472:3355443199]	auto[1]	6	1			T312	1		T414	1		T419	1
auto[3355443200:3489660927]	auto[0]	89	1			T23	1		T223	1		T255	1
auto[3355443200:3489660927]	auto[1]	9	1			T89	1		T157	1		T387	1
auto[3489660928:3623878655]	auto[0]	91	1			T1	1		T3	1		T34	1
auto[3489660928:3623878655]	auto[1]	7	1			T18	1		T155	1		T312	1
auto[3623878656:3758096383]	auto[0]	114	1			T26	3		T27	1		T47	1
auto[3623878656:3758096383]	auto[1]	5	1			T157	1		T292	1		T387	1
auto[3758096384:3892314111]	auto[0]	90	1			T47	1		T67	1		T48	1
auto[3758096384:3892314111]	auto[1]	8	1			T387	1		T321	1		T408	1
auto[3892314112:4026531839]	auto[0]	109	1			T16	2		T18	1		T224	1
auto[3892314112:4026531839]	auto[1]	8	1			T1	2		T155	1		T89	1
auto[4026531840:4160749567]	auto[0]	96	1			T26	1		T224	1		T154	2
auto[4026531840:4160749567]	auto[1]	9	1			T387	1		T321	1		T419	1
auto[4160749568:4294967295]	auto[0]	85	1			T125	1		T26	1		T156	1
auto[4160749568:4294967295]	auto[1]	7	1			T1	1		T274	1		T276	1