Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.84 99.07 98.14 98.69 100.00 99.11 98.41 91.46


Total test records in report: 1074
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1006 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2723488179 Apr 15 12:36:14 PM PDT 24 Apr 15 12:36:15 PM PDT 24 11465229 ps
T1007 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2687387816 Apr 15 12:36:06 PM PDT 24 Apr 15 12:36:10 PM PDT 24 84933761 ps
T1008 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2627610543 Apr 15 12:35:48 PM PDT 24 Apr 15 12:35:50 PM PDT 24 14144995 ps
T1009 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1912865341 Apr 15 12:35:57 PM PDT 24 Apr 15 12:36:02 PM PDT 24 1965678078 ps
T1010 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2145089122 Apr 15 12:35:59 PM PDT 24 Apr 15 12:36:01 PM PDT 24 55733102 ps
T1011 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2205755982 Apr 15 12:36:02 PM PDT 24 Apr 15 12:36:05 PM PDT 24 99388358 ps
T1012 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3466054332 Apr 15 12:36:09 PM PDT 24 Apr 15 12:36:10 PM PDT 24 25462397 ps
T1013 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2192228011 Apr 15 12:36:05 PM PDT 24 Apr 15 12:36:13 PM PDT 24 280350654 ps
T1014 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2188947596 Apr 15 12:35:50 PM PDT 24 Apr 15 12:35:56 PM PDT 24 481045567 ps
T1015 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3216119811 Apr 15 12:36:16 PM PDT 24 Apr 15 12:36:17 PM PDT 24 41302379 ps
T1016 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2928903592 Apr 15 12:36:18 PM PDT 24 Apr 15 12:36:20 PM PDT 24 9420613 ps
T1017 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1555764031 Apr 15 12:36:02 PM PDT 24 Apr 15 12:36:04 PM PDT 24 30126455 ps
T1018 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1754557501 Apr 15 12:36:03 PM PDT 24 Apr 15 12:36:05 PM PDT 24 22082654 ps
T1019 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4044921230 Apr 15 12:35:57 PM PDT 24 Apr 15 12:36:01 PM PDT 24 770023621 ps
T1020 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3645165162 Apr 15 12:36:10 PM PDT 24 Apr 15 12:36:19 PM PDT 24 840009337 ps
T1021 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2256746 Apr 15 12:36:09 PM PDT 24 Apr 15 12:36:11 PM PDT 24 46866721 ps
T1022 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1916972428 Apr 15 12:35:59 PM PDT 24 Apr 15 12:36:01 PM PDT 24 49270872 ps
T1023 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3638221621 Apr 15 12:36:02 PM PDT 24 Apr 15 12:36:11 PM PDT 24 508043261 ps
T1024 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1628653885 Apr 15 12:36:08 PM PDT 24 Apr 15 12:36:18 PM PDT 24 1581213273 ps
T1025 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3222228236 Apr 15 12:36:19 PM PDT 24 Apr 15 12:36:26 PM PDT 24 37463234 ps
T1026 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2755301683 Apr 15 12:35:48 PM PDT 24 Apr 15 12:35:51 PM PDT 24 62851906 ps
T1027 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4231499541 Apr 15 12:36:32 PM PDT 24 Apr 15 12:36:33 PM PDT 24 35162886 ps
T1028 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2441370776 Apr 15 12:36:16 PM PDT 24 Apr 15 12:36:18 PM PDT 24 22633429 ps
T1029 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.502273687 Apr 15 12:36:20 PM PDT 24 Apr 15 12:36:21 PM PDT 24 13522314 ps
T1030 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3209323381 Apr 15 12:35:56 PM PDT 24 Apr 15 12:36:00 PM PDT 24 70537761 ps
T1031 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2823943195 Apr 15 12:35:58 PM PDT 24 Apr 15 12:36:02 PM PDT 24 131434502 ps
T1032 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3515913966 Apr 15 12:35:54 PM PDT 24 Apr 15 12:35:56 PM PDT 24 42768004 ps
T1033 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2614301153 Apr 15 12:35:50 PM PDT 24 Apr 15 12:36:05 PM PDT 24 366191828 ps
T1034 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3033473442 Apr 15 12:35:48 PM PDT 24 Apr 15 12:36:03 PM PDT 24 408930719 ps
T1035 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.4197775740 Apr 15 12:35:54 PM PDT 24 Apr 15 12:35:56 PM PDT 24 428753045 ps
T1036 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1752702124 Apr 15 12:35:57 PM PDT 24 Apr 15 12:36:00 PM PDT 24 374481886 ps
T1037 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1915023606 Apr 15 12:36:07 PM PDT 24 Apr 15 12:36:08 PM PDT 24 46793504 ps
T1038 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1966086707 Apr 15 12:36:09 PM PDT 24 Apr 15 12:36:12 PM PDT 24 91592784 ps
T1039 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.858687490 Apr 15 12:36:13 PM PDT 24 Apr 15 12:36:16 PM PDT 24 35417801 ps
T1040 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2543746581 Apr 15 12:35:49 PM PDT 24 Apr 15 12:36:23 PM PDT 24 1696835098 ps
T1041 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2108486480 Apr 15 12:35:48 PM PDT 24 Apr 15 12:35:58 PM PDT 24 2590866032 ps
T1042 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3948150894 Apr 15 12:36:13 PM PDT 24 Apr 15 12:36:16 PM PDT 24 418071055 ps
T188 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1173956428 Apr 15 12:35:58 PM PDT 24 Apr 15 12:36:13 PM PDT 24 831653895 ps
T175 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2707563015 Apr 15 12:35:58 PM PDT 24 Apr 15 12:36:05 PM PDT 24 125995319 ps
T1043 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3950553677 Apr 15 12:36:04 PM PDT 24 Apr 15 12:36:07 PM PDT 24 38586579 ps
T1044 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2241600215 Apr 15 12:36:13 PM PDT 24 Apr 15 12:36:22 PM PDT 24 327021413 ps
T1045 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1947289198 Apr 15 12:36:03 PM PDT 24 Apr 15 12:36:07 PM PDT 24 179993291 ps
T1046 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3942224965 Apr 15 12:36:17 PM PDT 24 Apr 15 12:36:19 PM PDT 24 23568884 ps
T1047 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1048701457 Apr 15 12:36:16 PM PDT 24 Apr 15 12:36:20 PM PDT 24 195654968 ps
T1048 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1106377103 Apr 15 12:36:13 PM PDT 24 Apr 15 12:36:18 PM PDT 24 202696587 ps
T1049 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3212780036 Apr 15 12:36:09 PM PDT 24 Apr 15 12:36:11 PM PDT 24 199858022 ps
T1050 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2070131654 Apr 15 12:36:00 PM PDT 24 Apr 15 12:36:15 PM PDT 24 428027010 ps
T1051 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1273483807 Apr 15 12:35:58 PM PDT 24 Apr 15 12:36:00 PM PDT 24 56219066 ps
T1052 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3687784584 Apr 15 12:35:59 PM PDT 24 Apr 15 12:36:03 PM PDT 24 367160451 ps
T1053 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3535018333 Apr 15 12:36:19 PM PDT 24 Apr 15 12:36:20 PM PDT 24 174062454 ps
T189 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.538360593 Apr 15 12:35:59 PM PDT 24 Apr 15 12:36:04 PM PDT 24 69923268 ps
T1054 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3666777148 Apr 15 12:36:02 PM PDT 24 Apr 15 12:36:07 PM PDT 24 439487792 ps
T1055 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4294647381 Apr 15 12:36:13 PM PDT 24 Apr 15 12:36:19 PM PDT 24 124139866 ps
T1056 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4227595306 Apr 15 12:35:57 PM PDT 24 Apr 15 12:35:59 PM PDT 24 30169999 ps
T1057 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4185712953 Apr 15 12:36:19 PM PDT 24 Apr 15 12:36:21 PM PDT 24 11366986 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4056318261 Apr 15 12:35:56 PM PDT 24 Apr 15 12:35:58 PM PDT 24 17329506 ps
T1059 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1517406125 Apr 15 12:36:03 PM PDT 24 Apr 15 12:36:07 PM PDT 24 110346620 ps
T1060 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1897031044 Apr 15 12:35:47 PM PDT 24 Apr 15 12:35:52 PM PDT 24 986492207 ps
T1061 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3693503765 Apr 15 12:36:07 PM PDT 24 Apr 15 12:36:10 PM PDT 24 247985010 ps
T1062 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2380338246 Apr 15 12:35:51 PM PDT 24 Apr 15 12:35:53 PM PDT 24 11501747 ps
T194 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1651102066 Apr 15 12:36:10 PM PDT 24 Apr 15 12:36:16 PM PDT 24 187598209 ps
T1063 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4173835376 Apr 15 12:35:56 PM PDT 24 Apr 15 12:35:58 PM PDT 24 14695625 ps
T1064 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2564747199 Apr 15 12:36:07 PM PDT 24 Apr 15 12:36:10 PM PDT 24 168136497 ps
T1065 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.830330971 Apr 15 12:35:58 PM PDT 24 Apr 15 12:35:59 PM PDT 24 44095514 ps
T1066 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.425173683 Apr 15 12:36:16 PM PDT 24 Apr 15 12:36:18 PM PDT 24 26186688 ps
T1067 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1939339203 Apr 15 12:35:49 PM PDT 24 Apr 15 12:35:52 PM PDT 24 645045351 ps
T1068 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3614792913 Apr 15 12:35:56 PM PDT 24 Apr 15 12:36:21 PM PDT 24 4087212028 ps
T1069 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3172930700 Apr 15 12:35:57 PM PDT 24 Apr 15 12:36:13 PM PDT 24 812936916 ps
T182 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3986843434 Apr 15 12:36:09 PM PDT 24 Apr 15 12:36:21 PM PDT 24 333511550 ps
T1070 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3298365102 Apr 15 12:36:15 PM PDT 24 Apr 15 12:36:17 PM PDT 24 43933594 ps
T1071 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3229296261 Apr 15 12:36:07 PM PDT 24 Apr 15 12:36:09 PM PDT 24 18374435 ps
T1072 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.982237676 Apr 15 12:36:17 PM PDT 24 Apr 15 12:36:19 PM PDT 24 45162637 ps
T1073 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2491211915 Apr 15 12:36:13 PM PDT 24 Apr 15 12:36:22 PM PDT 24 273233670 ps
T1074 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3675140191 Apr 15 12:36:02 PM PDT 24 Apr 15 12:36:05 PM PDT 24 96905040 ps

Test location /workspace/coverage/default/26.keymgr_lc_disable.2528014357
Short name T16
Test name
Test status
Simulation time 96418930 ps
CPU time 4.26 seconds
Started Apr 15 02:28:16 PM PDT 24
Finished Apr 15 02:28:21 PM PDT 24
Peak memory 209972 kb
Host smart-f4eae373-93e0-4512-a6ec-de689db58387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528014357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2528014357
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1487887001
Short name T4
Test name
Test status
Simulation time 16550565753 ps
CPU time 53.95 seconds
Started Apr 15 02:28:12 PM PDT 24
Finished Apr 15 02:29:07 PM PDT 24
Peak memory 221300 kb
Host smart-b1084590-546b-4134-a659-63df1ca59edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487887001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1487887001
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1815102441
Short name T1
Test name
Test status
Simulation time 269926455 ps
CPU time 4.88 seconds
Started Apr 15 02:29:40 PM PDT 24
Finished Apr 15 02:29:46 PM PDT 24
Peak memory 214580 kb
Host smart-7510359d-71cd-437c-9eeb-3f57f9b154c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815102441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1815102441
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2134965795
Short name T88
Test name
Test status
Simulation time 496639274 ps
CPU time 19.03 seconds
Started Apr 15 02:28:39 PM PDT 24
Finished Apr 15 02:28:59 PM PDT 24
Peak memory 222956 kb
Host smart-ef758c27-3ebd-466d-ae5b-12c518e0eb52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134965795 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2134965795
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.4093868628
Short name T6
Test name
Test status
Simulation time 2155247637 ps
CPU time 14.98 seconds
Started Apr 15 02:26:30 PM PDT 24
Finished Apr 15 02:26:45 PM PDT 24
Peak memory 239040 kb
Host smart-daf757ad-3a72-460b-99ff-7283a47b2de4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093868628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.4093868628
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.4105565394
Short name T208
Test name
Test status
Simulation time 1525023761 ps
CPU time 39.72 seconds
Started Apr 15 02:26:43 PM PDT 24
Finished Apr 15 02:27:24 PM PDT 24
Peak memory 222824 kb
Host smart-22a96234-e209-4b3a-b914-e485ec9b38fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105565394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.4105565394
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.588107787
Short name T34
Test name
Test status
Simulation time 183697969 ps
CPU time 4.56 seconds
Started Apr 15 02:26:24 PM PDT 24
Finished Apr 15 02:26:29 PM PDT 24
Peak memory 222952 kb
Host smart-939c94f6-5a8b-43ae-9a30-eee7cc02782f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588107787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.588107787
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2954343273
Short name T7
Test name
Test status
Simulation time 527906197 ps
CPU time 6 seconds
Started Apr 15 02:29:03 PM PDT 24
Finished Apr 15 02:29:10 PM PDT 24
Peak memory 210956 kb
Host smart-045c7fa7-17c7-472b-be39-1083b9c89ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954343273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2954343273
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1634441403
Short name T129
Test name
Test status
Simulation time 319319899 ps
CPU time 6.53 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:20 PM PDT 24
Peak memory 214444 kb
Host smart-f1dcfed1-b4bc-4f1b-a039-e8f356f3b76f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634441403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1634441403
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2394136731
Short name T49
Test name
Test status
Simulation time 99499952 ps
CPU time 3.12 seconds
Started Apr 15 02:26:34 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 214952 kb
Host smart-d753e474-33b0-48f2-bf14-bf30a2cce3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394136731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2394136731
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3198703657
Short name T24
Test name
Test status
Simulation time 1056634636 ps
CPU time 10.17 seconds
Started Apr 15 02:28:02 PM PDT 24
Finished Apr 15 02:28:13 PM PDT 24
Peak memory 214504 kb
Host smart-e6df1649-b036-4837-ab55-ccff12819bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198703657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3198703657
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1945540510
Short name T321
Test name
Test status
Simulation time 772287144 ps
CPU time 43.06 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:29:27 PM PDT 24
Peak memory 215956 kb
Host smart-09235f36-b3e5-4433-a8b5-d70a47f8f379
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1945540510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1945540510
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.299933599
Short name T113
Test name
Test status
Simulation time 5080667920 ps
CPU time 34.61 seconds
Started Apr 15 02:28:14 PM PDT 24
Finished Apr 15 02:28:50 PM PDT 24
Peak memory 217380 kb
Host smart-2d360cfc-42b6-4e90-8850-2780511dba06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299933599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.299933599
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.967523779
Short name T23
Test name
Test status
Simulation time 1521376134 ps
CPU time 8.79 seconds
Started Apr 15 02:28:31 PM PDT 24
Finished Apr 15 02:28:41 PM PDT 24
Peak memory 219852 kb
Host smart-fa1f6c83-cbab-40da-bb7d-b0624debd63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967523779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.967523779
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3512307856
Short name T254
Test name
Test status
Simulation time 1186438721 ps
CPU time 14.91 seconds
Started Apr 15 02:29:16 PM PDT 24
Finished Apr 15 02:29:32 PM PDT 24
Peak memory 222824 kb
Host smart-f4d49001-0236-454c-ad31-11a4d61ece27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3512307856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3512307856
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2771616816
Short name T141
Test name
Test status
Simulation time 2297138369 ps
CPU time 19.47 seconds
Started Apr 15 02:27:35 PM PDT 24
Finished Apr 15 02:27:55 PM PDT 24
Peak memory 221388 kb
Host smart-bf71a3da-c83c-40c1-97de-c56f8c10c4ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771616816 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2771616816
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1647500909
Short name T73
Test name
Test status
Simulation time 2560189898 ps
CPU time 51.4 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:30:11 PM PDT 24
Peak memory 221284 kb
Host smart-ec815c66-df3d-4bc7-a450-31106a373210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647500909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1647500909
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1512345946
Short name T131
Test name
Test status
Simulation time 37361749 ps
CPU time 3.11 seconds
Started Apr 15 02:27:32 PM PDT 24
Finished Apr 15 02:27:36 PM PDT 24
Peak memory 214636 kb
Host smart-c5f07e4e-22ab-43db-917e-a6e206d30032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512345946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1512345946
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2994215703
Short name T387
Test name
Test status
Simulation time 173065676 ps
CPU time 8.9 seconds
Started Apr 15 02:27:11 PM PDT 24
Finished Apr 15 02:27:20 PM PDT 24
Peak memory 215000 kb
Host smart-99a7567c-71e7-4bb4-881f-8e2ee9fd8c8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994215703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2994215703
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.589205247
Short name T62
Test name
Test status
Simulation time 847390346 ps
CPU time 12.91 seconds
Started Apr 15 02:29:25 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 222872 kb
Host smart-127d8171-a60f-406d-a0c3-1583395e9ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589205247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.589205247
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3602571317
Short name T29
Test name
Test status
Simulation time 294729664 ps
CPU time 2.76 seconds
Started Apr 15 02:27:53 PM PDT 24
Finished Apr 15 02:27:57 PM PDT 24
Peak memory 211064 kb
Host smart-3b3c6470-a8aa-4f74-b532-e5df43c87296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602571317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3602571317
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.949562994
Short name T412
Test name
Test status
Simulation time 242366153 ps
CPU time 13.58 seconds
Started Apr 15 02:28:07 PM PDT 24
Finished Apr 15 02:28:21 PM PDT 24
Peak memory 214800 kb
Host smart-4a972e8e-2362-485b-af57-c3dd1c6b36af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949562994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.949562994
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3284856406
Short name T96
Test name
Test status
Simulation time 669236550 ps
CPU time 5.2 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:48 PM PDT 24
Peak memory 209808 kb
Host smart-bbba8338-1c81-469c-ae33-abf621172cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284856406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3284856406
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3036892286
Short name T84
Test name
Test status
Simulation time 197308818 ps
CPU time 3.59 seconds
Started Apr 15 02:28:30 PM PDT 24
Finished Apr 15 02:28:34 PM PDT 24
Peak memory 214728 kb
Host smart-be0bb80d-88d0-4906-bf72-47bf4b3ccc6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036892286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3036892286
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3668834005
Short name T132
Test name
Test status
Simulation time 204416887 ps
CPU time 4.06 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 214352 kb
Host smart-6eb7b39e-1d2c-4603-ae04-b17e51f65449
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668834005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3668834005
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1769053900
Short name T38
Test name
Test status
Simulation time 77410250 ps
CPU time 3.67 seconds
Started Apr 15 02:27:26 PM PDT 24
Finished Apr 15 02:27:30 PM PDT 24
Peak memory 209008 kb
Host smart-7677687e-cd18-4ed9-8ea3-bd4a31c28430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769053900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1769053900
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2435879251
Short name T31
Test name
Test status
Simulation time 88690629 ps
CPU time 4.21 seconds
Started Apr 15 02:28:13 PM PDT 24
Finished Apr 15 02:28:18 PM PDT 24
Peak memory 219888 kb
Host smart-b20c4fe5-125d-40ad-8174-f9823db4a1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435879251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2435879251
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.48377234
Short name T434
Test name
Test status
Simulation time 110543377 ps
CPU time 0.99 seconds
Started Apr 15 02:27:24 PM PDT 24
Finished Apr 15 02:27:26 PM PDT 24
Peak memory 206452 kb
Host smart-9671c211-2e07-449f-b9c3-a4a97e23a8b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48377234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.48377234
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2144984236
Short name T36
Test name
Test status
Simulation time 94228306 ps
CPU time 3.77 seconds
Started Apr 15 02:28:11 PM PDT 24
Finished Apr 15 02:28:15 PM PDT 24
Peak memory 214660 kb
Host smart-0faba39a-8f15-4d79-95ef-5ca8d836b5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144984236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2144984236
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1634946047
Short name T105
Test name
Test status
Simulation time 127095648 ps
CPU time 5.3 seconds
Started Apr 15 02:26:38 PM PDT 24
Finished Apr 15 02:26:44 PM PDT 24
Peak memory 214608 kb
Host smart-1b9fed1c-8ef9-4061-93e4-364419cf537f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634946047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1634946047
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1730568417
Short name T410
Test name
Test status
Simulation time 647513773 ps
CPU time 9.37 seconds
Started Apr 15 02:25:45 PM PDT 24
Finished Apr 15 02:25:55 PM PDT 24
Peak memory 215160 kb
Host smart-6d6bf1ca-3cd3-47dd-a87e-d3a363f9a5ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730568417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1730568417
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1520054444
Short name T245
Test name
Test status
Simulation time 11770076210 ps
CPU time 349.86 seconds
Started Apr 15 02:27:38 PM PDT 24
Finished Apr 15 02:33:29 PM PDT 24
Peak memory 222868 kb
Host smart-463b496e-2441-4f9e-ad8c-5a43f26421cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520054444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1520054444
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4011304128
Short name T64
Test name
Test status
Simulation time 83849529 ps
CPU time 3.36 seconds
Started Apr 15 02:27:39 PM PDT 24
Finished Apr 15 02:27:44 PM PDT 24
Peak memory 209992 kb
Host smart-e7dfbc80-5d4c-4442-82c8-82677d69fb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011304128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4011304128
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3176948709
Short name T358
Test name
Test status
Simulation time 113798531 ps
CPU time 4.08 seconds
Started Apr 15 02:26:40 PM PDT 24
Finished Apr 15 02:26:45 PM PDT 24
Peak memory 215592 kb
Host smart-a6bab27c-3827-4917-968e-5a5f453fdc24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176948709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3176948709
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2728435628
Short name T166
Test name
Test status
Simulation time 2220926693 ps
CPU time 14 seconds
Started Apr 15 12:35:50 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 209316 kb
Host smart-4e17760f-6b2a-4171-956d-2a7120e87a3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728435628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2728435628
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.4077816950
Short name T104
Test name
Test status
Simulation time 234767307 ps
CPU time 4.91 seconds
Started Apr 15 02:28:44 PM PDT 24
Finished Apr 15 02:28:49 PM PDT 24
Peak memory 222656 kb
Host smart-83be3b31-e530-4259-aaa8-c25b00a7d0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077816950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4077816950
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1786626598
Short name T72
Test name
Test status
Simulation time 533949424 ps
CPU time 25.61 seconds
Started Apr 15 02:29:34 PM PDT 24
Finished Apr 15 02:30:02 PM PDT 24
Peak memory 222852 kb
Host smart-b3ef99b5-59f0-4658-ac27-a091c402aad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786626598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1786626598
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.4279726640
Short name T18
Test name
Test status
Simulation time 386243340 ps
CPU time 3.79 seconds
Started Apr 15 02:28:46 PM PDT 24
Finished Apr 15 02:28:51 PM PDT 24
Peak memory 214556 kb
Host smart-36769b07-34bd-4764-840b-142014dad745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279726640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.4279726640
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.332899417
Short name T373
Test name
Test status
Simulation time 87508068 ps
CPU time 4.49 seconds
Started Apr 15 02:27:17 PM PDT 24
Finished Apr 15 02:27:22 PM PDT 24
Peak memory 214564 kb
Host smart-1a60cbf9-8164-4b8f-b36b-112d417a9e01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332899417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.332899417
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1309859580
Short name T120
Test name
Test status
Simulation time 670428514 ps
CPU time 4.8 seconds
Started Apr 15 02:28:34 PM PDT 24
Finished Apr 15 02:28:39 PM PDT 24
Peak memory 222736 kb
Host smart-682fac49-56d8-423d-841c-6bd9c0dfc798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309859580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1309859580
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3235683611
Short name T323
Test name
Test status
Simulation time 55840981 ps
CPU time 3.97 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 214592 kb
Host smart-321caa6b-3398-45cf-891d-8284d7d809fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235683611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3235683611
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2458337546
Short name T247
Test name
Test status
Simulation time 1944055408 ps
CPU time 55.41 seconds
Started Apr 15 02:28:28 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 215572 kb
Host smart-ce32eff6-9828-4756-bccd-c628afaf9feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458337546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2458337546
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1270908599
Short name T284
Test name
Test status
Simulation time 326043680 ps
CPU time 3.92 seconds
Started Apr 15 02:29:35 PM PDT 24
Finished Apr 15 02:29:41 PM PDT 24
Peak memory 214852 kb
Host smart-0aab4e81-d758-485f-acd5-91b53b8c1820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270908599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1270908599
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1400060404
Short name T236
Test name
Test status
Simulation time 849165072 ps
CPU time 21.94 seconds
Started Apr 15 02:28:51 PM PDT 24
Finished Apr 15 02:29:14 PM PDT 24
Peak memory 222776 kb
Host smart-52df8960-2ffc-4989-b1fd-44b635ae98c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400060404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1400060404
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.985833038
Short name T330
Test name
Test status
Simulation time 1301752866 ps
CPU time 50.28 seconds
Started Apr 15 02:29:29 PM PDT 24
Finished Apr 15 02:30:21 PM PDT 24
Peak memory 217396 kb
Host smart-8e069b02-a5f0-4212-af9c-a15db1931bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985833038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.985833038
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2497762836
Short name T172
Test name
Test status
Simulation time 459561834 ps
CPU time 5.83 seconds
Started Apr 15 12:35:54 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 209020 kb
Host smart-7dabdcdd-dcfc-4eb6-a3e0-8013a52b8b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497762836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2497762836
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1649959938
Short name T199
Test name
Test status
Simulation time 92180861 ps
CPU time 3.07 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:46 PM PDT 24
Peak memory 222732 kb
Host smart-f0d818d8-13a2-4f4c-bed5-4ef46f55b3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649959938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1649959938
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1322720695
Short name T158
Test name
Test status
Simulation time 779328452 ps
CPU time 6.68 seconds
Started Apr 15 02:29:17 PM PDT 24
Finished Apr 15 02:29:25 PM PDT 24
Peak memory 218456 kb
Host smart-f374e237-d24a-491c-a4c6-9a0cdedef8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322720695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1322720695
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3177406354
Short name T417
Test name
Test status
Simulation time 314059901 ps
CPU time 8.33 seconds
Started Apr 15 02:28:04 PM PDT 24
Finished Apr 15 02:28:14 PM PDT 24
Peak memory 222732 kb
Host smart-4f880f59-0aa2-473f-a3a8-0c13e1401166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177406354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3177406354
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.575753448
Short name T382
Test name
Test status
Simulation time 257326035 ps
CPU time 5.32 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:28:48 PM PDT 24
Peak memory 211860 kb
Host smart-9c0c8500-f9f3-4531-b787-6b8a3ab9e5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575753448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.575753448
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2562064049
Short name T114
Test name
Test status
Simulation time 1011925478 ps
CPU time 18.43 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:29:01 PM PDT 24
Peak memory 209352 kb
Host smart-f192f43d-1104-47fa-9d90-87c7fecdfd75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562064049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2562064049
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1149889601
Short name T169
Test name
Test status
Simulation time 1095960206 ps
CPU time 8.55 seconds
Started Apr 15 12:35:53 PM PDT 24
Finished Apr 15 12:36:03 PM PDT 24
Peak memory 209144 kb
Host smart-b638fe0c-c268-4bff-b5d8-790eb73d1764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149889601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1149889601
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3192813532
Short name T349
Test name
Test status
Simulation time 148141635 ps
CPU time 3.27 seconds
Started Apr 15 02:29:03 PM PDT 24
Finished Apr 15 02:29:07 PM PDT 24
Peak memory 209556 kb
Host smart-bbb59807-5d9a-44b8-aa3e-2c7fd50782fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192813532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3192813532
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2251764090
Short name T202
Test name
Test status
Simulation time 145919171 ps
CPU time 4.21 seconds
Started Apr 15 02:26:36 PM PDT 24
Finished Apr 15 02:26:41 PM PDT 24
Peak memory 218364 kb
Host smart-bc369770-5a22-4a74-a823-9d8c86f59cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251764090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2251764090
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2707563015
Short name T175
Test name
Test status
Simulation time 125995319 ps
CPU time 6.16 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 209452 kb
Host smart-a7ba3b28-f255-4a49-a21a-7c2657084003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707563015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2707563015
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.437091851
Short name T195
Test name
Test status
Simulation time 1108451841 ps
CPU time 6.92 seconds
Started Apr 15 02:28:47 PM PDT 24
Finished Apr 15 02:28:54 PM PDT 24
Peak memory 223044 kb
Host smart-cd259174-ead9-49a2-add2-13f9e6849b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437091851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.437091851
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3090579697
Short name T196
Test name
Test status
Simulation time 1717398619 ps
CPU time 8.53 seconds
Started Apr 15 02:29:24 PM PDT 24
Finished Apr 15 02:29:33 PM PDT 24
Peak memory 222196 kb
Host smart-16d15df4-dcb2-47e4-bd1b-e259b7a35d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090579697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3090579697
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2038260358
Short name T308
Test name
Test status
Simulation time 356674492 ps
CPU time 10.07 seconds
Started Apr 15 02:26:01 PM PDT 24
Finished Apr 15 02:26:12 PM PDT 24
Peak memory 222732 kb
Host smart-8a0614ee-a706-4a55-8b75-a194cce112af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038260358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2038260358
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3347852026
Short name T143
Test name
Test status
Simulation time 1454982539 ps
CPU time 15.5 seconds
Started Apr 15 02:27:44 PM PDT 24
Finished Apr 15 02:28:00 PM PDT 24
Peak memory 220452 kb
Host smart-be00b2c7-6686-4525-9c8b-164b1d4c7601
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347852026 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3347852026
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1026644717
Short name T271
Test name
Test status
Simulation time 1825567421 ps
CPU time 22.57 seconds
Started Apr 15 02:27:56 PM PDT 24
Finished Apr 15 02:28:20 PM PDT 24
Peak memory 221724 kb
Host smart-f52e59e3-afe8-4e73-a6e0-69f9da519a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026644717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1026644717
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3773496979
Short name T183
Test name
Test status
Simulation time 361823771 ps
CPU time 4.32 seconds
Started Apr 15 12:36:12 PM PDT 24
Finished Apr 15 12:36:17 PM PDT 24
Peak memory 209268 kb
Host smart-450ebbc7-1265-4d6a-ba27-576617d7cff6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773496979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3773496979
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1599814768
Short name T173
Test name
Test status
Simulation time 627151845 ps
CPU time 4.48 seconds
Started Apr 15 12:36:11 PM PDT 24
Finished Apr 15 12:36:17 PM PDT 24
Peak memory 209168 kb
Host smart-67952562-8253-4096-95ed-5d8eb41b0de1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599814768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1599814768
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3565000202
Short name T75
Test name
Test status
Simulation time 2640967185 ps
CPU time 40.02 seconds
Started Apr 15 02:27:14 PM PDT 24
Finished Apr 15 02:27:55 PM PDT 24
Peak memory 215560 kb
Host smart-82a4e2c0-8edb-4364-9973-3c129b1f6e01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565000202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3565000202
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3655349229
Short name T59
Test name
Test status
Simulation time 116878691 ps
CPU time 3.04 seconds
Started Apr 15 02:27:55 PM PDT 24
Finished Apr 15 02:27:59 PM PDT 24
Peak memory 210544 kb
Host smart-05fa5b1d-5a96-4f91-bc2a-6921f6bf1c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655349229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3655349229
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1109631941
Short name T809
Test name
Test status
Simulation time 1000748550 ps
CPU time 36.46 seconds
Started Apr 15 02:26:13 PM PDT 24
Finished Apr 15 02:26:50 PM PDT 24
Peak memory 222128 kb
Host smart-bd027c20-7bcf-4f12-b173-2135b3104f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109631941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1109631941
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2798220689
Short name T413
Test name
Test status
Simulation time 72862709 ps
CPU time 2.71 seconds
Started Apr 15 02:28:23 PM PDT 24
Finished Apr 15 02:28:27 PM PDT 24
Peak memory 214700 kb
Host smart-fb116745-ecea-4f2d-827b-fcb452fa8bb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798220689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2798220689
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3365628220
Short name T287
Test name
Test status
Simulation time 2867809193 ps
CPU time 23.08 seconds
Started Apr 15 02:29:15 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 222792 kb
Host smart-61f99519-6145-46b9-9730-440d298500cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365628220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3365628220
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1197595562
Short name T426
Test name
Test status
Simulation time 228630354 ps
CPU time 12.39 seconds
Started Apr 15 02:29:34 PM PDT 24
Finished Apr 15 02:29:48 PM PDT 24
Peak memory 214952 kb
Host smart-12e6c116-878e-4283-8f57-4f4d0bc8cdf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1197595562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1197595562
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.883602968
Short name T333
Test name
Test status
Simulation time 348629392 ps
CPU time 4.68 seconds
Started Apr 15 02:26:37 PM PDT 24
Finished Apr 15 02:26:43 PM PDT 24
Peak memory 214624 kb
Host smart-5a99a5af-07a4-4337-979a-627dbd211eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883602968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.883602968
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.179810456
Short name T168
Test name
Test status
Simulation time 478278364 ps
CPU time 10.29 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:44 PM PDT 24
Peak memory 220248 kb
Host smart-ea605add-1d4a-4fa1-a268-45a59ff550bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179810456 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.179810456
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3972465021
Short name T197
Test name
Test status
Simulation time 243254699 ps
CPU time 6.2 seconds
Started Apr 15 02:25:53 PM PDT 24
Finished Apr 15 02:26:00 PM PDT 24
Peak memory 215868 kb
Host smart-eb6b7cd2-9a56-4349-9aeb-56a2e043499f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972465021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3972465021
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.707990097
Short name T203
Test name
Test status
Simulation time 125223896 ps
CPU time 6.66 seconds
Started Apr 15 02:29:01 PM PDT 24
Finished Apr 15 02:29:09 PM PDT 24
Peak memory 222820 kb
Host smart-68508fac-b351-497f-b71d-0becedc9bfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707990097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.707990097
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2318862290
Short name T198
Test name
Test status
Simulation time 235034904 ps
CPU time 4.55 seconds
Started Apr 15 02:29:35 PM PDT 24
Finished Apr 15 02:29:42 PM PDT 24
Peak memory 222880 kb
Host smart-54ff17a5-0a18-454f-a83b-2c9fc7cc0374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318862290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2318862290
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.4278685964
Short name T335
Test name
Test status
Simulation time 136940092 ps
CPU time 5.76 seconds
Started Apr 15 02:27:34 PM PDT 24
Finished Apr 15 02:27:40 PM PDT 24
Peak memory 211184 kb
Host smart-1768ebf4-39b3-4b4f-9b31-d02898ebfcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278685964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.4278685964
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1685622508
Short name T737
Test name
Test status
Simulation time 132910070 ps
CPU time 3.45 seconds
Started Apr 15 02:26:09 PM PDT 24
Finished Apr 15 02:26:13 PM PDT 24
Peak memory 209328 kb
Host smart-a11844fe-7f44-40c0-909d-9be06fd50b2f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685622508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1685622508
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2912857948
Short name T144
Test name
Test status
Simulation time 245319291 ps
CPU time 10.05 seconds
Started Apr 15 02:27:57 PM PDT 24
Finished Apr 15 02:28:08 PM PDT 24
Peak memory 222960 kb
Host smart-7e43a158-77f1-4414-af79-c68b8d1b94ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912857948 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2912857948
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1688711009
Short name T359
Test name
Test status
Simulation time 152802067 ps
CPU time 8.83 seconds
Started Apr 15 02:28:19 PM PDT 24
Finished Apr 15 02:28:29 PM PDT 24
Peak memory 215352 kb
Host smart-c43748e4-17ad-430e-b465-e1ab527c20d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688711009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1688711009
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2861544478
Short name T345
Test name
Test status
Simulation time 5426110386 ps
CPU time 129.67 seconds
Started Apr 15 02:28:23 PM PDT 24
Finished Apr 15 02:30:34 PM PDT 24
Peak memory 217108 kb
Host smart-96ee4714-0d9c-4361-8d86-c52953b1a9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861544478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2861544478
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3820357787
Short name T319
Test name
Test status
Simulation time 54833469 ps
CPU time 3.62 seconds
Started Apr 15 02:26:21 PM PDT 24
Finished Apr 15 02:26:26 PM PDT 24
Peak memory 214608 kb
Host smart-c3594e89-ee1a-494c-96b4-a3d16a97a157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820357787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3820357787
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_random.1380999788
Short name T228
Test name
Test status
Simulation time 2036489541 ps
CPU time 5.61 seconds
Started Apr 15 02:26:24 PM PDT 24
Finished Apr 15 02:26:30 PM PDT 24
Peak memory 210164 kb
Host smart-d09e4105-c1a6-421f-856d-c288c95f9025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380999788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1380999788
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4166574803
Short name T268
Test name
Test status
Simulation time 211650584 ps
CPU time 6.63 seconds
Started Apr 15 02:26:35 PM PDT 24
Finished Apr 15 02:26:43 PM PDT 24
Peak memory 209988 kb
Host smart-5cae8994-2193-4149-ae19-17c8099412d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166574803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4166574803
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.538360593
Short name T189
Test name
Test status
Simulation time 69923268 ps
CPU time 3.65 seconds
Started Apr 15 12:35:59 PM PDT 24
Finished Apr 15 12:36:04 PM PDT 24
Peak memory 214020 kb
Host smart-ea708404-bcfa-405c-9ff9-a1b9500b5453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538360593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.538360593
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.567747207
Short name T192
Test name
Test status
Simulation time 2317926193 ps
CPU time 15.77 seconds
Started Apr 15 12:36:03 PM PDT 24
Finished Apr 15 12:36:20 PM PDT 24
Peak memory 214104 kb
Host smart-9844ff8d-eb24-42d2-bad9-7e11b26c3fe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567747207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.567747207
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1395150020
Short name T186
Test name
Test status
Simulation time 572808979 ps
CPU time 4.6 seconds
Started Apr 15 12:36:05 PM PDT 24
Finished Apr 15 12:36:11 PM PDT 24
Peak memory 213888 kb
Host smart-cd21041a-b70c-4e04-b532-4e8621f3b05b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395150020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1395150020
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3986843434
Short name T182
Test name
Test status
Simulation time 333511550 ps
CPU time 11.37 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 209340 kb
Host smart-8cdedf5b-6b55-4eeb-98cc-a6ab1563b73a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986843434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3986843434
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1194557036
Short name T116
Test name
Test status
Simulation time 7928892753 ps
CPU time 68.99 seconds
Started Apr 15 02:25:53 PM PDT 24
Finished Apr 15 02:27:03 PM PDT 24
Peak memory 244648 kb
Host smart-2cb512ca-fd43-43b9-b89a-ea66a248def6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194557036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1194557036
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1435107418
Short name T93
Test name
Test status
Simulation time 110084509 ps
CPU time 3.7 seconds
Started Apr 15 02:25:59 PM PDT 24
Finished Apr 15 02:26:03 PM PDT 24
Peak memory 214632 kb
Host smart-3d0c2ee6-7e85-4f04-b64e-173d118f0bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435107418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1435107418
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3795885162
Short name T184
Test name
Test status
Simulation time 41652626 ps
CPU time 2.27 seconds
Started Apr 15 02:26:23 PM PDT 24
Finished Apr 15 02:26:26 PM PDT 24
Peak memory 210432 kb
Host smart-12a8b096-1884-49fd-b8ec-854988adeab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795885162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3795885162
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2220111418
Short name T109
Test name
Test status
Simulation time 1391472224 ps
CPU time 23.91 seconds
Started Apr 15 02:27:07 PM PDT 24
Finished Apr 15 02:27:32 PM PDT 24
Peak memory 217012 kb
Host smart-dca66280-8b82-4e8f-9ea2-d20b91153aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220111418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2220111418
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.963554347
Short name T200
Test name
Test status
Simulation time 144225113 ps
CPU time 5.3 seconds
Started Apr 15 02:27:42 PM PDT 24
Finished Apr 15 02:27:48 PM PDT 24
Peak memory 215276 kb
Host smart-55c092bc-3fe8-4109-bfa5-9e959b5c200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963554347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.963554347
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1830611450
Short name T248
Test name
Test status
Simulation time 333793676 ps
CPU time 3.24 seconds
Started Apr 15 02:25:50 PM PDT 24
Finished Apr 15 02:25:53 PM PDT 24
Peak memory 219320 kb
Host smart-7a1611d5-876d-4d12-be8e-a01142b54a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830611450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1830611450
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.483548709
Short name T316
Test name
Test status
Simulation time 1042260711 ps
CPU time 27.85 seconds
Started Apr 15 02:25:46 PM PDT 24
Finished Apr 15 02:26:14 PM PDT 24
Peak memory 208892 kb
Host smart-ebab9256-d0e1-4bb2-9ab2-15b56fa638d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483548709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.483548709
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.297389586
Short name T421
Test name
Test status
Simulation time 551820418 ps
CPU time 4.39 seconds
Started Apr 15 02:25:59 PM PDT 24
Finished Apr 15 02:26:04 PM PDT 24
Peak memory 214656 kb
Host smart-97cbe02e-f5cf-4a69-99e4-d2c7dce3650e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297389586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.297389586
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.4274706709
Short name T40
Test name
Test status
Simulation time 146149752 ps
CPU time 3.01 seconds
Started Apr 15 02:25:57 PM PDT 24
Finished Apr 15 02:26:01 PM PDT 24
Peak memory 209396 kb
Host smart-784ce220-efd6-43a9-98bd-3ba5046e72c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274706709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.4274706709
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.710274462
Short name T266
Test name
Test status
Simulation time 218087652 ps
CPU time 4.03 seconds
Started Apr 15 02:25:56 PM PDT 24
Finished Apr 15 02:26:01 PM PDT 24
Peak memory 214800 kb
Host smart-6eebb643-4239-46bc-861e-ba5296a27555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710274462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.710274462
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.909772712
Short name T339
Test name
Test status
Simulation time 800915581 ps
CPU time 9.17 seconds
Started Apr 15 02:27:04 PM PDT 24
Finished Apr 15 02:27:13 PM PDT 24
Peak memory 207828 kb
Host smart-86457527-95ca-4711-97c8-a51a1b739c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909772712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.909772712
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2662526354
Short name T12
Test name
Test status
Simulation time 512451535 ps
CPU time 3.52 seconds
Started Apr 15 02:27:16 PM PDT 24
Finished Apr 15 02:27:20 PM PDT 24
Peak memory 211016 kb
Host smart-acbbdae5-c300-4e5c-a1c8-58ef0e4f9427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662526354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2662526354
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1008755020
Short name T251
Test name
Test status
Simulation time 843345875 ps
CPU time 23.9 seconds
Started Apr 15 02:27:33 PM PDT 24
Finished Apr 15 02:27:58 PM PDT 24
Peak memory 217472 kb
Host smart-07a9fb4f-6242-4f2c-aa69-13b0c2525ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008755020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1008755020
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2945963251
Short name T723
Test name
Test status
Simulation time 4210180264 ps
CPU time 33.47 seconds
Started Apr 15 02:27:36 PM PDT 24
Finished Apr 15 02:28:10 PM PDT 24
Peak memory 215320 kb
Host smart-eb00486b-9c2e-43ca-8f22-af8e6857109a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945963251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2945963251
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.903148154
Short name T425
Test name
Test status
Simulation time 174724929 ps
CPU time 9.34 seconds
Started Apr 15 02:27:56 PM PDT 24
Finished Apr 15 02:28:05 PM PDT 24
Peak memory 214952 kb
Host smart-df1505bf-454c-4c2c-aef0-91f764af4cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903148154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.903148154
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3073558128
Short name T249
Test name
Test status
Simulation time 163934401 ps
CPU time 4.56 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:06 PM PDT 24
Peak memory 222004 kb
Host smart-f99e0d3e-b7d5-43de-95ab-59fd28a50bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073558128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3073558128
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.454380963
Short name T231
Test name
Test status
Simulation time 98747068 ps
CPU time 3.61 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:06 PM PDT 24
Peak memory 210420 kb
Host smart-867e1945-1749-4462-9112-7f9b2b88d3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454380963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.454380963
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3098727695
Short name T250
Test name
Test status
Simulation time 62168025 ps
CPU time 2.72 seconds
Started Apr 15 02:28:05 PM PDT 24
Finished Apr 15 02:28:09 PM PDT 24
Peak memory 214616 kb
Host smart-1cd55ad4-36f2-422f-be9e-d21b425433dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098727695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3098727695
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1001496504
Short name T314
Test name
Test status
Simulation time 265391845 ps
CPU time 6.31 seconds
Started Apr 15 02:28:32 PM PDT 24
Finished Apr 15 02:28:39 PM PDT 24
Peak memory 222756 kb
Host smart-f1ca6523-e655-4746-888e-96a600c8985a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001496504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1001496504
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1515569658
Short name T311
Test name
Test status
Simulation time 82926912 ps
CPU time 3.44 seconds
Started Apr 15 02:28:54 PM PDT 24
Finished Apr 15 02:28:59 PM PDT 24
Peak memory 214672 kb
Host smart-169aebd6-ec79-4d92-9f7d-c412a54f5163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515569658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1515569658
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2214493886
Short name T415
Test name
Test status
Simulation time 49315091 ps
CPU time 2.29 seconds
Started Apr 15 02:29:03 PM PDT 24
Finished Apr 15 02:29:06 PM PDT 24
Peak memory 214708 kb
Host smart-a696ea4c-fbd4-415a-b25d-774f28464973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214493886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2214493886
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2440724260
Short name T294
Test name
Test status
Simulation time 61100112 ps
CPU time 3.66 seconds
Started Apr 15 02:29:20 PM PDT 24
Finished Apr 15 02:29:25 PM PDT 24
Peak memory 211100 kb
Host smart-814fdf09-1dbb-49a4-8e8e-5b6c5986fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440724260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2440724260
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1665041956
Short name T240
Test name
Test status
Simulation time 5182163985 ps
CPU time 35.61 seconds
Started Apr 15 02:29:42 PM PDT 24
Finished Apr 15 02:30:18 PM PDT 24
Peak memory 222928 kb
Host smart-ad9a03f5-4b6a-410f-8fd2-cc109d185688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665041956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1665041956
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3891858693
Short name T256
Test name
Test status
Simulation time 2734114328 ps
CPU time 28.11 seconds
Started Apr 15 02:29:36 PM PDT 24
Finished Apr 15 02:30:06 PM PDT 24
Peak memory 215332 kb
Host smart-f50f0d7a-bc00-4b42-bd89-3477377ff660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891858693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3891858693
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.778543549
Short name T108
Test name
Test status
Simulation time 111756122 ps
CPU time 4.72 seconds
Started Apr 15 02:26:32 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 221340 kb
Host smart-1a40b7e0-f387-4b2a-b3cf-1b7d75284fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778543549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.778543549
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2614301153
Short name T1033
Test name
Test status
Simulation time 366191828 ps
CPU time 14.52 seconds
Started Apr 15 12:35:50 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 205900 kb
Host smart-8543a39f-c5ff-4673-a332-48adbe4a96e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614301153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
614301153
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2108486480
Short name T1041
Test name
Test status
Simulation time 2590866032 ps
CPU time 8.82 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:58 PM PDT 24
Peak memory 205884 kb
Host smart-5a326f04-9535-488e-ab7d-565a2aff63ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108486480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
108486480
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2755301683
Short name T1026
Test name
Test status
Simulation time 62851906 ps
CPU time 1.14 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:51 PM PDT 24
Peak memory 205832 kb
Host smart-2366ec2e-5880-454b-adab-45ca8c1deb83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755301683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
755301683
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.696493082
Short name T930
Test name
Test status
Simulation time 103134404 ps
CPU time 1.25 seconds
Started Apr 15 12:35:55 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 205952 kb
Host smart-697ce2b0-c127-4809-bed0-ac713686a43b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696493082 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.696493082
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2876744195
Short name T922
Test name
Test status
Simulation time 22902368 ps
CPU time 1.25 seconds
Started Apr 15 12:35:50 PM PDT 24
Finished Apr 15 12:35:52 PM PDT 24
Peak memory 205888 kb
Host smart-05293249-fd33-4e40-b9db-a78211662275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876744195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2876744195
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2627610543
Short name T1008
Test name
Test status
Simulation time 14144995 ps
CPU time 0.68 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:50 PM PDT 24
Peak memory 205444 kb
Host smart-667379f9-ce52-43fa-a207-7b1051c8ef0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627610543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2627610543
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.591306952
Short name T159
Test name
Test status
Simulation time 204983986 ps
CPU time 2.57 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:52 PM PDT 24
Peak memory 205972 kb
Host smart-86ccc6a5-376f-479f-af13-ebc6585cc65f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591306952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.591306952
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2543746581
Short name T1040
Test name
Test status
Simulation time 1696835098 ps
CPU time 32.69 seconds
Started Apr 15 12:35:49 PM PDT 24
Finished Apr 15 12:36:23 PM PDT 24
Peak memory 221192 kb
Host smart-4c8b4926-cc49-4ee6-8b7a-d6488b8070b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543746581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2543746581
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2188947596
Short name T1014
Test name
Test status
Simulation time 481045567 ps
CPU time 4.84 seconds
Started Apr 15 12:35:50 PM PDT 24
Finished Apr 15 12:35:56 PM PDT 24
Peak memory 214452 kb
Host smart-eb1e053b-f41e-43a2-83ce-eff7533db391
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188947596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2188947596
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1800555689
Short name T925
Test name
Test status
Simulation time 358084993 ps
CPU time 3.92 seconds
Started Apr 15 12:35:47 PM PDT 24
Finished Apr 15 12:35:52 PM PDT 24
Peak memory 214068 kb
Host smart-97e695ed-fdab-4553-9b8d-9e1106c9ecf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800555689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1800555689
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2458946929
Short name T982
Test name
Test status
Simulation time 176985402 ps
CPU time 4.42 seconds
Started Apr 15 12:35:51 PM PDT 24
Finished Apr 15 12:35:56 PM PDT 24
Peak memory 205776 kb
Host smart-435604fd-1086-4b61-bae0-b8e1a5ba3d2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458946929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
458946929
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2232124528
Short name T960
Test name
Test status
Simulation time 1280081621 ps
CPU time 17.16 seconds
Started Apr 15 12:35:49 PM PDT 24
Finished Apr 15 12:36:07 PM PDT 24
Peak memory 205800 kb
Host smart-c5db19f0-49b0-421c-811c-6c53c7c78a56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232124528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
232124528
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4056318261
Short name T1058
Test name
Test status
Simulation time 17329506 ps
CPU time 1.16 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:35:58 PM PDT 24
Peak memory 205888 kb
Host smart-eaae26a4-fc87-4c7a-8913-84dfc0206191
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056318261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.4
056318261
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.4197775740
Short name T1035
Test name
Test status
Simulation time 428753045 ps
CPU time 1.5 seconds
Started Apr 15 12:35:54 PM PDT 24
Finished Apr 15 12:35:56 PM PDT 24
Peak memory 214132 kb
Host smart-a8c02977-6dca-471c-913a-2905b4b9b60b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197775740 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.4197775740
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4073230448
Short name T920
Test name
Test status
Simulation time 90552014 ps
CPU time 1.26 seconds
Started Apr 15 12:36:14 PM PDT 24
Finished Apr 15 12:36:16 PM PDT 24
Peak memory 206032 kb
Host smart-651b00a8-6b50-45a4-b203-ffea9bc9afd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073230448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4073230448
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1273803213
Short name T939
Test name
Test status
Simulation time 73934516 ps
CPU time 0.76 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:50 PM PDT 24
Peak memory 205632 kb
Host smart-6eeeb6f4-416b-4dd9-81c3-46436cb2f53d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273803213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1273803213
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1507348246
Short name T929
Test name
Test status
Simulation time 419380460 ps
CPU time 3.46 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:53 PM PDT 24
Peak memory 205884 kb
Host smart-e965cdd7-804f-4ecf-b36f-a5874f47a47b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507348246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1507348246
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1939339203
Short name T1067
Test name
Test status
Simulation time 645045351 ps
CPU time 2.1 seconds
Started Apr 15 12:35:49 PM PDT 24
Finished Apr 15 12:35:52 PM PDT 24
Peak memory 214296 kb
Host smart-0cc06e63-a1f3-4616-8215-58ad3cedb923
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939339203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1939339203
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3033473442
Short name T1034
Test name
Test status
Simulation time 408930719 ps
CPU time 13.81 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:36:03 PM PDT 24
Peak memory 214636 kb
Host smart-bb28c1b0-5369-42da-8fb4-0728623fe176
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033473442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3033473442
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1897031044
Short name T1060
Test name
Test status
Simulation time 986492207 ps
CPU time 3.76 seconds
Started Apr 15 12:35:47 PM PDT 24
Finished Apr 15 12:35:52 PM PDT 24
Peak memory 222284 kb
Host smart-7bca73f0-8d92-48ed-85de-6a30ebe8dbd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897031044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1897031044
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3114332625
Short name T394
Test name
Test status
Simulation time 119472411 ps
CPU time 3.64 seconds
Started Apr 15 12:35:52 PM PDT 24
Finished Apr 15 12:35:56 PM PDT 24
Peak memory 209396 kb
Host smart-a9603333-f46c-4ca3-b417-2db77abfee5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114332625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3114332625
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2271661288
Short name T947
Test name
Test status
Simulation time 32700286 ps
CPU time 1.54 seconds
Started Apr 15 12:36:03 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 214200 kb
Host smart-d2585694-fb1e-4566-925e-071e6aea8e1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271661288 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2271661288
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1404227170
Short name T933
Test name
Test status
Simulation time 30548978 ps
CPU time 0.99 seconds
Started Apr 15 12:36:01 PM PDT 24
Finished Apr 15 12:36:03 PM PDT 24
Peak memory 205596 kb
Host smart-e0052fc6-8c3d-44a8-ad86-b6060e8dbed3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404227170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1404227170
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1555764031
Short name T1017
Test name
Test status
Simulation time 30126455 ps
CPU time 0.74 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:04 PM PDT 24
Peak memory 205544 kb
Host smart-7363a887-cd81-4c0c-bb11-64242e6e35fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555764031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1555764031
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1947289198
Short name T1045
Test name
Test status
Simulation time 179993291 ps
CPU time 3.95 seconds
Started Apr 15 12:36:03 PM PDT 24
Finished Apr 15 12:36:07 PM PDT 24
Peak memory 205900 kb
Host smart-a87ab6be-a2df-4acf-8d60-f06714916439
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947289198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1947289198
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3666777148
Short name T1054
Test name
Test status
Simulation time 439487792 ps
CPU time 4.16 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:07 PM PDT 24
Peak memory 214332 kb
Host smart-760acc84-f0da-4c1b-aca3-ce36a05b446b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666777148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3666777148
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2070131654
Short name T1050
Test name
Test status
Simulation time 428027010 ps
CPU time 14.44 seconds
Started Apr 15 12:36:00 PM PDT 24
Finished Apr 15 12:36:15 PM PDT 24
Peak memory 220292 kb
Host smart-8a1626be-f581-4b0a-bb9d-1b8bc1c07dee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070131654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2070131654
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1752702124
Short name T1036
Test name
Test status
Simulation time 374481886 ps
CPU time 2.38 seconds
Started Apr 15 12:35:57 PM PDT 24
Finished Apr 15 12:36:00 PM PDT 24
Peak memory 214124 kb
Host smart-e1c16b7a-320f-4e27-941b-7f09376cb302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752702124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1752702124
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2205755982
Short name T1011
Test name
Test status
Simulation time 99388358 ps
CPU time 1.87 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 214224 kb
Host smart-d96ffd40-63e3-48c7-922a-71f9bcf882be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205755982 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2205755982
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1754557501
Short name T1018
Test name
Test status
Simulation time 22082654 ps
CPU time 1.05 seconds
Started Apr 15 12:36:03 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 205652 kb
Host smart-02d168f9-17cf-49c3-bfa5-736b6215f12d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754557501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1754557501
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.179541346
Short name T923
Test name
Test status
Simulation time 27734067 ps
CPU time 0.7 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:03 PM PDT 24
Peak memory 205604 kb
Host smart-94e8dd81-629b-4750-bb10-d72a2cf5a513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179541346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.179541346
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2288538496
Short name T934
Test name
Test status
Simulation time 242032438 ps
CPU time 1.61 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 205920 kb
Host smart-9f1af594-bc12-476a-b661-6dd8bd902dd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288538496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2288538496
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2564747199
Short name T1064
Test name
Test status
Simulation time 168136497 ps
CPU time 2.4 seconds
Started Apr 15 12:36:07 PM PDT 24
Finished Apr 15 12:36:10 PM PDT 24
Peak memory 219152 kb
Host smart-eef0e10f-58cf-4eb2-8976-2d77ac2a3163
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564747199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2564747199
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2192228011
Short name T1013
Test name
Test status
Simulation time 280350654 ps
CPU time 8.11 seconds
Started Apr 15 12:36:05 PM PDT 24
Finished Apr 15 12:36:13 PM PDT 24
Peak memory 214328 kb
Host smart-11388f49-ba99-4bac-8a09-9d13eb2e016c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192228011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2192228011
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1848639417
Short name T1005
Test name
Test status
Simulation time 131598555 ps
CPU time 2.92 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:06 PM PDT 24
Peak memory 214048 kb
Host smart-d54e4dfe-6ab8-402d-8776-afffc23e4961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848639417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1848639417
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3950553677
Short name T1043
Test name
Test status
Simulation time 38586579 ps
CPU time 2.39 seconds
Started Apr 15 12:36:04 PM PDT 24
Finished Apr 15 12:36:07 PM PDT 24
Peak memory 214160 kb
Host smart-9aaced56-3197-4c64-b476-1da44c38db6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950553677 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3950553677
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1973790151
Short name T931
Test name
Test status
Simulation time 17586887 ps
CPU time 0.99 seconds
Started Apr 15 12:36:03 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 205664 kb
Host smart-e5ef7425-2c56-48cc-a640-12a53d9a40a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973790151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1973790151
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2994586835
Short name T962
Test name
Test status
Simulation time 50931451 ps
CPU time 0.75 seconds
Started Apr 15 12:36:05 PM PDT 24
Finished Apr 15 12:36:07 PM PDT 24
Peak memory 205616 kb
Host smart-98aa311d-214e-4dc6-8f0e-e4f7f961ba89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994586835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2994586835
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3693503765
Short name T1061
Test name
Test status
Simulation time 247985010 ps
CPU time 2.31 seconds
Started Apr 15 12:36:07 PM PDT 24
Finished Apr 15 12:36:10 PM PDT 24
Peak memory 205824 kb
Host smart-c35123f3-76d9-45ae-8379-b7ccd085ef74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693503765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3693503765
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1517406125
Short name T1059
Test name
Test status
Simulation time 110346620 ps
CPU time 3.76 seconds
Started Apr 15 12:36:03 PM PDT 24
Finished Apr 15 12:36:07 PM PDT 24
Peak memory 222532 kb
Host smart-865d48b0-d6eb-4224-addc-a527f9c7d181
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517406125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1517406125
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.291294494
Short name T128
Test name
Test status
Simulation time 230722607 ps
CPU time 4.92 seconds
Started Apr 15 12:36:05 PM PDT 24
Finished Apr 15 12:36:11 PM PDT 24
Peak memory 214228 kb
Host smart-74525658-c5e9-47dc-955d-e50c69cd6966
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291294494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.291294494
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3675140191
Short name T1074
Test name
Test status
Simulation time 96905040 ps
CPU time 2.06 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 214064 kb
Host smart-9d2457ec-e636-45cd-8e57-f99b70b23691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675140191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3675140191
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2602273124
Short name T924
Test name
Test status
Simulation time 48484765 ps
CPU time 1.68 seconds
Started Apr 15 12:36:08 PM PDT 24
Finished Apr 15 12:36:10 PM PDT 24
Peak memory 214276 kb
Host smart-4aedb5c4-b49f-4a05-91be-fb025a5fd3a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602273124 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2602273124
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3301566263
Short name T998
Test name
Test status
Simulation time 14594656 ps
CPU time 1.07 seconds
Started Apr 15 12:36:07 PM PDT 24
Finished Apr 15 12:36:09 PM PDT 24
Peak memory 205732 kb
Host smart-cfcc37dc-9b10-4aee-9521-3ac7f75bfc6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301566263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3301566263
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3466054332
Short name T1012
Test name
Test status
Simulation time 25462397 ps
CPU time 0.76 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:10 PM PDT 24
Peak memory 205532 kb
Host smart-1bd2bd24-3df3-4234-b1fa-87fa1d0c7f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466054332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3466054332
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2603132583
Short name T163
Test name
Test status
Simulation time 93620603 ps
CPU time 3.21 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:14 PM PDT 24
Peak memory 205908 kb
Host smart-df70965d-3b7c-423e-8ec5-1f1e469de34f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603132583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2603132583
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2687387816
Short name T1007
Test name
Test status
Simulation time 84933761 ps
CPU time 3.44 seconds
Started Apr 15 12:36:06 PM PDT 24
Finished Apr 15 12:36:10 PM PDT 24
Peak memory 214412 kb
Host smart-20622444-bcaa-4082-8d90-a5ecd1236e5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687387816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2687387816
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1591100149
Short name T928
Test name
Test status
Simulation time 79517183 ps
CPU time 1.89 seconds
Started Apr 15 12:36:22 PM PDT 24
Finished Apr 15 12:36:25 PM PDT 24
Peak memory 217084 kb
Host smart-e0ff0b4c-9c6f-4fef-aa39-1287824ea0aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591100149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1591100149
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3008455054
Short name T181
Test name
Test status
Simulation time 178491581 ps
CPU time 5.48 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:15 PM PDT 24
Peak memory 214128 kb
Host smart-b8b6f694-980d-4936-9d70-6cc9177b8c63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008455054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3008455054
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.760806530
Short name T915
Test name
Test status
Simulation time 197150264 ps
CPU time 2.3 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:12 PM PDT 24
Peak memory 214052 kb
Host smart-4d99d805-fc6a-4214-8719-87f6c650ba24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760806530 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.760806530
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1918390259
Short name T945
Test name
Test status
Simulation time 67779528 ps
CPU time 1.21 seconds
Started Apr 15 12:36:06 PM PDT 24
Finished Apr 15 12:36:08 PM PDT 24
Peak memory 205744 kb
Host smart-a2c21cbe-77f7-4475-acc8-7616d71ff242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918390259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1918390259
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3013680025
Short name T932
Test name
Test status
Simulation time 20213401 ps
CPU time 0.77 seconds
Started Apr 15 12:36:07 PM PDT 24
Finished Apr 15 12:36:08 PM PDT 24
Peak memory 205616 kb
Host smart-900d2721-1ba8-4e83-9af2-52b2511bbe9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013680025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3013680025
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3212780036
Short name T1049
Test name
Test status
Simulation time 199858022 ps
CPU time 1.54 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:11 PM PDT 24
Peak memory 205928 kb
Host smart-744f047f-6fcc-4517-b2dd-118905ba5b1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212780036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3212780036
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4180222948
Short name T135
Test name
Test status
Simulation time 91948426 ps
CPU time 2.82 seconds
Started Apr 15 12:36:11 PM PDT 24
Finished Apr 15 12:36:15 PM PDT 24
Peak memory 214340 kb
Host smart-a847f778-31f2-4e4b-a19f-d3915d841627
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180222948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.4180222948
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1628653885
Short name T1024
Test name
Test status
Simulation time 1581213273 ps
CPU time 9.4 seconds
Started Apr 15 12:36:08 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 214436 kb
Host smart-e9cfa41d-c053-40ca-843b-505b6299d728
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628653885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1628653885
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1943883249
Short name T909
Test name
Test status
Simulation time 120815353 ps
CPU time 1.59 seconds
Started Apr 15 12:36:07 PM PDT 24
Finished Apr 15 12:36:09 PM PDT 24
Peak memory 214088 kb
Host smart-e1ad3df8-0381-4180-acb4-e24e918c5f17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943883249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1943883249
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2062918257
Short name T190
Test name
Test status
Simulation time 479224956 ps
CPU time 9.25 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 209608 kb
Host smart-0ff78e04-3ea0-408c-8797-1a7add8eaf61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062918257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2062918257
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2918042620
Short name T993
Test name
Test status
Simulation time 121761352 ps
CPU time 1.29 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:12 PM PDT 24
Peak memory 205828 kb
Host smart-d68274ab-4bd5-4915-87ed-d16f1ad404fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918042620 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2918042620
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3229296261
Short name T1071
Test name
Test status
Simulation time 18374435 ps
CPU time 1.09 seconds
Started Apr 15 12:36:07 PM PDT 24
Finished Apr 15 12:36:09 PM PDT 24
Peak memory 205620 kb
Host smart-af8dc679-2699-4d83-8a8b-a692a95bb97e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229296261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3229296261
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1915023606
Short name T1037
Test name
Test status
Simulation time 46793504 ps
CPU time 0.77 seconds
Started Apr 15 12:36:07 PM PDT 24
Finished Apr 15 12:36:08 PM PDT 24
Peak memory 205616 kb
Host smart-d04ec269-a974-440b-a71f-05eadf9e2dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915023606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1915023606
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.858687490
Short name T1039
Test name
Test status
Simulation time 35417801 ps
CPU time 2.36 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:16 PM PDT 24
Peak memory 205928 kb
Host smart-23d4421b-aa6c-4f9b-be95-a310eae19da3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858687490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.858687490
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.557078643
Short name T985
Test name
Test status
Simulation time 207982668 ps
CPU time 3.91 seconds
Started Apr 15 12:36:06 PM PDT 24
Finished Apr 15 12:36:10 PM PDT 24
Peak memory 214300 kb
Host smart-0c1982c7-26f5-45bd-8efd-500160df1db9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557078643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.557078643
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2746099628
Short name T936
Test name
Test status
Simulation time 424736825 ps
CPU time 7.52 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 220236 kb
Host smart-0e645256-d123-404c-996d-e3360f7da5b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746099628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2746099628
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.120980014
Short name T990
Test name
Test status
Simulation time 136347270 ps
CPU time 2.12 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:12 PM PDT 24
Peak memory 215056 kb
Host smart-e73765f5-ea3f-45ab-abfb-ca42624c62f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120980014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.120980014
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1651102066
Short name T194
Test name
Test status
Simulation time 187598209 ps
CPU time 5.44 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:16 PM PDT 24
Peak memory 209304 kb
Host smart-b2a899ca-a5ad-4959-b9e1-2ae90f80ad6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651102066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1651102066
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.866033969
Short name T980
Test name
Test status
Simulation time 202296448 ps
CPU time 1.78 seconds
Started Apr 15 12:36:11 PM PDT 24
Finished Apr 15 12:36:14 PM PDT 24
Peak memory 214132 kb
Host smart-c88d9e82-baed-4646-9b0c-fabfea3c1604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866033969 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.866033969
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2919728227
Short name T958
Test name
Test status
Simulation time 29912206 ps
CPU time 0.9 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:12 PM PDT 24
Peak memory 205604 kb
Host smart-349faece-cfad-4945-81a9-4b7d9a35f06f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919728227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2919728227
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.659966525
Short name T970
Test name
Test status
Simulation time 11132969 ps
CPU time 0.74 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:15 PM PDT 24
Peak memory 205528 kb
Host smart-54c744fb-c2b8-4de3-ab92-a95a1dbd445f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659966525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.659966525
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3298365102
Short name T1070
Test name
Test status
Simulation time 43933594 ps
CPU time 2.11 seconds
Started Apr 15 12:36:15 PM PDT 24
Finished Apr 15 12:36:17 PM PDT 24
Peak memory 205872 kb
Host smart-fd40fcb1-7255-4500-b5c6-5fc55641bb68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298365102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3298365102
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1271341220
Short name T136
Test name
Test status
Simulation time 153774498 ps
CPU time 3.31 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:14 PM PDT 24
Peak memory 214432 kb
Host smart-b7a56927-7b02-4a53-9c2b-fdbe53afcfb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271341220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1271341220
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2241600215
Short name T1044
Test name
Test status
Simulation time 327021413 ps
CPU time 8.11 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:22 PM PDT 24
Peak memory 214384 kb
Host smart-b8b10b9d-1fad-48c1-9cbd-ae4cb59c1fea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241600215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2241600215
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1891819181
Short name T935
Test name
Test status
Simulation time 80667817 ps
CPU time 2.59 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:17 PM PDT 24
Peak memory 213988 kb
Host smart-44406448-f8dc-41b6-832c-c5b315f17a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891819181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1891819181
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.4138660787
Short name T187
Test name
Test status
Simulation time 270643666 ps
CPU time 9.82 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:23 PM PDT 24
Peak memory 213900 kb
Host smart-c42ce9ff-b589-4585-bb60-54044ee4c569
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138660787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.4138660787
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2137149516
Short name T981
Test name
Test status
Simulation time 111017844 ps
CPU time 1.93 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:16 PM PDT 24
Peak memory 214256 kb
Host smart-a68faed8-b7d3-43a7-8ccb-6cbb0d8de1b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137149516 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2137149516
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.377940595
Short name T949
Test name
Test status
Simulation time 72550828 ps
CPU time 1.31 seconds
Started Apr 15 12:36:12 PM PDT 24
Finished Apr 15 12:36:14 PM PDT 24
Peak memory 205816 kb
Host smart-ce84d80e-7a9b-4035-8162-aaee992dfe26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377940595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.377940595
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.922258249
Short name T964
Test name
Test status
Simulation time 11002435 ps
CPU time 0.91 seconds
Started Apr 15 12:36:11 PM PDT 24
Finished Apr 15 12:36:13 PM PDT 24
Peak memory 205612 kb
Host smart-af34c6aa-6680-492e-8a0c-775a4515e12c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922258249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.922258249
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3948150894
Short name T1042
Test name
Test status
Simulation time 418071055 ps
CPU time 2.57 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:16 PM PDT 24
Peak memory 205864 kb
Host smart-eaa429f7-e77f-49ab-97c0-516e3a575d04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948150894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3948150894
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1106377103
Short name T1048
Test name
Test status
Simulation time 202696587 ps
CPU time 4.13 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 214244 kb
Host smart-35573b3d-7f11-4953-b70c-8bda0f400107
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106377103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1106377103
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3645165162
Short name T1020
Test name
Test status
Simulation time 840009337 ps
CPU time 8.43 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 214204 kb
Host smart-30983b4f-3d11-45ee-a3a6-d3f32b60467e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645165162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3645165162
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2818415710
Short name T961
Test name
Test status
Simulation time 81360037 ps
CPU time 3.07 seconds
Started Apr 15 12:36:15 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 213944 kb
Host smart-9974be12-a082-43f0-81b9-949d92954300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818415710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2818415710
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4294647381
Short name T1055
Test name
Test status
Simulation time 124139866 ps
CPU time 5.12 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 209324 kb
Host smart-246e6afb-7505-4915-9335-13e5d23d429f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294647381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4294647381
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4265850270
Short name T989
Test name
Test status
Simulation time 70966497 ps
CPU time 1.38 seconds
Started Apr 15 12:36:12 PM PDT 24
Finished Apr 15 12:36:15 PM PDT 24
Peak memory 214084 kb
Host smart-35a74cea-7b11-442f-b5e9-401914ccd2a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265850270 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4265850270
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2984141861
Short name T966
Test name
Test status
Simulation time 12375370 ps
CPU time 1.07 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:15 PM PDT 24
Peak memory 205748 kb
Host smart-e73b281d-4cf1-47d3-98b9-6d7848c040c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984141861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2984141861
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2256746
Short name T1021
Test name
Test status
Simulation time 46866721 ps
CPU time 0.81 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:11 PM PDT 24
Peak memory 205456 kb
Host smart-e0156609-e181-47c4-91ef-b5076abd57fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2256746
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.809652473
Short name T1000
Test name
Test status
Simulation time 51753156 ps
CPU time 1.44 seconds
Started Apr 15 12:36:12 PM PDT 24
Finished Apr 15 12:36:14 PM PDT 24
Peak memory 205844 kb
Host smart-11115178-17c6-4d58-b17f-426fe2add14b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809652473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.809652473
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1048701457
Short name T1047
Test name
Test status
Simulation time 195654968 ps
CPU time 2.64 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:20 PM PDT 24
Peak memory 214368 kb
Host smart-7a6bc9aa-e210-4926-97fd-f7ff57c3ec6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048701457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1048701457
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2491211915
Short name T1073
Test name
Test status
Simulation time 273233670 ps
CPU time 7.53 seconds
Started Apr 15 12:36:13 PM PDT 24
Finished Apr 15 12:36:22 PM PDT 24
Peak memory 214424 kb
Host smart-9c8a8c7a-e504-4fe0-8e69-dac7f2480f3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491211915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2491211915
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3761520594
Short name T972
Test name
Test status
Simulation time 140929927 ps
CPU time 2.66 seconds
Started Apr 15 12:36:14 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 216136 kb
Host smart-46d55793-b343-49b2-adaa-aecb000c3b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761520594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3761520594
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3664424678
Short name T1004
Test name
Test status
Simulation time 31267550 ps
CPU time 2.33 seconds
Started Apr 15 12:36:17 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 214180 kb
Host smart-ea28bdda-ecbb-470b-8e42-e78b34203615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664424678 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3664424678
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3856205477
Short name T994
Test name
Test status
Simulation time 70177200 ps
CPU time 0.88 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 205720 kb
Host smart-21948288-ceb2-4ac0-942a-92fe3e2e1d46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856205477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3856205477
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2723488179
Short name T1006
Test name
Test status
Simulation time 11465229 ps
CPU time 0.66 seconds
Started Apr 15 12:36:14 PM PDT 24
Finished Apr 15 12:36:15 PM PDT 24
Peak memory 205520 kb
Host smart-904c05da-75a1-4b8b-b0d4-533bbc578907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723488179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2723488179
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2936356024
Short name T161
Test name
Test status
Simulation time 892653457 ps
CPU time 4.03 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 205764 kb
Host smart-c1d35067-10af-41dd-a479-9c9eccc877b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936356024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2936356024
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3628832268
Short name T948
Test name
Test status
Simulation time 436147578 ps
CPU time 14.98 seconds
Started Apr 15 12:36:12 PM PDT 24
Finished Apr 15 12:36:28 PM PDT 24
Peak memory 214260 kb
Host smart-03bb4751-f4c0-4143-9c8a-b31eeb81aef3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628832268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3628832268
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.103332659
Short name T996
Test name
Test status
Simulation time 57873939 ps
CPU time 2.49 seconds
Started Apr 15 12:36:11 PM PDT 24
Finished Apr 15 12:36:15 PM PDT 24
Peak memory 216132 kb
Host smart-37e58862-4981-4779-a0e5-07b2e835bce0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103332659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.103332659
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1786206227
Short name T1001
Test name
Test status
Simulation time 369098106 ps
CPU time 4.38 seconds
Started Apr 15 12:35:53 PM PDT 24
Finished Apr 15 12:35:58 PM PDT 24
Peak memory 205816 kb
Host smart-c8aba702-2ee4-47ee-9f7d-c7916d540182
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786206227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
786206227
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3614792913
Short name T1068
Test name
Test status
Simulation time 4087212028 ps
CPU time 24.57 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 205880 kb
Host smart-630e42eb-4267-498b-ad3b-df19dc09dcd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614792913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
614792913
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1660679693
Short name T171
Test name
Test status
Simulation time 51648579 ps
CPU time 0.94 seconds
Started Apr 15 12:35:59 PM PDT 24
Finished Apr 15 12:36:00 PM PDT 24
Peak memory 205656 kb
Host smart-9850acff-d613-49f7-8ff1-bd83a614713f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660679693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
660679693
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1538636128
Short name T937
Test name
Test status
Simulation time 35608479 ps
CPU time 1.46 seconds
Started Apr 15 12:35:55 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 214072 kb
Host smart-e75821b7-84cd-46bd-801e-28b20f401626
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538636128 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1538636128
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2718323841
Short name T160
Test name
Test status
Simulation time 32929426 ps
CPU time 1.27 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:35:59 PM PDT 24
Peak memory 205980 kb
Host smart-4d72fb23-991f-40a6-90ef-e07b1329924b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718323841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2718323841
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1271361538
Short name T912
Test name
Test status
Simulation time 111153266 ps
CPU time 0.75 seconds
Started Apr 15 12:35:57 PM PDT 24
Finished Apr 15 12:35:58 PM PDT 24
Peak memory 205468 kb
Host smart-85e2950a-49d0-4d09-b311-8bd0b3f1afb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271361538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1271361538
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3524879351
Short name T162
Test name
Test status
Simulation time 70908378 ps
CPU time 2.81 seconds
Started Apr 15 12:35:55 PM PDT 24
Finished Apr 15 12:35:59 PM PDT 24
Peak memory 205844 kb
Host smart-46c9bfcb-3896-45f7-808b-acaa092ea36d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524879351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3524879351
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.303548669
Short name T138
Test name
Test status
Simulation time 166696979 ps
CPU time 5.21 seconds
Started Apr 15 12:35:50 PM PDT 24
Finished Apr 15 12:35:56 PM PDT 24
Peak memory 214328 kb
Host smart-06e0bce4-acc2-42de-8d5a-3325dfb4ef8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303548669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.303548669
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3532689395
Short name T971
Test name
Test status
Simulation time 310320424 ps
CPU time 4.37 seconds
Started Apr 15 12:35:54 PM PDT 24
Finished Apr 15 12:35:59 PM PDT 24
Peak memory 214224 kb
Host smart-9356fe7c-e210-4775-9342-03902825a84c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532689395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3532689395
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.363771298
Short name T959
Test name
Test status
Simulation time 104453913 ps
CPU time 1.82 seconds
Started Apr 15 12:35:57 PM PDT 24
Finished Apr 15 12:35:59 PM PDT 24
Peak memory 222136 kb
Host smart-7e89045e-d85d-402c-b6f2-025f280a6899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363771298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.363771298
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1230826649
Short name T914
Test name
Test status
Simulation time 30571452 ps
CPU time 0.7 seconds
Started Apr 15 12:36:18 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 205544 kb
Host smart-b0ffc2c1-c550-44e0-ba92-eb101af561c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230826649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1230826649
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1667069861
Short name T950
Test name
Test status
Simulation time 42911344 ps
CPU time 0.83 seconds
Started Apr 15 12:36:17 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 205620 kb
Host smart-281e51fb-ef95-44a9-b571-a9dee12a68ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667069861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1667069861
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.4229370015
Short name T984
Test name
Test status
Simulation time 10628316 ps
CPU time 0.74 seconds
Started Apr 15 12:36:19 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 205564 kb
Host smart-092b4dde-904f-4928-995b-016ff7a4bace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229370015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.4229370015
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.502273687
Short name T1029
Test name
Test status
Simulation time 13522314 ps
CPU time 0.86 seconds
Started Apr 15 12:36:20 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 205636 kb
Host smart-f911ea14-058b-41d8-a5d3-cb28ab1d64f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502273687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.502273687
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2963601674
Short name T942
Test name
Test status
Simulation time 12425158 ps
CPU time 0.69 seconds
Started Apr 15 12:36:15 PM PDT 24
Finished Apr 15 12:36:16 PM PDT 24
Peak memory 205460 kb
Host smart-947fe87c-9917-4648-bb04-1f12ff6d1d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963601674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2963601674
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3557925246
Short name T921
Test name
Test status
Simulation time 41597298 ps
CPU time 0.85 seconds
Started Apr 15 12:36:18 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 205384 kb
Host smart-09dbdebf-fe3d-4db5-b053-a0a49d54c837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557925246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3557925246
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3535018333
Short name T1053
Test name
Test status
Simulation time 174062454 ps
CPU time 0.87 seconds
Started Apr 15 12:36:19 PM PDT 24
Finished Apr 15 12:36:20 PM PDT 24
Peak memory 205600 kb
Host smart-f3f55a12-5967-43cb-bb35-f0ad8bd920d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535018333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3535018333
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4185712953
Short name T1057
Test name
Test status
Simulation time 11366986 ps
CPU time 0.8 seconds
Started Apr 15 12:36:19 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 205516 kb
Host smart-01c53aa8-aa59-47ac-9e5b-4658164b3ff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185712953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4185712953
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2896482211
Short name T907
Test name
Test status
Simulation time 19455672 ps
CPU time 0.73 seconds
Started Apr 15 12:36:20 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 205524 kb
Host smart-beb9991f-635c-4552-b60f-70ce1c192de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896482211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2896482211
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1489550475
Short name T938
Test name
Test status
Simulation time 21248100 ps
CPU time 0.72 seconds
Started Apr 15 12:36:20 PM PDT 24
Finished Apr 15 12:36:22 PM PDT 24
Peak memory 205524 kb
Host smart-cd1adb66-0fa0-433d-8168-a663fd968263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489550475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1489550475
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1289995753
Short name T973
Test name
Test status
Simulation time 133931084 ps
CPU time 7.65 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 205876 kb
Host smart-787cc770-c897-45eb-a838-e7dcefba189a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289995753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
289995753
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.4104214357
Short name T983
Test name
Test status
Simulation time 907490418 ps
CPU time 25.22 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:24 PM PDT 24
Peak memory 205824 kb
Host smart-3bc801ee-a785-4868-a44d-5d52d53ae15e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104214357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.4
104214357
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4262620905
Short name T957
Test name
Test status
Simulation time 43270904 ps
CPU time 0.94 seconds
Started Apr 15 12:36:00 PM PDT 24
Finished Apr 15 12:36:02 PM PDT 24
Peak memory 205660 kb
Host smart-7820b61a-7b88-4159-ad28-be41fc5672fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262620905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
262620905
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.198796602
Short name T954
Test name
Test status
Simulation time 16284338 ps
CPU time 1.12 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:35:58 PM PDT 24
Peak memory 205912 kb
Host smart-5ebfa132-90de-4324-b642-e67fee64d014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198796602 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.198796602
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3515913966
Short name T1032
Test name
Test status
Simulation time 42768004 ps
CPU time 1.39 seconds
Started Apr 15 12:35:54 PM PDT 24
Finished Apr 15 12:35:56 PM PDT 24
Peak memory 205788 kb
Host smart-5733d8ec-ed4d-4daa-aa58-6dd8292adab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515913966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3515913966
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1384959697
Short name T969
Test name
Test status
Simulation time 39936868 ps
CPU time 0.75 seconds
Started Apr 15 12:35:51 PM PDT 24
Finished Apr 15 12:35:52 PM PDT 24
Peak memory 205608 kb
Host smart-7d9223a4-282e-44c6-9eae-f90ed5fe572d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384959697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1384959697
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3741197955
Short name T941
Test name
Test status
Simulation time 67979632 ps
CPU time 2.61 seconds
Started Apr 15 12:35:54 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 205824 kb
Host smart-ae15fed2-e98d-4227-9f87-9ed7d0c869d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741197955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3741197955
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1192331555
Short name T955
Test name
Test status
Simulation time 508459837 ps
CPU time 2.34 seconds
Started Apr 15 12:35:54 PM PDT 24
Finished Apr 15 12:35:56 PM PDT 24
Peak memory 214340 kb
Host smart-687687f3-ce44-4491-a226-cbeda10d48be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192331555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1192331555
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2993336421
Short name T995
Test name
Test status
Simulation time 299008011 ps
CPU time 4.36 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 214360 kb
Host smart-13398dbc-60cc-451e-90a1-56fa5cf91ce5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993336421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2993336421
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3070202595
Short name T951
Test name
Test status
Simulation time 125163495 ps
CPU time 3.01 seconds
Started Apr 15 12:35:51 PM PDT 24
Finished Apr 15 12:35:55 PM PDT 24
Peak memory 217096 kb
Host smart-e7e7e045-1500-4ed9-be61-7b4b0a08db39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070202595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3070202595
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3039976096
Short name T174
Test name
Test status
Simulation time 481265251 ps
CPU time 5.28 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:36:02 PM PDT 24
Peak memory 209328 kb
Host smart-1d4d6973-446e-4bcc-9ef6-1a6c5b8dd06b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039976096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3039976096
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2340192084
Short name T956
Test name
Test status
Simulation time 19206178 ps
CPU time 0.73 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 205572 kb
Host smart-84dac4ad-a92c-4c52-97c5-7feb32953ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340192084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2340192084
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2441370776
Short name T1028
Test name
Test status
Simulation time 22633429 ps
CPU time 0.67 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 205536 kb
Host smart-150ce27e-ae7a-4994-b5d0-066f6c30fdc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441370776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2441370776
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3222228236
Short name T1025
Test name
Test status
Simulation time 37463234 ps
CPU time 0.68 seconds
Started Apr 15 12:36:19 PM PDT 24
Finished Apr 15 12:36:26 PM PDT 24
Peak memory 205504 kb
Host smart-bb49612d-2185-40d7-90c5-a2e56a9da12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222228236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3222228236
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2919349864
Short name T952
Test name
Test status
Simulation time 10267168 ps
CPU time 0.89 seconds
Started Apr 15 12:36:18 PM PDT 24
Finished Apr 15 12:36:20 PM PDT 24
Peak memory 205424 kb
Host smart-2b6ec80b-a59c-4c3d-8559-1e53abfef3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919349864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2919349864
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4231499541
Short name T1027
Test name
Test status
Simulation time 35162886 ps
CPU time 0.71 seconds
Started Apr 15 12:36:32 PM PDT 24
Finished Apr 15 12:36:33 PM PDT 24
Peak memory 205612 kb
Host smart-a2b604bf-9770-4d8b-9d67-3b52e0e71157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231499541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.4231499541
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.268495825
Short name T926
Test name
Test status
Simulation time 57286864 ps
CPU time 0.74 seconds
Started Apr 15 12:36:19 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 205436 kb
Host smart-a6ad8b75-0bda-4466-baaa-fef5905983fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268495825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.268495825
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2397696546
Short name T975
Test name
Test status
Simulation time 57959304 ps
CPU time 0.69 seconds
Started Apr 15 12:36:18 PM PDT 24
Finished Apr 15 12:36:20 PM PDT 24
Peak memory 205560 kb
Host smart-bc3e709c-b592-4d55-bede-4cd9f8475e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397696546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2397696546
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3725594521
Short name T979
Test name
Test status
Simulation time 11743995 ps
CPU time 0.72 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:17 PM PDT 24
Peak memory 205532 kb
Host smart-a955e4c7-f17a-4e5f-a556-085907da1c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725594521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3725594521
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2477029729
Short name T991
Test name
Test status
Simulation time 10746560 ps
CPU time 0.8 seconds
Started Apr 15 12:36:17 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 205520 kb
Host smart-2499633a-6cf1-400e-8ab6-e24ec21713e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477029729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2477029729
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.982237676
Short name T1072
Test name
Test status
Simulation time 45162637 ps
CPU time 0.74 seconds
Started Apr 15 12:36:17 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 205604 kb
Host smart-3bcd08f4-1d54-4c2d-aec5-557bc3e5cc73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982237676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.982237676
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3638221621
Short name T1023
Test name
Test status
Simulation time 508043261 ps
CPU time 8.39 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:11 PM PDT 24
Peak memory 205848 kb
Host smart-626beada-8686-4658-afbe-0258c0edb353
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638221621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
638221621
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2088187418
Short name T944
Test name
Test status
Simulation time 2172238328 ps
CPU time 8.83 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:07 PM PDT 24
Peak memory 205868 kb
Host smart-7bac3b7e-8023-4ec3-87de-a2766ebf14b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088187418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
088187418
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.984546607
Short name T965
Test name
Test status
Simulation time 18525752 ps
CPU time 1.07 seconds
Started Apr 15 12:35:55 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 205824 kb
Host smart-9a627bb6-0355-4867-ab86-3f21f8897559
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984546607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.984546607
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2145089122
Short name T1010
Test name
Test status
Simulation time 55733102 ps
CPU time 1.6 seconds
Started Apr 15 12:35:59 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 214104 kb
Host smart-56d4823a-ff79-41dc-9832-2674ed265d10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145089122 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2145089122
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.830330971
Short name T1065
Test name
Test status
Simulation time 44095514 ps
CPU time 0.9 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:35:59 PM PDT 24
Peak memory 205652 kb
Host smart-46918435-b353-4bdb-b4cd-254f118f8c8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830330971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.830330971
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1023826464
Short name T953
Test name
Test status
Simulation time 15615831 ps
CPU time 0.87 seconds
Started Apr 15 12:36:00 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 205632 kb
Host smart-4118b3a6-cdf6-4e85-be89-ab19a6ee3e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023826464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1023826464
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2019491726
Short name T164
Test name
Test status
Simulation time 516297565 ps
CPU time 4.87 seconds
Started Apr 15 12:35:57 PM PDT 24
Finished Apr 15 12:36:03 PM PDT 24
Peak memory 205904 kb
Host smart-0803e9fb-288d-47df-b72c-bf7bd6a0ce68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019491726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2019491726
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2683777643
Short name T137
Test name
Test status
Simulation time 93943218 ps
CPU time 2.44 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 214352 kb
Host smart-215ece7a-6837-4d1d-bafe-fe6f8c1e4361
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683777643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2683777643
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4282805060
Short name T130
Test name
Test status
Simulation time 600033356 ps
CPU time 5.88 seconds
Started Apr 15 12:35:59 PM PDT 24
Finished Apr 15 12:36:06 PM PDT 24
Peak memory 220240 kb
Host smart-31b4c9c1-91e3-4a6e-ad0d-5a83de0e72b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282805060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4282805060
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1663345071
Short name T967
Test name
Test status
Simulation time 723334238 ps
CPU time 3.89 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:03 PM PDT 24
Peak memory 217044 kb
Host smart-038dbf44-1a10-4a78-adc6-9a88be031617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663345071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1663345071
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3216119811
Short name T1015
Test name
Test status
Simulation time 41302379 ps
CPU time 0.73 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:17 PM PDT 24
Peak memory 205524 kb
Host smart-fb7dfea0-8bb6-4a07-bdf4-06f16baa4762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216119811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3216119811
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3838037126
Short name T1003
Test name
Test status
Simulation time 44311147 ps
CPU time 0.82 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:23 PM PDT 24
Peak memory 205520 kb
Host smart-9375d0ea-c931-4712-98b8-9f9af82bd4ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838037126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3838037126
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2106071652
Short name T976
Test name
Test status
Simulation time 9970257 ps
CPU time 0.69 seconds
Started Apr 15 12:36:17 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 205596 kb
Host smart-4e7036a4-8054-4e20-b48c-499da5b02b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106071652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2106071652
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.748789129
Short name T917
Test name
Test status
Simulation time 37452488 ps
CPU time 0.7 seconds
Started Apr 15 12:36:19 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 205512 kb
Host smart-552469f9-adf3-478e-9bac-271e02759c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748789129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.748789129
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.536014845
Short name T999
Test name
Test status
Simulation time 11270672 ps
CPU time 0.8 seconds
Started Apr 15 12:36:17 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 205508 kb
Host smart-49f2e221-5fe6-4858-927c-0f856517de04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536014845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.536014845
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2379685633
Short name T911
Test name
Test status
Simulation time 9331448 ps
CPU time 0.77 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 205548 kb
Host smart-258f4023-40ec-43f7-a31e-c779494230f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379685633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2379685633
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.425173683
Short name T1066
Test name
Test status
Simulation time 26186688 ps
CPU time 0.67 seconds
Started Apr 15 12:36:16 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 205540 kb
Host smart-99f914ac-69c4-4160-80fc-ab22797b65de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425173683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.425173683
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2928903592
Short name T1016
Test name
Test status
Simulation time 9420613 ps
CPU time 0.72 seconds
Started Apr 15 12:36:18 PM PDT 24
Finished Apr 15 12:36:20 PM PDT 24
Peak memory 205440 kb
Host smart-bff0b4c3-a0a4-4fe9-b59e-16d08d9e4cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928903592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2928903592
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3942224965
Short name T1046
Test name
Test status
Simulation time 23568884 ps
CPU time 1.05 seconds
Started Apr 15 12:36:17 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 205724 kb
Host smart-ad74e266-cc4c-43c6-87ee-0de705ae656a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942224965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3942224965
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4080733607
Short name T963
Test name
Test status
Simulation time 8725474 ps
CPU time 0.7 seconds
Started Apr 15 12:36:17 PM PDT 24
Finished Apr 15 12:36:19 PM PDT 24
Peak memory 205468 kb
Host smart-e8e1197a-1b90-4765-a021-07f47081ab4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080733607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4080733607
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1586600401
Short name T943
Test name
Test status
Simulation time 43600509 ps
CPU time 2.05 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 217096 kb
Host smart-fd097906-cfef-49a7-8d82-fc870797776e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586600401 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1586600401
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1916972428
Short name T1022
Test name
Test status
Simulation time 49270872 ps
CPU time 1.2 seconds
Started Apr 15 12:35:59 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 205836 kb
Host smart-8ac7efc8-8f23-4d38-a612-183a88026922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916972428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1916972428
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2380338246
Short name T1062
Test name
Test status
Simulation time 11501747 ps
CPU time 0.82 seconds
Started Apr 15 12:35:51 PM PDT 24
Finished Apr 15 12:35:53 PM PDT 24
Peak memory 205544 kb
Host smart-13c2db8a-9aa8-4fea-a31d-613192e8e3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380338246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2380338246
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3424869184
Short name T946
Test name
Test status
Simulation time 161809818 ps
CPU time 1.69 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:12 PM PDT 24
Peak memory 205916 kb
Host smart-7d5e6a49-8ee7-4b80-a6aa-16e4471636a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424869184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3424869184
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.522880145
Short name T134
Test name
Test status
Simulation time 159264207 ps
CPU time 4.07 seconds
Started Apr 15 12:35:59 PM PDT 24
Finished Apr 15 12:36:04 PM PDT 24
Peak memory 214204 kb
Host smart-173a2f97-ff30-4688-91bf-918ac885112f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522880145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.522880145
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2202852272
Short name T968
Test name
Test status
Simulation time 458570372 ps
CPU time 8.96 seconds
Started Apr 15 12:35:53 PM PDT 24
Finished Apr 15 12:36:02 PM PDT 24
Peak memory 214244 kb
Host smart-09ce48fa-869a-4673-a9ed-cedd5f2b7923
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202852272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2202852272
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1855850383
Short name T919
Test name
Test status
Simulation time 305476566 ps
CPU time 3.16 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:36:00 PM PDT 24
Peak memory 213988 kb
Host smart-0fb9e7e0-dfe7-4a07-9a56-6834088e9fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855850383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1855850383
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.325291525
Short name T940
Test name
Test status
Simulation time 82755710 ps
CPU time 1.15 seconds
Started Apr 15 12:36:00 PM PDT 24
Finished Apr 15 12:36:02 PM PDT 24
Peak memory 205716 kb
Host smart-c71221ae-cbf4-4fe5-b95a-d63364fe65c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325291525 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.325291525
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1553390813
Short name T910
Test name
Test status
Simulation time 38027282 ps
CPU time 1.16 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:12 PM PDT 24
Peak memory 205828 kb
Host smart-7af43626-5e8a-46b0-8b44-eacf992118c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553390813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1553390813
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4173835376
Short name T1063
Test name
Test status
Simulation time 14695625 ps
CPU time 0.8 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:35:58 PM PDT 24
Peak memory 205540 kb
Host smart-d4eeb8af-9654-40e8-aa77-bc9d43998505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173835376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4173835376
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1637795858
Short name T165
Test name
Test status
Simulation time 238153363 ps
CPU time 2.39 seconds
Started Apr 15 12:35:57 PM PDT 24
Finished Apr 15 12:36:00 PM PDT 24
Peak memory 205824 kb
Host smart-8cd2b6e2-d45d-4045-9e92-f18a848e366f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637795858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1637795858
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4044921230
Short name T1019
Test name
Test status
Simulation time 770023621 ps
CPU time 3.41 seconds
Started Apr 15 12:35:57 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 214584 kb
Host smart-beaab3cc-44cd-4915-bd55-b5a0b23b666b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044921230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4044921230
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3172930700
Short name T1069
Test name
Test status
Simulation time 812936916 ps
CPU time 15.3 seconds
Started Apr 15 12:35:57 PM PDT 24
Finished Apr 15 12:36:13 PM PDT 24
Peak memory 214276 kb
Host smart-b14e1e3d-bb1a-4a92-8915-167abafd49b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172930700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3172930700
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3769239477
Short name T974
Test name
Test status
Simulation time 77884521 ps
CPU time 1.91 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 205740 kb
Host smart-0d64b40c-8931-4acf-bb5b-dd0c7cd9e633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769239477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3769239477
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3282677568
Short name T193
Test name
Test status
Simulation time 1082057241 ps
CPU time 11.09 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:14 PM PDT 24
Peak memory 209456 kb
Host smart-a968b24b-f19d-4444-abd5-6975ca01ccc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282677568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3282677568
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1966086707
Short name T1038
Test name
Test status
Simulation time 91592784 ps
CPU time 1.32 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:12 PM PDT 24
Peak memory 205616 kb
Host smart-c1c7aa64-a8ba-4fca-be60-02bdf468fb05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966086707 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1966086707
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2448937320
Short name T988
Test name
Test status
Simulation time 31238096 ps
CPU time 1.24 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:00 PM PDT 24
Peak memory 205852 kb
Host smart-f64a1a3a-5ff7-4222-8e88-ab5bfcc91ecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448937320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2448937320
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.843891068
Short name T927
Test name
Test status
Simulation time 18634176 ps
CPU time 0.76 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:04 PM PDT 24
Peak memory 205440 kb
Host smart-78b7e912-bb12-447c-9cb0-65e8e8054448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843891068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.843891068
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1912865341
Short name T1009
Test name
Test status
Simulation time 1965678078 ps
CPU time 4.05 seconds
Started Apr 15 12:35:57 PM PDT 24
Finished Apr 15 12:36:02 PM PDT 24
Peak memory 205688 kb
Host smart-40ffd692-c8d6-4dc6-8d63-da4b6eedef71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912865341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1912865341
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.45737513
Short name T133
Test name
Test status
Simulation time 89143929 ps
CPU time 2.81 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:13 PM PDT 24
Peak memory 219160 kb
Host smart-3738aca7-e735-48b7-bc0a-3beff70c27ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45737513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_
reg_errors.45737513
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3464076318
Short name T992
Test name
Test status
Simulation time 911344253 ps
CPU time 5.6 seconds
Started Apr 15 12:36:00 PM PDT 24
Finished Apr 15 12:36:06 PM PDT 24
Peak memory 214240 kb
Host smart-235cc203-c171-4095-b448-0150e4617246
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464076318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3464076318
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1285964575
Short name T916
Test name
Test status
Simulation time 39979294 ps
CPU time 1.8 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:11 PM PDT 24
Peak memory 214100 kb
Host smart-1b23f79b-d79c-4c63-a5f5-633d38ac4339
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285964575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1285964575
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1974821936
Short name T191
Test name
Test status
Simulation time 157164953 ps
CPU time 5.34 seconds
Started Apr 15 12:36:00 PM PDT 24
Finished Apr 15 12:36:06 PM PDT 24
Peak memory 209408 kb
Host smart-75d4ffc5-03ba-436a-be7c-c554b6afb193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974821936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1974821936
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1273483807
Short name T1051
Test name
Test status
Simulation time 56219066 ps
CPU time 1.39 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:00 PM PDT 24
Peak memory 204924 kb
Host smart-1cedc2b9-ecf7-4888-b531-41d01e1e69a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273483807 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1273483807
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.57313233
Short name T978
Test name
Test status
Simulation time 87411051 ps
CPU time 1.07 seconds
Started Apr 15 12:36:02 PM PDT 24
Finished Apr 15 12:36:04 PM PDT 24
Peak memory 205840 kb
Host smart-27cbfa60-9996-45c9-bbc8-ae0221873b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57313233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.57313233
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1832738311
Short name T908
Test name
Test status
Simulation time 38927406 ps
CPU time 0.79 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:00 PM PDT 24
Peak memory 205532 kb
Host smart-0f78ce14-890a-4a19-b166-6efbe944bcb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832738311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1832738311
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2199961358
Short name T918
Test name
Test status
Simulation time 67590617 ps
CPU time 2.41 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:02 PM PDT 24
Peak memory 205800 kb
Host smart-fe482127-0924-4ad5-8075-a48a79a07fcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199961358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2199961358
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2823943195
Short name T1031
Test name
Test status
Simulation time 131434502 ps
CPU time 2.82 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:02 PM PDT 24
Peak memory 214320 kb
Host smart-6f2efea6-9784-4de0-a278-1beb21242271
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823943195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2823943195
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1968988628
Short name T997
Test name
Test status
Simulation time 447814117 ps
CPU time 9.29 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:20 PM PDT 24
Peak memory 214436 kb
Host smart-8c3f25af-5666-44d6-b65b-936de2429a4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968988628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1968988628
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3687784584
Short name T1052
Test name
Test status
Simulation time 367160451 ps
CPU time 3.2 seconds
Started Apr 15 12:35:59 PM PDT 24
Finished Apr 15 12:36:03 PM PDT 24
Peak memory 215128 kb
Host smart-98be5274-0285-4a00-bb35-faabdd3900e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687784584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3687784584
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1173956428
Short name T188
Test name
Test status
Simulation time 831653895 ps
CPU time 14.49 seconds
Started Apr 15 12:35:58 PM PDT 24
Finished Apr 15 12:36:13 PM PDT 24
Peak memory 213012 kb
Host smart-b20c9443-40e5-4be6-b07b-b3b414c37844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173956428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1173956428
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2734251471
Short name T986
Test name
Test status
Simulation time 99163172 ps
CPU time 1.17 seconds
Started Apr 15 12:36:01 PM PDT 24
Finished Apr 15 12:36:03 PM PDT 24
Peak memory 205968 kb
Host smart-1ed0461a-a83d-42df-b448-0d3d8cf932da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734251471 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2734251471
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4227595306
Short name T1056
Test name
Test status
Simulation time 30169999 ps
CPU time 1.16 seconds
Started Apr 15 12:35:57 PM PDT 24
Finished Apr 15 12:35:59 PM PDT 24
Peak memory 205816 kb
Host smart-1ab8de8f-0d4a-4b6a-8343-2ca9da0e58fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227595306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4227595306
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3688575502
Short name T913
Test name
Test status
Simulation time 18723395 ps
CPU time 0.79 seconds
Started Apr 15 12:36:01 PM PDT 24
Finished Apr 15 12:36:03 PM PDT 24
Peak memory 205540 kb
Host smart-58662a2d-639d-48d0-9585-a30ce68d9bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688575502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3688575502
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.188157315
Short name T987
Test name
Test status
Simulation time 104416634 ps
CPU time 1.5 seconds
Started Apr 15 12:36:09 PM PDT 24
Finished Apr 15 12:36:12 PM PDT 24
Peak memory 205708 kb
Host smart-a630fdd5-6354-4be4-b2e1-c160d46d5632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188157315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.188157315
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3487147153
Short name T977
Test name
Test status
Simulation time 586546917 ps
CPU time 4.81 seconds
Started Apr 15 12:35:59 PM PDT 24
Finished Apr 15 12:36:05 PM PDT 24
Peak memory 214392 kb
Host smart-f3c86b1c-333d-4bb2-a2f6-6d091c81f4bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487147153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3487147153
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3692829546
Short name T1002
Test name
Test status
Simulation time 134580182 ps
CPU time 3.69 seconds
Started Apr 15 12:36:10 PM PDT 24
Finished Apr 15 12:36:14 PM PDT 24
Peak memory 214408 kb
Host smart-e628f232-56d4-47d3-8ef7-cdfcd206a009
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692829546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3692829546
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3209323381
Short name T1030
Test name
Test status
Simulation time 70537761 ps
CPU time 2.68 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:36:00 PM PDT 24
Peak memory 214048 kb
Host smart-66d91618-5bf8-4b8b-994a-4a0f4d8742e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209323381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3209323381
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2978016708
Short name T624
Test name
Test status
Simulation time 72544772 ps
CPU time 0.77 seconds
Started Apr 15 02:25:54 PM PDT 24
Finished Apr 15 02:25:56 PM PDT 24
Peak memory 206276 kb
Host smart-d053e3e2-ab34-4ecf-988b-ddac9bb00dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978016708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2978016708
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2438357779
Short name T725
Test name
Test status
Simulation time 42860368 ps
CPU time 2.44 seconds
Started Apr 15 02:25:50 PM PDT 24
Finished Apr 15 02:25:53 PM PDT 24
Peak memory 208544 kb
Host smart-af9db1f1-11ce-4198-9471-a2a867b68e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438357779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2438357779
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3402856572
Short name T625
Test name
Test status
Simulation time 130160550 ps
CPU time 5.76 seconds
Started Apr 15 02:25:50 PM PDT 24
Finished Apr 15 02:25:57 PM PDT 24
Peak memory 210036 kb
Host smart-03600b0f-9011-4d34-bde6-2dcbb29dc4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402856572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3402856572
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1993007118
Short name T688
Test name
Test status
Simulation time 257023292 ps
CPU time 5.12 seconds
Started Apr 15 02:25:49 PM PDT 24
Finished Apr 15 02:25:55 PM PDT 24
Peak memory 210732 kb
Host smart-5655dde2-44cb-4d6f-b610-b3f96073e6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993007118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1993007118
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.3004975899
Short name T483
Test name
Test status
Simulation time 65641223 ps
CPU time 4.3 seconds
Started Apr 15 02:25:44 PM PDT 24
Finished Apr 15 02:25:49 PM PDT 24
Peak memory 208432 kb
Host smart-e541a507-2265-4521-a7d4-0d9d9fefbdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004975899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3004975899
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.688505021
Short name T771
Test name
Test status
Simulation time 63442736 ps
CPU time 3.02 seconds
Started Apr 15 02:25:43 PM PDT 24
Finished Apr 15 02:25:47 PM PDT 24
Peak memory 208744 kb
Host smart-f8b199b0-487f-419e-bd2c-fb53d0906248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688505021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.688505021
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3953840348
Short name T476
Test name
Test status
Simulation time 38246363 ps
CPU time 2.34 seconds
Started Apr 15 02:25:45 PM PDT 24
Finished Apr 15 02:25:48 PM PDT 24
Peak memory 207144 kb
Host smart-2c77df5e-cd27-48e4-993d-ee5dcf4a2445
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953840348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3953840348
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3959291836
Short name T875
Test name
Test status
Simulation time 65597866 ps
CPU time 2.6 seconds
Started Apr 15 02:25:44 PM PDT 24
Finished Apr 15 02:25:47 PM PDT 24
Peak memory 206956 kb
Host smart-d4945ca8-110d-4e94-821f-317562d16587
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959291836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3959291836
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.195902767
Short name T336
Test name
Test status
Simulation time 47524849 ps
CPU time 2.29 seconds
Started Apr 15 02:25:51 PM PDT 24
Finished Apr 15 02:25:54 PM PDT 24
Peak memory 218808 kb
Host smart-a20876ef-c942-4b9c-b95e-4dbc4e51c636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195902767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.195902767
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1384687321
Short name T570
Test name
Test status
Simulation time 77418627 ps
CPU time 2.43 seconds
Started Apr 15 02:25:41 PM PDT 24
Finished Apr 15 02:25:44 PM PDT 24
Peak memory 208632 kb
Host smart-bdea19da-004d-4e47-ad4c-e71df052bfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384687321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1384687321
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.74049408
Short name T209
Test name
Test status
Simulation time 2994190902 ps
CPU time 27.13 seconds
Started Apr 15 02:25:52 PM PDT 24
Finished Apr 15 02:26:20 PM PDT 24
Peak memory 222852 kb
Host smart-2cdbb8e2-b7ac-4c98-a419-0d02b2c6a419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74049408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.74049408
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1188535449
Short name T386
Test name
Test status
Simulation time 777288990 ps
CPU time 4.97 seconds
Started Apr 15 02:25:53 PM PDT 24
Finished Apr 15 02:25:59 PM PDT 24
Peak memory 209432 kb
Host smart-db0f918c-a110-4f20-92ee-3d22ee76f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188535449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1188535449
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1028677720
Short name T758
Test name
Test status
Simulation time 62728402 ps
CPU time 3.44 seconds
Started Apr 15 02:25:49 PM PDT 24
Finished Apr 15 02:25:53 PM PDT 24
Peak memory 210172 kb
Host smart-9c690e1e-5b6b-4e6e-a000-328ea1f3fb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028677720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1028677720
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1216430756
Short name T783
Test name
Test status
Simulation time 45996252 ps
CPU time 0.78 seconds
Started Apr 15 02:26:03 PM PDT 24
Finished Apr 15 02:26:05 PM PDT 24
Peak memory 206304 kb
Host smart-3b6c94fa-d072-4aee-9fe0-7b4c2f9d5df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216430756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1216430756
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.111431886
Short name T556
Test name
Test status
Simulation time 107795225 ps
CPU time 1.63 seconds
Started Apr 15 02:25:56 PM PDT 24
Finished Apr 15 02:25:58 PM PDT 24
Peak memory 209704 kb
Host smart-4333c04c-4c51-4724-9548-c717cc611416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111431886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.111431886
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1749467664
Short name T713
Test name
Test status
Simulation time 107725668 ps
CPU time 4.56 seconds
Started Apr 15 02:25:56 PM PDT 24
Finished Apr 15 02:26:02 PM PDT 24
Peak memory 210424 kb
Host smart-634e261c-6d86-460b-871a-18e0a121160a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749467664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1749467664
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1595174158
Short name T372
Test name
Test status
Simulation time 44894439 ps
CPU time 3.37 seconds
Started Apr 15 02:25:54 PM PDT 24
Finished Apr 15 02:25:58 PM PDT 24
Peak memory 220012 kb
Host smart-9eee2174-aedd-4f63-a51e-0624bc6bb880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595174158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1595174158
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2239369325
Short name T10
Test name
Test status
Simulation time 293314422 ps
CPU time 9.64 seconds
Started Apr 15 02:26:02 PM PDT 24
Finished Apr 15 02:26:12 PM PDT 24
Peak memory 230208 kb
Host smart-00a24928-8acc-484d-ac24-eee37af2392f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239369325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2239369325
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.862556841
Short name T802
Test name
Test status
Simulation time 6869901071 ps
CPU time 55.05 seconds
Started Apr 15 02:25:53 PM PDT 24
Finished Apr 15 02:26:48 PM PDT 24
Peak memory 208628 kb
Host smart-44a68bb2-d5da-4f53-9d78-cd653dbe178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862556841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.862556841
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4216098682
Short name T299
Test name
Test status
Simulation time 471663623 ps
CPU time 9.73 seconds
Started Apr 15 02:26:00 PM PDT 24
Finished Apr 15 02:26:10 PM PDT 24
Peak memory 209152 kb
Host smart-34c39b52-f77e-45c9-8be5-554b7bf4a0ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216098682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4216098682
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3750908049
Short name T148
Test name
Test status
Simulation time 311423888 ps
CPU time 6.67 seconds
Started Apr 15 02:25:58 PM PDT 24
Finished Apr 15 02:26:05 PM PDT 24
Peak memory 208100 kb
Host smart-6e32b3fe-52a2-4f4d-872f-9fcfb87eafe3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750908049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3750908049
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.640884068
Short name T495
Test name
Test status
Simulation time 257678964 ps
CPU time 3.3 seconds
Started Apr 15 02:25:52 PM PDT 24
Finished Apr 15 02:25:56 PM PDT 24
Peak memory 208764 kb
Host smart-9312856c-844a-4aee-a8b7-e758e3ec7ec3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640884068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.640884068
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3646559760
Short name T235
Test name
Test status
Simulation time 136954440 ps
CPU time 2.29 seconds
Started Apr 15 02:26:01 PM PDT 24
Finished Apr 15 02:26:04 PM PDT 24
Peak memory 216096 kb
Host smart-8b43b5ec-c6b6-4ae8-b93b-e740c0724bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646559760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3646559760
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1362449137
Short name T491
Test name
Test status
Simulation time 86706939 ps
CPU time 2.08 seconds
Started Apr 15 02:25:57 PM PDT 24
Finished Apr 15 02:26:00 PM PDT 24
Peak memory 208864 kb
Host smart-44ced1fa-e565-432d-a287-673ed4d60668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362449137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1362449137
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1073062472
Short name T877
Test name
Test status
Simulation time 55475457 ps
CPU time 3.49 seconds
Started Apr 15 02:25:58 PM PDT 24
Finished Apr 15 02:26:02 PM PDT 24
Peak memory 218900 kb
Host smart-c029ad99-53d6-4f90-b51c-1dc38105ce6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073062472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1073062472
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3584232713
Short name T393
Test name
Test status
Simulation time 390757370 ps
CPU time 2.36 seconds
Started Apr 15 02:26:01 PM PDT 24
Finished Apr 15 02:26:04 PM PDT 24
Peak memory 210064 kb
Host smart-b8267858-3f72-4e30-9846-3e9bc0c6a989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584232713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3584232713
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2281739646
Short name T469
Test name
Test status
Simulation time 13441401 ps
CPU time 0.73 seconds
Started Apr 15 02:27:08 PM PDT 24
Finished Apr 15 02:27:09 PM PDT 24
Peak memory 206304 kb
Host smart-dc44f828-eb39-4952-b9e3-8db981919ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281739646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2281739646
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1096246437
Short name T420
Test name
Test status
Simulation time 171147594 ps
CPU time 3.58 seconds
Started Apr 15 02:27:02 PM PDT 24
Finished Apr 15 02:27:06 PM PDT 24
Peak memory 214604 kb
Host smart-afc202e3-bd06-4657-af82-0a815e7a9138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096246437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1096246437
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3351589350
Short name T801
Test name
Test status
Simulation time 140044665 ps
CPU time 2.38 seconds
Started Apr 15 02:27:02 PM PDT 24
Finished Apr 15 02:27:05 PM PDT 24
Peak memory 207476 kb
Host smart-631faae2-0b14-4f81-a5d9-5221bb17bd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351589350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3351589350
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.520900275
Short name T606
Test name
Test status
Simulation time 495639762 ps
CPU time 3.66 seconds
Started Apr 15 02:27:07 PM PDT 24
Finished Apr 15 02:27:12 PM PDT 24
Peak memory 214628 kb
Host smart-167fdc67-ffd5-4245-b9f1-e4695e110a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520900275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.520900275
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.513315061
Short name T334
Test name
Test status
Simulation time 100392544 ps
CPU time 4.56 seconds
Started Apr 15 02:27:06 PM PDT 24
Finished Apr 15 02:27:12 PM PDT 24
Peak memory 210160 kb
Host smart-7305ab40-a579-4f61-ac2b-bfab6f18bdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513315061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.513315061
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.457150612
Short name T241
Test name
Test status
Simulation time 61670345 ps
CPU time 2.8 seconds
Started Apr 15 02:27:07 PM PDT 24
Finished Apr 15 02:27:11 PM PDT 24
Peak memory 214672 kb
Host smart-bf54661e-3204-4892-a112-daee3d76847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457150612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.457150612
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2592293382
Short name T291
Test name
Test status
Simulation time 90413101 ps
CPU time 2 seconds
Started Apr 15 02:27:01 PM PDT 24
Finished Apr 15 02:27:04 PM PDT 24
Peak memory 208924 kb
Host smart-6ca41fef-2805-416f-a244-6635aa272848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592293382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2592293382
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2948736460
Short name T746
Test name
Test status
Simulation time 91008869 ps
CPU time 2.71 seconds
Started Apr 15 02:27:01 PM PDT 24
Finished Apr 15 02:27:05 PM PDT 24
Peak memory 208332 kb
Host smart-03153faa-debe-4752-87ed-fc710c670031
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948736460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2948736460
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1233729641
Short name T719
Test name
Test status
Simulation time 101383335 ps
CPU time 2.89 seconds
Started Apr 15 02:27:03 PM PDT 24
Finished Apr 15 02:27:06 PM PDT 24
Peak memory 209028 kb
Host smart-0ec2333f-54ae-44b6-a8db-3ec818a3dac8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233729641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1233729641
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2733287227
Short name T798
Test name
Test status
Simulation time 2053713552 ps
CPU time 71.37 seconds
Started Apr 15 02:27:04 PM PDT 24
Finished Apr 15 02:28:16 PM PDT 24
Peak memory 208816 kb
Host smart-aebfe2de-5207-4e4f-ace0-de549360d990
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733287227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2733287227
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2507272293
Short name T828
Test name
Test status
Simulation time 3304737506 ps
CPU time 17.96 seconds
Started Apr 15 02:27:08 PM PDT 24
Finished Apr 15 02:27:27 PM PDT 24
Peak memory 209068 kb
Host smart-d1ee14f7-7786-4b22-b10c-eb4c0187170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507272293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2507272293
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2991246444
Short name T524
Test name
Test status
Simulation time 794830905 ps
CPU time 18.96 seconds
Started Apr 15 02:27:01 PM PDT 24
Finished Apr 15 02:27:20 PM PDT 24
Peak memory 207984 kb
Host smart-7414cbd0-ecdd-4ae6-8a12-6374590d3413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991246444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2991246444
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.4159379931
Short name T77
Test name
Test status
Simulation time 2108791313 ps
CPU time 26.06 seconds
Started Apr 15 02:27:07 PM PDT 24
Finished Apr 15 02:27:33 PM PDT 24
Peak memory 216004 kb
Host smart-40f82d48-13bc-48cc-92f2-73c70e231bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159379931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.4159379931
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.4255981805
Short name T735
Test name
Test status
Simulation time 824583947 ps
CPU time 4.95 seconds
Started Apr 15 02:27:07 PM PDT 24
Finished Apr 15 02:27:13 PM PDT 24
Peak memory 210656 kb
Host smart-307ff5d2-e589-42ae-8c7e-345f7d67921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255981805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.4255981805
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3397431559
Short name T574
Test name
Test status
Simulation time 116738027 ps
CPU time 3.35 seconds
Started Apr 15 02:27:05 PM PDT 24
Finished Apr 15 02:27:09 PM PDT 24
Peak memory 210664 kb
Host smart-46a2fa39-d37a-4d32-9cfd-83116cf0b8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397431559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3397431559
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2440095238
Short name T30
Test name
Test status
Simulation time 49550030 ps
CPU time 2.99 seconds
Started Apr 15 02:27:23 PM PDT 24
Finished Apr 15 02:27:27 PM PDT 24
Peak memory 209856 kb
Host smart-ea201f9a-f8e4-4d34-bbd5-b782fbe6a64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440095238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2440095238
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2944307860
Short name T620
Test name
Test status
Simulation time 834258205 ps
CPU time 29.76 seconds
Started Apr 15 02:27:11 PM PDT 24
Finished Apr 15 02:27:41 PM PDT 24
Peak memory 214644 kb
Host smart-a9437e71-bea2-4172-8f59-df3aa23a4f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944307860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2944307860
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.510459378
Short name T27
Test name
Test status
Simulation time 4633679832 ps
CPU time 45.89 seconds
Started Apr 15 02:27:14 PM PDT 24
Finished Apr 15 02:28:00 PM PDT 24
Peak memory 214796 kb
Host smart-ea60e1fc-eabf-4ad0-9250-0ac451060d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510459378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.510459378
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2753486358
Short name T265
Test name
Test status
Simulation time 411765066 ps
CPU time 4.09 seconds
Started Apr 15 02:27:15 PM PDT 24
Finished Apr 15 02:27:20 PM PDT 24
Peak memory 210788 kb
Host smart-356770b0-ce88-4107-8e6b-c9d856f9b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753486358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2753486358
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2606384061
Short name T581
Test name
Test status
Simulation time 287616029 ps
CPU time 3.46 seconds
Started Apr 15 02:27:14 PM PDT 24
Finished Apr 15 02:27:18 PM PDT 24
Peak memory 215116 kb
Host smart-76f48672-7635-453b-b56f-20a5edecdc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606384061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2606384061
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2768538474
Short name T747
Test name
Test status
Simulation time 384300521 ps
CPU time 4.37 seconds
Started Apr 15 02:27:10 PM PDT 24
Finished Apr 15 02:27:15 PM PDT 24
Peak memory 218456 kb
Host smart-25c78799-7da0-4b37-8149-39d754512df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768538474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2768538474
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.588031750
Short name T15
Test name
Test status
Simulation time 142989808 ps
CPU time 4.34 seconds
Started Apr 15 02:27:05 PM PDT 24
Finished Apr 15 02:27:10 PM PDT 24
Peak memory 208400 kb
Host smart-8325fe47-52b7-43b5-8985-48cb744c3618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588031750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.588031750
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.37087141
Short name T689
Test name
Test status
Simulation time 22025790 ps
CPU time 1.9 seconds
Started Apr 15 02:27:09 PM PDT 24
Finished Apr 15 02:27:11 PM PDT 24
Peak memory 207176 kb
Host smart-c4219f0d-846b-4a96-91a1-ebd858b8dac0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37087141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.37087141
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3929804368
Short name T830
Test name
Test status
Simulation time 12177835976 ps
CPU time 24.52 seconds
Started Apr 15 02:27:06 PM PDT 24
Finished Apr 15 02:27:31 PM PDT 24
Peak memory 208468 kb
Host smart-931a249f-9b83-4318-a73f-8064c476494f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929804368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3929804368
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.756733865
Short name T671
Test name
Test status
Simulation time 147817845 ps
CPU time 5.97 seconds
Started Apr 15 02:27:06 PM PDT 24
Finished Apr 15 02:27:12 PM PDT 24
Peak memory 208760 kb
Host smart-4358fc69-8e07-43fb-bb6c-e8ca1094ef26
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756733865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.756733865
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1655160073
Short name T599
Test name
Test status
Simulation time 33208036 ps
CPU time 2.29 seconds
Started Apr 15 02:27:22 PM PDT 24
Finished Apr 15 02:27:25 PM PDT 24
Peak memory 216012 kb
Host smart-1e9f923f-e0c7-43f2-b60c-7da956babb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655160073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1655160073
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3955857719
Short name T672
Test name
Test status
Simulation time 205998989 ps
CPU time 5.24 seconds
Started Apr 15 02:27:06 PM PDT 24
Finished Apr 15 02:27:12 PM PDT 24
Peak memory 208580 kb
Host smart-d44e01d2-d71a-4f19-9e72-a6d293e09efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955857719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3955857719
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1309994409
Short name T342
Test name
Test status
Simulation time 188429726 ps
CPU time 3.12 seconds
Started Apr 15 02:27:13 PM PDT 24
Finished Apr 15 02:27:17 PM PDT 24
Peak memory 210572 kb
Host smart-b8968aac-4722-424d-a469-73b22bafcbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309994409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1309994409
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2507089000
Short name T588
Test name
Test status
Simulation time 26596792 ps
CPU time 0.93 seconds
Started Apr 15 02:27:17 PM PDT 24
Finished Apr 15 02:27:18 PM PDT 24
Peak memory 206460 kb
Host smart-8bc1e7a0-e6e7-46c7-8b41-deb79d204e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507089000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2507089000
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2797532163
Short name T19
Test name
Test status
Simulation time 257991657 ps
CPU time 3.47 seconds
Started Apr 15 02:27:16 PM PDT 24
Finished Apr 15 02:27:20 PM PDT 24
Peak memory 222416 kb
Host smart-932b811d-540f-460c-b0a1-c2683a2e1ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797532163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2797532163
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3733435810
Short name T452
Test name
Test status
Simulation time 168038192 ps
CPU time 2.26 seconds
Started Apr 15 02:27:15 PM PDT 24
Finished Apr 15 02:27:18 PM PDT 24
Peak memory 207464 kb
Host smart-7fc21d81-bc5f-4eb2-b749-dcea106a7554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733435810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3733435810
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3325518567
Short name T272
Test name
Test status
Simulation time 92212873 ps
CPU time 3.09 seconds
Started Apr 15 02:27:23 PM PDT 24
Finished Apr 15 02:27:27 PM PDT 24
Peak memory 219844 kb
Host smart-81db6309-ccd1-44f1-892f-58ea98fb9161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325518567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3325518567
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3244632049
Short name T83
Test name
Test status
Simulation time 129880740 ps
CPU time 5.09 seconds
Started Apr 15 02:27:16 PM PDT 24
Finished Apr 15 02:27:22 PM PDT 24
Peak memory 222604 kb
Host smart-6458e69d-499f-4889-a1e5-aecb1049481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244632049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3244632049
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2744181783
Short name T5
Test name
Test status
Simulation time 885255726 ps
CPU time 7.92 seconds
Started Apr 15 02:27:24 PM PDT 24
Finished Apr 15 02:27:33 PM PDT 24
Peak memory 210132 kb
Host smart-0fd68ac7-e976-4717-954f-9deefb06dfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744181783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2744181783
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1164615696
Short name T742
Test name
Test status
Simulation time 1822508276 ps
CPU time 24.28 seconds
Started Apr 15 02:27:16 PM PDT 24
Finished Apr 15 02:27:41 PM PDT 24
Peak memory 209772 kb
Host smart-af19a4e5-1903-4704-8249-0fe074b10efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164615696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1164615696
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2858030067
Short name T374
Test name
Test status
Simulation time 152452114 ps
CPU time 2.69 seconds
Started Apr 15 02:27:22 PM PDT 24
Finished Apr 15 02:27:26 PM PDT 24
Peak memory 208336 kb
Host smart-2129c203-5961-4a39-bf04-153ef20abbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858030067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2858030067
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2524780461
Short name T754
Test name
Test status
Simulation time 383308600 ps
CPU time 4.81 seconds
Started Apr 15 02:27:15 PM PDT 24
Finished Apr 15 02:27:20 PM PDT 24
Peak memory 208744 kb
Host smart-709b2ffb-507c-4ff7-96db-349792f49f04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524780461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2524780461
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1650424970
Short name T704
Test name
Test status
Simulation time 384317844 ps
CPU time 3.34 seconds
Started Apr 15 02:27:11 PM PDT 24
Finished Apr 15 02:27:15 PM PDT 24
Peak memory 207328 kb
Host smart-30af508e-b6c8-4ca2-9a17-65e4bf6c31d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650424970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1650424970
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2580861964
Short name T234
Test name
Test status
Simulation time 135215481 ps
CPU time 4.2 seconds
Started Apr 15 02:27:22 PM PDT 24
Finished Apr 15 02:27:27 PM PDT 24
Peak memory 208376 kb
Host smart-6ee39ab7-53ea-451d-8e9b-f44c343f23d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580861964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2580861964
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2513561668
Short name T429
Test name
Test status
Simulation time 25057441 ps
CPU time 1.87 seconds
Started Apr 15 02:27:16 PM PDT 24
Finished Apr 15 02:27:18 PM PDT 24
Peak memory 207780 kb
Host smart-a6fce4c8-0bb2-40eb-9d94-3332018e1f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513561668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2513561668
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2678528816
Short name T499
Test name
Test status
Simulation time 188954516 ps
CPU time 5.04 seconds
Started Apr 15 02:27:15 PM PDT 24
Finished Apr 15 02:27:20 PM PDT 24
Peak memory 207104 kb
Host smart-3da8e8d6-ebe2-41e6-b315-88fdefc95f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678528816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2678528816
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3766283253
Short name T78
Test name
Test status
Simulation time 213911043 ps
CPU time 5.9 seconds
Started Apr 15 02:27:15 PM PDT 24
Finished Apr 15 02:27:22 PM PDT 24
Peak memory 214728 kb
Host smart-626caecf-ab90-44be-bf77-3b000b95cf43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766283253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3766283253
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1449691338
Short name T899
Test name
Test status
Simulation time 592322912 ps
CPU time 22.16 seconds
Started Apr 15 02:27:13 PM PDT 24
Finished Apr 15 02:27:36 PM PDT 24
Peak memory 222824 kb
Host smart-c3bb6342-61fb-4847-bf76-75df8086f2a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449691338 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1449691338
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.919366425
Short name T346
Test name
Test status
Simulation time 106208154 ps
CPU time 2.41 seconds
Started Apr 15 02:27:14 PM PDT 24
Finished Apr 15 02:27:17 PM PDT 24
Peak memory 207536 kb
Host smart-4921754b-a220-4711-b25b-daae8779e582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919366425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.919366425
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3762457533
Short name T220
Test name
Test status
Simulation time 132078684 ps
CPU time 1.73 seconds
Started Apr 15 02:27:17 PM PDT 24
Finished Apr 15 02:27:20 PM PDT 24
Peak memory 209876 kb
Host smart-1aae5bd7-c4fa-4cae-b0b8-24e3963dedf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762457533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3762457533
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.598496544
Short name T889
Test name
Test status
Simulation time 27261384 ps
CPU time 0.82 seconds
Started Apr 15 02:27:23 PM PDT 24
Finished Apr 15 02:27:25 PM PDT 24
Peak memory 206276 kb
Host smart-51c26067-3555-41dd-ab34-8e8b66117ec6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598496544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.598496544
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1712853818
Short name T408
Test name
Test status
Simulation time 34482394 ps
CPU time 2.79 seconds
Started Apr 15 02:27:20 PM PDT 24
Finished Apr 15 02:27:23 PM PDT 24
Peak memory 214616 kb
Host smart-57be8f2d-2c9a-48ae-a11a-c5507cfecde0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712853818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1712853818
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3292090579
Short name T687
Test name
Test status
Simulation time 522511914 ps
CPU time 4.22 seconds
Started Apr 15 02:27:23 PM PDT 24
Finished Apr 15 02:27:28 PM PDT 24
Peak memory 214884 kb
Host smart-fb4d2ad0-b82b-4cb8-8175-628a210753a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292090579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3292090579
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3743041166
Short name T329
Test name
Test status
Simulation time 2265696186 ps
CPU time 10.66 seconds
Started Apr 15 02:27:19 PM PDT 24
Finished Apr 15 02:27:31 PM PDT 24
Peak memory 207336 kb
Host smart-bccab2d9-df1a-4b8d-b1fb-b51dcbfd44f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743041166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3743041166
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2599623359
Short name T97
Test name
Test status
Simulation time 112963367 ps
CPU time 5.48 seconds
Started Apr 15 02:27:18 PM PDT 24
Finished Apr 15 02:27:24 PM PDT 24
Peak memory 214656 kb
Host smart-ca638eac-af78-4068-8e46-ff7259775eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599623359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2599623359
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.986119238
Short name T281
Test name
Test status
Simulation time 235973536 ps
CPU time 4.66 seconds
Started Apr 15 02:27:19 PM PDT 24
Finished Apr 15 02:27:24 PM PDT 24
Peak memory 222712 kb
Host smart-519a0d2d-8247-4b18-90ee-96b3eac1bdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986119238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.986119238
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1016745434
Short name T582
Test name
Test status
Simulation time 90640660 ps
CPU time 4.14 seconds
Started Apr 15 02:27:21 PM PDT 24
Finished Apr 15 02:27:25 PM PDT 24
Peak memory 220368 kb
Host smart-a7777c15-da51-4427-b350-e4074fc9b64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016745434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1016745434
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1126940303
Short name T221
Test name
Test status
Simulation time 11156733982 ps
CPU time 22.87 seconds
Started Apr 15 02:27:18 PM PDT 24
Finished Apr 15 02:27:41 PM PDT 24
Peak memory 209404 kb
Host smart-8f53e2d7-0748-4ac3-9ea4-32ae9fa50bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126940303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1126940303
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1457024117
Short name T470
Test name
Test status
Simulation time 338930299 ps
CPU time 4.69 seconds
Started Apr 15 02:27:23 PM PDT 24
Finished Apr 15 02:27:28 PM PDT 24
Peak memory 208168 kb
Host smart-3757088e-e3e9-495d-872e-80ae12efa236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457024117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1457024117
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1265075883
Short name T669
Test name
Test status
Simulation time 400941885 ps
CPU time 3.56 seconds
Started Apr 15 02:27:19 PM PDT 24
Finished Apr 15 02:27:24 PM PDT 24
Peak memory 207852 kb
Host smart-7427c406-aa76-405a-802c-b98213749468
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265075883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1265075883
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3973992292
Short name T377
Test name
Test status
Simulation time 420803356 ps
CPU time 5.56 seconds
Started Apr 15 02:27:20 PM PDT 24
Finished Apr 15 02:27:26 PM PDT 24
Peak memory 208928 kb
Host smart-8fea51e2-2864-469a-8f6c-b71d1e88dd33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973992292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3973992292
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.974390002
Short name T447
Test name
Test status
Simulation time 655232143 ps
CPU time 5.65 seconds
Started Apr 15 02:27:19 PM PDT 24
Finished Apr 15 02:27:25 PM PDT 24
Peak memory 208236 kb
Host smart-698e8c23-2711-4d5b-89cf-de32dc75d6a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974390002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.974390002
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2705793083
Short name T213
Test name
Test status
Simulation time 3304194994 ps
CPU time 23.97 seconds
Started Apr 15 02:27:18 PM PDT 24
Finished Apr 15 02:27:43 PM PDT 24
Peak memory 210688 kb
Host smart-a2b6079e-a6a2-4bee-bd49-7e89ce692411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705793083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2705793083
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1398170872
Short name T854
Test name
Test status
Simulation time 57009338 ps
CPU time 2.61 seconds
Started Apr 15 02:27:22 PM PDT 24
Finished Apr 15 02:27:25 PM PDT 24
Peak memory 208196 kb
Host smart-cc6fa7b1-9671-4b85-9563-316eb1c94bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398170872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1398170872
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3815062378
Short name T57
Test name
Test status
Simulation time 146879226 ps
CPU time 6.63 seconds
Started Apr 15 02:27:17 PM PDT 24
Finished Apr 15 02:27:25 PM PDT 24
Peak memory 221160 kb
Host smart-2b94f84d-c11a-4343-88c0-875712a6818e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815062378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3815062378
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.953364590
Short name T139
Test name
Test status
Simulation time 224328311 ps
CPU time 8.47 seconds
Started Apr 15 02:27:18 PM PDT 24
Finished Apr 15 02:27:27 PM PDT 24
Peak memory 223004 kb
Host smart-57b64833-03b6-4e72-928a-87f63b347065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953364590 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.953364590
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.92044591
Short name T122
Test name
Test status
Simulation time 146351127 ps
CPU time 5.85 seconds
Started Apr 15 02:27:21 PM PDT 24
Finished Apr 15 02:27:28 PM PDT 24
Peak memory 214632 kb
Host smart-40b8d548-57eb-458d-9648-62e4b43358c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92044591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.92044591
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1552889901
Short name T641
Test name
Test status
Simulation time 125959372 ps
CPU time 2.68 seconds
Started Apr 15 02:27:18 PM PDT 24
Finished Apr 15 02:27:22 PM PDT 24
Peak memory 210056 kb
Host smart-7750fd5e-38c6-4d36-9650-f2bdfb6ed3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552889901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1552889901
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.333037498
Short name T850
Test name
Test status
Simulation time 21554025 ps
CPU time 0.78 seconds
Started Apr 15 02:27:27 PM PDT 24
Finished Apr 15 02:27:28 PM PDT 24
Peak memory 206284 kb
Host smart-ca9dc2b4-4444-432a-9566-a0810a38cc9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333037498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.333037498
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1134110203
Short name T89
Test name
Test status
Simulation time 2011719320 ps
CPU time 27.97 seconds
Started Apr 15 02:27:23 PM PDT 24
Finished Apr 15 02:27:52 PM PDT 24
Peak memory 222296 kb
Host smart-3f0c4f8f-d37f-44fd-a1ed-da0623329d35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134110203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1134110203
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.161962572
Short name T304
Test name
Test status
Simulation time 224292798 ps
CPU time 7.72 seconds
Started Apr 15 02:27:25 PM PDT 24
Finished Apr 15 02:27:33 PM PDT 24
Peak memory 223056 kb
Host smart-68449efe-edb9-4ae9-95ec-a5594eb21475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161962572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.161962572
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.32024385
Short name T536
Test name
Test status
Simulation time 54516843 ps
CPU time 1.67 seconds
Started Apr 15 02:27:28 PM PDT 24
Finished Apr 15 02:27:30 PM PDT 24
Peak memory 207852 kb
Host smart-1b35367b-1f40-4d0e-824a-b459eb23232d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32024385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.32024385
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2880342374
Short name T390
Test name
Test status
Simulation time 45289758 ps
CPU time 2.86 seconds
Started Apr 15 02:27:24 PM PDT 24
Finished Apr 15 02:27:27 PM PDT 24
Peak memory 208856 kb
Host smart-c4ad0ecb-ca8a-46f9-960c-77865733bd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880342374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2880342374
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3072491909
Short name T844
Test name
Test status
Simulation time 33066256 ps
CPU time 2.49 seconds
Started Apr 15 02:27:22 PM PDT 24
Finished Apr 15 02:27:25 PM PDT 24
Peak memory 211452 kb
Host smart-0dd7a9c2-befc-4d1f-bd92-1bb318180dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072491909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3072491909
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1980599569
Short name T849
Test name
Test status
Simulation time 80460038 ps
CPU time 3.15 seconds
Started Apr 15 02:27:26 PM PDT 24
Finished Apr 15 02:27:30 PM PDT 24
Peak memory 214920 kb
Host smart-a1660e93-d9f3-496a-b61b-ef84de112e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980599569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1980599569
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1978046454
Short name T326
Test name
Test status
Simulation time 112396180 ps
CPU time 3.92 seconds
Started Apr 15 02:27:22 PM PDT 24
Finished Apr 15 02:27:27 PM PDT 24
Peak memory 209220 kb
Host smart-cf5d938a-8208-4542-a173-156c91f96477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978046454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1978046454
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3226810760
Short name T573
Test name
Test status
Simulation time 4406060230 ps
CPU time 46.93 seconds
Started Apr 15 02:27:19 PM PDT 24
Finished Apr 15 02:28:07 PM PDT 24
Peak memory 209184 kb
Host smart-517c4ed3-1437-4d86-a895-ac2a090e265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226810760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3226810760
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3798773464
Short name T472
Test name
Test status
Simulation time 5367468523 ps
CPU time 44.94 seconds
Started Apr 15 02:27:19 PM PDT 24
Finished Apr 15 02:28:05 PM PDT 24
Peak memory 208776 kb
Host smart-cd6fda39-0df7-41d8-8790-2306ce01d0cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798773464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3798773464
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2189245048
Short name T776
Test name
Test status
Simulation time 410029031 ps
CPU time 13.64 seconds
Started Apr 15 02:27:20 PM PDT 24
Finished Apr 15 02:27:35 PM PDT 24
Peak memory 208944 kb
Host smart-d2ca9abe-1f51-4e44-a82f-601fa71f704d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189245048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2189245048
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3035041286
Short name T406
Test name
Test status
Simulation time 227911222 ps
CPU time 6.81 seconds
Started Apr 15 02:27:19 PM PDT 24
Finished Apr 15 02:27:27 PM PDT 24
Peak memory 209076 kb
Host smart-a2a82a35-f055-43aa-9e89-b879f827428f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035041286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3035041286
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3576367021
Short name T692
Test name
Test status
Simulation time 290308762 ps
CPU time 2.45 seconds
Started Apr 15 02:27:23 PM PDT 24
Finished Apr 15 02:27:26 PM PDT 24
Peak memory 208332 kb
Host smart-91070f98-8e93-4e4b-b76f-c8f873e4f1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576367021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3576367021
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1606362036
Short name T405
Test name
Test status
Simulation time 182762816 ps
CPU time 2.84 seconds
Started Apr 15 02:27:19 PM PDT 24
Finished Apr 15 02:27:22 PM PDT 24
Peak memory 208816 kb
Host smart-e262210f-005d-46e1-b568-ad732b65ee61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606362036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1606362036
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.4086119888
Short name T283
Test name
Test status
Simulation time 487384567 ps
CPU time 11.62 seconds
Started Apr 15 02:27:25 PM PDT 24
Finished Apr 15 02:27:37 PM PDT 24
Peak memory 208544 kb
Host smart-84a49c3d-b2b9-4e1d-9bc8-6d3f1c8d1f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086119888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4086119888
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1018316065
Short name T759
Test name
Test status
Simulation time 12957339636 ps
CPU time 58.54 seconds
Started Apr 15 02:27:24 PM PDT 24
Finished Apr 15 02:28:24 PM PDT 24
Peak memory 221784 kb
Host smart-c78d52a3-6dc6-47ee-aabf-264571a59f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018316065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1018316065
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.820484037
Short name T206
Test name
Test status
Simulation time 1313181235 ps
CPU time 3.59 seconds
Started Apr 15 02:27:27 PM PDT 24
Finished Apr 15 02:27:31 PM PDT 24
Peak memory 210516 kb
Host smart-dbd98d9a-a66f-46ab-aae7-9e761a89a918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820484037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.820484037
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1516772647
Short name T449
Test name
Test status
Simulation time 19115304 ps
CPU time 0.73 seconds
Started Apr 15 02:27:33 PM PDT 24
Finished Apr 15 02:27:35 PM PDT 24
Peak memory 206276 kb
Host smart-20d5d3db-e5fd-4eb3-a15c-f272e860713f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516772647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1516772647
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1064310753
Short name T292
Test name
Test status
Simulation time 172841146 ps
CPU time 9.96 seconds
Started Apr 15 02:27:26 PM PDT 24
Finished Apr 15 02:27:37 PM PDT 24
Peak memory 214636 kb
Host smart-28785c20-8158-443e-9229-c9e8e4feea0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064310753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1064310753
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.495203579
Short name T814
Test name
Test status
Simulation time 82935128 ps
CPU time 1.74 seconds
Started Apr 15 02:27:27 PM PDT 24
Finished Apr 15 02:27:29 PM PDT 24
Peak memory 208240 kb
Host smart-f1743e3f-ae81-4c98-92e9-86989c7c2146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495203579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.495203579
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3407963741
Short name T597
Test name
Test status
Simulation time 142755740 ps
CPU time 3.25 seconds
Started Apr 15 02:27:27 PM PDT 24
Finished Apr 15 02:27:31 PM PDT 24
Peak memory 208812 kb
Host smart-1270fb8a-f18b-49f9-bb9d-fbac5f5046e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407963741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3407963741
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3647759256
Short name T381
Test name
Test status
Simulation time 142955217 ps
CPU time 6.05 seconds
Started Apr 15 02:27:27 PM PDT 24
Finished Apr 15 02:27:34 PM PDT 24
Peak memory 222692 kb
Host smart-f2d95124-c480-44dc-bddb-8394d831942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647759256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3647759256
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1821859069
Short name T786
Test name
Test status
Simulation time 42463865 ps
CPU time 2.36 seconds
Started Apr 15 02:27:26 PM PDT 24
Finished Apr 15 02:27:30 PM PDT 24
Peak memory 220496 kb
Host smart-1f3661e0-cc7a-40eb-a901-d30c82baf4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821859069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1821859069
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2985330372
Short name T223
Test name
Test status
Simulation time 166680067 ps
CPU time 5.44 seconds
Started Apr 15 02:27:27 PM PDT 24
Finished Apr 15 02:27:34 PM PDT 24
Peak memory 209096 kb
Host smart-3863fb4f-5205-4431-8f65-1d90d7728748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985330372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2985330372
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2365549761
Short name T679
Test name
Test status
Simulation time 162835686 ps
CPU time 6.3 seconds
Started Apr 15 02:27:22 PM PDT 24
Finished Apr 15 02:27:29 PM PDT 24
Peak memory 206972 kb
Host smart-bfd9052f-6bcd-4e80-b1e5-c13d6df33a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365549761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2365549761
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1273070744
Short name T639
Test name
Test status
Simulation time 160907406 ps
CPU time 4.44 seconds
Started Apr 15 02:27:27 PM PDT 24
Finished Apr 15 02:27:33 PM PDT 24
Peak memory 209020 kb
Host smart-050a6ec7-39d1-4ef5-8326-6a2a62c818d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273070744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1273070744
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2527414314
Short name T765
Test name
Test status
Simulation time 1347552156 ps
CPU time 7.45 seconds
Started Apr 15 02:27:27 PM PDT 24
Finished Apr 15 02:27:36 PM PDT 24
Peak memory 208764 kb
Host smart-2eaa8279-23ac-4d86-b32a-222bad272b1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527414314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2527414314
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.314186984
Short name T825
Test name
Test status
Simulation time 403095995 ps
CPU time 7.11 seconds
Started Apr 15 02:27:27 PM PDT 24
Finished Apr 15 02:27:35 PM PDT 24
Peak memory 208304 kb
Host smart-dd2d290d-d8cd-4292-b73d-b9a8a7f05b62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314186984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.314186984
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1903539617
Short name T644
Test name
Test status
Simulation time 118665569 ps
CPU time 2.45 seconds
Started Apr 15 02:27:28 PM PDT 24
Finished Apr 15 02:27:31 PM PDT 24
Peak memory 210068 kb
Host smart-0bad8e38-3801-4b62-a4ed-509be97111d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903539617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1903539617
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2663600920
Short name T897
Test name
Test status
Simulation time 249149329 ps
CPU time 8.48 seconds
Started Apr 15 02:27:28 PM PDT 24
Finished Apr 15 02:27:37 PM PDT 24
Peak memory 208240 kb
Host smart-89dc615e-1a0d-421a-8524-96c712a14671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663600920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2663600920
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2931136098
Short name T26
Test name
Test status
Simulation time 100227124 ps
CPU time 4.84 seconds
Started Apr 15 02:27:28 PM PDT 24
Finished Apr 15 02:27:34 PM PDT 24
Peak memory 210132 kb
Host smart-a2c66bb8-a3fe-4605-a5f8-b8e3689b6dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931136098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2931136098
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.99620736
Short name T396
Test name
Test status
Simulation time 172774957 ps
CPU time 2.59 seconds
Started Apr 15 02:27:32 PM PDT 24
Finished Apr 15 02:27:35 PM PDT 24
Peak memory 210488 kb
Host smart-9a290d26-8e6d-479f-ab24-f16672b08196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99620736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.99620736
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.125005587
Short name T868
Test name
Test status
Simulation time 57393817 ps
CPU time 0.91 seconds
Started Apr 15 02:27:35 PM PDT 24
Finished Apr 15 02:27:37 PM PDT 24
Peak memory 206208 kb
Host smart-763ddfaa-e3e0-4a31-8ba6-6c0acc5910c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125005587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.125005587
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3223573652
Short name T32
Test name
Test status
Simulation time 141652399 ps
CPU time 4.55 seconds
Started Apr 15 02:27:36 PM PDT 24
Finished Apr 15 02:27:41 PM PDT 24
Peak memory 208096 kb
Host smart-985428e9-1ead-43cc-bae9-40f8be22216b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223573652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3223573652
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.225329170
Short name T530
Test name
Test status
Simulation time 511077316 ps
CPU time 2.22 seconds
Started Apr 15 02:27:36 PM PDT 24
Finished Apr 15 02:27:39 PM PDT 24
Peak memory 207904 kb
Host smart-8d00e2b6-a229-49d4-b6c2-152d198588a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225329170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.225329170
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3120667924
Short name T657
Test name
Test status
Simulation time 2051318885 ps
CPU time 11.15 seconds
Started Apr 15 02:27:35 PM PDT 24
Finished Apr 15 02:27:47 PM PDT 24
Peak memory 209808 kb
Host smart-9508b260-5f2c-4b8f-9edc-d0e074317ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120667924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3120667924
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.413852177
Short name T733
Test name
Test status
Simulation time 110314518 ps
CPU time 3.52 seconds
Started Apr 15 02:27:36 PM PDT 24
Finished Apr 15 02:27:40 PM PDT 24
Peak memory 209024 kb
Host smart-455bd24c-9299-4568-aec2-b3b46c75d68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413852177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.413852177
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2290711531
Short name T526
Test name
Test status
Simulation time 52469502 ps
CPU time 3.16 seconds
Started Apr 15 02:27:32 PM PDT 24
Finished Apr 15 02:27:36 PM PDT 24
Peak memory 214676 kb
Host smart-f6802668-75a3-465b-aa2b-a2f1350404fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290711531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2290711531
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3708865047
Short name T307
Test name
Test status
Simulation time 4249935195 ps
CPU time 16.52 seconds
Started Apr 15 02:27:30 PM PDT 24
Finished Apr 15 02:27:47 PM PDT 24
Peak memory 208268 kb
Host smart-a49637bc-db0d-4cd9-b4d2-a70bd2c9e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708865047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3708865047
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.944757840
Short name T509
Test name
Test status
Simulation time 48257791 ps
CPU time 2.55 seconds
Started Apr 15 02:27:31 PM PDT 24
Finished Apr 15 02:27:34 PM PDT 24
Peak memory 207044 kb
Host smart-b4cf8cb9-d39d-463b-963d-b505b2f8557a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944757840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.944757840
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.960578067
Short name T665
Test name
Test status
Simulation time 46567711 ps
CPU time 2.64 seconds
Started Apr 15 02:27:32 PM PDT 24
Finished Apr 15 02:27:35 PM PDT 24
Peak memory 207168 kb
Host smart-0a040cda-4442-421b-a1fe-98c0c4b62896
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960578067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.960578067
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.849030706
Short name T866
Test name
Test status
Simulation time 199703125 ps
CPU time 3.03 seconds
Started Apr 15 02:27:30 PM PDT 24
Finished Apr 15 02:27:33 PM PDT 24
Peak memory 208880 kb
Host smart-734df28b-4bea-46c9-8af2-c6462123aa9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849030706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.849030706
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.36394280
Short name T890
Test name
Test status
Simulation time 1232488777 ps
CPU time 8.39 seconds
Started Apr 15 02:27:36 PM PDT 24
Finished Apr 15 02:27:45 PM PDT 24
Peak memory 209828 kb
Host smart-c7c8f99e-3956-488d-b973-06deed2dcd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36394280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.36394280
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.4067142667
Short name T468
Test name
Test status
Simulation time 96409759 ps
CPU time 4.08 seconds
Started Apr 15 02:27:31 PM PDT 24
Finished Apr 15 02:27:36 PM PDT 24
Peak memory 207104 kb
Host smart-aee36c6b-f9be-4cbd-8399-e21bd148e3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067142667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4067142667
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4099643789
Short name T127
Test name
Test status
Simulation time 1254680199 ps
CPU time 14.76 seconds
Started Apr 15 02:27:36 PM PDT 24
Finished Apr 15 02:27:51 PM PDT 24
Peak memory 222964 kb
Host smart-fbeb121e-50f3-44c5-92b2-b46afc50412e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099643789 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4099643789
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2876002936
Short name T492
Test name
Test status
Simulation time 90052987 ps
CPU time 4.46 seconds
Started Apr 15 02:27:34 PM PDT 24
Finished Apr 15 02:27:39 PM PDT 24
Peak memory 208148 kb
Host smart-9958752b-78f2-4fde-9c5e-ed01930a7e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876002936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2876002936
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2780494508
Short name T785
Test name
Test status
Simulation time 312466381 ps
CPU time 2.69 seconds
Started Apr 15 02:27:38 PM PDT 24
Finished Apr 15 02:27:42 PM PDT 24
Peak memory 209964 kb
Host smart-342e11a0-b401-42f5-ab02-3119552a1545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780494508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2780494508
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3223414212
Short name T446
Test name
Test status
Simulation time 16824125 ps
CPU time 0.76 seconds
Started Apr 15 02:27:41 PM PDT 24
Finished Apr 15 02:27:42 PM PDT 24
Peak memory 206200 kb
Host smart-dec765e1-783d-4f04-a4a3-1c81f1d4ea4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223414212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3223414212
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2809036774
Short name T422
Test name
Test status
Simulation time 40659185 ps
CPU time 3.25 seconds
Started Apr 15 02:27:39 PM PDT 24
Finished Apr 15 02:27:43 PM PDT 24
Peak memory 215088 kb
Host smart-722e57d9-da0d-49cd-859b-3f999530152d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809036774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2809036774
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1328102223
Short name T847
Test name
Test status
Simulation time 1095549069 ps
CPU time 3.86 seconds
Started Apr 15 02:27:42 PM PDT 24
Finished Apr 15 02:27:47 PM PDT 24
Peak memory 210448 kb
Host smart-cf05a83c-9825-414a-9100-764a820ac766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328102223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1328102223
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3194486669
Short name T94
Test name
Test status
Simulation time 194735649 ps
CPU time 5.29 seconds
Started Apr 15 02:27:44 PM PDT 24
Finished Apr 15 02:27:50 PM PDT 24
Peak memory 222332 kb
Host smart-44e3017d-6dff-42a2-b2d4-8937bfcdce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194486669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3194486669
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1272791864
Short name T729
Test name
Test status
Simulation time 473481425 ps
CPU time 9.34 seconds
Started Apr 15 02:27:43 PM PDT 24
Finished Apr 15 02:27:53 PM PDT 24
Peak memory 215408 kb
Host smart-1df44028-1b77-439a-a2ab-45cfebce6506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272791864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1272791864
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2794690724
Short name T903
Test name
Test status
Simulation time 168326024 ps
CPU time 5.92 seconds
Started Apr 15 02:27:34 PM PDT 24
Finished Apr 15 02:27:40 PM PDT 24
Peak memory 208128 kb
Host smart-a910091a-25c7-4a42-9a48-4e9a55e2319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794690724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2794690724
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2173537912
Short name T716
Test name
Test status
Simulation time 489478206 ps
CPU time 13.49 seconds
Started Apr 15 02:27:35 PM PDT 24
Finished Apr 15 02:27:49 PM PDT 24
Peak memory 208708 kb
Host smart-ae93d1da-c5b1-4035-9f14-ffe8390084e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173537912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2173537912
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3263587204
Short name T799
Test name
Test status
Simulation time 38828147 ps
CPU time 2.28 seconds
Started Apr 15 02:27:35 PM PDT 24
Finished Apr 15 02:27:38 PM PDT 24
Peak memory 207168 kb
Host smart-53e5cad4-d9de-4abd-a4e1-a5748965bf7e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263587204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3263587204
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1048318014
Short name T285
Test name
Test status
Simulation time 963565955 ps
CPU time 4.03 seconds
Started Apr 15 02:27:34 PM PDT 24
Finished Apr 15 02:27:39 PM PDT 24
Peak memory 208972 kb
Host smart-a711647c-1028-4ae8-b305-5f27b1e82b50
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048318014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1048318014
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2666829037
Short name T705
Test name
Test status
Simulation time 43599764 ps
CPU time 2.55 seconds
Started Apr 15 02:27:35 PM PDT 24
Finished Apr 15 02:27:39 PM PDT 24
Peak memory 207184 kb
Host smart-9c628887-5697-43e8-87d4-4cbc1e51fe87
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666829037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2666829037
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2600985861
Short name T553
Test name
Test status
Simulation time 67424449 ps
CPU time 1.57 seconds
Started Apr 15 02:27:43 PM PDT 24
Finished Apr 15 02:27:46 PM PDT 24
Peak memory 207544 kb
Host smart-faa21ee7-60fe-4453-ab57-feeb6dbfc0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600985861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2600985861
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1469471010
Short name T459
Test name
Test status
Simulation time 389378950 ps
CPU time 5.35 seconds
Started Apr 15 02:27:37 PM PDT 24
Finished Apr 15 02:27:43 PM PDT 24
Peak memory 207908 kb
Host smart-a40baeb5-0ecd-49d7-8d76-a619dcc40057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469471010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1469471010
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3834613109
Short name T315
Test name
Test status
Simulation time 423140725 ps
CPU time 5.06 seconds
Started Apr 15 02:27:40 PM PDT 24
Finished Apr 15 02:27:46 PM PDT 24
Peak memory 219048 kb
Host smart-ff3949b6-e15e-47ee-84bc-deaecb4aa6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834613109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3834613109
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.442760852
Short name T659
Test name
Test status
Simulation time 12706926 ps
CPU time 0.77 seconds
Started Apr 15 02:27:44 PM PDT 24
Finished Apr 15 02:27:46 PM PDT 24
Peak memory 206252 kb
Host smart-a9b27618-db3f-4ec5-9d92-46503bb61058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442760852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.442760852
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3362576124
Short name T419
Test name
Test status
Simulation time 174145881 ps
CPU time 4.19 seconds
Started Apr 15 02:27:44 PM PDT 24
Finished Apr 15 02:27:49 PM PDT 24
Peak memory 214636 kb
Host smart-d13e91ef-008b-4925-81fa-fb8f99739800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362576124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3362576124
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.571940787
Short name T707
Test name
Test status
Simulation time 1086731098 ps
CPU time 7.87 seconds
Started Apr 15 02:27:43 PM PDT 24
Finished Apr 15 02:27:52 PM PDT 24
Peak memory 222312 kb
Host smart-dd34ae51-5370-43cc-b005-3a54e9ec7552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571940787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.571940787
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1485007958
Short name T48
Test name
Test status
Simulation time 1708837598 ps
CPU time 3.4 seconds
Started Apr 15 02:27:42 PM PDT 24
Finished Apr 15 02:27:47 PM PDT 24
Peak memory 208036 kb
Host smart-900f2058-be47-4916-bcba-9659e6a38589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485007958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1485007958
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2305917514
Short name T525
Test name
Test status
Simulation time 161763622 ps
CPU time 5.96 seconds
Started Apr 15 02:27:52 PM PDT 24
Finished Apr 15 02:27:58 PM PDT 24
Peak memory 210104 kb
Host smart-9511c76c-19e9-414e-97e2-a35c73e8588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305917514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2305917514
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3320574479
Short name T106
Test name
Test status
Simulation time 399016264 ps
CPU time 4.99 seconds
Started Apr 15 02:27:45 PM PDT 24
Finished Apr 15 02:27:51 PM PDT 24
Peak memory 212000 kb
Host smart-4d91d25e-ed48-4f2b-9b7d-bf4aa710f360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320574479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3320574479
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.247316252
Short name T627
Test name
Test status
Simulation time 213974138 ps
CPU time 3.54 seconds
Started Apr 15 02:27:43 PM PDT 24
Finished Apr 15 02:27:48 PM PDT 24
Peak memory 220680 kb
Host smart-ac96c389-41b4-405e-bb74-3ad2c36b31cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247316252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.247316252
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1189362092
Short name T613
Test name
Test status
Simulation time 407795607 ps
CPU time 5.17 seconds
Started Apr 15 02:27:45 PM PDT 24
Finished Apr 15 02:27:51 PM PDT 24
Peak memory 208228 kb
Host smart-cfdccb43-59a6-4ce1-9bde-5e911d23d179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189362092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1189362092
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2272249727
Short name T229
Test name
Test status
Simulation time 131054061 ps
CPU time 2.49 seconds
Started Apr 15 02:27:42 PM PDT 24
Finished Apr 15 02:27:45 PM PDT 24
Peak memory 206456 kb
Host smart-788000ac-a041-4f07-8278-717e3e26034f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272249727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2272249727
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.827388590
Short name T878
Test name
Test status
Simulation time 960787637 ps
CPU time 8.01 seconds
Started Apr 15 02:27:45 PM PDT 24
Finished Apr 15 02:27:54 PM PDT 24
Peak memory 208836 kb
Host smart-d6e7c86a-e9b1-4f22-993b-07255db4aca8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827388590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.827388590
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3078398684
Short name T591
Test name
Test status
Simulation time 124923740 ps
CPU time 3.05 seconds
Started Apr 15 02:27:45 PM PDT 24
Finished Apr 15 02:27:48 PM PDT 24
Peak memory 209188 kb
Host smart-57c7ce81-d387-4bb8-9c2f-b5564e7665df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078398684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3078398684
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3085253708
Short name T514
Test name
Test status
Simulation time 36282181 ps
CPU time 1.72 seconds
Started Apr 15 02:27:46 PM PDT 24
Finished Apr 15 02:27:48 PM PDT 24
Peak memory 207116 kb
Host smart-76c9d70f-59d0-4e08-a282-002da2ca8fdf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085253708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3085253708
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.693488862
Short name T832
Test name
Test status
Simulation time 1574294097 ps
CPU time 4.48 seconds
Started Apr 15 02:27:44 PM PDT 24
Finished Apr 15 02:27:49 PM PDT 24
Peak memory 208256 kb
Host smart-a76d2457-d3c5-4c88-b6ec-d5ecbc99f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693488862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.693488862
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3887907062
Short name T651
Test name
Test status
Simulation time 159935696 ps
CPU time 2.61 seconds
Started Apr 15 02:27:40 PM PDT 24
Finished Apr 15 02:27:44 PM PDT 24
Peak memory 208880 kb
Host smart-00a08e3d-aa97-4cc8-a210-12487c08811f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887907062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3887907062
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2980552791
Short name T210
Test name
Test status
Simulation time 11531263854 ps
CPU time 66.53 seconds
Started Apr 15 02:27:44 PM PDT 24
Finished Apr 15 02:28:51 PM PDT 24
Peak memory 222824 kb
Host smart-75d42e95-69fa-4d55-a329-19c3e4de76bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980552791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2980552791
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.4228452942
Short name T537
Test name
Test status
Simulation time 2674641921 ps
CPU time 7.12 seconds
Started Apr 15 02:27:43 PM PDT 24
Finished Apr 15 02:27:51 PM PDT 24
Peak memory 208484 kb
Host smart-e57fdc53-99e8-43e7-b430-6897e42440ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228452942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.4228452942
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.48928849
Short name T558
Test name
Test status
Simulation time 295672258 ps
CPU time 2.02 seconds
Started Apr 15 02:27:44 PM PDT 24
Finished Apr 15 02:27:46 PM PDT 24
Peak memory 210576 kb
Host smart-2c3eb779-f9f2-4b89-af79-8f3cac4c1321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48928849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.48928849
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1957592225
Short name T695
Test name
Test status
Simulation time 13681306 ps
CPU time 0.8 seconds
Started Apr 15 02:27:53 PM PDT 24
Finished Apr 15 02:27:54 PM PDT 24
Peak memory 206268 kb
Host smart-aba1030e-b489-4dd4-aa53-c4e4c4946d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957592225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1957592225
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.223356120
Short name T430
Test name
Test status
Simulation time 573704191 ps
CPU time 3.7 seconds
Started Apr 15 02:27:48 PM PDT 24
Finished Apr 15 02:27:53 PM PDT 24
Peak memory 214676 kb
Host smart-9b98099d-03f6-48ea-b3eb-ef1de638c6a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223356120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.223356120
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2447637049
Short name T547
Test name
Test status
Simulation time 29120223 ps
CPU time 1.72 seconds
Started Apr 15 02:27:49 PM PDT 24
Finished Apr 15 02:27:51 PM PDT 24
Peak memory 207500 kb
Host smart-3dde4df0-dc49-40d8-9301-1a4f1fe0599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447637049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2447637049
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3998740994
Short name T320
Test name
Test status
Simulation time 740192670 ps
CPU time 5.1 seconds
Started Apr 15 02:27:52 PM PDT 24
Finished Apr 15 02:27:57 PM PDT 24
Peak memory 214584 kb
Host smart-257bf417-8e23-4cfd-9afb-8391271fb36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998740994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3998740994
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2062406601
Short name T280
Test name
Test status
Simulation time 4054161237 ps
CPU time 32.53 seconds
Started Apr 15 02:27:53 PM PDT 24
Finished Apr 15 02:28:26 PM PDT 24
Peak memory 215112 kb
Host smart-2d24f60f-b1f5-4b5d-b1f9-7bea0396de14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062406601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2062406601
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2059013657
Short name T546
Test name
Test status
Simulation time 750093077 ps
CPU time 4.86 seconds
Started Apr 15 02:27:48 PM PDT 24
Finished Apr 15 02:27:53 PM PDT 24
Peak memory 210456 kb
Host smart-97cbf7b1-fa06-4c61-a8c5-0464c7aeff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059013657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2059013657
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.684380755
Short name T739
Test name
Test status
Simulation time 174845213 ps
CPU time 4.35 seconds
Started Apr 15 02:27:51 PM PDT 24
Finished Apr 15 02:27:56 PM PDT 24
Peak memory 210680 kb
Host smart-acb4c359-2140-4579-992e-b8226707275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684380755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.684380755
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4165058012
Short name T474
Test name
Test status
Simulation time 122476094 ps
CPU time 3.18 seconds
Started Apr 15 02:27:48 PM PDT 24
Finished Apr 15 02:27:52 PM PDT 24
Peak memory 207056 kb
Host smart-f9600c94-cda7-4bfd-a58d-42f155346e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165058012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4165058012
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3319256478
Short name T817
Test name
Test status
Simulation time 10637532073 ps
CPU time 42.94 seconds
Started Apr 15 02:27:47 PM PDT 24
Finished Apr 15 02:28:30 PM PDT 24
Peak memory 209088 kb
Host smart-d2fbb0fb-e588-462f-8481-c2ac40d16537
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319256478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3319256478
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.90321136
Short name T852
Test name
Test status
Simulation time 607749682 ps
CPU time 5.06 seconds
Started Apr 15 02:27:48 PM PDT 24
Finished Apr 15 02:27:54 PM PDT 24
Peak memory 207020 kb
Host smart-cf534d05-4823-4e73-96b1-ea6f32c69d0d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90321136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.90321136
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1553322202
Short name T362
Test name
Test status
Simulation time 154757588 ps
CPU time 4.68 seconds
Started Apr 15 02:27:49 PM PDT 24
Finished Apr 15 02:27:54 PM PDT 24
Peak memory 208860 kb
Host smart-b51c9afc-44db-431b-ac58-599b790bf21b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553322202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1553322202
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1978320640
Short name T489
Test name
Test status
Simulation time 1411256751 ps
CPU time 4.45 seconds
Started Apr 15 02:27:54 PM PDT 24
Finished Apr 15 02:27:59 PM PDT 24
Peak memory 216068 kb
Host smart-2729cc89-8a29-4af7-be74-45b9318441a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978320640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1978320640
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.256410155
Short name T761
Test name
Test status
Simulation time 321662959 ps
CPU time 4.87 seconds
Started Apr 15 02:27:49 PM PDT 24
Finished Apr 15 02:27:54 PM PDT 24
Peak memory 208036 kb
Host smart-cc7eec84-4387-41dc-a7dc-f1b8e7b30cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256410155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.256410155
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3198243593
Short name T696
Test name
Test status
Simulation time 7215265845 ps
CPU time 162.99 seconds
Started Apr 15 02:27:52 PM PDT 24
Finished Apr 15 02:30:36 PM PDT 24
Peak memory 216456 kb
Host smart-bf836b64-03fc-49d9-b5be-6eff0bb8fea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198243593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3198243593
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4020302998
Short name T538
Test name
Test status
Simulation time 629470725 ps
CPU time 9.47 seconds
Started Apr 15 02:27:49 PM PDT 24
Finished Apr 15 02:27:59 PM PDT 24
Peak memory 214668 kb
Host smart-36f094c1-dba8-42e2-b72f-6421b71800d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020302998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4020302998
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3516042989
Short name T594
Test name
Test status
Simulation time 16427031 ps
CPU time 0.78 seconds
Started Apr 15 02:26:16 PM PDT 24
Finished Apr 15 02:26:18 PM PDT 24
Peak memory 206284 kb
Host smart-1c448e25-152e-4a9d-a650-12c85c389bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516042989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3516042989
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4188291282
Short name T424
Test name
Test status
Simulation time 56057035 ps
CPU time 3.68 seconds
Started Apr 15 02:26:06 PM PDT 24
Finished Apr 15 02:26:10 PM PDT 24
Peak memory 215356 kb
Host smart-d6f68c4a-20ff-44e1-a4d8-c3f224c744f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188291282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4188291282
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2572365904
Short name T28
Test name
Test status
Simulation time 275294390 ps
CPU time 2.12 seconds
Started Apr 15 02:26:14 PM PDT 24
Finished Apr 15 02:26:17 PM PDT 24
Peak memory 209008 kb
Host smart-40d9d3e0-c514-4b19-8c8e-6da2658b3497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572365904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2572365904
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1089797861
Short name T69
Test name
Test status
Simulation time 275204747 ps
CPU time 2.2 seconds
Started Apr 15 02:26:07 PM PDT 24
Finished Apr 15 02:26:10 PM PDT 24
Peak memory 207156 kb
Host smart-5a1c3035-030a-4715-96d4-8dd8fa771782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089797861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1089797861
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4158772840
Short name T686
Test name
Test status
Simulation time 242621148 ps
CPU time 4.38 seconds
Started Apr 15 02:26:12 PM PDT 24
Finished Apr 15 02:26:17 PM PDT 24
Peak memory 214600 kb
Host smart-8a5c1995-4acd-4149-ac5c-22f6b2478ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158772840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4158772840
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.841225478
Short name T267
Test name
Test status
Simulation time 2324434061 ps
CPU time 24.28 seconds
Started Apr 15 02:26:11 PM PDT 24
Finished Apr 15 02:26:36 PM PDT 24
Peak memory 214648 kb
Host smart-86dffde3-3134-488f-9882-0a86db9ce85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841225478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.841225478
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3420558733
Short name T53
Test name
Test status
Simulation time 77286774 ps
CPU time 2.98 seconds
Started Apr 15 02:26:07 PM PDT 24
Finished Apr 15 02:26:11 PM PDT 24
Peak memory 210548 kb
Host smart-5bb95c96-3f53-4073-9146-4f9475eaee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420558733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3420558733
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.204728813
Short name T749
Test name
Test status
Simulation time 132320398 ps
CPU time 5.33 seconds
Started Apr 15 02:26:06 PM PDT 24
Finished Apr 15 02:26:12 PM PDT 24
Peak memory 207196 kb
Host smart-67b49576-a6a5-473c-9f6b-8f3f67504d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204728813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.204728813
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3692847381
Short name T11
Test name
Test status
Simulation time 1038627497 ps
CPU time 29.88 seconds
Started Apr 15 02:26:18 PM PDT 24
Finished Apr 15 02:26:49 PM PDT 24
Peak memory 244412 kb
Host smart-badec1fe-7c5c-4198-8167-27bbdad0b9a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692847381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3692847381
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2414713074
Short name T789
Test name
Test status
Simulation time 100023290 ps
CPU time 3.25 seconds
Started Apr 15 02:26:08 PM PDT 24
Finished Apr 15 02:26:12 PM PDT 24
Peak memory 206928 kb
Host smart-6582b2da-330e-4406-b47e-7cd447f1f77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414713074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2414713074
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3949763122
Short name T818
Test name
Test status
Simulation time 90685001 ps
CPU time 3.8 seconds
Started Apr 15 02:26:08 PM PDT 24
Finished Apr 15 02:26:13 PM PDT 24
Peak memory 208872 kb
Host smart-7c592d9d-050c-42c8-8f45-ba39d5c5ca5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949763122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3949763122
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2029622120
Short name T437
Test name
Test status
Simulation time 150513238 ps
CPU time 4.95 seconds
Started Apr 15 02:26:06 PM PDT 24
Finished Apr 15 02:26:11 PM PDT 24
Peak memory 209148 kb
Host smart-e58adaf3-6059-4b2f-8226-5014f00ba880
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029622120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2029622120
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2908533744
Short name T560
Test name
Test status
Simulation time 57442205 ps
CPU time 2.16 seconds
Started Apr 15 02:26:10 PM PDT 24
Finished Apr 15 02:26:13 PM PDT 24
Peak memory 214688 kb
Host smart-3e000767-e43d-4f62-b438-2e56ae1b1013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908533744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2908533744
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2628590231
Short name T589
Test name
Test status
Simulation time 154380101 ps
CPU time 1.72 seconds
Started Apr 15 02:26:06 PM PDT 24
Finished Apr 15 02:26:09 PM PDT 24
Peak memory 207124 kb
Host smart-907a3143-12ec-42ff-9cca-0211188b1c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628590231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2628590231
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3079258572
Short name T676
Test name
Test status
Simulation time 1044486643 ps
CPU time 5.9 seconds
Started Apr 15 02:26:06 PM PDT 24
Finished Apr 15 02:26:12 PM PDT 24
Peak memory 218668 kb
Host smart-5d7e69d0-4b51-4942-9234-57d9ef0a56a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079258572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3079258572
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.4187991762
Short name T846
Test name
Test status
Simulation time 153907687 ps
CPU time 2.5 seconds
Started Apr 15 02:26:11 PM PDT 24
Finished Apr 15 02:26:14 PM PDT 24
Peak memory 210156 kb
Host smart-edc4ca35-b5b2-408e-b7d0-423011bd9555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187991762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.4187991762
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3486271665
Short name T740
Test name
Test status
Simulation time 42969020 ps
CPU time 0.75 seconds
Started Apr 15 02:27:59 PM PDT 24
Finished Apr 15 02:28:00 PM PDT 24
Peak memory 206292 kb
Host smart-045dc7ad-cb17-4002-a1fb-8e5563d25624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486271665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3486271665
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2291695674
Short name T416
Test name
Test status
Simulation time 175993903 ps
CPU time 3.4 seconds
Started Apr 15 02:27:50 PM PDT 24
Finished Apr 15 02:27:54 PM PDT 24
Peak memory 214632 kb
Host smart-d18b72a9-7c97-437a-a797-3d71fda1510b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291695674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2291695674
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.596748339
Short name T812
Test name
Test status
Simulation time 53613827 ps
CPU time 1.74 seconds
Started Apr 15 02:27:56 PM PDT 24
Finished Apr 15 02:27:58 PM PDT 24
Peak memory 219572 kb
Host smart-c09c271e-00b1-40c8-b7fe-5cb3bdbbd0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596748339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.596748339
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3930355612
Short name T816
Test name
Test status
Simulation time 665192158 ps
CPU time 5.53 seconds
Started Apr 15 02:27:58 PM PDT 24
Finished Apr 15 02:28:04 PM PDT 24
Peak memory 210156 kb
Host smart-c6508c5e-af5a-4023-972f-2879b865b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930355612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3930355612
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2266677568
Short name T107
Test name
Test status
Simulation time 158848223 ps
CPU time 3.49 seconds
Started Apr 15 02:27:56 PM PDT 24
Finished Apr 15 02:28:00 PM PDT 24
Peak memory 214696 kb
Host smart-babc04d3-5058-492f-b167-6a8617948347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266677568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2266677568
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.616556304
Short name T45
Test name
Test status
Simulation time 222031259 ps
CPU time 3.2 seconds
Started Apr 15 02:27:53 PM PDT 24
Finished Apr 15 02:27:56 PM PDT 24
Peak memory 209836 kb
Host smart-0a200df9-dc60-42ec-9784-67d81a43a3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616556304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.616556304
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1218501387
Short name T309
Test name
Test status
Simulation time 1843944819 ps
CPU time 14.35 seconds
Started Apr 15 02:27:55 PM PDT 24
Finished Apr 15 02:28:10 PM PDT 24
Peak memory 214548 kb
Host smart-e4130cb1-1ec7-4564-b2dc-9e79c9f72bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218501387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1218501387
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.757822142
Short name T888
Test name
Test status
Simulation time 456775974 ps
CPU time 12.22 seconds
Started Apr 15 02:27:53 PM PDT 24
Finished Apr 15 02:28:06 PM PDT 24
Peak memory 208948 kb
Host smart-ed0de4a4-0f8b-4f3e-bb3e-e5af4e3249f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757822142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.757822142
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2382724312
Short name T217
Test name
Test status
Simulation time 240330980 ps
CPU time 2.83 seconds
Started Apr 15 02:27:53 PM PDT 24
Finished Apr 15 02:27:56 PM PDT 24
Peak memory 207228 kb
Host smart-4189609c-7e4a-4e71-a85a-14d6388ea8eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382724312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2382724312
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.455032574
Short name T602
Test name
Test status
Simulation time 198150327 ps
CPU time 2.87 seconds
Started Apr 15 02:27:54 PM PDT 24
Finished Apr 15 02:27:58 PM PDT 24
Peak memory 208936 kb
Host smart-40fe27d2-e0cb-4fe3-9e89-7df6ea7870e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455032574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.455032574
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1724772120
Short name T658
Test name
Test status
Simulation time 266312800 ps
CPU time 6.96 seconds
Started Apr 15 02:27:53 PM PDT 24
Finished Apr 15 02:28:01 PM PDT 24
Peak memory 208308 kb
Host smart-57a2293d-aaf5-4038-baab-f3668760e5e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724772120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1724772120
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.819141445
Short name T451
Test name
Test status
Simulation time 28594862 ps
CPU time 2.08 seconds
Started Apr 15 02:27:57 PM PDT 24
Finished Apr 15 02:28:00 PM PDT 24
Peak memory 218720 kb
Host smart-b201038b-af92-48a2-ac32-a791d16ad4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819141445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.819141445
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1151990431
Short name T793
Test name
Test status
Simulation time 38290591 ps
CPU time 1.72 seconds
Started Apr 15 02:27:54 PM PDT 24
Finished Apr 15 02:27:56 PM PDT 24
Peak memory 206528 kb
Host smart-fb2e544d-0f61-4bb6-8bff-d0f1a2f90e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151990431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1151990431
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2238072464
Short name T788
Test name
Test status
Simulation time 1901301683 ps
CPU time 13.29 seconds
Started Apr 15 02:27:53 PM PDT 24
Finished Apr 15 02:28:07 PM PDT 24
Peak memory 209532 kb
Host smart-b20e4891-e313-4f8b-b983-5901f1d008d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238072464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2238072464
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3836998109
Short name T215
Test name
Test status
Simulation time 39918689 ps
CPU time 1.39 seconds
Started Apr 15 02:27:58 PM PDT 24
Finished Apr 15 02:28:00 PM PDT 24
Peak memory 209996 kb
Host smart-ba89173c-99cd-41ed-bdc2-64f49fb0f0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836998109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3836998109
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2284764457
Short name T895
Test name
Test status
Simulation time 70590939 ps
CPU time 1.01 seconds
Started Apr 15 02:28:02 PM PDT 24
Finished Apr 15 02:28:04 PM PDT 24
Peak memory 206476 kb
Host smart-131f16e9-6922-49e1-8999-e08e7df4bffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284764457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2284764457
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3079239847
Short name T843
Test name
Test status
Simulation time 262658931 ps
CPU time 2.78 seconds
Started Apr 15 02:27:57 PM PDT 24
Finished Apr 15 02:28:00 PM PDT 24
Peak memory 214888 kb
Host smart-dc918537-0957-4967-a1a5-5bf1567702ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079239847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3079239847
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.36001964
Short name T551
Test name
Test status
Simulation time 238461235 ps
CPU time 3.44 seconds
Started Apr 15 02:27:58 PM PDT 24
Finished Apr 15 02:28:02 PM PDT 24
Peak memory 207656 kb
Host smart-a43c9c70-4aea-4b51-9434-ee9f63d5750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36001964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.36001964
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2558807711
Short name T95
Test name
Test status
Simulation time 112700242 ps
CPU time 3.88 seconds
Started Apr 15 02:27:57 PM PDT 24
Finished Apr 15 02:28:01 PM PDT 24
Peak memory 219524 kb
Host smart-a3d08020-299d-4720-943a-f05b123a2bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558807711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2558807711
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1927473234
Short name T732
Test name
Test status
Simulation time 172549790 ps
CPU time 2.63 seconds
Started Apr 15 02:27:55 PM PDT 24
Finished Apr 15 02:27:58 PM PDT 24
Peak memory 220668 kb
Host smart-778d8063-6b9c-49ee-ae05-d4c69062b46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927473234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1927473234
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1016076364
Short name T85
Test name
Test status
Simulation time 1539465940 ps
CPU time 7.68 seconds
Started Apr 15 02:27:57 PM PDT 24
Finished Apr 15 02:28:05 PM PDT 24
Peak memory 210116 kb
Host smart-905d03b9-3a52-4bea-b865-16602afe07c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016076364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1016076364
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1431670933
Short name T902
Test name
Test status
Simulation time 4983724069 ps
CPU time 31.94 seconds
Started Apr 15 02:27:57 PM PDT 24
Finished Apr 15 02:28:30 PM PDT 24
Peak memory 208292 kb
Host smart-33ed4c1e-ea5c-48bc-9e30-d86116861395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431670933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1431670933
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.935486217
Short name T453
Test name
Test status
Simulation time 2018117286 ps
CPU time 65.59 seconds
Started Apr 15 02:27:58 PM PDT 24
Finished Apr 15 02:29:04 PM PDT 24
Peak memory 208728 kb
Host smart-3b896088-ad83-4286-ab42-8de64571e0d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935486217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.935486217
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.705550955
Short name T118
Test name
Test status
Simulation time 141694280 ps
CPU time 2.56 seconds
Started Apr 15 02:27:57 PM PDT 24
Finished Apr 15 02:28:01 PM PDT 24
Peak memory 207092 kb
Host smart-4059dda3-d8b6-4ad7-b35d-254d7b87a9b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705550955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.705550955
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2696319273
Short name T715
Test name
Test status
Simulation time 22164591989 ps
CPU time 42.16 seconds
Started Apr 15 02:28:02 PM PDT 24
Finished Apr 15 02:28:45 PM PDT 24
Peak memory 208308 kb
Host smart-7009d55c-aa7e-4f4f-b671-20d165d07dec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696319273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2696319273
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.973001283
Short name T583
Test name
Test status
Simulation time 235751901 ps
CPU time 4.71 seconds
Started Apr 15 02:28:04 PM PDT 24
Finished Apr 15 02:28:09 PM PDT 24
Peak memory 208824 kb
Host smart-284d96b9-80b2-434f-99b1-51d89a30441b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973001283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.973001283
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2481811975
Short name T436
Test name
Test status
Simulation time 116666728 ps
CPU time 3.17 seconds
Started Apr 15 02:27:57 PM PDT 24
Finished Apr 15 02:28:01 PM PDT 24
Peak memory 207044 kb
Host smart-bef37a66-88f2-460c-b8e8-3ca45d2eb777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481811975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2481811975
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3396703251
Short name T700
Test name
Test status
Simulation time 62319812 ps
CPU time 0.76 seconds
Started Apr 15 02:28:02 PM PDT 24
Finished Apr 15 02:28:04 PM PDT 24
Peak memory 206180 kb
Host smart-956b0a75-bb83-4b01-a10b-a2c11a4ab307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396703251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3396703251
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3695077883
Short name T179
Test name
Test status
Simulation time 1342105019 ps
CPU time 10.93 seconds
Started Apr 15 02:27:59 PM PDT 24
Finished Apr 15 02:28:10 PM PDT 24
Peak memory 220540 kb
Host smart-e3f097f1-bbb2-46ff-8def-061573dc4556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695077883 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3695077883
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3012828777
Short name T673
Test name
Test status
Simulation time 827319682 ps
CPU time 9.19 seconds
Started Apr 15 02:27:57 PM PDT 24
Finished Apr 15 02:28:08 PM PDT 24
Peak memory 209572 kb
Host smart-8428f8f1-5051-4e72-a17d-2d4842caf02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012828777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3012828777
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.87398757
Short name T150
Test name
Test status
Simulation time 30673913 ps
CPU time 1.31 seconds
Started Apr 15 02:28:03 PM PDT 24
Finished Apr 15 02:28:05 PM PDT 24
Peak memory 208756 kb
Host smart-cd25d012-0256-4746-a6fb-23cff0848841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87398757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.87398757
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.533367844
Short name T465
Test name
Test status
Simulation time 51518386 ps
CPU time 0.76 seconds
Started Apr 15 02:28:05 PM PDT 24
Finished Apr 15 02:28:06 PM PDT 24
Peak memory 206304 kb
Host smart-5f309171-fdb7-430c-9ca9-000153f70c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533367844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.533367844
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3897808266
Short name T820
Test name
Test status
Simulation time 109081734 ps
CPU time 3.04 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:05 PM PDT 24
Peak memory 209352 kb
Host smart-8a0e9abe-395b-4d9f-85da-f4f04c258a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897808266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3897808266
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3241800510
Short name T454
Test name
Test status
Simulation time 91745566 ps
CPU time 3.78 seconds
Started Apr 15 02:28:03 PM PDT 24
Finished Apr 15 02:28:08 PM PDT 24
Peak memory 209952 kb
Host smart-fa044f27-c0c9-4b21-8ac6-009cb6cca9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241800510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3241800510
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3314515992
Short name T863
Test name
Test status
Simulation time 75558143 ps
CPU time 3.51 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:05 PM PDT 24
Peak memory 214620 kb
Host smart-e305b2f8-a343-411b-af1f-dec3f0e908ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314515992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3314515992
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1196594560
Short name T529
Test name
Test status
Simulation time 607739292 ps
CPU time 5.45 seconds
Started Apr 15 02:28:04 PM PDT 24
Finished Apr 15 02:28:10 PM PDT 24
Peak memory 207960 kb
Host smart-d221616b-ff5b-4564-9432-1523491ee4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196594560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1196594560
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.85723001
Short name T376
Test name
Test status
Simulation time 209407562 ps
CPU time 3.07 seconds
Started Apr 15 02:28:02 PM PDT 24
Finished Apr 15 02:28:06 PM PDT 24
Peak memory 207168 kb
Host smart-049bc21c-e625-460e-aaff-7a8a0ad2024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85723001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.85723001
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.989494549
Short name T508
Test name
Test status
Simulation time 272167654 ps
CPU time 5.95 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:08 PM PDT 24
Peak memory 208484 kb
Host smart-825b7c9b-4216-40b2-94b3-1eacaa5efc89
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989494549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.989494549
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.371167324
Short name T768
Test name
Test status
Simulation time 385998594 ps
CPU time 5.94 seconds
Started Apr 15 02:28:02 PM PDT 24
Finished Apr 15 02:28:09 PM PDT 24
Peak memory 209220 kb
Host smart-e3ae944c-3637-471a-92c0-d578329fef9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371167324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.371167324
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1610227413
Short name T479
Test name
Test status
Simulation time 1063051148 ps
CPU time 8.86 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:10 PM PDT 24
Peak memory 208208 kb
Host smart-2796f6a7-8cbe-4587-82e3-53f85b415184
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610227413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1610227413
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1603236973
Short name T510
Test name
Test status
Simulation time 36248888 ps
CPU time 2.36 seconds
Started Apr 15 02:28:03 PM PDT 24
Finished Apr 15 02:28:06 PM PDT 24
Peak memory 216072 kb
Host smart-596fe251-25c8-4dab-b781-a1f9b920d6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603236973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1603236973
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3774183559
Short name T124
Test name
Test status
Simulation time 202289068 ps
CPU time 3.62 seconds
Started Apr 15 02:28:02 PM PDT 24
Finished Apr 15 02:28:07 PM PDT 24
Peak memory 206952 kb
Host smart-d9403573-7e75-478d-abc8-9bef1eb8176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774183559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3774183559
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3499824148
Short name T296
Test name
Test status
Simulation time 18553243896 ps
CPU time 554.06 seconds
Started Apr 15 02:28:00 PM PDT 24
Finished Apr 15 02:37:15 PM PDT 24
Peak memory 222884 kb
Host smart-c5720c1e-c549-4a5d-8d14-64cdba401eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499824148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3499824148
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2012051821
Short name T610
Test name
Test status
Simulation time 1362084204 ps
CPU time 9.52 seconds
Started Apr 15 02:28:02 PM PDT 24
Finished Apr 15 02:28:12 PM PDT 24
Peak memory 209172 kb
Host smart-be1e6ac0-b5c6-4865-a5bc-29b4ed9c7cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012051821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2012051821
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3762948647
Short name T126
Test name
Test status
Simulation time 577983576 ps
CPU time 9.74 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:12 PM PDT 24
Peak memory 211104 kb
Host smart-d1ebca38-fd2d-4f0d-b979-7563ed172b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762948647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3762948647
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2614249482
Short name T631
Test name
Test status
Simulation time 14952412 ps
CPU time 0.79 seconds
Started Apr 15 02:28:07 PM PDT 24
Finished Apr 15 02:28:08 PM PDT 24
Peak memory 206272 kb
Host smart-476bc120-2c94-4022-8143-c9b5d70fefe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614249482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2614249482
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1674111860
Short name T154
Test name
Test status
Simulation time 130663714 ps
CPU time 2.87 seconds
Started Apr 15 02:28:08 PM PDT 24
Finished Apr 15 02:28:12 PM PDT 24
Peak memory 214592 kb
Host smart-e38b6bf9-44dc-4723-9287-a6470860a4ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674111860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1674111860
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1240621296
Short name T803
Test name
Test status
Simulation time 157913317 ps
CPU time 2.44 seconds
Started Apr 15 02:28:05 PM PDT 24
Finished Apr 15 02:28:09 PM PDT 24
Peak memory 209152 kb
Host smart-8210c890-c49d-4a3d-b6a1-9abca1c42da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240621296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1240621296
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.440604134
Short name T348
Test name
Test status
Simulation time 904424484 ps
CPU time 23.51 seconds
Started Apr 15 02:28:09 PM PDT 24
Finished Apr 15 02:28:33 PM PDT 24
Peak memory 221824 kb
Host smart-33420d87-1613-4c97-8f6c-73643cc58260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440604134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.440604134
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2854355722
Short name T318
Test name
Test status
Simulation time 246111161 ps
CPU time 6.24 seconds
Started Apr 15 02:28:30 PM PDT 24
Finished Apr 15 02:28:37 PM PDT 24
Peak memory 214632 kb
Host smart-b125a32d-5cb5-444d-b79c-3e35cbb193c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854355722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2854355722
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2428196826
Short name T766
Test name
Test status
Simulation time 666999526 ps
CPU time 13.36 seconds
Started Apr 15 02:28:12 PM PDT 24
Finished Apr 15 02:28:26 PM PDT 24
Peak memory 214604 kb
Host smart-5305607f-c236-4b3d-875a-ebd741efacc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428196826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2428196826
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_random.3841167291
Short name T838
Test name
Test status
Simulation time 232498798 ps
CPU time 6.65 seconds
Started Apr 15 02:28:00 PM PDT 24
Finished Apr 15 02:28:08 PM PDT 24
Peak memory 208496 kb
Host smart-1c7e81d4-ff64-4b9b-9a56-248ef5dd2142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841167291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3841167291
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3529421671
Short name T218
Test name
Test status
Simulation time 244039877 ps
CPU time 3.4 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:06 PM PDT 24
Peak memory 206992 kb
Host smart-477d980f-c174-4627-8cc3-cf0e0b3e5c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529421671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3529421671
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.937074781
Short name T579
Test name
Test status
Simulation time 71560854 ps
CPU time 3.17 seconds
Started Apr 15 02:28:04 PM PDT 24
Finished Apr 15 02:28:08 PM PDT 24
Peak memory 208288 kb
Host smart-b7b47ce8-51d9-49ed-8d65-a146a97bda87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937074781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.937074781
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2380067343
Short name T563
Test name
Test status
Simulation time 175785574 ps
CPU time 6.1 seconds
Started Apr 15 02:28:00 PM PDT 24
Finished Apr 15 02:28:07 PM PDT 24
Peak memory 208528 kb
Host smart-672079a5-2966-4e48-9eff-c3d19b828902
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380067343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2380067343
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2460794512
Short name T505
Test name
Test status
Simulation time 48913788 ps
CPU time 3.01 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:04 PM PDT 24
Peak memory 209140 kb
Host smart-b818637a-7d5d-4e34-ac8d-314658af0f56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460794512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2460794512
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1575042095
Short name T322
Test name
Test status
Simulation time 102044274 ps
CPU time 2.88 seconds
Started Apr 15 02:28:11 PM PDT 24
Finished Apr 15 02:28:15 PM PDT 24
Peak memory 214664 kb
Host smart-5f4ce85f-9214-4b3d-b96d-27b9f8eac858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575042095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1575042095
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.579292358
Short name T630
Test name
Test status
Simulation time 123794677 ps
CPU time 4.78 seconds
Started Apr 15 02:28:01 PM PDT 24
Finished Apr 15 02:28:06 PM PDT 24
Peak memory 208936 kb
Host smart-8fadcc02-4731-44c6-9bd1-ca9db0693746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579292358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.579292358
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.239092668
Short name T258
Test name
Test status
Simulation time 469597179 ps
CPU time 5.88 seconds
Started Apr 15 02:28:06 PM PDT 24
Finished Apr 15 02:28:12 PM PDT 24
Peak memory 218716 kb
Host smart-9e129bad-d1ca-42cd-b9cc-6fd260af79ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239092668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.239092668
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3655859147
Short name T395
Test name
Test status
Simulation time 58491364 ps
CPU time 1.95 seconds
Started Apr 15 02:28:08 PM PDT 24
Finished Apr 15 02:28:11 PM PDT 24
Peak memory 209972 kb
Host smart-2f82d0e6-0474-4ae7-b775-b8ea47e87f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655859147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3655859147
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.690701216
Short name T541
Test name
Test status
Simulation time 16386983 ps
CPU time 0.85 seconds
Started Apr 15 02:28:14 PM PDT 24
Finished Apr 15 02:28:15 PM PDT 24
Peak memory 206280 kb
Host smart-54984025-95e7-4e61-a8ae-172bdd1f3b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690701216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.690701216
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1012002029
Short name T794
Test name
Test status
Simulation time 5062922979 ps
CPU time 44.16 seconds
Started Apr 15 02:28:11 PM PDT 24
Finished Apr 15 02:28:55 PM PDT 24
Peak memory 223140 kb
Host smart-8074347e-3339-4c36-b9cf-e4094ff78273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012002029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1012002029
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3091457217
Short name T752
Test name
Test status
Simulation time 293031291 ps
CPU time 1.88 seconds
Started Apr 15 02:28:06 PM PDT 24
Finished Apr 15 02:28:09 PM PDT 24
Peak memory 209712 kb
Host smart-338ce7fb-2029-490e-a7b5-d0ee22080a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091457217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3091457217
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.994009940
Short name T561
Test name
Test status
Simulation time 2903630230 ps
CPU time 7.65 seconds
Started Apr 15 02:28:11 PM PDT 24
Finished Apr 15 02:28:20 PM PDT 24
Peak memory 219516 kb
Host smart-750d7204-41f4-457f-87ec-4a461715e182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994009940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.994009940
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.4000601482
Short name T811
Test name
Test status
Simulation time 28095809 ps
CPU time 2.24 seconds
Started Apr 15 02:28:11 PM PDT 24
Finished Apr 15 02:28:14 PM PDT 24
Peak memory 215756 kb
Host smart-1a357e0c-c60a-4eed-8cbc-28c4ec03128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000601482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4000601482
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.481680302
Short name T813
Test name
Test status
Simulation time 379718246 ps
CPU time 4.72 seconds
Started Apr 15 02:28:05 PM PDT 24
Finished Apr 15 02:28:11 PM PDT 24
Peak memory 218600 kb
Host smart-66317d69-f1b3-4abe-bc5f-68500efe94a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481680302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.481680302
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3574468155
Short name T277
Test name
Test status
Simulation time 57971774 ps
CPU time 2.94 seconds
Started Apr 15 02:28:12 PM PDT 24
Finished Apr 15 02:28:16 PM PDT 24
Peak memory 206820 kb
Host smart-334bc0ae-d306-46c6-bfcd-e6e09ccbc205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574468155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3574468155
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2616138825
Short name T777
Test name
Test status
Simulation time 121750097 ps
CPU time 3.34 seconds
Started Apr 15 02:28:09 PM PDT 24
Finished Apr 15 02:28:13 PM PDT 24
Peak memory 207068 kb
Host smart-ae6dae71-8bf6-4549-a8bb-c25c70e4620b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616138825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2616138825
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1607715523
Short name T564
Test name
Test status
Simulation time 158722103 ps
CPU time 4.8 seconds
Started Apr 15 02:28:08 PM PDT 24
Finished Apr 15 02:28:13 PM PDT 24
Peak memory 208144 kb
Host smart-bc7f00a1-355a-44c8-bbf1-991ff295b010
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607715523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1607715523
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2170799834
Short name T445
Test name
Test status
Simulation time 210684410 ps
CPU time 2.92 seconds
Started Apr 15 02:28:11 PM PDT 24
Finished Apr 15 02:28:15 PM PDT 24
Peak memory 208208 kb
Host smart-4daa814d-5dc8-4d1a-88b7-1d025584a1db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170799834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2170799834
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.187455410
Short name T302
Test name
Test status
Simulation time 1010804787 ps
CPU time 9.38 seconds
Started Apr 15 02:28:13 PM PDT 24
Finished Apr 15 02:28:24 PM PDT 24
Peak memory 209636 kb
Host smart-ad63b249-c318-432f-a730-b48c44fe6d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187455410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.187455410
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2573416641
Short name T555
Test name
Test status
Simulation time 288960607 ps
CPU time 2.69 seconds
Started Apr 15 02:28:05 PM PDT 24
Finished Apr 15 02:28:09 PM PDT 24
Peak memory 206880 kb
Host smart-1a323b6f-78a7-40b4-9790-1c0cd4c8621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573416641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2573416641
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2577122549
Short name T355
Test name
Test status
Simulation time 1125424517 ps
CPU time 40.67 seconds
Started Apr 15 02:28:12 PM PDT 24
Finished Apr 15 02:28:54 PM PDT 24
Peak memory 221752 kb
Host smart-f1c2ac79-f2ca-41af-841d-55fc5afdd0a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577122549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2577122549
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3959472974
Short name T327
Test name
Test status
Simulation time 67791209 ps
CPU time 3.95 seconds
Started Apr 15 02:28:12 PM PDT 24
Finished Apr 15 02:28:17 PM PDT 24
Peak memory 218704 kb
Host smart-2c537ee5-eb16-41f8-8b4c-3e44fd3ce942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959472974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3959472974
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1760231972
Short name T636
Test name
Test status
Simulation time 343501415 ps
CPU time 2.15 seconds
Started Apr 15 02:28:13 PM PDT 24
Finished Apr 15 02:28:16 PM PDT 24
Peak memory 210352 kb
Host smart-8fdbd1dd-2761-4fb9-87f0-71a7668110b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760231972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1760231972
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3279644154
Short name T112
Test name
Test status
Simulation time 37366188 ps
CPU time 0.85 seconds
Started Apr 15 02:28:14 PM PDT 24
Finished Apr 15 02:28:16 PM PDT 24
Peak memory 206276 kb
Host smart-6227f9f7-d39c-4ffd-9808-a40d0220fde0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279644154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3279644154
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3342502006
Short name T261
Test name
Test status
Simulation time 167998026 ps
CPU time 3.39 seconds
Started Apr 15 02:28:13 PM PDT 24
Finished Apr 15 02:28:17 PM PDT 24
Peak memory 215400 kb
Host smart-97d8591d-8340-46bd-aef4-dd786e531b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342502006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3342502006
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1325702538
Short name T618
Test name
Test status
Simulation time 75289731 ps
CPU time 1.65 seconds
Started Apr 15 02:28:11 PM PDT 24
Finished Apr 15 02:28:13 PM PDT 24
Peak memory 218568 kb
Host smart-710e51bc-66b0-4567-97f9-60acf2593014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325702538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1325702538
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.4243762994
Short name T25
Test name
Test status
Simulation time 35571572 ps
CPU time 2.29 seconds
Started Apr 15 02:28:14 PM PDT 24
Finished Apr 15 02:28:17 PM PDT 24
Peak memory 220844 kb
Host smart-293a28ae-941f-455a-ac48-cfe24f429382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243762994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4243762994
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1961000057
Short name T880
Test name
Test status
Simulation time 517284868 ps
CPU time 5.37 seconds
Started Apr 15 02:28:12 PM PDT 24
Finished Apr 15 02:28:18 PM PDT 24
Peak memory 222824 kb
Host smart-26e21091-932b-4d4e-b36a-82140c2b8093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961000057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1961000057
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1383097049
Short name T584
Test name
Test status
Simulation time 267546706 ps
CPU time 3.47 seconds
Started Apr 15 02:28:12 PM PDT 24
Finished Apr 15 02:28:16 PM PDT 24
Peak memory 209896 kb
Host smart-a80c3011-079b-41b1-932e-c99fae070fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383097049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1383097049
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.911290176
Short name T527
Test name
Test status
Simulation time 163105198 ps
CPU time 4.06 seconds
Started Apr 15 02:28:16 PM PDT 24
Finished Apr 15 02:28:21 PM PDT 24
Peak memory 210228 kb
Host smart-b630315f-7b30-4eb9-a7fd-0ea6187017c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911290176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.911290176
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2453783410
Short name T473
Test name
Test status
Simulation time 997145817 ps
CPU time 8.68 seconds
Started Apr 15 02:28:16 PM PDT 24
Finished Apr 15 02:28:25 PM PDT 24
Peak memory 208572 kb
Host smart-0bbd7a4c-dfe2-40ea-b601-04bf9755ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453783410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2453783410
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.284237743
Short name T263
Test name
Test status
Simulation time 434759522 ps
CPU time 2.57 seconds
Started Apr 15 02:28:12 PM PDT 24
Finished Apr 15 02:28:16 PM PDT 24
Peak memory 207104 kb
Host smart-192c9ee8-740f-4490-a67e-007861f45ee1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284237743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.284237743
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3501624870
Short name T409
Test name
Test status
Simulation time 1660839489 ps
CPU time 11.89 seconds
Started Apr 15 02:28:24 PM PDT 24
Finished Apr 15 02:28:37 PM PDT 24
Peak memory 207180 kb
Host smart-6a685847-ef97-4ed5-8662-a8613704da59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501624870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3501624870
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1924121190
Short name T681
Test name
Test status
Simulation time 132266456 ps
CPU time 4.76 seconds
Started Apr 15 02:28:16 PM PDT 24
Finished Apr 15 02:28:22 PM PDT 24
Peak memory 209076 kb
Host smart-70d28b44-5524-4dbb-8dd5-2cce8e2563d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924121190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1924121190
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2361942566
Short name T647
Test name
Test status
Simulation time 6566486963 ps
CPU time 14.76 seconds
Started Apr 15 02:28:13 PM PDT 24
Finished Apr 15 02:28:29 PM PDT 24
Peak memory 209924 kb
Host smart-4987c479-c000-44e9-8468-84d7f589e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361942566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2361942566
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1983917358
Short name T773
Test name
Test status
Simulation time 72380488 ps
CPU time 2.36 seconds
Started Apr 15 02:28:10 PM PDT 24
Finished Apr 15 02:28:13 PM PDT 24
Peak memory 207092 kb
Host smart-7cf97895-e81d-4e81-9423-ec64c32ddffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983917358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1983917358
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2957008037
Short name T518
Test name
Test status
Simulation time 458383617 ps
CPU time 5.56 seconds
Started Apr 15 02:28:15 PM PDT 24
Finished Apr 15 02:28:21 PM PDT 24
Peak memory 214688 kb
Host smart-448c7248-4100-4657-961b-bdb2577537f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957008037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2957008037
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.712794548
Short name T887
Test name
Test status
Simulation time 104196920 ps
CPU time 1.65 seconds
Started Apr 15 02:28:14 PM PDT 24
Finished Apr 15 02:28:17 PM PDT 24
Peak memory 208740 kb
Host smart-84b8cddb-4a08-47b1-bee8-3f2cd7f66b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712794548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.712794548
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1316605536
Short name T884
Test name
Test status
Simulation time 51640569 ps
CPU time 0.75 seconds
Started Apr 15 02:28:17 PM PDT 24
Finished Apr 15 02:28:18 PM PDT 24
Peak memory 206204 kb
Host smart-547ebc79-eb04-47e1-ae81-8ebdd0a321b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316605536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1316605536
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2910695676
Short name T427
Test name
Test status
Simulation time 44093526 ps
CPU time 3.54 seconds
Started Apr 15 02:28:18 PM PDT 24
Finished Apr 15 02:28:23 PM PDT 24
Peak memory 214620 kb
Host smart-c1048ca1-f459-40e9-94b0-68e59f035f90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910695676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2910695676
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.242690502
Short name T68
Test name
Test status
Simulation time 6791603773 ps
CPU time 51.6 seconds
Started Apr 15 02:28:21 PM PDT 24
Finished Apr 15 02:29:13 PM PDT 24
Peak memory 215512 kb
Host smart-871af8f9-887a-4e93-b7c3-96e45c8f0b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242690502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.242690502
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.144939018
Short name T511
Test name
Test status
Simulation time 77501949 ps
CPU time 3.64 seconds
Started Apr 15 02:28:13 PM PDT 24
Finished Apr 15 02:28:18 PM PDT 24
Peak memory 210208 kb
Host smart-6f429c53-36f7-4146-8a49-648b2b9995d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144939018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.144939018
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1560805879
Short name T859
Test name
Test status
Simulation time 70633413 ps
CPU time 3.81 seconds
Started Apr 15 02:28:18 PM PDT 24
Finished Apr 15 02:28:23 PM PDT 24
Peak memory 209092 kb
Host smart-a111c460-569c-4b09-9ee0-4e3a37f00fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560805879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1560805879
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.688857884
Short name T58
Test name
Test status
Simulation time 120177308 ps
CPU time 4.38 seconds
Started Apr 15 02:28:20 PM PDT 24
Finished Apr 15 02:28:25 PM PDT 24
Peak memory 212044 kb
Host smart-5adcd7e0-feae-41e3-8ff0-56d3b6d17393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688857884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.688857884
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.1453497213
Short name T3
Test name
Test status
Simulation time 5117659469 ps
CPU time 49.91 seconds
Started Apr 15 02:28:15 PM PDT 24
Finished Apr 15 02:29:05 PM PDT 24
Peak memory 208608 kb
Host smart-41cd668d-ea41-4cb7-b5e1-35eb4d1ef160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453497213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1453497213
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3894086752
Short name T611
Test name
Test status
Simulation time 12962882783 ps
CPU time 17.77 seconds
Started Apr 15 02:28:13 PM PDT 24
Finished Apr 15 02:28:32 PM PDT 24
Peak memory 208392 kb
Host smart-b122b80a-3d87-496e-9abb-b29e730fa815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894086752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3894086752
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2626191640
Short name T503
Test name
Test status
Simulation time 255774803 ps
CPU time 3.64 seconds
Started Apr 15 02:28:16 PM PDT 24
Finished Apr 15 02:28:20 PM PDT 24
Peak memory 207092 kb
Host smart-71075deb-7cd9-44b8-bd8f-286447c54340
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626191640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2626191640
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1236835736
Short name T652
Test name
Test status
Simulation time 1005290874 ps
CPU time 7.68 seconds
Started Apr 15 02:28:15 PM PDT 24
Finished Apr 15 02:28:24 PM PDT 24
Peak memory 208400 kb
Host smart-e9311745-f822-4a84-a693-09af48c0d6ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236835736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1236835736
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2025963365
Short name T865
Test name
Test status
Simulation time 433289831 ps
CPU time 5.24 seconds
Started Apr 15 02:28:16 PM PDT 24
Finished Apr 15 02:28:22 PM PDT 24
Peak memory 207236 kb
Host smart-8a41786c-cea4-4c92-94b3-c9d5b46a4e7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025963365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2025963365
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1852248189
Short name T841
Test name
Test status
Simulation time 46872735 ps
CPU time 2.66 seconds
Started Apr 15 02:28:18 PM PDT 24
Finished Apr 15 02:28:22 PM PDT 24
Peak memory 209432 kb
Host smart-59c0d7c8-75cd-47b1-9c7e-d4192de7db8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852248189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1852248189
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2361725095
Short name T442
Test name
Test status
Simulation time 993185277 ps
CPU time 24.53 seconds
Started Apr 15 02:28:16 PM PDT 24
Finished Apr 15 02:28:41 PM PDT 24
Peak memory 208576 kb
Host smart-31b675af-ef02-4fac-b3d6-159348677bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361725095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2361725095
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2638233128
Short name T81
Test name
Test status
Simulation time 2970216322 ps
CPU time 65.86 seconds
Started Apr 15 02:28:18 PM PDT 24
Finished Apr 15 02:29:25 PM PDT 24
Peak memory 216272 kb
Host smart-5edde3b2-69be-43bf-be42-63bebc2fbcf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638233128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2638233128
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1150019495
Short name T219
Test name
Test status
Simulation time 81640731 ps
CPU time 4.05 seconds
Started Apr 15 02:28:19 PM PDT 24
Finished Apr 15 02:28:24 PM PDT 24
Peak memory 209356 kb
Host smart-966d96c2-1d21-4dee-aeb6-df5665bf6ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150019495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1150019495
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1304038706
Short name T63
Test name
Test status
Simulation time 132500741 ps
CPU time 4.38 seconds
Started Apr 15 02:28:18 PM PDT 24
Finished Apr 15 02:28:23 PM PDT 24
Peak memory 210496 kb
Host smart-ece89210-f0b9-46b8-87c0-472ccc50838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304038706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1304038706
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3100622430
Short name T855
Test name
Test status
Simulation time 8980752 ps
CPU time 0.71 seconds
Started Apr 15 02:28:29 PM PDT 24
Finished Apr 15 02:28:30 PM PDT 24
Peak memory 206372 kb
Host smart-d7a9d383-7086-4a30-927b-229da6492e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100622430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3100622430
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3524135026
Short name T201
Test name
Test status
Simulation time 443052535 ps
CPU time 2.63 seconds
Started Apr 15 02:28:24 PM PDT 24
Finished Apr 15 02:28:28 PM PDT 24
Peak memory 222972 kb
Host smart-103b4d3f-974e-40ec-8af0-0b4b6479e76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524135026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3524135026
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.514722739
Short name T520
Test name
Test status
Simulation time 393792509 ps
CPU time 4.89 seconds
Started Apr 15 02:28:22 PM PDT 24
Finished Apr 15 02:28:28 PM PDT 24
Peak memory 210616 kb
Host smart-a1ef3748-bf01-4363-ac39-49c13cc9bfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514722739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.514722739
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1221129555
Short name T273
Test name
Test status
Simulation time 547076718 ps
CPU time 2.54 seconds
Started Apr 15 02:28:26 PM PDT 24
Finished Apr 15 02:28:29 PM PDT 24
Peak memory 214656 kb
Host smart-b82b1f5f-4492-438a-b145-6b86ca4f1cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221129555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1221129555
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2830660400
Short name T633
Test name
Test status
Simulation time 107465273 ps
CPU time 5.12 seconds
Started Apr 15 02:28:24 PM PDT 24
Finished Apr 15 02:28:30 PM PDT 24
Peak memory 212268 kb
Host smart-2cac7bfd-79d4-43cd-95dd-d2b5f0614875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830660400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2830660400
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1917249766
Short name T482
Test name
Test status
Simulation time 167698064 ps
CPU time 2.4 seconds
Started Apr 15 02:28:25 PM PDT 24
Finished Apr 15 02:28:28 PM PDT 24
Peak memory 209968 kb
Host smart-8677f957-740a-4193-a8bb-2a95652517b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917249766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1917249766
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2570401015
Short name T848
Test name
Test status
Simulation time 137962073 ps
CPU time 5.94 seconds
Started Apr 15 02:28:21 PM PDT 24
Finished Apr 15 02:28:28 PM PDT 24
Peak memory 209428 kb
Host smart-6b00ef17-c290-4539-ac2d-842be908b1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570401015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2570401015
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1831780794
Short name T605
Test name
Test status
Simulation time 255268012 ps
CPU time 4.55 seconds
Started Apr 15 02:28:19 PM PDT 24
Finished Apr 15 02:28:24 PM PDT 24
Peak memory 208108 kb
Host smart-8cea2926-809b-4bbc-a6c7-957664da8660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831780794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1831780794
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1147960728
Short name T502
Test name
Test status
Simulation time 101085093 ps
CPU time 3.3 seconds
Started Apr 15 02:28:20 PM PDT 24
Finished Apr 15 02:28:24 PM PDT 24
Peak memory 208752 kb
Host smart-2c83385c-1d5f-4735-b1e3-3c750a7c040b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147960728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1147960728
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3486476712
Short name T900
Test name
Test status
Simulation time 227954746 ps
CPU time 5.03 seconds
Started Apr 15 02:28:19 PM PDT 24
Finished Apr 15 02:28:25 PM PDT 24
Peak memory 207188 kb
Host smart-c59e2043-06c2-4388-af02-8b9f7be7c35d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486476712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3486476712
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.411144910
Short name T762
Test name
Test status
Simulation time 320041769 ps
CPU time 3.65 seconds
Started Apr 15 02:28:18 PM PDT 24
Finished Apr 15 02:28:22 PM PDT 24
Peak memory 209048 kb
Host smart-1ebb1be8-51a6-40b8-a7b9-7875267d8d79
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411144910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.411144910
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1505071060
Short name T402
Test name
Test status
Simulation time 50902571 ps
CPU time 2.28 seconds
Started Apr 15 02:28:25 PM PDT 24
Finished Apr 15 02:28:28 PM PDT 24
Peak memory 210372 kb
Host smart-bb49dee6-99b2-4efe-b62f-759e85db833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505071060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1505071060
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2704077713
Short name T531
Test name
Test status
Simulation time 915179376 ps
CPU time 4.34 seconds
Started Apr 15 02:28:19 PM PDT 24
Finished Apr 15 02:28:24 PM PDT 24
Peak memory 208296 kb
Host smart-6cce5e53-401c-455c-9f1c-7efbd1f31fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704077713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2704077713
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1337762653
Short name T142
Test name
Test status
Simulation time 2470714323 ps
CPU time 19.09 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 222940 kb
Host smart-998beb90-bfff-48be-a9bd-785ba5f112df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337762653 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1337762653
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.853042207
Short name T517
Test name
Test status
Simulation time 107718757 ps
CPU time 3.53 seconds
Started Apr 15 02:28:24 PM PDT 24
Finished Apr 15 02:28:29 PM PDT 24
Peak memory 208508 kb
Host smart-263a5b77-eedc-4316-aca7-1e1e978110f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853042207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.853042207
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2843212475
Short name T500
Test name
Test status
Simulation time 246291343 ps
CPU time 2.99 seconds
Started Apr 15 02:28:25 PM PDT 24
Finished Apr 15 02:28:29 PM PDT 24
Peak memory 210224 kb
Host smart-f6db74bc-7131-4735-9a84-03622a517ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843212475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2843212475
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.4169508492
Short name T571
Test name
Test status
Simulation time 31746392 ps
CPU time 0.73 seconds
Started Apr 15 02:28:28 PM PDT 24
Finished Apr 15 02:28:30 PM PDT 24
Peak memory 206268 kb
Host smart-5b34cdda-c401-4620-8c2d-e5c7666aadb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169508492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.4169508492
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3887570987
Short name T779
Test name
Test status
Simulation time 93390470 ps
CPU time 3.78 seconds
Started Apr 15 02:28:27 PM PDT 24
Finished Apr 15 02:28:32 PM PDT 24
Peak memory 210092 kb
Host smart-88233c2d-95a3-4a78-9c97-884ede90be3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887570987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3887570987
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3263766029
Short name T290
Test name
Test status
Simulation time 187847567 ps
CPU time 2.75 seconds
Started Apr 15 02:28:24 PM PDT 24
Finished Apr 15 02:28:28 PM PDT 24
Peak memory 208468 kb
Host smart-bbbe6779-a73e-475a-9593-4bdc51640262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263766029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3263766029
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.943659553
Short name T717
Test name
Test status
Simulation time 314461753 ps
CPU time 11.61 seconds
Started Apr 15 02:28:28 PM PDT 24
Finished Apr 15 02:28:40 PM PDT 24
Peak memory 222840 kb
Host smart-a43fb14b-1eed-4207-abec-32cb3b52bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943659553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.943659553
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1332353233
Short name T252
Test name
Test status
Simulation time 76526025 ps
CPU time 3.76 seconds
Started Apr 15 02:28:31 PM PDT 24
Finished Apr 15 02:28:36 PM PDT 24
Peak memory 209380 kb
Host smart-20ee4aa1-47dc-46a2-923f-9a5532f1b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332353233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1332353233
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2365700187
Short name T461
Test name
Test status
Simulation time 1223747756 ps
CPU time 27.89 seconds
Started Apr 15 02:28:24 PM PDT 24
Finished Apr 15 02:28:53 PM PDT 24
Peak memory 208944 kb
Host smart-9424c2eb-9ee4-4cf9-809c-a2b557cc04a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365700187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2365700187
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3607473539
Short name T2
Test name
Test status
Simulation time 790561298 ps
CPU time 22.19 seconds
Started Apr 15 02:28:23 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 208664 kb
Host smart-eaee73d9-afa4-49dc-b5c6-8d6b31663ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607473539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3607473539
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3303763256
Short name T706
Test name
Test status
Simulation time 176398528 ps
CPU time 2.87 seconds
Started Apr 15 02:28:24 PM PDT 24
Finished Apr 15 02:28:28 PM PDT 24
Peak memory 208896 kb
Host smart-13eb9fa8-72c9-46d9-9141-ab0d2dc690f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303763256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3303763256
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.477461465
Short name T757
Test name
Test status
Simulation time 6436069033 ps
CPU time 41.65 seconds
Started Apr 15 02:28:25 PM PDT 24
Finished Apr 15 02:29:08 PM PDT 24
Peak memory 208540 kb
Host smart-d553b452-6072-41f6-8e51-97da1fab42ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477461465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.477461465
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2471288239
Short name T857
Test name
Test status
Simulation time 212628312 ps
CPU time 3.32 seconds
Started Apr 15 02:28:24 PM PDT 24
Finished Apr 15 02:28:28 PM PDT 24
Peak memory 209004 kb
Host smart-a92b2289-e15f-4dbe-b05c-3b7671eaccfa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471288239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2471288239
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4286157999
Short name T577
Test name
Test status
Simulation time 502617649 ps
CPU time 12.37 seconds
Started Apr 15 02:28:31 PM PDT 24
Finished Apr 15 02:28:45 PM PDT 24
Peak memory 208144 kb
Host smart-3ff7f5d4-e1ef-446e-bd8e-40c6fafe71e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286157999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4286157999
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2042681698
Short name T438
Test name
Test status
Simulation time 18302052726 ps
CPU time 50.03 seconds
Started Apr 15 02:28:26 PM PDT 24
Finished Apr 15 02:29:17 PM PDT 24
Peak memory 209264 kb
Host smart-cff8dad5-325f-4ba1-aba4-5f2907640300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042681698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2042681698
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2600811654
Short name T180
Test name
Test status
Simulation time 274556277 ps
CPU time 7.11 seconds
Started Apr 15 02:28:32 PM PDT 24
Finished Apr 15 02:28:39 PM PDT 24
Peak memory 222952 kb
Host smart-ba37dab2-6122-4cbb-9b67-908dacc94bb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600811654 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2600811654
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2366314540
Short name T566
Test name
Test status
Simulation time 270112995 ps
CPU time 3.73 seconds
Started Apr 15 02:28:28 PM PDT 24
Finished Apr 15 02:28:33 PM PDT 24
Peak memory 218496 kb
Host smart-d3983cc0-9051-4326-a718-6c4b8e11e970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366314540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2366314540
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1512491748
Short name T617
Test name
Test status
Simulation time 78619623 ps
CPU time 2.12 seconds
Started Apr 15 02:28:30 PM PDT 24
Finished Apr 15 02:28:33 PM PDT 24
Peak memory 210308 kb
Host smart-d62429f4-5586-40f8-8c44-a8fe0a9e7e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512491748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1512491748
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.842741115
Short name T110
Test name
Test status
Simulation time 27930901 ps
CPU time 0.93 seconds
Started Apr 15 02:28:32 PM PDT 24
Finished Apr 15 02:28:33 PM PDT 24
Peak memory 206360 kb
Host smart-bb1ce926-9f7d-4af4-9160-f871d98cb7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842741115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.842741115
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2059103089
Short name T33
Test name
Test status
Simulation time 34714077 ps
CPU time 1.95 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:28:45 PM PDT 24
Peak memory 214508 kb
Host smart-45b7037b-8c10-4c7c-bb47-15c9423e2dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059103089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2059103089
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3878217856
Short name T47
Test name
Test status
Simulation time 69978124 ps
CPU time 3.31 seconds
Started Apr 15 02:28:37 PM PDT 24
Finished Apr 15 02:28:41 PM PDT 24
Peak memory 218636 kb
Host smart-a50a42fb-947d-442c-9c4b-554f41f0401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878217856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3878217856
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3453185208
Short name T253
Test name
Test status
Simulation time 235248435 ps
CPU time 3.55 seconds
Started Apr 15 02:28:31 PM PDT 24
Finished Apr 15 02:28:35 PM PDT 24
Peak memory 209652 kb
Host smart-07acc21c-d9bf-4030-89ce-a3896c20f419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453185208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3453185208
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1425106830
Short name T117
Test name
Test status
Simulation time 343514252 ps
CPU time 2.52 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:36 PM PDT 24
Peak memory 208012 kb
Host smart-92f73c6f-68bb-4139-b86e-aadf9e6f182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425106830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1425106830
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3954637397
Short name T738
Test name
Test status
Simulation time 598662222 ps
CPU time 4.82 seconds
Started Apr 15 02:28:27 PM PDT 24
Finished Apr 15 02:28:33 PM PDT 24
Peak memory 208788 kb
Host smart-8d2c39cc-b552-4884-961d-18d30d20e3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954637397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3954637397
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1228266004
Short name T214
Test name
Test status
Simulation time 42930468 ps
CPU time 2.98 seconds
Started Apr 15 02:28:32 PM PDT 24
Finished Apr 15 02:28:36 PM PDT 24
Peak memory 209272 kb
Host smart-42eb9dd0-f129-4fb0-8c88-2f9c53f0fe19
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228266004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1228266004
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4168361704
Short name T693
Test name
Test status
Simulation time 75994878 ps
CPU time 2.49 seconds
Started Apr 15 02:28:30 PM PDT 24
Finished Apr 15 02:28:33 PM PDT 24
Peak memory 207132 kb
Host smart-9f3d3c41-a843-4ca7-aaf7-4fdc61566fe5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168361704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4168361704
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2007752296
Short name T780
Test name
Test status
Simulation time 3822720574 ps
CPU time 21.93 seconds
Started Apr 15 02:28:32 PM PDT 24
Finished Apr 15 02:28:55 PM PDT 24
Peak memory 209024 kb
Host smart-cce7a06a-e753-4c48-be50-d6c36f49e958
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007752296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2007752296
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1688072477
Short name T871
Test name
Test status
Simulation time 372549594 ps
CPU time 4.48 seconds
Started Apr 15 02:28:37 PM PDT 24
Finished Apr 15 02:28:43 PM PDT 24
Peak memory 210204 kb
Host smart-ba4a3051-1232-47bc-9d4f-7ec979ec5cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688072477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1688072477
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1963710396
Short name T13
Test name
Test status
Simulation time 194555913 ps
CPU time 2.54 seconds
Started Apr 15 02:28:28 PM PDT 24
Finished Apr 15 02:28:31 PM PDT 24
Peak memory 207068 kb
Host smart-a7d3b148-222d-4fd6-8a2b-fa4df67d2eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963710396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1963710396
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.697578069
Short name T623
Test name
Test status
Simulation time 7285902268 ps
CPU time 135.7 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:30:59 PM PDT 24
Peak memory 222880 kb
Host smart-6c6bd2e2-663e-4f84-baa5-24793f02221d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697578069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.697578069
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3294165656
Short name T226
Test name
Test status
Simulation time 1634084777 ps
CPU time 4.69 seconds
Started Apr 15 02:28:30 PM PDT 24
Finished Apr 15 02:28:36 PM PDT 24
Peak memory 209540 kb
Host smart-53dde8be-5792-4c24-a4de-730bb899bb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294165656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3294165656
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1647272126
Short name T504
Test name
Test status
Simulation time 5689837595 ps
CPU time 35.76 seconds
Started Apr 15 02:28:35 PM PDT 24
Finished Apr 15 02:29:12 PM PDT 24
Peak memory 212060 kb
Host smart-18fecad1-9363-4675-a2ff-20041f46351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647272126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1647272126
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1584576144
Short name T698
Test name
Test status
Simulation time 31915068 ps
CPU time 0.76 seconds
Started Apr 15 02:26:24 PM PDT 24
Finished Apr 15 02:26:25 PM PDT 24
Peak memory 206292 kb
Host smart-5862c7d9-3a75-4e72-9d91-db985866e465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584576144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1584576144
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3753629273
Short name T340
Test name
Test status
Simulation time 112299497 ps
CPU time 2.57 seconds
Started Apr 15 02:26:20 PM PDT 24
Finished Apr 15 02:26:24 PM PDT 24
Peak memory 214604 kb
Host smart-81b3c775-30a6-4f32-8eef-604a49cbb062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753629273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3753629273
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4242170425
Short name T347
Test name
Test status
Simulation time 22489548 ps
CPU time 1.21 seconds
Started Apr 15 02:26:24 PM PDT 24
Finished Apr 15 02:26:26 PM PDT 24
Peak memory 208068 kb
Host smart-2739d140-36a0-41a0-9078-52eb80129a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242170425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4242170425
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3189586178
Short name T726
Test name
Test status
Simulation time 280060736 ps
CPU time 3.68 seconds
Started Apr 15 02:26:23 PM PDT 24
Finished Apr 15 02:26:28 PM PDT 24
Peak memory 214552 kb
Host smart-6d34e273-4ebe-4b4e-8123-806674b38719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189586178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3189586178
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.317376178
Short name T824
Test name
Test status
Simulation time 1034066022 ps
CPU time 22.41 seconds
Started Apr 15 02:26:20 PM PDT 24
Finished Apr 15 02:26:43 PM PDT 24
Peak memory 208560 kb
Host smart-0ae8d1ab-09a3-433e-ac97-c9869d35bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317376178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.317376178
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2579880248
Short name T41
Test name
Test status
Simulation time 2425752417 ps
CPU time 28.25 seconds
Started Apr 15 02:26:23 PM PDT 24
Finished Apr 15 02:26:52 PM PDT 24
Peak memory 236516 kb
Host smart-d82212fd-5ccc-47ea-a6a7-a1c05fa51bc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579880248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2579880248
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.243790340
Short name T712
Test name
Test status
Simulation time 1032722068 ps
CPU time 6.65 seconds
Started Apr 15 02:26:17 PM PDT 24
Finished Apr 15 02:26:25 PM PDT 24
Peak memory 208216 kb
Host smart-22f3293f-b4b3-48ab-a99d-44b401b62aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243790340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.243790340
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3198010316
Short name T259
Test name
Test status
Simulation time 201384771 ps
CPU time 5.5 seconds
Started Apr 15 02:26:18 PM PDT 24
Finished Apr 15 02:26:25 PM PDT 24
Peak memory 208344 kb
Host smart-df142f25-7092-43df-b0ce-99233f16a408
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198010316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3198010316
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.771560135
Short name T616
Test name
Test status
Simulation time 3953433347 ps
CPU time 65.7 seconds
Started Apr 15 02:26:17 PM PDT 24
Finished Apr 15 02:27:23 PM PDT 24
Peak memory 209392 kb
Host smart-ea96c1ee-a3cb-43a1-85ae-bcbe97262dd0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771560135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.771560135
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.753541377
Short name T540
Test name
Test status
Simulation time 224074400 ps
CPU time 5.06 seconds
Started Apr 15 02:26:19 PM PDT 24
Finished Apr 15 02:26:24 PM PDT 24
Peak memory 208180 kb
Host smart-95228021-a504-4040-8ea5-e113170cbd28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753541377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.753541377
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1114319243
Short name T806
Test name
Test status
Simulation time 338402993 ps
CPU time 4.21 seconds
Started Apr 15 02:26:22 PM PDT 24
Finished Apr 15 02:26:27 PM PDT 24
Peak memory 214616 kb
Host smart-31536dfa-29dc-4796-82fc-984e5d173fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114319243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1114319243
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3694900473
Short name T728
Test name
Test status
Simulation time 92800788 ps
CPU time 2.46 seconds
Started Apr 15 02:26:17 PM PDT 24
Finished Apr 15 02:26:20 PM PDT 24
Peak memory 208656 kb
Host smart-53651a30-7775-422d-8636-3938e460c848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694900473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3694900473
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1102514528
Short name T375
Test name
Test status
Simulation time 7637157581 ps
CPU time 58.6 seconds
Started Apr 15 02:26:23 PM PDT 24
Finished Apr 15 02:27:22 PM PDT 24
Peak memory 222904 kb
Host smart-7924d0c9-e580-4bfe-a30a-da7d779db4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102514528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1102514528
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.43269694
Short name T709
Test name
Test status
Simulation time 579500762 ps
CPU time 6.14 seconds
Started Apr 15 02:26:22 PM PDT 24
Finished Apr 15 02:26:28 PM PDT 24
Peak memory 209520 kb
Host smart-bb3b35ae-2ff8-4730-b592-b95d7e18073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43269694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.43269694
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1401102541
Short name T212
Test name
Test status
Simulation time 26185818 ps
CPU time 0.88 seconds
Started Apr 15 02:28:40 PM PDT 24
Finished Apr 15 02:28:43 PM PDT 24
Peak memory 206444 kb
Host smart-b8e37c28-0f1b-4f45-8e3a-a8f8bcd36ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401102541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1401102541
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2649719559
Short name T423
Test name
Test status
Simulation time 966959667 ps
CPU time 4.78 seconds
Started Apr 15 02:28:35 PM PDT 24
Finished Apr 15 02:28:40 PM PDT 24
Peak memory 214636 kb
Host smart-952fd30a-ad3e-4097-90fd-d814279be37a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649719559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2649719559
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1921661466
Short name T21
Test name
Test status
Simulation time 137575056 ps
CPU time 4.38 seconds
Started Apr 15 02:28:37 PM PDT 24
Finished Apr 15 02:28:42 PM PDT 24
Peak memory 210172 kb
Host smart-6644036d-b942-4f1a-9aaa-2af5a09167b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921661466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1921661466
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.470343361
Short name T891
Test name
Test status
Simulation time 155841648 ps
CPU time 4.98 seconds
Started Apr 15 02:28:34 PM PDT 24
Finished Apr 15 02:28:40 PM PDT 24
Peak memory 214564 kb
Host smart-ba328977-f430-4a28-ab48-b6e9c72e6e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470343361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.470343361
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1869434308
Short name T595
Test name
Test status
Simulation time 638770454 ps
CPU time 5.35 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:40 PM PDT 24
Peak memory 221664 kb
Host smart-d3e58411-3756-4f2c-a0cb-5124c34758dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869434308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1869434308
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1158718360
Short name T233
Test name
Test status
Simulation time 125395765 ps
CPU time 3.65 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:46 PM PDT 24
Peak memory 211448 kb
Host smart-e7c0fe70-6a61-442a-a8cf-25872fb4f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158718360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1158718360
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.4192455630
Short name T796
Test name
Test status
Simulation time 168826312 ps
CPU time 1.82 seconds
Started Apr 15 02:28:40 PM PDT 24
Finished Apr 15 02:28:44 PM PDT 24
Peak memory 207912 kb
Host smart-d62926c6-399f-44f2-aa26-76edef3c111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192455630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.4192455630
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3039312253
Short name T401
Test name
Test status
Simulation time 344439922 ps
CPU time 4.41 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:38 PM PDT 24
Peak memory 214676 kb
Host smart-84050356-02e1-4d74-9db1-f79cf02cceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039312253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3039312253
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3625551878
Short name T699
Test name
Test status
Simulation time 154123749 ps
CPU time 4.6 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:39 PM PDT 24
Peak memory 209120 kb
Host smart-ef135718-2984-42a6-a3ee-eeb4b27e26a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625551878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3625551878
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2568460554
Short name T153
Test name
Test status
Simulation time 45192752 ps
CPU time 1.99 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:44 PM PDT 24
Peak memory 207560 kb
Host smart-c01ba761-a163-4775-84ca-cdd91cf041cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568460554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2568460554
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3368121563
Short name T775
Test name
Test status
Simulation time 4531549381 ps
CPU time 26.25 seconds
Started Apr 15 02:28:36 PM PDT 24
Finished Apr 15 02:29:03 PM PDT 24
Peak memory 208348 kb
Host smart-acbaf1da-9f24-4584-837b-0da5e8b47667
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368121563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3368121563
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.828958523
Short name T646
Test name
Test status
Simulation time 935960314 ps
CPU time 3.3 seconds
Started Apr 15 02:28:38 PM PDT 24
Finished Apr 15 02:28:43 PM PDT 24
Peak memory 207148 kb
Host smart-f58f403e-b426-4ac6-a676-279cfe1a01f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828958523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.828958523
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1138590344
Short name T680
Test name
Test status
Simulation time 1807562108 ps
CPU time 9.21 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:43 PM PDT 24
Peak memory 209152 kb
Host smart-3a56efd3-145c-454c-945f-2923fde704a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138590344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1138590344
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3757647493
Short name T760
Test name
Test status
Simulation time 77073061 ps
CPU time 2.51 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:37 PM PDT 24
Peak memory 208908 kb
Host smart-4165b25c-28a2-47b4-83dc-5257da0000f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757647493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3757647493
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.4080762706
Short name T365
Test name
Test status
Simulation time 589263650 ps
CPU time 24.47 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:59 PM PDT 24
Peak memory 215344 kb
Host smart-42926141-c58b-45bb-8c02-674100a39dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080762706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.4080762706
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3336267006
Short name T222
Test name
Test status
Simulation time 908078692 ps
CPU time 9.7 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:43 PM PDT 24
Peak memory 208176 kb
Host smart-6f19aaf5-4d97-4467-8bec-86b2bbaaccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336267006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3336267006
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.47657780
Short name T152
Test name
Test status
Simulation time 75862320 ps
CPU time 2.92 seconds
Started Apr 15 02:28:36 PM PDT 24
Finished Apr 15 02:28:40 PM PDT 24
Peak memory 210428 kb
Host smart-2276eed1-8dea-4330-8bb7-c34c6edb05ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47657780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.47657780
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2518816735
Short name T795
Test name
Test status
Simulation time 26489292 ps
CPU time 0.89 seconds
Started Apr 15 02:28:38 PM PDT 24
Finished Apr 15 02:28:41 PM PDT 24
Peak memory 206292 kb
Host smart-596df1cb-3d7d-468e-9104-9ed50cbad481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518816735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2518816735
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2560448340
Short name T295
Test name
Test status
Simulation time 57580776 ps
CPU time 3.7 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 215860 kb
Host smart-b7cd6c57-905c-4d76-9193-196dc4581b3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2560448340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2560448340
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3318533093
Short name T242
Test name
Test status
Simulation time 766775051 ps
CPU time 10.76 seconds
Started Apr 15 02:28:37 PM PDT 24
Finished Apr 15 02:28:48 PM PDT 24
Peak memory 214832 kb
Host smart-b74579de-dc27-4ad1-8750-e3e94bcfec5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318533093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3318533093
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.552816909
Short name T552
Test name
Test status
Simulation time 202546977 ps
CPU time 2.83 seconds
Started Apr 15 02:28:38 PM PDT 24
Finished Apr 15 02:28:43 PM PDT 24
Peak memory 208552 kb
Host smart-1034b80f-7d95-4d1f-a24a-fc0145f2bab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552816909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.552816909
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3004765317
Short name T317
Test name
Test status
Simulation time 48616681 ps
CPU time 3.14 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 214572 kb
Host smart-689291fb-7578-435e-aa3d-23a227bef89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004765317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3004765317
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.627269955
Short name T383
Test name
Test status
Simulation time 221382083 ps
CPU time 4.16 seconds
Started Apr 15 02:28:39 PM PDT 24
Finished Apr 15 02:28:45 PM PDT 24
Peak memory 214528 kb
Host smart-e751dbe8-8245-47e0-b023-78c01601ac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627269955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.627269955
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3249067940
Short name T701
Test name
Test status
Simulation time 134003855 ps
CPU time 3.1 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:45 PM PDT 24
Peak memory 220776 kb
Host smart-202bbf41-3096-4cb8-886c-8e6afdbbefc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249067940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3249067940
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1393624081
Short name T874
Test name
Test status
Simulation time 904242344 ps
CPU time 4.24 seconds
Started Apr 15 02:28:36 PM PDT 24
Finished Apr 15 02:28:41 PM PDT 24
Peak memory 208940 kb
Host smart-0aa95b57-302a-43e7-8a97-8570e9d525e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393624081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1393624081
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.384253714
Short name T808
Test name
Test status
Simulation time 52222292 ps
CPU time 2.46 seconds
Started Apr 15 02:28:38 PM PDT 24
Finished Apr 15 02:28:41 PM PDT 24
Peak memory 208164 kb
Host smart-99b46dc4-8844-4d41-aaf8-693779fcedde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384253714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.384253714
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.483164032
Short name T770
Test name
Test status
Simulation time 38996532 ps
CPU time 1.83 seconds
Started Apr 15 02:28:37 PM PDT 24
Finished Apr 15 02:28:40 PM PDT 24
Peak memory 207136 kb
Host smart-eeb73d93-48fd-4755-9775-8ab1726abe75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483164032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.483164032
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.4189088936
Short name T576
Test name
Test status
Simulation time 74247389 ps
CPU time 2.57 seconds
Started Apr 15 02:28:37 PM PDT 24
Finished Apr 15 02:28:41 PM PDT 24
Peak memory 207152 kb
Host smart-973407c8-ab3a-4336-a0c1-deed6671a4ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189088936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4189088936
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.656648629
Short name T708
Test name
Test status
Simulation time 98188555 ps
CPU time 2.99 seconds
Started Apr 15 02:28:38 PM PDT 24
Finished Apr 15 02:28:43 PM PDT 24
Peak memory 207872 kb
Host smart-d4db17c1-fc33-41a8-ac47-3d536ea57694
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656648629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.656648629
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2648204948
Short name T532
Test name
Test status
Simulation time 65257586 ps
CPU time 2.46 seconds
Started Apr 15 02:28:37 PM PDT 24
Finished Apr 15 02:28:41 PM PDT 24
Peak memory 215960 kb
Host smart-cf882916-e57b-4be3-bf4c-33c7824463ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648204948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2648204948
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.117952060
Short name T603
Test name
Test status
Simulation time 1597411176 ps
CPU time 13.33 seconds
Started Apr 15 02:28:33 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 208608 kb
Host smart-b498a99f-a9ae-4fb5-9519-e0c66a5b9136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117952060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.117952060
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1609744085
Short name T678
Test name
Test status
Simulation time 8814141707 ps
CPU time 51.91 seconds
Started Apr 15 02:28:38 PM PDT 24
Finished Apr 15 02:29:31 PM PDT 24
Peak memory 220372 kb
Host smart-5daae20f-cfc5-4f1c-a5e1-0dd1846b6764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609744085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1609744085
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3703584021
Short name T562
Test name
Test status
Simulation time 872745653 ps
CPU time 8.51 seconds
Started Apr 15 02:28:38 PM PDT 24
Finished Apr 15 02:28:48 PM PDT 24
Peak memory 210028 kb
Host smart-12aca14d-5ed0-4383-94b4-c69cf11c72e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703584021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3703584021
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1057771962
Short name T204
Test name
Test status
Simulation time 103947755 ps
CPU time 2.64 seconds
Started Apr 15 02:28:40 PM PDT 24
Finished Apr 15 02:28:44 PM PDT 24
Peak memory 210268 kb
Host smart-ecbbbbcb-3934-4391-9414-262dd5d614a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057771962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1057771962
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2671390969
Short name T542
Test name
Test status
Simulation time 27197667 ps
CPU time 1.17 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:43 PM PDT 24
Peak memory 206472 kb
Host smart-9347f5e2-e4ea-4db9-a987-416ea84915c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671390969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2671390969
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.626347849
Short name T79
Test name
Test status
Simulation time 177205739 ps
CPU time 2.5 seconds
Started Apr 15 02:28:46 PM PDT 24
Finished Apr 15 02:28:49 PM PDT 24
Peak memory 218676 kb
Host smart-bf42efdc-6f6c-4a77-92fa-1e0e9e5d0fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626347849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.626347849
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.551865309
Short name T101
Test name
Test status
Simulation time 313316157 ps
CPU time 6.12 seconds
Started Apr 15 02:28:43 PM PDT 24
Finished Apr 15 02:28:50 PM PDT 24
Peak memory 209428 kb
Host smart-5d3fbb19-19aa-4816-87d8-0d165d1f7bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551865309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.551865309
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1689219274
Short name T548
Test name
Test status
Simulation time 112690821 ps
CPU time 3.58 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 209948 kb
Host smart-4bed94f1-cb93-4555-85de-2a833778387e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689219274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1689219274
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1482970375
Short name T475
Test name
Test status
Simulation time 62120691 ps
CPU time 3.47 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:46 PM PDT 24
Peak memory 208424 kb
Host smart-a42668ff-e82c-4499-83ff-077ea872232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482970375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1482970375
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2275425814
Short name T368
Test name
Test status
Simulation time 329757827 ps
CPU time 3.9 seconds
Started Apr 15 02:28:36 PM PDT 24
Finished Apr 15 02:28:41 PM PDT 24
Peak memory 208720 kb
Host smart-712361b8-cf8f-4547-9392-35be72869da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275425814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2275425814
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2239826206
Short name T379
Test name
Test status
Simulation time 75618751 ps
CPU time 3.38 seconds
Started Apr 15 02:28:36 PM PDT 24
Finished Apr 15 02:28:40 PM PDT 24
Peak memory 207064 kb
Host smart-d299ac46-d83e-4c46-a5ad-a5ddddf78975
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239826206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2239826206
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3957237290
Short name T211
Test name
Test status
Simulation time 38128358 ps
CPU time 1.76 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:28:45 PM PDT 24
Peak memory 207072 kb
Host smart-bee1d928-479b-4ffb-b2d9-519955aee2d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957237290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3957237290
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3322775059
Short name T621
Test name
Test status
Simulation time 68881083 ps
CPU time 2.45 seconds
Started Apr 15 02:28:38 PM PDT 24
Finished Apr 15 02:28:42 PM PDT 24
Peak memory 207164 kb
Host smart-02306754-6b0b-4fea-af22-6b962321a8b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322775059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3322775059
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2778138319
Short name T86
Test name
Test status
Simulation time 36228495 ps
CPU time 2.38 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:28:46 PM PDT 24
Peak memory 214576 kb
Host smart-efd3689b-597f-43b8-b140-e53454fbc3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778138319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2778138319
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.621820823
Short name T593
Test name
Test status
Simulation time 155239918 ps
CPU time 2.55 seconds
Started Apr 15 02:28:36 PM PDT 24
Finished Apr 15 02:28:40 PM PDT 24
Peak memory 206980 kb
Host smart-20e7710d-5784-476c-9354-5d86f5ba2aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621820823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.621820823
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1092976248
Short name T65
Test name
Test status
Simulation time 734843478 ps
CPU time 27.66 seconds
Started Apr 15 02:28:44 PM PDT 24
Finished Apr 15 02:29:13 PM PDT 24
Peak memory 222852 kb
Host smart-36c8fb02-81f3-4c17-91a8-eb2ffc8c6e7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092976248 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1092976248
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3741563155
Short name T667
Test name
Test status
Simulation time 50677076 ps
CPU time 3.13 seconds
Started Apr 15 02:28:45 PM PDT 24
Finished Apr 15 02:28:49 PM PDT 24
Peak memory 210112 kb
Host smart-5d43a436-30b8-474d-a4cc-98f15c3e55f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741563155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3741563155
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3567316996
Short name T872
Test name
Test status
Simulation time 35854595 ps
CPU time 2.3 seconds
Started Apr 15 02:28:44 PM PDT 24
Finished Apr 15 02:28:48 PM PDT 24
Peak memory 209884 kb
Host smart-7170bdac-22e1-4423-b5ee-9921071dca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567316996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3567316996
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.162710914
Short name T736
Test name
Test status
Simulation time 33325973 ps
CPU time 0.85 seconds
Started Apr 15 02:28:45 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 206260 kb
Host smart-9e3b997d-29f3-4f72-9baf-f55990c806ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162710914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.162710914
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1687796042
Short name T428
Test name
Test status
Simulation time 145477934 ps
CPU time 2.87 seconds
Started Apr 15 02:28:40 PM PDT 24
Finished Apr 15 02:28:45 PM PDT 24
Peak memory 215748 kb
Host smart-e20e44a5-8c27-4687-9822-36ab01011437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687796042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1687796042
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1623950950
Short name T565
Test name
Test status
Simulation time 338955124 ps
CPU time 7.21 seconds
Started Apr 15 02:28:43 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 222188 kb
Host smart-5e97301f-fd5d-41fc-a5b4-fdea42052fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623950950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1623950950
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.892558482
Short name T638
Test name
Test status
Simulation time 23685725 ps
CPU time 1.76 seconds
Started Apr 15 02:28:45 PM PDT 24
Finished Apr 15 02:28:48 PM PDT 24
Peak memory 208080 kb
Host smart-f58dc6c6-8172-4e91-ba33-fdc5496cb828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892558482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.892558482
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2260162159
Short name T650
Test name
Test status
Simulation time 86261896 ps
CPU time 2.88 seconds
Started Apr 15 02:28:45 PM PDT 24
Finished Apr 15 02:28:48 PM PDT 24
Peak memory 216264 kb
Host smart-752625eb-a2c1-4bdb-8f08-c632dd876346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260162159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2260162159
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.407279336
Short name T533
Test name
Test status
Simulation time 680222771 ps
CPU time 5.4 seconds
Started Apr 15 02:28:44 PM PDT 24
Finished Apr 15 02:28:50 PM PDT 24
Peak memory 218452 kb
Host smart-3a88641a-88c7-431e-9b5c-3ca93596c123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407279336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.407279336
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1712378250
Short name T750
Test name
Test status
Simulation time 349290869 ps
CPU time 2.45 seconds
Started Apr 15 02:28:44 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 206980 kb
Host smart-df1e02c4-63e8-4d99-b8e3-05548279c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712378250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1712378250
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2969206147
Short name T905
Test name
Test status
Simulation time 213328004 ps
CPU time 3.44 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:46 PM PDT 24
Peak memory 208816 kb
Host smart-cbe0f9aa-9478-4496-9fb6-9ea9cc5bd767
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969206147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2969206147
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1261878852
Short name T441
Test name
Test status
Simulation time 339067246 ps
CPU time 2.65 seconds
Started Apr 15 02:28:43 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 208880 kb
Host smart-9f955de6-1c1f-44e7-a98f-932b2e6e8121
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261878852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1261878852
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1428256975
Short name T464
Test name
Test status
Simulation time 110702983 ps
CPU time 4.05 seconds
Started Apr 15 02:29:07 PM PDT 24
Finished Apr 15 02:29:12 PM PDT 24
Peak memory 207208 kb
Host smart-067a70c6-068f-4512-9c63-b294a1acc5fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428256975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1428256975
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2571870423
Short name T661
Test name
Test status
Simulation time 497789472 ps
CPU time 2.98 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:46 PM PDT 24
Peak memory 218572 kb
Host smart-dfd5be06-60bf-49e0-a080-80be17484ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571870423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2571870423
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3615161373
Short name T662
Test name
Test status
Simulation time 523043053 ps
CPU time 2.98 seconds
Started Apr 15 02:28:43 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 207352 kb
Host smart-b51fd255-0088-47eb-92de-f340df45c296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615161373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3615161373
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.4134839241
Short name T66
Test name
Test status
Simulation time 9908299073 ps
CPU time 233.57 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:32:37 PM PDT 24
Peak memory 218328 kb
Host smart-7779846a-95b9-4daa-89c4-b2fb442eb20f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134839241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4134839241
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3021242016
Short name T205
Test name
Test status
Simulation time 464247749 ps
CPU time 9.27 seconds
Started Apr 15 02:28:42 PM PDT 24
Finished Apr 15 02:28:53 PM PDT 24
Peak memory 222980 kb
Host smart-c94a8a2d-cfba-46ed-8183-007db24112d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021242016 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3021242016
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.4251585249
Short name T513
Test name
Test status
Simulation time 470809864 ps
CPU time 12.53 seconds
Started Apr 15 02:28:41 PM PDT 24
Finished Apr 15 02:28:55 PM PDT 24
Peak memory 208068 kb
Host smart-0cb78480-fca1-45e9-95ee-e36757440d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251585249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.4251585249
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.525866093
Short name T642
Test name
Test status
Simulation time 178908834 ps
CPU time 2.82 seconds
Started Apr 15 02:28:43 PM PDT 24
Finished Apr 15 02:28:47 PM PDT 24
Peak memory 210576 kb
Host smart-5a938dc2-0220-47b8-92cd-c92b0066e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525866093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.525866093
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1346200107
Short name T664
Test name
Test status
Simulation time 18684447 ps
CPU time 0.88 seconds
Started Apr 15 02:28:52 PM PDT 24
Finished Apr 15 02:28:55 PM PDT 24
Peak memory 206300 kb
Host smart-fd415a60-0f68-43eb-bb0e-9d9eac8a788a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346200107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1346200107
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1627490657
Short name T380
Test name
Test status
Simulation time 937795469 ps
CPU time 3.9 seconds
Started Apr 15 02:28:47 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 214620 kb
Host smart-06e19942-bc42-46e9-bf62-c5a12261b9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627490657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1627490657
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1368809618
Short name T298
Test name
Test status
Simulation time 261011522 ps
CPU time 4.16 seconds
Started Apr 15 02:28:47 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 214588 kb
Host smart-1c551e5a-1084-4c36-9488-17bf5a787d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368809618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1368809618
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1134281470
Short name T590
Test name
Test status
Simulation time 221932551 ps
CPU time 5.51 seconds
Started Apr 15 02:28:48 PM PDT 24
Finished Apr 15 02:28:54 PM PDT 24
Peak memory 211800 kb
Host smart-b29d92cf-fe13-42b2-b469-34475fd11231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134281470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1134281470
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2725068747
Short name T756
Test name
Test status
Simulation time 85170920 ps
CPU time 2.79 seconds
Started Apr 15 02:28:48 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 206416 kb
Host smart-2ce0214e-e34f-4ee4-ad63-61bbbf9aba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725068747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2725068747
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1620937120
Short name T310
Test name
Test status
Simulation time 155517806 ps
CPU time 5.21 seconds
Started Apr 15 02:28:47 PM PDT 24
Finished Apr 15 02:28:54 PM PDT 24
Peak memory 209408 kb
Host smart-11446716-0a5b-4735-965f-c32f42092f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620937120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1620937120
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3313184647
Short name T351
Test name
Test status
Simulation time 174794190 ps
CPU time 4.05 seconds
Started Apr 15 02:28:47 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 208908 kb
Host smart-52d5839d-2f1a-4fac-be2c-c3318f7b5143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313184647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3313184647
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1934457764
Short name T353
Test name
Test status
Simulation time 332908594 ps
CPU time 3.48 seconds
Started Apr 15 02:28:46 PM PDT 24
Finished Apr 15 02:28:50 PM PDT 24
Peak memory 208964 kb
Host smart-7b949b89-d349-420d-aa56-116c58711b58
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934457764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1934457764
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.120990237
Short name T550
Test name
Test status
Simulation time 202549917 ps
CPU time 7.45 seconds
Started Apr 15 02:28:46 PM PDT 24
Finished Apr 15 02:28:54 PM PDT 24
Peak memory 208328 kb
Host smart-fdca3d61-5e66-43c4-92fd-6ff380372064
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120990237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.120990237
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3322910625
Short name T119
Test name
Test status
Simulation time 56368661 ps
CPU time 1.87 seconds
Started Apr 15 02:28:50 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 207068 kb
Host smart-d3cc3681-82c7-4aae-a752-3baa5e48b20f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322910625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3322910625
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2145272806
Short name T575
Test name
Test status
Simulation time 232984490 ps
CPU time 2.87 seconds
Started Apr 15 02:28:49 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 210580 kb
Host smart-aec46656-3fad-481a-a2e7-8d5971efb5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145272806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2145272806
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3251658254
Short name T831
Test name
Test status
Simulation time 117117055 ps
CPU time 3.17 seconds
Started Apr 15 02:28:47 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 208580 kb
Host smart-5b8b1a5d-ffd1-4ff2-aa12-17411516db86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251658254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3251658254
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2387353848
Short name T331
Test name
Test status
Simulation time 2028176754 ps
CPU time 53.34 seconds
Started Apr 15 02:28:46 PM PDT 24
Finished Apr 15 02:29:40 PM PDT 24
Peak memory 217660 kb
Host smart-da5402b2-ab46-4c27-8f9a-68cdfe7b4d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387353848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2387353848
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2730787053
Short name T488
Test name
Test status
Simulation time 63232628 ps
CPU time 4.25 seconds
Started Apr 15 02:28:46 PM PDT 24
Finished Apr 15 02:28:51 PM PDT 24
Peak memory 209468 kb
Host smart-6fd942d3-7721-4908-91e4-20ba67b7ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730787053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2730787053
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2696767675
Short name T507
Test name
Test status
Simulation time 121409046 ps
CPU time 2.88 seconds
Started Apr 15 02:28:48 PM PDT 24
Finished Apr 15 02:28:52 PM PDT 24
Peak memory 210092 kb
Host smart-a7f49fa6-3a8b-4adb-a93e-343e2bc5ed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696767675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2696767675
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3122728715
Short name T819
Test name
Test status
Simulation time 62915828 ps
CPU time 1.01 seconds
Started Apr 15 02:28:51 PM PDT 24
Finished Apr 15 02:28:53 PM PDT 24
Peak memory 206428 kb
Host smart-e3ea8210-c4b3-4514-80bd-2bd18358ce7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122728715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3122728715
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.4057329394
Short name T357
Test name
Test status
Simulation time 247132603 ps
CPU time 4.82 seconds
Started Apr 15 02:28:52 PM PDT 24
Finished Apr 15 02:28:58 PM PDT 24
Peak memory 215872 kb
Host smart-84b28488-faad-4342-9137-4c32f0ba298c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4057329394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.4057329394
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2595706154
Short name T881
Test name
Test status
Simulation time 5808656466 ps
CPU time 41.15 seconds
Started Apr 15 02:28:52 PM PDT 24
Finished Apr 15 02:29:35 PM PDT 24
Peak memory 214656 kb
Host smart-fcecda86-557a-4e7f-b626-d0379de4852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595706154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2595706154
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3944492479
Short name T649
Test name
Test status
Simulation time 226048409 ps
CPU time 3.09 seconds
Started Apr 15 02:28:53 PM PDT 24
Finished Apr 15 02:28:57 PM PDT 24
Peak memory 209372 kb
Host smart-8474d2aa-4852-42e4-84c3-5961cfc9f316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944492479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3944492479
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.151118769
Short name T389
Test name
Test status
Simulation time 197675950 ps
CPU time 3.63 seconds
Started Apr 15 02:28:53 PM PDT 24
Finished Apr 15 02:28:58 PM PDT 24
Peak memory 214556 kb
Host smart-6217cf53-17d3-4dbf-bf52-83d86554a1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151118769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.151118769
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.659543574
Short name T54
Test name
Test status
Simulation time 320415186 ps
CPU time 4.26 seconds
Started Apr 15 02:28:50 PM PDT 24
Finished Apr 15 02:28:55 PM PDT 24
Peak memory 210316 kb
Host smart-e0899874-94fd-4ea9-a1fc-1e21c6e80dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659543574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.659543574
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3572976753
Short name T614
Test name
Test status
Simulation time 139454056 ps
CPU time 4.39 seconds
Started Apr 15 02:28:53 PM PDT 24
Finished Apr 15 02:28:59 PM PDT 24
Peak memory 207856 kb
Host smart-cc204d54-9936-4a99-b074-bd0cfe9a2984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572976753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3572976753
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.53118566
Short name T262
Test name
Test status
Simulation time 62838911 ps
CPU time 3.07 seconds
Started Apr 15 02:28:52 PM PDT 24
Finished Apr 15 02:28:57 PM PDT 24
Peak memory 207412 kb
Host smart-78a48651-e509-461e-a9b3-923c69fc9f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53118566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.53118566
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4052650610
Short name T815
Test name
Test status
Simulation time 86784221 ps
CPU time 2.78 seconds
Started Apr 15 02:28:55 PM PDT 24
Finished Apr 15 02:28:59 PM PDT 24
Peak memory 207076 kb
Host smart-2a190aaa-97bf-42f1-8ffe-01548757d8ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052650610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4052650610
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.157131930
Short name T834
Test name
Test status
Simulation time 1381463025 ps
CPU time 22.57 seconds
Started Apr 15 02:28:51 PM PDT 24
Finished Apr 15 02:29:14 PM PDT 24
Peak memory 208752 kb
Host smart-42fb9b1b-3f93-441a-9398-336020472283
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157131930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.157131930
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.395013677
Short name T216
Test name
Test status
Simulation time 81819210 ps
CPU time 3.67 seconds
Started Apr 15 02:28:50 PM PDT 24
Finished Apr 15 02:28:54 PM PDT 24
Peak memory 208980 kb
Host smart-78c0f3e9-580f-4796-a90c-5bd99fbeabbb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395013677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.395013677
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3774061059
Short name T497
Test name
Test status
Simulation time 337156881 ps
CPU time 3.51 seconds
Started Apr 15 02:28:51 PM PDT 24
Finished Apr 15 02:28:56 PM PDT 24
Peak memory 214712 kb
Host smart-f94208e7-b313-492e-9aca-946c22fa70ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774061059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3774061059
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.922852724
Short name T444
Test name
Test status
Simulation time 465175845 ps
CPU time 6.47 seconds
Started Apr 15 02:28:50 PM PDT 24
Finished Apr 15 02:28:57 PM PDT 24
Peak memory 208056 kb
Host smart-7445ea30-eadf-420d-ad61-2b17e771c6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922852724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.922852724
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.203972324
Short name T246
Test name
Test status
Simulation time 720507559 ps
CPU time 10.33 seconds
Started Apr 15 02:28:52 PM PDT 24
Finished Apr 15 02:29:04 PM PDT 24
Peak memory 215396 kb
Host smart-36f7220b-c999-41f4-aac3-605a7d4b50a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203972324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.203972324
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.4262946641
Short name T177
Test name
Test status
Simulation time 436821832 ps
CPU time 16.21 seconds
Started Apr 15 02:28:53 PM PDT 24
Finished Apr 15 02:29:10 PM PDT 24
Peak memory 222952 kb
Host smart-4022c14b-13b7-48a4-83ff-e1520f50130c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262946641 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.4262946641
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.34077319
Short name T460
Test name
Test status
Simulation time 69471272 ps
CPU time 3.75 seconds
Started Apr 15 02:28:52 PM PDT 24
Finished Apr 15 02:28:58 PM PDT 24
Peak memory 207364 kb
Host smart-5ab94676-9ed1-4e87-a59d-99e24e0439b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34077319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.34077319
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1527858632
Short name T893
Test name
Test status
Simulation time 158050510 ps
CPU time 2.12 seconds
Started Apr 15 02:28:52 PM PDT 24
Finished Apr 15 02:28:56 PM PDT 24
Peak memory 209972 kb
Host smart-07efb4ca-9e64-4a92-bc53-bbfe3bcc50bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527858632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1527858632
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2300925066
Short name T635
Test name
Test status
Simulation time 18760835 ps
CPU time 0.85 seconds
Started Apr 15 02:28:57 PM PDT 24
Finished Apr 15 02:28:59 PM PDT 24
Peak memory 206308 kb
Host smart-33cda5ae-7899-4204-bb66-b06d96fe22f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300925066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2300925066
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2914461963
Short name T37
Test name
Test status
Simulation time 1830621541 ps
CPU time 7.39 seconds
Started Apr 15 02:28:55 PM PDT 24
Finished Apr 15 02:29:04 PM PDT 24
Peak memory 209592 kb
Host smart-17dc01af-a99b-4cde-a073-e33ffb166e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914461963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2914461963
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.566736607
Short name T481
Test name
Test status
Simulation time 103372726 ps
CPU time 2.05 seconds
Started Apr 15 02:28:57 PM PDT 24
Finished Apr 15 02:29:00 PM PDT 24
Peak memory 207024 kb
Host smart-138cc150-be02-42ed-8b45-b5b5c36c8d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566736607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.566736607
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3995994099
Short name T297
Test name
Test status
Simulation time 35830928100 ps
CPU time 60.04 seconds
Started Apr 15 02:28:58 PM PDT 24
Finished Apr 15 02:29:59 PM PDT 24
Peak memory 219224 kb
Host smart-196abb8a-f1da-43d1-bea2-d4f26b2c550e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995994099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3995994099
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2186689680
Short name T115
Test name
Test status
Simulation time 678418825 ps
CPU time 26.42 seconds
Started Apr 15 02:28:58 PM PDT 24
Finished Apr 15 02:29:25 PM PDT 24
Peak memory 222508 kb
Host smart-191e4471-cfae-4a4a-89f5-a71758062af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186689680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2186689680
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4045909935
Short name T244
Test name
Test status
Simulation time 420312814 ps
CPU time 5.28 seconds
Started Apr 15 02:28:55 PM PDT 24
Finished Apr 15 02:29:01 PM PDT 24
Peak memory 216084 kb
Host smart-eff5ee8b-d383-4241-bcb2-d2e0bd64e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045909935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4045909935
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3404796604
Short name T861
Test name
Test status
Simulation time 522951754 ps
CPU time 8.17 seconds
Started Apr 15 02:28:57 PM PDT 24
Finished Apr 15 02:29:06 PM PDT 24
Peak memory 210096 kb
Host smart-b3e42847-e20f-4812-98b9-f9a2a1083d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404796604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3404796604
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1230290415
Short name T660
Test name
Test status
Simulation time 2130968582 ps
CPU time 7.27 seconds
Started Apr 15 02:28:51 PM PDT 24
Finished Apr 15 02:29:00 PM PDT 24
Peak memory 208272 kb
Host smart-6494aa17-b2bd-4349-be98-19ba82a7cbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230290415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1230290415
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1657314888
Short name T260
Test name
Test status
Simulation time 129356065 ps
CPU time 3.32 seconds
Started Apr 15 02:28:51 PM PDT 24
Finished Apr 15 02:28:55 PM PDT 24
Peak memory 208880 kb
Host smart-6ca3f572-411f-4d20-ae78-1deb0a01d47a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657314888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1657314888
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3663893807
Short name T826
Test name
Test status
Simulation time 49451194 ps
CPU time 2.83 seconds
Started Apr 15 02:28:52 PM PDT 24
Finished Apr 15 02:28:57 PM PDT 24
Peak memory 208836 kb
Host smart-13fa9cdb-aa94-4b30-8f51-cd75490a6945
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663893807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3663893807
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1814259591
Short name T364
Test name
Test status
Simulation time 28445837 ps
CPU time 2.27 seconds
Started Apr 15 02:28:56 PM PDT 24
Finished Apr 15 02:28:59 PM PDT 24
Peak memory 208912 kb
Host smart-485284ac-02e6-41fd-b17d-8f8641b0629b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814259591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1814259591
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.285872953
Short name T656
Test name
Test status
Simulation time 37367194 ps
CPU time 2.19 seconds
Started Apr 15 02:28:55 PM PDT 24
Finished Apr 15 02:28:59 PM PDT 24
Peak memory 214560 kb
Host smart-50b016df-8583-420b-b26e-4932578100c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285872953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.285872953
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1358743775
Short name T645
Test name
Test status
Simulation time 151400040 ps
CPU time 4.29 seconds
Started Apr 15 02:28:53 PM PDT 24
Finished Apr 15 02:28:58 PM PDT 24
Peak memory 208848 kb
Host smart-10833506-22e5-46f3-a4b5-8d2d3c774173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358743775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1358743775
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2727636888
Short name T301
Test name
Test status
Simulation time 33282967668 ps
CPU time 120.17 seconds
Started Apr 15 02:28:58 PM PDT 24
Finished Apr 15 02:30:59 PM PDT 24
Peak memory 216648 kb
Host smart-355184c6-6df7-4836-aa01-fa72ade07c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727636888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2727636888
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.680645408
Short name T862
Test name
Test status
Simulation time 114970043 ps
CPU time 4.92 seconds
Started Apr 15 02:28:54 PM PDT 24
Finished Apr 15 02:29:01 PM PDT 24
Peak memory 209128 kb
Host smart-75ca465b-948e-429f-bb41-e30912a7e6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680645408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.680645408
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3239776416
Short name T714
Test name
Test status
Simulation time 35081442 ps
CPU time 0.77 seconds
Started Apr 15 02:28:58 PM PDT 24
Finished Apr 15 02:29:00 PM PDT 24
Peak memory 206312 kb
Host smart-b8efc60a-6543-4a2a-9358-1bd981a5b04b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239776416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3239776416
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3942795308
Short name T411
Test name
Test status
Simulation time 213533364 ps
CPU time 3.71 seconds
Started Apr 15 02:29:02 PM PDT 24
Finished Apr 15 02:29:07 PM PDT 24
Peak memory 215664 kb
Host smart-866e279a-5a41-42c4-8cf8-07db356410dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942795308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3942795308
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.895144820
Short name T82
Test name
Test status
Simulation time 405614295 ps
CPU time 2.95 seconds
Started Apr 15 02:28:59 PM PDT 24
Finished Apr 15 02:29:03 PM PDT 24
Peak memory 207720 kb
Host smart-200678f2-e08a-4ac8-bff3-89f426b79d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895144820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.895144820
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1092049997
Short name T391
Test name
Test status
Simulation time 6035851170 ps
CPU time 72.54 seconds
Started Apr 15 02:29:00 PM PDT 24
Finished Apr 15 02:30:14 PM PDT 24
Peak memory 222836 kb
Host smart-8d58a45b-3831-455c-83c6-e9742f239404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092049997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1092049997
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.180688902
Short name T332
Test name
Test status
Simulation time 2373616030 ps
CPU time 12.23 seconds
Started Apr 15 02:29:02 PM PDT 24
Finished Apr 15 02:29:15 PM PDT 24
Peak memory 222856 kb
Host smart-ac9904b1-2520-4a9f-85c0-8f691efc6dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180688902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.180688902
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2658805738
Short name T781
Test name
Test status
Simulation time 63820446 ps
CPU time 2.76 seconds
Started Apr 15 02:29:01 PM PDT 24
Finished Apr 15 02:29:05 PM PDT 24
Peak memory 214700 kb
Host smart-093db413-bb53-45c5-97df-c3868f1e7c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658805738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2658805738
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1720542498
Short name T341
Test name
Test status
Simulation time 114477578 ps
CPU time 5.33 seconds
Started Apr 15 02:29:01 PM PDT 24
Finished Apr 15 02:29:08 PM PDT 24
Peak memory 209496 kb
Host smart-a63eb46e-9b39-4935-bbea-490944edd178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720542498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1720542498
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.941742511
Short name T896
Test name
Test status
Simulation time 25728694 ps
CPU time 1.77 seconds
Started Apr 15 02:28:55 PM PDT 24
Finished Apr 15 02:28:58 PM PDT 24
Peak memory 207064 kb
Host smart-fd914645-1faf-4a6f-a27e-63d551048e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941742511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.941742511
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2383229205
Short name T640
Test name
Test status
Simulation time 245054520 ps
CPU time 7.31 seconds
Started Apr 15 02:28:53 PM PDT 24
Finished Apr 15 02:29:02 PM PDT 24
Peak memory 208880 kb
Host smart-85aabc35-e4b9-4f2c-8381-fd4e5ebc17d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383229205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2383229205
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1101223793
Short name T612
Test name
Test status
Simulation time 275092056 ps
CPU time 7.78 seconds
Started Apr 15 02:28:55 PM PDT 24
Finished Apr 15 02:29:04 PM PDT 24
Peak memory 208348 kb
Host smart-0b12e0e9-2395-45fb-86e2-eafc4235af67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101223793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1101223793
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2662818417
Short name T886
Test name
Test status
Simulation time 845306440 ps
CPU time 9.31 seconds
Started Apr 15 02:29:01 PM PDT 24
Finished Apr 15 02:29:11 PM PDT 24
Peak memory 208212 kb
Host smart-c388ba94-d5a6-4861-afc5-d97d3bd21b4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662818417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2662818417
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.4095988544
Short name T257
Test name
Test status
Simulation time 103701199 ps
CPU time 2.62 seconds
Started Apr 15 02:29:00 PM PDT 24
Finished Apr 15 02:29:03 PM PDT 24
Peak memory 215776 kb
Host smart-385d58f7-e05c-4be3-b2b4-1d464ef152f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095988544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.4095988544
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3587827837
Short name T604
Test name
Test status
Simulation time 3669364147 ps
CPU time 37.09 seconds
Started Apr 15 02:28:57 PM PDT 24
Finished Apr 15 02:29:35 PM PDT 24
Peak memory 208936 kb
Host smart-c74c1b4a-dce3-49f7-985a-c66a40e25131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587827837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3587827837
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2306345301
Short name T80
Test name
Test status
Simulation time 726398231 ps
CPU time 27.16 seconds
Started Apr 15 02:29:00 PM PDT 24
Finished Apr 15 02:29:28 PM PDT 24
Peak memory 216012 kb
Host smart-2ae68361-de4b-41bf-bc91-94ad278fb706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306345301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2306345301
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3418801887
Short name T778
Test name
Test status
Simulation time 88896501 ps
CPU time 5.77 seconds
Started Apr 15 02:29:02 PM PDT 24
Finished Apr 15 02:29:09 PM PDT 24
Peak memory 220348 kb
Host smart-188f9934-7b78-41a0-97c7-33035750fd4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418801887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3418801887
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3103157583
Short name T490
Test name
Test status
Simulation time 375209726 ps
CPU time 4.71 seconds
Started Apr 15 02:29:00 PM PDT 24
Finished Apr 15 02:29:06 PM PDT 24
Peak memory 209324 kb
Host smart-69a5dc78-154a-41b6-afab-da2eafd97c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103157583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3103157583
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.162624654
Short name T557
Test name
Test status
Simulation time 105430274 ps
CPU time 3.88 seconds
Started Apr 15 02:29:02 PM PDT 24
Finished Apr 15 02:29:07 PM PDT 24
Peak memory 211204 kb
Host smart-30fde3da-3e89-4232-b660-0f721bd0067d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162624654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.162624654
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1451820231
Short name T523
Test name
Test status
Simulation time 107741197 ps
CPU time 0.8 seconds
Started Apr 15 02:29:04 PM PDT 24
Finished Apr 15 02:29:06 PM PDT 24
Peak memory 206304 kb
Host smart-b28900a1-9d95-46fa-95ea-0a040c8aa7fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451820231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1451820231
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2493041538
Short name T703
Test name
Test status
Simulation time 195981181 ps
CPU time 1.21 seconds
Started Apr 15 02:29:04 PM PDT 24
Finished Apr 15 02:29:07 PM PDT 24
Peak memory 207416 kb
Host smart-9cad1d01-5b8d-4b78-a6e9-b03d5363d8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493041538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2493041538
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1903914680
Short name T270
Test name
Test status
Simulation time 169894379 ps
CPU time 4.28 seconds
Started Apr 15 02:29:04 PM PDT 24
Finished Apr 15 02:29:10 PM PDT 24
Peak memory 214568 kb
Host smart-d3d2ea35-4bf9-45f9-81fc-de793f1453a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903914680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1903914680
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2533995341
Short name T629
Test name
Test status
Simulation time 286637194 ps
CPU time 4.38 seconds
Started Apr 15 02:29:04 PM PDT 24
Finished Apr 15 02:29:09 PM PDT 24
Peak memory 214544 kb
Host smart-809f4f47-9ef3-4790-87de-e39f7c05e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533995341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2533995341
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.361661753
Short name T125
Test name
Test status
Simulation time 54786578 ps
CPU time 3.71 seconds
Started Apr 15 02:29:04 PM PDT 24
Finished Apr 15 02:29:08 PM PDT 24
Peak memory 208336 kb
Host smart-2b5da739-1c84-49da-b8d9-c34ddd618f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361661753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.361661753
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3284823548
Short name T787
Test name
Test status
Simulation time 224063016 ps
CPU time 3.11 seconds
Started Apr 15 02:29:01 PM PDT 24
Finished Apr 15 02:29:05 PM PDT 24
Peak memory 208236 kb
Host smart-d5378647-1250-45fc-94df-8208f96f552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284823548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3284823548
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.623280339
Short name T906
Test name
Test status
Simulation time 75458669 ps
CPU time 2.89 seconds
Started Apr 15 02:29:06 PM PDT 24
Finished Apr 15 02:29:11 PM PDT 24
Peak memory 207140 kb
Host smart-3f4f0f63-ee0a-42da-87d0-9da8a3f1b900
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623280339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.623280339
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2380543827
Short name T535
Test name
Test status
Simulation time 448369772 ps
CPU time 5.46 seconds
Started Apr 15 02:29:02 PM PDT 24
Finished Apr 15 02:29:09 PM PDT 24
Peak memory 208820 kb
Host smart-f34538c7-8245-4fe8-9438-ab9854249226
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380543827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2380543827
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2796052870
Short name T764
Test name
Test status
Simulation time 182969029 ps
CPU time 2.92 seconds
Started Apr 15 02:29:07 PM PDT 24
Finished Apr 15 02:29:11 PM PDT 24
Peak memory 207180 kb
Host smart-5886e7a0-5074-4f52-bf14-eeed245874de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796052870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2796052870
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1684746413
Short name T677
Test name
Test status
Simulation time 86084324 ps
CPU time 3.17 seconds
Started Apr 15 02:29:06 PM PDT 24
Finished Apr 15 02:29:11 PM PDT 24
Peak memory 214588 kb
Host smart-7762398e-8b5f-4562-a973-7b57146d1fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684746413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1684746413
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2270846629
Short name T615
Test name
Test status
Simulation time 50782868 ps
CPU time 2.1 seconds
Started Apr 15 02:29:00 PM PDT 24
Finished Apr 15 02:29:03 PM PDT 24
Peak memory 208616 kb
Host smart-b0da0f59-6d99-43bf-9ece-03b77e6805f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270846629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2270846629
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.493302661
Short name T721
Test name
Test status
Simulation time 2252534111 ps
CPU time 54.98 seconds
Started Apr 15 02:29:05 PM PDT 24
Finished Apr 15 02:30:01 PM PDT 24
Peak memory 215460 kb
Host smart-b4487ac3-c10b-4ce2-93f5-40c252010960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493302661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.493302661
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.920430959
Short name T876
Test name
Test status
Simulation time 630371517 ps
CPU time 26.38 seconds
Started Apr 15 02:29:03 PM PDT 24
Finished Apr 15 02:29:30 PM PDT 24
Peak memory 220648 kb
Host smart-2f5af1ec-3686-4f89-8ec6-8040674578ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920430959 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.920430959
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3720761177
Short name T400
Test name
Test status
Simulation time 398036220 ps
CPU time 4.66 seconds
Started Apr 15 02:29:04 PM PDT 24
Finished Apr 15 02:29:10 PM PDT 24
Peak memory 207920 kb
Host smart-959224e0-cda9-4606-9237-ec7a56dbab8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720761177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3720761177
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3834928740
Short name T238
Test name
Test status
Simulation time 238739023 ps
CPU time 1.86 seconds
Started Apr 15 02:29:06 PM PDT 24
Finished Apr 15 02:29:09 PM PDT 24
Peak memory 211020 kb
Host smart-026d197c-8c5f-492e-87fc-8d64ca7f2ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834928740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3834928740
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2114223987
Short name T480
Test name
Test status
Simulation time 25304544 ps
CPU time 0.88 seconds
Started Apr 15 02:29:08 PM PDT 24
Finished Apr 15 02:29:11 PM PDT 24
Peak memory 206300 kb
Host smart-2a2d2fc9-fb84-47af-93c2-45c6a87519c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114223987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2114223987
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1643893093
Short name T312
Test name
Test status
Simulation time 39026475 ps
CPU time 2.69 seconds
Started Apr 15 02:29:08 PM PDT 24
Finished Apr 15 02:29:13 PM PDT 24
Peak memory 214664 kb
Host smart-68d94d32-4ea3-4a1f-99da-ee16aee7d968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643893093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1643893093
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1634882412
Short name T827
Test name
Test status
Simulation time 444851047 ps
CPU time 5.53 seconds
Started Apr 15 02:29:09 PM PDT 24
Finished Apr 15 02:29:16 PM PDT 24
Peak memory 208920 kb
Host smart-dda3e25d-6bd3-4d4d-b803-186761d9ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634882412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1634882412
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1218144766
Short name T769
Test name
Test status
Simulation time 354340114 ps
CPU time 3.6 seconds
Started Apr 15 02:29:09 PM PDT 24
Finished Apr 15 02:29:14 PM PDT 24
Peak memory 214524 kb
Host smart-3ea2429b-b29d-4a47-b731-c04407dbfbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218144766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1218144766
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.931909096
Short name T559
Test name
Test status
Simulation time 499355499 ps
CPU time 7.18 seconds
Started Apr 15 02:29:09 PM PDT 24
Finished Apr 15 02:29:18 PM PDT 24
Peak memory 222512 kb
Host smart-948850a9-9b46-4c30-9a24-c77de9ebcc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931909096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.931909096
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3352632731
Short name T103
Test name
Test status
Simulation time 336698943 ps
CPU time 4.84 seconds
Started Apr 15 02:29:08 PM PDT 24
Finished Apr 15 02:29:15 PM PDT 24
Peak memory 214528 kb
Host smart-cecb47d5-01fb-40f9-a768-aff35409acaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352632731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3352632731
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.662072089
Short name T51
Test name
Test status
Simulation time 69663402 ps
CPU time 2.67 seconds
Started Apr 15 02:29:09 PM PDT 24
Finished Apr 15 02:29:14 PM PDT 24
Peak memory 208468 kb
Host smart-39371986-6f00-4e73-b310-c20687d80937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662072089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.662072089
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2696168240
Short name T371
Test name
Test status
Simulation time 221701454 ps
CPU time 6.87 seconds
Started Apr 15 02:29:06 PM PDT 24
Finished Apr 15 02:29:15 PM PDT 24
Peak memory 208224 kb
Host smart-716221fd-576e-4dcd-a689-91fcf0f4718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696168240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2696168240
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.528934471
Short name T264
Test name
Test status
Simulation time 1001258170 ps
CPU time 6.81 seconds
Started Apr 15 02:29:05 PM PDT 24
Finished Apr 15 02:29:14 PM PDT 24
Peak memory 208672 kb
Host smart-a9f8c30f-571e-4909-95d4-a9c924be3dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528934471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.528934471
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3104924125
Short name T697
Test name
Test status
Simulation time 137027157 ps
CPU time 2.45 seconds
Started Apr 15 02:29:04 PM PDT 24
Finished Apr 15 02:29:07 PM PDT 24
Peak memory 207156 kb
Host smart-6f56502e-322c-4100-b14d-98e6e7b543ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104924125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3104924125
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1388391180
Short name T516
Test name
Test status
Simulation time 134945760 ps
CPU time 1.78 seconds
Started Apr 15 02:29:05 PM PDT 24
Finished Apr 15 02:29:08 PM PDT 24
Peak memory 207136 kb
Host smart-cff54d97-8643-4706-99d2-8e5f4f05892a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388391180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1388391180
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3169152810
Short name T543
Test name
Test status
Simulation time 520833348 ps
CPU time 6.78 seconds
Started Apr 15 02:29:05 PM PDT 24
Finished Apr 15 02:29:13 PM PDT 24
Peak memory 208248 kb
Host smart-84c25906-953a-4893-9697-0a181785d1e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169152810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3169152810
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.808018732
Short name T360
Test name
Test status
Simulation time 71027250 ps
CPU time 3.27 seconds
Started Apr 15 02:29:10 PM PDT 24
Finished Apr 15 02:29:15 PM PDT 24
Peak memory 210372 kb
Host smart-6d49dafa-1cb0-4737-b357-b2b2bdd6655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808018732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.808018732
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1066707353
Short name T743
Test name
Test status
Simulation time 2932851806 ps
CPU time 20 seconds
Started Apr 15 02:29:05 PM PDT 24
Finished Apr 15 02:29:27 PM PDT 24
Peak memory 208304 kb
Host smart-3ac4b027-e96c-4e55-b9ca-ecfe0b74607c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066707353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1066707353
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4221885731
Short name T684
Test name
Test status
Simulation time 43646563 ps
CPU time 0.81 seconds
Started Apr 15 02:29:07 PM PDT 24
Finished Apr 15 02:29:10 PM PDT 24
Peak memory 206276 kb
Host smart-a0b22dca-9b21-4ce9-ab26-b5367e31f360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221885731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4221885731
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3799444315
Short name T366
Test name
Test status
Simulation time 1153651222 ps
CPU time 8.18 seconds
Started Apr 15 02:29:10 PM PDT 24
Finished Apr 15 02:29:20 PM PDT 24
Peak memory 210064 kb
Host smart-71ede679-30a4-4b93-8435-a145a429256b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799444315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3799444315
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4276626336
Short name T791
Test name
Test status
Simulation time 130940090 ps
CPU time 2.15 seconds
Started Apr 15 02:29:07 PM PDT 24
Finished Apr 15 02:29:12 PM PDT 24
Peak memory 210352 kb
Host smart-4ec0ba06-0c63-40bf-b58c-41b6b7f1f6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276626336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4276626336
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.750747493
Short name T512
Test name
Test status
Simulation time 32829374 ps
CPU time 0.95 seconds
Started Apr 15 02:26:29 PM PDT 24
Finished Apr 15 02:26:31 PM PDT 24
Peak memory 206356 kb
Host smart-0f51790c-b5dd-4cfc-86f0-3863505a160d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750747493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.750747493
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1508378232
Short name T155
Test name
Test status
Simulation time 880556479 ps
CPU time 46.15 seconds
Started Apr 15 02:26:25 PM PDT 24
Finished Apr 15 02:27:12 PM PDT 24
Peak memory 214580 kb
Host smart-2b6e0826-9f3b-47e9-8306-07b8b20cea1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508378232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1508378232
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1959984256
Short name T648
Test name
Test status
Simulation time 354886198 ps
CPU time 3.71 seconds
Started Apr 15 02:26:30 PM PDT 24
Finished Apr 15 02:26:35 PM PDT 24
Peak memory 223000 kb
Host smart-bcac3076-f009-4a33-b6c2-a1301be2f345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959984256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1959984256
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4158160907
Short name T293
Test name
Test status
Simulation time 83732354 ps
CPU time 3.2 seconds
Started Apr 15 02:26:31 PM PDT 24
Finished Apr 15 02:26:34 PM PDT 24
Peak memory 208872 kb
Host smart-043a3dd5-ebb8-4ec8-a72b-c980a1878d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158160907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4158160907
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3620637732
Short name T369
Test name
Test status
Simulation time 155685853 ps
CPU time 3.13 seconds
Started Apr 15 02:26:34 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 222144 kb
Host smart-d638a996-3e08-4fe6-8b94-cdc985371054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620637732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3620637732
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.228682643
Short name T239
Test name
Test status
Simulation time 517419923 ps
CPU time 5.76 seconds
Started Apr 15 02:26:28 PM PDT 24
Finished Apr 15 02:26:34 PM PDT 24
Peak memory 220548 kb
Host smart-70a0a37f-6fc0-4457-bfcc-5e1601d69bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228682643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.228682643
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2918805607
Short name T286
Test name
Test status
Simulation time 824270855 ps
CPU time 16.57 seconds
Started Apr 15 02:26:25 PM PDT 24
Finished Apr 15 02:26:42 PM PDT 24
Peak memory 208712 kb
Host smart-d900ed8f-b8f8-42e2-a3d8-7dfef2dcbd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918805607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2918805607
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.739970616
Short name T767
Test name
Test status
Simulation time 52656435 ps
CPU time 2.47 seconds
Started Apr 15 02:26:24 PM PDT 24
Finished Apr 15 02:26:27 PM PDT 24
Peak memory 206948 kb
Host smart-9a6dd10c-1534-4aae-a9b0-dd8fa578e1a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739970616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.739970616
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1585418190
Short name T724
Test name
Test status
Simulation time 3057265176 ps
CPU time 23.17 seconds
Started Apr 15 02:26:25 PM PDT 24
Finished Apr 15 02:26:49 PM PDT 24
Peak memory 208304 kb
Host smart-299d9a5c-ab46-4983-9631-ecf353b943f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585418190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1585418190
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3674115177
Short name T549
Test name
Test status
Simulation time 700118424 ps
CPU time 3.8 seconds
Started Apr 15 02:26:28 PM PDT 24
Finished Apr 15 02:26:32 PM PDT 24
Peak memory 208712 kb
Host smart-bd4ed7b3-5993-4a93-b722-8642d32e4592
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674115177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3674115177
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3214128147
Short name T585
Test name
Test status
Simulation time 1164018693 ps
CPU time 2.92 seconds
Started Apr 15 02:26:30 PM PDT 24
Finished Apr 15 02:26:34 PM PDT 24
Peak memory 209404 kb
Host smart-791c46d3-0a3f-4242-a7f4-a0ebb9d5bc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214128147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3214128147
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2128354942
Short name T833
Test name
Test status
Simulation time 50340084 ps
CPU time 2.73 seconds
Started Apr 15 02:26:24 PM PDT 24
Finished Apr 15 02:26:27 PM PDT 24
Peak memory 207120 kb
Host smart-25ca6039-f196-452f-830f-c77f2cc1e0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128354942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2128354942
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.103167084
Short name T637
Test name
Test status
Simulation time 18526950557 ps
CPU time 122.39 seconds
Started Apr 15 02:26:32 PM PDT 24
Finished Apr 15 02:28:36 PM PDT 24
Peak memory 217696 kb
Host smart-8b277640-931c-4a8d-952a-276d65aa2343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103167084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.103167084
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.247656750
Short name T800
Test name
Test status
Simulation time 551737562 ps
CPU time 18.11 seconds
Started Apr 15 02:26:32 PM PDT 24
Finished Apr 15 02:26:51 PM PDT 24
Peak memory 222348 kb
Host smart-c3b68000-38d2-49ca-a689-fe610dac4282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247656750 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.247656750
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2504379545
Short name T328
Test name
Test status
Simulation time 91709042 ps
CPU time 4.42 seconds
Started Apr 15 02:26:30 PM PDT 24
Finished Apr 15 02:26:35 PM PDT 24
Peak memory 208660 kb
Host smart-a8527773-cf57-4d19-b7b1-26d336be48af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504379545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2504379545
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1141184870
Short name T797
Test name
Test status
Simulation time 3163115666 ps
CPU time 16.23 seconds
Started Apr 15 02:26:34 PM PDT 24
Finished Apr 15 02:26:51 PM PDT 24
Peak memory 210956 kb
Host smart-516d6ccc-fd17-446b-8db2-1da21006a167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141184870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1141184870
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3541375970
Short name T592
Test name
Test status
Simulation time 17866418 ps
CPU time 1.01 seconds
Started Apr 15 02:29:14 PM PDT 24
Finished Apr 15 02:29:17 PM PDT 24
Peak memory 206424 kb
Host smart-0079d1ce-75e5-4832-9f3a-c25a53825045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541375970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3541375970
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1750872818
Short name T663
Test name
Test status
Simulation time 130407740 ps
CPU time 2.71 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:29:23 PM PDT 24
Peak memory 222200 kb
Host smart-a95b1944-2846-46f6-aab2-4c5b0684793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750872818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1750872818
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1150843598
Short name T892
Test name
Test status
Simulation time 89013256 ps
CPU time 2.4 seconds
Started Apr 15 02:29:13 PM PDT 24
Finished Apr 15 02:29:17 PM PDT 24
Peak memory 207200 kb
Host smart-a6642f8b-7d77-4769-aee4-6d2532ee79df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150843598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1150843598
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3693399120
Short name T100
Test name
Test status
Simulation time 118077561 ps
CPU time 5.28 seconds
Started Apr 15 02:29:15 PM PDT 24
Finished Apr 15 02:29:21 PM PDT 24
Peak memory 221832 kb
Host smart-2278d688-b520-4950-adbc-cb8d475bd3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693399120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3693399120
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.954318849
Short name T361
Test name
Test status
Simulation time 311605809 ps
CPU time 4.28 seconds
Started Apr 15 02:29:15 PM PDT 24
Finished Apr 15 02:29:20 PM PDT 24
Peak memory 214600 kb
Host smart-ec20d782-3d0d-4479-bae2-a805a7dca0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954318849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.954318849
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.979922670
Short name T67
Test name
Test status
Simulation time 57049704 ps
CPU time 3.76 seconds
Started Apr 15 02:29:12 PM PDT 24
Finished Apr 15 02:29:17 PM PDT 24
Peak memory 209924 kb
Host smart-530c410a-40b7-4adc-b202-fef548f13847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979922670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.979922670
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1365666732
Short name T702
Test name
Test status
Simulation time 108761655 ps
CPU time 5.07 seconds
Started Apr 15 02:29:16 PM PDT 24
Finished Apr 15 02:29:22 PM PDT 24
Peak memory 210872 kb
Host smart-dba36d68-db5f-4b13-b775-eb685aa6d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365666732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1365666732
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.488257570
Short name T522
Test name
Test status
Simulation time 183763639 ps
CPU time 2.6 seconds
Started Apr 15 02:29:09 PM PDT 24
Finished Apr 15 02:29:13 PM PDT 24
Peak memory 208940 kb
Host smart-429ea1d1-83b0-4d6b-a933-9f2403569860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488257570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.488257570
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3942035289
Short name T484
Test name
Test status
Simulation time 52456511 ps
CPU time 2.96 seconds
Started Apr 15 02:29:10 PM PDT 24
Finished Apr 15 02:29:14 PM PDT 24
Peak memory 208608 kb
Host smart-7b2c8679-d405-444f-b680-df3565e55ecb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942035289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3942035289
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.57634047
Short name T753
Test name
Test status
Simulation time 71012391 ps
CPU time 3.04 seconds
Started Apr 15 02:29:06 PM PDT 24
Finished Apr 15 02:29:11 PM PDT 24
Peak memory 207044 kb
Host smart-ad38fdb4-15b9-4b54-ba9f-1e489049f8d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57634047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.57634047
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2504707708
Short name T403
Test name
Test status
Simulation time 189841862 ps
CPU time 2.69 seconds
Started Apr 15 02:29:14 PM PDT 24
Finished Apr 15 02:29:18 PM PDT 24
Peak memory 207196 kb
Host smart-2ad1aad2-d232-412a-832a-16027aa99cfc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504707708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2504707708
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3042354627
Short name T727
Test name
Test status
Simulation time 208171869 ps
CPU time 7.93 seconds
Started Apr 15 02:29:13 PM PDT 24
Finished Apr 15 02:29:23 PM PDT 24
Peak memory 218576 kb
Host smart-e3e2105d-5a26-4c47-a0a7-cb235abfafe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042354627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3042354627
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3660692535
Short name T730
Test name
Test status
Simulation time 21597714 ps
CPU time 1.84 seconds
Started Apr 15 02:29:06 PM PDT 24
Finished Apr 15 02:29:09 PM PDT 24
Peak memory 207004 kb
Host smart-a523c6fd-6ee5-468f-aba6-7535648038b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660692535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3660692535
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1812983386
Short name T731
Test name
Test status
Simulation time 137000904 ps
CPU time 5.28 seconds
Started Apr 15 02:29:15 PM PDT 24
Finished Apr 15 02:29:21 PM PDT 24
Peak memory 209996 kb
Host smart-80e6e245-75a8-4596-a388-94df345ca3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812983386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1812983386
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3699377340
Short name T145
Test name
Test status
Simulation time 87106891 ps
CPU time 3.07 seconds
Started Apr 15 02:29:13 PM PDT 24
Finished Apr 15 02:29:18 PM PDT 24
Peak memory 210780 kb
Host smart-33798d24-0e2f-40ea-886f-ab9cceaa49a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699377340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3699377340
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2278214265
Short name T485
Test name
Test status
Simulation time 50906471 ps
CPU time 0.93 seconds
Started Apr 15 02:29:18 PM PDT 24
Finished Apr 15 02:29:20 PM PDT 24
Peak memory 206484 kb
Host smart-89a536f0-6a11-4aa4-8e05-27ac27f73ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278214265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2278214265
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3500353421
Short name T397
Test name
Test status
Simulation time 41270618 ps
CPU time 2.86 seconds
Started Apr 15 02:29:14 PM PDT 24
Finished Apr 15 02:29:19 PM PDT 24
Peak memory 214568 kb
Host smart-6ce7ccf0-810b-45f3-a4d2-8ff26f9ff001
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500353421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3500353421
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2045333185
Short name T821
Test name
Test status
Simulation time 4472304492 ps
CPU time 7.89 seconds
Started Apr 15 02:29:14 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 208756 kb
Host smart-3b7c87f3-92f6-487a-8488-a90c9f9e257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045333185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2045333185
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3820845966
Short name T92
Test name
Test status
Simulation time 162701675 ps
CPU time 5.47 seconds
Started Apr 15 02:29:18 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 221012 kb
Host smart-481a4238-0ebe-475c-a017-b1d63feb325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820845966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3820845966
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3601478770
Short name T567
Test name
Test status
Simulation time 185180466 ps
CPU time 3.45 seconds
Started Apr 15 02:29:17 PM PDT 24
Finished Apr 15 02:29:21 PM PDT 24
Peak memory 222784 kb
Host smart-95505149-e44b-42cf-a69b-17120ca834fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601478770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3601478770
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1788671313
Short name T792
Test name
Test status
Simulation time 354325966 ps
CPU time 2.43 seconds
Started Apr 15 02:29:18 PM PDT 24
Finished Apr 15 02:29:21 PM PDT 24
Peak memory 209456 kb
Host smart-c41add35-1944-40a7-8330-508e8bcf1064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788671313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1788671313
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3673682139
Short name T608
Test name
Test status
Simulation time 955038520 ps
CPU time 8.12 seconds
Started Apr 15 02:29:11 PM PDT 24
Finished Apr 15 02:29:21 PM PDT 24
Peak memory 214532 kb
Host smart-dc4d5c9c-951f-4575-8260-663d74ea400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673682139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3673682139
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2969155662
Short name T842
Test name
Test status
Simulation time 75012209 ps
CPU time 3.51 seconds
Started Apr 15 02:29:17 PM PDT 24
Finished Apr 15 02:29:22 PM PDT 24
Peak memory 208844 kb
Host smart-9cf0fa11-3c4d-4f8e-9ccb-a1f3e7b474bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969155662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2969155662
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2511226005
Short name T632
Test name
Test status
Simulation time 244142927 ps
CPU time 2.87 seconds
Started Apr 15 02:29:18 PM PDT 24
Finished Apr 15 02:29:22 PM PDT 24
Peak memory 208928 kb
Host smart-a4ecf901-6ee5-4de5-9120-f617b183365d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511226005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2511226005
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2067688225
Short name T807
Test name
Test status
Simulation time 111762406 ps
CPU time 2.44 seconds
Started Apr 15 02:29:16 PM PDT 24
Finished Apr 15 02:29:19 PM PDT 24
Peak memory 207084 kb
Host smart-3510d1e2-3d37-45fd-9f4c-a445910534dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067688225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2067688225
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.386598184
Short name T300
Test name
Test status
Simulation time 642593529 ps
CPU time 16.79 seconds
Started Apr 15 02:29:14 PM PDT 24
Finished Apr 15 02:29:32 PM PDT 24
Peak memory 209176 kb
Host smart-69c39a76-fc30-4476-8360-f70e80e3ffc4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386598184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.386598184
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2256295362
Short name T601
Test name
Test status
Simulation time 45470917 ps
CPU time 1.8 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 207960 kb
Host smart-a5155b3c-6b00-460f-83b3-2f4b5a9f1290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256295362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2256295362
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.326098334
Short name T440
Test name
Test status
Simulation time 307373431 ps
CPU time 3.91 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 207632 kb
Host smart-0bdec324-6a6b-4032-9b69-d0294ccaa6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326098334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.326098334
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.533325016
Short name T176
Test name
Test status
Simulation time 460741568 ps
CPU time 15.89 seconds
Started Apr 15 02:29:20 PM PDT 24
Finished Apr 15 02:29:37 PM PDT 24
Peak memory 222892 kb
Host smart-35c57b94-8436-4494-ae7d-59f290864822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533325016 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.533325016
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3909175773
Short name T763
Test name
Test status
Simulation time 59590527 ps
CPU time 3.91 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 208260 kb
Host smart-ba493774-7ff0-4dc8-8c4f-194a68160acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909175773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3909175773
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3268387951
Short name T56
Test name
Test status
Simulation time 287312490 ps
CPU time 7.46 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:30 PM PDT 24
Peak memory 210592 kb
Host smart-b73520d7-5c5a-4c59-b92b-9af8ee8d5adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268387951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3268387951
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1153959583
Short name T835
Test name
Test status
Simulation time 45855888 ps
CPU time 0.97 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:29:21 PM PDT 24
Peak memory 206432 kb
Host smart-0ca5de5f-fb8f-4845-899a-82f729c749da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153959583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1153959583
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2970640680
Short name T276
Test name
Test status
Simulation time 807055942 ps
CPU time 42.34 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:30:06 PM PDT 24
Peak memory 215196 kb
Host smart-dd77cfa6-4e01-4d3c-ad3c-cc75333a49ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970640680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2970640680
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3795830143
Short name T870
Test name
Test status
Simulation time 100803707 ps
CPU time 1.95 seconds
Started Apr 15 02:29:21 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 210152 kb
Host smart-9918db4c-7913-4404-90b0-13c0d9955be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795830143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3795830143
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.258690316
Short name T313
Test name
Test status
Simulation time 242069239 ps
CPU time 3 seconds
Started Apr 15 02:29:18 PM PDT 24
Finished Apr 15 02:29:23 PM PDT 24
Peak memory 209604 kb
Host smart-cc93bfcc-9cb6-4a81-918a-7cf7c46852e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258690316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.258690316
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.668839857
Short name T363
Test name
Test status
Simulation time 423390340 ps
CPU time 3.62 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 222800 kb
Host smart-242834b3-d55c-4b84-b489-0d0ad1de11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668839857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.668839857
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3233233712
Short name T50
Test name
Test status
Simulation time 29087043 ps
CPU time 1.66 seconds
Started Apr 15 02:29:20 PM PDT 24
Finished Apr 15 02:29:22 PM PDT 24
Peak memory 214684 kb
Host smart-96dc7427-46a6-48b7-8656-1bc17ef5ba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233233712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3233233712
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.4063860782
Short name T230
Test name
Test status
Simulation time 417218216 ps
CPU time 8.43 seconds
Started Apr 15 02:29:18 PM PDT 24
Finished Apr 15 02:29:27 PM PDT 24
Peak memory 219604 kb
Host smart-066a561f-233d-46ed-971e-b3f306605ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063860782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.4063860782
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2820320962
Short name T87
Test name
Test status
Simulation time 170625535 ps
CPU time 4.97 seconds
Started Apr 15 02:29:21 PM PDT 24
Finished Apr 15 02:29:27 PM PDT 24
Peak memory 208140 kb
Host smart-f5265621-0d52-41be-9b3f-5c261429ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820320962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2820320962
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3111794168
Short name T845
Test name
Test status
Simulation time 66372970 ps
CPU time 3.43 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:29:23 PM PDT 24
Peak memory 208840 kb
Host smart-7cfad47f-4ac8-4a34-a8f5-c8a607bebbbf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111794168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3111794168
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.4175173902
Short name T745
Test name
Test status
Simulation time 132831943 ps
CPU time 4.86 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:29:25 PM PDT 24
Peak memory 207444 kb
Host smart-0975c5f6-e3c5-4341-b5bb-503f7c9dadd4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175173902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4175173902
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1000498294
Short name T578
Test name
Test status
Simulation time 248635094 ps
CPU time 3.84 seconds
Started Apr 15 02:29:17 PM PDT 24
Finished Apr 15 02:29:22 PM PDT 24
Peak memory 209032 kb
Host smart-0d1fdcb2-2cab-4a8b-ae23-24c36c5932aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000498294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1000498294
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1141033114
Short name T634
Test name
Test status
Simulation time 63810530 ps
CPU time 3.41 seconds
Started Apr 15 02:29:17 PM PDT 24
Finished Apr 15 02:29:22 PM PDT 24
Peak memory 214652 kb
Host smart-6e0c0345-4eac-482d-aa75-d51cc9a0ef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141033114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1141033114
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.543156061
Short name T722
Test name
Test status
Simulation time 1835212674 ps
CPU time 43.69 seconds
Started Apr 15 02:29:19 PM PDT 24
Finished Apr 15 02:30:04 PM PDT 24
Peak memory 208916 kb
Host smart-41dd9683-57d0-4380-90f3-b8ffac1df03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543156061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.543156061
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.55762829
Short name T790
Test name
Test status
Simulation time 63665815 ps
CPU time 3.88 seconds
Started Apr 15 02:29:17 PM PDT 24
Finished Apr 15 02:29:22 PM PDT 24
Peak memory 209728 kb
Host smart-2c03a3fd-9f10-4183-a4ff-23cb7390bf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55762829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.55762829
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1763627459
Short name T836
Test name
Test status
Simulation time 108648256 ps
CPU time 2.85 seconds
Started Apr 15 02:29:20 PM PDT 24
Finished Apr 15 02:29:23 PM PDT 24
Peak memory 211144 kb
Host smart-9245829f-e8c3-4fee-bb76-b4d9057a2ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763627459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1763627459
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3515000307
Short name T898
Test name
Test status
Simulation time 34861082 ps
CPU time 0.84 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:24 PM PDT 24
Peak memory 206300 kb
Host smart-95f6d6ff-2cc3-4d10-916c-7f2d80b4c550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515000307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3515000307
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.59331368
Short name T9
Test name
Test status
Simulation time 44285118 ps
CPU time 2.99 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:26 PM PDT 24
Peak memory 210568 kb
Host smart-7c7d0902-9d3f-4346-8b4f-4b46bf588367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59331368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.59331368
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.547713623
Short name T71
Test name
Test status
Simulation time 90238177 ps
CPU time 2.85 seconds
Started Apr 15 02:29:34 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 214600 kb
Host smart-c1630cbb-0499-4559-9b55-52151f0e5b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547713623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.547713623
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1722908309
Short name T98
Test name
Test status
Simulation time 52774646 ps
CPU time 3.15 seconds
Started Apr 15 02:29:27 PM PDT 24
Finished Apr 15 02:29:31 PM PDT 24
Peak memory 222768 kb
Host smart-e23a2ab3-a50a-4276-899d-8e69974fe802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722908309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1722908309
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2133746834
Short name T282
Test name
Test status
Simulation time 782094025 ps
CPU time 7.72 seconds
Started Apr 15 02:29:23 PM PDT 24
Finished Apr 15 02:29:32 PM PDT 24
Peak memory 214664 kb
Host smart-737d2a9d-375d-462c-bee7-c23bb3aef0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133746834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2133746834
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1505306732
Short name T596
Test name
Test status
Simulation time 102627086 ps
CPU time 3.54 seconds
Started Apr 15 02:29:27 PM PDT 24
Finished Apr 15 02:29:32 PM PDT 24
Peak memory 220548 kb
Host smart-f9d0a5ab-8650-43ab-b68b-bad4948d6ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505306732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1505306732
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3863485809
Short name T279
Test name
Test status
Simulation time 2723382134 ps
CPU time 39.3 seconds
Started Apr 15 02:29:17 PM PDT 24
Finished Apr 15 02:29:57 PM PDT 24
Peak memory 210640 kb
Host smart-dce3c3c6-b178-4a6a-bddc-5dfd904360f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863485809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3863485809
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2757078207
Short name T404
Test name
Test status
Simulation time 492398423 ps
CPU time 3.61 seconds
Started Apr 15 02:29:21 PM PDT 24
Finished Apr 15 02:29:25 PM PDT 24
Peak memory 207112 kb
Host smart-7f5fd0d7-a797-45cf-b76a-28d8d20a4201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757078207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2757078207
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1443429467
Short name T496
Test name
Test status
Simulation time 550192925 ps
CPU time 4.13 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:28 PM PDT 24
Peak memory 207216 kb
Host smart-9a09582c-3752-4405-aede-7d7aa68abf8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443429467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1443429467
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3521037877
Short name T463
Test name
Test status
Simulation time 384635914 ps
CPU time 6.21 seconds
Started Apr 15 02:29:20 PM PDT 24
Finished Apr 15 02:29:28 PM PDT 24
Peak memory 208368 kb
Host smart-2d8a60cf-e977-45b8-8478-7534140929d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521037877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3521037877
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1671881201
Short name T873
Test name
Test status
Simulation time 61438017 ps
CPU time 1.84 seconds
Started Apr 15 02:29:20 PM PDT 24
Finished Apr 15 02:29:23 PM PDT 24
Peak memory 207012 kb
Host smart-4567ead4-b3f7-4865-9ada-c3b757f3f829
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671881201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1671881201
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1402839933
Short name T149
Test name
Test status
Simulation time 37781723 ps
CPU time 2.62 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:26 PM PDT 24
Peak memory 216096 kb
Host smart-5355ade0-fe62-4586-8f9c-385be30bf197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402839933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1402839933
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2213106589
Short name T467
Test name
Test status
Simulation time 209405867 ps
CPU time 2.49 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:26 PM PDT 24
Peak memory 206476 kb
Host smart-6fddc399-976c-455b-b0f7-dc70cb840e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213106589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2213106589
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.727979466
Short name T337
Test name
Test status
Simulation time 4895453488 ps
CPU time 12.93 seconds
Started Apr 15 02:29:25 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 216788 kb
Host smart-17063997-7746-43cb-86b3-812fd1bc5b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727979466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.727979466
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.548562722
Short name T804
Test name
Test status
Simulation time 366923974 ps
CPU time 8.69 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:32 PM PDT 24
Peak memory 222924 kb
Host smart-bc2e25d8-4220-4626-96c3-5e433f9ba56c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548562722 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.548562722
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.550568087
Short name T772
Test name
Test status
Simulation time 356029269 ps
CPU time 3.51 seconds
Started Apr 15 02:29:25 PM PDT 24
Finished Apr 15 02:29:30 PM PDT 24
Peak memory 207696 kb
Host smart-9569eb32-0bcf-4a02-a8ff-9985e51f4956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550568087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.550568087
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2870747128
Short name T151
Test name
Test status
Simulation time 48611779 ps
CPU time 1.82 seconds
Started Apr 15 02:29:26 PM PDT 24
Finished Apr 15 02:29:29 PM PDT 24
Peak memory 210516 kb
Host smart-f2efc802-2808-45f4-a98f-0c0383331422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870747128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2870747128
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3315558273
Short name T147
Test name
Test status
Simulation time 23794765 ps
CPU time 0.78 seconds
Started Apr 15 02:29:28 PM PDT 24
Finished Apr 15 02:29:30 PM PDT 24
Peak memory 206212 kb
Host smart-8e363ed5-ed46-44e1-8b99-2bf4a0e0b713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315558273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3315558273
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3573235685
Short name T156
Test name
Test status
Simulation time 5052118683 ps
CPU time 41.13 seconds
Started Apr 15 02:29:23 PM PDT 24
Finished Apr 15 02:30:06 PM PDT 24
Peak memory 216124 kb
Host smart-bfd75a59-5368-4126-a7f9-babe27a179bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573235685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3573235685
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.428571597
Short name T829
Test name
Test status
Simulation time 76430893 ps
CPU time 3.09 seconds
Started Apr 15 02:29:26 PM PDT 24
Finished Apr 15 02:29:31 PM PDT 24
Peak memory 209196 kb
Host smart-789ddb87-a74f-4d33-b234-93f278d3617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428571597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.428571597
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.71398676
Short name T598
Test name
Test status
Simulation time 145371397 ps
CPU time 5.25 seconds
Started Apr 15 02:29:28 PM PDT 24
Finished Apr 15 02:29:35 PM PDT 24
Peak memory 219224 kb
Host smart-2b807b90-8ad8-4958-ac58-19bffb03bb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71398676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.71398676
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.945222347
Short name T269
Test name
Test status
Simulation time 198170148 ps
CPU time 6.76 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:31 PM PDT 24
Peak memory 222608 kb
Host smart-f532390b-f19a-4f6f-9660-ac0186f54b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945222347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.945222347
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.4120280360
Short name T433
Test name
Test status
Simulation time 301503068 ps
CPU time 4.09 seconds
Started Apr 15 02:29:23 PM PDT 24
Finished Apr 15 02:29:28 PM PDT 24
Peak memory 222848 kb
Host smart-5e07c033-8412-40f6-b669-4188970e41e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120280360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.4120280360
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2078322780
Short name T255
Test name
Test status
Simulation time 132519110 ps
CPU time 5.69 seconds
Started Apr 15 02:29:23 PM PDT 24
Finished Apr 15 02:29:30 PM PDT 24
Peak memory 218688 kb
Host smart-d170b2f4-97cb-42d5-aced-baf825a1ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078322780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2078322780
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.59124170
Short name T544
Test name
Test status
Simulation time 87436052 ps
CPU time 3.04 seconds
Started Apr 15 02:29:21 PM PDT 24
Finished Apr 15 02:29:25 PM PDT 24
Peak memory 207080 kb
Host smart-defc324d-ccbb-45f1-ad5b-7ae8c39cae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59124170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.59124170
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3721130264
Short name T471
Test name
Test status
Simulation time 226988723 ps
CPU time 4.16 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:28 PM PDT 24
Peak memory 208680 kb
Host smart-86d5047e-7c8f-4dd8-ab28-0b928d2ff578
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721130264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3721130264
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3829292486
Short name T851
Test name
Test status
Simulation time 518109753 ps
CPU time 10.28 seconds
Started Apr 15 02:29:28 PM PDT 24
Finished Apr 15 02:29:40 PM PDT 24
Peak memory 208176 kb
Host smart-0a9f28bb-d08b-46b1-be85-a8979ab4373e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829292486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3829292486
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2746985988
Short name T501
Test name
Test status
Simulation time 102721371 ps
CPU time 1.92 seconds
Started Apr 15 02:29:23 PM PDT 24
Finished Apr 15 02:29:27 PM PDT 24
Peak memory 206356 kb
Host smart-dd5a89a1-67b7-424c-b068-acdeb5ab1745
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746985988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2746985988
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.4275426713
Short name T864
Test name
Test status
Simulation time 544984729 ps
CPU time 15.14 seconds
Started Apr 15 02:29:23 PM PDT 24
Finished Apr 15 02:29:40 PM PDT 24
Peak memory 208628 kb
Host smart-2c98b73b-0312-4d9c-b97c-a5c8cc412bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275426713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4275426713
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1199906390
Short name T439
Test name
Test status
Simulation time 64765539 ps
CPU time 2.35 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:25 PM PDT 24
Peak memory 207088 kb
Host smart-e113966b-df75-4356-97d2-e66e87d2e049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199906390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1199906390
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.474269685
Short name T450
Test name
Test status
Simulation time 27641309 ps
CPU time 2.25 seconds
Started Apr 15 02:29:21 PM PDT 24
Finished Apr 15 02:29:25 PM PDT 24
Peak memory 207792 kb
Host smart-98b63123-af64-4857-a5b1-7b7e404ef8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474269685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.474269685
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3683837456
Short name T392
Test name
Test status
Simulation time 141991515 ps
CPU time 2.42 seconds
Started Apr 15 02:29:22 PM PDT 24
Finished Apr 15 02:29:26 PM PDT 24
Peak memory 210180 kb
Host smart-2003c0ba-1fd2-4fb6-8443-3ee841316728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683837456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3683837456
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.522831759
Short name T682
Test name
Test status
Simulation time 12997613 ps
CPU time 0.79 seconds
Started Apr 15 02:29:28 PM PDT 24
Finished Apr 15 02:29:30 PM PDT 24
Peak memory 206284 kb
Host smart-65c0e851-2f9b-4796-84c1-4f8d6ccb84b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522831759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.522831759
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.596068515
Short name T157
Test name
Test status
Simulation time 3261362881 ps
CPU time 39.75 seconds
Started Apr 15 02:29:24 PM PDT 24
Finished Apr 15 02:30:05 PM PDT 24
Peak memory 222752 kb
Host smart-c374781f-e452-4b36-9aef-539e40653883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596068515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.596068515
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.258353833
Short name T774
Test name
Test status
Simulation time 86073621 ps
CPU time 3.62 seconds
Started Apr 15 02:29:26 PM PDT 24
Finished Apr 15 02:29:30 PM PDT 24
Peak memory 218420 kb
Host smart-e79d49ad-012b-4091-a30b-82cb93d486e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258353833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.258353833
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2782984081
Short name T305
Test name
Test status
Simulation time 138986100 ps
CPU time 4.07 seconds
Started Apr 15 02:29:38 PM PDT 24
Finished Apr 15 02:29:44 PM PDT 24
Peak memory 209428 kb
Host smart-d2ad177f-d9b7-4025-827f-730265b66b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782984081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2782984081
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2923126115
Short name T539
Test name
Test status
Simulation time 957479701 ps
CPU time 7.32 seconds
Started Apr 15 02:29:30 PM PDT 24
Finished Apr 15 02:29:38 PM PDT 24
Peak memory 210100 kb
Host smart-e2e6f29a-d609-4e03-a846-e9023497a924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923126115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2923126115
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1994286174
Short name T856
Test name
Test status
Simulation time 1061338943 ps
CPU time 8.91 seconds
Started Apr 15 02:29:28 PM PDT 24
Finished Apr 15 02:29:38 PM PDT 24
Peak memory 211876 kb
Host smart-178c7463-16b3-4a1a-aa75-df688465edad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994286174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1994286174
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1203797547
Short name T710
Test name
Test status
Simulation time 130359556 ps
CPU time 3.59 seconds
Started Apr 15 02:29:27 PM PDT 24
Finished Apr 15 02:29:32 PM PDT 24
Peak memory 220800 kb
Host smart-ec3a035c-137c-4389-988e-675c4ff761ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203797547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1203797547
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.200076248
Short name T370
Test name
Test status
Simulation time 414441276 ps
CPU time 5.43 seconds
Started Apr 15 02:29:26 PM PDT 24
Finished Apr 15 02:29:33 PM PDT 24
Peak memory 208800 kb
Host smart-143279b3-b3cc-45b1-b0e1-90ed3f5aa526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200076248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.200076248
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.4113487358
Short name T121
Test name
Test status
Simulation time 988388687 ps
CPU time 32.51 seconds
Started Apr 15 02:29:26 PM PDT 24
Finished Apr 15 02:30:00 PM PDT 24
Peak memory 208400 kb
Host smart-80264762-558e-42c5-bdce-89aadf35313d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113487358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4113487358
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3786697158
Short name T894
Test name
Test status
Simulation time 114312486 ps
CPU time 4.98 seconds
Started Apr 15 02:29:26 PM PDT 24
Finished Apr 15 02:29:32 PM PDT 24
Peak memory 206964 kb
Host smart-94ea3ef0-bfd9-4a37-9434-c4f1e593bb6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786697158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3786697158
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2324352816
Short name T456
Test name
Test status
Simulation time 198816954 ps
CPU time 2.75 seconds
Started Apr 15 02:29:29 PM PDT 24
Finished Apr 15 02:29:34 PM PDT 24
Peak memory 207144 kb
Host smart-fb6db15e-de48-462c-8e83-0e135be1d367
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324352816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2324352816
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3128774254
Short name T805
Test name
Test status
Simulation time 193796957 ps
CPU time 1.93 seconds
Started Apr 15 02:29:25 PM PDT 24
Finished Apr 15 02:29:28 PM PDT 24
Peak memory 208368 kb
Host smart-fa772909-80a4-4540-8b51-0682d7d714fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128774254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3128774254
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1831251424
Short name T455
Test name
Test status
Simulation time 143435771 ps
CPU time 3.84 seconds
Started Apr 15 02:29:32 PM PDT 24
Finished Apr 15 02:29:38 PM PDT 24
Peak memory 208160 kb
Host smart-c318ecc6-e2bb-4808-a9e2-31659316f0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831251424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1831251424
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3742647860
Short name T399
Test name
Test status
Simulation time 219017675 ps
CPU time 5.27 seconds
Started Apr 15 02:29:29 PM PDT 24
Finished Apr 15 02:29:36 PM PDT 24
Peak memory 208392 kb
Host smart-4e184f11-56b7-4851-86fc-e35aff7640e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742647860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3742647860
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3288358592
Short name T207
Test name
Test status
Simulation time 124211028 ps
CPU time 2.25 seconds
Started Apr 15 02:29:27 PM PDT 24
Finished Apr 15 02:29:31 PM PDT 24
Peak memory 210068 kb
Host smart-5ff4ce29-af1a-48cc-839f-76ce9020d7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288358592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3288358592
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4222279250
Short name T545
Test name
Test status
Simulation time 9786199 ps
CPU time 0.76 seconds
Started Apr 15 02:29:30 PM PDT 24
Finished Apr 15 02:29:32 PM PDT 24
Peak memory 206300 kb
Host smart-c8eadc97-5f80-41e7-9444-ac8c4708fae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222279250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4222279250
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.182263140
Short name T431
Test name
Test status
Simulation time 40902804 ps
CPU time 3.33 seconds
Started Apr 15 02:29:31 PM PDT 24
Finished Apr 15 02:29:36 PM PDT 24
Peak memory 215844 kb
Host smart-bdc854b7-a477-484e-a857-68c1197a8787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182263140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.182263140
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.620039400
Short name T8
Test name
Test status
Simulation time 85784099 ps
CPU time 4.21 seconds
Started Apr 15 02:29:32 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 214864 kb
Host smart-222ad78f-224e-41c6-aa1e-da770c1c136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620039400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.620039400
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1057232616
Short name T528
Test name
Test status
Simulation time 25334412 ps
CPU time 1.65 seconds
Started Apr 15 02:29:31 PM PDT 24
Finished Apr 15 02:29:34 PM PDT 24
Peak memory 207292 kb
Host smart-e286dd27-202a-407a-9971-32538d08dfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057232616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1057232616
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1216084216
Short name T22
Test name
Test status
Simulation time 124464515 ps
CPU time 3.36 seconds
Started Apr 15 02:29:33 PM PDT 24
Finished Apr 15 02:29:38 PM PDT 24
Peak memory 214664 kb
Host smart-65331fd0-c1ce-4921-a813-6b52a0762202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216084216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1216084216
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.4189983380
Short name T858
Test name
Test status
Simulation time 124652530 ps
CPU time 3.82 seconds
Started Apr 15 02:29:28 PM PDT 24
Finished Apr 15 02:29:33 PM PDT 24
Peak memory 215264 kb
Host smart-45c77dea-a032-4dd4-a489-6be6e7bc17c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189983380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4189983380
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.4049425095
Short name T655
Test name
Test status
Simulation time 956843674 ps
CPU time 7.01 seconds
Started Apr 15 02:29:32 PM PDT 24
Finished Apr 15 02:29:41 PM PDT 24
Peak memory 208704 kb
Host smart-bf3d4d23-eeed-469b-88d1-a0eb7752f39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049425095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4049425095
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3520340424
Short name T587
Test name
Test status
Simulation time 135995297 ps
CPU time 2.61 seconds
Started Apr 15 02:29:27 PM PDT 24
Finished Apr 15 02:29:31 PM PDT 24
Peak memory 207692 kb
Host smart-be070a91-8c2f-4b04-b8a8-c4acc23251e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520340424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3520340424
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.707052511
Short name T690
Test name
Test status
Simulation time 203157841 ps
CPU time 2.63 seconds
Started Apr 15 02:29:32 PM PDT 24
Finished Apr 15 02:29:37 PM PDT 24
Peak memory 208084 kb
Host smart-32b95e8c-a4c6-4db9-8c2a-21ae39215f75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707052511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.707052511
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.508899054
Short name T860
Test name
Test status
Simulation time 1072581669 ps
CPU time 24.75 seconds
Started Apr 15 02:29:29 PM PDT 24
Finished Apr 15 02:29:56 PM PDT 24
Peak memory 208708 kb
Host smart-d6c087f1-59ce-4977-b483-f759b28793dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508899054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.508899054
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2154899047
Short name T674
Test name
Test status
Simulation time 131271186 ps
CPU time 4.27 seconds
Started Apr 15 02:29:29 PM PDT 24
Finished Apr 15 02:29:34 PM PDT 24
Peak memory 207112 kb
Host smart-7a29a18f-8bf3-4086-a1c3-a4038ea9da02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154899047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2154899047
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3838970808
Short name T810
Test name
Test status
Simulation time 2064524198 ps
CPU time 10.99 seconds
Started Apr 15 02:29:33 PM PDT 24
Finished Apr 15 02:29:46 PM PDT 24
Peak memory 218848 kb
Host smart-c368a3ec-419d-4efb-8ccb-8934b7363c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838970808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3838970808
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3896313590
Short name T462
Test name
Test status
Simulation time 1512136363 ps
CPU time 37.52 seconds
Started Apr 15 02:29:29 PM PDT 24
Finished Apr 15 02:30:08 PM PDT 24
Peak memory 208376 kb
Host smart-838f8130-58de-483c-b8c4-3f9e02e2687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896313590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3896313590
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.4239492067
Short name T170
Test name
Test status
Simulation time 205327248 ps
CPU time 6.37 seconds
Started Apr 15 02:29:33 PM PDT 24
Finished Apr 15 02:29:41 PM PDT 24
Peak memory 220884 kb
Host smart-9d418efc-2e66-4c62-a88f-d6a5aab8619d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239492067 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.4239492067
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3342305669
Short name T343
Test name
Test status
Simulation time 196507440 ps
CPU time 5.11 seconds
Started Apr 15 02:29:30 PM PDT 24
Finished Apr 15 02:29:36 PM PDT 24
Peak memory 209456 kb
Host smart-1c2d8ef0-0607-43fd-bc6e-a23139b042ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342305669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3342305669
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.4154179439
Short name T853
Test name
Test status
Simulation time 310914827 ps
CPU time 2.77 seconds
Started Apr 15 02:29:33 PM PDT 24
Finished Apr 15 02:29:38 PM PDT 24
Peak memory 210908 kb
Host smart-e3be0062-ad5c-4beb-8872-aa87d3924997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154179439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.4154179439
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1488302142
Short name T569
Test name
Test status
Simulation time 54504946 ps
CPU time 0.98 seconds
Started Apr 15 02:29:41 PM PDT 24
Finished Apr 15 02:29:43 PM PDT 24
Peak memory 206432 kb
Host smart-c4577ae0-269e-4825-b87f-87e0fc7b39ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488302142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1488302142
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2841977099
Short name T498
Test name
Test status
Simulation time 109335138 ps
CPU time 2.23 seconds
Started Apr 15 02:29:31 PM PDT 24
Finished Apr 15 02:29:36 PM PDT 24
Peak memory 209864 kb
Host smart-42dd1f1d-f7c7-4fe7-8f7d-0951a05bd20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841977099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2841977099
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.636303167
Short name T487
Test name
Test status
Simulation time 411265793 ps
CPU time 7.83 seconds
Started Apr 15 02:29:33 PM PDT 24
Finished Apr 15 02:29:43 PM PDT 24
Peak memory 222796 kb
Host smart-0c96c295-c602-4063-b279-8b1095edbc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636303167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.636303167
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2880720868
Short name T622
Test name
Test status
Simulation time 74693422 ps
CPU time 4.07 seconds
Started Apr 15 02:29:32 PM PDT 24
Finished Apr 15 02:29:38 PM PDT 24
Peak memory 211172 kb
Host smart-608d53b3-56e2-4435-8966-7966c5277970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880720868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2880720868
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1448246233
Short name T46
Test name
Test status
Simulation time 192122765 ps
CPU time 4.2 seconds
Started Apr 15 02:29:30 PM PDT 24
Finished Apr 15 02:29:36 PM PDT 24
Peak memory 210584 kb
Host smart-70a27f4f-74b7-4ad3-a0d0-272dc4ee91e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448246233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1448246233
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.959833751
Short name T568
Test name
Test status
Simulation time 359487624 ps
CPU time 4.62 seconds
Started Apr 15 02:29:32 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 215536 kb
Host smart-72cd2740-3947-429c-a530-f3a6cb0f7320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959833751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.959833751
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2961560178
Short name T288
Test name
Test status
Simulation time 251363503 ps
CPU time 3.31 seconds
Started Apr 15 02:29:33 PM PDT 24
Finished Apr 15 02:29:38 PM PDT 24
Peak memory 207056 kb
Host smart-51f4f651-8975-48d0-8f93-616af5868a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961560178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2961560178
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1860650416
Short name T378
Test name
Test status
Simulation time 1015382941 ps
CPU time 7.83 seconds
Started Apr 15 02:29:38 PM PDT 24
Finished Apr 15 02:29:47 PM PDT 24
Peak memory 208312 kb
Host smart-d687577c-bc72-4fab-a7fd-7d893aeb0f1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860650416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1860650416
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.43670092
Short name T683
Test name
Test status
Simulation time 109514962 ps
CPU time 4.69 seconds
Started Apr 15 02:29:33 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 208864 kb
Host smart-fd1e6498-201d-4624-b976-a833b3f048d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43670092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.43670092
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.85923384
Short name T883
Test name
Test status
Simulation time 495959867 ps
CPU time 5.76 seconds
Started Apr 15 02:29:34 PM PDT 24
Finished Apr 15 02:29:42 PM PDT 24
Peak memory 208312 kb
Host smart-b59f6f15-45bf-4c93-badb-67fae80a46ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85923384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.85923384
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1600702845
Short name T478
Test name
Test status
Simulation time 56591075 ps
CPU time 2.98 seconds
Started Apr 15 02:29:35 PM PDT 24
Finished Apr 15 02:29:40 PM PDT 24
Peak memory 208504 kb
Host smart-201abebb-98b9-421b-8d10-bcd9471acc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600702845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1600702845
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.425447998
Short name T227
Test name
Test status
Simulation time 57248730 ps
CPU time 2.62 seconds
Started Apr 15 02:29:37 PM PDT 24
Finished Apr 15 02:29:42 PM PDT 24
Peak memory 208472 kb
Host smart-647c409b-af9c-42bb-b96f-3001eb3e0560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425447998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.425447998
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.424391131
Short name T167
Test name
Test status
Simulation time 715271316 ps
CPU time 9.42 seconds
Started Apr 15 02:29:39 PM PDT 24
Finished Apr 15 02:29:50 PM PDT 24
Peak memory 222924 kb
Host smart-5de017de-1fee-43b0-bb49-90cabe06fa6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424391131 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.424391131
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2012242314
Short name T784
Test name
Test status
Simulation time 61924655 ps
CPU time 3.66 seconds
Started Apr 15 02:29:33 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 210676 kb
Host smart-c8b90562-ab17-4840-9691-58d8ece64e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012242314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2012242314
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2783026179
Short name T55
Test name
Test status
Simulation time 80779835 ps
CPU time 1.79 seconds
Started Apr 15 02:29:36 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 210332 kb
Host smart-c9786954-5f64-4bab-aac6-617a1de19f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783026179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2783026179
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2708598245
Short name T448
Test name
Test status
Simulation time 177033510 ps
CPU time 0.83 seconds
Started Apr 15 02:29:41 PM PDT 24
Finished Apr 15 02:29:43 PM PDT 24
Peak memory 206224 kb
Host smart-732dc00f-93ce-4682-9497-483f9424e693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708598245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2708598245
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3699533065
Short name T418
Test name
Test status
Simulation time 407665151 ps
CPU time 6.31 seconds
Started Apr 15 02:29:35 PM PDT 24
Finished Apr 15 02:29:43 PM PDT 24
Peak memory 215652 kb
Host smart-a326ad7d-6cdc-4f80-9ee6-cd34a7bbdec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699533065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3699533065
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1101603497
Short name T904
Test name
Test status
Simulation time 174521782 ps
CPU time 4.03 seconds
Started Apr 15 02:29:35 PM PDT 24
Finished Apr 15 02:29:41 PM PDT 24
Peak memory 209372 kb
Host smart-50117ce8-9eb0-4540-a362-88ce39a32747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101603497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1101603497
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2972356635
Short name T882
Test name
Test status
Simulation time 417957143 ps
CPU time 6.51 seconds
Started Apr 15 02:29:42 PM PDT 24
Finished Apr 15 02:29:49 PM PDT 24
Peak memory 214552 kb
Host smart-f4bea80b-716d-44c6-bf56-a97445b77eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972356635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2972356635
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.602543
Short name T232
Test name
Test status
Simulation time 123785372 ps
CPU time 4.8 seconds
Started Apr 15 02:29:34 PM PDT 24
Finished Apr 15 02:29:40 PM PDT 24
Peak memory 211472 kb
Host smart-98810a30-acb0-4530-aceb-3eb3caa9c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.602543
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.214766514
Short name T237
Test name
Test status
Simulation time 152635863 ps
CPU time 2.75 seconds
Started Apr 15 02:29:38 PM PDT 24
Finished Apr 15 02:29:42 PM PDT 24
Peak memory 219820 kb
Host smart-b80ec95a-e459-4b79-b8e9-b9bced1d69ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214766514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.214766514
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2456274665
Short name T303
Test name
Test status
Simulation time 158730220 ps
CPU time 2.31 seconds
Started Apr 15 02:29:39 PM PDT 24
Finished Apr 15 02:29:43 PM PDT 24
Peak memory 218708 kb
Host smart-13d15c36-d2dc-4de3-aaa4-435738bfde2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456274665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2456274665
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2364441965
Short name T356
Test name
Test status
Simulation time 222338921 ps
CPU time 3.04 seconds
Started Apr 15 02:29:36 PM PDT 24
Finished Apr 15 02:29:41 PM PDT 24
Peak memory 207112 kb
Host smart-a52f9d26-a738-4eff-8007-89fb5e0a9d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364441965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2364441965
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2631820758
Short name T494
Test name
Test status
Simulation time 25764866 ps
CPU time 1.88 seconds
Started Apr 15 02:29:34 PM PDT 24
Finished Apr 15 02:29:38 PM PDT 24
Peak memory 207136 kb
Host smart-63f6a2b9-b47f-41ec-a69e-311a880fc98a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631820758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2631820758
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3920697403
Short name T554
Test name
Test status
Simulation time 27982260 ps
CPU time 2.21 seconds
Started Apr 15 02:29:42 PM PDT 24
Finished Apr 15 02:29:45 PM PDT 24
Peak memory 208828 kb
Host smart-0429b3ef-af26-4a1c-ac69-6875b2fa2507
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920697403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3920697403
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1077541454
Short name T720
Test name
Test status
Simulation time 1069179171 ps
CPU time 8.32 seconds
Started Apr 15 02:29:35 PM PDT 24
Finished Apr 15 02:29:45 PM PDT 24
Peak memory 209020 kb
Host smart-d6f01bf4-7c47-4588-9952-2eff416dfea0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077541454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1077541454
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3512454893
Short name T506
Test name
Test status
Simulation time 363089370 ps
CPU time 2.78 seconds
Started Apr 15 02:29:34 PM PDT 24
Finished Apr 15 02:29:39 PM PDT 24
Peak memory 209468 kb
Host smart-8e705055-8f8d-4c9f-bbcd-7d265ee372ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512454893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3512454893
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2018239605
Short name T691
Test name
Test status
Simulation time 127868076 ps
CPU time 3.55 seconds
Started Apr 15 02:29:36 PM PDT 24
Finished Apr 15 02:29:41 PM PDT 24
Peak memory 206840 kb
Host smart-20241daa-4f85-4197-b3b2-5365e3715fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018239605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2018239605
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3235184737
Short name T668
Test name
Test status
Simulation time 321780590 ps
CPU time 5.4 seconds
Started Apr 15 02:29:37 PM PDT 24
Finished Apr 15 02:29:45 PM PDT 24
Peak memory 219272 kb
Host smart-2faf786f-c867-4bf9-b2af-ff67f307d769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235184737 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3235184737
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.767114617
Short name T225
Test name
Test status
Simulation time 353985688 ps
CPU time 4.39 seconds
Started Apr 15 02:29:34 PM PDT 24
Finished Apr 15 02:29:40 PM PDT 24
Peak memory 207988 kb
Host smart-502252f7-e9c0-4eec-ad64-34b73d05f01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767114617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.767114617
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.494437191
Short name T521
Test name
Test status
Simulation time 159310788 ps
CPU time 2.59 seconds
Started Apr 15 02:29:33 PM PDT 24
Finished Apr 15 02:29:38 PM PDT 24
Peak memory 210184 kb
Host smart-7b5b941f-5d55-402a-98d2-150a25df96e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494437191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.494437191
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1715377329
Short name T477
Test name
Test status
Simulation time 13663831 ps
CPU time 0.73 seconds
Started Apr 15 02:29:47 PM PDT 24
Finished Apr 15 02:29:49 PM PDT 24
Peak memory 206276 kb
Host smart-812c4f82-aa80-4ca7-945e-0432113a0d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715377329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1715377329
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4136130256
Short name T741
Test name
Test status
Simulation time 150355780 ps
CPU time 5.6 seconds
Started Apr 15 02:29:43 PM PDT 24
Finished Apr 15 02:29:50 PM PDT 24
Peak memory 218692 kb
Host smart-41d62149-3d72-4294-b65b-a2eac19a954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136130256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4136130256
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2747227587
Short name T748
Test name
Test status
Simulation time 59064578 ps
CPU time 2.3 seconds
Started Apr 15 02:29:40 PM PDT 24
Finished Apr 15 02:29:44 PM PDT 24
Peak memory 220180 kb
Host smart-468c1d96-3516-4d23-bedf-e7a6941037e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747227587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2747227587
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4161465150
Short name T388
Test name
Test status
Simulation time 160535969 ps
CPU time 3.01 seconds
Started Apr 15 02:29:39 PM PDT 24
Finished Apr 15 02:29:43 PM PDT 24
Peak memory 220960 kb
Host smart-78930114-ea51-4eb9-bc49-2954e0fc57c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161465150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4161465150
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.342537292
Short name T350
Test name
Test status
Simulation time 158315469 ps
CPU time 6.93 seconds
Started Apr 15 02:29:40 PM PDT 24
Finished Apr 15 02:29:49 PM PDT 24
Peak memory 222772 kb
Host smart-83414ede-5437-4135-ba73-39ca9597f1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342537292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.342537292
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2355630640
Short name T43
Test name
Test status
Simulation time 86651838 ps
CPU time 3.75 seconds
Started Apr 15 02:29:39 PM PDT 24
Finished Apr 15 02:29:44 PM PDT 24
Peak memory 219528 kb
Host smart-7ac69f6d-f98a-47d8-9bff-b94536277f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355630640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2355630640
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.4054275182
Short name T224
Test name
Test status
Simulation time 1034697344 ps
CPU time 6.9 seconds
Started Apr 15 02:29:41 PM PDT 24
Finished Apr 15 02:29:49 PM PDT 24
Peak memory 207876 kb
Host smart-e2d5aa0f-8c29-499a-91f6-c98cb941050d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054275182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.4054275182
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2865413010
Short name T666
Test name
Test status
Simulation time 124624832 ps
CPU time 4.17 seconds
Started Apr 15 02:29:38 PM PDT 24
Finished Apr 15 02:29:44 PM PDT 24
Peak memory 208916 kb
Host smart-9a0375da-0c0f-4436-9b3d-bfaca35554df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865413010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2865413010
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2772265777
Short name T885
Test name
Test status
Simulation time 843141150 ps
CPU time 28.83 seconds
Started Apr 15 02:29:41 PM PDT 24
Finished Apr 15 02:30:11 PM PDT 24
Peak memory 208580 kb
Host smart-3b27165e-a903-407f-9939-a18f4da5b876
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772265777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2772265777
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.590996455
Short name T466
Test name
Test status
Simulation time 106674266 ps
CPU time 2.96 seconds
Started Apr 15 02:29:41 PM PDT 24
Finished Apr 15 02:29:45 PM PDT 24
Peak memory 208420 kb
Host smart-35da2d27-5986-483c-a7f3-5ab30ff598e5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590996455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.590996455
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3635385082
Short name T744
Test name
Test status
Simulation time 203343572 ps
CPU time 3.19 seconds
Started Apr 15 02:29:41 PM PDT 24
Finished Apr 15 02:29:45 PM PDT 24
Peak memory 207064 kb
Host smart-6fcfdc16-025f-4c75-bce3-1a2d8bd5f176
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635385082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3635385082
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1673371347
Short name T869
Test name
Test status
Simulation time 354658089 ps
CPU time 5.99 seconds
Started Apr 15 02:29:38 PM PDT 24
Finished Apr 15 02:29:46 PM PDT 24
Peak memory 208268 kb
Host smart-c006199d-426f-40a8-a611-5969aa7abd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673371347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1673371347
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3514471200
Short name T493
Test name
Test status
Simulation time 1031414934 ps
CPU time 3.69 seconds
Started Apr 15 02:29:42 PM PDT 24
Finished Apr 15 02:29:46 PM PDT 24
Peak memory 207348 kb
Host smart-6c408cbb-b0b9-4745-b078-100a93bbeab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514471200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3514471200
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1011258701
Short name T751
Test name
Test status
Simulation time 1279726895 ps
CPU time 6.7 seconds
Started Apr 15 02:29:40 PM PDT 24
Finished Apr 15 02:29:47 PM PDT 24
Peak memory 214628 kb
Host smart-f0b0e8f0-eeb8-4907-8abb-ddfcc45e3473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011258701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1011258701
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.825729853
Short name T178
Test name
Test status
Simulation time 2989934832 ps
CPU time 16.68 seconds
Started Apr 15 02:29:42 PM PDT 24
Finished Apr 15 02:30:00 PM PDT 24
Peak memory 211164 kb
Host smart-7d77f385-a073-437a-90f7-b1364fba1506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825729853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.825729853
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4044623699
Short name T435
Test name
Test status
Simulation time 42251749 ps
CPU time 0.77 seconds
Started Apr 15 02:26:34 PM PDT 24
Finished Apr 15 02:26:36 PM PDT 24
Peak memory 206228 kb
Host smart-80d520f3-8f7b-4e80-9b3c-1a4a433d5eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044623699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4044623699
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2083736620
Short name T432
Test name
Test status
Simulation time 132748625 ps
CPU time 2.67 seconds
Started Apr 15 02:26:35 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 214616 kb
Host smart-69dd2eb2-9157-4a64-9ac2-c5b0bdf30302
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083736620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2083736620
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3414496083
Short name T458
Test name
Test status
Simulation time 128681306 ps
CPU time 3.24 seconds
Started Apr 15 02:26:34 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 207428 kb
Host smart-ef396e96-82c8-4568-bee7-01e04d2668c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414496083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3414496083
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_random.1688601028
Short name T14
Test name
Test status
Simulation time 34754773 ps
CPU time 2.47 seconds
Started Apr 15 02:26:34 PM PDT 24
Finished Apr 15 02:26:37 PM PDT 24
Peak memory 207664 kb
Host smart-4a276c43-eee4-4c05-83b8-1dfa79edd33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688601028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1688601028
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.198176239
Short name T694
Test name
Test status
Simulation time 191981231 ps
CPU time 2.88 seconds
Started Apr 15 02:26:30 PM PDT 24
Finished Apr 15 02:26:34 PM PDT 24
Peak memory 207068 kb
Host smart-18ad6509-e89d-4f6e-88dd-0a7d59619999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198176239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.198176239
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2291966510
Short name T586
Test name
Test status
Simulation time 148929122 ps
CPU time 2.65 seconds
Started Apr 15 02:26:29 PM PDT 24
Finished Apr 15 02:26:32 PM PDT 24
Peak memory 208804 kb
Host smart-3bf9ae62-a9e5-416d-8788-ced85b35e340
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291966510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2291966510
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.514324563
Short name T354
Test name
Test status
Simulation time 3025036833 ps
CPU time 6.53 seconds
Started Apr 15 02:26:28 PM PDT 24
Finished Apr 15 02:26:35 PM PDT 24
Peak memory 208908 kb
Host smart-8dac6a1f-c4fa-4cff-9eae-7b6fb38aad5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514324563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.514324563
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1145430444
Short name T782
Test name
Test status
Simulation time 209803277 ps
CPU time 3.1 seconds
Started Apr 15 02:26:35 PM PDT 24
Finished Apr 15 02:26:39 PM PDT 24
Peak memory 208408 kb
Host smart-2171b9f2-d61e-49d8-bd6d-7ce3484bbc2a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145430444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1145430444
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2327551018
Short name T654
Test name
Test status
Simulation time 58345001 ps
CPU time 2.4 seconds
Started Apr 15 02:26:48 PM PDT 24
Finished Apr 15 02:26:51 PM PDT 24
Peak memory 218456 kb
Host smart-058f57ae-4628-4701-ab28-4f6f5194b9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327551018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2327551018
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.625452358
Short name T626
Test name
Test status
Simulation time 97473788 ps
CPU time 2.67 seconds
Started Apr 15 02:26:29 PM PDT 24
Finished Apr 15 02:26:32 PM PDT 24
Peak memory 207348 kb
Host smart-214fdb38-9278-4e0d-8dac-9172d657a23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625452358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.625452358
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3989935509
Short name T275
Test name
Test status
Simulation time 4473540195 ps
CPU time 12.88 seconds
Started Apr 15 02:26:34 PM PDT 24
Finished Apr 15 02:26:48 PM PDT 24
Peak memory 222820 kb
Host smart-0dc920e9-1218-488e-b3f9-7fbb71dd2862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989935509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3989935509
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.459802867
Short name T755
Test name
Test status
Simulation time 277044128 ps
CPU time 4.13 seconds
Started Apr 15 02:26:33 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 208496 kb
Host smart-e302b08a-8c75-4ab2-9674-870ed4da1c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459802867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.459802867
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1615417655
Short name T519
Test name
Test status
Simulation time 126106278 ps
CPU time 1.65 seconds
Started Apr 15 02:26:32 PM PDT 24
Finished Apr 15 02:26:34 PM PDT 24
Peak memory 210176 kb
Host smart-94f30337-707d-4a6b-a382-4f779f245601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615417655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1615417655
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2047579985
Short name T711
Test name
Test status
Simulation time 16945199 ps
CPU time 0.82 seconds
Started Apr 15 02:26:41 PM PDT 24
Finished Apr 15 02:26:43 PM PDT 24
Peak memory 206316 kb
Host smart-8d4cdbfa-4412-4e2c-bb5b-012ec29aff1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047579985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2047579985
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3272477740
Short name T414
Test name
Test status
Simulation time 51370937 ps
CPU time 3.57 seconds
Started Apr 15 02:26:37 PM PDT 24
Finished Apr 15 02:26:41 PM PDT 24
Peak memory 216040 kb
Host smart-cd5a7b3f-0d96-4558-9099-58cb663b5505
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272477740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3272477740
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2204531128
Short name T670
Test name
Test status
Simulation time 202548320 ps
CPU time 4.97 seconds
Started Apr 15 02:26:41 PM PDT 24
Finished Apr 15 02:26:46 PM PDT 24
Peak memory 210520 kb
Host smart-70e0f6a1-e304-4700-8f7b-7fd32fb206c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204531128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2204531128
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1859318280
Short name T352
Test name
Test status
Simulation time 474569447 ps
CPU time 4.25 seconds
Started Apr 15 02:26:37 PM PDT 24
Finished Apr 15 02:26:42 PM PDT 24
Peak memory 218464 kb
Host smart-abb402cc-000d-4ef5-bd94-49e4fb40664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859318280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1859318280
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.4236077419
Short name T628
Test name
Test status
Simulation time 144374335 ps
CPU time 5.71 seconds
Started Apr 15 02:26:38 PM PDT 24
Finished Apr 15 02:26:45 PM PDT 24
Peak memory 218292 kb
Host smart-88865fd8-7315-4955-95f0-879342173db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236077419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.4236077419
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3788511702
Short name T385
Test name
Test status
Simulation time 279620578 ps
CPU time 4.02 seconds
Started Apr 15 02:26:40 PM PDT 24
Finished Apr 15 02:26:45 PM PDT 24
Peak memory 207264 kb
Host smart-1c25f574-b7aa-4f3d-8c57-e34e47964c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788511702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3788511702
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1721150888
Short name T840
Test name
Test status
Simulation time 210771493 ps
CPU time 3.41 seconds
Started Apr 15 02:26:35 PM PDT 24
Finished Apr 15 02:26:39 PM PDT 24
Peak memory 207328 kb
Host smart-045956c9-9178-4cd0-aab0-3e604c731241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721150888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1721150888
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4237125099
Short name T675
Test name
Test status
Simulation time 75610197 ps
CPU time 3.36 seconds
Started Apr 15 02:26:37 PM PDT 24
Finished Apr 15 02:26:41 PM PDT 24
Peak memory 208812 kb
Host smart-7dcb6e69-1c75-4c5d-bf48-f57417df37ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237125099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4237125099
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2543474718
Short name T367
Test name
Test status
Simulation time 174785740 ps
CPU time 4.86 seconds
Started Apr 15 02:26:39 PM PDT 24
Finished Apr 15 02:26:45 PM PDT 24
Peak memory 208528 kb
Host smart-0a99e551-2222-44d2-9aae-3f66eb91c5a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543474718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2543474718
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2351789372
Short name T619
Test name
Test status
Simulation time 84104341 ps
CPU time 1.96 seconds
Started Apr 15 02:26:36 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 207104 kb
Host smart-708de3a1-d4f1-439a-b072-a1f0fb99a3e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351789372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2351789372
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3166104467
Short name T325
Test name
Test status
Simulation time 123262997 ps
CPU time 2.71 seconds
Started Apr 15 02:26:37 PM PDT 24
Finished Apr 15 02:26:41 PM PDT 24
Peak memory 210088 kb
Host smart-cc0bb58a-7468-48fa-b06e-e6a26181cfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166104467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3166104467
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.117730416
Short name T407
Test name
Test status
Simulation time 454003352 ps
CPU time 3.44 seconds
Started Apr 15 02:26:34 PM PDT 24
Finished Apr 15 02:26:38 PM PDT 24
Peak memory 208780 kb
Host smart-d7127621-a192-49f1-840a-46977df136b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117730416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.117730416
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.531604532
Short name T140
Test name
Test status
Simulation time 294939462 ps
CPU time 12.46 seconds
Started Apr 15 02:26:47 PM PDT 24
Finished Apr 15 02:27:00 PM PDT 24
Peak memory 222972 kb
Host smart-1e0f5add-efa0-4cc4-a662-0a6b01ee040e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531604532 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.531604532
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2007576873
Short name T338
Test name
Test status
Simulation time 229332698 ps
CPU time 7.76 seconds
Started Apr 15 02:26:40 PM PDT 24
Finished Apr 15 02:26:49 PM PDT 24
Peak memory 218920 kb
Host smart-49dd85bd-f34f-402f-9c39-039e8fc41775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007576873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2007576873
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2943386596
Short name T486
Test name
Test status
Simulation time 130733104 ps
CPU time 1.94 seconds
Started Apr 15 02:26:42 PM PDT 24
Finished Apr 15 02:26:45 PM PDT 24
Peak memory 210296 kb
Host smart-47ea1926-20c0-4202-8964-dd814e19c21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943386596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2943386596
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3646905270
Short name T839
Test name
Test status
Simulation time 17430174 ps
CPU time 0.86 seconds
Started Apr 15 02:26:46 PM PDT 24
Finished Apr 15 02:26:48 PM PDT 24
Peak memory 206248 kb
Host smart-c36aad93-966b-4609-a354-c05533d004f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646905270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3646905270
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.765027015
Short name T39
Test name
Test status
Simulation time 150300512 ps
CPU time 4.73 seconds
Started Apr 15 02:26:46 PM PDT 24
Finished Apr 15 02:26:51 PM PDT 24
Peak memory 214540 kb
Host smart-f1e8e1fe-961e-47b5-bffd-9fb83c69bf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765027015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.765027015
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4179078419
Short name T70
Test name
Test status
Simulation time 2675628370 ps
CPU time 16.33 seconds
Started Apr 15 02:26:51 PM PDT 24
Finished Apr 15 02:27:09 PM PDT 24
Peak memory 209712 kb
Host smart-f37c550f-8df3-4cf3-bd70-4980c4f4f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179078419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4179078419
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1810166481
Short name T102
Test name
Test status
Simulation time 118753879 ps
CPU time 2.58 seconds
Started Apr 15 02:26:45 PM PDT 24
Finished Apr 15 02:26:48 PM PDT 24
Peak memory 218256 kb
Host smart-1c6b3ed4-b480-4a3a-afcd-074fc688a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810166481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1810166481
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.4212924160
Short name T99
Test name
Test status
Simulation time 435447099 ps
CPU time 5.88 seconds
Started Apr 15 02:26:47 PM PDT 24
Finished Apr 15 02:26:53 PM PDT 24
Peak memory 214548 kb
Host smart-8debd8b3-f073-46ce-9ba4-7027b76aba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212924160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.4212924160
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.971908396
Short name T52
Test name
Test status
Simulation time 854947636 ps
CPU time 4.72 seconds
Started Apr 15 02:26:51 PM PDT 24
Finished Apr 15 02:26:57 PM PDT 24
Peak memory 209592 kb
Host smart-27f075bd-8be2-493a-85cc-c9e28b20057b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971908396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.971908396
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3749213972
Short name T515
Test name
Test status
Simulation time 155295239 ps
CPU time 4.55 seconds
Started Apr 15 02:26:42 PM PDT 24
Finished Apr 15 02:26:47 PM PDT 24
Peak memory 218564 kb
Host smart-62d6d089-b6a7-4bf4-9452-86b3688db2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749213972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3749213972
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3080874383
Short name T289
Test name
Test status
Simulation time 41862089 ps
CPU time 2.55 seconds
Started Apr 15 02:26:40 PM PDT 24
Finished Apr 15 02:26:44 PM PDT 24
Peak memory 208180 kb
Host smart-2e104ae5-be6a-44fb-820d-422e02eda20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080874383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3080874383
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.238566279
Short name T42
Test name
Test status
Simulation time 185566493 ps
CPU time 7.04 seconds
Started Apr 15 02:26:43 PM PDT 24
Finished Apr 15 02:26:51 PM PDT 24
Peak memory 209404 kb
Host smart-2a129688-02f7-4303-92f3-e0e33e1bc18f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238566279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.238566279
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1348574661
Short name T457
Test name
Test status
Simulation time 141616842 ps
CPU time 4.74 seconds
Started Apr 15 02:26:42 PM PDT 24
Finished Apr 15 02:26:48 PM PDT 24
Peak memory 208068 kb
Host smart-fdeecaa5-9965-4cda-b582-ed30768ba2cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348574661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1348574661
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.626232918
Short name T17
Test name
Test status
Simulation time 412753210 ps
CPU time 3.6 seconds
Started Apr 15 02:26:43 PM PDT 24
Finished Apr 15 02:26:47 PM PDT 24
Peak memory 208872 kb
Host smart-f554ab5d-20bc-4247-9252-6e2810802f2e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626232918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.626232918
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1014623847
Short name T146
Test name
Test status
Simulation time 455065356 ps
CPU time 3.05 seconds
Started Apr 15 02:26:45 PM PDT 24
Finished Apr 15 02:26:49 PM PDT 24
Peak memory 210112 kb
Host smart-7a053f67-bb50-4dbe-9d51-c9dd10592103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014623847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1014623847
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3491678639
Short name T443
Test name
Test status
Simulation time 57294072 ps
CPU time 2.83 seconds
Started Apr 15 02:26:43 PM PDT 24
Finished Apr 15 02:26:47 PM PDT 24
Peak memory 206436 kb
Host smart-9003280c-4151-46a7-8fe4-2d958f88195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491678639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3491678639
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2530822443
Short name T61
Test name
Test status
Simulation time 1680009026 ps
CPU time 18.3 seconds
Started Apr 15 02:26:47 PM PDT 24
Finished Apr 15 02:27:07 PM PDT 24
Peak memory 222936 kb
Host smart-1f8d2e7d-90da-4272-94b9-863fa9f27ab2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530822443 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2530822443
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2889382818
Short name T718
Test name
Test status
Simulation time 525738713 ps
CPU time 7.06 seconds
Started Apr 15 02:26:47 PM PDT 24
Finished Apr 15 02:26:55 PM PDT 24
Peak memory 218832 kb
Host smart-43c87958-5c08-43df-a646-beaa784288e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889382818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2889382818
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.100480591
Short name T734
Test name
Test status
Simulation time 171649978 ps
CPU time 3.38 seconds
Started Apr 15 02:26:45 PM PDT 24
Finished Apr 15 02:26:49 PM PDT 24
Peak memory 210836 kb
Host smart-c88570b7-209e-4fd6-ad66-acd6b3fa9dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100480591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.100480591
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.750298818
Short name T111
Test name
Test status
Simulation time 14811579 ps
CPU time 0.77 seconds
Started Apr 15 02:26:54 PM PDT 24
Finished Apr 15 02:26:55 PM PDT 24
Peak memory 206280 kb
Host smart-ccc584e0-d71e-4aed-aa87-e1ecefcf675a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750298818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.750298818
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3426511151
Short name T398
Test name
Test status
Simulation time 90928489 ps
CPU time 3.56 seconds
Started Apr 15 02:26:51 PM PDT 24
Finished Apr 15 02:26:55 PM PDT 24
Peak memory 214904 kb
Host smart-ad686ea4-f2ed-446d-8a39-b710602746d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426511151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3426511151
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1668742552
Short name T74
Test name
Test status
Simulation time 121260649 ps
CPU time 3.06 seconds
Started Apr 15 02:26:51 PM PDT 24
Finished Apr 15 02:26:55 PM PDT 24
Peak memory 223148 kb
Host smart-5700e33c-2fd6-40df-a665-478ae9d1c6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668742552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1668742552
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3214804568
Short name T76
Test name
Test status
Simulation time 267270091 ps
CPU time 1.53 seconds
Started Apr 15 02:26:51 PM PDT 24
Finished Apr 15 02:26:53 PM PDT 24
Peak memory 207888 kb
Host smart-3b0e9a96-89d1-40b3-b3da-2e7979f5a1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214804568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3214804568
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.361878438
Short name T572
Test name
Test status
Simulation time 1497340590 ps
CPU time 8.65 seconds
Started Apr 15 02:26:51 PM PDT 24
Finished Apr 15 02:27:01 PM PDT 24
Peak memory 210036 kb
Host smart-9edbd1b3-326f-42d9-8e49-96155fd938a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361878438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.361878438
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3661912826
Short name T35
Test name
Test status
Simulation time 4308626121 ps
CPU time 29.36 seconds
Started Apr 15 02:26:50 PM PDT 24
Finished Apr 15 02:27:20 PM PDT 24
Peak memory 222708 kb
Host smart-81330f29-0d55-4993-b224-5df4b118718b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661912826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3661912826
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2899727842
Short name T44
Test name
Test status
Simulation time 73649341 ps
CPU time 1.81 seconds
Started Apr 15 02:26:51 PM PDT 24
Finished Apr 15 02:26:54 PM PDT 24
Peak memory 215024 kb
Host smart-86c723f6-ed3c-4b2d-979a-4ffc89beaa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899727842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2899727842
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.746868252
Short name T580
Test name
Test status
Simulation time 1245674633 ps
CPU time 7.55 seconds
Started Apr 15 02:26:52 PM PDT 24
Finished Apr 15 02:27:00 PM PDT 24
Peak memory 214680 kb
Host smart-382fe3f2-d22f-4d77-9450-3a0869ddc0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746868252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.746868252
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2478030314
Short name T91
Test name
Test status
Simulation time 7131298889 ps
CPU time 46.71 seconds
Started Apr 15 02:27:07 PM PDT 24
Finished Apr 15 02:27:55 PM PDT 24
Peak memory 208188 kb
Host smart-46f1457c-827e-4124-8400-a4055bfbdfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478030314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2478030314
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3821534831
Short name T823
Test name
Test status
Simulation time 76855972 ps
CPU time 2.41 seconds
Started Apr 15 02:26:51 PM PDT 24
Finished Apr 15 02:26:54 PM PDT 24
Peak memory 207196 kb
Host smart-fc477084-559d-4e7f-b608-2125b9932f6a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821534831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3821534831
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.96311255
Short name T306
Test name
Test status
Simulation time 100225359 ps
CPU time 3.28 seconds
Started Apr 15 02:26:54 PM PDT 24
Finished Apr 15 02:26:58 PM PDT 24
Peak memory 209052 kb
Host smart-4f2ba2b2-77e2-46c4-919d-e1d73a3b6efe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96311255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.96311255
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2602923228
Short name T685
Test name
Test status
Simulation time 581047886 ps
CPU time 3.54 seconds
Started Apr 15 02:26:46 PM PDT 24
Finished Apr 15 02:26:50 PM PDT 24
Peak memory 208684 kb
Host smart-a13d7c53-d639-4e3d-9c61-197513a99c65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602923228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2602923228
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3873217113
Short name T600
Test name
Test status
Simulation time 207690552 ps
CPU time 2.96 seconds
Started Apr 15 02:26:54 PM PDT 24
Finished Apr 15 02:26:57 PM PDT 24
Peak memory 214660 kb
Host smart-f2ef57bd-98a1-435d-8c81-e444ee02d7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873217113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3873217113
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1247319966
Short name T653
Test name
Test status
Simulation time 75458597 ps
CPU time 1.75 seconds
Started Apr 15 02:26:46 PM PDT 24
Finished Apr 15 02:26:48 PM PDT 24
Peak memory 207004 kb
Host smart-83d34f93-d997-4f35-ba16-fa336f774be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247319966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1247319966
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.546505027
Short name T324
Test name
Test status
Simulation time 4099225049 ps
CPU time 59.25 seconds
Started Apr 15 02:26:55 PM PDT 24
Finished Apr 15 02:27:55 PM PDT 24
Peak memory 217224 kb
Host smart-7cf2629b-fd8c-4616-9218-152d8e7e6c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546505027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.546505027
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1907994995
Short name T609
Test name
Test status
Simulation time 96910995 ps
CPU time 5.02 seconds
Started Apr 15 02:26:49 PM PDT 24
Finished Apr 15 02:26:55 PM PDT 24
Peak memory 209348 kb
Host smart-00b57002-ac7a-4d75-bc3e-d060f5cb6796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907994995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1907994995
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.461200229
Short name T185
Test name
Test status
Simulation time 47399081 ps
CPU time 2.37 seconds
Started Apr 15 02:26:53 PM PDT 24
Finished Apr 15 02:26:56 PM PDT 24
Peak memory 210168 kb
Host smart-d003bb5f-e6b6-4f39-ae51-90107abedc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461200229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.461200229
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2395722396
Short name T822
Test name
Test status
Simulation time 156517694 ps
CPU time 0.92 seconds
Started Apr 15 02:27:04 PM PDT 24
Finished Apr 15 02:27:05 PM PDT 24
Peak memory 206280 kb
Host smart-4c8f8f10-c5fe-4a96-b7c2-2257951c56a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395722396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2395722396
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.90167556
Short name T274
Test name
Test status
Simulation time 228475994 ps
CPU time 4.65 seconds
Started Apr 15 02:26:58 PM PDT 24
Finished Apr 15 02:27:04 PM PDT 24
Peak memory 215560 kb
Host smart-9fa29a87-531a-496b-93e1-be8ba6247dfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90167556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.90167556
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1798201622
Short name T20
Test name
Test status
Simulation time 298787817 ps
CPU time 2.76 seconds
Started Apr 15 02:26:57 PM PDT 24
Finished Apr 15 02:27:00 PM PDT 24
Peak memory 223060 kb
Host smart-2b4a53d6-6729-49f9-845b-58ffb4710ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798201622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1798201622
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4233809162
Short name T643
Test name
Test status
Simulation time 33755301 ps
CPU time 2.38 seconds
Started Apr 15 02:26:58 PM PDT 24
Finished Apr 15 02:27:01 PM PDT 24
Peak memory 214664 kb
Host smart-5b187fb3-9106-45b8-97f9-684deb5ed1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233809162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4233809162
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2437714774
Short name T867
Test name
Test status
Simulation time 254313395 ps
CPU time 6.28 seconds
Started Apr 15 02:26:59 PM PDT 24
Finished Apr 15 02:27:06 PM PDT 24
Peak memory 209040 kb
Host smart-01d3258f-417f-49d5-89b6-ac83878e8e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437714774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2437714774
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3322248028
Short name T384
Test name
Test status
Simulation time 364003135 ps
CPU time 4.78 seconds
Started Apr 15 02:27:01 PM PDT 24
Finished Apr 15 02:27:06 PM PDT 24
Peak memory 214576 kb
Host smart-17bf8223-7cc5-4647-ae56-d18f4858fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322248028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3322248028
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2636202913
Short name T901
Test name
Test status
Simulation time 453247961 ps
CPU time 2.67 seconds
Started Apr 15 02:26:58 PM PDT 24
Finished Apr 15 02:27:01 PM PDT 24
Peak memory 206384 kb
Host smart-0f168f93-723d-48a3-977d-acf905430a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636202913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2636202913
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2019674711
Short name T90
Test name
Test status
Simulation time 78270100 ps
CPU time 4.22 seconds
Started Apr 15 02:26:59 PM PDT 24
Finished Apr 15 02:27:03 PM PDT 24
Peak memory 207780 kb
Host smart-d6450276-12eb-4266-883e-18c302a6ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019674711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2019674711
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2665924014
Short name T278
Test name
Test status
Simulation time 181605010 ps
CPU time 2.91 seconds
Started Apr 15 02:26:53 PM PDT 24
Finished Apr 15 02:26:57 PM PDT 24
Peak memory 208896 kb
Host smart-fb8157fb-f779-43e3-9f65-b6b90e3701da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665924014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2665924014
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1629243990
Short name T837
Test name
Test status
Simulation time 207102111 ps
CPU time 2.53 seconds
Started Apr 15 02:26:54 PM PDT 24
Finished Apr 15 02:26:58 PM PDT 24
Peak memory 207712 kb
Host smart-5cfdbd5c-75f6-4276-a94b-02b0fb5cedf2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629243990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1629243990
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.713862804
Short name T879
Test name
Test status
Simulation time 735195003 ps
CPU time 24 seconds
Started Apr 15 02:26:54 PM PDT 24
Finished Apr 15 02:27:19 PM PDT 24
Peak memory 208904 kb
Host smart-72870c5d-d99d-4462-8cdb-0f096d7b2a77
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713862804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.713862804
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3469453452
Short name T607
Test name
Test status
Simulation time 165463110 ps
CPU time 2.75 seconds
Started Apr 15 02:26:57 PM PDT 24
Finished Apr 15 02:27:01 PM PDT 24
Peak memory 207048 kb
Host smart-73ad6287-9b9f-486c-a8cb-32e407fc4287
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469453452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3469453452
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3194495010
Short name T123
Test name
Test status
Simulation time 411672920 ps
CPU time 12.32 seconds
Started Apr 15 02:27:00 PM PDT 24
Finished Apr 15 02:27:13 PM PDT 24
Peak memory 209724 kb
Host smart-c9c3f0dd-4314-4273-8758-d1304502f431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194495010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3194495010
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.331760663
Short name T534
Test name
Test status
Simulation time 1426394454 ps
CPU time 16.36 seconds
Started Apr 15 02:26:55 PM PDT 24
Finished Apr 15 02:27:12 PM PDT 24
Peak memory 207924 kb
Host smart-2961771f-00bb-4f59-a09d-2bf180b9041e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331760663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.331760663
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2978225096
Short name T243
Test name
Test status
Simulation time 467480524 ps
CPU time 4.96 seconds
Started Apr 15 02:26:59 PM PDT 24
Finished Apr 15 02:27:05 PM PDT 24
Peak memory 222676 kb
Host smart-d27cd8dd-82f3-4a8d-8c42-de210b75e2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978225096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2978225096
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2246507716
Short name T344
Test name
Test status
Simulation time 374559824 ps
CPU time 4.29 seconds
Started Apr 15 02:26:58 PM PDT 24
Finished Apr 15 02:27:02 PM PDT 24
Peak memory 209684 kb
Host smart-eb95bc0a-ca13-4af8-bd66-78d8e58cf683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246507716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2246507716
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3540467173
Short name T60
Test name
Test status
Simulation time 759231981 ps
CPU time 7.81 seconds
Started Apr 15 02:26:57 PM PDT 24
Finished Apr 15 02:27:05 PM PDT 24
Peak memory 211180 kb
Host smart-d0dcc44a-e153-4f6a-9788-ec2bcb1356e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540467173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3540467173
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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