Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4648

1

T1

6

T2

13

T3

43

auto[1]

561

1

T2

1

T3

5

T17

11

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4648

1

T1

6

T2

13

T3

43

auto[1]

561

1

T2

1

T3

5

T17

11

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4686

1

T1

6

T2

14

T3

43

auto[1]

523

1

T3

5

T14

3

T16

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4686

1

T1

6

T2

14

T3

43

auto[1]

523

1

T3

5

T14

3

T16

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T2	2		T3	6		T17	9
auto[OpGenId]	1074	1			T1	3		T2	4		T3	13
auto[OpGenSwOut]	1128	1			T1	1		T2	3		T3	12
auto[OpGenHwOut]	2509	1			T1	2		T2	5		T3	17
auto[OpDisable]	66	1			T18	1		T4	2		T45	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T2	2		T3	6		T17	9
auto[OpGenId]	1074	1			T1	3		T2	4		T3	13
auto[OpGenSwOut]	1128	1			T1	1		T2	3		T3	12
auto[OpGenHwOut]	2509	1			T1	2		T2	5		T3	17
auto[OpDisable]	66	1			T18	1		T4	2		T45	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4633

1

T1

6

T2

14

T3

43

auto[1]

576

1

T3

5

T16

2

T17

6

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4633

1

T1

6

T2

14

T3

43

auto[1]

576

1

T3

5

T16

2

T17

6

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4919

1

T1

6

T2

10

T3

48

auto[1]

290

1

T2

4

T70

4

T109

9

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1812	1			T1	1		T2	6		T3	16
auto[1]	672	1			T1	1		T3	7		T14	1
auto[2]	684	1			T2	1		T3	9		T13	2
auto[3]	674	1			T1	1		T2	3		T3	10
auto[4]	316	1			T1	1		T2	3		T3	1
auto[5]	369	1			T2	1		T3	3		T14	2
auto[6]	358	1			T1	2		T3	2		T14	1
auto[7]	324	1			T17	2		T20	1		T72	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1367	1			T1	3		T2	4		T3	6
clear_one[1]	672	1			T1	1		T3	7		T14	1
clear_one[2]	684	1			T2	1		T3	9		T13	2
clear_one[3]	674	1			T1	1		T2	3		T3	10
clear_none	1812	1			T1	1		T2	6		T3	16

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	939	1			T1	1		T2	5		T3	9
auto[StInit]	765	1			T1	3		T2	3		T3	7
auto[StCreatorRootKey]	567	1			T2	1		T3	6		T14	1
auto[StOwnerIntKey]	498	1			T1	1		T2	1		T3	2
auto[StOwnerKey]	455	1			T1	1		T2	1		T3	8
auto[StDisabled]	1833	1			T2	3		T3	16		T14	4
auto[StInvalid]	152	1			T13	3		T33	4		T62	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	939	1			T1	1		T2	5		T3	9
auto[StInit]	765	1			T1	3		T2	3		T3	7
auto[StCreatorRootKey]	567	1			T2	1		T3	6		T14	1
auto[StOwnerIntKey]	498	1			T1	1		T2	1		T3	2
auto[StOwnerKey]	455	1			T1	1		T2	1		T3	8
auto[StDisabled]	1833	1			T2	3		T3	16		T14	4
auto[StInvalid]	152	1			T13	3		T33	4		T62	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	6
[auto[2] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	6
[auto[2] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	24
[auto[2] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	6

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T234	1		T235	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	154	1			T1	1		T2	2		T3	3
auto[0]	auto[StReset]	auto[OpGenSwOut]	160	1			T3	2		T17	3		T20	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	249	1			T2	1		T3	1		T14	2
auto[0]	auto[StInit]	auto[OpAdvance]	47	1			T3	1		T17	1		T72	1
auto[0]	auto[StInit]	auto[OpGenId]	109	1			T17	2		T18	1		T20	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	114	1			T3	1		T15	1		T17	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	188	1			T3	3		T73	1		T52	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	23	1			T39	1		T109	1		T198	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	51	1			T17	1		T199	1		T197	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	53	1			T39	1		T4	1		T46	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	70	1			T3	1		T16	1		T70	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T3	1		T211	1		T44	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	22	1			T70	1		T39	1		T109	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	31	1			T15	1		T236	1		T54	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	62	1			T210	1		T68	1		T237	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T3	1		T17	1		T109	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	17	1			T45	1		T238	1		T48	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T41	1		T44	1		T239	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T73	1		T208	1		T207	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	38	1			T2	1		T17	1		T208	1
auto[0]	auto[StDisabled]	auto[OpGenId]	56	1			T72	1		T39	2		T4	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	76	1			T2	1		T3	1		T17	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	149	1			T2	1		T3	1		T14	1
auto[0]	auto[StDisabled]	auto[OpDisable]	17	1			T45	1		T41	1		T240	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	3	1			T203	1		T90	1		T241	1
auto[0]	auto[StInvalid]	auto[OpGenId]	5	1			T123	1		T242	1		T74	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T46	1		T206	1		T200	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T13	1		T62	1		T123	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T129	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	21	1			T38	1		T62	1		T102	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	11	1			T17	1		T4	1		T202	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	45	1			T17	1		T27	1		T210	1
auto[1]	auto[StInit]	auto[OpAdvance]	14	1			T17	1		T25	1		T238	1
auto[1]	auto[StInit]	auto[OpGenId]	14	1			T193	1		T77	1		T239	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T33	1		T41	1		T243	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T1	1		T207	1		T125	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T244	1		T6	1		T245	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T41	1		T132	1		T246	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T17	1		T196	1		T247	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T73	1		T41	2		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T4	1		T40	1		T249	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T205	1		T4	1		T102	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T16	1		T197	1		T52	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T19	1		T207	1		T250	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T109	1		T251	1		T188	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T3	2		T17	1		T65	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T252	1		T253	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T3	1		T67	1		T68	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	28	1			T3	1		T17	1		T70	1
auto[1]	auto[StDisabled]	auto[OpGenId]	56	1			T3	1		T17	1		T70	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T17	1		T52	1		T39	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T3	2		T14	1		T73	2
auto[1]	auto[StDisabled]	auto[OpDisable]	6	1			T4	1		T41	1		T56	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T255	1		T256	2		T82	2
auto[1]	auto[StInvalid]	auto[OpGenId]	6	1			T203	1		T195	2		T257	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T74	1		T258	1		T257	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T203	1		T242	1		T259	1
auto[2]	auto[StReset]	auto[OpGenId]	11	1			T260	1		T131	1		T261	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	18	1			T17	2		T4	1		T45	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	40	1			T4	1		T142	1		T262	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T3	1		T26	1		T58	1
auto[2]	auto[StInit]	auto[OpGenId]	9	1			T215	1		T75	1		T188	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	16	1			T24	1		T142	1		T78	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T17	1		T142	1		T260	2
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T41	1		T215	1		T116	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T3	1		T261	1		T263	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T41	2		T238	1		T86	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T19	1		T142	1		T41	2
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T260	1		T264	1		T219	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T265	1		T266	1		T96	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T45	1		T267	1		T131	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T3	1		T39	1		T212	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T64	1		T268	1		T44	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	18	1			T41	2		T269	1		T270	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T2	1		T3	1		T237	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T72	1		T39	1		T271	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	25	1			T45	2		T125	1		T129	1
auto[2]	auto[StDisabled]	auto[OpGenId]	50	1			T17	2		T199	1		T4	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	71	1			T3	3		T17	1		T72	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	153	1			T3	2		T14	1		T17	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T41	2		T272	1		T273	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T195	1		T274	1		T259	1
auto[2]	auto[StInvalid]	auto[OpGenId]	12	1			T13	2		T62	1		T206	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T184	1		T242	1		T259	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T209	1		T89	1		T82	1
auto[3]	auto[StReset]	auto[OpGenId]	14	1			T2	1		T3	1		T41	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	25	1			T3	1		T41	1		T6	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	38	1			T3	1		T212	1		T41	1
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T130	1		T275	1		T276	1
auto[3]	auto[StInit]	auto[OpGenId]	19	1			T2	1		T3	1		T26	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T1	1		T2	1		T4	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	33	1			T277	1		T278	1		T53	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T130	1		T117	1		T275	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T27	1		T279	1		T131	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T39	1		T4	1		T45	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T3	2		T212	1		T280	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T243	1		T188	1		T281	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T277	2		T57	1		T275	2
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T17	1		T41	1		T279	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T14	1		T39	1		T63	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T17	1		T277	1		T266	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	17	1			T17	1		T236	1		T267	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T3	1		T39	1		T277	2
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T3	1		T39	1		T282	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	31	1			T17	2		T39	1		T41	1
auto[3]	auto[StDisabled]	auto[OpGenId]	41	1			T3	1		T205	1		T4	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T196	1		T45	1		T41	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	145	1			T3	1		T17	1		T19	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T18	1		T41	1		T48	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	6	1			T33	1		T198	1		T283	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T198	1		T206	1		T209	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T62	1		T206	1		T195	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T184	1		T90	1		T284	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T48	1		T181	1		T42	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T17	1		T20	1		T41	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	17	1			T17	1		T207	1		T285	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T2	1		T89	1		T87	1
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T4	1		T286	1		T132	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	10	1			T48	1		T255	1		T74	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	15	1			T17	1		T19	1		T287	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T142	1		T288	1		T289	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T41	1		T182	1		T290	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T3	1		T126	1		T291	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T2	1		T29	1		T131	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T64	1		T216	1		T292	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T1	1		T45	1		T293	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T211	1		T57	1		T116	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	13	1			T2	1		T294	1		T124	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T48	1		T58	1		T295	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T296	1		T102	1		T291	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T40	1		T297	1		T298	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	13	1			T14	1		T19	1		T202	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	13	1			T4	1		T142	1		T125	1
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T72	1		T52	2		T201	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T17	2		T64	1		T142	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T17	1		T199	1		T39	1
auto[4]	auto[StDisabled]	auto[OpDisable]	3	1			T131	1		T188	1		T299	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T300	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	2	1			T33	1		T274	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T184	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T300	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T6	1		T48	1		T115	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	5	1			T142	1		T77	1		T53	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	22	1			T2	1		T210	1		T212	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T301	1		T302	1		T298	1
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T25	1		T36	1		T116	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T131	1		T251	1		T40	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T14	1		T4	1		T41	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T303	1		-	-		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T3	1		T17	1		T44	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T66	1		T102	1		T304	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T14	1		T63	1		T305	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T306	1		T307	1		T308	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T115	1		T216	1		T309	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T41	2		T131	1		T310	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T211	1		T311	1		T312	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T133	1		T289	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T3	1		T17	1		T44	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T197	1		T313	1		T314	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T199	1		T210	1		T248	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	19	1			T70	1		T315	1		T243	1
auto[5]	auto[StDisabled]	auto[OpGenId]	21	1			T17	1		T70	1		T41	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T3	1		T316	1		T317	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	91	1			T17	2		T210	1		T4	1
auto[5]	auto[StDisabled]	auto[OpDisable]	7	1			T243	1		T59	1		T219	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T81	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T81	1		T318	1		T283	2
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T255	1		T284	1		T319	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T209	1		T320	1		-	-
auto[6]	auto[StReset]	auto[OpGenId]	6	1			T40	1		T216	1		T321	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	9	1			T238	1		T129	1		T272	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T186	1		T36	1		T131	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T247	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T78	1		T322	1		T323	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T78	1		T286	1		T324	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T1	1		T25	1		T261	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T4	1		T76	1		T324	2
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T131	1		T40	1		T322	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T239	1		T233	1		T325	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T207	1		T33	1		T237	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T182	1		T326	1		T327	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T316	1		T48	2		T324	2
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T17	1		T328	2		T326	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	14	1			T73	1		T238	1		T285	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T45	1		T245	1		T326	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	14	1			T1	1		T17	1		T181	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T243	1		T329	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	13	1			T294	1		T330	1		T331	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T3	1		T70	1		T39	1
auto[6]	auto[StDisabled]	auto[OpGenId]	35	1			T3	1		T17	1		T39	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T17	1		T39	1		T4	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	96	1			T14	1		T17	2		T19	1
auto[6]	auto[StDisabled]	auto[OpDisable]	10	1			T4	1		T317	1		T332	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T33	1		T184	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T203	1		T258	2		T319	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T320	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T62	1		T319	1		T333	1
auto[7]	auto[StReset]	auto[OpGenId]	7	1			T4	1		T334	1		T335	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T20	1		T131	1		T336	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	20	1			T285	1		T271	1		T278	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T222	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	3	1			T44	1		T55	1		T337	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T45	1		T40	1		T337	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T130	1		T338	1		T331	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T102	1		T313	1		T339	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T243	1		T57	1		T340	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T102	1		T328	1		T131	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T72	1		T341	1		T294	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T17	1		T41	1		T342	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T39	2		T76	1		T254	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T41	1		T118	1		T339	2
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T125	1		T245	1		T343	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T344	1		T292	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	9	1			T345	1		T215	2		T346	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T44	1		T40	1		T57	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T205	1		T212	1		T41	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	9	1			T347	1		T215	1		T58	1
auto[7]	auto[StDisabled]	auto[OpGenId]	24	1			T17	1		T208	1		T45	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	17	1			T197	1		T45	1		T348	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T197	1		T305	1		T349	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T132	1		T57	1		T222	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T33	1		T198	1		T206	1
auto[7]	auto[StInvalid]	auto[OpGenId]	2	1			T259	1		T350	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T198	1		T195	1		T89	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T351	1		T256	1		T283	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1367

1

T1

3

T2

4

T3

6

clear_one[1]

auto[0]

auto[0]

auto[0]

399

1

T1

1

T3

2

T17

6

clear_one[1]

auto[0]

auto[0]

auto[1]

133

1

T3

4

T17

1

T73

3

clear_one[1]

auto[0]

auto[1]

auto[0]

107

1

T3

1

T14

1

T70

1

clear_one[1]

auto[0]

auto[1]

auto[1]

33

1

T16

1

T17

1

T65

1

clear_one[2]

auto[0]

auto[0]

auto[0]

381

1

T2

1

T3

5

T13

2

clear_one[2]

auto[0]

auto[0]

auto[1]

128

1

T210

2

T39

1

T237

1

clear_one[2]

auto[1]

auto[0]

auto[0]

118

1

T3

3

T17

1

T19

1

clear_one[2]

auto[1]

auto[0]

auto[1]

57

1

T3

1

T17

2

T72

1

clear_one[3]

auto[0]

auto[0]

auto[0]

397

1

T1

1

T2

3

T3

8

clear_one[3]

auto[0]

auto[1]

auto[0]

117

1

T3

2

T14

1

T196

1

clear_one[3]

auto[1]

auto[0]

auto[0]

112

1

T17

1

T19

1

T39

1

clear_one[3]

auto[1]

auto[1]

auto[0]

48

1

T17

4

T39

3

T4

1

clear_none

auto[0]

auto[0]

auto[0]

1305

1

T1

1

T2

5

T3

14

clear_none

auto[0]

auto[0]

auto[1]

132

1

T16

1

T17

1

T73

1

clear_none

auto[0]

auto[1]

auto[0]

119

1

T3

1

T14

1

T199

1

clear_none

auto[0]

auto[1]

auto[1]

30

1

T17

1

T208

1

T39

1

clear_none

auto[1]

auto[0]

auto[0]

118

1

T2

1

T17

2

T19

2

clear_none

auto[1]

auto[0]

auto[1]

39

1

T70

2

T4

1

T45

2

clear_none

auto[1]

auto[1]

auto[0]

45

1

T3

1

T17

1

T236

1

clear_none

auto[1]

auto[1]

auto[1]

24

1

T4

1

T65

1

T282

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1288	1			T1	3		T2	3		T3	6
clear_all	auto[1]	79	1			T2	1		T70	1		T142	6
clear_one[1]	auto[0]	632	1			T1	1		T3	7		T14	1
clear_one[1]	auto[1]	40	1			T70	2		T109	5		T260	3
clear_one[2]	auto[0]	634	1			T2	1		T3	9		T13	2
clear_one[2]	auto[1]	50	1			T142	1		T268	4		T260	5
clear_one[3]	auto[0]	633	1			T1	1		T2	2		T3	10
clear_one[3]	auto[1]	41	1			T2	1		T277	7		T130	1
clear_none	auto[0]	1732	1			T1	1		T2	4		T3	16
clear_none	auto[1]	80	1			T2	2		T70	1		T109	4