Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11285

1

T1

16

T2

26

T3

135

auto[Attestation]

8147

1

T1

14

T2

13

T3

82

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2875	1			T1	4		T2	3		T3	40
auto[Aes]	3429	1			T1	2		T2	11		T3	30
auto[Kmac]	3524	1			T1	4		T2	6		T3	27
auto[Otbn]	3595	1			T1	7		T2	7		T3	38

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7975	1			T1	8		T2	8		T3	98
auto[OpGenId]	6009	1			T1	13		T2	12		T3	82
auto[OpGenSwOut]	6207	1			T1	12		T2	16		T3	68
auto[OpGenHwOut]	7216	1			T1	5		T2	11		T3	67
auto[OpDisable]	138	1			T3	1		T17	1		T18	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10356

1

T1

11

T2

12

T3

114

auto[OpDoneFail]

17189

1

T1

27

T2

35

T3

202

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6097	1			T1	6		T2	15		T3	71
auto[StInit]	4492	1			T1	23		T2	6		T3	28
auto[StCreatorRootKey]	3082	1			T1	2		T2	2		T3	37
auto[StOwnerIntKey]	2759	1			T1	3		T2	5		T3	32
auto[StOwnerKey]	2373	1			T1	4		T2	3		T3	33
auto[StDisabled]	7812	1			T2	16		T3	115		T14	7
auto[StInvalid]	930	1			T13	24		T33	12		T62	22

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	298	1			T3	4		T17	7		T20	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	111	1			T1	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	89	1			T3	2		T41	3		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	60	1			T3	1		T17	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	67	1			T194	1		T39	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	224	1			T3	4		T17	3		T71	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	28	1			T13	1		T184	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	293	1			T2	2		T3	3		T17	5
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T1	1		T3	1		T17	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T17	3		T72	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	61	1			T3	1		T196	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T3	2		T17	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	204	1			T2	2		T3	7		T17	6
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T13	2		T62	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	305	1			T2	1		T3	2		T17	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	119	1			T1	1		T15	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	90	1			T3	1		T17	2		T72	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	70	1			T3	2		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	44	1			T3	1		T39	2		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	247	1			T3	3		T17	3		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	35	1			T13	2		T62	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	337	1			T2	1		T3	7		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	130	1			T1	1		T2	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T3	2		T17	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	62	1			T2	1		T15	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	68	1			T17	1		T70	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	215	1			T2	2		T3	3		T17	7
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	24	1			T123	2		T200	1		T184	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	74	1			T17	1		T39	3		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	137	1			T1	1		T3	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	85	1			T3	1		T17	2		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	92	1			T3	2		T17	3		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T17	1		T201	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	209	1			T3	2		T17	6		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	25	1			T33	2		T123	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	89	1			T3	1		T17	2		T39	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	124	1			T1	1		T3	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	91	1			T3	1		T17	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	79	1			T15	1		T16	1		T17	7
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	57	1			T2	1		T3	2		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	183	1			T2	1		T17	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	28	1			T13	1		T62	2		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	60	1			T17	5		T4	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	139	1			T1	2		T2	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	66	1			T17	1		T70	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	77	1			T2	1		T17	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	60	1			T1	1		T3	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	202	1			T2	1		T3	2		T17	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	34	1			T62	1		T46	3		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	84	1			T3	2		T17	2		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	136	1			T1	3		T2	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T3	1		T16	1		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T3	1		T17	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T49	1		T41	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	213	1			T3	3		T17	2		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	34	1			T13	2		T33	1		T62	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	257	1			T3	2		T17	7		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	108	1			T1	2		T3	3		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T3	2		T205	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T3	1		T52	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	46	1			T17	1		T196	1		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	169	1			T3	6		T17	3		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	20	1			T62	2		T123	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	429	1			T2	2		T3	1		T17	5
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	147	1			T3	1		T17	3		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	94	1			T17	1		T19	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	104	1			T15	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	85	1			T3	1		T17	2		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	266	1			T2	1		T3	3		T17	6
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T62	2		T46	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	444	1			T2	1		T3	3		T14	6
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	152	1			T17	3		T207	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T3	2		T17	3		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T14	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	78	1			T14	1		T199	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	297	1			T3	2		T14	3		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	24	1			T200	1		T184	2		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	471	1			T2	1		T3	4		T17	6
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	132	1			T1	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T3	1		T17	2		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	113	1			T3	1		T15	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	87	1			T1	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	304	1			T3	5		T17	9		T73	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	29	1			T33	1		T62	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	56	1			T17	1		T39	3		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	125	1			T17	1		T208	2		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	83	1			T3	2		T17	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T3	2		T15	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T3	2		T39	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	177	1			T2	3		T3	2		T17	7
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	25	1			T13	1		T62	1		T200	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	49	1			T17	1		T39	1		T62	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	140	1			T17	1		T199	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T2	1		T17	4		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	99	1			T2	1		T3	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T3	1		T19	1		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	285	1			T3	3		T17	3		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	23	1			T13	1		T62	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	43	1			T4	2		T211	1		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	151	1			T2	1		T3	3		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T3	1		T14	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	99	1			T16	1		T39	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	72	1			T4	1		T67	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	274	1			T3	4		T14	1		T17	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	29	1			T13	3		T62	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	48	1			T3	5		T4	1		T62	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T17	2		T38	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T16	2		T17	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T17	1		T73	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	91	1			T1	1		T17	2		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	262	1			T3	2		T17	4		T73	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	29	1			T13	1		T62	1		T123	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	200	1			T3	3		T17	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	677	1			T1	1		T3	9		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	181	1			T3	3		T17	4		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	662	1			T1	1		T2	4		T3	11
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	181	1			T3	3		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	729	1			T1	1		T2	1		T3	6
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T2	1		T3	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	718	1			T1	1		T2	4		T3	11
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	224	1			T3	3		T17	6		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	461	1			T1	1		T3	3		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	197	1			T2	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	454	1			T1	1		T2	1		T3	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	183	1			T1	1		T2	1		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	455	1			T1	2		T2	2		T3	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	207	1			T3	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	485	1			T1	3		T2	1		T3	6
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	163	1			T3	1		T17	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	567	1			T1	2		T3	13		T17	11
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	272	1			T3	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	885	1			T2	3		T3	5		T17	14
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	274	1			T3	2		T14	2		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	932	1			T2	1		T3	5		T14	9
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T1	1		T3	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	950	1			T1	1		T2	1		T3	11
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	184	1			T3	3		T15	1		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	399	1			T2	3		T3	5		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	260	1			T2	2		T3	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	518	1			T3	4		T13	1		T17	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	258	1			T3	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	512	1			T2	1		T3	7		T13	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	298	1			T1	1		T16	2		T17	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	471	1			T3	7		T13	1		T17	6