Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31627

1

T1

43

T2

54

T3

361

auto[1]

304

1

T2

11

T70

3

T109

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31638	1			T1	43		T2	54		T3	361
auto[134217728:268435455]	7	1			T2	1		T275	1		T339	1
auto[268435456:402653183]	8	1			T2	1		T326	2		T377	1
auto[402653184:536870911]	8	1			T109	2		T260	1		T326	1
auto[536870912:671088639]	6	1			T2	1		T268	1		T326	1
auto[671088640:805306367]	6	1			T2	1		T324	1		T266	1
auto[805306368:939524095]	5	1			T2	1		T328	1		T378	1
auto[939524096:1073741823]	9	1			T2	1		T133	1		T275	1
auto[1073741824:1207959551]	5	1			T266	1		T100	1		T377	1
auto[1207959552:1342177279]	14	1			T2	2		T315	1		T324	1
auto[1342177280:1476395007]	4	1			T2	1		T277	1		T308	1
auto[1476395008:1610612735]	12	1			T268	2		T260	1		T130	1
auto[1610612736:1744830463]	14	1			T277	1		T324	1		T266	1
auto[1744830464:1879048191]	7	1			T130	1		T315	1		T324	1
auto[1879048192:2013265919]	21	1			T70	1		T109	1		T268	1
auto[2013265920:2147483647]	14	1			T268	1		T363	2		T266	1
auto[2147483648:2281701375]	10	1			T363	1		T133	1		T289	1
auto[2281701376:2415919103]	14	1			T2	1		T142	1		T328	1
auto[2415919104:2550136831]	7	1			T109	1		T326	1		T275	2
auto[2550136832:2684354559]	5	1			T266	1		T275	2		T339	1
auto[2684354560:2818572287]	7	1			T268	1		T266	1		T379	1
auto[2818572288:2952790015]	7	1			T277	2		T324	1		T275	2
auto[2952790016:3087007743]	12	1			T277	1		T315	3		T266	1
auto[3087007744:3221225471]	11	1			T129	1		T324	1		T266	1
auto[3221225472:3355443199]	9	1			T109	1		T277	1		T328	1
auto[3355443200:3489660927]	12	1			T277	1		T260	1		T326	1
auto[3489660928:3623878655]	12	1			T142	1		T315	1		T269	1
auto[3623878656:3758096383]	11	1			T109	1		T315	1		T289	1
auto[3758096384:3892314111]	7	1			T2	1		T142	1		T268	1
auto[3892314112:4026531839]	10	1			T70	1		T260	1		T100	1
auto[4026531840:4160749567]	12	1			T109	2		T269	1		T133	1
auto[4160749568:4294967295]	7	1			T109	1		T142	1		T277	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31627	1			T1	43		T2	54		T3	361
auto[0:134217727]	auto[1]	11	1			T70	1		T142	1		T266	2
auto[134217728:268435455]	auto[1]	7	1			T2	1		T275	1		T339	1
auto[268435456:402653183]	auto[1]	8	1			T2	1		T326	2		T377	1
auto[402653184:536870911]	auto[1]	8	1			T109	2		T260	1		T326	1
auto[536870912:671088639]	auto[1]	6	1			T2	1		T268	1		T326	1
auto[671088640:805306367]	auto[1]	6	1			T2	1		T324	1		T266	1
auto[805306368:939524095]	auto[1]	5	1			T2	1		T328	1		T378	1
auto[939524096:1073741823]	auto[1]	9	1			T2	1		T133	1		T275	1
auto[1073741824:1207959551]	auto[1]	5	1			T266	1		T100	1		T377	1
auto[1207959552:1342177279]	auto[1]	14	1			T2	2		T315	1		T324	1
auto[1342177280:1476395007]	auto[1]	4	1			T2	1		T277	1		T308	1
auto[1476395008:1610612735]	auto[1]	12	1			T268	2		T260	1		T130	1
auto[1610612736:1744830463]	auto[1]	14	1			T277	1		T324	1		T266	1
auto[1744830464:1879048191]	auto[1]	7	1			T130	1		T315	1		T324	1
auto[1879048192:2013265919]	auto[1]	21	1			T70	1		T109	1		T268	1
auto[2013265920:2147483647]	auto[1]	14	1			T268	1		T363	2		T266	1
auto[2147483648:2281701375]	auto[1]	10	1			T363	1		T133	1		T289	1
auto[2281701376:2415919103]	auto[1]	14	1			T2	1		T142	1		T328	1
auto[2415919104:2550136831]	auto[1]	7	1			T109	1		T326	1		T275	2
auto[2550136832:2684354559]	auto[1]	5	1			T266	1		T275	2		T339	1
auto[2684354560:2818572287]	auto[1]	7	1			T268	1		T266	1		T379	1
auto[2818572288:2952790015]	auto[1]	7	1			T277	2		T324	1		T275	2
auto[2952790016:3087007743]	auto[1]	12	1			T277	1		T315	3		T266	1
auto[3087007744:3221225471]	auto[1]	11	1			T129	1		T324	1		T266	1
auto[3221225472:3355443199]	auto[1]	9	1			T109	1		T277	1		T328	1
auto[3355443200:3489660927]	auto[1]	12	1			T277	1		T260	1		T326	1
auto[3489660928:3623878655]	auto[1]	12	1			T142	1		T315	1		T269	1
auto[3623878656:3758096383]	auto[1]	11	1			T109	1		T315	1		T289	1
auto[3758096384:3892314111]	auto[1]	7	1			T2	1		T142	1		T268	1
auto[3892314112:4026531839]	auto[1]	10	1			T70	1		T260	1		T100	1
auto[4026531840:4160749567]	auto[1]	12	1			T109	2		T269	1		T133	1
auto[4160749568:4294967295]	auto[1]	7	1			T109	1		T142	1		T277	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1552

1

T2

4

T3

13

T13

2

auto[1]

1742

1

T1

5

T2

2

T3

12

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T3	1		T17	3		T33	1
auto[134217728:268435455]	108	1			T3	1		T70	1		T199	1
auto[268435456:402653183]	94	1			T3	2		T38	1		T4	1
auto[402653184:536870911]	107	1			T1	1		T17	1		T70	1
auto[536870912:671088639]	114	1			T1	1		T20	1		T72	1
auto[671088640:805306367]	105	1			T3	1		T17	1		T72	1
auto[805306368:939524095]	97	1			T3	1		T17	3		T39	2
auto[939524096:1073741823]	112	1			T3	2		T17	1		T199	1
auto[1073741824:1207959551]	107	1			T3	1		T17	3		T208	1
auto[1207959552:1342177279]	90	1			T17	1		T208	1		T38	1
auto[1342177280:1476395007]	119	1			T2	1		T3	1		T17	1
auto[1476395008:1610612735]	100	1			T2	1		T16	1		T17	2
auto[1610612736:1744830463]	89	1			T3	1		T13	2		T17	2
auto[1744830464:1879048191]	109	1			T3	1		T17	4		T208	1
auto[1879048192:2013265919]	99	1			T1	1		T3	1		T13	1
auto[2013265920:2147483647]	103	1			T2	1		T17	3		T20	1
auto[2147483648:2281701375]	111	1			T2	1		T3	1		T17	2
auto[2281701376:2415919103]	106	1			T3	1		T17	1		T4	2
auto[2415919104:2550136831]	90	1			T17	1		T43	1		T33	1
auto[2550136832:2684354559]	90	1			T3	1		T17	1		T43	1
auto[2684354560:2818572287]	99	1			T3	1		T13	1		T17	1
auto[2818572288:2952790015]	110	1			T3	1		T17	2		T27	2
auto[2952790016:3087007743]	110	1			T17	2		T72	1		T38	2
auto[3087007744:3221225471]	88	1			T2	1		T13	1		T15	1
auto[3221225472:3355443199]	97	1			T3	1		T17	2		T38	1
auto[3355443200:3489660927]	105	1			T3	1		T17	1		T4	3
auto[3489660928:3623878655]	114	1			T3	1		T17	2		T70	1
auto[3623878656:3758096383]	94	1			T1	1		T2	1		T17	3
auto[3758096384:3892314111]	115	1			T3	1		T16	1		T17	1
auto[3892314112:4026531839]	93	1			T1	1		T3	2		T17	2
auto[4026531840:4160749567]	114	1			T17	2		T72	1		T39	4
auto[4160749568:4294967295]	106	1			T3	1		T16	1		T17	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T33	1		T39	1		T6	1
auto[0:134217727]	auto[1]	53	1			T3	1		T17	3		T279	1
auto[134217728:268435455]	auto[0]	54	1			T70	1		T39	1		T4	1
auto[134217728:268435455]	auto[1]	54	1			T3	1		T199	1		T52	1
auto[268435456:402653183]	auto[0]	44	1			T38	1		T4	1		T45	1
auto[268435456:402653183]	auto[1]	50	1			T3	2		T65	1		T237	1
auto[402653184:536870911]	auto[0]	46	1			T70	1		T72	1		T7	1
auto[402653184:536870911]	auto[1]	61	1			T1	1		T17	1		T4	1
auto[536870912:671088639]	auto[0]	51	1			T72	1		T4	1		T41	1
auto[536870912:671088639]	auto[1]	63	1			T1	1		T20	1		T4	1
auto[671088640:805306367]	auto[0]	50	1			T3	1		T17	1		T24	1
auto[671088640:805306367]	auto[1]	55	1			T72	1		T4	1		T45	1
auto[805306368:939524095]	auto[0]	46	1			T3	1		T17	1		T39	1
auto[805306368:939524095]	auto[1]	51	1			T17	2		T39	1		T4	1
auto[939524096:1073741823]	auto[0]	54	1			T3	1		T17	1		T199	1
auto[939524096:1073741823]	auto[1]	58	1			T3	1		T208	1		T52	1
auto[1073741824:1207959551]	auto[0]	44	1			T17	1		T142	1		T41	1
auto[1073741824:1207959551]	auto[1]	63	1			T3	1		T17	2		T208	1
auto[1207959552:1342177279]	auto[0]	41	1			T39	1		T24	1		T348	1
auto[1207959552:1342177279]	auto[1]	49	1			T17	1		T208	1		T38	1
auto[1342177280:1476395007]	auto[0]	54	1			T2	1		T3	1		T17	1
auto[1342177280:1476395007]	auto[1]	65	1			T43	1		T196	1		T4	1
auto[1476395008:1610612735]	auto[0]	52	1			T16	1		T17	2		T70	1
auto[1476395008:1610612735]	auto[1]	48	1			T2	1		T39	1		T4	1
auto[1610612736:1744830463]	auto[0]	37	1			T3	1		T13	1		T17	1
auto[1610612736:1744830463]	auto[1]	52	1			T13	1		T17	1		T4	1
auto[1744830464:1879048191]	auto[0]	52	1			T3	1		T38	1		T24	1
auto[1744830464:1879048191]	auto[1]	57	1			T17	4		T208	1		T27	1
auto[1879048192:2013265919]	auto[0]	46	1			T3	1		T70	1		T38	1
auto[1879048192:2013265919]	auto[1]	53	1			T1	1		T13	1		T16	1
auto[2013265920:2147483647]	auto[0]	56	1			T2	1		T17	2		T20	1
auto[2013265920:2147483647]	auto[1]	47	1			T17	1		T65	1		T142	1
auto[2147483648:2281701375]	auto[0]	52	1			T2	1		T3	1		T17	1
auto[2147483648:2281701375]	auto[1]	59	1			T17	1		T4	2		T86	1
auto[2281701376:2415919103]	auto[0]	51	1			T45	1		T348	1		T41	2
auto[2281701376:2415919103]	auto[1]	55	1			T3	1		T17	1		T4	2
auto[2415919104:2550136831]	auto[0]	43	1			T17	1		T43	1		T33	1
auto[2415919104:2550136831]	auto[1]	47	1			T39	1		T4	1		T41	1
auto[2550136832:2684354559]	auto[0]	33	1			T39	1		T4	1		T41	1
auto[2550136832:2684354559]	auto[1]	57	1			T3	1		T17	1		T43	1
auto[2684354560:2818572287]	auto[0]	44	1			T3	1		T62	1		T46	1
auto[2684354560:2818572287]	auto[1]	55	1			T13	1		T17	1		T62	1
auto[2818572288:2952790015]	auto[0]	54	1			T3	1		T39	1		T4	1
auto[2818572288:2952790015]	auto[1]	56	1			T17	2		T27	2		T39	1
auto[2952790016:3087007743]	auto[0]	52	1			T38	1		T4	1		T237	1
auto[2952790016:3087007743]	auto[1]	58	1			T17	2		T72	1		T38	1
auto[3087007744:3221225471]	auto[0]	48	1			T2	1		T13	1		T17	2
auto[3087007744:3221225471]	auto[1]	40	1			T15	1		T17	2		T64	2
auto[3221225472:3355443199]	auto[0]	48	1			T3	1		T38	1		T66	1
auto[3221225472:3355443199]	auto[1]	49	1			T17	2		T46	1		T41	3
auto[3355443200:3489660927]	auto[0]	49	1			T17	1		T4	2		T62	1
auto[3355443200:3489660927]	auto[1]	56	1			T3	1		T4	1		T348	1
auto[3489660928:3623878655]	auto[0]	57	1			T17	1		T70	1		T199	1
auto[3489660928:3623878655]	auto[1]	57	1			T3	1		T17	1		T208	1
auto[3623878656:3758096383]	auto[0]	40	1			T17	1		T33	1		T4	1
auto[3623878656:3758096383]	auto[1]	54	1			T1	1		T2	1		T17	2
auto[3758096384:3892314111]	auto[0]	55	1			T16	1		T4	2		T45	2
auto[3758096384:3892314111]	auto[1]	60	1			T3	1		T17	1		T39	1
auto[3892314112:4026531839]	auto[0]	38	1			T3	1		T279	1		T209	1
auto[3892314112:4026531839]	auto[1]	55	1			T1	1		T3	1		T17	2
auto[4026531840:4160749567]	auto[0]	63	1			T17	1		T39	1		T46	1
auto[4026531840:4160749567]	auto[1]	51	1			T17	1		T72	1		T39	3
auto[4160749568:4294967295]	auto[0]	52	1			T3	1		T16	1		T17	1
auto[4160749568:4294967295]	auto[1]	54	1			T17	2		T52	1		T39	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1557

1

T2

3

T3

11

T13

1

auto[1]

1737

1

T1

5

T2

3

T3

14

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	124	1			T1	1		T3	2		T17	2
auto[134217728:268435455]	100	1			T3	2		T17	2		T208	1
auto[268435456:402653183]	104	1			T3	2		T13	1		T17	3
auto[402653184:536870911]	101	1			T20	1		T27	1		T45	2
auto[536870912:671088639]	105	1			T2	1		T3	1		T17	1
auto[671088640:805306367]	112	1			T1	1		T2	1		T13	2
auto[805306368:939524095]	102	1			T3	1		T17	1		T4	2
auto[939524096:1073741823]	110	1			T3	1		T17	3		T39	1
auto[1073741824:1207959551]	104	1			T3	1		T39	2		T24	1
auto[1207959552:1342177279]	116	1			T3	1		T17	4		T43	1
auto[1342177280:1476395007]	97	1			T2	1		T3	2		T27	1
auto[1476395008:1610612735]	102	1			T16	1		T199	1		T33	1
auto[1610612736:1744830463]	98	1			T13	1		T17	2		T70	1
auto[1744830464:1879048191]	99	1			T2	1		T17	4		T64	1
auto[1879048192:2013265919]	110	1			T3	1		T16	1		T17	4
auto[2013265920:2147483647]	113	1			T17	1		T70	1		T39	1
auto[2147483648:2281701375]	90	1			T1	1		T3	1		T17	1
auto[2281701376:2415919103]	82	1			T3	2		T17	2		T70	1
auto[2415919104:2550136831]	100	1			T1	1		T17	4		T20	2
auto[2550136832:2684354559]	107	1			T3	1		T17	1		T39	1
auto[2684354560:2818572287]	102	1			T3	1		T17	1		T70	1
auto[2818572288:2952790015]	111	1			T3	1		T13	1		T15	1
auto[2952790016:3087007743]	107	1			T17	2		T52	1		T43	1
auto[3087007744:3221225471]	100	1			T3	1		T17	1		T52	1
auto[3221225472:3355443199]	94	1			T17	2		T38	1		T4	1
auto[3355443200:3489660927]	96	1			T1	1		T17	2		T72	2
auto[3489660928:3623878655]	110	1			T2	1		T3	1		T17	1
auto[3623878656:3758096383]	107	1			T3	1		T208	1		T38	1
auto[3758096384:3892314111]	76	1			T17	1		T38	1		T65	1
auto[3892314112:4026531839]	113	1			T16	1		T17	4		T199	1
auto[4026531840:4160749567]	103	1			T17	2		T208	1		T52	1
auto[4160749568:4294967295]	99	1			T2	1		T3	2		T17	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T3	1		T17	2		T39	1
auto[0:134217727]	auto[1]	72	1			T1	1		T3	1		T196	1
auto[134217728:268435455]	auto[0]	46	1			T38	1		T62	1		T25	1
auto[134217728:268435455]	auto[1]	54	1			T3	2		T17	2		T208	1
auto[268435456:402653183]	auto[0]	49	1			T3	1		T17	1		T33	1
auto[268435456:402653183]	auto[1]	55	1			T3	1		T13	1		T17	2
auto[402653184:536870911]	auto[0]	49	1			T202	1		T29	1		T78	1
auto[402653184:536870911]	auto[1]	52	1			T20	1		T27	1		T45	2
auto[536870912:671088639]	auto[0]	51	1			T2	1		T17	1		T4	1
auto[536870912:671088639]	auto[1]	54	1			T3	1		T43	1		T39	1
auto[671088640:805306367]	auto[0]	63	1			T13	1		T16	1		T17	1
auto[671088640:805306367]	auto[1]	49	1			T1	1		T2	1		T13	1
auto[805306368:939524095]	auto[0]	45	1			T17	1		T4	1		T237	1
auto[805306368:939524095]	auto[1]	57	1			T3	1		T4	1		T41	2
auto[939524096:1073741823]	auto[0]	47	1			T17	1		T39	1		T24	2
auto[939524096:1073741823]	auto[1]	63	1			T3	1		T17	2		T4	3
auto[1073741824:1207959551]	auto[0]	50	1			T3	1		T39	1		T24	1
auto[1073741824:1207959551]	auto[1]	54	1			T39	1		T45	2		T240	1
auto[1207959552:1342177279]	auto[0]	49	1			T17	1		T4	1		T62	1
auto[1207959552:1342177279]	auto[1]	67	1			T3	1		T17	3		T43	1
auto[1342177280:1476395007]	auto[0]	49	1			T2	1		T3	1		T4	2
auto[1342177280:1476395007]	auto[1]	48	1			T3	1		T27	1		T62	1
auto[1476395008:1610612735]	auto[0]	54	1			T33	1		T65	1		T45	1
auto[1476395008:1610612735]	auto[1]	48	1			T16	1		T199	1		T4	1
auto[1610612736:1744830463]	auto[0]	51	1			T70	1		T39	1		T41	2
auto[1610612736:1744830463]	auto[1]	47	1			T13	1		T17	2		T208	1
auto[1744830464:1879048191]	auto[0]	42	1			T200	1		T365	1		T44	2
auto[1744830464:1879048191]	auto[1]	57	1			T2	1		T17	4		T64	1
auto[1879048192:2013265919]	auto[0]	63	1			T16	1		T17	2		T38	1
auto[1879048192:2013265919]	auto[1]	47	1			T3	1		T17	2		T27	1
auto[2013265920:2147483647]	auto[0]	58	1			T41	1		T5	1		T76	1
auto[2013265920:2147483647]	auto[1]	55	1			T17	1		T70	1		T39	1
auto[2147483648:2281701375]	auto[0]	42	1			T4	1		T45	1		T348	1
auto[2147483648:2281701375]	auto[1]	48	1			T1	1		T3	1		T17	1
auto[2281701376:2415919103]	auto[0]	36	1			T3	1		T72	1		T45	1
auto[2281701376:2415919103]	auto[1]	46	1			T3	1		T17	2		T70	1
auto[2415919104:2550136831]	auto[0]	41	1			T20	2		T39	1		T4	1
auto[2415919104:2550136831]	auto[1]	59	1			T1	1		T17	4		T208	1
auto[2550136832:2684354559]	auto[0]	45	1			T3	1		T17	1		T4	1
auto[2550136832:2684354559]	auto[1]	62	1			T39	1		T62	1		T142	2
auto[2684354560:2818572287]	auto[0]	38	1			T3	1		T25	1		T77	1
auto[2684354560:2818572287]	auto[1]	64	1			T17	1		T70	1		T43	1
auto[2818572288:2952790015]	auto[0]	47	1			T3	1		T39	2		T7	1
auto[2818572288:2952790015]	auto[1]	64	1			T13	1		T15	1		T17	1
auto[2952790016:3087007743]	auto[0]	54	1			T17	1		T39	1		T4	1
auto[2952790016:3087007743]	auto[1]	53	1			T17	1		T52	1		T43	1
auto[3087007744:3221225471]	auto[0]	41	1			T3	1		T17	1		T39	2
auto[3087007744:3221225471]	auto[1]	59	1			T52	1		T38	1		T4	3
auto[3221225472:3355443199]	auto[0]	49	1			T38	1		T45	1		T42	1
auto[3221225472:3355443199]	auto[1]	45	1			T17	2		T4	1		T65	1
auto[3355443200:3489660927]	auto[0]	45	1			T72	1		T38	1		T39	1
auto[3355443200:3489660927]	auto[1]	51	1			T1	1		T17	2		T72	1
auto[3489660928:3623878655]	auto[0]	62	1			T2	1		T3	1		T17	1
auto[3489660928:3623878655]	auto[1]	48	1			T33	1		T4	1		T41	1
auto[3623878656:3758096383]	auto[0]	50	1			T38	1		T4	1		T24	1
auto[3623878656:3758096383]	auto[1]	57	1			T3	1		T208	1		T39	1
auto[3758096384:3892314111]	auto[0]	35	1			T17	1		T65	1		T6	1
auto[3758096384:3892314111]	auto[1]	41	1			T38	1		T45	1		T86	1
auto[3892314112:4026531839]	auto[0]	58	1			T16	1		T17	2		T199	1
auto[3892314112:4026531839]	auto[1]	55	1			T17	2		T27	1		T41	1
auto[4026531840:4160749567]	auto[0]	42	1			T17	1		T4	2		T45	1
auto[4026531840:4160749567]	auto[1]	61	1			T17	1		T208	1		T52	1
auto[4160749568:4294967295]	auto[0]	54	1			T3	1		T17	1		T70	1
auto[4160749568:4294967295]	auto[1]	45	1			T2	1		T3	1		T17	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1541

1

T1

1

T2

4

T3

13

auto[1]

1753

1

T1

4

T2

2

T3

12

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T3	2		T13	1		T16	1
auto[134217728:268435455]	104	1			T1	1		T3	2		T17	1
auto[268435456:402653183]	110	1			T38	1		T39	2		T4	1
auto[402653184:536870911]	86	1			T2	1		T3	1		T33	1
auto[536870912:671088639]	106	1			T3	1		T17	2		T72	1
auto[671088640:805306367]	115	1			T3	1		T17	1		T27	1
auto[805306368:939524095]	96	1			T17	1		T43	1		T39	1
auto[939524096:1073741823]	108	1			T3	1		T17	3		T27	1
auto[1073741824:1207959551]	111	1			T1	1		T17	2		T208	1
auto[1207959552:1342177279]	106	1			T1	1		T16	1		T17	1
auto[1342177280:1476395007]	99	1			T3	1		T17	3		T208	1
auto[1476395008:1610612735]	120	1			T3	2		T17	4		T4	1
auto[1610612736:1744830463]	113	1			T1	1		T17	1		T52	1
auto[1744830464:1879048191]	100	1			T3	1		T16	1		T17	2
auto[1879048192:2013265919]	91	1			T17	2		T208	1		T27	1
auto[2013265920:2147483647]	104	1			T3	2		T13	1		T17	1
auto[2147483648:2281701375]	105	1			T13	1		T17	5		T72	1
auto[2281701376:2415919103]	89	1			T1	1		T13	1		T17	1
auto[2415919104:2550136831]	90	1			T4	1		T24	1		T45	1
auto[2550136832:2684354559]	106	1			T2	1		T3	2		T17	1
auto[2684354560:2818572287]	98	1			T17	2		T46	1		T348	1
auto[2818572288:2952790015]	110	1			T15	1		T16	1		T199	1
auto[2952790016:3087007743]	110	1			T3	1		T13	1		T17	3
auto[3087007744:3221225471]	100	1			T2	1		T3	2		T17	2
auto[3221225472:3355443199]	99	1			T3	1		T17	2		T4	2
auto[3355443200:3489660927]	89	1			T3	1		T17	2		T199	1
auto[3489660928:3623878655]	98	1			T3	1		T17	3		T52	1
auto[3623878656:3758096383]	129	1			T2	1		T3	1		T17	1
auto[3758096384:3892314111]	108	1			T17	1		T20	1		T72	1
auto[3892314112:4026531839]	102	1			T2	1		T3	1		T17	4
auto[4026531840:4160749567]	100	1			T2	1		T3	1		T17	2
auto[4160749568:4294967295]	103	1			T17	2		T70	1		T72	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T3	1		T38	1		T348	1
auto[0:134217727]	auto[1]	42	1			T3	1		T13	1		T16	1
auto[134217728:268435455]	auto[0]	47	1			T3	1		T39	1		T4	2
auto[134217728:268435455]	auto[1]	57	1			T1	1		T3	1		T17	1
auto[268435456:402653183]	auto[0]	48	1			T38	1		T4	1		T41	2
auto[268435456:402653183]	auto[1]	62	1			T39	2		T41	2		T282	1
auto[402653184:536870911]	auto[0]	39	1			T2	1		T33	1		T348	1
auto[402653184:536870911]	auto[1]	47	1			T3	1		T46	1		T45	1
auto[536870912:671088639]	auto[0]	51	1			T3	1		T72	1		T199	1
auto[536870912:671088639]	auto[1]	55	1			T17	2		T4	1		T62	2
auto[671088640:805306367]	auto[0]	53	1			T3	1		T25	1		T45	1
auto[671088640:805306367]	auto[1]	62	1			T17	1		T27	1		T33	1
auto[805306368:939524095]	auto[0]	47	1			T4	1		T45	1		T348	1
auto[805306368:939524095]	auto[1]	49	1			T17	1		T43	1		T39	1
auto[939524096:1073741823]	auto[0]	62	1			T17	1		T24	1		T25	1
auto[939524096:1073741823]	auto[1]	46	1			T3	1		T17	2		T27	1
auto[1073741824:1207959551]	auto[0]	53	1			T17	1		T38	1		T4	1
auto[1073741824:1207959551]	auto[1]	58	1			T1	1		T17	1		T208	1
auto[1207959552:1342177279]	auto[0]	52	1			T70	1		T208	1		T39	1
auto[1207959552:1342177279]	auto[1]	54	1			T1	1		T16	1		T17	1
auto[1342177280:1476395007]	auto[0]	34	1			T38	1		T39	1		T4	1
auto[1342177280:1476395007]	auto[1]	65	1			T3	1		T17	3		T208	1
auto[1476395008:1610612735]	auto[0]	61	1			T3	1		T17	2		T62	1
auto[1476395008:1610612735]	auto[1]	59	1			T3	1		T17	2		T4	1
auto[1610612736:1744830463]	auto[0]	59	1			T66	1		T41	3		T211	1
auto[1610612736:1744830463]	auto[1]	54	1			T1	1		T17	1		T52	1
auto[1744830464:1879048191]	auto[0]	48	1			T3	1		T16	1		T70	1
auto[1744830464:1879048191]	auto[1]	52	1			T17	2		T20	1		T72	1
auto[1879048192:2013265919]	auto[0]	45	1			T17	1		T202	1		T48	2
auto[1879048192:2013265919]	auto[1]	46	1			T17	1		T208	1		T27	1
auto[2013265920:2147483647]	auto[0]	45	1			T20	1		T62	1		T65	1
auto[2013265920:2147483647]	auto[1]	59	1			T3	2		T13	1		T17	1
auto[2147483648:2281701375]	auto[0]	53	1			T13	1		T17	1		T72	1
auto[2147483648:2281701375]	auto[1]	52	1			T17	4		T4	1		T64	1
auto[2281701376:2415919103]	auto[0]	39	1			T1	1		T17	1		T4	1
auto[2281701376:2415919103]	auto[1]	50	1			T13	1		T39	1		T41	2
auto[2415919104:2550136831]	auto[0]	38	1			T4	1		T24	1		T348	1
auto[2415919104:2550136831]	auto[1]	52	1			T45	1		T142	1		T198	1
auto[2550136832:2684354559]	auto[0]	55	1			T2	1		T3	2		T17	1
auto[2550136832:2684354559]	auto[1]	51	1			T54	1		T267	1		T260	1
auto[2684354560:2818572287]	auto[0]	36	1			T348	1		T41	1		T206	1
auto[2684354560:2818572287]	auto[1]	62	1			T17	2		T46	1		T41	1
auto[2818572288:2952790015]	auto[0]	50	1			T16	1		T199	1		T65	1
auto[2818572288:2952790015]	auto[1]	60	1			T15	1		T4	2		T62	1
auto[2952790016:3087007743]	auto[0]	57	1			T3	1		T70	2		T33	1
auto[2952790016:3087007743]	auto[1]	53	1			T13	1		T17	3		T4	1
auto[3087007744:3221225471]	auto[0]	45	1			T2	1		T3	1		T38	1
auto[3087007744:3221225471]	auto[1]	55	1			T3	1		T17	2		T196	1
auto[3221225472:3355443199]	auto[0]	45	1			T3	1		T4	1		T45	1
auto[3221225472:3355443199]	auto[1]	54	1			T17	2		T4	1		T65	2
auto[3355443200:3489660927]	auto[0]	42	1			T17	1		T45	1		T44	1
auto[3355443200:3489660927]	auto[1]	47	1			T3	1		T17	1		T199	1
auto[3489660928:3623878655]	auto[0]	44	1			T4	1		T201	1		T77	1
auto[3489660928:3623878655]	auto[1]	54	1			T3	1		T17	3		T52	1
auto[3623878656:3758096383]	auto[0]	60	1			T17	1		T39	1		T24	1
auto[3623878656:3758096383]	auto[1]	69	1			T2	1		T3	1		T38	1
auto[3758096384:3892314111]	auto[0]	50	1			T20	1		T72	1		T196	1
auto[3758096384:3892314111]	auto[1]	58	1			T17	1		T33	1		T4	1
auto[3892314112:4026531839]	auto[0]	47	1			T3	1		T17	1		T62	1
auto[3892314112:4026531839]	auto[1]	55	1			T2	1		T17	3		T199	1
auto[4026531840:4160749567]	auto[0]	47	1			T2	1		T3	1		T33	1
auto[4026531840:4160749567]	auto[1]	53	1			T17	2		T27	1		T211	1
auto[4160749568:4294967295]	auto[0]	42	1			T17	1		T70	1		T38	1
auto[4160749568:4294967295]	auto[1]	61	1			T17	1		T72	1		T4	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1555

1

T2

4

T3

9

T13

2

auto[1]

1739

1

T1

5

T2

2

T3

16

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T1	1		T17	2		T33	1
auto[134217728:268435455]	98	1			T2	1		T17	3		T4	1
auto[268435456:402653183]	86	1			T3	1		T13	1		T27	1
auto[402653184:536870911]	105	1			T1	1		T3	2		T70	1
auto[536870912:671088639]	92	1			T3	1		T17	1		T52	1
auto[671088640:805306367]	110	1			T1	1		T2	1		T3	1
auto[805306368:939524095]	103	1			T13	1		T17	4		T20	1
auto[939524096:1073741823]	110	1			T2	1		T3	2		T43	1
auto[1073741824:1207959551]	118	1			T13	1		T17	3		T199	1
auto[1207959552:1342177279]	116	1			T3	1		T17	3		T20	1
auto[1342177280:1476395007]	103	1			T17	1		T43	1		T39	1
auto[1476395008:1610612735]	101	1			T3	2		T17	2		T208	1
auto[1610612736:1744830463]	111	1			T3	1		T17	3		T72	1
auto[1744830464:1879048191]	86	1			T2	1		T3	1		T16	1
auto[1879048192:2013265919]	103	1			T13	1		T17	4		T72	1
auto[2013265920:2147483647]	87	1			T17	2		T20	1		T72	1
auto[2147483648:2281701375]	89	1			T17	2		T4	2		T64	1
auto[2281701376:2415919103]	98	1			T17	1		T43	1		T27	1
auto[2415919104:2550136831]	123	1			T1	1		T16	1		T17	1
auto[2550136832:2684354559]	98	1			T3	1		T199	1		T39	1
auto[2684354560:2818572287]	112	1			T2	1		T17	4		T208	1
auto[2818572288:2952790015]	101	1			T16	1		T17	1		T38	2
auto[2952790016:3087007743]	112	1			T3	2		T17	3		T208	1
auto[3087007744:3221225471]	101	1			T1	1		T3	4		T208	1
auto[3221225472:3355443199]	108	1			T15	1		T199	1		T52	1
auto[3355443200:3489660927]	110	1			T3	1		T17	4		T70	1
auto[3489660928:3623878655]	106	1			T3	1		T16	1		T17	1
auto[3623878656:3758096383]	102	1			T2	1		T13	1		T17	1
auto[3758096384:3892314111]	92	1			T3	2		T39	1		T4	4
auto[3892314112:4026531839]	112	1			T17	2		T43	1		T196	1
auto[4026531840:4160749567]	124	1			T3	1		T17	2		T39	1
auto[4160749568:4294967295]	88	1			T3	1		T39	2		T45	1