Unified Coverage Report :: Group Instance : salt_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2869

1

T1

5

T2

6

T3

25

auto[1]

335

1

T2

11

T70

8

T109

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T17	3		T196	1		T38	1
auto[134217728:268435455]	96	1			T2	1		T3	1		T17	1
auto[268435456:402653183]	85	1			T2	2		T3	1		T17	1
auto[402653184:536870911]	100	1			T3	1		T16	1		T17	1
auto[536870912:671088639]	95	1			T2	1		T16	1		T17	2
auto[671088640:805306367]	105	1			T3	1		T16	1		T17	3
auto[805306368:939524095]	101	1			T1	1		T2	1		T13	1
auto[939524096:1073741823]	87	1			T1	2		T3	1		T17	1
auto[1073741824:1207959551]	119	1			T2	3		T3	2		T70	2
auto[1207959552:1342177279]	101	1			T1	1		T3	3		T17	4
auto[1342177280:1476395007]	85	1			T4	1		T65	1		T66	1
auto[1476395008:1610612735]	110	1			T3	1		T17	1		T199	1
auto[1610612736:1744830463]	107	1			T1	1		T2	1		T3	1
auto[1744830464:1879048191]	105	1			T3	1		T17	2		T70	1
auto[1879048192:2013265919]	95	1			T13	1		T17	3		T25	1
auto[2013265920:2147483647]	85	1			T3	1		T17	2		T4	2
auto[2147483648:2281701375]	91	1			T3	1		T17	1		T45	1
auto[2281701376:2415919103]	120	1			T2	2		T13	1		T17	2
auto[2415919104:2550136831]	98	1			T2	1		T3	1		T15	1
auto[2550136832:2684354559]	100	1			T17	1		T208	1		T52	1
auto[2684354560:2818572287]	120	1			T2	1		T17	1		T70	1
auto[2818572288:2952790015]	117	1			T2	1		T17	3		T33	1
auto[2952790016:3087007743]	118	1			T2	1		T3	1		T17	2
auto[3087007744:3221225471]	103	1			T3	1		T4	2		T64	1
auto[3221225472:3355443199]	97	1			T3	1		T17	1		T20	1
auto[3355443200:3489660927]	88	1			T3	1		T17	3		T70	1
auto[3489660928:3623878655]	97	1			T199	1		T52	1		T43	1
auto[3623878656:3758096383]	97	1			T2	1		T3	3		T16	1
auto[3758096384:3892314111]	89	1			T3	1		T17	1		T33	1
auto[3892314112:4026531839]	91	1			T13	1		T17	1		T72	1
auto[4026531840:4160749567]	93	1			T2	1		T17	3		T27	1
auto[4160749568:4294967295]	102	1			T3	1		T17	4		T20	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	100	1			T17	3		T196	1		T38	1
auto[0:134217727]	auto[1]	7	1			T268	1		T266	1		T392	1
auto[134217728:268435455]	auto[0]	82	1			T3	1		T17	1		T20	1
auto[134217728:268435455]	auto[1]	14	1			T2	1		T109	1		T277	1
auto[268435456:402653183]	auto[0]	79	1			T2	1		T3	1		T17	1
auto[268435456:402653183]	auto[1]	6	1			T2	1		T324	1		T377	1
auto[402653184:536870911]	auto[0]	92	1			T3	1		T16	1		T17	1
auto[402653184:536870911]	auto[1]	8	1			T268	1		T328	1		T133	1
auto[536870912:671088639]	auto[0]	86	1			T16	1		T17	2		T33	1
auto[536870912:671088639]	auto[1]	9	1			T2	1		T328	1		T269	1
auto[671088640:805306367]	auto[0]	92	1			T3	1		T16	1		T17	3
auto[671088640:805306367]	auto[1]	13	1			T109	2		T268	1		T326	1
auto[805306368:939524095]	auto[0]	90	1			T1	1		T13	1		T27	1
auto[805306368:939524095]	auto[1]	11	1			T2	1		T70	1		T109	1
auto[939524096:1073741823]	auto[0]	75	1			T1	2		T3	1		T17	1
auto[939524096:1073741823]	auto[1]	12	1			T260	1		T315	1		T379	1
auto[1073741824:1207959551]	auto[0]	106	1			T2	1		T3	2		T72	1
auto[1073741824:1207959551]	auto[1]	13	1			T2	2		T70	2		T142	1
auto[1207959552:1342177279]	auto[0]	87	1			T1	1		T3	3		T17	4
auto[1207959552:1342177279]	auto[1]	14	1			T109	1		T277	1		T326	1
auto[1342177280:1476395007]	auto[0]	76	1			T4	1		T65	1		T66	1
auto[1342177280:1476395007]	auto[1]	9	1			T363	1		T266	1		T133	2
auto[1476395008:1610612735]	auto[0]	102	1			T3	1		T17	1		T199	1
auto[1476395008:1610612735]	auto[1]	8	1			T315	1		T324	1		T275	1
auto[1610612736:1744830463]	auto[0]	91	1			T1	1		T3	1		T13	1
auto[1610612736:1744830463]	auto[1]	16	1			T2	1		T268	3		T277	1
auto[1744830464:1879048191]	auto[0]	100	1			T3	1		T17	2		T70	1
auto[1744830464:1879048191]	auto[1]	5	1			T130	1		T275	1		T308	1
auto[1879048192:2013265919]	auto[0]	88	1			T13	1		T17	3		T25	1
auto[1879048192:2013265919]	auto[1]	7	1			T277	1		T315	1		T363	1
auto[2013265920:2147483647]	auto[0]	76	1			T3	1		T17	2		T4	2
auto[2013265920:2147483647]	auto[1]	9	1			T266	1		T133	1		T100	1
auto[2147483648:2281701375]	auto[0]	81	1			T3	1		T17	1		T45	1
auto[2147483648:2281701375]	auto[1]	10	1			T315	2		T326	1		T289	1
auto[2281701376:2415919103]	auto[0]	104	1			T2	2		T13	1		T17	2
auto[2281701376:2415919103]	auto[1]	16	1			T70	1		T315	2		T266	1
auto[2415919104:2550136831]	auto[0]	86	1			T2	1		T3	1		T15	1
auto[2415919104:2550136831]	auto[1]	12	1			T251	1		T266	1		T133	1
auto[2550136832:2684354559]	auto[0]	87	1			T17	1		T208	1		T52	1
auto[2550136832:2684354559]	auto[1]	13	1			T109	1		T268	1		T326	1
auto[2684354560:2818572287]	auto[0]	104	1			T2	1		T17	1		T27	1
auto[2684354560:2818572287]	auto[1]	16	1			T70	1		T251	1		T324	1
auto[2818572288:2952790015]	auto[0]	111	1			T17	3		T33	1		T39	1
auto[2818572288:2952790015]	auto[1]	6	1			T2	1		T109	1		T251	1
auto[2952790016:3087007743]	auto[0]	109	1			T3	1		T17	2		T27	2
auto[2952790016:3087007743]	auto[1]	9	1			T2	1		T277	1		T260	1
auto[3087007744:3221225471]	auto[0]	87	1			T3	1		T4	2		T64	1
auto[3087007744:3221225471]	auto[1]	16	1			T109	1		T142	1		T268	1
auto[3221225472:3355443199]	auto[0]	86	1			T3	1		T17	1		T20	1
auto[3221225472:3355443199]	auto[1]	11	1			T70	1		T268	1		T277	1
auto[3355443200:3489660927]	auto[0]	77	1			T3	1		T17	3		T72	1
auto[3355443200:3489660927]	auto[1]	11	1			T70	1		T260	1		T326	1
auto[3489660928:3623878655]	auto[0]	88	1			T199	1		T52	1		T43	1
auto[3489660928:3623878655]	auto[1]	9	1			T109	1		T326	1		T269	1
auto[3623878656:3758096383]	auto[0]	90	1			T3	3		T16	1		T33	1
auto[3623878656:3758096383]	auto[1]	7	1			T2	1		T100	2		T377	1
auto[3758096384:3892314111]	auto[0]	79	1			T3	1		T17	1		T33	1
auto[3758096384:3892314111]	auto[1]	10	1			T269	1		T363	1		T379	1
auto[3892314112:4026531839]	auto[0]	85	1			T13	1		T17	1		T72	1
auto[3892314112:4026531839]	auto[1]	6	1			T363	1		T133	2		T234	1
auto[4026531840:4160749567]	auto[0]	82	1			T17	3		T27	1		T39	1
auto[4026531840:4160749567]	auto[1]	11	1			T2	1		T277	1		T328	1
auto[4160749568:4294967295]	auto[0]	91	1			T3	1		T17	4		T20	1
auto[4160749568:4294967295]	auto[1]	11	1			T70	1		T142	1		T268	1