Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6713

1

T1

13

T2

11

T3

90

auto[1]

308

1

T2

10

T70

3

T109

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2773	1			T1	7		T2	6		T3	33
auto[134217728:268435455]	176	1			T3	1		T16	1		T17	4
auto[268435456:402653183]	140	1			T2	1		T3	3		T13	1
auto[402653184:536870911]	136	1			T1	1		T2	1		T3	5
auto[536870912:671088639]	159	1			T2	2		T3	5		T17	2
auto[671088640:805306367]	163	1			T1	1		T2	1		T3	5
auto[805306368:939524095]	137	1			T2	2		T3	3		T17	3
auto[939524096:1073741823]	154	1			T2	1		T13	2		T17	4
auto[1073741824:1207959551]	133	1			T3	4		T15	1		T20	1
auto[1207959552:1342177279]	141	1			T3	2		T17	1		T196	1
auto[1342177280:1476395007]	145	1			T1	1		T2	2		T3	2
auto[1476395008:1610612735]	138	1			T1	1		T2	1		T13	1
auto[1610612736:1744830463]	147	1			T1	1		T2	1		T3	2
auto[1744830464:1879048191]	120	1			T3	1		T17	4		T72	1
auto[1879048192:2013265919]	118	1			T2	1		T3	1		T17	3
auto[2013265920:2147483647]	120	1			T17	2		T237	1		T24	1
auto[2147483648:2281701375]	143	1			T3	2		T16	1		T17	1
auto[2281701376:2415919103]	125	1			T13	1		T17	3		T70	1
auto[2415919104:2550136831]	120	1			T3	1		T17	3		T72	1
auto[2550136832:2684354559]	132	1			T3	1		T17	2		T27	1
auto[2684354560:2818572287]	141	1			T2	1		T3	1		T13	1
auto[2818572288:2952790015]	124	1			T3	1		T17	1		T72	1
auto[2952790016:3087007743]	143	1			T3	2		T17	1		T70	1
auto[3087007744:3221225471]	125	1			T3	1		T16	1		T17	1
auto[3221225472:3355443199]	137	1			T3	2		T17	4		T70	1
auto[3355443200:3489660927]	138	1			T3	1		T17	3		T199	1
auto[3489660928:3623878655]	145	1			T2	1		T3	1		T17	3
auto[3623878656:3758096383]	124	1			T1	1		T3	2		T13	1
auto[3758096384:3892314111]	137	1			T3	2		T17	1		T27	1
auto[3892314112:4026531839]	114	1			T3	2		T17	1		T39	2
auto[4026531840:4160749567]	136	1			T3	2		T17	1		T72	2
auto[4160749568:4294967295]	137	1			T3	2		T17	3		T33	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2765	1			T1	7		T2	6		T3	33
auto[0:134217727]	auto[1]	8	1			T130	1		T315	1		T363	2
auto[134217728:268435455]	auto[0]	164	1			T3	1		T16	1		T17	4
auto[134217728:268435455]	auto[1]	12	1			T142	1		T277	1		T328	1
auto[268435456:402653183]	auto[0]	131	1			T3	3		T13	1		T16	1
auto[268435456:402653183]	auto[1]	9	1			T2	1		T363	1		T378	1
auto[402653184:536870911]	auto[0]	128	1			T1	1		T2	1		T3	5
auto[402653184:536870911]	auto[1]	8	1			T142	1		T326	1		T133	1
auto[536870912:671088639]	auto[0]	144	1			T3	5		T17	2		T70	1
auto[536870912:671088639]	auto[1]	15	1			T2	2		T109	1		T142	1
auto[671088640:805306367]	auto[0]	147	1			T1	1		T2	1		T3	5
auto[671088640:805306367]	auto[1]	16	1			T268	1		T260	2		T324	1
auto[805306368:939524095]	auto[0]	129	1			T2	1		T3	3		T17	3
auto[805306368:939524095]	auto[1]	8	1			T2	1		T277	2		T269	1
auto[939524096:1073741823]	auto[0]	143	1			T13	2		T17	4		T72	1
auto[939524096:1073741823]	auto[1]	11	1			T2	1		T142	1		T328	1
auto[1073741824:1207959551]	auto[0]	121	1			T3	4		T15	1		T20	1
auto[1073741824:1207959551]	auto[1]	12	1			T142	1		T260	1		T326	1
auto[1207959552:1342177279]	auto[0]	132	1			T3	2		T17	1		T196	1
auto[1207959552:1342177279]	auto[1]	9	1			T109	2		T277	1		T326	1
auto[1342177280:1476395007]	auto[0]	138	1			T1	1		T2	1		T3	2
auto[1342177280:1476395007]	auto[1]	7	1			T2	1		T363	1		T289	1
auto[1476395008:1610612735]	auto[0]	130	1			T1	1		T13	1		T17	2
auto[1476395008:1610612735]	auto[1]	8	1			T2	1		T315	1		T133	1
auto[1610612736:1744830463]	auto[0]	137	1			T1	1		T2	1		T3	2
auto[1610612736:1744830463]	auto[1]	10	1			T268	1		T277	1		T315	1
auto[1744830464:1879048191]	auto[0]	109	1			T3	1		T17	4		T72	1
auto[1744830464:1879048191]	auto[1]	11	1			T142	1		T268	1		T269	1
auto[1879048192:2013265919]	auto[0]	108	1			T3	1		T17	3		T199	1
auto[1879048192:2013265919]	auto[1]	10	1			T2	1		T277	1		T260	1
auto[2013265920:2147483647]	auto[0]	108	1			T17	2		T237	1		T24	1
auto[2013265920:2147483647]	auto[1]	12	1			T109	1		T268	2		T260	2
auto[2147483648:2281701375]	auto[0]	130	1			T3	2		T16	1		T17	1
auto[2147483648:2281701375]	auto[1]	13	1			T268	1		T133	1		T289	1
auto[2281701376:2415919103]	auto[0]	118	1			T13	1		T17	3		T70	1
auto[2281701376:2415919103]	auto[1]	7	1			T268	1		T260	2		T269	1
auto[2415919104:2550136831]	auto[0]	110	1			T3	1		T17	3		T72	1
auto[2415919104:2550136831]	auto[1]	10	1			T266	2		T306	1		T275	1
auto[2550136832:2684354559]	auto[0]	125	1			T3	1		T17	2		T27	1
auto[2550136832:2684354559]	auto[1]	7	1			T324	1		T133	1		T289	1
auto[2684354560:2818572287]	auto[0]	126	1			T3	1		T13	1		T17	3
auto[2684354560:2818572287]	auto[1]	15	1			T2	1		T70	3		T130	1
auto[2818572288:2952790015]	auto[0]	113	1			T3	1		T17	1		T72	1
auto[2818572288:2952790015]	auto[1]	11	1			T324	1		T266	1		T289	1
auto[2952790016:3087007743]	auto[0]	139	1			T3	2		T17	1		T70	1
auto[2952790016:3087007743]	auto[1]	4	1			T363	1		T100	1		T234	1
auto[3087007744:3221225471]	auto[0]	120	1			T3	1		T16	1		T17	1
auto[3087007744:3221225471]	auto[1]	5	1			T275	1		T378	1		T381	2
auto[3221225472:3355443199]	auto[0]	126	1			T3	2		T17	4		T70	1
auto[3221225472:3355443199]	auto[1]	11	1			T277	1		T260	1		T326	2
auto[3355443200:3489660927]	auto[0]	125	1			T3	1		T17	3		T199	1
auto[3355443200:3489660927]	auto[1]	13	1			T109	1		T326	1		T133	1
auto[3489660928:3623878655]	auto[0]	137	1			T3	1		T17	3		T39	2
auto[3489660928:3623878655]	auto[1]	8	1			T2	1		T109	1		T326	1
auto[3623878656:3758096383]	auto[0]	117	1			T1	1		T3	2		T13	1
auto[3623878656:3758096383]	auto[1]	7	1			T277	1		T324	1		T266	2
auto[3758096384:3892314111]	auto[0]	125	1			T3	2		T17	1		T27	1
auto[3758096384:3892314111]	auto[1]	12	1			T268	1		T260	1		T377	1
auto[3892314112:4026531839]	auto[0]	108	1			T3	2		T17	1		T39	2
auto[3892314112:4026531839]	auto[1]	6	1			T268	1		T277	1		T130	1
auto[4026531840:4160749567]	auto[0]	128	1			T3	2		T17	1		T72	2
auto[4026531840:4160749567]	auto[1]	8	1			T382	1		T383	1		T384	1
auto[4160749568:4294967295]	auto[0]	132	1			T3	2		T17	3		T33	2
auto[4160749568:4294967295]	auto[1]	5	1			T315	1		T363	1		T100	1