Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.85 99.07 98.06 98.66 100.00 99.11 98.41 91.61


Total test records in report: 1069
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T1007 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1996997324 Apr 16 12:40:46 PM PDT 24 Apr 16 12:40:49 PM PDT 24 9263172 ps
T1008 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4214836714 Apr 16 12:41:02 PM PDT 24 Apr 16 12:41:03 PM PDT 24 19858821 ps
T1009 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4144903839 Apr 16 12:40:51 PM PDT 24 Apr 16 12:40:54 PM PDT 24 53468847 ps
T1010 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2909735914 Apr 16 12:40:15 PM PDT 24 Apr 16 12:40:24 PM PDT 24 905221276 ps
T1011 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.270873126 Apr 16 12:40:45 PM PDT 24 Apr 16 12:40:50 PM PDT 24 306091860 ps
T1012 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1844323393 Apr 16 12:40:54 PM PDT 24 Apr 16 12:40:56 PM PDT 24 23504961 ps
T161 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2946752885 Apr 16 12:40:44 PM PDT 24 Apr 16 12:40:56 PM PDT 24 1201801971 ps
T1013 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1097782306 Apr 16 12:40:52 PM PDT 24 Apr 16 12:40:53 PM PDT 24 67119078 ps
T1014 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3571993926 Apr 16 12:40:39 PM PDT 24 Apr 16 12:40:45 PM PDT 24 1214622684 ps
T1015 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2009115529 Apr 16 12:40:39 PM PDT 24 Apr 16 12:40:46 PM PDT 24 153130012 ps
T1016 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2236008450 Apr 16 12:40:14 PM PDT 24 Apr 16 12:40:16 PM PDT 24 20704517 ps
T1017 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3873689176 Apr 16 12:40:47 PM PDT 24 Apr 16 12:40:51 PM PDT 24 148640896 ps
T1018 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2984581827 Apr 16 12:40:36 PM PDT 24 Apr 16 12:40:38 PM PDT 24 30249247 ps
T1019 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1419403545 Apr 16 12:40:44 PM PDT 24 Apr 16 12:40:48 PM PDT 24 387017266 ps
T1020 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3109541500 Apr 16 12:40:33 PM PDT 24 Apr 16 12:40:38 PM PDT 24 158047921 ps
T1021 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2897211037 Apr 16 12:40:55 PM PDT 24 Apr 16 12:40:56 PM PDT 24 33222648 ps
T155 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3719647053 Apr 16 12:40:26 PM PDT 24 Apr 16 12:40:39 PM PDT 24 4111554935 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2220186846 Apr 16 12:40:24 PM PDT 24 Apr 16 12:40:25 PM PDT 24 58660123 ps
T1023 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.983072703 Apr 16 12:40:25 PM PDT 24 Apr 16 12:40:33 PM PDT 24 509025559 ps
T1024 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.174155128 Apr 16 12:40:21 PM PDT 24 Apr 16 12:40:38 PM PDT 24 893521412 ps
T1025 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.193427866 Apr 16 12:40:39 PM PDT 24 Apr 16 12:40:43 PM PDT 24 100864843 ps
T1026 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3183561823 Apr 16 12:40:48 PM PDT 24 Apr 16 12:41:06 PM PDT 24 543164368 ps
T1027 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1449227964 Apr 16 12:40:46 PM PDT 24 Apr 16 12:40:48 PM PDT 24 17189887 ps
T1028 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1480447295 Apr 16 12:40:40 PM PDT 24 Apr 16 12:40:43 PM PDT 24 38909203 ps
T1029 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.840397710 Apr 16 12:40:36 PM PDT 24 Apr 16 12:40:38 PM PDT 24 19298556 ps
T1030 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.175025171 Apr 16 12:40:45 PM PDT 24 Apr 16 12:40:48 PM PDT 24 103790897 ps
T1031 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.267214521 Apr 16 12:40:21 PM PDT 24 Apr 16 12:40:22 PM PDT 24 11418415 ps
T1032 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4235278252 Apr 16 12:40:49 PM PDT 24 Apr 16 12:40:57 PM PDT 24 661085605 ps
T1033 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3164291142 Apr 16 12:40:37 PM PDT 24 Apr 16 12:40:39 PM PDT 24 34252627 ps
T1034 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2984265107 Apr 16 12:40:55 PM PDT 24 Apr 16 12:40:57 PM PDT 24 9396755 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3477693543 Apr 16 12:40:35 PM PDT 24 Apr 16 12:40:38 PM PDT 24 150961503 ps
T156 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3681850273 Apr 16 12:40:51 PM PDT 24 Apr 16 12:40:56 PM PDT 24 228320601 ps
T1036 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2589684292 Apr 16 12:40:50 PM PDT 24 Apr 16 12:40:53 PM PDT 24 52903432 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2720109007 Apr 16 12:40:40 PM PDT 24 Apr 16 12:40:43 PM PDT 24 17411508 ps
T1038 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2698110574 Apr 16 12:40:23 PM PDT 24 Apr 16 12:40:24 PM PDT 24 30802926 ps
T1039 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.954553611 Apr 16 12:40:48 PM PDT 24 Apr 16 12:41:00 PM PDT 24 150285590 ps
T1040 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3084884944 Apr 16 12:40:48 PM PDT 24 Apr 16 12:41:03 PM PDT 24 2309515082 ps
T1041 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1752702159 Apr 16 12:40:52 PM PDT 24 Apr 16 12:41:09 PM PDT 24 1491532469 ps
T1042 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3080705237 Apr 16 12:40:45 PM PDT 24 Apr 16 12:40:50 PM PDT 24 480153049 ps
T1043 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4065747320 Apr 16 12:40:42 PM PDT 24 Apr 16 12:40:50 PM PDT 24 157253469 ps
T1044 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3766084576 Apr 16 12:40:46 PM PDT 24 Apr 16 12:40:49 PM PDT 24 55548548 ps
T1045 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1126357034 Apr 16 12:40:27 PM PDT 24 Apr 16 12:40:30 PM PDT 24 71935691 ps
T1046 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2698503032 Apr 16 12:40:21 PM PDT 24 Apr 16 12:40:23 PM PDT 24 80636958 ps
T157 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.214406034 Apr 16 12:40:38 PM PDT 24 Apr 16 12:40:46 PM PDT 24 1772206937 ps
T1047 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2805533271 Apr 16 12:40:36 PM PDT 24 Apr 16 12:40:38 PM PDT 24 240824997 ps
T1048 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1976825577 Apr 16 12:40:42 PM PDT 24 Apr 16 12:40:45 PM PDT 24 33370200 ps
T1049 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.337520241 Apr 16 12:40:52 PM PDT 24 Apr 16 12:40:54 PM PDT 24 18714181 ps
T1050 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2601208714 Apr 16 12:41:03 PM PDT 24 Apr 16 12:41:07 PM PDT 24 226590121 ps
T1051 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.422580146 Apr 16 12:40:48 PM PDT 24 Apr 16 12:40:55 PM PDT 24 489025182 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2233497131 Apr 16 12:40:29 PM PDT 24 Apr 16 12:40:31 PM PDT 24 28918852 ps
T1053 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3415787103 Apr 16 12:40:42 PM PDT 24 Apr 16 12:40:45 PM PDT 24 69031509 ps
T1054 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2480270646 Apr 16 12:40:38 PM PDT 24 Apr 16 12:40:40 PM PDT 24 11965180 ps
T1055 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1953571693 Apr 16 12:40:30 PM PDT 24 Apr 16 12:40:32 PM PDT 24 42472277 ps
T1056 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2714716935 Apr 16 12:40:47 PM PDT 24 Apr 16 12:40:50 PM PDT 24 15255285 ps
T1057 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3130049176 Apr 16 12:40:46 PM PDT 24 Apr 16 12:40:49 PM PDT 24 68179345 ps
T1058 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.140076473 Apr 16 12:40:44 PM PDT 24 Apr 16 12:40:46 PM PDT 24 14968578 ps
T1059 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2128102883 Apr 16 12:40:36 PM PDT 24 Apr 16 12:40:44 PM PDT 24 597657308 ps
T1060 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1618581661 Apr 16 12:40:40 PM PDT 24 Apr 16 12:40:43 PM PDT 24 39832016 ps
T150 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3100225211 Apr 16 12:40:44 PM PDT 24 Apr 16 12:40:54 PM PDT 24 423477477 ps
T151 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1458563600 Apr 16 12:40:26 PM PDT 24 Apr 16 12:40:36 PM PDT 24 845692590 ps
T1061 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3757984259 Apr 16 12:40:51 PM PDT 24 Apr 16 12:40:53 PM PDT 24 48681191 ps
T1062 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1338841543 Apr 16 12:40:36 PM PDT 24 Apr 16 12:40:43 PM PDT 24 353154045 ps
T1063 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.321712512 Apr 16 12:40:44 PM PDT 24 Apr 16 12:40:48 PM PDT 24 202378379 ps
T1064 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2585455276 Apr 16 12:40:47 PM PDT 24 Apr 16 12:40:49 PM PDT 24 23433192 ps
T1065 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2276701764 Apr 16 12:40:45 PM PDT 24 Apr 16 12:40:48 PM PDT 24 214303548 ps
T1066 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1661755508 Apr 16 12:40:39 PM PDT 24 Apr 16 12:40:41 PM PDT 24 39795735 ps
T1067 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.129831129 Apr 16 12:40:50 PM PDT 24 Apr 16 12:40:54 PM PDT 24 375701889 ps
T1068 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.367383327 Apr 16 12:40:37 PM PDT 24 Apr 16 12:40:40 PM PDT 24 50988162 ps
T1069 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.969199067 Apr 16 12:40:45 PM PDT 24 Apr 16 12:40:51 PM PDT 24 1049783737 ps

Test location /workspace/coverage/default/36.keymgr_stress_all.1316198339
Short name T17
Test name
Test status
Simulation time 692406543 ps
CPU time 28.97 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:46 PM PDT 24
Peak memory 222764 kb
Host smart-f8853274-728c-49e0-a84e-33ef69554177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316198339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1316198339
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1841399346
Short name T4
Test name
Test status
Simulation time 3888226573 ps
CPU time 37.18 seconds
Started Apr 16 12:45:51 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 222892 kb
Host smart-d5b55bdb-0e52-4f11-a09c-3c119966da44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841399346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1841399346
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.356163925
Short name T102
Test name
Test status
Simulation time 732612929 ps
CPU time 24.24 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:39 PM PDT 24
Peak memory 222956 kb
Host smart-9b195286-4c6f-4e78-a521-2c5737824f40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356163925 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.356163925
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.918891938
Short name T10
Test name
Test status
Simulation time 9716549876 ps
CPU time 20.73 seconds
Started Apr 16 12:44:52 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 236592 kb
Host smart-fdf78c5a-8661-4574-851c-fe85f29f56ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918891938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.918891938
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3427322242
Short name T48
Test name
Test status
Simulation time 7783159885 ps
CPU time 70.63 seconds
Started Apr 16 12:44:58 PM PDT 24
Finished Apr 16 12:46:10 PM PDT 24
Peak memory 222848 kb
Host smart-d7696dc1-9eff-4fe8-a25d-80fe36f54909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427322242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3427322242
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1766152202
Short name T62
Test name
Test status
Simulation time 79386879 ps
CPU time 3.72 seconds
Started Apr 16 12:46:07 PM PDT 24
Finished Apr 16 12:46:15 PM PDT 24
Peak memory 214524 kb
Host smart-48183c04-9341-46e1-b6a1-76215472e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766152202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1766152202
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.264569266
Short name T2
Test name
Test status
Simulation time 163856959 ps
CPU time 8.38 seconds
Started Apr 16 12:44:43 PM PDT 24
Finished Apr 16 12:44:53 PM PDT 24
Peak memory 215476 kb
Host smart-86a1ad59-faf9-4e9b-b8bf-f8e84bf330c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264569266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.264569266
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1803763649
Short name T7
Test name
Test status
Simulation time 175326439 ps
CPU time 7.49 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:11 PM PDT 24
Peak memory 222992 kb
Host smart-9ff2ff09-8209-4f63-8924-240365336e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803763649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1803763649
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3047709139
Short name T104
Test name
Test status
Simulation time 966973097 ps
CPU time 4.82 seconds
Started Apr 16 12:40:29 PM PDT 24
Finished Apr 16 12:40:35 PM PDT 24
Peak memory 214420 kb
Host smart-d6dcdddc-56a1-4ef2-88c9-a8ec9f090ac1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047709139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3047709139
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.144015381
Short name T275
Test name
Test status
Simulation time 2059452070 ps
CPU time 28.55 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:54 PM PDT 24
Peak memory 222356 kb
Host smart-b079e926-1ddc-4c08-ba38-748c6b9372d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=144015381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.144015381
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3930335228
Short name T41
Test name
Test status
Simulation time 1322732482 ps
CPU time 39.41 seconds
Started Apr 16 12:45:29 PM PDT 24
Finished Apr 16 12:46:11 PM PDT 24
Peak memory 222864 kb
Host smart-a57a8626-a545-4e24-844b-4d6610182a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930335228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3930335228
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3954586483
Short name T78
Test name
Test status
Simulation time 194395928 ps
CPU time 5.37 seconds
Started Apr 16 12:45:25 PM PDT 24
Finished Apr 16 12:45:32 PM PDT 24
Peak memory 209784 kb
Host smart-580b7583-39ac-41ce-9049-5ef04a747332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954586483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3954586483
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2769232897
Short name T117
Test name
Test status
Simulation time 13850650358 ps
CPU time 34.76 seconds
Started Apr 16 12:46:28 PM PDT 24
Finished Apr 16 12:47:05 PM PDT 24
Peak memory 232236 kb
Host smart-d74f3446-c4f5-4caa-8ac3-674216942eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769232897 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2769232897
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2391816085
Short name T277
Test name
Test status
Simulation time 139628784 ps
CPU time 7.71 seconds
Started Apr 16 12:46:19 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 215460 kb
Host smart-0d7e6ad6-eb55-45ac-a9f8-4e86f825b1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391816085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2391816085
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1803803854
Short name T70
Test name
Test status
Simulation time 203114796 ps
CPU time 3.77 seconds
Started Apr 16 12:46:09 PM PDT 24
Finished Apr 16 12:46:17 PM PDT 24
Peak memory 214608 kb
Host smart-752b5781-41d2-4c6c-af36-b2ead2112e75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803803854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1803803854
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1401357998
Short name T947
Test name
Test status
Simulation time 746481161 ps
CPU time 3.81 seconds
Started Apr 16 12:40:40 PM PDT 24
Finished Apr 16 12:40:45 PM PDT 24
Peak memory 214272 kb
Host smart-563aa0d8-1be3-4046-8712-2293b37c2657
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401357998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1401357998
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2105195425
Short name T133
Test name
Test status
Simulation time 2407068935 ps
CPU time 65.8 seconds
Started Apr 16 12:45:19 PM PDT 24
Finished Apr 16 12:46:27 PM PDT 24
Peak memory 215424 kb
Host smart-1c58f05b-07a4-4c27-9c0e-1e015c36233b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2105195425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2105195425
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.427165296
Short name T153
Test name
Test status
Simulation time 833395214 ps
CPU time 21.13 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:41:10 PM PDT 24
Peak memory 208912 kb
Host smart-45b6ba3d-e999-45a5-9c8b-3c0b634bef78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427165296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.427165296
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.712500982
Short name T131
Test name
Test status
Simulation time 4658767008 ps
CPU time 33.85 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:55 PM PDT 24
Peak memory 221564 kb
Host smart-2de1920b-2ddb-4256-875d-b4ca5caf5c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712500982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.712500982
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2823874714
Short name T266
Test name
Test status
Simulation time 543683422 ps
CPU time 8.87 seconds
Started Apr 16 12:44:42 PM PDT 24
Finished Apr 16 12:44:52 PM PDT 24
Peak memory 214628 kb
Host smart-a6322439-96ae-4106-a95a-387664150c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823874714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2823874714
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2764084285
Short name T36
Test name
Test status
Simulation time 769790969 ps
CPU time 5.06 seconds
Started Apr 16 12:44:47 PM PDT 24
Finished Apr 16 12:44:53 PM PDT 24
Peak memory 220764 kb
Host smart-e30c4bd1-1229-4a55-9136-07c14598e6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764084285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2764084285
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2749729719
Short name T167
Test name
Test status
Simulation time 200130164 ps
CPU time 3.43 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:12 PM PDT 24
Peak memory 222836 kb
Host smart-4e60c238-48b1-4e0e-9c1b-d4d4ba976876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749729719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2749729719
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2257187120
Short name T3
Test name
Test status
Simulation time 3094200443 ps
CPU time 70.78 seconds
Started Apr 16 12:45:57 PM PDT 24
Finished Apr 16 12:47:08 PM PDT 24
Peak memory 215348 kb
Host smart-14324760-7491-40c4-83a6-524e042dc784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257187120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2257187120
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.13297272
Short name T416
Test name
Test status
Simulation time 35263217 ps
CPU time 0.72 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 206204 kb
Host smart-63802632-996d-46fa-a476-0e847f7b4fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13297272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.13297272
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.329110311
Short name T84
Test name
Test status
Simulation time 2434063136 ps
CPU time 42.86 seconds
Started Apr 16 12:46:10 PM PDT 24
Finished Apr 16 12:46:57 PM PDT 24
Peak memory 221224 kb
Host smart-2c65d4e9-f6cd-4cf0-a802-f3bcb5e688c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329110311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.329110311
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2158455765
Short name T234
Test name
Test status
Simulation time 138048990 ps
CPU time 4.94 seconds
Started Apr 16 12:45:35 PM PDT 24
Finished Apr 16 12:45:41 PM PDT 24
Peak memory 214664 kb
Host smart-549cc20d-09f9-4a69-a5b6-71a1e4f1142e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158455765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2158455765
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2225887248
Short name T31
Test name
Test status
Simulation time 67873889 ps
CPU time 2.56 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 209036 kb
Host smart-c85ea456-20e0-47a8-ab62-81da8bc97e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225887248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2225887248
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.304561043
Short name T216
Test name
Test status
Simulation time 2398377947 ps
CPU time 50.68 seconds
Started Apr 16 12:46:28 PM PDT 24
Finished Apr 16 12:47:21 PM PDT 24
Peak memory 222788 kb
Host smart-e330f09d-dc99-4b79-9f12-8dff6051414e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304561043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.304561043
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2427673895
Short name T163
Test name
Test status
Simulation time 187639885 ps
CPU time 3.99 seconds
Started Apr 16 12:46:10 PM PDT 24
Finished Apr 16 12:46:18 PM PDT 24
Peak memory 210636 kb
Host smart-b5c9252a-2854-4b0f-9f21-dcc4a5906d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427673895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2427673895
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2505889061
Short name T339
Test name
Test status
Simulation time 2895205058 ps
CPU time 153.63 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 222768 kb
Host smart-02b4a731-88be-47c3-9fe9-b51a6ee7af02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505889061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2505889061
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.334825481
Short name T28
Test name
Test status
Simulation time 64266045 ps
CPU time 3.11 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:43 PM PDT 24
Peak memory 210008 kb
Host smart-5bb8beed-9a93-4ce8-b456-88f65ec2a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334825481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.334825481
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.736862684
Short name T230
Test name
Test status
Simulation time 2900800632 ps
CPU time 32.73 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:33 PM PDT 24
Peak memory 222792 kb
Host smart-01088879-d689-4eec-a57d-6c893f10ac81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736862684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.736862684
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.290791868
Short name T184
Test name
Test status
Simulation time 288343601 ps
CPU time 3.76 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:25 PM PDT 24
Peak memory 211488 kb
Host smart-cad7cb09-38f3-4799-9970-f08ff447f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290791868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.290791868
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3583176146
Short name T260
Test name
Test status
Simulation time 235123844 ps
CPU time 4.74 seconds
Started Apr 16 12:46:44 PM PDT 24
Finished Apr 16 12:46:50 PM PDT 24
Peak memory 215432 kb
Host smart-557eee3d-6b69-467a-8c24-a33bb79234e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583176146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3583176146
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3159291238
Short name T39
Test name
Test status
Simulation time 27660855797 ps
CPU time 60.23 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:46:14 PM PDT 24
Peak memory 215472 kb
Host smart-1963144f-5bc0-49db-88fa-bdd125268dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159291238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3159291238
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2793978855
Short name T33
Test name
Test status
Simulation time 325017715 ps
CPU time 4.28 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 214428 kb
Host smart-1f40fe59-b0f4-417a-9605-16fed3dad459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793978855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2793978855
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.855733498
Short name T149
Test name
Test status
Simulation time 157996028 ps
CPU time 6.18 seconds
Started Apr 16 12:40:41 PM PDT 24
Finished Apr 16 12:40:49 PM PDT 24
Peak memory 214152 kb
Host smart-c54dda9a-87d0-4c45-9125-1be2d0d9d8ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855733498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.855733498
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2093217254
Short name T315
Test name
Test status
Simulation time 601100963 ps
CPU time 8.79 seconds
Started Apr 16 12:46:31 PM PDT 24
Finished Apr 16 12:46:42 PM PDT 24
Peak memory 215380 kb
Host smart-1541cbeb-f99a-4cea-9631-caa5edcd6ca8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093217254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2093217254
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4218106272
Short name T57
Test name
Test status
Simulation time 7170723022 ps
CPU time 77.49 seconds
Started Apr 16 12:45:25 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 215924 kb
Host smart-dc3bce2a-6a63-4848-870b-2729deaa9c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218106272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4218106272
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1851060859
Short name T203
Test name
Test status
Simulation time 376844461 ps
CPU time 8.44 seconds
Started Apr 16 12:45:50 PM PDT 24
Finished Apr 16 12:45:59 PM PDT 24
Peak memory 211464 kb
Host smart-6212fd00-15d1-4112-ba7d-f80f6d6a6068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851060859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1851060859
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1363593453
Short name T215
Test name
Test status
Simulation time 539254462 ps
CPU time 28.96 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:36 PM PDT 24
Peak memory 221488 kb
Host smart-7c6f541f-f575-450c-b47f-6e1432d03c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363593453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1363593453
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1084437204
Short name T379
Test name
Test status
Simulation time 1536279558 ps
CPU time 9.38 seconds
Started Apr 16 12:46:17 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 222744 kb
Host smart-8ab092dc-2d62-4219-a03e-9a7b07894a34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1084437204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1084437204
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1568733349
Short name T146
Test name
Test status
Simulation time 221329445 ps
CPU time 8.9 seconds
Started Apr 16 12:40:36 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 209340 kb
Host smart-e329e3d1-d0cb-4fa5-b8ee-cf30e2f55110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568733349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1568733349
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.214406034
Short name T157
Test name
Test status
Simulation time 1772206937 ps
CPU time 5.84 seconds
Started Apr 16 12:40:38 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 209276 kb
Host smart-122f4ab3-ed22-421c-ac86-bd86443c978e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214406034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
214406034
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3814808867
Short name T651
Test name
Test status
Simulation time 220878925 ps
CPU time 3.51 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:17 PM PDT 24
Peak memory 209340 kb
Host smart-45416843-05ab-43c6-9b59-e5507241e2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814808867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3814808867
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3289087337
Short name T171
Test name
Test status
Simulation time 75115309 ps
CPU time 4.06 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:30 PM PDT 24
Peak memory 217624 kb
Host smart-124b6b58-53ea-4c7a-af9f-588d75ecc99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289087337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3289087337
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1427606202
Short name T89
Test name
Test status
Simulation time 87302419 ps
CPU time 4.53 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 214572 kb
Host smart-d5e8949c-7d1d-4400-820d-e147066940c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427606202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1427606202
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1205165470
Short name T58
Test name
Test status
Simulation time 923749023 ps
CPU time 34.13 seconds
Started Apr 16 12:46:39 PM PDT 24
Finished Apr 16 12:47:15 PM PDT 24
Peak memory 217248 kb
Host smart-f6113c74-f7ec-4652-9d36-9009cd9a8c58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205165470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1205165470
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1817215480
Short name T170
Test name
Test status
Simulation time 194840119 ps
CPU time 3.14 seconds
Started Apr 16 12:45:44 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 217744 kb
Host smart-b88bd975-0567-43cf-ab10-5d33a671bb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817215480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1817215480
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.886404336
Short name T81
Test name
Test status
Simulation time 142236039 ps
CPU time 5.22 seconds
Started Apr 16 12:45:28 PM PDT 24
Finished Apr 16 12:45:36 PM PDT 24
Peak memory 211824 kb
Host smart-dc255bd7-53e4-4e38-99c8-9c50ab7acee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886404336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.886404336
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.72751609
Short name T49
Test name
Test status
Simulation time 271008279 ps
CPU time 3.37 seconds
Started Apr 16 12:46:31 PM PDT 24
Finished Apr 16 12:46:36 PM PDT 24
Peak memory 210548 kb
Host smart-7253fe2e-123c-4ad0-9560-bc436d19c184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72751609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.72751609
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1458563600
Short name T151
Test name
Test status
Simulation time 845692590 ps
CPU time 8.79 seconds
Started Apr 16 12:40:26 PM PDT 24
Finished Apr 16 12:40:36 PM PDT 24
Peak memory 214060 kb
Host smart-2bb7d24a-8ee8-4a64-9047-87d5eaff5d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458563600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1458563600
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3579386204
Short name T166
Test name
Test status
Simulation time 1098247864 ps
CPU time 3.87 seconds
Started Apr 16 12:46:12 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 222944 kb
Host smart-45410089-9678-4bc9-a8e9-2bd57c5e3dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579386204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3579386204
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.725947073
Short name T901
Test name
Test status
Simulation time 262457278 ps
CPU time 13.87 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 214964 kb
Host smart-5a545fd1-3d48-4d2e-91fd-1e842d610696
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725947073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.725947073
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.310307094
Short name T313
Test name
Test status
Simulation time 555028108 ps
CPU time 6.96 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 209848 kb
Host smart-fb9d4ad0-6dbc-4917-b933-e2fb973a5d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310307094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.310307094
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2372109048
Short name T222
Test name
Test status
Simulation time 1085933188 ps
CPU time 23.25 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:40 PM PDT 24
Peak memory 222800 kb
Host smart-9d510d92-c2c5-40c8-a8f4-9300f00a02c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372109048 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2372109048
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1331432636
Short name T255
Test name
Test status
Simulation time 1626578790 ps
CPU time 12.55 seconds
Started Apr 16 12:45:52 PM PDT 24
Finished Apr 16 12:46:05 PM PDT 24
Peak memory 211692 kb
Host smart-13d45f9f-a902-4e22-94bf-892dd02fdad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331432636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1331432636
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.674825044
Short name T341
Test name
Test status
Simulation time 898227918 ps
CPU time 22.11 seconds
Started Apr 16 12:45:55 PM PDT 24
Finished Apr 16 12:46:18 PM PDT 24
Peak memory 208048 kb
Host smart-d6679444-af23-480f-8486-6658fb43e931
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674825044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.674825044
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3912584442
Short name T298
Test name
Test status
Simulation time 389067550 ps
CPU time 4.92 seconds
Started Apr 16 12:46:59 PM PDT 24
Finished Apr 16 12:47:08 PM PDT 24
Peak memory 214556 kb
Host smart-cce635a6-fe56-4461-8d97-9398f3e70e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912584442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3912584442
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2946752885
Short name T161
Test name
Test status
Simulation time 1201801971 ps
CPU time 10.67 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:56 PM PDT 24
Peak memory 214016 kb
Host smart-5e8d19f5-5434-430a-9d49-f96ab07f00b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946752885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2946752885
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.737279400
Short name T169
Test name
Test status
Simulation time 560721433 ps
CPU time 9.11 seconds
Started Apr 16 12:46:26 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 222892 kb
Host smart-27c03de8-95d2-4963-a3dd-e0db41698f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737279400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.737279400
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2140220203
Short name T860
Test name
Test status
Simulation time 238436204 ps
CPU time 4.52 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:30 PM PDT 24
Peak memory 214540 kb
Host smart-d01052c3-1c1a-4df4-8d84-1b8f614b00cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2140220203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2140220203
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2247770467
Short name T47
Test name
Test status
Simulation time 469411445 ps
CPU time 12.6 seconds
Started Apr 16 12:45:21 PM PDT 24
Finished Apr 16 12:45:35 PM PDT 24
Peak memory 211172 kb
Host smart-6f6ba279-30df-4475-b6aa-566c0f2eef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247770467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2247770467
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1534352346
Short name T74
Test name
Test status
Simulation time 537125251 ps
CPU time 10.5 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:51 PM PDT 24
Peak memory 214436 kb
Host smart-a9b94cbc-e0c7-4bd6-9d8c-853a98e7937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534352346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1534352346
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2114862576
Short name T497
Test name
Test status
Simulation time 208575606 ps
CPU time 3.09 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 208792 kb
Host smart-964dea10-5b54-4565-a8cf-499e9814a544
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114862576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2114862576
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3005134214
Short name T370
Test name
Test status
Simulation time 549522153 ps
CPU time 4.2 seconds
Started Apr 16 12:44:49 PM PDT 24
Finished Apr 16 12:44:55 PM PDT 24
Peak memory 209016 kb
Host smart-ba103a77-1cc6-4969-9f1b-fcb09885ab26
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005134214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3005134214
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.703407116
Short name T321
Test name
Test status
Simulation time 4793597154 ps
CPU time 41.36 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:41 PM PDT 24
Peak memory 222928 kb
Host smart-bb8ddbd7-240f-4423-bdd5-76766ca8e1e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703407116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.703407116
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1633583641
Short name T320
Test name
Test status
Simulation time 125598956 ps
CPU time 4.1 seconds
Started Apr 16 12:46:09 PM PDT 24
Finished Apr 16 12:46:17 PM PDT 24
Peak memory 222500 kb
Host smart-0c171057-f73e-47bd-b2b4-9ac150cdbdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633583641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1633583641
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3069486975
Short name T6
Test name
Test status
Simulation time 348180043 ps
CPU time 4.7 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 222020 kb
Host smart-bcdedfc9-71cd-4a97-a4ac-4a6ba0ce3a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069486975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3069486975
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.87992767
Short name T259
Test name
Test status
Simulation time 398792038 ps
CPU time 5.04 seconds
Started Apr 16 12:46:07 PM PDT 24
Finished Apr 16 12:46:17 PM PDT 24
Peak memory 222700 kb
Host smart-4d3807a4-5a7d-4b7a-badc-2b944e90b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87992767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.87992767
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4030602025
Short name T251
Test name
Test status
Simulation time 41335231 ps
CPU time 2.88 seconds
Started Apr 16 12:46:17 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 215832 kb
Host smart-52949ac9-0d80-4d91-8ca6-5d3aef7dfc22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030602025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4030602025
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3748558786
Short name T300
Test name
Test status
Simulation time 255839329 ps
CPU time 5.03 seconds
Started Apr 16 12:45:17 PM PDT 24
Finished Apr 16 12:45:25 PM PDT 24
Peak memory 222676 kb
Host smart-c4b2f0e4-e115-46c2-a2a5-1eba5b75903f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748558786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3748558786
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1000053616
Short name T44
Test name
Test status
Simulation time 28935966721 ps
CPU time 604.97 seconds
Started Apr 16 12:44:59 PM PDT 24
Finished Apr 16 12:55:05 PM PDT 24
Peak memory 217636 kb
Host smart-687b6a2f-9993-4f43-8d3e-00cd57be464f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000053616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1000053616
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.63319786
Short name T158
Test name
Test status
Simulation time 392444166 ps
CPU time 5.78 seconds
Started Apr 16 12:40:46 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 209516 kb
Host smart-136c6481-951f-4723-bd98-5f0bbe55d586
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63319786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.63319786
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3100225211
Short name T150
Test name
Test status
Simulation time 423477477 ps
CPU time 8.58 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 209368 kb
Host smart-96e1ff8f-af4f-4dfd-9da9-e7a17e2c2819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100225211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3100225211
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2202429512
Short name T733
Test name
Test status
Simulation time 585995608 ps
CPU time 3.1 seconds
Started Apr 16 12:44:49 PM PDT 24
Finished Apr 16 12:44:53 PM PDT 24
Peak memory 215024 kb
Host smart-2c42a9ad-4615-467b-a2b0-b7ff6f453e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202429512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2202429512
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1947902348
Short name T168
Test name
Test status
Simulation time 84533644 ps
CPU time 3.82 seconds
Started Apr 16 12:45:58 PM PDT 24
Finished Apr 16 12:46:03 PM PDT 24
Peak memory 217848 kb
Host smart-7f426293-0fb8-43c3-b6cf-8c4a9d9cec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947902348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1947902348
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.724144616
Short name T308
Test name
Test status
Simulation time 1011730661 ps
CPU time 53.61 seconds
Started Apr 16 12:45:05 PM PDT 24
Finished Apr 16 12:46:01 PM PDT 24
Peak memory 214604 kb
Host smart-990da24a-a801-4d05-a619-9ead62af9bec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724144616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.724144616
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.158951101
Short name T239
Test name
Test status
Simulation time 86788872 ps
CPU time 3.47 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 218668 kb
Host smart-5db0e3a2-cd3b-4c8b-99a0-30f81404527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158951101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.158951101
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3350590710
Short name T142
Test name
Test status
Simulation time 232902906 ps
CPU time 4.49 seconds
Started Apr 16 12:45:14 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 215504 kb
Host smart-5d1d50e0-29a8-4e59-8cf2-2ba705bfcc2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350590710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3350590710
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1866281567
Short name T327
Test name
Test status
Simulation time 155008141 ps
CPU time 4.91 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:30 PM PDT 24
Peak memory 209720 kb
Host smart-4db6b234-b9c0-40c1-bb0a-bcf5066fb0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866281567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1866281567
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3529053566
Short name T225
Test name
Test status
Simulation time 326453718 ps
CPU time 4.13 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 209900 kb
Host smart-b0d75b3e-b12b-48e6-b215-07918a772b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529053566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3529053566
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3775603637
Short name T742
Test name
Test status
Simulation time 470356784 ps
CPU time 10.8 seconds
Started Apr 16 12:45:20 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 222628 kb
Host smart-ff462a8f-7351-4c2b-8ff1-12178febc3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775603637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3775603637
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.684970335
Short name T217
Test name
Test status
Simulation time 450399240 ps
CPU time 10.19 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:46 PM PDT 24
Peak memory 214636 kb
Host smart-c102ed3c-7ddc-4cee-b178-906c8653a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684970335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.684970335
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.849862490
Short name T243
Test name
Test status
Simulation time 181502743 ps
CPU time 9.41 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:44 PM PDT 24
Peak memory 214592 kb
Host smart-c052b0ab-06bf-4733-89c6-d880653f2485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849862490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.849862490
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4216319210
Short name T292
Test name
Test status
Simulation time 819070723 ps
CPU time 29.28 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:46:09 PM PDT 24
Peak memory 215280 kb
Host smart-0e65cae9-d89d-4566-97ac-974dde487073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216319210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4216319210
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3779537533
Short name T353
Test name
Test status
Simulation time 845324705 ps
CPU time 3.93 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 218700 kb
Host smart-1f567136-a91a-4690-aeeb-5a5f94f911aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779537533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3779537533
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2402809292
Short name T129
Test name
Test status
Simulation time 67891007 ps
CPU time 2.56 seconds
Started Apr 16 12:45:48 PM PDT 24
Finished Apr 16 12:45:52 PM PDT 24
Peak memory 215804 kb
Host smart-48ae931d-2382-411c-b257-ad4158fafb88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402809292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2402809292
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1678265555
Short name T247
Test name
Test status
Simulation time 678740407 ps
CPU time 4.41 seconds
Started Apr 16 12:45:56 PM PDT 24
Finished Apr 16 12:46:02 PM PDT 24
Peak memory 214632 kb
Host smart-9556d377-397b-4fde-b590-9fa0f3d54620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678265555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1678265555
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3453206129
Short name T303
Test name
Test status
Simulation time 71187123 ps
CPU time 4.37 seconds
Started Apr 16 12:46:37 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 210476 kb
Host smart-d66eee7d-e8fd-4ae0-9d23-ace1f73fdfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453206129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3453206129
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.481765788
Short name T172
Test name
Test status
Simulation time 3231296493 ps
CPU time 21.93 seconds
Started Apr 16 12:45:15 PM PDT 24
Finished Apr 16 12:45:40 PM PDT 24
Peak memory 223032 kb
Host smart-31b54fea-175c-4ac0-bd19-99462844de4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481765788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.481765788
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1081808503
Short name T920
Test name
Test status
Simulation time 234046374 ps
CPU time 7.54 seconds
Started Apr 16 12:40:13 PM PDT 24
Finished Apr 16 12:40:21 PM PDT 24
Peak memory 205976 kb
Host smart-06c64beb-4407-4cf7-a11b-bf80178eae77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081808503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
081808503
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.775520589
Short name T1003
Test name
Test status
Simulation time 486094072 ps
CPU time 11.71 seconds
Started Apr 16 12:40:29 PM PDT 24
Finished Apr 16 12:40:41 PM PDT 24
Peak memory 205872 kb
Host smart-62fc903c-8c79-4423-a1a2-d66d3333b13c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775520589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.775520589
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.4283825104
Short name T909
Test name
Test status
Simulation time 39732512 ps
CPU time 0.92 seconds
Started Apr 16 12:40:17 PM PDT 24
Finished Apr 16 12:40:18 PM PDT 24
Peak memory 205700 kb
Host smart-0c70c466-f6e0-422f-a4f9-eaf66e244336
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283825104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.4
283825104
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1991934395
Short name T971
Test name
Test status
Simulation time 30531405 ps
CPU time 2.17 seconds
Started Apr 16 12:40:24 PM PDT 24
Finished Apr 16 12:40:27 PM PDT 24
Peak memory 222368 kb
Host smart-85aaa410-4577-4954-99e5-71834efd26e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991934395 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1991934395
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.851817487
Short name T944
Test name
Test status
Simulation time 70233152 ps
CPU time 0.89 seconds
Started Apr 16 12:40:26 PM PDT 24
Finished Apr 16 12:40:27 PM PDT 24
Peak memory 205624 kb
Host smart-fb2a83e8-f438-47db-ab9a-5d47ab733d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851817487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.851817487
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2698110574
Short name T1038
Test name
Test status
Simulation time 30802926 ps
CPU time 0.79 seconds
Started Apr 16 12:40:23 PM PDT 24
Finished Apr 16 12:40:24 PM PDT 24
Peak memory 205548 kb
Host smart-0efc135c-a531-45b4-b5f5-2d48608c1361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698110574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2698110574
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.344988258
Short name T977
Test name
Test status
Simulation time 113162800 ps
CPU time 1.55 seconds
Started Apr 16 12:40:25 PM PDT 24
Finished Apr 16 12:40:27 PM PDT 24
Peak memory 205928 kb
Host smart-e6c31fa0-f3ae-4693-a837-61c4c06db0c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344988258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.344988258
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3284237990
Short name T110
Test name
Test status
Simulation time 80418377 ps
CPU time 2.76 seconds
Started Apr 16 12:40:05 PM PDT 24
Finished Apr 16 12:40:09 PM PDT 24
Peak memory 214388 kb
Host smart-d38bdbcd-8f98-4f5f-9287-0dd2ade18645
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284237990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3284237990
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3788716084
Short name T986
Test name
Test status
Simulation time 180251819 ps
CPU time 7.15 seconds
Started Apr 16 12:40:13 PM PDT 24
Finished Apr 16 12:40:20 PM PDT 24
Peak memory 214488 kb
Host smart-dbd5f766-e354-4cc4-bdc5-5c63b0238cb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788716084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3788716084
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1677317234
Short name T983
Test name
Test status
Simulation time 43839646 ps
CPU time 2.72 seconds
Started Apr 16 12:40:14 PM PDT 24
Finished Apr 16 12:40:17 PM PDT 24
Peak memory 214100 kb
Host smart-94e00b0b-e7ee-4eed-bb4e-3ae3dfff1f56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677317234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1677317234
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2909735914
Short name T1010
Test name
Test status
Simulation time 905221276 ps
CPU time 8.22 seconds
Started Apr 16 12:40:15 PM PDT 24
Finished Apr 16 12:40:24 PM PDT 24
Peak memory 209100 kb
Host smart-971abf99-7098-432c-a9cf-0aef444dca69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909735914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2909735914
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.983072703
Short name T1023
Test name
Test status
Simulation time 509025559 ps
CPU time 7.79 seconds
Started Apr 16 12:40:25 PM PDT 24
Finished Apr 16 12:40:33 PM PDT 24
Peak memory 205824 kb
Host smart-a3fd1605-0921-4283-8398-6f5b15924452
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983072703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.983072703
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1004439317
Short name T918
Test name
Test status
Simulation time 467975031 ps
CPU time 6.56 seconds
Started Apr 16 12:40:29 PM PDT 24
Finished Apr 16 12:40:36 PM PDT 24
Peak memory 205892 kb
Host smart-6a4e5213-915b-44ca-95c1-c4b252487b14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004439317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
004439317
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1654262863
Short name T998
Test name
Test status
Simulation time 21368038 ps
CPU time 1.19 seconds
Started Apr 16 12:40:13 PM PDT 24
Finished Apr 16 12:40:15 PM PDT 24
Peak memory 205944 kb
Host smart-9d453823-56ed-4751-8740-2d894003f01a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654262863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
654262863
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2042737892
Short name T959
Test name
Test status
Simulation time 51869857 ps
CPU time 2.28 seconds
Started Apr 16 12:40:36 PM PDT 24
Finished Apr 16 12:40:39 PM PDT 24
Peak memory 214128 kb
Host smart-759be87b-b1bd-4cba-b74f-b6368e891a4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042737892 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2042737892
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3249518951
Short name T925
Test name
Test status
Simulation time 31083895 ps
CPU time 1.57 seconds
Started Apr 16 12:40:15 PM PDT 24
Finished Apr 16 12:40:17 PM PDT 24
Peak memory 205804 kb
Host smart-4a9e67af-ccb4-4dc1-afe9-949596b95436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249518951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3249518951
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.267214521
Short name T1031
Test name
Test status
Simulation time 11418415 ps
CPU time 0.7 seconds
Started Apr 16 12:40:21 PM PDT 24
Finished Apr 16 12:40:22 PM PDT 24
Peak memory 205612 kb
Host smart-c506b971-8d8f-4e6a-a681-3a234c894939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267214521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.267214521
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2745239056
Short name T136
Test name
Test status
Simulation time 170581258 ps
CPU time 2.23 seconds
Started Apr 16 12:40:32 PM PDT 24
Finished Apr 16 12:40:35 PM PDT 24
Peak memory 205820 kb
Host smart-5c1dbd78-69e6-491f-bafc-585d0efa2416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745239056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2745239056
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2277973833
Short name T106
Test name
Test status
Simulation time 3245355768 ps
CPU time 6.04 seconds
Started Apr 16 12:40:14 PM PDT 24
Finished Apr 16 12:40:21 PM PDT 24
Peak memory 214428 kb
Host smart-a3646f36-a4c7-4a96-8436-4eca4353f272
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277973833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2277973833
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3416437764
Short name T1001
Test name
Test status
Simulation time 317597004 ps
CPU time 3.93 seconds
Started Apr 16 12:40:16 PM PDT 24
Finished Apr 16 12:40:20 PM PDT 24
Peak memory 214340 kb
Host smart-192f25eb-33fc-483d-affc-2dba5842a3c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416437764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3416437764
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.290156982
Short name T942
Test name
Test status
Simulation time 136905825 ps
CPU time 4.7 seconds
Started Apr 16 12:40:26 PM PDT 24
Finished Apr 16 12:40:32 PM PDT 24
Peak memory 214092 kb
Host smart-354618ee-8e33-47d8-85bc-1ee8541d676f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290156982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.290156982
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2522276141
Short name T147
Test name
Test status
Simulation time 361048000 ps
CPU time 5.53 seconds
Started Apr 16 12:40:14 PM PDT 24
Finished Apr 16 12:40:20 PM PDT 24
Peak memory 209288 kb
Host smart-e24c9e16-05dc-49fc-98ea-f2b678f567fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522276141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2522276141
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.367383327
Short name T1068
Test name
Test status
Simulation time 50988162 ps
CPU time 1.12 seconds
Started Apr 16 12:40:37 PM PDT 24
Finished Apr 16 12:40:40 PM PDT 24
Peak memory 205668 kb
Host smart-3ab653f8-ce80-46b0-a59b-d0e92a6a3e93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367383327 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.367383327
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4174191251
Short name T954
Test name
Test status
Simulation time 21901311 ps
CPU time 1.02 seconds
Started Apr 16 12:40:41 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 205872 kb
Host smart-0606bc9a-8203-4ea5-8034-d14968c8cf2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174191251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4174191251
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1948214502
Short name T979
Test name
Test status
Simulation time 33773663 ps
CPU time 0.73 seconds
Started Apr 16 12:40:41 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 205540 kb
Host smart-ce55f8dc-845a-45fe-91e2-ec9be63b37e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948214502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1948214502
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2571040533
Short name T141
Test name
Test status
Simulation time 1011134580 ps
CPU time 3.72 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:44 PM PDT 24
Peak memory 205904 kb
Host smart-220da215-7341-40a5-95d7-f722259bceac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571040533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2571040533
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.969199067
Short name T1069
Test name
Test status
Simulation time 1049783737 ps
CPU time 3.61 seconds
Started Apr 16 12:40:45 PM PDT 24
Finished Apr 16 12:40:51 PM PDT 24
Peak memory 222492 kb
Host smart-025174a8-9b37-4a6c-9a33-9a831a9737e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969199067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.969199067
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3169169978
Short name T984
Test name
Test status
Simulation time 1273721171 ps
CPU time 8.12 seconds
Started Apr 16 12:40:49 PM PDT 24
Finished Apr 16 12:40:59 PM PDT 24
Peak memory 214432 kb
Host smart-d0bfce6c-cdda-4597-b474-5bbde7ee49ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169169978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3169169978
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.204193672
Short name T955
Test name
Test status
Simulation time 36411430 ps
CPU time 2.03 seconds
Started Apr 16 12:40:43 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 214084 kb
Host smart-d07e8dbf-cbe1-4a36-b29b-f2d145914cef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204193672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.204193672
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2276701764
Short name T1065
Test name
Test status
Simulation time 214303548 ps
CPU time 1.77 seconds
Started Apr 16 12:40:45 PM PDT 24
Finished Apr 16 12:40:48 PM PDT 24
Peak memory 214116 kb
Host smart-d111740b-4d82-4422-b890-eaa99849495f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276701764 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2276701764
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3401844554
Short name T1000
Test name
Test status
Simulation time 21810529 ps
CPU time 1.37 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:42 PM PDT 24
Peak memory 205920 kb
Host smart-81cf24b3-5e28-4d80-a29e-ca485e49e287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401844554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3401844554
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1851232417
Short name T904
Test name
Test status
Simulation time 42791267 ps
CPU time 0.79 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 205572 kb
Host smart-8cbba842-7ab9-46c6-9146-5e13a6f6c109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851232417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1851232417
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.4195642208
Short name T140
Test name
Test status
Simulation time 57660445 ps
CPU time 2.3 seconds
Started Apr 16 12:40:38 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 205888 kb
Host smart-3d038aaa-9b2a-48e6-9418-ac562e4698e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195642208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.4195642208
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4081881196
Short name T113
Test name
Test status
Simulation time 159881225 ps
CPU time 2.71 seconds
Started Apr 16 12:40:28 PM PDT 24
Finished Apr 16 12:40:31 PM PDT 24
Peak memory 214312 kb
Host smart-f59d35ac-65d7-48b2-b3cf-a948273d8827
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081881196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.4081881196
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3183561823
Short name T1026
Test name
Test status
Simulation time 543164368 ps
CPU time 16.19 seconds
Started Apr 16 12:40:48 PM PDT 24
Finished Apr 16 12:41:06 PM PDT 24
Peak memory 214252 kb
Host smart-a8c1cc5c-6c73-43e9-8255-2e87e69a96ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183561823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3183561823
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3571993926
Short name T1014
Test name
Test status
Simulation time 1214622684 ps
CPU time 4.2 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:45 PM PDT 24
Peak memory 214040 kb
Host smart-f76ea2fc-cafc-4889-84fb-75f5c13ee76d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571993926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3571993926
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1721600502
Short name T144
Test name
Test status
Simulation time 101541155 ps
CPU time 3.54 seconds
Started Apr 16 12:40:45 PM PDT 24
Finished Apr 16 12:40:50 PM PDT 24
Peak memory 209328 kb
Host smart-25d0deca-b429-481c-8820-94b9341e1d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721600502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1721600502
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3952725170
Short name T996
Test name
Test status
Simulation time 27077800 ps
CPU time 1.84 seconds
Started Apr 16 12:40:38 PM PDT 24
Finished Apr 16 12:40:41 PM PDT 24
Peak memory 214200 kb
Host smart-0d3e595b-05f2-40fb-bb58-354a11e20c42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952725170 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3952725170
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1480447295
Short name T1028
Test name
Test status
Simulation time 38909203 ps
CPU time 0.99 seconds
Started Apr 16 12:40:40 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 205832 kb
Host smart-00dbc76a-84b8-4ae3-9f9e-ff28467e6c38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480447295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1480447295
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2022983652
Short name T934
Test name
Test status
Simulation time 10742545 ps
CPU time 0.69 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:41 PM PDT 24
Peak memory 205448 kb
Host smart-fc0651d7-423f-477a-b479-2efbe2a2b9e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022983652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2022983652
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2119770434
Short name T981
Test name
Test status
Simulation time 134836146 ps
CPU time 1.91 seconds
Started Apr 16 12:40:40 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 205872 kb
Host smart-aa5b18e9-37c6-4b8e-a311-adaf18d4c161
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119770434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2119770434
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1896115788
Short name T114
Test name
Test status
Simulation time 1996380087 ps
CPU time 11.88 seconds
Started Apr 16 12:40:35 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 214272 kb
Host smart-3db39fcb-c7b6-4a22-b1cb-c49b2d842908
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896115788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1896115788
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4065747320
Short name T1043
Test name
Test status
Simulation time 157253469 ps
CPU time 6.55 seconds
Started Apr 16 12:40:42 PM PDT 24
Finished Apr 16 12:40:50 PM PDT 24
Peak memory 214420 kb
Host smart-af67ee7f-9225-4899-a1db-3e97a0269787
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065747320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.4065747320
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3761025930
Short name T989
Test name
Test status
Simulation time 1187372606 ps
CPU time 3.25 seconds
Started Apr 16 12:40:38 PM PDT 24
Finished Apr 16 12:40:42 PM PDT 24
Peak memory 214024 kb
Host smart-7e1d7b39-d5b0-4dee-9a87-70791faede19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761025930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3761025930
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2642836388
Short name T162
Test name
Test status
Simulation time 83132447 ps
CPU time 3.77 seconds
Started Apr 16 12:40:43 PM PDT 24
Finished Apr 16 12:40:49 PM PDT 24
Peak memory 209312 kb
Host smart-b9ee2f4f-0b7e-4338-bfad-f992653254ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642836388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2642836388
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3702523551
Short name T975
Test name
Test status
Simulation time 78856716 ps
CPU time 1.76 seconds
Started Apr 16 12:40:49 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 214040 kb
Host smart-006d1acd-885e-4f3a-a617-bd019a3688fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702523551 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3702523551
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2999023219
Short name T935
Test name
Test status
Simulation time 37690869 ps
CPU time 1 seconds
Started Apr 16 12:40:48 PM PDT 24
Finished Apr 16 12:40:51 PM PDT 24
Peak memory 205828 kb
Host smart-1e3fc494-08f6-4645-ba42-4c8da525ac82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999023219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2999023219
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2984581827
Short name T1018
Test name
Test status
Simulation time 30249247 ps
CPU time 0.75 seconds
Started Apr 16 12:40:36 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 205408 kb
Host smart-83771296-753d-4ea9-a244-0704f0954094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984581827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2984581827
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2564887159
Short name T921
Test name
Test status
Simulation time 99881672 ps
CPU time 3.22 seconds
Started Apr 16 12:40:40 PM PDT 24
Finished Apr 16 12:40:45 PM PDT 24
Peak memory 205768 kb
Host smart-236fa067-4dc8-46a3-9c0a-90384d492d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564887159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2564887159
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2856741344
Short name T993
Test name
Test status
Simulation time 267305401 ps
CPU time 2.45 seconds
Started Apr 16 12:40:35 PM PDT 24
Finished Apr 16 12:40:39 PM PDT 24
Peak memory 222564 kb
Host smart-c849b7af-4834-44b3-b2dc-ba64c50df15e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856741344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2856741344
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3084884944
Short name T1040
Test name
Test status
Simulation time 2309515082 ps
CPU time 13.99 seconds
Started Apr 16 12:40:48 PM PDT 24
Finished Apr 16 12:41:03 PM PDT 24
Peak memory 220572 kb
Host smart-524447ed-9323-4220-bd5c-272812bf5f26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084884944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3084884944
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1419403545
Short name T1019
Test name
Test status
Simulation time 387017266 ps
CPU time 2.42 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:48 PM PDT 24
Peak memory 214080 kb
Host smart-91859d8b-842b-466b-90a2-ecfd62f1aeff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419403545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1419403545
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3681850273
Short name T156
Test name
Test status
Simulation time 228320601 ps
CPU time 3.35 seconds
Started Apr 16 12:40:51 PM PDT 24
Finished Apr 16 12:40:56 PM PDT 24
Peak memory 209432 kb
Host smart-d16871ad-7344-4330-8ce3-5bc66b428bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681850273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3681850273
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1497453574
Short name T950
Test name
Test status
Simulation time 126720236 ps
CPU time 1.37 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:50 PM PDT 24
Peak memory 214140 kb
Host smart-bf9fe71c-eca7-492b-9d2e-bda4ad475d15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497453574 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1497453574
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3826228602
Short name T969
Test name
Test status
Simulation time 13344727 ps
CPU time 0.97 seconds
Started Apr 16 12:40:49 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 205652 kb
Host smart-2f6c53c7-8b1e-4d89-9653-e3085eb95506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826228602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3826228602
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.140076473
Short name T1058
Test name
Test status
Simulation time 14968578 ps
CPU time 0.9 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 205744 kb
Host smart-48051d34-54c9-4c36-a8a1-9d235a6fdeb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140076473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.140076473
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2234735533
Short name T1006
Test name
Test status
Simulation time 124938929 ps
CPU time 2.08 seconds
Started Apr 16 12:40:43 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 205888 kb
Host smart-f65a9fb8-48be-4282-8495-de3b4e98e6fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234735533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2234735533
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1366429096
Short name T988
Test name
Test status
Simulation time 368598828 ps
CPU time 2.23 seconds
Started Apr 16 12:40:48 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 219244 kb
Host smart-dd51251b-9e58-458b-8d56-c1d1e49edfa0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366429096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1366429096
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.757973889
Short name T960
Test name
Test status
Simulation time 892831159 ps
CPU time 5.63 seconds
Started Apr 16 12:40:51 PM PDT 24
Finished Apr 16 12:40:58 PM PDT 24
Peak memory 214412 kb
Host smart-456bfbdb-90a2-4f7c-9695-a4c543864c46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757973889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.757973889
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2687332532
Short name T948
Test name
Test status
Simulation time 671541564 ps
CPU time 2.08 seconds
Started Apr 16 12:40:43 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 214144 kb
Host smart-eda158c3-ba62-46d6-9412-7698b1f5360a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687332532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2687332532
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2310778583
Short name T962
Test name
Test status
Simulation time 28684929 ps
CPU time 1.11 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 205992 kb
Host smart-46aeb61a-5947-46a1-a28a-2c3da8aaa66a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310778583 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2310778583
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2585455276
Short name T1064
Test name
Test status
Simulation time 23433192 ps
CPU time 0.98 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:49 PM PDT 24
Peak memory 205696 kb
Host smart-64a1836c-da3c-4e27-b007-309e68a33d2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585455276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2585455276
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.808032604
Short name T976
Test name
Test status
Simulation time 22608817 ps
CPU time 0.81 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:41 PM PDT 24
Peak memory 205536 kb
Host smart-9a6437e0-1297-4377-8ad9-9d163ec2868d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808032604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.808032604
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1468713052
Short name T958
Test name
Test status
Simulation time 88447434 ps
CPU time 3.65 seconds
Started Apr 16 12:41:03 PM PDT 24
Finished Apr 16 12:41:07 PM PDT 24
Peak memory 205952 kb
Host smart-1941cea9-b826-4683-81b2-1b61ef29c1c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468713052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1468713052
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.797938288
Short name T982
Test name
Test status
Simulation time 105443401 ps
CPU time 2.2 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:42 PM PDT 24
Peak memory 214380 kb
Host smart-b9cb0f83-8ee6-4751-b940-21ebc0f8830e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797938288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.797938288
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4235278252
Short name T1032
Test name
Test status
Simulation time 661085605 ps
CPU time 6.61 seconds
Started Apr 16 12:40:49 PM PDT 24
Finished Apr 16 12:40:57 PM PDT 24
Peak memory 214352 kb
Host smart-988e746a-981e-4504-be40-71470db39b61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235278252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4235278252
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3873689176
Short name T1017
Test name
Test status
Simulation time 148640896 ps
CPU time 3.24 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:51 PM PDT 24
Peak memory 222140 kb
Host smart-0d597764-6634-45f1-a2b7-d80c0a12f3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873689176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3873689176
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1618581661
Short name T1060
Test name
Test status
Simulation time 39832016 ps
CPU time 1.69 seconds
Started Apr 16 12:40:40 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 214336 kb
Host smart-f8a989b9-f76a-4202-9451-0574efc36c50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618581661 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1618581661
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3568575137
Short name T963
Test name
Test status
Simulation time 59012211 ps
CPU time 1.24 seconds
Started Apr 16 12:40:37 PM PDT 24
Finished Apr 16 12:40:40 PM PDT 24
Peak memory 205992 kb
Host smart-45e8916f-4bd3-463a-b452-7bc26c4e68dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568575137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3568575137
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2589684292
Short name T1036
Test name
Test status
Simulation time 52903432 ps
CPU time 0.84 seconds
Started Apr 16 12:40:50 PM PDT 24
Finished Apr 16 12:40:53 PM PDT 24
Peak memory 205396 kb
Host smart-88f6bed1-fa27-4963-a944-8a04cffb3a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589684292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2589684292
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.270873126
Short name T1011
Test name
Test status
Simulation time 306091860 ps
CPU time 3.23 seconds
Started Apr 16 12:40:45 PM PDT 24
Finished Apr 16 12:40:50 PM PDT 24
Peak memory 205892 kb
Host smart-c25db40b-caab-4478-a8e3-c531aed6c0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270873126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.270873126
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2601208714
Short name T1050
Test name
Test status
Simulation time 226590121 ps
CPU time 3.13 seconds
Started Apr 16 12:41:03 PM PDT 24
Finished Apr 16 12:41:07 PM PDT 24
Peak memory 214352 kb
Host smart-fb00be9f-5e1d-46fe-9471-0b8192e57481
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601208714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2601208714
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3255723609
Short name T991
Test name
Test status
Simulation time 164842503 ps
CPU time 3.61 seconds
Started Apr 16 12:40:41 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 214276 kb
Host smart-d57987f1-4ffd-477e-bbb1-9d388102386d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255723609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3255723609
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1586468534
Short name T929
Test name
Test status
Simulation time 85109968 ps
CPU time 2.59 seconds
Started Apr 16 12:40:42 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 214072 kb
Host smart-967d1493-4ad1-45d5-a894-d52b36490b42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586468534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1586468534
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3415787103
Short name T1053
Test name
Test status
Simulation time 69031509 ps
CPU time 1.35 seconds
Started Apr 16 12:40:42 PM PDT 24
Finished Apr 16 12:40:45 PM PDT 24
Peak memory 214188 kb
Host smart-bcf7ace6-7d92-4ae7-b7e6-4c3bce3e3ca8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415787103 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3415787103
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3277933183
Short name T135
Test name
Test status
Simulation time 41385140 ps
CPU time 0.87 seconds
Started Apr 16 12:40:37 PM PDT 24
Finished Apr 16 12:40:39 PM PDT 24
Peak memory 205564 kb
Host smart-14a57081-e6ad-42d9-98ae-6ccb81394af5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277933183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3277933183
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.118300437
Short name T939
Test name
Test status
Simulation time 18187917 ps
CPU time 0.72 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 205548 kb
Host smart-0230c2be-10e1-4444-8cd1-730d257c3d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118300437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.118300437
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.509723442
Short name T967
Test name
Test status
Simulation time 302099297 ps
CPU time 1.36 seconds
Started Apr 16 12:40:41 PM PDT 24
Finished Apr 16 12:40:44 PM PDT 24
Peak memory 205856 kb
Host smart-652a6330-4398-4cee-9e51-51d681b3d062
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509723442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.509723442
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.129831129
Short name T1067
Test name
Test status
Simulation time 375701889 ps
CPU time 2.31 seconds
Started Apr 16 12:40:50 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 214420 kb
Host smart-df66d99d-257e-4c65-9c57-47940e81d124
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129831129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.129831129
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2690084886
Short name T1004
Test name
Test status
Simulation time 834028304 ps
CPU time 13.24 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:41:04 PM PDT 24
Peak memory 214432 kb
Host smart-3330a4a0-d219-4768-9b28-7edc26fa827c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690084886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2690084886
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2009115529
Short name T1015
Test name
Test status
Simulation time 153130012 ps
CPU time 4.79 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 217396 kb
Host smart-46754ace-6fc0-40eb-b3d4-7cf11230e15f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009115529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2009115529
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2004723437
Short name T980
Test name
Test status
Simulation time 2114070707 ps
CPU time 7.9 seconds
Started Apr 16 12:40:43 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 209468 kb
Host smart-e82ad029-adef-4864-b542-18368d1c7b24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004723437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2004723437
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3314048327
Short name T992
Test name
Test status
Simulation time 639820174 ps
CPU time 1.62 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 214112 kb
Host smart-67bd21a0-f914-4eeb-8137-937d5c4e49c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314048327 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3314048327
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2148250053
Short name T362
Test name
Test status
Simulation time 112975489 ps
CPU time 0.92 seconds
Started Apr 16 12:40:40 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 205840 kb
Host smart-4f78874b-6a63-4865-be6c-00a43fdede5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148250053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2148250053
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.227864457
Short name T972
Test name
Test status
Simulation time 19139129 ps
CPU time 0.8 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 205576 kb
Host smart-0c496d36-c770-4b7d-a502-8a915a4bc3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227864457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.227864457
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1164817164
Short name T139
Test name
Test status
Simulation time 342771052 ps
CPU time 2.51 seconds
Started Apr 16 12:40:48 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 205932 kb
Host smart-9c1f3d61-9a85-424c-93f1-9a7f394501b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164817164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1164817164
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3374423528
Short name T108
Test name
Test status
Simulation time 501465466 ps
CPU time 2.78 seconds
Started Apr 16 12:40:42 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 222580 kb
Host smart-2f826c14-3d14-4275-b6bb-c1006179508e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374423528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3374423528
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1479506130
Short name T105
Test name
Test status
Simulation time 769586060 ps
CPU time 11.46 seconds
Started Apr 16 12:40:42 PM PDT 24
Finished Apr 16 12:40:55 PM PDT 24
Peak memory 214432 kb
Host smart-0f1608bb-f5b5-4cc8-8511-a2c763eb327e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479506130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1479506130
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2956947105
Short name T178
Test name
Test status
Simulation time 159745899 ps
CPU time 5 seconds
Started Apr 16 12:40:45 PM PDT 24
Finished Apr 16 12:40:51 PM PDT 24
Peak memory 216752 kb
Host smart-148ac820-2e20-49b7-b542-41b85b4c1ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956947105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2956947105
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.337520241
Short name T1049
Test name
Test status
Simulation time 18714181 ps
CPU time 1.04 seconds
Started Apr 16 12:40:52 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 205668 kb
Host smart-d9dc0c80-e2be-4a13-898a-1218b026a57d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337520241 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.337520241
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3130049176
Short name T1057
Test name
Test status
Simulation time 68179345 ps
CPU time 0.99 seconds
Started Apr 16 12:40:46 PM PDT 24
Finished Apr 16 12:40:49 PM PDT 24
Peak memory 205868 kb
Host smart-be593a47-71b6-40f9-aea9-164cc70eb405
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130049176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3130049176
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2662638237
Short name T946
Test name
Test status
Simulation time 8822607 ps
CPU time 0.78 seconds
Started Apr 16 12:40:49 PM PDT 24
Finished Apr 16 12:40:51 PM PDT 24
Peak memory 205396 kb
Host smart-87f66c37-715b-43bc-bd0e-1a4fdd917123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662638237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2662638237
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2805533271
Short name T1047
Test name
Test status
Simulation time 240824997 ps
CPU time 1.71 seconds
Started Apr 16 12:40:36 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 205972 kb
Host smart-014348d7-96ea-491e-a8db-295c66814e57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805533271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2805533271
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3061223874
Short name T107
Test name
Test status
Simulation time 467190986 ps
CPU time 9.27 seconds
Started Apr 16 12:40:49 PM PDT 24
Finished Apr 16 12:41:00 PM PDT 24
Peak memory 214396 kb
Host smart-a038fb78-371b-4f8c-9ddf-8b4ddb91cd7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061223874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3061223874
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1752702159
Short name T1041
Test name
Test status
Simulation time 1491532469 ps
CPU time 15.85 seconds
Started Apr 16 12:40:52 PM PDT 24
Finished Apr 16 12:41:09 PM PDT 24
Peak memory 214416 kb
Host smart-6063ac4f-489b-4b96-aca4-844ee2ca932e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752702159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1752702159
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4059340664
Short name T974
Test name
Test status
Simulation time 122404234 ps
CPU time 2.35 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:48 PM PDT 24
Peak memory 216284 kb
Host smart-39e11232-6cb7-4025-ae1c-9309e7d7f14a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059340664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4059340664
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3184024164
Short name T143
Test name
Test status
Simulation time 4148897046 ps
CPU time 16.69 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:57 PM PDT 24
Peak memory 205884 kb
Host smart-9cf9517e-8d01-459a-ae37-4ece8e0447ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184024164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
184024164
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2915869458
Short name T949
Test name
Test status
Simulation time 2488358520 ps
CPU time 12.39 seconds
Started Apr 16 12:40:20 PM PDT 24
Finished Apr 16 12:40:33 PM PDT 24
Peak memory 205836 kb
Host smart-cfc6106d-56ad-40fe-8117-1811ca3b57b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915869458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
915869458
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2720109007
Short name T1037
Test name
Test status
Simulation time 17411508 ps
CPU time 1.18 seconds
Started Apr 16 12:40:40 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 205820 kb
Host smart-04142bcf-74e8-45bd-b340-4d608ebff1b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720109007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
720109007
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2698503032
Short name T1046
Test name
Test status
Simulation time 80636958 ps
CPU time 1.61 seconds
Started Apr 16 12:40:21 PM PDT 24
Finished Apr 16 12:40:23 PM PDT 24
Peak memory 214196 kb
Host smart-a226318e-835e-4f76-8d4b-bde05afb24c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698503032 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2698503032
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.317162416
Short name T945
Test name
Test status
Simulation time 79386403 ps
CPU time 1.38 seconds
Started Apr 16 12:40:21 PM PDT 24
Finished Apr 16 12:40:23 PM PDT 24
Peak memory 205864 kb
Host smart-133257d5-9010-4511-9855-fc95801a7bd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317162416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.317162416
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3526893206
Short name T961
Test name
Test status
Simulation time 10181181 ps
CPU time 0.82 seconds
Started Apr 16 12:40:21 PM PDT 24
Finished Apr 16 12:40:23 PM PDT 24
Peak memory 205608 kb
Host smart-6df2332f-cec7-4da3-bc7c-0f1f2f99b684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526893206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3526893206
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2739515346
Short name T970
Test name
Test status
Simulation time 71098779 ps
CPU time 1.97 seconds
Started Apr 16 12:40:08 PM PDT 24
Finished Apr 16 12:40:11 PM PDT 24
Peak memory 205884 kb
Host smart-32eedad3-e82f-4a41-bf37-61e9569ffb30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739515346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2739515346
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3477693543
Short name T1035
Test name
Test status
Simulation time 150961503 ps
CPU time 2.54 seconds
Started Apr 16 12:40:35 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 214392 kb
Host smart-a5f8455a-6aeb-40d3-bc90-62fd77c9cb17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477693543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3477693543
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3109541500
Short name T1020
Test name
Test status
Simulation time 158047921 ps
CPU time 3.62 seconds
Started Apr 16 12:40:33 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 214088 kb
Host smart-66f1c9ab-f91e-4669-8f21-93b7b6cd54eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109541500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3109541500
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3213228849
Short name T154
Test name
Test status
Simulation time 407850163 ps
CPU time 9.72 seconds
Started Apr 16 12:40:30 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 209444 kb
Host smart-e5ddcf7d-cf63-41b4-a8f2-9d8fc2383a99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213228849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3213228849
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.840397710
Short name T1029
Test name
Test status
Simulation time 19298556 ps
CPU time 0.77 seconds
Started Apr 16 12:40:36 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 205480 kb
Host smart-fc1a7b58-71c4-49e9-a5b1-eb8e63bfb1c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840397710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.840397710
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1092183839
Short name T919
Test name
Test status
Simulation time 11683182 ps
CPU time 0.72 seconds
Started Apr 16 12:40:46 PM PDT 24
Finished Apr 16 12:40:48 PM PDT 24
Peak memory 205604 kb
Host smart-056cb8f5-3a62-4165-93c3-9195cb581337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092183839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1092183839
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.830603431
Short name T1005
Test name
Test status
Simulation time 26937010 ps
CPU time 0.78 seconds
Started Apr 16 12:40:50 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 205528 kb
Host smart-912dde47-abed-4dd3-a9dc-9348fc8097eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830603431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.830603431
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1449227964
Short name T1027
Test name
Test status
Simulation time 17189887 ps
CPU time 0.78 seconds
Started Apr 16 12:40:46 PM PDT 24
Finished Apr 16 12:40:48 PM PDT 24
Peak memory 205572 kb
Host smart-63a7addc-6578-4e0e-90a2-0de04e0d63eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449227964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1449227964
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1996997324
Short name T1007
Test name
Test status
Simulation time 9263172 ps
CPU time 0.8 seconds
Started Apr 16 12:40:46 PM PDT 24
Finished Apr 16 12:40:49 PM PDT 24
Peak memory 205580 kb
Host smart-41937aad-1aff-4bac-a4e3-c93dd246e3bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996997324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1996997324
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3937803838
Short name T943
Test name
Test status
Simulation time 10156125 ps
CPU time 0.71 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:49 PM PDT 24
Peak memory 205504 kb
Host smart-3a07287a-8bd8-416f-b68c-dd2e626aa72f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937803838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3937803838
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1976825577
Short name T1048
Test name
Test status
Simulation time 33370200 ps
CPU time 0.77 seconds
Started Apr 16 12:40:42 PM PDT 24
Finished Apr 16 12:40:45 PM PDT 24
Peak memory 205632 kb
Host smart-c3910311-406a-40e6-a38b-0cfa269a70fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976825577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1976825577
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.878639800
Short name T951
Test name
Test status
Simulation time 24787271 ps
CPU time 0.75 seconds
Started Apr 16 12:40:50 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 205500 kb
Host smart-31581c85-6d19-4553-ac6b-3660ad1ab31d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878639800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.878639800
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3426500125
Short name T908
Test name
Test status
Simulation time 40512023 ps
CPU time 0.81 seconds
Started Apr 16 12:40:46 PM PDT 24
Finished Apr 16 12:40:49 PM PDT 24
Peak memory 205632 kb
Host smart-3f9982bd-3813-4397-ab60-36ce87e9fda5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426500125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3426500125
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2882301663
Short name T940
Test name
Test status
Simulation time 34756548 ps
CPU time 0.7 seconds
Started Apr 16 12:40:42 PM PDT 24
Finished Apr 16 12:40:44 PM PDT 24
Peak memory 205612 kb
Host smart-afe67017-e5c9-4549-a8cf-f8ff7bffa837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882301663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2882301663
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.174155128
Short name T1024
Test name
Test status
Simulation time 893521412 ps
CPU time 16.15 seconds
Started Apr 16 12:40:21 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 205916 kb
Host smart-3113d8f2-cf60-4438-bc4f-4bd6572f5a7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174155128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.174155128
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1453514642
Short name T965
Test name
Test status
Simulation time 1053165925 ps
CPU time 16.74 seconds
Started Apr 16 12:40:19 PM PDT 24
Finished Apr 16 12:40:36 PM PDT 24
Peak memory 205904 kb
Host smart-754e4f7f-106a-4ffe-8cca-f0a7468bc71d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453514642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
453514642
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2236008450
Short name T1016
Test name
Test status
Simulation time 20704517 ps
CPU time 0.94 seconds
Started Apr 16 12:40:14 PM PDT 24
Finished Apr 16 12:40:16 PM PDT 24
Peak memory 205564 kb
Host smart-ec053d49-6686-4f61-8cff-b47c888c33f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236008450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
236008450
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.193427866
Short name T1025
Test name
Test status
Simulation time 100864843 ps
CPU time 2.23 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 217684 kb
Host smart-474ad642-54a4-42c0-b223-2ff5de910aa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193427866 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.193427866
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1671476607
Short name T936
Test name
Test status
Simulation time 40416606 ps
CPU time 0.88 seconds
Started Apr 16 12:40:26 PM PDT 24
Finished Apr 16 12:40:28 PM PDT 24
Peak memory 205608 kb
Host smart-2800f21f-42b0-4485-9288-85c52e363b9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671476607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1671476607
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.731773936
Short name T953
Test name
Test status
Simulation time 11548736 ps
CPU time 0.78 seconds
Started Apr 16 12:40:21 PM PDT 24
Finished Apr 16 12:40:22 PM PDT 24
Peak memory 205472 kb
Host smart-62d064c4-ecf6-43e9-bd24-9d3156e36e0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731773936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.731773936
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.187014265
Short name T999
Test name
Test status
Simulation time 247695593 ps
CPU time 2.55 seconds
Started Apr 16 12:40:24 PM PDT 24
Finished Apr 16 12:40:27 PM PDT 24
Peak memory 205896 kb
Host smart-997a51a1-7232-4b6c-99d9-1c3375de48a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187014265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.187014265
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1086346470
Short name T997
Test name
Test status
Simulation time 595348323 ps
CPU time 5.01 seconds
Started Apr 16 12:40:31 PM PDT 24
Finished Apr 16 12:40:36 PM PDT 24
Peak memory 214404 kb
Host smart-d4cbcaf8-b57e-4800-ae64-738a8a5c5584
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086346470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1086346470
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2092635246
Short name T187
Test name
Test status
Simulation time 1649210486 ps
CPU time 3.03 seconds
Started Apr 16 12:40:30 PM PDT 24
Finished Apr 16 12:40:34 PM PDT 24
Peak memory 216444 kb
Host smart-5037fff0-7ba8-49ae-a90b-f4ebacebcbd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092635246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2092635246
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2306807182
Short name T160
Test name
Test status
Simulation time 122781785 ps
CPU time 4.53 seconds
Started Apr 16 12:40:32 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 209508 kb
Host smart-fdbbfc4c-a06a-4fe9-9b78-4d9dcd91aa3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306807182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2306807182
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3626322613
Short name T931
Test name
Test status
Simulation time 11429721 ps
CPU time 0.7 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 205540 kb
Host smart-2a8d829a-c286-4502-ad61-02bdb74536d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626322613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3626322613
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2578477881
Short name T913
Test name
Test status
Simulation time 16992688 ps
CPU time 0.82 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 205552 kb
Host smart-e08b231c-f3be-4477-a20d-a8428071a974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578477881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2578477881
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3757984259
Short name T1061
Test name
Test status
Simulation time 48681191 ps
CPU time 0.74 seconds
Started Apr 16 12:40:51 PM PDT 24
Finished Apr 16 12:40:53 PM PDT 24
Peak memory 205604 kb
Host smart-e7b54333-709a-42eb-9d03-1e2b291f104e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757984259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3757984259
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2897211037
Short name T1021
Test name
Test status
Simulation time 33222648 ps
CPU time 0.68 seconds
Started Apr 16 12:40:55 PM PDT 24
Finished Apr 16 12:40:56 PM PDT 24
Peak memory 205612 kb
Host smart-895404c9-cfd9-4320-b3d8-a142b6a7c794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897211037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2897211037
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2173745126
Short name T910
Test name
Test status
Simulation time 28900307 ps
CPU time 0.74 seconds
Started Apr 16 12:40:52 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 205604 kb
Host smart-50b00f54-9224-463a-b60f-eb00cc9a8066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173745126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2173745126
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1097782306
Short name T1013
Test name
Test status
Simulation time 67119078 ps
CPU time 0.73 seconds
Started Apr 16 12:40:52 PM PDT 24
Finished Apr 16 12:40:53 PM PDT 24
Peak memory 205604 kb
Host smart-451d920a-c4b5-48dd-9f6c-b4d92bae0983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097782306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1097782306
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.796285791
Short name T923
Test name
Test status
Simulation time 26403623 ps
CPU time 0.77 seconds
Started Apr 16 12:41:07 PM PDT 24
Finished Apr 16 12:41:09 PM PDT 24
Peak memory 205592 kb
Host smart-0eab5d54-2be6-44a7-8c03-738f199134e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796285791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.796285791
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3308310827
Short name T914
Test name
Test status
Simulation time 15252750 ps
CPU time 0.88 seconds
Started Apr 16 12:40:52 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 205760 kb
Host smart-6386914c-aa55-44f8-8a89-b5e7fe7bb241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308310827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3308310827
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3171673409
Short name T932
Test name
Test status
Simulation time 14221659 ps
CPU time 0.86 seconds
Started Apr 16 12:40:46 PM PDT 24
Finished Apr 16 12:40:48 PM PDT 24
Peak memory 205740 kb
Host smart-6d8d9de2-85c8-40c7-8ad0-d95c2c71dbf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171673409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3171673409
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1648494124
Short name T911
Test name
Test status
Simulation time 25827816 ps
CPU time 0.79 seconds
Started Apr 16 12:40:55 PM PDT 24
Finished Apr 16 12:40:57 PM PDT 24
Peak memory 205488 kb
Host smart-a4de2198-a1af-414d-92f3-0f3dc226a776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648494124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1648494124
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1516609807
Short name T134
Test name
Test status
Simulation time 2526803652 ps
CPU time 9.05 seconds
Started Apr 16 12:40:36 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 206020 kb
Host smart-651763fa-0bdb-450c-af9e-c29992f06228
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516609807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
516609807
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2584403328
Short name T966
Test name
Test status
Simulation time 284656824 ps
CPU time 6.32 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 205992 kb
Host smart-49190c44-7c08-40f6-b271-ecf7a0c7eeb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584403328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
584403328
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1953571693
Short name T1055
Test name
Test status
Simulation time 42472277 ps
CPU time 0.91 seconds
Started Apr 16 12:40:30 PM PDT 24
Finished Apr 16 12:40:32 PM PDT 24
Peak memory 205656 kb
Host smart-d55bc607-ec7f-46ab-a5b6-dc276cd7311c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953571693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
953571693
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2220186846
Short name T1022
Test name
Test status
Simulation time 58660123 ps
CPU time 1.13 seconds
Started Apr 16 12:40:24 PM PDT 24
Finished Apr 16 12:40:25 PM PDT 24
Peak memory 214220 kb
Host smart-feebea83-6175-491d-a4ce-13ab27fad436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220186846 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2220186846
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.661014360
Short name T990
Test name
Test status
Simulation time 61390818 ps
CPU time 0.92 seconds
Started Apr 16 12:40:37 PM PDT 24
Finished Apr 16 12:40:39 PM PDT 24
Peak memory 205688 kb
Host smart-8beeb94a-681f-4bf9-be52-53f9a8a9a241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661014360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.661014360
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1661755508
Short name T1066
Test name
Test status
Simulation time 39795735 ps
CPU time 0.78 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:41 PM PDT 24
Peak memory 205460 kb
Host smart-df751426-b56d-4486-9b9b-c194e292b720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661755508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1661755508
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3691663987
Short name T930
Test name
Test status
Simulation time 130537238 ps
CPU time 2.35 seconds
Started Apr 16 12:40:24 PM PDT 24
Finished Apr 16 12:40:27 PM PDT 24
Peak memory 205972 kb
Host smart-ff96bc6f-8688-4140-82ed-52983042dd5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691663987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3691663987
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1018542514
Short name T964
Test name
Test status
Simulation time 1021412146 ps
CPU time 9.89 seconds
Started Apr 16 12:40:42 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 214324 kb
Host smart-4847c1df-637d-482c-8d1b-83ae6ffa113d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018542514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1018542514
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3078612663
Short name T937
Test name
Test status
Simulation time 271016366 ps
CPU time 8.61 seconds
Started Apr 16 12:40:26 PM PDT 24
Finished Apr 16 12:40:36 PM PDT 24
Peak memory 220484 kb
Host smart-5835dad3-0c7f-45e0-96dd-4b5e05758b3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078612663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3078612663
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3579080675
Short name T915
Test name
Test status
Simulation time 20309710 ps
CPU time 1.63 seconds
Started Apr 16 12:40:33 PM PDT 24
Finished Apr 16 12:40:36 PM PDT 24
Peak memory 214032 kb
Host smart-d7a96d94-825a-4e02-9acd-130be974f844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579080675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3579080675
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2984265107
Short name T1034
Test name
Test status
Simulation time 9396755 ps
CPU time 0.68 seconds
Started Apr 16 12:40:55 PM PDT 24
Finished Apr 16 12:40:57 PM PDT 24
Peak memory 205552 kb
Host smart-fcb567e5-fb73-482e-944a-1664da9edb46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984265107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2984265107
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.954553611
Short name T1039
Test name
Test status
Simulation time 150285590 ps
CPU time 0.87 seconds
Started Apr 16 12:40:48 PM PDT 24
Finished Apr 16 12:41:00 PM PDT 24
Peak memory 204784 kb
Host smart-6d594d86-52de-451b-ae6f-44f19bf48e00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954553611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.954553611
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2977169967
Short name T973
Test name
Test status
Simulation time 167136475 ps
CPU time 0.8 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:50 PM PDT 24
Peak memory 205580 kb
Host smart-6f2f1e53-f247-4a3f-8b8e-234dfb517dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977169967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2977169967
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2714716935
Short name T1056
Test name
Test status
Simulation time 15255285 ps
CPU time 0.8 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:50 PM PDT 24
Peak memory 205596 kb
Host smart-e942ec04-23d5-4d8b-8e92-7415e64c64e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714716935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2714716935
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2881416954
Short name T926
Test name
Test status
Simulation time 17918460 ps
CPU time 0.8 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:49 PM PDT 24
Peak memory 205532 kb
Host smart-1acd157f-5463-47b2-a14f-03e89940a0bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881416954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2881416954
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.4071968481
Short name T907
Test name
Test status
Simulation time 15796062 ps
CPU time 0.77 seconds
Started Apr 16 12:40:50 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 205604 kb
Host smart-827445c7-0f79-4958-a666-4963b5012df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071968481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4071968481
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3935840544
Short name T912
Test name
Test status
Simulation time 70723318 ps
CPU time 0.79 seconds
Started Apr 16 12:40:48 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 204424 kb
Host smart-89bacb0a-9cad-431a-a6f3-d108d14c7f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935840544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3935840544
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3766084576
Short name T1044
Test name
Test status
Simulation time 55548548 ps
CPU time 0.83 seconds
Started Apr 16 12:40:46 PM PDT 24
Finished Apr 16 12:40:49 PM PDT 24
Peak memory 205604 kb
Host smart-bb72eb3c-e0fc-49da-99a0-49776d3963ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766084576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3766084576
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4214836714
Short name T1008
Test name
Test status
Simulation time 19858821 ps
CPU time 0.79 seconds
Started Apr 16 12:41:02 PM PDT 24
Finished Apr 16 12:41:03 PM PDT 24
Peak memory 205424 kb
Host smart-d78aa78c-fef2-427f-8389-5644b741979d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214836714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4214836714
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1844323393
Short name T1012
Test name
Test status
Simulation time 23504961 ps
CPU time 0.9 seconds
Started Apr 16 12:40:54 PM PDT 24
Finished Apr 16 12:40:56 PM PDT 24
Peak memory 205616 kb
Host smart-2e73b495-f3e0-4205-b9b6-aa60be50f8ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844323393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1844323393
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3164291142
Short name T1033
Test name
Test status
Simulation time 34252627 ps
CPU time 1.19 seconds
Started Apr 16 12:40:37 PM PDT 24
Finished Apr 16 12:40:39 PM PDT 24
Peak memory 206008 kb
Host smart-9022c432-497a-433e-85d7-c9beb0e1986e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164291142 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3164291142
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3097501016
Short name T933
Test name
Test status
Simulation time 64955131 ps
CPU time 1.15 seconds
Started Apr 16 12:40:33 PM PDT 24
Finished Apr 16 12:40:34 PM PDT 24
Peak memory 205924 kb
Host smart-86f37102-b016-4c0c-b7a9-238db3c99a55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097501016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3097501016
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1166725463
Short name T941
Test name
Test status
Simulation time 16747510 ps
CPU time 0.9 seconds
Started Apr 16 12:40:26 PM PDT 24
Finished Apr 16 12:40:28 PM PDT 24
Peak memory 205788 kb
Host smart-e9a30f88-cf26-45f0-b0a0-513ce696037e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166725463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1166725463
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3933481284
Short name T138
Test name
Test status
Simulation time 208368317 ps
CPU time 2.37 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 205828 kb
Host smart-d665948e-e631-4e60-9380-586725eb9a85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933481284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3933481284
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.233333362
Short name T995
Test name
Test status
Simulation time 128742067 ps
CPU time 2.56 seconds
Started Apr 16 12:40:35 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 214352 kb
Host smart-a3686721-aecb-49c5-9a2a-aa509f9ddf59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233333362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.233333362
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4147784684
Short name T957
Test name
Test status
Simulation time 836278027 ps
CPU time 5.16 seconds
Started Apr 16 12:40:37 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 220348 kb
Host smart-d605bb45-45d8-4d60-b3c4-3a7562483f76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147784684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.4147784684
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.694110624
Short name T906
Test name
Test status
Simulation time 105033183 ps
CPU time 1.88 seconds
Started Apr 16 12:40:52 PM PDT 24
Finished Apr 16 12:40:55 PM PDT 24
Peak memory 214032 kb
Host smart-f45f0cf8-15c7-4bf1-a126-ae777a610019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694110624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.694110624
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3719647053
Short name T155
Test name
Test status
Simulation time 4111554935 ps
CPU time 11.93 seconds
Started Apr 16 12:40:26 PM PDT 24
Finished Apr 16 12:40:39 PM PDT 24
Peak memory 209400 kb
Host smart-84e1a88a-76bd-4c89-9da7-c4b025eb52a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719647053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3719647053
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2676977924
Short name T928
Test name
Test status
Simulation time 33175502 ps
CPU time 2.26 seconds
Started Apr 16 12:40:38 PM PDT 24
Finished Apr 16 12:40:42 PM PDT 24
Peak memory 214112 kb
Host smart-8bb65141-a058-42b1-a64f-7b045165a258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676977924 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2676977924
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1299736607
Short name T137
Test name
Test status
Simulation time 14705530 ps
CPU time 1.21 seconds
Started Apr 16 12:40:35 PM PDT 24
Finished Apr 16 12:40:37 PM PDT 24
Peak memory 205864 kb
Host smart-af545c61-5233-453d-8994-0b3761fca584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299736607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1299736607
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1212761617
Short name T916
Test name
Test status
Simulation time 17766187 ps
CPU time 0.7 seconds
Started Apr 16 12:40:50 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 205512 kb
Host smart-fedf4f60-88bf-4896-acca-883cee1a93c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212761617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1212761617
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1126357034
Short name T1045
Test name
Test status
Simulation time 71935691 ps
CPU time 1.54 seconds
Started Apr 16 12:40:27 PM PDT 24
Finished Apr 16 12:40:30 PM PDT 24
Peak memory 205836 kb
Host smart-f24ef688-76c5-4d80-9821-073e089f59e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126357034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1126357034
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2233497131
Short name T1052
Test name
Test status
Simulation time 28918852 ps
CPU time 1.52 seconds
Started Apr 16 12:40:29 PM PDT 24
Finished Apr 16 12:40:31 PM PDT 24
Peak memory 214284 kb
Host smart-6d74bcd0-5d71-4e4c-a698-57d13cb84a48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233497131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2233497131
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2024198605
Short name T112
Test name
Test status
Simulation time 403677206 ps
CPU time 7.79 seconds
Started Apr 16 12:40:37 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 214324 kb
Host smart-e19e072b-a110-4afb-8c73-400f057cd31c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024198605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2024198605
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3080705237
Short name T1042
Test name
Test status
Simulation time 480153049 ps
CPU time 3.59 seconds
Started Apr 16 12:40:45 PM PDT 24
Finished Apr 16 12:40:50 PM PDT 24
Peak memory 216316 kb
Host smart-32e61732-b7a5-485f-8281-15a13e653150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080705237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3080705237
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.943931877
Short name T148
Test name
Test status
Simulation time 61302271 ps
CPU time 3.43 seconds
Started Apr 16 12:40:32 PM PDT 24
Finished Apr 16 12:40:36 PM PDT 24
Peak memory 217956 kb
Host smart-abccbbc1-165c-4d0c-9399-a45f1e4fa2b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943931877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
943931877
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1153058178
Short name T985
Test name
Test status
Simulation time 20174287 ps
CPU time 1.55 seconds
Started Apr 16 12:40:27 PM PDT 24
Finished Apr 16 12:40:29 PM PDT 24
Peak memory 205940 kb
Host smart-d4ba0ae8-a5ae-4c4e-8d3f-163be6b6a457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153058178 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1153058178
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1050418385
Short name T927
Test name
Test status
Simulation time 9879090 ps
CPU time 1.02 seconds
Started Apr 16 12:40:43 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 205824 kb
Host smart-9ade73f6-5023-46de-8895-2c8346be320c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050418385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1050418385
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3823583581
Short name T917
Test name
Test status
Simulation time 29057477 ps
CPU time 0.72 seconds
Started Apr 16 12:40:49 PM PDT 24
Finished Apr 16 12:40:52 PM PDT 24
Peak memory 205560 kb
Host smart-73d331e5-ab17-451b-8460-dfdfcd0da10a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823583581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3823583581
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3436220408
Short name T956
Test name
Test status
Simulation time 122663243 ps
CPU time 4.08 seconds
Started Apr 16 12:40:33 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 205876 kb
Host smart-e6244d08-a4b0-4a71-89f3-6d45fb6a0e98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436220408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3436220408
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.321712512
Short name T1063
Test name
Test status
Simulation time 202378379 ps
CPU time 2.19 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:48 PM PDT 24
Peak memory 222496 kb
Host smart-9e40046a-c448-4d75-b732-a2e6ce74791f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321712512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.321712512
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.422580146
Short name T1051
Test name
Test status
Simulation time 489025182 ps
CPU time 4.68 seconds
Started Apr 16 12:40:48 PM PDT 24
Finished Apr 16 12:40:55 PM PDT 24
Peak memory 214300 kb
Host smart-db8368bd-9bc8-49e1-9e35-7a4a18a25fca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422580146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.422580146
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3756864507
Short name T922
Test name
Test status
Simulation time 31269972 ps
CPU time 2.07 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 214056 kb
Host smart-01f2b277-82ca-407a-a4d6-aecd2fd532fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756864507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3756864507
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1596686103
Short name T924
Test name
Test status
Simulation time 308611239 ps
CPU time 4.89 seconds
Started Apr 16 12:40:39 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 209520 kb
Host smart-0ecfeae2-7e43-4945-b830-84759334fbbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596686103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1596686103
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4144903839
Short name T1009
Test name
Test status
Simulation time 53468847 ps
CPU time 1.56 seconds
Started Apr 16 12:40:51 PM PDT 24
Finished Apr 16 12:40:54 PM PDT 24
Peak memory 214256 kb
Host smart-0006cdd2-cb07-41b3-87d8-605abe959a3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144903839 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4144903839
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3720075695
Short name T968
Test name
Test status
Simulation time 72412847 ps
CPU time 1.01 seconds
Started Apr 16 12:40:42 PM PDT 24
Finished Apr 16 12:40:45 PM PDT 24
Peak memory 205744 kb
Host smart-e51466c7-a595-4897-8722-458e359eeb27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720075695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3720075695
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2480270646
Short name T1054
Test name
Test status
Simulation time 11965180 ps
CPU time 0.73 seconds
Started Apr 16 12:40:38 PM PDT 24
Finished Apr 16 12:40:40 PM PDT 24
Peak memory 205596 kb
Host smart-b5c9079a-b09f-4f20-b9d0-05ede46d5749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480270646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2480270646
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.690312148
Short name T1002
Test name
Test status
Simulation time 36218377 ps
CPU time 1.98 seconds
Started Apr 16 12:40:36 PM PDT 24
Finished Apr 16 12:40:39 PM PDT 24
Peak memory 205840 kb
Host smart-57252bc9-3685-4d72-bb3d-5c6f307eb2d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690312148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.690312148
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1338841543
Short name T1062
Test name
Test status
Simulation time 353154045 ps
CPU time 5.9 seconds
Started Apr 16 12:40:36 PM PDT 24
Finished Apr 16 12:40:43 PM PDT 24
Peak memory 214396 kb
Host smart-1e51eb3b-ed96-4fa6-9cf9-f1f4c330a88c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338841543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1338841543
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1316332557
Short name T111
Test name
Test status
Simulation time 1811840652 ps
CPU time 15.41 seconds
Started Apr 16 12:40:30 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 214388 kb
Host smart-b88eb31c-04a1-4dd1-812f-04b38db56efa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316332557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1316332557
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1402153924
Short name T938
Test name
Test status
Simulation time 269764524 ps
CPU time 4.59 seconds
Started Apr 16 12:40:44 PM PDT 24
Finished Apr 16 12:40:50 PM PDT 24
Peak memory 214124 kb
Host smart-157765bb-8306-4789-91dd-b5db3cbce5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402153924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1402153924
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3578017254
Short name T165
Test name
Test status
Simulation time 409655064 ps
CPU time 6.89 seconds
Started Apr 16 12:40:31 PM PDT 24
Finished Apr 16 12:40:38 PM PDT 24
Peak memory 214100 kb
Host smart-45ca7a74-a7a4-4071-94dc-9b54fe20b5e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578017254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3578017254
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1025999669
Short name T952
Test name
Test status
Simulation time 29656324 ps
CPU time 2.28 seconds
Started Apr 16 12:40:38 PM PDT 24
Finished Apr 16 12:40:42 PM PDT 24
Peak memory 214332 kb
Host smart-e93ebd10-7344-46ff-807b-1d39d96b64da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025999669 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1025999669
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.175025171
Short name T1030
Test name
Test status
Simulation time 103790897 ps
CPU time 1.21 seconds
Started Apr 16 12:40:45 PM PDT 24
Finished Apr 16 12:40:48 PM PDT 24
Peak memory 205928 kb
Host smart-1bff30b4-c67c-463e-ace5-fce19b628ebe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175025171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.175025171
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4270026972
Short name T978
Test name
Test status
Simulation time 37037075 ps
CPU time 0.77 seconds
Started Apr 16 12:40:40 PM PDT 24
Finished Apr 16 12:40:42 PM PDT 24
Peak memory 205560 kb
Host smart-b8b3bd82-0c39-4aac-a07d-d6f56b2c2972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270026972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4270026972
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1935999028
Short name T994
Test name
Test status
Simulation time 175807903 ps
CPU time 2.69 seconds
Started Apr 16 12:40:43 PM PDT 24
Finished Apr 16 12:40:47 PM PDT 24
Peak memory 205812 kb
Host smart-f1f53302-a0ed-4810-83c6-7fc1fa106dd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935999028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1935999028
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3034278269
Short name T987
Test name
Test status
Simulation time 357443916 ps
CPU time 3.87 seconds
Started Apr 16 12:40:41 PM PDT 24
Finished Apr 16 12:40:46 PM PDT 24
Peak memory 214412 kb
Host smart-8007ba84-781f-4540-ba9c-233adf358220
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034278269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3034278269
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2128102883
Short name T1059
Test name
Test status
Simulation time 597657308 ps
CPU time 7.28 seconds
Started Apr 16 12:40:36 PM PDT 24
Finished Apr 16 12:40:44 PM PDT 24
Peak memory 214272 kb
Host smart-e2e9dd48-c66e-4e5a-9a2c-a1a57c58b31e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128102883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2128102883
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2760845997
Short name T905
Test name
Test status
Simulation time 44721285 ps
CPU time 2.49 seconds
Started Apr 16 12:40:47 PM PDT 24
Finished Apr 16 12:40:51 PM PDT 24
Peak memory 217272 kb
Host smart-f04faca5-f122-4cb4-ab46-0b1a5c93a1f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760845997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2760845997
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2593007628
Short name T776
Test name
Test status
Simulation time 46115076 ps
CPU time 0.79 seconds
Started Apr 16 12:44:59 PM PDT 24
Finished Apr 16 12:45:02 PM PDT 24
Peak memory 206220 kb
Host smart-9e804d58-6108-4d9b-ba60-992f14a1e6bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593007628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2593007628
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.4177311000
Short name T268
Test name
Test status
Simulation time 1000911598 ps
CPU time 26.95 seconds
Started Apr 16 12:44:50 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 214656 kb
Host smart-bf3a7c6b-ec32-4a66-8163-5382917f7b08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177311000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.4177311000
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.275896941
Short name T511
Test name
Test status
Simulation time 46830501 ps
CPU time 2.3 seconds
Started Apr 16 12:44:54 PM PDT 24
Finished Apr 16 12:44:57 PM PDT 24
Peak memory 209240 kb
Host smart-8c9555c9-669f-4154-a484-99c511da9127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275896941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.275896941
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2705290862
Short name T87
Test name
Test status
Simulation time 112605134 ps
CPU time 4.84 seconds
Started Apr 16 12:44:45 PM PDT 24
Finished Apr 16 12:44:51 PM PDT 24
Peak memory 221988 kb
Host smart-5cab8fd9-d5c2-4269-a490-5c521bc3300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705290862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2705290862
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3453981810
Short name T855
Test name
Test status
Simulation time 585750793 ps
CPU time 13.12 seconds
Started Apr 16 12:44:42 PM PDT 24
Finished Apr 16 12:44:57 PM PDT 24
Peak memory 222720 kb
Host smart-be637cdc-efdf-4640-818b-9af897f69aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453981810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3453981810
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2906870261
Short name T606
Test name
Test status
Simulation time 133469366 ps
CPU time 2.36 seconds
Started Apr 16 12:44:44 PM PDT 24
Finished Apr 16 12:44:48 PM PDT 24
Peak memory 215480 kb
Host smart-0b071163-152c-410c-be83-04240e51c0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906870261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2906870261
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2380104872
Short name T671
Test name
Test status
Simulation time 1295823578 ps
CPU time 33.71 seconds
Started Apr 16 12:44:49 PM PDT 24
Finished Apr 16 12:45:23 PM PDT 24
Peak memory 222756 kb
Host smart-c0c11476-036d-4683-ab30-e15ad5aed604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380104872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2380104872
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2905529625
Short name T94
Test name
Test status
Simulation time 2166492228 ps
CPU time 30.24 seconds
Started Apr 16 12:44:46 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 243584 kb
Host smart-07895b62-a669-40fd-93a5-a9c4c4fc3053
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905529625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2905529625
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1331674372
Short name T323
Test name
Test status
Simulation time 1677803452 ps
CPU time 39.73 seconds
Started Apr 16 12:44:43 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 208608 kb
Host smart-ebeb8bc9-a927-405d-9270-a5aaaf1c1ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331674372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1331674372
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1030001660
Short name T581
Test name
Test status
Simulation time 167011882 ps
CPU time 4.89 seconds
Started Apr 16 12:44:54 PM PDT 24
Finished Apr 16 12:45:00 PM PDT 24
Peak memory 209056 kb
Host smart-9e5c0ab7-af88-4998-a973-92ac84d7b010
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030001660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1030001660
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.855656222
Short name T528
Test name
Test status
Simulation time 58471984 ps
CPU time 3.21 seconds
Started Apr 16 12:44:48 PM PDT 24
Finished Apr 16 12:44:53 PM PDT 24
Peak memory 208836 kb
Host smart-3689e216-0dcd-4299-a038-b7140a4396d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855656222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.855656222
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1893808130
Short name T779
Test name
Test status
Simulation time 1025520496 ps
CPU time 14.58 seconds
Started Apr 16 12:44:53 PM PDT 24
Finished Apr 16 12:45:08 PM PDT 24
Peak memory 208692 kb
Host smart-94916468-4d40-4778-92d2-012ff6d7be9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893808130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1893808130
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.359802659
Short name T66
Test name
Test status
Simulation time 583974800 ps
CPU time 5.35 seconds
Started Apr 16 12:44:45 PM PDT 24
Finished Apr 16 12:44:52 PM PDT 24
Peak memory 210028 kb
Host smart-1b5adcfc-c04b-4003-897e-c865b7db0116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359802659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.359802659
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.320621833
Short name T762
Test name
Test status
Simulation time 7894353657 ps
CPU time 43.92 seconds
Started Apr 16 12:44:32 PM PDT 24
Finished Apr 16 12:45:17 PM PDT 24
Peak memory 208012 kb
Host smart-3f8a3dc7-9c92-409c-8807-4216d047331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320621833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.320621833
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.478329786
Short name T211
Test name
Test status
Simulation time 421061728 ps
CPU time 16.96 seconds
Started Apr 16 12:44:57 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 222836 kb
Host smart-0d4dc291-c24c-4619-a7b6-3bc4153377a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478329786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.478329786
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1975727665
Short name T825
Test name
Test status
Simulation time 417200067 ps
CPU time 7.64 seconds
Started Apr 16 12:45:04 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 208628 kb
Host smart-dbe792ef-c49d-4d05-9c78-2634bee57593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975727665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1975727665
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2691133682
Short name T505
Test name
Test status
Simulation time 76962445 ps
CPU time 2.01 seconds
Started Apr 16 12:44:45 PM PDT 24
Finished Apr 16 12:44:49 PM PDT 24
Peak memory 210004 kb
Host smart-3fef4d6c-4014-4b30-8673-be9cd9496062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691133682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2691133682
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4158381996
Short name T774
Test name
Test status
Simulation time 56128646 ps
CPU time 0.88 seconds
Started Apr 16 12:44:54 PM PDT 24
Finished Apr 16 12:44:56 PM PDT 24
Peak memory 206448 kb
Host smart-951bc91d-1703-4d97-8379-1e1f80fd21ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158381996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4158381996
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2339037220
Short name T730
Test name
Test status
Simulation time 29548762 ps
CPU time 1.75 seconds
Started Apr 16 12:44:41 PM PDT 24
Finished Apr 16 12:44:45 PM PDT 24
Peak memory 207608 kb
Host smart-dfb9fd57-dd1c-4152-9491-0c316c0fb08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339037220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2339037220
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1626383028
Short name T86
Test name
Test status
Simulation time 2072775277 ps
CPU time 6.56 seconds
Started Apr 16 12:44:46 PM PDT 24
Finished Apr 16 12:44:53 PM PDT 24
Peak memory 210256 kb
Host smart-a4898224-1dea-4d16-ab51-7299e7b11d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626383028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1626383028
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1199194432
Short name T284
Test name
Test status
Simulation time 817592615 ps
CPU time 7.48 seconds
Started Apr 16 12:44:40 PM PDT 24
Finished Apr 16 12:44:48 PM PDT 24
Peak memory 222740 kb
Host smart-c8c0c13d-436a-4bdf-999f-6ad1169460f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199194432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1199194432
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3225797101
Short name T612
Test name
Test status
Simulation time 183470279 ps
CPU time 3.25 seconds
Started Apr 16 12:44:55 PM PDT 24
Finished Apr 16 12:44:59 PM PDT 24
Peak memory 209864 kb
Host smart-99243c6e-0bd2-443f-bb14-fd349e874f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225797101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3225797101
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1105345984
Short name T660
Test name
Test status
Simulation time 225426101 ps
CPU time 7.55 seconds
Started Apr 16 12:44:46 PM PDT 24
Finished Apr 16 12:44:55 PM PDT 24
Peak memory 208852 kb
Host smart-acad1d8f-843b-4907-a695-93d97e5b71d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105345984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1105345984
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4280419396
Short name T435
Test name
Test status
Simulation time 172422597 ps
CPU time 2.79 seconds
Started Apr 16 12:44:46 PM PDT 24
Finished Apr 16 12:44:50 PM PDT 24
Peak memory 206892 kb
Host smart-0086db7d-dcd0-4a09-8473-a60ff54237c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280419396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4280419396
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.244223499
Short name T312
Test name
Test status
Simulation time 41239721 ps
CPU time 1.83 seconds
Started Apr 16 12:44:49 PM PDT 24
Finished Apr 16 12:44:51 PM PDT 24
Peak memory 206908 kb
Host smart-027e46b1-5952-4fc3-a39e-43439262aa9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244223499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.244223499
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.800560391
Short name T478
Test name
Test status
Simulation time 241851958 ps
CPU time 4.11 seconds
Started Apr 16 12:44:39 PM PDT 24
Finished Apr 16 12:44:44 PM PDT 24
Peak memory 208816 kb
Host smart-7f27e0c8-fd7c-4709-a059-8446fadfbb91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800560391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.800560391
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.973517526
Short name T529
Test name
Test status
Simulation time 32916311 ps
CPU time 2.23 seconds
Started Apr 16 12:44:54 PM PDT 24
Finished Apr 16 12:44:57 PM PDT 24
Peak memory 207088 kb
Host smart-683ea65c-8e37-4d16-82ba-a402feb6d948
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973517526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.973517526
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1948192746
Short name T386
Test name
Test status
Simulation time 192825431 ps
CPU time 2.41 seconds
Started Apr 16 12:44:55 PM PDT 24
Finished Apr 16 12:44:58 PM PDT 24
Peak memory 218568 kb
Host smart-7cbf442c-98da-4994-9e6e-3f771aab8569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948192746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1948192746
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1596951699
Short name T847
Test name
Test status
Simulation time 70373430 ps
CPU time 2.35 seconds
Started Apr 16 12:44:30 PM PDT 24
Finished Apr 16 12:44:34 PM PDT 24
Peak memory 207092 kb
Host smart-8a1cde1e-1e0d-4c5b-836a-d297d91542d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596951699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1596951699
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2900392875
Short name T462
Test name
Test status
Simulation time 120791371 ps
CPU time 3.67 seconds
Started Apr 16 12:44:42 PM PDT 24
Finished Apr 16 12:44:47 PM PDT 24
Peak memory 208140 kb
Host smart-6f4aea8f-d5f8-40b5-a535-9a2f22eb45c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900392875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2900392875
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2757112265
Short name T103
Test name
Test status
Simulation time 128653269 ps
CPU time 2.14 seconds
Started Apr 16 12:44:44 PM PDT 24
Finished Apr 16 12:44:47 PM PDT 24
Peak memory 210056 kb
Host smart-63827422-48ed-442e-85de-f045dddb8c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757112265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2757112265
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2452226324
Short name T796
Test name
Test status
Simulation time 33931907 ps
CPU time 0.75 seconds
Started Apr 16 12:45:17 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 206176 kb
Host smart-9eac7f49-79f5-4b5b-8c66-63cb05ca10fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452226324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2452226324
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1008224925
Short name T20
Test name
Test status
Simulation time 192815293 ps
CPU time 4.21 seconds
Started Apr 16 12:45:01 PM PDT 24
Finished Apr 16 12:45:07 PM PDT 24
Peak memory 210516 kb
Host smart-b71c4e53-f0b9-4c44-b740-87b0e618fbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008224925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1008224925
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1557979146
Short name T652
Test name
Test status
Simulation time 1877982951 ps
CPU time 16.48 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:29 PM PDT 24
Peak memory 209764 kb
Host smart-32c0bd46-e95e-4c73-8d9b-c8bd0a328278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557979146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1557979146
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1037863651
Short name T333
Test name
Test status
Simulation time 63937858 ps
CPU time 2.79 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 211268 kb
Host smart-de68d926-48d1-44a3-885a-86f8412e2f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037863651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1037863651
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2475581621
Short name T227
Test name
Test status
Simulation time 141757149 ps
CPU time 4.09 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 220596 kb
Host smart-a669aa5d-c3a8-4f80-9c84-62672d707482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475581621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2475581621
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3775180531
Short name T490
Test name
Test status
Simulation time 190322986 ps
CPU time 4.4 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 208192 kb
Host smart-b48476d3-2ad4-4656-858d-b9fe8b736242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775180531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3775180531
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2020978761
Short name T197
Test name
Test status
Simulation time 3346481587 ps
CPU time 22.58 seconds
Started Apr 16 12:45:02 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 208292 kb
Host smart-ebeb4063-707a-4016-b57c-5ac07f248a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020978761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2020978761
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.310755598
Short name T63
Test name
Test status
Simulation time 25950963 ps
CPU time 1.7 seconds
Started Apr 16 12:45:04 PM PDT 24
Finished Apr 16 12:45:08 PM PDT 24
Peak memory 207208 kb
Host smart-708ca9b3-0fae-460b-89d3-1301b89718dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310755598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.310755598
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3450150544
Short name T711
Test name
Test status
Simulation time 171672924 ps
CPU time 4.84 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:17 PM PDT 24
Peak memory 208112 kb
Host smart-1f2b38b9-788f-40b0-9d30-0bf98b207156
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450150544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3450150544
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1265438539
Short name T681
Test name
Test status
Simulation time 40065405 ps
CPU time 1.77 seconds
Started Apr 16 12:45:05 PM PDT 24
Finished Apr 16 12:45:09 PM PDT 24
Peak memory 207564 kb
Host smart-9838d9f2-8380-4186-aa05-cd2ebfceb2c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265438539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1265438539
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.643873418
Short name T644
Test name
Test status
Simulation time 1465253162 ps
CPU time 21.82 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 209740 kb
Host smart-0a61b496-da91-4202-b6b8-55bac2660bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643873418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.643873418
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1407158620
Short name T472
Test name
Test status
Simulation time 360682507 ps
CPU time 2.35 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:13 PM PDT 24
Peak memory 207308 kb
Host smart-c90602e9-345b-4cfe-953d-a5afd97ab504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407158620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1407158620
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2080381834
Short name T60
Test name
Test status
Simulation time 5354531911 ps
CPU time 16.38 seconds
Started Apr 16 12:45:15 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 217600 kb
Host smart-552e70b0-46dc-4b30-bd94-1e9d5fe0bd80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080381834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2080381834
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.118274989
Short name T201
Test name
Test status
Simulation time 140427577 ps
CPU time 3.55 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 207664 kb
Host smart-353e6dea-123b-461d-b59f-875f2d145f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118274989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.118274989
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3799837067
Short name T359
Test name
Test status
Simulation time 82433493 ps
CPU time 2.18 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 210068 kb
Host smart-0bac342f-e357-4a28-8c56-abb575a0b7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799837067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3799837067
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3452953530
Short name T419
Test name
Test status
Simulation time 13133119 ps
CPU time 0.7 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:13 PM PDT 24
Peak memory 206056 kb
Host smart-d3b7cd42-2475-45f7-9616-aaa9f4c43458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452953530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3452953530
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2001932418
Short name T710
Test name
Test status
Simulation time 219677040 ps
CPU time 11.9 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 215804 kb
Host smart-a9d8084f-1171-4d58-8243-2de6d54cab80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001932418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2001932418
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2889533557
Short name T525
Test name
Test status
Simulation time 256741448 ps
CPU time 3.7 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 209000 kb
Host smart-34e03e95-b429-43b7-96f0-706846d60da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889533557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2889533557
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3828759179
Short name T622
Test name
Test status
Simulation time 33108986 ps
CPU time 2.74 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 207820 kb
Host smart-8d788834-92ea-43d3-8db1-d73b451d5c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828759179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3828759179
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3140098029
Short name T196
Test name
Test status
Simulation time 177937923 ps
CPU time 5.37 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:26 PM PDT 24
Peak memory 210044 kb
Host smart-e05b49fb-195a-48f9-b454-3a3852947ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140098029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3140098029
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.605999803
Short name T883
Test name
Test status
Simulation time 1435942786 ps
CPU time 7.52 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 208848 kb
Host smart-d0410957-0267-4f90-ba5b-7fe7cb387a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605999803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.605999803
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2770226837
Short name T476
Test name
Test status
Simulation time 131483487 ps
CPU time 3.47 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:45:45 PM PDT 24
Peak memory 207292 kb
Host smart-3874fddd-6e09-4811-b34c-a74f6ac977a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770226837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2770226837
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2493904147
Short name T613
Test name
Test status
Simulation time 554620298 ps
CPU time 4.41 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 207108 kb
Host smart-6debc4e1-5cf1-41bc-bc5c-582038faca53
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493904147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2493904147
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1535999502
Short name T330
Test name
Test status
Simulation time 52117245 ps
CPU time 2.79 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 207124 kb
Host smart-b94111f7-4eaa-43a9-8444-0ae8f37430b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535999502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1535999502
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2740357484
Short name T547
Test name
Test status
Simulation time 183608722 ps
CPU time 4.05 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 218448 kb
Host smart-ac5eabe0-777a-40ee-9489-6c84f2843a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740357484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2740357484
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2480583491
Short name T866
Test name
Test status
Simulation time 731788221 ps
CPU time 4.82 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 208672 kb
Host smart-8fd05dd1-6c43-4fa4-850d-5f2ec1b80f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480583491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2480583491
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1949589920
Short name T224
Test name
Test status
Simulation time 1135145489 ps
CPU time 27.77 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:37 PM PDT 24
Peak memory 220576 kb
Host smart-4cef5ae4-406e-45dc-9a14-41099911ca8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949589920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1949589920
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.750932100
Short name T347
Test name
Test status
Simulation time 212128844 ps
CPU time 5.05 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 207632 kb
Host smart-69b64e73-4000-4f58-bc38-d224054e3be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750932100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.750932100
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.383727202
Short name T357
Test name
Test status
Simulation time 647068572 ps
CPU time 13.48 seconds
Started Apr 16 12:45:15 PM PDT 24
Finished Apr 16 12:45:31 PM PDT 24
Peak memory 211264 kb
Host smart-a8823d7c-c3de-43b8-913d-2f1413de58e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383727202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.383727202
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.377546587
Short name T878
Test name
Test status
Simulation time 25272202 ps
CPU time 0.78 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 206284 kb
Host smart-e49ea74b-0eec-4ae6-95aa-988d497925f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377546587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.377546587
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3704604349
Short name T880
Test name
Test status
Simulation time 678418002 ps
CPU time 5.51 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 209896 kb
Host smart-4bf30746-0860-475c-983d-2ba46abd6e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704604349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3704604349
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.665429852
Short name T554
Test name
Test status
Simulation time 416778676 ps
CPU time 3.71 seconds
Started Apr 16 12:45:19 PM PDT 24
Finished Apr 16 12:45:25 PM PDT 24
Peak memory 208108 kb
Host smart-c3728192-50a2-4b63-92a0-4f9c3550c4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665429852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.665429852
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.148529126
Short name T77
Test name
Test status
Simulation time 948571458 ps
CPU time 4.78 seconds
Started Apr 16 12:45:13 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 214624 kb
Host smart-3988b526-baf4-424b-8fa8-8d788cd72665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148529126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.148529126
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_random.498009190
Short name T451
Test name
Test status
Simulation time 781561952 ps
CPU time 5.07 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 218504 kb
Host smart-7c4d9971-0cfc-467c-91d7-78b6e9d77032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498009190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.498009190
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1014880983
Short name T265
Test name
Test status
Simulation time 111883881 ps
CPU time 3.61 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 208460 kb
Host smart-3b4a92ad-4c41-43e7-bdae-fe32373bd7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014880983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1014880983
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1990990453
Short name T862
Test name
Test status
Simulation time 135272703 ps
CPU time 3.43 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 209088 kb
Host smart-a4b52038-a1f7-4f18-82eb-9d81fbe91ba0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990990453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1990990453
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1754002792
Short name T867
Test name
Test status
Simulation time 480575882 ps
CPU time 5.62 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 208268 kb
Host smart-a10d7afc-a8ab-4b53-8b30-b1499ce8a548
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754002792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1754002792
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2618718673
Short name T408
Test name
Test status
Simulation time 584430360 ps
CPU time 4.9 seconds
Started Apr 16 12:45:14 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 207948 kb
Host smart-0034aa63-43f1-4e1f-960a-70595f0741db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618718673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2618718673
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.864150646
Short name T683
Test name
Test status
Simulation time 192319378 ps
CPU time 2.37 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 215948 kb
Host smart-d22a29c5-ce47-485b-8907-7fa76613c347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864150646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.864150646
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.224171867
Short name T719
Test name
Test status
Simulation time 311038472 ps
CPU time 6.38 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 208956 kb
Host smart-8ac91ed6-873c-4355-bf91-86e8e094cc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224171867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.224171867
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.404785420
Short name T176
Test name
Test status
Simulation time 450689877 ps
CPU time 14.37 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 222848 kb
Host smart-85eacda6-7ae7-4547-af39-579c7cd6b0d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404785420 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.404785420
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3742749226
Short name T798
Test name
Test status
Simulation time 585405872 ps
CPU time 18.74 seconds
Started Apr 16 12:45:15 PM PDT 24
Finished Apr 16 12:45:37 PM PDT 24
Peak memory 208956 kb
Host smart-5dbd31a2-6f47-496c-a097-9425c69693b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742749226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3742749226
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.71299100
Short name T873
Test name
Test status
Simulation time 119509315 ps
CPU time 2.87 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 210040 kb
Host smart-2637aee5-2a32-4dd1-bad9-17a37eb0e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71299100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.71299100
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2141060958
Short name T900
Test name
Test status
Simulation time 66514906 ps
CPU time 0.81 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 206224 kb
Host smart-dde85860-6d4a-42c7-883e-a88f6936c121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141060958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2141060958
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3757215306
Short name T488
Test name
Test status
Simulation time 38683274 ps
CPU time 1.81 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 209540 kb
Host smart-80cfce3f-c226-4301-bc96-435806aa1ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757215306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3757215306
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4064846556
Short name T843
Test name
Test status
Simulation time 206782440 ps
CPU time 4.53 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:30 PM PDT 24
Peak memory 214652 kb
Host smart-8174b76e-152e-4caf-972d-5555703136fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064846556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4064846556
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3709806675
Short name T13
Test name
Test status
Simulation time 221634117 ps
CPU time 7.54 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:17 PM PDT 24
Peak memory 210108 kb
Host smart-3c462787-34b2-46f9-a8dd-e2aed92b8500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709806675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3709806675
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1296780031
Short name T492
Test name
Test status
Simulation time 96274513 ps
CPU time 4.91 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 219408 kb
Host smart-6bd35e82-4ab7-4dd9-bd6e-53fa3ae54b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296780031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1296780031
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2535143407
Short name T376
Test name
Test status
Simulation time 100608207 ps
CPU time 4.31 seconds
Started Apr 16 12:45:05 PM PDT 24
Finished Apr 16 12:45:12 PM PDT 24
Peak memory 210236 kb
Host smart-11edb076-dbf0-4df0-85f0-648da6393895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535143407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2535143407
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1935570023
Short name T720
Test name
Test status
Simulation time 33320478 ps
CPU time 2.28 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:23 PM PDT 24
Peak memory 207068 kb
Host smart-4866c50e-6c79-4e29-8bae-71b93218bf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935570023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1935570023
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.632434895
Short name T773
Test name
Test status
Simulation time 394560310 ps
CPU time 5.28 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 208124 kb
Host smart-2f9382bf-9cc9-4bab-986e-72626bb425f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632434895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.632434895
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3292898608
Short name T836
Test name
Test status
Simulation time 58031650 ps
CPU time 2.97 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 207156 kb
Host smart-c3be0492-276b-4407-95e6-724251f531cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292898608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3292898608
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3216351204
Short name T371
Test name
Test status
Simulation time 399659035 ps
CPU time 5.25 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:26 PM PDT 24
Peak memory 208856 kb
Host smart-56ce4e52-c727-4a28-9d17-21f87f1dd199
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216351204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3216351204
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1084410575
Short name T807
Test name
Test status
Simulation time 148762608 ps
CPU time 4.29 seconds
Started Apr 16 12:45:20 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 209140 kb
Host smart-0b40c5a0-aada-4f00-88a8-adf35a9b7ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084410575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1084410575
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1285417767
Short name T521
Test name
Test status
Simulation time 962678225 ps
CPU time 6.68 seconds
Started Apr 16 12:45:14 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 208664 kb
Host smart-46d13557-fda0-458e-8dcb-2366ea9735dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285417767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1285417767
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2244338719
Short name T297
Test name
Test status
Simulation time 859056284 ps
CPU time 11.04 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:26 PM PDT 24
Peak memory 222820 kb
Host smart-e2d06075-da69-4227-ac0c-498b97a1d98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244338719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2244338719
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2866305265
Short name T54
Test name
Test status
Simulation time 635133766 ps
CPU time 17.37 seconds
Started Apr 16 12:45:31 PM PDT 24
Finished Apr 16 12:45:50 PM PDT 24
Peak memory 222880 kb
Host smart-dfadfd80-9912-467f-b9c1-f466289d6521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866305265 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2866305265
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1377683014
Short name T385
Test name
Test status
Simulation time 1643862426 ps
CPU time 17.5 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:31 PM PDT 24
Peak memory 208216 kb
Host smart-1a2931b6-455d-4758-ae6f-aa96e64c98b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377683014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1377683014
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2823621876
Short name T537
Test name
Test status
Simulation time 29596640 ps
CPU time 1.87 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 209928 kb
Host smart-c796ffcc-5098-4ae1-b75f-c7b9a345fc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823621876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2823621876
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2172754333
Short name T726
Test name
Test status
Simulation time 3872252337 ps
CPU time 28.55 seconds
Started Apr 16 12:45:25 PM PDT 24
Finished Apr 16 12:45:55 PM PDT 24
Peak memory 223136 kb
Host smart-111a2480-eeea-4e79-94b5-06f9fb55ad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172754333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2172754333
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.23991032
Short name T434
Test name
Test status
Simulation time 448634847 ps
CPU time 2.75 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 210512 kb
Host smart-d42c6a3d-38d1-46a7-b177-8d2d33f98f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23991032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.23991032
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.234746184
Short name T704
Test name
Test status
Simulation time 334050474 ps
CPU time 4.01 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:25 PM PDT 24
Peak memory 209328 kb
Host smart-7db309ac-d20c-4b29-aed6-8ea5e4fc284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234746184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.234746184
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3841560389
Short name T206
Test name
Test status
Simulation time 1715733176 ps
CPU time 46.18 seconds
Started Apr 16 12:45:17 PM PDT 24
Finished Apr 16 12:46:06 PM PDT 24
Peak memory 221316 kb
Host smart-10088d94-3b7f-45ba-a2a4-c4a30c735764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841560389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3841560389
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3321801700
Short name T485
Test name
Test status
Simulation time 1032030675 ps
CPU time 3.63 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:17 PM PDT 24
Peak memory 214584 kb
Host smart-75275255-ded3-4200-b247-7dbfdde667f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321801700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3321801700
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.771664719
Short name T684
Test name
Test status
Simulation time 43502269 ps
CPU time 3.09 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:46 PM PDT 24
Peak memory 218440 kb
Host smart-1c39af81-7b5e-4891-a019-e84665e3470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771664719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.771664719
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3569553136
Short name T252
Test name
Test status
Simulation time 200121916 ps
CPU time 6.84 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 207024 kb
Host smart-4aa30790-259b-42f9-ab60-ba082c86f303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569553136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3569553136
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2208214287
Short name T823
Test name
Test status
Simulation time 172985641 ps
CPU time 2.75 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 207112 kb
Host smart-142cec3e-346a-4736-a304-77a7c6be6582
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208214287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2208214287
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2484610331
Short name T372
Test name
Test status
Simulation time 1360637737 ps
CPU time 33.68 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 208512 kb
Host smart-429eb799-d053-45f4-8474-2d167f24a237
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484610331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2484610331
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1295638378
Short name T577
Test name
Test status
Simulation time 118897556 ps
CPU time 3.03 seconds
Started Apr 16 12:45:15 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 207128 kb
Host smart-ef8fad7e-9243-4131-9857-eedf9f3e7ce7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295638378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1295638378
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2287212767
Short name T425
Test name
Test status
Simulation time 175780479 ps
CPU time 2.4 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 215764 kb
Host smart-03981798-5446-4926-881e-e68b913f3a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287212767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2287212767
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.13583604
Short name T407
Test name
Test status
Simulation time 73531105 ps
CPU time 3.19 seconds
Started Apr 16 12:45:14 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 208804 kb
Host smart-c5fdbcf8-21a8-48a5-bb68-9faee878ea19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13583604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.13583604
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2974899094
Short name T874
Test name
Test status
Simulation time 2476644086 ps
CPU time 60.73 seconds
Started Apr 16 12:45:26 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 221264 kb
Host smart-b23d32e7-5072-42e9-a188-98bb0adadcd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974899094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2974899094
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3620203511
Short name T282
Test name
Test status
Simulation time 18222662694 ps
CPU time 49.47 seconds
Started Apr 16 12:45:04 PM PDT 24
Finished Apr 16 12:45:56 PM PDT 24
Peak memory 214732 kb
Host smart-6e3f1b4d-50e7-44cc-94e0-f0be89d0f5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620203511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3620203511
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2867232069
Short name T361
Test name
Test status
Simulation time 717406706 ps
CPU time 7.5 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:23 PM PDT 24
Peak memory 211028 kb
Host smart-e3ec519e-6572-4052-b57c-30e631fc87b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867232069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2867232069
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.447421736
Short name T127
Test name
Test status
Simulation time 11394368 ps
CPU time 0.77 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 206288 kb
Host smart-94ddc0ae-345c-48ea-b76d-fe7d6d502a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447421736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.447421736
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2261635821
Short name T306
Test name
Test status
Simulation time 685292666 ps
CPU time 4.98 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 214536 kb
Host smart-68dcbb5d-b446-44f3-8fa9-a03f3e0a18e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261635821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2261635821
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2550462885
Short name T229
Test name
Test status
Simulation time 491292461 ps
CPU time 6.22 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 209592 kb
Host smart-d16d1105-9d46-4b96-8d3b-9fb6a72b21d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550462885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2550462885
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3449603312
Short name T367
Test name
Test status
Simulation time 85043503 ps
CPU time 3 seconds
Started Apr 16 12:45:15 PM PDT 24
Finished Apr 16 12:45:25 PM PDT 24
Peak memory 214532 kb
Host smart-f8423816-59b0-4e3a-b689-5c13a4648a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449603312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3449603312
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2282788007
Short name T661
Test name
Test status
Simulation time 442736982 ps
CPU time 9.57 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:28 PM PDT 24
Peak memory 214856 kb
Host smart-f2c2f6d1-1eb3-4a0f-9498-aa0bfd926200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282788007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2282788007
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2696958885
Short name T455
Test name
Test status
Simulation time 91525733 ps
CPU time 2.87 seconds
Started Apr 16 12:45:28 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 220596 kb
Host smart-72088943-db8f-4f97-b8b1-ce52f1f6f61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696958885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2696958885
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2908743452
Short name T610
Test name
Test status
Simulation time 523316504 ps
CPU time 12.03 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:25 PM PDT 24
Peak memory 209536 kb
Host smart-4cfb3579-2513-47a0-936c-86bca351926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908743452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2908743452
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1876336772
Short name T763
Test name
Test status
Simulation time 113003277 ps
CPU time 2.47 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 208840 kb
Host smart-e276604f-c7c6-47aa-863c-929f2538ff21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876336772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1876336772
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1829985657
Short name T678
Test name
Test status
Simulation time 230872292 ps
CPU time 2.93 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:32 PM PDT 24
Peak memory 207132 kb
Host smart-eed4be2e-df2f-42b8-8251-cbe21463aa3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829985657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1829985657
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2356122897
Short name T262
Test name
Test status
Simulation time 1858965620 ps
CPU time 36.25 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 208740 kb
Host smart-c4fb7c43-804c-4cc9-a8fb-3fe64f1f183f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356122897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2356122897
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3467071401
Short name T670
Test name
Test status
Simulation time 180685619 ps
CPU time 5.08 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:17 PM PDT 24
Peak memory 208884 kb
Host smart-c8edd9a6-d856-469a-9ae8-b5870a82aa94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467071401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3467071401
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2941610970
Short name T729
Test name
Test status
Simulation time 187263000 ps
CPU time 3.93 seconds
Started Apr 16 12:45:30 PM PDT 24
Finished Apr 16 12:45:36 PM PDT 24
Peak memory 209596 kb
Host smart-bd539f9d-731b-48e6-9a63-5e726a916478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941610970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2941610970
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2858517424
Short name T721
Test name
Test status
Simulation time 1541557895 ps
CPU time 21.57 seconds
Started Apr 16 12:45:22 PM PDT 24
Finished Apr 16 12:45:45 PM PDT 24
Peak memory 207836 kb
Host smart-ac1a7d8f-c0a0-455f-bbb3-8fb28e62dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858517424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2858517424
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.221191860
Short name T345
Test name
Test status
Simulation time 192562939 ps
CPU time 9.84 seconds
Started Apr 16 12:45:20 PM PDT 24
Finished Apr 16 12:45:32 PM PDT 24
Peak memory 215652 kb
Host smart-30c71fce-959d-4b32-a359-1fc70cca6da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221191860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.221191860
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2067207541
Short name T55
Test name
Test status
Simulation time 621508850 ps
CPU time 8.92 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:44 PM PDT 24
Peak memory 223012 kb
Host smart-2fbe006e-ac9c-48a5-ab64-6c638643470a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067207541 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2067207541
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2335500077
Short name T469
Test name
Test status
Simulation time 32157529 ps
CPU time 0.73 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 206284 kb
Host smart-b9154ca1-a959-4b36-81da-4e76646fe446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335500077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2335500077
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1492661862
Short name T35
Test name
Test status
Simulation time 2135778199 ps
CPU time 21.66 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 219116 kb
Host smart-a63cd53e-e5be-4f8b-8d52-47ec6fa162b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492661862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1492661862
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2574913611
Short name T516
Test name
Test status
Simulation time 110045474 ps
CPU time 1.86 seconds
Started Apr 16 12:45:26 PM PDT 24
Finished Apr 16 12:45:31 PM PDT 24
Peak memory 209556 kb
Host smart-4d8c8d37-a9a0-437c-810d-0fce810216f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574913611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2574913611
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1421405566
Short name T123
Test name
Test status
Simulation time 93320585 ps
CPU time 3.49 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 210560 kb
Host smart-12146ca5-d3bb-4a7c-ba7d-1ac449170ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421405566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1421405566
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4262932653
Short name T659
Test name
Test status
Simulation time 134447673 ps
CPU time 4.39 seconds
Started Apr 16 12:45:20 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 214556 kb
Host smart-14ae216d-a63a-4c34-bd5a-af8c3c09614a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262932653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4262932653
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3830860201
Short name T335
Test name
Test status
Simulation time 286073696 ps
CPU time 3.56 seconds
Started Apr 16 12:45:32 PM PDT 24
Finished Apr 16 12:45:38 PM PDT 24
Peak memory 209576 kb
Host smart-61caaae6-18d0-4ae9-b65d-216a77a533a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830860201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3830860201
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.726035865
Short name T747
Test name
Test status
Simulation time 710097188 ps
CPU time 5.52 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 208588 kb
Host smart-0a835671-8eb1-40c9-afb9-023ba58a0155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726035865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.726035865
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1845489872
Short name T471
Test name
Test status
Simulation time 62743117 ps
CPU time 3.04 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 207200 kb
Host smart-c3f98a10-d784-4b1d-b645-600d2fe18bde
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845489872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1845489872
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3495679182
Short name T621
Test name
Test status
Simulation time 65119700 ps
CPU time 3.32 seconds
Started Apr 16 12:45:13 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 208928 kb
Host smart-a3a16614-8d19-4998-9cac-f738be05aea9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495679182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3495679182
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.420304128
Short name T845
Test name
Test status
Simulation time 196104551 ps
CPU time 7.11 seconds
Started Apr 16 12:45:17 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 208396 kb
Host smart-62bd1634-76ce-4b7d-9944-b3a7cc2c82de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420304128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.420304128
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2931902397
Short name T128
Test name
Test status
Simulation time 104289330 ps
CPU time 1.52 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 208160 kb
Host smart-5a1ba048-2661-4766-b185-469ee12579df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931902397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2931902397
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2134199518
Short name T806
Test name
Test status
Simulation time 32939056 ps
CPU time 2.2 seconds
Started Apr 16 12:45:26 PM PDT 24
Finished Apr 16 12:45:30 PM PDT 24
Peak memory 206960 kb
Host smart-5374ef67-b771-45a4-b8c5-02f86504a49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134199518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2134199518
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3727389374
Short name T263
Test name
Test status
Simulation time 225173793 ps
CPU time 11.43 seconds
Started Apr 16 12:45:21 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 217508 kb
Host smart-9b0dc2c4-39e5-4247-9b99-2dbd530e01c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727389374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3727389374
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1424485813
Short name T754
Test name
Test status
Simulation time 77160041 ps
CPU time 2.95 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 210324 kb
Host smart-3afe68f9-85df-4a58-a3aa-0f5987301573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424485813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1424485813
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2502961577
Short name T494
Test name
Test status
Simulation time 82590076 ps
CPU time 2.31 seconds
Started Apr 16 12:45:30 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 210060 kb
Host smart-f9be2ced-086a-4df6-8656-47bac4e45cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502961577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2502961577
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3867703897
Short name T91
Test name
Test status
Simulation time 21722595 ps
CPU time 0.85 seconds
Started Apr 16 12:45:29 PM PDT 24
Finished Apr 16 12:45:32 PM PDT 24
Peak memory 206256 kb
Host smart-72c79de4-034d-4328-90f7-0cb25a5bf20f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867703897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3867703897
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3146870940
Short name T383
Test name
Test status
Simulation time 181868203 ps
CPU time 9.91 seconds
Started Apr 16 12:45:34 PM PDT 24
Finished Apr 16 12:45:46 PM PDT 24
Peak memory 214640 kb
Host smart-51c3a12f-2df2-4f17-9f3c-8d213b5dbe17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146870940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3146870940
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1120913195
Short name T21
Test name
Test status
Simulation time 183652326 ps
CPU time 2.41 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:31 PM PDT 24
Peak memory 216944 kb
Host smart-80f170c2-5515-41f1-ae78-e3170760b8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120913195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1120913195
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1903134789
Short name T450
Test name
Test status
Simulation time 257760761 ps
CPU time 2.34 seconds
Started Apr 16 12:45:30 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 207272 kb
Host smart-991f64be-66f7-4f4d-a6a6-060de50046e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903134789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1903134789
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2855708703
Short name T301
Test name
Test status
Simulation time 70446954 ps
CPU time 3.43 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:29 PM PDT 24
Peak memory 210392 kb
Host smart-4173a76c-9dd7-481e-b106-e9bfe56f481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855708703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2855708703
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_random.2640480589
Short name T560
Test name
Test status
Simulation time 130801470 ps
CPU time 4.92 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:23 PM PDT 24
Peak memory 208152 kb
Host smart-4e37d199-d668-42b9-8c3a-236b593c76fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640480589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2640480589
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1020896580
Short name T250
Test name
Test status
Simulation time 620281720 ps
CPU time 4.97 seconds
Started Apr 16 12:45:28 PM PDT 24
Finished Apr 16 12:45:35 PM PDT 24
Peak memory 208780 kb
Host smart-2f5abcbc-d33e-4572-a82c-41b4bcce0b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020896580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1020896580
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1006522920
Short name T814
Test name
Test status
Simulation time 1272676383 ps
CPU time 4.34 seconds
Started Apr 16 12:45:17 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 208948 kb
Host smart-0c8e5456-d553-41e7-a9cf-8d56f191aec5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006522920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1006522920
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2051329686
Short name T868
Test name
Test status
Simulation time 99897549 ps
CPU time 2.17 seconds
Started Apr 16 12:45:28 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 209140 kb
Host smart-a804763b-0d8a-4724-8aba-c7271cc72dd1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051329686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2051329686
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.290622134
Short name T124
Test name
Test status
Simulation time 1143329439 ps
CPU time 37.52 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 208912 kb
Host smart-8339ab7c-cf26-4f2f-b987-7fc5f9ccf9b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290622134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.290622134
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3532889255
Short name T470
Test name
Test status
Simulation time 307193124 ps
CPU time 3.21 seconds
Started Apr 16 12:45:21 PM PDT 24
Finished Apr 16 12:45:26 PM PDT 24
Peak memory 210308 kb
Host smart-404040f9-e9d6-4eb3-8306-a2a58d0add80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532889255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3532889255
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2465847405
Short name T803
Test name
Test status
Simulation time 1775561590 ps
CPU time 29.5 seconds
Started Apr 16 12:45:23 PM PDT 24
Finished Apr 16 12:45:54 PM PDT 24
Peak memory 208904 kb
Host smart-0c0a43dd-8a64-4d64-8614-080ec3991c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465847405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2465847405
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2554924786
Short name T892
Test name
Test status
Simulation time 1492963197 ps
CPU time 13.29 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:43 PM PDT 24
Peak memory 222816 kb
Host smart-97ceaf1a-e389-44dc-a06c-21b7a77f4892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554924786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2554924786
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3611504267
Short name T744
Test name
Test status
Simulation time 845926205 ps
CPU time 3.91 seconds
Started Apr 16 12:45:26 PM PDT 24
Finished Apr 16 12:45:32 PM PDT 24
Peak memory 208232 kb
Host smart-394c3299-b9b9-4c0b-9236-2fe52a21fd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611504267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3611504267
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.845170185
Short name T649
Test name
Test status
Simulation time 216018507 ps
CPU time 3.04 seconds
Started Apr 16 12:45:31 PM PDT 24
Finished Apr 16 12:45:35 PM PDT 24
Peak memory 210520 kb
Host smart-1d75b47c-217d-4b7c-bb31-11e23cfc7f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845170185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.845170185
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1599345442
Short name T541
Test name
Test status
Simulation time 27259148 ps
CPU time 0.72 seconds
Started Apr 16 12:45:31 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 206212 kb
Host smart-8becce4d-c87f-487e-8eef-3a02a545e99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599345442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1599345442
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2533554332
Short name T324
Test name
Test status
Simulation time 1089337314 ps
CPU time 63.37 seconds
Started Apr 16 12:45:29 PM PDT 24
Finished Apr 16 12:46:34 PM PDT 24
Peak memory 216164 kb
Host smart-edbf0fb6-9591-4d3e-8063-49733c269d47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533554332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2533554332
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1312494550
Short name T223
Test name
Test status
Simulation time 405357774 ps
CPU time 3.04 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:45:46 PM PDT 24
Peak memory 222068 kb
Host smart-2befa0fa-2101-4760-8b19-accfd1df7844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312494550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1312494550
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2586620037
Short name T56
Test name
Test status
Simulation time 178525830 ps
CPU time 2.35 seconds
Started Apr 16 12:45:28 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 209572 kb
Host smart-2dfae0f1-16ff-4ff8-a865-0ad3537172cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586620037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2586620037
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.525204064
Short name T739
Test name
Test status
Simulation time 392655504 ps
CPU time 4.16 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:25 PM PDT 24
Peak memory 210372 kb
Host smart-7e0c828d-f42d-49bc-aaab-0a7093b430c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525204064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.525204064
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.72144427
Short name T898
Test name
Test status
Simulation time 109328679 ps
CPU time 5.01 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:17 PM PDT 24
Peak memory 218932 kb
Host smart-784de0eb-d619-430d-b472-0e876152fbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72144427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.72144427
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.610950967
Short name T430
Test name
Test status
Simulation time 157803734 ps
CPU time 2.65 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 206984 kb
Host smart-b1496476-cca7-4f0e-b77f-ed5b9d2a3b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610950967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.610950967
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3975950696
Short name T481
Test name
Test status
Simulation time 4918317676 ps
CPU time 10.97 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:36 PM PDT 24
Peak memory 208336 kb
Host smart-527b5e00-dd16-4d3a-b1fd-f4abc4cba4bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975950696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3975950696
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2426990225
Short name T212
Test name
Test status
Simulation time 28091238 ps
CPU time 2.28 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:37 PM PDT 24
Peak memory 209060 kb
Host smart-77fcac7b-adc0-45b0-878e-570ff64a63e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426990225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2426990225
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3338876171
Short name T846
Test name
Test status
Simulation time 99229794 ps
CPU time 2.73 seconds
Started Apr 16 12:45:25 PM PDT 24
Finished Apr 16 12:45:29 PM PDT 24
Peak memory 207024 kb
Host smart-34a99dd1-9742-483c-acd9-67d5d4046fd2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338876171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3338876171
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2272463153
Short name T565
Test name
Test status
Simulation time 160960387 ps
CPU time 2.47 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:31 PM PDT 24
Peak memory 215836 kb
Host smart-85073249-1b40-42c1-80d2-5341fc5c781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272463153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2272463153
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3972401265
Short name T609
Test name
Test status
Simulation time 714463663 ps
CPU time 8.49 seconds
Started Apr 16 12:45:17 PM PDT 24
Finished Apr 16 12:45:28 PM PDT 24
Peak memory 207080 kb
Host smart-54839211-e692-4b56-a2f5-ab5b6071e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972401265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3972401265
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2321096114
Short name T673
Test name
Test status
Simulation time 90510335 ps
CPU time 4.59 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 209356 kb
Host smart-2b45ba27-5763-4b51-b2e9-10e642dace52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321096114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2321096114
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2860640704
Short name T164
Test name
Test status
Simulation time 183072269 ps
CPU time 2.2 seconds
Started Apr 16 12:45:29 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 210180 kb
Host smart-08bdde52-a347-428e-98be-89bb2ea4f26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860640704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2860640704
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1455719746
Short name T791
Test name
Test status
Simulation time 12636474 ps
CPU time 0.75 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:41 PM PDT 24
Peak memory 206144 kb
Host smart-205d415c-9bf8-491e-a35c-0c888a787c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455719746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1455719746
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3886907688
Short name T396
Test name
Test status
Simulation time 52989365 ps
CPU time 2.25 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:38 PM PDT 24
Peak memory 214576 kb
Host smart-be80f85c-66be-4102-86f2-8baf6e8e0f69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886907688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3886907688
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2765886110
Short name T751
Test name
Test status
Simulation time 66242330 ps
CPU time 3.39 seconds
Started Apr 16 12:45:30 PM PDT 24
Finished Apr 16 12:45:35 PM PDT 24
Peak memory 219436 kb
Host smart-350f9000-37ad-4120-849e-8f1a63b02243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765886110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2765886110
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4211309741
Short name T299
Test name
Test status
Simulation time 74288606 ps
CPU time 3.42 seconds
Started Apr 16 12:45:20 PM PDT 24
Finished Apr 16 12:45:25 PM PDT 24
Peak memory 209592 kb
Host smart-debf3137-5ea3-4ae6-ada8-d729b664fcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211309741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4211309741
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1734631046
Short name T75
Test name
Test status
Simulation time 296193640 ps
CPU time 6.64 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 221268 kb
Host smart-b8b52329-be48-4303-af52-59ffbc60dbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734631046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1734631046
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3182921862
Short name T870
Test name
Test status
Simulation time 60804530 ps
CPU time 3.25 seconds
Started Apr 16 12:45:32 PM PDT 24
Finished Apr 16 12:45:37 PM PDT 24
Peak memory 220704 kb
Host smart-c455f5b7-70e1-415d-9e25-ffe2efb674de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182921862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3182921862
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3793027748
Short name T782
Test name
Test status
Simulation time 91777003 ps
CPU time 4.17 seconds
Started Apr 16 12:45:23 PM PDT 24
Finished Apr 16 12:45:28 PM PDT 24
Peak memory 208424 kb
Host smart-2cd726e7-7079-4106-9c91-da3e9fcd5cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793027748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3793027748
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3709400230
Short name T550
Test name
Test status
Simulation time 744176812 ps
CPU time 3.44 seconds
Started Apr 16 12:45:28 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 208764 kb
Host smart-80fda964-c234-4e4e-9dc5-bf436e31876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709400230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3709400230
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3542604315
Short name T768
Test name
Test status
Simulation time 767846830 ps
CPU time 7.05 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:23 PM PDT 24
Peak memory 208016 kb
Host smart-f1e8a5ae-13cc-4397-93b6-5a075a22de86
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542604315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3542604315
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.41053435
Short name T186
Test name
Test status
Simulation time 252502586 ps
CPU time 9.06 seconds
Started Apr 16 12:45:25 PM PDT 24
Finished Apr 16 12:45:36 PM PDT 24
Peak memory 208816 kb
Host smart-0b42f5d4-9950-49c5-870b-dfed34d0cf56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41053435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.41053435
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2741009557
Short name T872
Test name
Test status
Simulation time 187674357 ps
CPU time 5.22 seconds
Started Apr 16 12:45:28 PM PDT 24
Finished Apr 16 12:45:35 PM PDT 24
Peak memory 210660 kb
Host smart-3050fc0b-2423-4153-8089-20d1f5339187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741009557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2741009557
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1110618004
Short name T518
Test name
Test status
Simulation time 263059623 ps
CPU time 2.63 seconds
Started Apr 16 12:45:14 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 206836 kb
Host smart-24cc3276-93e8-4a03-ab97-1c096a539fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110618004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1110618004
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3588119313
Short name T632
Test name
Test status
Simulation time 145269700 ps
CPU time 8.38 seconds
Started Apr 16 12:45:47 PM PDT 24
Finished Apr 16 12:45:57 PM PDT 24
Peak memory 220664 kb
Host smart-d388c244-1190-4ce4-851a-3bd083c1da1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588119313 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3588119313
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2010985660
Short name T831
Test name
Test status
Simulation time 172212012 ps
CPU time 5.1 seconds
Started Apr 16 12:45:29 PM PDT 24
Finished Apr 16 12:45:36 PM PDT 24
Peak memory 208344 kb
Host smart-932e6d73-f993-45a4-ab00-dd2a833f1169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010985660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2010985660
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.545393616
Short name T191
Test name
Test status
Simulation time 2984231420 ps
CPU time 14.53 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:43 PM PDT 24
Peak memory 222896 kb
Host smart-97ed37ef-cdd9-459a-88c7-32d8597c6750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545393616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.545393616
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.591004385
Short name T722
Test name
Test status
Simulation time 19449772 ps
CPU time 0.81 seconds
Started Apr 16 12:44:50 PM PDT 24
Finished Apr 16 12:44:52 PM PDT 24
Peak memory 206152 kb
Host smart-061f6e0e-5994-4616-9e40-b88c48b18b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591004385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.591004385
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2522043446
Short name T799
Test name
Test status
Simulation time 97347951 ps
CPU time 3.81 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 218132 kb
Host smart-a1a742c7-4b3e-4233-bb74-95736bc876e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522043446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2522043446
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3783084166
Short name T757
Test name
Test status
Simulation time 48114059 ps
CPU time 1.84 seconds
Started Apr 16 12:44:59 PM PDT 24
Finished Apr 16 12:45:03 PM PDT 24
Peak memory 209788 kb
Host smart-f97d7bbb-5a66-42c3-8cee-37000fbc1016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783084166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3783084166
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3811000749
Short name T698
Test name
Test status
Simulation time 62440403 ps
CPU time 3.84 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 214656 kb
Host smart-657e0e1f-6cf5-4a00-972f-255678870ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811000749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3811000749
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2208206589
Short name T618
Test name
Test status
Simulation time 312521973 ps
CPU time 9.64 seconds
Started Apr 16 12:44:57 PM PDT 24
Finished Apr 16 12:45:08 PM PDT 24
Peak memory 214536 kb
Host smart-f250d4ae-9fb1-41ed-b3b4-87342c1fa76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208206589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2208206589
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2659431791
Short name T758
Test name
Test status
Simulation time 340342168 ps
CPU time 3.93 seconds
Started Apr 16 12:44:47 PM PDT 24
Finished Apr 16 12:44:52 PM PDT 24
Peak memory 220256 kb
Host smart-2a638696-8808-45b2-ad04-3d2dc01f0af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659431791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2659431791
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3185680127
Short name T697
Test name
Test status
Simulation time 124167519 ps
CPU time 3.49 seconds
Started Apr 16 12:44:47 PM PDT 24
Finished Apr 16 12:45:01 PM PDT 24
Peak memory 207180 kb
Host smart-6e06f882-6923-4215-a16d-dc3590197080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185680127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3185680127
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3838752141
Short name T95
Test name
Test status
Simulation time 1935907501 ps
CPU time 19.91 seconds
Started Apr 16 12:44:47 PM PDT 24
Finished Apr 16 12:45:08 PM PDT 24
Peak memory 239972 kb
Host smart-35fc4aec-270c-4ba3-bdd7-8af4830a7cd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838752141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3838752141
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1978218850
Short name T406
Test name
Test status
Simulation time 410090811 ps
CPU time 2.87 seconds
Started Apr 16 12:44:40 PM PDT 24
Finished Apr 16 12:44:44 PM PDT 24
Peak memory 206980 kb
Host smart-5ce498d1-f0d0-4a32-af0c-ec65e627e22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978218850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1978218850
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.572521339
Short name T677
Test name
Test status
Simulation time 42358476 ps
CPU time 1.67 seconds
Started Apr 16 12:44:42 PM PDT 24
Finished Apr 16 12:44:46 PM PDT 24
Peak memory 207000 kb
Host smart-5255c206-ee28-4623-8961-81813fc4e145
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572521339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.572521339
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.145097852
Short name T885
Test name
Test status
Simulation time 247081273 ps
CPU time 3.06 seconds
Started Apr 16 12:44:51 PM PDT 24
Finished Apr 16 12:44:55 PM PDT 24
Peak memory 209092 kb
Host smart-a025a404-5dd0-4be9-9b2a-896d0e5c5cb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145097852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.145097852
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2599366187
Short name T837
Test name
Test status
Simulation time 780029780 ps
CPU time 8.65 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 209436 kb
Host smart-d31d67c1-555d-4a8f-bc8c-e4f9b2e1f59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599366187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2599366187
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3316620
Short name T185
Test name
Test status
Simulation time 577790161 ps
CPU time 4 seconds
Started Apr 16 12:44:58 PM PDT 24
Finished Apr 16 12:45:04 PM PDT 24
Peak memory 206992 kb
Host smart-7eef6796-432f-40cd-a4f8-6d7d40d2c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3316620
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3416603818
Short name T741
Test name
Test status
Simulation time 65714306 ps
CPU time 4.17 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 214728 kb
Host smart-cbc81f04-4d06-458a-a56a-c611ddc95b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416603818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3416603818
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1805493265
Short name T358
Test name
Test status
Simulation time 79205949 ps
CPU time 2.25 seconds
Started Apr 16 12:44:57 PM PDT 24
Finished Apr 16 12:45:01 PM PDT 24
Peak memory 210104 kb
Host smart-d043c41f-1ed1-472e-866f-7879fbb95dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805493265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1805493265
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1313442340
Short name T583
Test name
Test status
Simulation time 58908786 ps
CPU time 0.77 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:30 PM PDT 24
Peak memory 206180 kb
Host smart-093d97e6-26a9-4706-bd53-58715d400994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313442340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1313442340
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1833814441
Short name T391
Test name
Test status
Simulation time 39333990 ps
CPU time 2.69 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:45:46 PM PDT 24
Peak memory 215568 kb
Host smart-db53ce96-dd91-4d50-b500-af04358b6f14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833814441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1833814441
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2601354609
Short name T781
Test name
Test status
Simulation time 102984265 ps
CPU time 2.02 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:45:43 PM PDT 24
Peak memory 208760 kb
Host smart-c528801d-6cf0-4fb5-a4a3-ad61f07154a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601354609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2601354609
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2799977443
Short name T863
Test name
Test status
Simulation time 597732214 ps
CPU time 6.26 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:41 PM PDT 24
Peak memory 209364 kb
Host smart-74e19130-aed1-4601-8672-1144d6cec981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799977443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2799977443
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.704786402
Short name T857
Test name
Test status
Simulation time 39605496 ps
CPU time 2.76 seconds
Started Apr 16 12:45:30 PM PDT 24
Finished Apr 16 12:45:35 PM PDT 24
Peak memory 222728 kb
Host smart-cdf1a91d-7eaa-48ce-93c7-f902c2027711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704786402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.704786402
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.736174004
Short name T182
Test name
Test status
Simulation time 1197731247 ps
CPU time 20.09 seconds
Started Apr 16 12:45:32 PM PDT 24
Finished Apr 16 12:45:54 PM PDT 24
Peak memory 218352 kb
Host smart-005ab400-88fd-4c84-89ab-271a6c24ac0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736174004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.736174004
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3859023702
Short name T669
Test name
Test status
Simulation time 572585622 ps
CPU time 4.55 seconds
Started Apr 16 12:45:21 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 208172 kb
Host smart-4b7f9428-af8e-4556-a43e-a1f43a6abfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859023702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3859023702
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.844278091
Short name T736
Test name
Test status
Simulation time 195452449 ps
CPU time 2.68 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:43 PM PDT 24
Peak memory 207096 kb
Host smart-0cdec7ca-c527-46d5-b2ed-813a1070a466
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844278091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.844278091
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3612222767
Short name T625
Test name
Test status
Simulation time 1089818461 ps
CPU time 24.35 seconds
Started Apr 16 12:45:32 PM PDT 24
Finished Apr 16 12:45:58 PM PDT 24
Peak memory 208644 kb
Host smart-c9831fbf-f617-4f4a-8b5f-d80435da675b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612222767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3612222767
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.201205371
Short name T589
Test name
Test status
Simulation time 2507187136 ps
CPU time 24.98 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:54 PM PDT 24
Peak memory 208124 kb
Host smart-beb71c84-13a3-4028-9e9e-9e4c66320592
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201205371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.201205371
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.548412706
Short name T16
Test name
Test status
Simulation time 653457609 ps
CPU time 5.07 seconds
Started Apr 16 12:45:20 PM PDT 24
Finished Apr 16 12:45:28 PM PDT 24
Peak memory 214552 kb
Host smart-1bb61a4b-6ef6-4f75-a7ba-fb69f456304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548412706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.548412706
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.4223844379
Short name T544
Test name
Test status
Simulation time 306705926 ps
CPU time 8.5 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 207008 kb
Host smart-7b0e1785-d203-4c7e-8149-0b0c3418a22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223844379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.4223844379
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1088498342
Short name T69
Test name
Test status
Simulation time 403391565 ps
CPU time 4.82 seconds
Started Apr 16 12:45:43 PM PDT 24
Finished Apr 16 12:45:50 PM PDT 24
Peak memory 208396 kb
Host smart-ce6aa389-7f61-4e7d-922d-a7531f68e076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088498342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1088498342
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.4022929314
Short name T775
Test name
Test status
Simulation time 1258342558 ps
CPU time 17.24 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:45:56 PM PDT 24
Peak memory 220756 kb
Host smart-5c25c81c-7596-4f8c-a68e-f4c453412574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022929314 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.4022929314
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1986271668
Short name T519
Test name
Test status
Simulation time 203338597 ps
CPU time 3.39 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 208372 kb
Host smart-87fc998f-be98-4360-a6f4-ebe2f9172e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986271668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1986271668
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1239671410
Short name T891
Test name
Test status
Simulation time 112272015 ps
CPU time 2.83 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:32 PM PDT 24
Peak memory 210624 kb
Host smart-98254a21-cdfc-42aa-9bad-fd969799b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239671410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1239671410
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.604720406
Short name T440
Test name
Test status
Simulation time 16376146 ps
CPU time 0.8 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 206256 kb
Host smart-b23f35e5-e993-4962-890b-9725cd5f8089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604720406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.604720406
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3100327616
Short name T397
Test name
Test status
Simulation time 50410665 ps
CPU time 2.93 seconds
Started Apr 16 12:45:36 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 214588 kb
Host smart-65953bec-3ba0-4d62-89c2-c8c5a1d48731
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100327616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3100327616
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2024894783
Short name T600
Test name
Test status
Simulation time 261316387 ps
CPU time 5.47 seconds
Started Apr 16 12:45:26 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 208588 kb
Host smart-97c2e1a3-0f95-48ed-bac4-2ef6e430536d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024894783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2024894783
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.475785249
Short name T79
Test name
Test status
Simulation time 413800866 ps
CPU time 4.83 seconds
Started Apr 16 12:45:24 PM PDT 24
Finished Apr 16 12:45:30 PM PDT 24
Peak memory 209824 kb
Host smart-a59c44d9-5093-468e-b12d-df5687fb84db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475785249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.475785249
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.662053340
Short name T195
Test name
Test status
Simulation time 1242526883 ps
CPU time 6.74 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:36 PM PDT 24
Peak memory 214652 kb
Host smart-e5bd1c79-ce1b-4e04-a469-d8ced17d2642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662053340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.662053340
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.2592447038
Short name T717
Test name
Test status
Simulation time 986534859 ps
CPU time 23.49 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:46:06 PM PDT 24
Peak memory 208812 kb
Host smart-bc116ace-96f1-49ef-985b-e59fdc8f83b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592447038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2592447038
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2633355188
Short name T304
Test name
Test status
Simulation time 129981655 ps
CPU time 3.27 seconds
Started Apr 16 12:45:31 PM PDT 24
Finished Apr 16 12:45:36 PM PDT 24
Peak memory 209072 kb
Host smart-4389bd99-19ea-4602-b5da-da8472f4d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633355188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2633355188
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1397112099
Short name T738
Test name
Test status
Simulation time 51347270 ps
CPU time 2.66 seconds
Started Apr 16 12:45:42 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 207624 kb
Host smart-2d2db133-b1d3-4137-b100-3929a80fb271
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397112099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1397112099
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3427795216
Short name T530
Test name
Test status
Simulation time 1536378009 ps
CPU time 16.94 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:45:59 PM PDT 24
Peak memory 208192 kb
Host smart-3d9bc248-5ae5-43ae-8075-40f07f44bdef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427795216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3427795216
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2237036555
Short name T655
Test name
Test status
Simulation time 885576249 ps
CPU time 6.4 seconds
Started Apr 16 12:45:32 PM PDT 24
Finished Apr 16 12:45:40 PM PDT 24
Peak memory 208772 kb
Host smart-b3d0260b-43e3-4924-a3be-ed9c7ea9aad6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237036555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2237036555
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1108238149
Short name T531
Test name
Test status
Simulation time 60246768 ps
CPU time 2.74 seconds
Started Apr 16 12:45:42 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 209420 kb
Host smart-ed9b871f-3844-48d3-942c-2347399fadd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108238149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1108238149
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1001149095
Short name T752
Test name
Test status
Simulation time 2229473427 ps
CPU time 10.13 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:45:51 PM PDT 24
Peak memory 208156 kb
Host smart-1436ab09-851c-4964-85fb-62c844bc0a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001149095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1001149095
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3299321175
Short name T52
Test name
Test status
Simulation time 220382216 ps
CPU time 3.47 seconds
Started Apr 16 12:45:22 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 209588 kb
Host smart-498ab2b8-3458-469b-92b1-cbba147b0e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299321175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3299321175
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2223650443
Short name T594
Test name
Test status
Simulation time 231606777 ps
CPU time 6.93 seconds
Started Apr 16 12:45:34 PM PDT 24
Finished Apr 16 12:45:43 PM PDT 24
Peak memory 219868 kb
Host smart-38b2315a-218b-4c81-8287-07d0ac8ac52e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223650443 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2223650443
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.482816986
Short name T287
Test name
Test status
Simulation time 78022651 ps
CPU time 4.77 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 210156 kb
Host smart-e25af0ec-1223-4eae-a9d5-4583a41b219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482816986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.482816986
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2299090499
Short name T190
Test name
Test status
Simulation time 50479285 ps
CPU time 1.73 seconds
Started Apr 16 12:45:23 PM PDT 24
Finished Apr 16 12:45:26 PM PDT 24
Peak memory 210028 kb
Host smart-11e9d771-7d10-4cf9-acb5-57dfdfcbd1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299090499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2299090499
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3158064755
Short name T896
Test name
Test status
Simulation time 13868520 ps
CPU time 0.88 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:35 PM PDT 24
Peak memory 206388 kb
Host smart-21acd147-1a1d-431a-a3d7-c8831b80f68d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158064755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3158064755
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.243380681
Short name T32
Test name
Test status
Simulation time 81375906 ps
CPU time 1.84 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:43 PM PDT 24
Peak memory 215424 kb
Host smart-f90bddb8-d9c9-4dd5-aa62-a48edd8c7360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243380681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.243380681
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1896009833
Short name T627
Test name
Test status
Simulation time 162864646 ps
CPU time 2.39 seconds
Started Apr 16 12:45:30 PM PDT 24
Finished Apr 16 12:45:35 PM PDT 24
Peak memory 209876 kb
Host smart-862a8e55-f1c2-4d8b-b653-06df875cf6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896009833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1896009833
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1053142276
Short name T83
Test name
Test status
Simulation time 4865571272 ps
CPU time 60.83 seconds
Started Apr 16 12:45:35 PM PDT 24
Finished Apr 16 12:46:38 PM PDT 24
Peak memory 222880 kb
Host smart-1ef91214-38b0-49a8-97f9-79d876797d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053142276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1053142276
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2553045076
Short name T578
Test name
Test status
Simulation time 129592623 ps
CPU time 2.61 seconds
Started Apr 16 12:45:44 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 209540 kb
Host smart-455ba141-3387-4860-a8f9-03e6cec93a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553045076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2553045076
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1479535264
Short name T364
Test name
Test status
Simulation time 349789515 ps
CPU time 2.63 seconds
Started Apr 16 12:45:35 PM PDT 24
Finished Apr 16 12:45:39 PM PDT 24
Peak memory 214508 kb
Host smart-e1044d38-6e1a-44a4-ba52-f8d08126fc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479535264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1479535264
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3414361485
Short name T665
Test name
Test status
Simulation time 312067939 ps
CPU time 8.25 seconds
Started Apr 16 12:45:23 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 208976 kb
Host smart-b21e440c-1f10-48fd-ac75-c28ff1ed8641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414361485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3414361485
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2311116351
Short name T816
Test name
Test status
Simulation time 390852191 ps
CPU time 7.43 seconds
Started Apr 16 12:45:43 PM PDT 24
Finished Apr 16 12:45:52 PM PDT 24
Peak memory 208172 kb
Host smart-6fece7b4-8d4f-4231-8b91-8b2930acf989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311116351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2311116351
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.911633861
Short name T852
Test name
Test status
Simulation time 155546335 ps
CPU time 2.39 seconds
Started Apr 16 12:45:36 PM PDT 24
Finished Apr 16 12:45:41 PM PDT 24
Peak memory 207176 kb
Host smart-452a2aeb-f67d-42b6-b691-2ec1c6e9c032
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911633861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.911633861
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.439800374
Short name T703
Test name
Test status
Simulation time 162591024 ps
CPU time 4.66 seconds
Started Apr 16 12:45:35 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 208272 kb
Host smart-65fc12b5-e98c-492f-9b5e-2a8e0b48b9b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439800374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.439800374
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1777310391
Short name T646
Test name
Test status
Simulation time 565340774 ps
CPU time 6.81 seconds
Started Apr 16 12:45:27 PM PDT 24
Finished Apr 16 12:45:36 PM PDT 24
Peak memory 208084 kb
Host smart-12ab2f30-9e71-40ed-8e5f-fa328c780790
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777310391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1777310391
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1710551454
Short name T792
Test name
Test status
Simulation time 85770824 ps
CPU time 2.17 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 209072 kb
Host smart-d2e5dfc9-36a9-4ef3-8554-a66f8e37b1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710551454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1710551454
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3068383057
Short name T663
Test name
Test status
Simulation time 820727611 ps
CPU time 8.46 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:45:51 PM PDT 24
Peak memory 208688 kb
Host smart-f6705569-20f4-42d6-bcb2-940c30a27711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068383057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3068383057
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1866602429
Short name T474
Test name
Test status
Simulation time 913205752 ps
CPU time 6.02 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 214560 kb
Host smart-d14c5001-8787-4137-a593-9fee1119da81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866602429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1866602429
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4116546879
Short name T493
Test name
Test status
Simulation time 60252652 ps
CPU time 2.78 seconds
Started Apr 16 12:45:32 PM PDT 24
Finished Apr 16 12:45:37 PM PDT 24
Peak memory 210328 kb
Host smart-ff6e6d25-c37c-4fdb-8dd4-8ad76f1dc708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116546879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4116546879
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.623098251
Short name T819
Test name
Test status
Simulation time 50273707 ps
CPU time 0.76 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:45:45 PM PDT 24
Peak memory 206240 kb
Host smart-4e450642-fee7-4454-ac3c-d4d191ce86b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623098251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.623098251
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1101750981
Short name T392
Test name
Test status
Simulation time 732947042 ps
CPU time 12.33 seconds
Started Apr 16 12:45:23 PM PDT 24
Finished Apr 16 12:45:37 PM PDT 24
Peak memory 214612 kb
Host smart-53974c58-87c9-455f-9ad5-27a8e4dd5fe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101750981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1101750981
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.410603134
Short name T842
Test name
Test status
Simulation time 209115383 ps
CPU time 3.27 seconds
Started Apr 16 12:45:48 PM PDT 24
Finished Apr 16 12:45:52 PM PDT 24
Peak memory 208980 kb
Host smart-267c5fcb-938c-4361-9f14-8ec61c1ad8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410603134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.410603134
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.735159159
Short name T276
Test name
Test status
Simulation time 916364062 ps
CPU time 6.41 seconds
Started Apr 16 12:45:35 PM PDT 24
Finished Apr 16 12:45:44 PM PDT 24
Peak memory 214604 kb
Host smart-c214eb7e-665e-4f90-ad3b-103b3685fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735159159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.735159159
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3487553216
Short name T460
Test name
Test status
Simulation time 198430460 ps
CPU time 4.34 seconds
Started Apr 16 12:46:18 PM PDT 24
Finished Apr 16 12:46:25 PM PDT 24
Peak memory 219132 kb
Host smart-b80f354a-800b-4361-9f27-cd93ad9de9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487553216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3487553216
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1762990597
Short name T510
Test name
Test status
Simulation time 293096687 ps
CPU time 7.39 seconds
Started Apr 16 12:45:29 PM PDT 24
Finished Apr 16 12:45:39 PM PDT 24
Peak memory 209568 kb
Host smart-ccd6d225-e9fa-49f4-b1af-f904769d6ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762990597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1762990597
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.4054817192
Short name T322
Test name
Test status
Simulation time 317055963 ps
CPU time 2.69 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 208720 kb
Host smart-d9a45ddc-3092-4d83-a22d-a29bd01ab96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054817192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.4054817192
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3961376513
Short name T748
Test name
Test status
Simulation time 76442277 ps
CPU time 3.83 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:45:43 PM PDT 24
Peak memory 208828 kb
Host smart-6dd872e6-eea9-48db-a471-b65687e11636
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961376513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3961376513
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2984535031
Short name T662
Test name
Test status
Simulation time 776530024 ps
CPU time 11.9 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:45:53 PM PDT 24
Peak memory 208744 kb
Host smart-8599ecf0-ec82-42bb-ac6b-2627c31a20a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984535031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2984535031
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3822731102
Short name T617
Test name
Test status
Simulation time 1078859216 ps
CPU time 32.48 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:46:15 PM PDT 24
Peak memory 208128 kb
Host smart-1ca78cac-4338-49f4-923a-56e415787f3b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822731102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3822731102
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2916420092
Short name T459
Test name
Test status
Simulation time 326440804 ps
CPU time 2.07 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:45:45 PM PDT 24
Peak memory 208228 kb
Host smart-3b7805fc-8cb5-4882-a9e4-ee076b4dccba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916420092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2916420092
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3581517061
Short name T584
Test name
Test status
Simulation time 51556047 ps
CPU time 2.66 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 208568 kb
Host smart-6b1cbddc-a53b-4d84-a645-ea4f0c9a3662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581517061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3581517061
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3601321044
Short name T647
Test name
Test status
Simulation time 902521681 ps
CPU time 12.55 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:45:54 PM PDT 24
Peak memory 216864 kb
Host smart-2dcd414f-8a45-4d3e-bef7-fd434203f09b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601321044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3601321044
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2988718134
Short name T119
Test name
Test status
Simulation time 123551125 ps
CPU time 8.5 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:52 PM PDT 24
Peak memory 222944 kb
Host smart-efd947ae-ac75-494a-8304-ddac7b3d098e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988718134 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2988718134
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.398091189
Short name T503
Test name
Test status
Simulation time 1092689242 ps
CPU time 8.64 seconds
Started Apr 16 12:45:28 PM PDT 24
Finished Apr 16 12:45:39 PM PDT 24
Peak memory 209952 kb
Host smart-37425966-d43a-4e98-9659-a6061eb3c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398091189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.398091189
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3413830596
Short name T839
Test name
Test status
Simulation time 182693972 ps
CPU time 1.63 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:46 PM PDT 24
Peak memory 210088 kb
Host smart-5ee53a68-709c-414e-93b3-58b506645a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413830596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3413830596
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2078386903
Short name T790
Test name
Test status
Simulation time 79979559 ps
CPU time 0.8 seconds
Started Apr 16 12:45:35 PM PDT 24
Finished Apr 16 12:45:38 PM PDT 24
Peak memory 206220 kb
Host smart-7a60f5fe-7c00-4af6-b96b-33eaaad5ade2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078386903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2078386903
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4219090366
Short name T363
Test name
Test status
Simulation time 2848584780 ps
CPU time 37.87 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:46:18 PM PDT 24
Peak memory 215184 kb
Host smart-d95207d5-ce47-4475-bf65-71c26ca2f3a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219090366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4219090366
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.627196838
Short name T844
Test name
Test status
Simulation time 302727481 ps
CPU time 3.99 seconds
Started Apr 16 12:45:45 PM PDT 24
Finished Apr 16 12:45:51 PM PDT 24
Peak memory 218648 kb
Host smart-5b6c7224-118a-4500-acb3-5f3dd8d056f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627196838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.627196838
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2828660729
Short name T59
Test name
Test status
Simulation time 714320343 ps
CPU time 3.31 seconds
Started Apr 16 12:45:44 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 207576 kb
Host smart-f3787754-b85e-4d21-969d-ad8c62ea6fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828660729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2828660729
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.628237998
Short name T688
Test name
Test status
Simulation time 178901711 ps
CPU time 4.45 seconds
Started Apr 16 12:45:35 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 214624 kb
Host smart-946490c7-ba8c-449d-9cf5-b54a1318f756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628237998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.628237998
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4095763201
Short name T351
Test name
Test status
Simulation time 1537688365 ps
CPU time 53.2 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:56 PM PDT 24
Peak memory 221584 kb
Host smart-cc3034d1-67fa-45b1-a9df-aca00f7154cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095763201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4095763201
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2579070568
Short name T902
Test name
Test status
Simulation time 736521585 ps
CPU time 3.81 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:39 PM PDT 24
Peak memory 210648 kb
Host smart-5f219ae4-0b18-4659-adf1-1d9217f862f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579070568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2579070568
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.146583917
Short name T851
Test name
Test status
Simulation time 217899622 ps
CPU time 7.32 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:51 PM PDT 24
Peak memory 208588 kb
Host smart-71775e4f-79fa-4121-862e-46f25fd8be4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146583917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.146583917
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2580879292
Short name T815
Test name
Test status
Simulation time 24100044 ps
CPU time 1.87 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 207144 kb
Host smart-5b95daa4-b81e-4db7-a2a4-98161235320d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580879292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2580879292
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2446553258
Short name T696
Test name
Test status
Simulation time 89523814 ps
CPU time 1.94 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:45:45 PM PDT 24
Peak memory 208740 kb
Host smart-eb3d99bc-c429-42c5-8a3c-3dbac0d35d16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446553258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2446553258
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3092833603
Short name T97
Test name
Test status
Simulation time 262225897 ps
CPU time 2.76 seconds
Started Apr 16 12:45:46 PM PDT 24
Finished Apr 16 12:45:51 PM PDT 24
Peak memory 206988 kb
Host smart-6dc05582-d4e6-4e71-8008-d1d6d58dddf7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092833603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3092833603
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.200721291
Short name T305
Test name
Test status
Simulation time 193038698 ps
CPU time 6.12 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:06 PM PDT 24
Peak memory 208168 kb
Host smart-1d033a3e-7e7b-4db0-a9d4-ff513ddbc327
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200721291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.200721291
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.39649455
Short name T526
Test name
Test status
Simulation time 1149233756 ps
CPU time 15.48 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:45:55 PM PDT 24
Peak memory 208508 kb
Host smart-61e17f04-7ea9-49d1-b07c-5da4bd8489a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39649455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.39649455
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3108978674
Short name T71
Test name
Test status
Simulation time 760741984 ps
CPU time 5.74 seconds
Started Apr 16 12:45:36 PM PDT 24
Finished Apr 16 12:45:45 PM PDT 24
Peak memory 208784 kb
Host smart-a87c2b61-518c-417f-85d2-5c0dbd1cc653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108978674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3108978674
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3043014418
Short name T767
Test name
Test status
Simulation time 3967312305 ps
CPU time 27.49 seconds
Started Apr 16 12:45:53 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 217152 kb
Host smart-b0aad5b3-ae0f-4004-95d5-7cd9248ffd03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043014418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3043014418
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3146370064
Short name T174
Test name
Test status
Simulation time 424864831 ps
CPU time 13.32 seconds
Started Apr 16 12:45:44 PM PDT 24
Finished Apr 16 12:45:59 PM PDT 24
Peak memory 222904 kb
Host smart-2fb92fc0-8623-4813-b9bb-d3f4ebaa7f44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146370064 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3146370064
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.905136801
Short name T281
Test name
Test status
Simulation time 45695718 ps
CPU time 3.05 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:43 PM PDT 24
Peak memory 214568 kb
Host smart-b7dd0d86-e9ae-4b21-beae-d8c801615cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905136801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.905136801
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3316200009
Short name T527
Test name
Test status
Simulation time 48257621 ps
CPU time 0.92 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:36 PM PDT 24
Peak memory 206220 kb
Host smart-9b0a5b45-66f7-40c2-ad2e-12931f747a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316200009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3316200009
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.829781560
Short name T382
Test name
Test status
Simulation time 1153359361 ps
CPU time 15.92 seconds
Started Apr 16 12:45:45 PM PDT 24
Finished Apr 16 12:46:02 PM PDT 24
Peak memory 215288 kb
Host smart-29065013-a520-427d-a2f7-88f2752af170
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829781560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.829781560
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.588584043
Short name T218
Test name
Test status
Simulation time 2126483620 ps
CPU time 49.48 seconds
Started Apr 16 12:45:35 PM PDT 24
Finished Apr 16 12:46:26 PM PDT 24
Peak memory 221164 kb
Host smart-f091bab2-8088-410a-82a9-a519cd48ea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588584043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.588584043
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2628268078
Short name T693
Test name
Test status
Simulation time 42250555 ps
CPU time 2.28 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:45:45 PM PDT 24
Peak memory 209412 kb
Host smart-8434e91b-a98b-4260-a3ae-ff0a717bedbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628268078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2628268078
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2032935063
Short name T884
Test name
Test status
Simulation time 821101141 ps
CPU time 27.14 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 214516 kb
Host smart-0505786e-ec24-4f06-b0c1-1f3df79a0fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032935063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2032935063
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2583860479
Short name T428
Test name
Test status
Simulation time 681307096 ps
CPU time 4.52 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 220716 kb
Host smart-60473032-4269-4174-9304-9bfb132f4755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583860479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2583860479
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.253933190
Short name T348
Test name
Test status
Simulation time 220772321 ps
CPU time 7.09 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 210024 kb
Host smart-0023d859-cac9-4bad-827d-50a7d251f6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253933190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.253933190
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2666610763
Short name T329
Test name
Test status
Simulation time 828028767 ps
CPU time 11.33 seconds
Started Apr 16 12:45:45 PM PDT 24
Finished Apr 16 12:45:58 PM PDT 24
Peak memory 208668 kb
Host smart-8e6e1974-dc16-4f94-a04e-652ceb1e0d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666610763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2666610763
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1926705534
Short name T68
Test name
Test status
Simulation time 120841756 ps
CPU time 3.68 seconds
Started Apr 16 12:45:47 PM PDT 24
Finished Apr 16 12:45:52 PM PDT 24
Peak memory 206996 kb
Host smart-4ba55195-40cc-42c1-87a2-a7658f4f2cb9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926705534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1926705534
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2719416970
Short name T626
Test name
Test status
Simulation time 660647728 ps
CPU time 3.25 seconds
Started Apr 16 12:45:36 PM PDT 24
Finished Apr 16 12:45:41 PM PDT 24
Peak memory 207356 kb
Host smart-3f8dc33c-6587-419f-9030-e05dc6c1034c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719416970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2719416970
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1294581095
Short name T423
Test name
Test status
Simulation time 586671800 ps
CPU time 7.11 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 209208 kb
Host smart-049fc187-d997-4fc1-a9e5-6fcc146c82dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294581095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1294581095
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.331116127
Short name T778
Test name
Test status
Simulation time 89089845 ps
CPU time 3.3 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 214480 kb
Host smart-1abad3b4-0023-4f2f-8b65-8276145d5735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331116127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.331116127
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.159471151
Short name T894
Test name
Test status
Simulation time 83603624 ps
CPU time 3.33 seconds
Started Apr 16 12:45:51 PM PDT 24
Finished Apr 16 12:45:55 PM PDT 24
Peak memory 208884 kb
Host smart-1ec8a5b6-e870-4900-93fe-4649a933613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159471151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.159471151
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1622480864
Short name T766
Test name
Test status
Simulation time 239460065 ps
CPU time 11.67 seconds
Started Apr 16 12:45:35 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 216796 kb
Host smart-23f6aaab-9e44-4af3-9109-be12ca378455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622480864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1622480864
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.777443103
Short name T707
Test name
Test status
Simulation time 217436707 ps
CPU time 4.05 seconds
Started Apr 16 12:45:43 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 210548 kb
Host smart-c94bcac1-70f5-4957-ae0c-cc8f3683d8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777443103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.777443103
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2896038795
Short name T734
Test name
Test status
Simulation time 194857148 ps
CPU time 5.38 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 211328 kb
Host smart-a52efa28-e5f1-4531-a3ed-1add9fb25297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896038795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2896038795
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1931192386
Short name T93
Test name
Test status
Simulation time 14622844 ps
CPU time 0.8 seconds
Started Apr 16 12:45:46 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 206284 kb
Host smart-7be30192-c811-401b-b74d-590afeb016a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931192386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1931192386
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1960892843
Short name T390
Test name
Test status
Simulation time 107185043 ps
CPU time 6.37 seconds
Started Apr 16 12:45:46 PM PDT 24
Finished Apr 16 12:45:54 PM PDT 24
Peak memory 214892 kb
Host smart-9bb38888-7689-42b4-88fb-8375040d8455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960892843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1960892843
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3305675392
Short name T640
Test name
Test status
Simulation time 372000205 ps
CPU time 2.92 seconds
Started Apr 16 12:45:33 PM PDT 24
Finished Apr 16 12:45:38 PM PDT 24
Peak memory 209028 kb
Host smart-a17d3f32-8892-41fa-8aee-4e082f81ae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305675392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3305675392
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1861989375
Short name T569
Test name
Test status
Simulation time 396687981 ps
CPU time 6.06 seconds
Started Apr 16 12:45:49 PM PDT 24
Finished Apr 16 12:45:56 PM PDT 24
Peak memory 208828 kb
Host smart-d748fb5f-46e4-4407-9f4c-465217d62776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861989375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1861989375
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1467667513
Short name T209
Test name
Test status
Simulation time 795449749 ps
CPU time 5.21 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 214548 kb
Host smart-e2fcd00e-c74e-4a93-8be1-0376d4fc9162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467667513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1467667513
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.41069898
Short name T713
Test name
Test status
Simulation time 296889137 ps
CPU time 2.76 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:45:46 PM PDT 24
Peak memory 222732 kb
Host smart-2ce3b648-a504-4555-8b7d-e9b582d75ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41069898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.41069898
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3778555784
Short name T267
Test name
Test status
Simulation time 109356527 ps
CPU time 4.91 seconds
Started Apr 16 12:45:37 PM PDT 24
Finished Apr 16 12:45:44 PM PDT 24
Peak memory 209052 kb
Host smart-f73221ab-0002-4b50-a92c-57a858db10c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778555784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3778555784
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.4272661812
Short name T316
Test name
Test status
Simulation time 69647057 ps
CPU time 2.89 seconds
Started Apr 16 12:45:45 PM PDT 24
Finished Apr 16 12:45:50 PM PDT 24
Peak memory 206932 kb
Host smart-402eabef-289f-4840-be03-ed0d10a03a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272661812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.4272661812
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.569901338
Short name T871
Test name
Test status
Simulation time 112959322 ps
CPU time 4.59 seconds
Started Apr 16 12:45:58 PM PDT 24
Finished Apr 16 12:46:03 PM PDT 24
Peak memory 209056 kb
Host smart-370fb947-5a00-45ca-8357-842af75cc368
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569901338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.569901338
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3206003670
Short name T633
Test name
Test status
Simulation time 226014267 ps
CPU time 2.62 seconds
Started Apr 16 12:45:45 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 208592 kb
Host smart-11142e7b-ee46-4533-8e0b-8ea4521d9ec8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206003670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3206003670
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1869875239
Short name T853
Test name
Test status
Simulation time 92721548 ps
CPU time 3.98 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 208892 kb
Host smart-1a478348-41a8-42a9-9c43-e58a94182629
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869875239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1869875239
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3137294804
Short name T418
Test name
Test status
Simulation time 202896215 ps
CPU time 2.43 seconds
Started Apr 16 12:45:38 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 209428 kb
Host smart-b8243473-a2f3-42fb-9d7e-e2ae144664bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137294804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3137294804
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2893489901
Short name T410
Test name
Test status
Simulation time 565348817 ps
CPU time 17.89 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:45:59 PM PDT 24
Peak memory 208040 kb
Host smart-4ab4d414-8aa3-49c2-a0ef-c2c5d1685dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893489901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2893489901
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3110709380
Short name T881
Test name
Test status
Simulation time 388779476 ps
CPU time 4.92 seconds
Started Apr 16 12:45:56 PM PDT 24
Finished Apr 16 12:46:02 PM PDT 24
Peak memory 207576 kb
Host smart-ce4d4ab0-4de4-4f4a-a88e-229d9fd58609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110709380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3110709380
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1995474089
Short name T360
Test name
Test status
Simulation time 70993011 ps
CPU time 2.82 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 210064 kb
Host smart-8d1100d7-cf0d-4080-b0fe-7a8d2cca047b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995474089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1995474089
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3537485641
Short name T637
Test name
Test status
Simulation time 15870961 ps
CPU time 0.76 seconds
Started Apr 16 12:45:46 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 206200 kb
Host smart-7a624e8a-f726-40ff-a343-18abcf15522b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537485641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3537485641
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2917349493
Short name T858
Test name
Test status
Simulation time 37211278 ps
CPU time 2.72 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:45:44 PM PDT 24
Peak memory 215504 kb
Host smart-fedccd3a-2a68-439a-81d8-0d1501e898dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2917349493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2917349493
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1478318249
Short name T604
Test name
Test status
Simulation time 205616963 ps
CPU time 3.35 seconds
Started Apr 16 12:45:42 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 209788 kb
Host smart-1e84ff4d-ad88-4d50-87f5-34ba3d21b32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478318249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1478318249
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3978783625
Short name T689
Test name
Test status
Simulation time 566152400 ps
CPU time 5.19 seconds
Started Apr 16 12:45:49 PM PDT 24
Finished Apr 16 12:45:55 PM PDT 24
Peak memory 209152 kb
Host smart-e9855c5a-d1a1-4ffd-b2c5-c9307af662e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978783625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3978783625
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2304190590
Short name T26
Test name
Test status
Simulation time 583327111 ps
CPU time 12.84 seconds
Started Apr 16 12:45:43 PM PDT 24
Finished Apr 16 12:45:58 PM PDT 24
Peak memory 209784 kb
Host smart-39a70096-5810-4c3c-8182-190f612884e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304190590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2304190590
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3764207947
Short name T421
Test name
Test status
Simulation time 112015290 ps
CPU time 3.51 seconds
Started Apr 16 12:45:39 PM PDT 24
Finished Apr 16 12:45:44 PM PDT 24
Peak memory 208936 kb
Host smart-1dff48ec-205d-417a-9bde-8dd35e48be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764207947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3764207947
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.700877608
Short name T429
Test name
Test status
Simulation time 49587863 ps
CPU time 2.95 seconds
Started Apr 16 12:45:46 PM PDT 24
Finished Apr 16 12:45:50 PM PDT 24
Peak memory 218288 kb
Host smart-efe5a5e6-5ffe-4f27-a4ea-28619e7d02df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700877608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.700877608
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.62631280
Short name T769
Test name
Test status
Simulation time 3618010358 ps
CPU time 41.33 seconds
Started Apr 16 12:45:40 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 208716 kb
Host smart-1cb42dcf-ce3c-4208-8e88-d24c7eb0cf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62631280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.62631280
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.331571108
Short name T271
Test name
Test status
Simulation time 558709187 ps
CPU time 7.6 seconds
Started Apr 16 12:45:55 PM PDT 24
Finished Apr 16 12:46:03 PM PDT 24
Peak memory 208780 kb
Host smart-2ad18ec1-46d6-4d9c-acb7-607d6029eddc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331571108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.331571108
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1785627775
Short name T448
Test name
Test status
Simulation time 38224849 ps
CPU time 2.61 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:08 PM PDT 24
Peak memory 207092 kb
Host smart-bb9f7a00-8888-45fc-8678-4155f0df60aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785627775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1785627775
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.313700347
Short name T561
Test name
Test status
Simulation time 2505679684 ps
CPU time 5.39 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:09 PM PDT 24
Peak memory 209116 kb
Host smart-ab936aab-6f1f-405e-9906-65b0e8fb5052
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313700347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.313700347
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.4091565577
Short name T101
Test name
Test status
Simulation time 20055820 ps
CPU time 1.72 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:02 PM PDT 24
Peak memory 208088 kb
Host smart-5a013e0b-b50f-4786-b3fe-44d062482675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091565577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.4091565577
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3652437728
Short name T420
Test name
Test status
Simulation time 963847671 ps
CPU time 12.03 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:55 PM PDT 24
Peak memory 208476 kb
Host smart-81ac6670-a598-4015-887b-5f9f10e13ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652437728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3652437728
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3489176271
Short name T116
Test name
Test status
Simulation time 277412954 ps
CPU time 16.93 seconds
Started Apr 16 12:45:51 PM PDT 24
Finished Apr 16 12:46:09 PM PDT 24
Peak memory 223044 kb
Host smart-ca4d92a4-54db-4c8a-bbe1-3d7fcecc2dda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489176271 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3489176271
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.951551787
Short name T72
Test name
Test status
Simulation time 50492722 ps
CPU time 3.47 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 208628 kb
Host smart-16bda856-1f1b-4daf-9c80-7b39a532169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951551787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.951551787
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1381782445
Short name T183
Test name
Test status
Simulation time 1283532893 ps
CPU time 12.45 seconds
Started Apr 16 12:45:53 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 211096 kb
Host smart-6d0435ac-497b-44c3-abb9-bb7ebde20549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381782445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1381782445
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2263526666
Short name T400
Test name
Test status
Simulation time 38950480 ps
CPU time 0.8 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:01 PM PDT 24
Peak memory 206280 kb
Host smart-8b524574-788c-4942-93c5-8fb62f22e407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263526666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2263526666
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1302333349
Short name T835
Test name
Test status
Simulation time 62365080 ps
CPU time 4.43 seconds
Started Apr 16 12:45:43 PM PDT 24
Finished Apr 16 12:45:50 PM PDT 24
Peak memory 222800 kb
Host smart-e55fc0df-9d6b-420a-aabb-c824bb2b1446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302333349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1302333349
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1734726146
Short name T712
Test name
Test status
Simulation time 232755772 ps
CPU time 3.03 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 214652 kb
Host smart-a646b56c-73e0-4fe3-b2e8-b3d7f1dbe801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734726146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1734726146
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.4276813577
Short name T893
Test name
Test status
Simulation time 509786600 ps
CPU time 4.78 seconds
Started Apr 16 12:45:48 PM PDT 24
Finished Apr 16 12:45:54 PM PDT 24
Peak memory 210092 kb
Host smart-08dfd3db-4b59-4dfb-be98-65db965c2661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276813577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.4276813577
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.764177791
Short name T307
Test name
Test status
Simulation time 67522761 ps
CPU time 3.32 seconds
Started Apr 16 12:45:56 PM PDT 24
Finished Apr 16 12:46:00 PM PDT 24
Peak memory 208872 kb
Host smart-2018e5e6-f030-4aa5-b52e-511a508d20d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764177791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.764177791
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1978396965
Short name T417
Test name
Test status
Simulation time 232315373 ps
CPU time 6.53 seconds
Started Apr 16 12:46:00 PM PDT 24
Finished Apr 16 12:46:14 PM PDT 24
Peak memory 206940 kb
Host smart-ff5d4aa8-861e-4d9d-a86b-194be9a12f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978396965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1978396965
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2219648062
Short name T414
Test name
Test status
Simulation time 72255665 ps
CPU time 2.64 seconds
Started Apr 16 12:45:47 PM PDT 24
Finished Apr 16 12:45:51 PM PDT 24
Peak memory 207108 kb
Host smart-f4643579-1df2-4d3c-a633-f24891b124f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219648062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2219648062
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1413100249
Short name T409
Test name
Test status
Simulation time 581776672 ps
CPU time 5.31 seconds
Started Apr 16 12:45:54 PM PDT 24
Finished Apr 16 12:46:01 PM PDT 24
Peak memory 207148 kb
Host smart-035c03a3-a580-4a2f-841b-ec5fe64a7c6d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413100249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1413100249
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.4108391429
Short name T489
Test name
Test status
Simulation time 208877543 ps
CPU time 6.09 seconds
Started Apr 16 12:45:52 PM PDT 24
Finished Apr 16 12:45:59 PM PDT 24
Peak memory 208300 kb
Host smart-635af5f9-4b7b-4f28-8ecd-540a24d99207
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108391429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4108391429
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1680857293
Short name T336
Test name
Test status
Simulation time 643484923 ps
CPU time 7.52 seconds
Started Apr 16 12:45:50 PM PDT 24
Finished Apr 16 12:45:58 PM PDT 24
Peak memory 209984 kb
Host smart-1eb3610d-6eec-492b-9458-8cc77a66b9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680857293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1680857293
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.370219107
Short name T366
Test name
Test status
Simulation time 25626050 ps
CPU time 1.93 seconds
Started Apr 16 12:45:58 PM PDT 24
Finished Apr 16 12:46:02 PM PDT 24
Peak memory 208592 kb
Host smart-a4ac7478-4fd1-4fef-b507-d2914acc1a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370219107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.370219107
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2551124276
Short name T562
Test name
Test status
Simulation time 45411283 ps
CPU time 2.95 seconds
Started Apr 16 12:45:42 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 208368 kb
Host smart-01bbdf02-12f6-43a6-8043-8643afc8697e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551124276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2551124276
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3404797452
Short name T653
Test name
Test status
Simulation time 109475201 ps
CPU time 1.77 seconds
Started Apr 16 12:45:41 PM PDT 24
Finished Apr 16 12:45:45 PM PDT 24
Peak memory 210168 kb
Host smart-c738a7bd-f5af-4b19-8793-4f68f513bcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404797452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3404797452
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.313072207
Short name T682
Test name
Test status
Simulation time 21737805 ps
CPU time 0.78 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:10 PM PDT 24
Peak memory 206240 kb
Host smart-d074a053-a672-4109-87ab-3f627675c2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313072207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.313072207
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2418125808
Short name T30
Test name
Test status
Simulation time 78858958 ps
CPU time 1.93 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:05 PM PDT 24
Peak memory 208092 kb
Host smart-092a4368-ac8f-4135-a9b4-6eb138cc154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418125808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2418125808
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1643773511
Short name T317
Test name
Test status
Simulation time 359941727 ps
CPU time 6.93 seconds
Started Apr 16 12:46:10 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 208956 kb
Host smart-f292ef97-c7cd-420c-9b97-68791d9d3ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643773511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1643773511
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.305047474
Short name T865
Test name
Test status
Simulation time 340142489 ps
CPU time 6.55 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 214616 kb
Host smart-da613464-6241-46ab-ab58-31c1a0892dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305047474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.305047474
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1840827878
Short name T777
Test name
Test status
Simulation time 404637018 ps
CPU time 4.94 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:05 PM PDT 24
Peak memory 219036 kb
Host smart-fbb17b4a-567b-4b72-9210-e9713d54287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840827878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1840827878
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1816766401
Short name T64
Test name
Test status
Simulation time 89785413 ps
CPU time 4.22 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 218436 kb
Host smart-f9f47d23-878f-4ef1-858d-f3f95d17b59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816766401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1816766401
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.410449176
Short name T270
Test name
Test status
Simulation time 66236808 ps
CPU time 2.51 seconds
Started Apr 16 12:46:02 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 206944 kb
Host smart-545f5174-fc47-4678-87b2-5e30059488c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410449176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.410449176
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.4248472795
Short name T706
Test name
Test status
Simulation time 94871140 ps
CPU time 2.93 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:06 PM PDT 24
Peak memory 207232 kb
Host smart-4f224dca-1924-49b7-9fdd-19700663cab4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248472795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.4248472795
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.52439871
Short name T280
Test name
Test status
Simulation time 54158381 ps
CPU time 2.99 seconds
Started Apr 16 12:45:43 PM PDT 24
Finished Apr 16 12:45:48 PM PDT 24
Peak memory 207112 kb
Host smart-cc3b800b-8514-4362-bfc2-7c37fbdeee7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52439871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.52439871
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1627046544
Short name T553
Test name
Test status
Simulation time 64181185 ps
CPU time 3.23 seconds
Started Apr 16 12:45:53 PM PDT 24
Finished Apr 16 12:45:57 PM PDT 24
Peak memory 208984 kb
Host smart-e2ae8892-f85e-46e0-9ab0-da64dc39aa4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627046544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1627046544
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3583392933
Short name T700
Test name
Test status
Simulation time 24846984 ps
CPU time 1.75 seconds
Started Apr 16 12:45:43 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 207556 kb
Host smart-94b4e14f-16f9-4b86-8c0e-85897722afe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583392933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3583392933
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3002980154
Short name T601
Test name
Test status
Simulation time 40661915 ps
CPU time 2.39 seconds
Started Apr 16 12:45:46 PM PDT 24
Finished Apr 16 12:45:49 PM PDT 24
Peak memory 207032 kb
Host smart-063e3278-dde6-4d2b-bdff-c76cb693be60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002980154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3002980154
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.228546277
Short name T373
Test name
Test status
Simulation time 483040036 ps
CPU time 10.96 seconds
Started Apr 16 12:46:11 PM PDT 24
Finished Apr 16 12:46:26 PM PDT 24
Peak memory 218760 kb
Host smart-d37028a2-15f4-4ddb-b030-1911bd3ca8c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228546277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.228546277
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3030598936
Short name T579
Test name
Test status
Simulation time 671457570 ps
CPU time 9.33 seconds
Started Apr 16 12:46:02 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 214580 kb
Host smart-b94b561d-15b4-453b-aaa3-9a49d254085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030598936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3030598936
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1060463849
Short name T743
Test name
Test status
Simulation time 191566720 ps
CPU time 1.94 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:12 PM PDT 24
Peak memory 210520 kb
Host smart-19b7e6d7-8012-459f-8d51-5d7520dafc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060463849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1060463849
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3665867786
Short name T810
Test name
Test status
Simulation time 11179739 ps
CPU time 0.92 seconds
Started Apr 16 12:45:05 PM PDT 24
Finished Apr 16 12:45:08 PM PDT 24
Peak memory 206260 kb
Host smart-7124a2ee-0fc2-47b1-900a-02b15355420a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665867786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3665867786
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1438918193
Short name T384
Test name
Test status
Simulation time 197901657 ps
CPU time 3.96 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 215540 kb
Host smart-505d8697-15b2-4691-8f3b-109d1c6ede1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1438918193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1438918193
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4017010994
Short name T458
Test name
Test status
Simulation time 1174571983 ps
CPU time 3.22 seconds
Started Apr 16 12:45:03 PM PDT 24
Finished Apr 16 12:45:09 PM PDT 24
Peak memory 210176 kb
Host smart-62933f59-204d-4972-96eb-a6ebe6048e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017010994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4017010994
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2540349049
Short name T895
Test name
Test status
Simulation time 208531795 ps
CPU time 1.79 seconds
Started Apr 16 12:44:48 PM PDT 24
Finished Apr 16 12:44:51 PM PDT 24
Peak memory 208740 kb
Host smart-3bbd81dd-bfa1-47e4-9694-23fd8e5e2982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540349049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2540349049
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1526783871
Short name T200
Test name
Test status
Simulation time 597895758 ps
CPU time 7.45 seconds
Started Apr 16 12:44:48 PM PDT 24
Finished Apr 16 12:44:56 PM PDT 24
Peak memory 214596 kb
Host smart-21c05697-a162-45b2-99cb-e8baf8cac44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526783871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1526783871
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.522650237
Short name T261
Test name
Test status
Simulation time 353667904 ps
CPU time 4.24 seconds
Started Apr 16 12:44:45 PM PDT 24
Finished Apr 16 12:44:50 PM PDT 24
Peak memory 214664 kb
Host smart-fcffd473-5107-49f6-ba49-1f1ad289d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522650237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.522650237
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2034515223
Short name T446
Test name
Test status
Simulation time 545818649 ps
CPU time 3.45 seconds
Started Apr 16 12:44:50 PM PDT 24
Finished Apr 16 12:44:54 PM PDT 24
Peak memory 214596 kb
Host smart-1744df47-6377-4d97-a6ba-e6fec6955fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034515223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2034515223
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3170064606
Short name T12
Test name
Test status
Simulation time 16453019273 ps
CPU time 312 seconds
Started Apr 16 12:45:03 PM PDT 24
Finished Apr 16 12:50:18 PM PDT 24
Peak memory 336176 kb
Host smart-5f9152b3-de76-4f43-b945-e06655f2cd0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170064606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3170064606
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.10628343
Short name T495
Test name
Test status
Simulation time 214977251 ps
CPU time 2.8 seconds
Started Apr 16 12:44:54 PM PDT 24
Finished Apr 16 12:44:58 PM PDT 24
Peak memory 207184 kb
Host smart-cf31d931-4ff2-48f9-b023-115cd27d97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10628343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.10628343
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1924089074
Short name T422
Test name
Test status
Simulation time 294369838 ps
CPU time 3.27 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 206944 kb
Host smart-9699a26f-aec3-4e55-aaf0-4982c6d1505d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924089074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1924089074
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1162287811
Short name T433
Test name
Test status
Simulation time 241445592 ps
CPU time 3.22 seconds
Started Apr 16 12:44:52 PM PDT 24
Finished Apr 16 12:44:56 PM PDT 24
Peak memory 207108 kb
Host smart-51aa1cba-69c1-4d62-9e49-f487d579dd91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162287811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1162287811
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4242244625
Short name T479
Test name
Test status
Simulation time 40901617 ps
CPU time 2.18 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 209168 kb
Host smart-53acaba5-d28c-4b7d-9df4-018c19c1a21e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242244625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4242244625
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1818188921
Short name T812
Test name
Test status
Simulation time 437441870 ps
CPU time 2.65 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 209688 kb
Host smart-3982693a-c8f1-4cf1-b5e0-52f09413dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818188921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1818188921
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4050876327
Short name T463
Test name
Test status
Simulation time 1822043206 ps
CPU time 44.74 seconds
Started Apr 16 12:45:01 PM PDT 24
Finished Apr 16 12:45:47 PM PDT 24
Peak memory 208196 kb
Host smart-0dfbfa58-ce89-4aff-ba35-e0d4b9de6672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050876327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4050876327
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3911313742
Short name T877
Test name
Test status
Simulation time 276385585 ps
CPU time 3.8 seconds
Started Apr 16 12:45:05 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 208932 kb
Host smart-6fd91ab2-64ce-448d-9dd6-abfb6b9938e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911313742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3911313742
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2896337854
Short name T177
Test name
Test status
Simulation time 2343716757 ps
CPU time 13.02 seconds
Started Apr 16 12:44:59 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 222932 kb
Host smart-c7c191cf-9953-43c5-ab4e-8d8c145d6b8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896337854 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2896337854
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3477787464
Short name T346
Test name
Test status
Simulation time 123845968 ps
CPU time 4.11 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 210024 kb
Host smart-6f6a4df7-ef24-42f2-8bba-3accee221a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477787464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3477787464
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3621462246
Short name T685
Test name
Test status
Simulation time 143545600 ps
CPU time 3.09 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 210608 kb
Host smart-2ffdb5b4-1668-4418-8bbc-b4e0b51eb147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621462246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3621462246
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1812740321
Short name T92
Test name
Test status
Simulation time 11078409 ps
CPU time 0.76 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:01 PM PDT 24
Peak memory 206256 kb
Host smart-fdc8b113-c0bc-4ce3-9292-4b7e4f35c754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812740321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1812740321
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3875655176
Short name T393
Test name
Test status
Simulation time 76904375 ps
CPU time 4.7 seconds
Started Apr 16 12:45:53 PM PDT 24
Finished Apr 16 12:46:00 PM PDT 24
Peak memory 214688 kb
Host smart-9b9f3adc-97b9-4aec-8dcb-19cd762560cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875655176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3875655176
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.335329399
Short name T753
Test name
Test status
Simulation time 55961927 ps
CPU time 2.66 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:08 PM PDT 24
Peak memory 207640 kb
Host smart-20b10f4c-adfa-4603-b50b-2c6c6ee6b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335329399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.335329399
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3401459801
Short name T636
Test name
Test status
Simulation time 392088928 ps
CPU time 7.5 seconds
Started Apr 16 12:46:09 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 208960 kb
Host smart-602e8634-4f52-4429-8f8f-a612aaea2c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401459801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3401459801
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2228784736
Short name T888
Test name
Test status
Simulation time 374512096 ps
CPU time 3.38 seconds
Started Apr 16 12:46:11 PM PDT 24
Finished Apr 16 12:46:18 PM PDT 24
Peak memory 209580 kb
Host smart-dbc50e02-8efd-4df7-93e8-1d5d8ee03ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228784736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2228784736
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1488643841
Short name T638
Test name
Test status
Simulation time 216322409 ps
CPU time 3.12 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:10 PM PDT 24
Peak memory 206948 kb
Host smart-a5a05052-7746-4b93-b928-7bd809bedc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488643841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1488643841
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3206467664
Short name T512
Test name
Test status
Simulation time 98442092 ps
CPU time 2.75 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 207128 kb
Host smart-11b78850-5f04-4a6d-b9a2-bdb0853f3950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206467664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3206467664
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1957974044
Short name T343
Test name
Test status
Simulation time 64991032 ps
CPU time 2.44 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:08 PM PDT 24
Peak memory 207112 kb
Host smart-fd1f834f-14bb-4fae-8dca-4fc9f1d18b1c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957974044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1957974044
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.4153252519
Short name T14
Test name
Test status
Simulation time 75063821 ps
CPU time 3.53 seconds
Started Apr 16 12:45:54 PM PDT 24
Finished Apr 16 12:45:59 PM PDT 24
Peak memory 208876 kb
Host smart-20e27df8-1805-467d-a16f-59aa14dd778d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153252519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.4153252519
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1602675265
Short name T349
Test name
Test status
Simulation time 711779685 ps
CPU time 5.28 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:09 PM PDT 24
Peak memory 207144 kb
Host smart-2ce9ec93-1010-4fd9-a76a-05aa585d27ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602675265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1602675265
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.529232712
Short name T15
Test name
Test status
Simulation time 787111923 ps
CPU time 10.92 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 209608 kb
Host smart-e279b309-588d-48fc-a1e5-e22414fa8a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529232712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.529232712
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4064270114
Short name T645
Test name
Test status
Simulation time 479860838 ps
CPU time 3.74 seconds
Started Apr 16 12:45:55 PM PDT 24
Finished Apr 16 12:46:00 PM PDT 24
Peak memory 206944 kb
Host smart-369396aa-2ccb-43c2-b9d5-6d3a3dd1cda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064270114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4064270114
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.779797157
Short name T175
Test name
Test status
Simulation time 2462465253 ps
CPU time 21.05 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 221844 kb
Host smart-7209207c-e467-4921-8ed8-42c77a0ece15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779797157 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.779797157
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1177954788
Short name T520
Test name
Test status
Simulation time 416430703 ps
CPU time 5.37 seconds
Started Apr 16 12:46:02 PM PDT 24
Finished Apr 16 12:46:09 PM PDT 24
Peak memory 209632 kb
Host smart-cecdf09c-d683-4054-bcc3-ad84ce0f93ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177954788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1177954788
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3462120044
Short name T159
Test name
Test status
Simulation time 57936214 ps
CPU time 2.57 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:12 PM PDT 24
Peak memory 210284 kb
Host smart-69094fc7-aacd-48c6-9d21-f7754e0510ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462120044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3462120044
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.613440846
Short name T426
Test name
Test status
Simulation time 44307295 ps
CPU time 0.71 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:17 PM PDT 24
Peak memory 206264 kb
Host smart-e7ab1d4f-7e7e-4424-ad16-35e2fcd5858f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613440846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.613440846
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2398592042
Short name T850
Test name
Test status
Simulation time 8950444958 ps
CPU time 59.99 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:47:11 PM PDT 24
Peak memory 222876 kb
Host smart-b187c4ba-7639-4371-a1e4-6d0f7b0ff694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398592042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2398592042
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3350145255
Short name T232
Test name
Test status
Simulation time 122600049 ps
CPU time 2.92 seconds
Started Apr 16 12:45:58 PM PDT 24
Finished Apr 16 12:46:02 PM PDT 24
Peak memory 222036 kb
Host smart-040a7f2e-c39f-4528-a14a-d6ed12ff4e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350145255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3350145255
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2470425949
Short name T536
Test name
Test status
Simulation time 68530330 ps
CPU time 1.66 seconds
Started Apr 16 12:45:56 PM PDT 24
Finished Apr 16 12:45:59 PM PDT 24
Peak memory 218476 kb
Host smart-0622e87a-233d-4277-bc2c-34daa66bf7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470425949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2470425949
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3986357359
Short name T249
Test name
Test status
Simulation time 150692898 ps
CPU time 4.63 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:08 PM PDT 24
Peak memory 214680 kb
Host smart-a977fa57-f455-45bd-8fcf-558ac9a58307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986357359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3986357359
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1693938311
Short name T813
Test name
Test status
Simulation time 947360306 ps
CPU time 7.45 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:17 PM PDT 24
Peak memory 214452 kb
Host smart-83226c73-e98a-4683-a6d0-a53d7fbd1f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693938311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1693938311
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2215704093
Short name T445
Test name
Test status
Simulation time 361592152 ps
CPU time 1.77 seconds
Started Apr 16 12:46:02 PM PDT 24
Finished Apr 16 12:46:06 PM PDT 24
Peak memory 214656 kb
Host smart-12a2ff66-af95-4b8e-acae-bbb26ce188ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215704093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2215704093
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.37584339
Short name T208
Test name
Test status
Simulation time 822410067 ps
CPU time 8.5 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:09 PM PDT 24
Peak memory 209468 kb
Host smart-181a4ef9-5bf0-473f-aa87-531feaf8d67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37584339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.37584339
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.990475633
Short name T205
Test name
Test status
Simulation time 146434400 ps
CPU time 2.38 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 207024 kb
Host smart-5115b31a-ee33-4813-959c-883e43ab40c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990475633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.990475633
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3006135217
Short name T639
Test name
Test status
Simulation time 1489841070 ps
CPU time 8.23 seconds
Started Apr 16 12:45:59 PM PDT 24
Finished Apr 16 12:46:08 PM PDT 24
Peak memory 208176 kb
Host smart-dcd6f9ed-4db2-4f5c-9ceb-08189f5826eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006135217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3006135217
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3587066583
Short name T667
Test name
Test status
Simulation time 151489497 ps
CPU time 3.46 seconds
Started Apr 16 12:45:53 PM PDT 24
Finished Apr 16 12:45:58 PM PDT 24
Peak memory 209120 kb
Host smart-c8f8be86-a462-445c-9ffd-eb199c811c12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587066583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3587066583
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2602433009
Short name T264
Test name
Test status
Simulation time 65006670 ps
CPU time 2.55 seconds
Started Apr 16 12:46:02 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 207444 kb
Host smart-ea60edea-6f02-4e1a-991c-9ded1a68252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602433009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2602433009
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2093134042
Short name T454
Test name
Test status
Simulation time 60587747 ps
CPU time 3.12 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 208764 kb
Host smart-5d796d83-b512-4035-9c2d-1710f0a3ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093134042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2093134042
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2843364740
Short name T233
Test name
Test status
Simulation time 38323599876 ps
CPU time 250.77 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:50:20 PM PDT 24
Peak memory 222796 kb
Host smart-e942d60a-dd5a-4528-a2b1-82b9fddce937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843364740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2843364740
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2249413558
Short name T121
Test name
Test status
Simulation time 1906252497 ps
CPU time 19.35 seconds
Started Apr 16 12:45:58 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 222860 kb
Host smart-0bd50409-289e-4747-9806-b2cd27b84ed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249413558 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2249413558
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.686050351
Short name T695
Test name
Test status
Simulation time 105554656 ps
CPU time 5.08 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:11 PM PDT 24
Peak memory 208880 kb
Host smart-5911df66-f639-4ea0-85f2-d98305013d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686050351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.686050351
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.779637033
Short name T535
Test name
Test status
Simulation time 115044595 ps
CPU time 1.74 seconds
Started Apr 16 12:46:00 PM PDT 24
Finished Apr 16 12:46:03 PM PDT 24
Peak memory 210060 kb
Host smart-d8a875df-edbb-4feb-b304-b546f1e3baf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779637033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.779637033
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1441231746
Short name T786
Test name
Test status
Simulation time 64534983 ps
CPU time 1 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:04 PM PDT 24
Peak memory 206300 kb
Host smart-31749d38-9b45-4b5b-8e6f-624c36d95343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441231746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1441231746
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2146413678
Short name T705
Test name
Test status
Simulation time 995802438 ps
CPU time 15.1 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 214504 kb
Host smart-f4e10ffe-d5f3-46aa-ae8e-a158112411e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146413678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2146413678
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2850171057
Short name T46
Test name
Test status
Simulation time 79167363 ps
CPU time 4.25 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 211572 kb
Host smart-25af394f-0282-4758-84f1-88fe89d6671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850171057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2850171057
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_random.32206202
Short name T500
Test name
Test status
Simulation time 127735718 ps
CPU time 5.58 seconds
Started Apr 16 12:46:00 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 209636 kb
Host smart-e3ad4b2f-44a7-4150-a7b3-96b3863ebb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32206202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.32206202
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2981363264
Short name T441
Test name
Test status
Simulation time 43895042 ps
CPU time 2.5 seconds
Started Apr 16 12:46:00 PM PDT 24
Finished Apr 16 12:46:03 PM PDT 24
Peak memory 208564 kb
Host smart-c5c2adac-fece-4967-b8db-08ea4062c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981363264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2981363264
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2434805899
Short name T432
Test name
Test status
Simulation time 374063433 ps
CPU time 4.62 seconds
Started Apr 16 12:46:02 PM PDT 24
Finished Apr 16 12:46:09 PM PDT 24
Peak memory 208664 kb
Host smart-beb1e5b9-c0fb-46e9-9525-bec057efb34a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434805899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2434805899
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3816491907
Short name T248
Test name
Test status
Simulation time 62884339 ps
CPU time 2.48 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:11 PM PDT 24
Peak memory 207212 kb
Host smart-65bc8cdd-5828-478d-9a23-64ba0309fc59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816491907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3816491907
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.332945274
Short name T210
Test name
Test status
Simulation time 26163857 ps
CPU time 2.03 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:06 PM PDT 24
Peak memory 208588 kb
Host smart-de8b916e-81cb-4565-b6d0-f811dd3462f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332945274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.332945274
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2479125988
Short name T484
Test name
Test status
Simulation time 357586773 ps
CPU time 2.25 seconds
Started Apr 16 12:46:10 PM PDT 24
Finished Apr 16 12:46:16 PM PDT 24
Peak memory 214692 kb
Host smart-68bf83f7-eec6-4e65-a91d-90fc45c22ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479125988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2479125988
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1522873528
Short name T532
Test name
Test status
Simulation time 55964226 ps
CPU time 1.87 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:09 PM PDT 24
Peak memory 207048 kb
Host smart-699c9a2a-15bb-4443-8890-a33065178820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522873528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1522873528
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1938782271
Short name T219
Test name
Test status
Simulation time 523341842 ps
CPU time 24.77 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:30 PM PDT 24
Peak memory 216052 kb
Host smart-cd838e50-a7e8-4000-98bf-9908df4fff51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938782271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1938782271
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.384480391
Short name T745
Test name
Test status
Simulation time 795682758 ps
CPU time 8.69 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:16 PM PDT 24
Peak memory 208852 kb
Host smart-37d14a86-baf5-41f2-b59a-96f84c421864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384480391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.384480391
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1902427123
Short name T573
Test name
Test status
Simulation time 72328037 ps
CPU time 2.41 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:08 PM PDT 24
Peak memory 210340 kb
Host smart-458becf9-a098-4b7d-9069-c47561deb861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902427123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1902427123
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3530495075
Short name T401
Test name
Test status
Simulation time 54008166 ps
CPU time 0.7 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:05 PM PDT 24
Peak memory 206288 kb
Host smart-aee85454-6094-4a67-bbad-2154010775f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530495075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3530495075
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1808780657
Short name T756
Test name
Test status
Simulation time 255412514 ps
CPU time 5.64 seconds
Started Apr 16 12:45:56 PM PDT 24
Finished Apr 16 12:46:03 PM PDT 24
Peak memory 218616 kb
Host smart-f3fd9e3e-53ec-4235-962d-fc6f259b7f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808780657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1808780657
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3148393585
Short name T332
Test name
Test status
Simulation time 2754700093 ps
CPU time 27.95 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:33 PM PDT 24
Peak memory 209828 kb
Host smart-611a39d0-9a3c-461a-9a9e-79da1d6ee660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148393585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3148393585
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3521675287
Short name T687
Test name
Test status
Simulation time 812742282 ps
CPU time 17.01 seconds
Started Apr 16 12:45:58 PM PDT 24
Finished Apr 16 12:46:16 PM PDT 24
Peak memory 209820 kb
Host smart-995ea28f-926e-48ba-9bf5-62e28350978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521675287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3521675287
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.926134917
Short name T692
Test name
Test status
Simulation time 1121458159 ps
CPU time 10.45 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:16 PM PDT 24
Peak memory 211072 kb
Host smart-09378760-803d-48b7-95f0-d6247b03c8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926134917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.926134917
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3823538596
Short name T389
Test name
Test status
Simulation time 80798599 ps
CPU time 2.64 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:08 PM PDT 24
Peak memory 214736 kb
Host smart-3641c1e5-3d05-4e27-8f75-bb8a6384f8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823538596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3823538596
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1870357786
Short name T290
Test name
Test status
Simulation time 70836479 ps
CPU time 4.76 seconds
Started Apr 16 12:46:00 PM PDT 24
Finished Apr 16 12:46:06 PM PDT 24
Peak memory 210348 kb
Host smart-f84389e6-a6d9-4526-90aa-bacb55275adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870357786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1870357786
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1691965296
Short name T310
Test name
Test status
Simulation time 1141773373 ps
CPU time 3.38 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:12 PM PDT 24
Peak memory 207056 kb
Host smart-1ba262e6-4153-44a9-ab81-b7f4d1a0f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691965296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1691965296
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2297272977
Short name T556
Test name
Test status
Simulation time 147350350 ps
CPU time 5.64 seconds
Started Apr 16 12:46:21 PM PDT 24
Finished Apr 16 12:46:28 PM PDT 24
Peak memory 208204 kb
Host smart-a345aac2-15ea-433f-bfbf-8ade429372d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297272977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2297272977
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.714743679
Short name T802
Test name
Test status
Simulation time 251781162 ps
CPU time 3.39 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:14 PM PDT 24
Peak memory 208704 kb
Host smart-bd5feb19-dc95-43c7-90bf-0e2f80f63265
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714743679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.714743679
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4086247975
Short name T614
Test name
Test status
Simulation time 4567523400 ps
CPU time 15.28 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:25 PM PDT 24
Peak memory 208728 kb
Host smart-ff750116-16d1-41b5-9c44-6feb549587bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086247975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4086247975
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2443154176
Short name T548
Test name
Test status
Simulation time 229094134 ps
CPU time 7.49 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:10 PM PDT 24
Peak memory 209468 kb
Host smart-931fd86a-3925-41a6-a5a0-1c46df4b24e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443154176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2443154176
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.586429187
Short name T551
Test name
Test status
Simulation time 460588768 ps
CPU time 3.95 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:10 PM PDT 24
Peak memory 206904 kb
Host smart-13d52e16-d2b1-4411-9ca0-32836e19c4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586429187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.586429187
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3597714672
Short name T793
Test name
Test status
Simulation time 619237129 ps
CPU time 12.52 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 209372 kb
Host smart-89d4b0bc-e59d-4858-84c7-fb67999c775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597714672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3597714672
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.4187289997
Short name T546
Test name
Test status
Simulation time 78325776 ps
CPU time 2.88 seconds
Started Apr 16 12:46:09 PM PDT 24
Finished Apr 16 12:46:16 PM PDT 24
Peak memory 210132 kb
Host smart-11cee56d-208c-43ef-b6b4-c02e3d852bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187289997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.4187289997
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3518404537
Short name T824
Test name
Test status
Simulation time 13080269 ps
CPU time 0.78 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 206284 kb
Host smart-cce53641-403b-4b43-a104-a4b95959015a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518404537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3518404537
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1014097919
Short name T289
Test name
Test status
Simulation time 161229869 ps
CPU time 8.65 seconds
Started Apr 16 12:46:11 PM PDT 24
Finished Apr 16 12:46:23 PM PDT 24
Peak memory 215068 kb
Host smart-ecddd3a3-3668-4e3b-8f0f-7758532986e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014097919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1014097919
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3845569689
Short name T98
Test name
Test status
Simulation time 147249647 ps
CPU time 3.96 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 214896 kb
Host smart-61818052-dbd0-487f-95d1-9e3f866f3a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845569689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3845569689
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2510268849
Short name T61
Test name
Test status
Simulation time 22610441 ps
CPU time 1.46 seconds
Started Apr 16 12:46:11 PM PDT 24
Finished Apr 16 12:46:17 PM PDT 24
Peak memory 207108 kb
Host smart-76b846b9-9a98-4f64-92b1-8e16c009b7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510268849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2510268849
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2377447246
Short name T302
Test name
Test status
Simulation time 10265772572 ps
CPU time 67.23 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:47:16 PM PDT 24
Peak memory 222800 kb
Host smart-310e9478-3b59-4fe3-beba-1841b607deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377447246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2377447246
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3921581721
Short name T415
Test name
Test status
Simulation time 94635386 ps
CPU time 1.98 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 206436 kb
Host smart-69c73d91-7b92-468a-a500-2698eede96d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921581721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3921581721
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.97673725
Short name T437
Test name
Test status
Simulation time 456504316 ps
CPU time 5.81 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:12 PM PDT 24
Peak memory 218732 kb
Host smart-6ad4ca10-d35b-4d5f-a3ce-7ac064c7e4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97673725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.97673725
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2195866649
Short name T642
Test name
Test status
Simulation time 1172214239 ps
CPU time 32.18 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:38 PM PDT 24
Peak memory 207972 kb
Host smart-945b5f32-8aa5-4214-b7fe-738b13afd12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195866649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2195866649
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3108258855
Short name T690
Test name
Test status
Simulation time 319030493 ps
CPU time 3.29 seconds
Started Apr 16 12:46:12 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 208848 kb
Host smart-153ded65-1966-428e-ba3d-9a11c1e59bd6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108258855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3108258855
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2863704378
Short name T897
Test name
Test status
Simulation time 414320286 ps
CPU time 5.02 seconds
Started Apr 16 12:46:11 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 207128 kb
Host smart-ed64e7c3-9e37-40dc-92ae-47b87ab4f73a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863704378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2863704378
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2571660588
Short name T473
Test name
Test status
Simulation time 121948297 ps
CPU time 4.01 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:10 PM PDT 24
Peak memory 207004 kb
Host smart-dd5573ec-b26c-4dfd-94c0-a60f8f82c950
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571660588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2571660588
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1693125964
Short name T427
Test name
Test status
Simulation time 94058631 ps
CPU time 2.03 seconds
Started Apr 16 12:46:00 PM PDT 24
Finished Apr 16 12:46:04 PM PDT 24
Peak memory 218496 kb
Host smart-e0eff2fe-33c3-4910-8fd7-d8ad9dbaf0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693125964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1693125964
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3569491384
Short name T724
Test name
Test status
Simulation time 750253580 ps
CPU time 4.44 seconds
Started Apr 16 12:46:15 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 208240 kb
Host smart-e51ac328-0c13-4428-810e-6f2d712bc280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569491384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3569491384
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1446761909
Short name T882
Test name
Test status
Simulation time 222602646 ps
CPU time 9.33 seconds
Started Apr 16 12:46:10 PM PDT 24
Finished Apr 16 12:46:23 PM PDT 24
Peak memory 222940 kb
Host smart-c867bf43-15e1-4fe3-a4bc-67c9399d420e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446761909 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1446761909
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.886338097
Short name T566
Test name
Test status
Simulation time 728921015 ps
CPU time 6.15 seconds
Started Apr 16 12:46:16 PM PDT 24
Finished Apr 16 12:46:25 PM PDT 24
Peak memory 218432 kb
Host smart-23c5a788-e330-42f1-b4aa-38ac25be403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886338097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.886338097
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3292236702
Short name T826
Test name
Test status
Simulation time 130474393 ps
CPU time 1.5 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:18 PM PDT 24
Peak memory 209800 kb
Host smart-dddbf7b6-0224-4531-bbbf-6f70f6f48235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292236702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3292236702
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.175299567
Short name T876
Test name
Test status
Simulation time 18745575 ps
CPU time 0.9 seconds
Started Apr 16 12:46:26 PM PDT 24
Finished Apr 16 12:46:28 PM PDT 24
Peak memory 206220 kb
Host smart-3011f6ac-eb98-4c9d-bfb8-09a70cedaa33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175299567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.175299567
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3336639487
Short name T737
Test name
Test status
Simulation time 186181255 ps
CPU time 4.34 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 215432 kb
Host smart-34b84240-ab82-4949-8b8c-42b5ba6fef7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336639487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3336639487
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1098281597
Short name T37
Test name
Test status
Simulation time 43681636 ps
CPU time 2.53 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 209604 kb
Host smart-da23dffb-8a06-4a02-8a85-31e27afb809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098281597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1098281597
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2449567055
Short name T522
Test name
Test status
Simulation time 384709082 ps
CPU time 2.33 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 207556 kb
Host smart-339dd669-8c0e-421e-943d-34831a536f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449567055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2449567055
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3896132354
Short name T702
Test name
Test status
Simulation time 104455216 ps
CPU time 3.58 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 216988 kb
Host smart-e90a4154-a599-480e-800e-e1eda19aaa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896132354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3896132354
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.388138525
Short name T241
Test name
Test status
Simulation time 301142267 ps
CPU time 3.66 seconds
Started Apr 16 12:46:31 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 222664 kb
Host smart-2d69dd4f-dd94-4dc0-ab18-b17d0060c31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388138525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.388138525
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3604501055
Short name T859
Test name
Test status
Simulation time 103210722 ps
CPU time 4.44 seconds
Started Apr 16 12:46:11 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 210512 kb
Host smart-5f24ac25-bd35-4bf7-8a0b-690dfbff7666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604501055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3604501055
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.644060587
Short name T620
Test name
Test status
Simulation time 213783071 ps
CPU time 3.58 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:10 PM PDT 24
Peak memory 218612 kb
Host smart-36305fda-7d55-4f87-9d9c-2a3c925c5200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644060587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.644060587
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3126726582
Short name T864
Test name
Test status
Simulation time 3165385426 ps
CPU time 31.19 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:47 PM PDT 24
Peak memory 208108 kb
Host smart-c06bd848-854c-4081-8d73-a526874a4523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126726582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3126726582
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2039134867
Short name T461
Test name
Test status
Simulation time 3388631375 ps
CPU time 47.07 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:56 PM PDT 24
Peak memory 208888 kb
Host smart-56994e18-c153-456c-aced-01c1986bee89
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039134867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2039134867
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.791915706
Short name T557
Test name
Test status
Simulation time 614812721 ps
CPU time 2.61 seconds
Started Apr 16 12:46:09 PM PDT 24
Finished Apr 16 12:46:15 PM PDT 24
Peak memory 207112 kb
Host smart-dd49aede-90ca-42dd-b76b-523710e205f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791915706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.791915706
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3950837821
Short name T630
Test name
Test status
Simulation time 285561011 ps
CPU time 3.57 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:14 PM PDT 24
Peak memory 209004 kb
Host smart-07209158-43e7-4ed8-9cca-1e64225098b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950837821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3950837821
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3627725139
Short name T467
Test name
Test status
Simulation time 76512598 ps
CPU time 3.57 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:12 PM PDT 24
Peak memory 215604 kb
Host smart-ecbef7b5-2bef-4254-ae1e-8f5e8e68f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627725139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3627725139
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1001354545
Short name T457
Test name
Test status
Simulation time 242682041 ps
CPU time 3.03 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:11 PM PDT 24
Peak memory 206936 kb
Host smart-1170f3f5-cf6c-4812-9b9f-f8ba53bb380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001354545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1001354545
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4206239233
Short name T188
Test name
Test status
Simulation time 16542758843 ps
CPU time 46.43 seconds
Started Apr 16 12:46:15 PM PDT 24
Finished Apr 16 12:47:04 PM PDT 24
Peak memory 217472 kb
Host smart-aabbf9ab-38ad-4209-a8c2-f696ec0835a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206239233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4206239233
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2598863626
Short name T115
Test name
Test status
Simulation time 445505787 ps
CPU time 27.35 seconds
Started Apr 16 12:46:42 PM PDT 24
Finished Apr 16 12:47:11 PM PDT 24
Peak memory 222896 kb
Host smart-6aef60de-6b58-4e30-9a02-d78f999295f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598863626 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2598863626
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2458832145
Short name T725
Test name
Test status
Simulation time 1045204895 ps
CPU time 26.21 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 208340 kb
Host smart-a3a00e24-1d80-4c53-9f61-d29ce5049553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458832145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2458832145
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1550467867
Short name T152
Test name
Test status
Simulation time 541564186 ps
CPU time 2.21 seconds
Started Apr 16 12:46:20 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 210168 kb
Host smart-2c560244-1b0e-4018-b5c8-d07d4475dc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550467867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1550467867
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3254080394
Short name T809
Test name
Test status
Simulation time 113788924 ps
CPU time 0.75 seconds
Started Apr 16 12:46:09 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 206240 kb
Host smart-e5763495-0f55-40cd-baa8-1ffdc2ed5d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254080394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3254080394
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.245988577
Short name T564
Test name
Test status
Simulation time 288046034 ps
CPU time 8.19 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:25 PM PDT 24
Peak memory 218484 kb
Host smart-ba220fce-84b7-48b6-b4b6-c005224e4fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245988577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.245988577
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.4164824027
Short name T822
Test name
Test status
Simulation time 744723150 ps
CPU time 3.97 seconds
Started Apr 16 12:46:25 PM PDT 24
Finished Apr 16 12:46:30 PM PDT 24
Peak memory 214564 kb
Host smart-5f21c971-3489-43ae-bcb6-07c63ee50e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164824027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.4164824027
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1010181163
Short name T616
Test name
Test status
Simulation time 825199030 ps
CPU time 13.13 seconds
Started Apr 16 12:46:07 PM PDT 24
Finished Apr 16 12:46:25 PM PDT 24
Peak memory 214616 kb
Host smart-03a6e2ff-5dd6-4803-a613-47b773ff368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010181163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1010181163
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2841509388
Short name T903
Test name
Test status
Simulation time 308620357 ps
CPU time 9.31 seconds
Started Apr 16 12:46:15 PM PDT 24
Finished Apr 16 12:46:27 PM PDT 24
Peak memory 214492 kb
Host smart-3f5d5922-c85e-4127-9b6a-9761ea72d6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841509388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2841509388
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1775091101
Short name T576
Test name
Test status
Simulation time 499611859 ps
CPU time 3.34 seconds
Started Apr 16 12:46:19 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 210568 kb
Host smart-39c466b0-44f6-4b96-9cc0-098790d545b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775091101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1775091101
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2136767438
Short name T795
Test name
Test status
Simulation time 130429118 ps
CPU time 4.08 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 209448 kb
Host smart-c183e384-6b4d-4e16-96f3-d1ab56f82798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136767438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2136767438
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2319964162
Short name T296
Test name
Test status
Simulation time 2109674599 ps
CPU time 14.82 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 208156 kb
Host smart-dd291a89-fa37-4617-a075-5f7e3a656d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319964162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2319964162
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3937284982
Short name T482
Test name
Test status
Simulation time 506813539 ps
CPU time 2.77 seconds
Started Apr 16 12:46:02 PM PDT 24
Finished Apr 16 12:46:07 PM PDT 24
Peak memory 207212 kb
Host smart-35ef4539-b74a-4e37-9618-3c09e406ebca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937284982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3937284982
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2555818598
Short name T570
Test name
Test status
Simulation time 39647114 ps
CPU time 2.41 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 207128 kb
Host smart-02790e00-94e9-471f-a4ee-d190da3ea8d3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555818598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2555818598
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2319102945
Short name T672
Test name
Test status
Simulation time 450790801 ps
CPU time 4.03 seconds
Started Apr 16 12:46:43 PM PDT 24
Finished Apr 16 12:46:49 PM PDT 24
Peak memory 207076 kb
Host smart-6d020039-d323-4e48-85ae-ee879a01fdf7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319102945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2319102945
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.929472376
Short name T244
Test name
Test status
Simulation time 1319930529 ps
CPU time 8.26 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:26 PM PDT 24
Peak memory 208740 kb
Host smart-53df1600-ab76-4090-8d4e-31795eb8d4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929472376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.929472376
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2530688779
Short name T714
Test name
Test status
Simulation time 560391874 ps
CPU time 3.31 seconds
Started Apr 16 12:46:05 PM PDT 24
Finished Apr 16 12:46:11 PM PDT 24
Peak memory 208928 kb
Host smart-9d0de3fa-3b03-4f0e-862c-9157661c06d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530688779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2530688779
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2673542844
Short name T380
Test name
Test status
Simulation time 215567911 ps
CPU time 7.65 seconds
Started Apr 16 12:46:12 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 207860 kb
Host smart-2c898b69-99a4-469d-9dcc-c6ceecf3cb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673542844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2673542844
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.974248886
Short name T731
Test name
Test status
Simulation time 2318570764 ps
CPU time 13.52 seconds
Started Apr 16 12:46:12 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 211100 kb
Host smart-70de7989-d70a-4b27-b305-0589d660d2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974248886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.974248886
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2318094071
Short name T593
Test name
Test status
Simulation time 12419830 ps
CPU time 0.88 seconds
Started Apr 16 12:46:15 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 206252 kb
Host smart-6ff3d7bb-043d-481f-a378-7b6b48133702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318094071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2318094071
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1519883770
Short name T352
Test name
Test status
Simulation time 327073718 ps
CPU time 7.89 seconds
Started Apr 16 12:46:11 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 210340 kb
Host smart-1604ee0b-25de-4061-8a78-3f590515824b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519883770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1519883770
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.616026036
Short name T486
Test name
Test status
Simulation time 791012498 ps
CPU time 18.89 seconds
Started Apr 16 12:46:07 PM PDT 24
Finished Apr 16 12:46:31 PM PDT 24
Peak memory 210092 kb
Host smart-a3370a55-19af-4faa-acaf-2cd847ae3abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616026036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.616026036
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4041487350
Short name T805
Test name
Test status
Simulation time 755530056 ps
CPU time 8.71 seconds
Started Apr 16 12:46:16 PM PDT 24
Finished Apr 16 12:46:27 PM PDT 24
Peak memory 214616 kb
Host smart-14e19c02-780f-4680-a849-ea5f70a50f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041487350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4041487350
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1275116852
Short name T538
Test name
Test status
Simulation time 106596155 ps
CPU time 3.64 seconds
Started Apr 16 12:46:04 PM PDT 24
Finished Apr 16 12:46:11 PM PDT 24
Peak memory 211304 kb
Host smart-a3cebdff-0abb-4e84-8193-766261cd3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275116852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1275116852
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3370057062
Short name T508
Test name
Test status
Simulation time 326499690 ps
CPU time 3.43 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 210044 kb
Host smart-befa96d7-b11d-4aff-8dc8-bc563ad9997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370057062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3370057062
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3115292926
Short name T465
Test name
Test status
Simulation time 246500783 ps
CPU time 4 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 210248 kb
Host smart-d0303864-982a-4231-beef-544415e9c211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115292926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3115292926
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.129031723
Short name T293
Test name
Test status
Simulation time 42419123 ps
CPU time 2.83 seconds
Started Apr 16 12:46:17 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 208996 kb
Host smart-7f71aaa6-6615-4bf2-9c19-b6c86379e2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129031723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.129031723
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1325221364
Short name T765
Test name
Test status
Simulation time 623165148 ps
CPU time 3.86 seconds
Started Apr 16 12:46:30 PM PDT 24
Finished Apr 16 12:46:36 PM PDT 24
Peak memory 209272 kb
Host smart-61c6403e-216a-4ee9-803d-13c154310e06
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325221364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1325221364
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3793972524
Short name T666
Test name
Test status
Simulation time 299916082 ps
CPU time 9.64 seconds
Started Apr 16 12:46:03 PM PDT 24
Finished Apr 16 12:46:15 PM PDT 24
Peak memory 207964 kb
Host smart-32dbdd37-6fc6-48eb-af05-9d14eced110a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793972524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3793972524
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3244148990
Short name T285
Test name
Test status
Simulation time 938386891 ps
CPU time 18.99 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 209188 kb
Host smart-6a0da7ac-84e3-4315-9541-84927543a05c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244148990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3244148990
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.40680818
Short name T619
Test name
Test status
Simulation time 26791908 ps
CPU time 1.52 seconds
Started Apr 16 12:46:33 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 208748 kb
Host smart-fce6f2eb-2f26-49ec-beb8-980cdd735ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40680818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.40680818
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.4206860434
Short name T431
Test name
Test status
Simulation time 32988608 ps
CPU time 2.45 seconds
Started Apr 16 12:46:07 PM PDT 24
Finished Apr 16 12:46:14 PM PDT 24
Peak memory 206876 kb
Host smart-c3492413-7648-4001-9457-16311ede0c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206860434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.4206860434
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2999715795
Short name T231
Test name
Test status
Simulation time 16865463679 ps
CPU time 111.96 seconds
Started Apr 16 12:46:12 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 222852 kb
Host smart-b2ff6dfb-2fa3-4a50-84c0-0128e8aea515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999715795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2999715795
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.4055171676
Short name T699
Test name
Test status
Simulation time 309251768 ps
CPU time 8.18 seconds
Started Apr 16 12:46:20 PM PDT 24
Finished Apr 16 12:46:30 PM PDT 24
Peak memory 220180 kb
Host smart-fb348c51-2e21-43bc-b670-a94d14014f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055171676 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.4055171676
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2018938391
Short name T597
Test name
Test status
Simulation time 87144691 ps
CPU time 4.09 seconds
Started Apr 16 12:46:10 PM PDT 24
Finished Apr 16 12:46:18 PM PDT 24
Peak memory 209928 kb
Host smart-f29bcdc6-72d6-4f71-a565-aa5087770c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018938391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2018938391
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1220742678
Short name T727
Test name
Test status
Simulation time 8861835 ps
CPU time 0.77 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:18 PM PDT 24
Peak memory 206112 kb
Host smart-28cd3ab5-35cb-46e3-af89-9af038b320aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220742678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1220742678
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3484044748
Short name T377
Test name
Test status
Simulation time 65188671 ps
CPU time 4.68 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 214700 kb
Host smart-d9346e8c-a846-4a33-a56c-c601e279462b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3484044748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3484044748
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2947712124
Short name T221
Test name
Test status
Simulation time 228861834 ps
CPU time 3.2 seconds
Started Apr 16 12:46:08 PM PDT 24
Finished Apr 16 12:46:15 PM PDT 24
Peak memory 208332 kb
Host smart-3fa64d5f-9b2c-423b-b837-5b1c11a54d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947712124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2947712124
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4033224027
Short name T18
Test name
Test status
Simulation time 38288664 ps
CPU time 1.46 seconds
Started Apr 16 12:46:19 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 207284 kb
Host smart-111c85b7-d847-4849-b0a9-8f2e174cb193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033224027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4033224027
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1090841330
Short name T85
Test name
Test status
Simulation time 3325285345 ps
CPU time 26.59 seconds
Started Apr 16 12:46:16 PM PDT 24
Finished Apr 16 12:46:46 PM PDT 24
Peak memory 214636 kb
Host smart-6d11cb2a-3db2-4762-a577-53bec2b869ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090841330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1090841330
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2741202332
Short name T740
Test name
Test status
Simulation time 35462996 ps
CPU time 2.51 seconds
Started Apr 16 12:46:19 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 214672 kb
Host smart-3f6cad67-7203-475d-871e-d90ec8c3cefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741202332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2741202332
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1424586164
Short name T65
Test name
Test status
Simulation time 109734330 ps
CPU time 4.91 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 214548 kb
Host smart-c047bd5f-fd79-436a-a05c-8349e3b36f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424586164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1424586164
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1644365606
Short name T728
Test name
Test status
Simulation time 243916887 ps
CPU time 3.08 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 209008 kb
Host smart-611fad3f-160d-4e94-9983-3c222e4d52ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644365606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1644365606
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2937366885
Short name T179
Test name
Test status
Simulation time 22782468 ps
CPU time 1.85 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:05 PM PDT 24
Peak memory 207068 kb
Host smart-0d2a003c-af3a-4ea8-b658-2b39099b5ca1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937366885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2937366885
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.496173505
Short name T641
Test name
Test status
Simulation time 165645460 ps
CPU time 2.38 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 207468 kb
Host smart-c7026a6a-1ac6-45b0-a82f-176114298350
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496173505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.496173505
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2720491465
Short name T73
Test name
Test status
Simulation time 1689585108 ps
CPU time 39.9 seconds
Started Apr 16 12:46:19 PM PDT 24
Finished Apr 16 12:47:01 PM PDT 24
Peak memory 208608 kb
Host smart-95ea9f05-e644-4f1c-8930-6f5fcc89bb62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720491465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2720491465
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3230901206
Short name T447
Test name
Test status
Simulation time 2730136102 ps
CPU time 29.86 seconds
Started Apr 16 12:46:11 PM PDT 24
Finished Apr 16 12:46:45 PM PDT 24
Peak memory 218968 kb
Host smart-f9e2126d-b6c7-4724-9e9c-030df488f3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230901206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3230901206
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3942027072
Short name T444
Test name
Test status
Simulation time 228628320 ps
CPU time 2.56 seconds
Started Apr 16 12:46:15 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 208120 kb
Host smart-0e225802-8d9f-4003-bde7-469fb9a6e352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942027072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3942027072
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1866861799
Short name T295
Test name
Test status
Simulation time 1227548442 ps
CPU time 30.24 seconds
Started Apr 16 12:46:02 PM PDT 24
Finished Apr 16 12:46:35 PM PDT 24
Peak memory 221784 kb
Host smart-cdb0aeb9-9748-4ef6-be0f-5f20997de6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866861799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1866861799
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.944304537
Short name T173
Test name
Test status
Simulation time 417814754 ps
CPU time 6.34 seconds
Started Apr 16 12:46:08 PM PDT 24
Finished Apr 16 12:46:18 PM PDT 24
Peak memory 222936 kb
Host smart-17e3a235-bba7-4851-9d9d-726599fca807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944304537 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.944304537
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1774658023
Short name T517
Test name
Test status
Simulation time 137043985 ps
CPU time 5.33 seconds
Started Apr 16 12:46:07 PM PDT 24
Finished Apr 16 12:46:17 PM PDT 24
Peak memory 209784 kb
Host smart-d70ecad3-1618-4e7f-a57b-5d11e192ea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774658023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1774658023
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2189032531
Short name T623
Test name
Test status
Simulation time 48337548 ps
CPU time 1.59 seconds
Started Apr 16 12:46:09 PM PDT 24
Finished Apr 16 12:46:15 PM PDT 24
Peak memory 209992 kb
Host smart-a31e77b8-9c00-4bd3-9f24-6de01388e4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189032531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2189032531
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2968183449
Short name T504
Test name
Test status
Simulation time 34912708 ps
CPU time 0.85 seconds
Started Apr 16 12:46:15 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 206280 kb
Host smart-fe21c809-14f9-4977-92c1-6a34e6a5b911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968183449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2968183449
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.119383827
Short name T269
Test name
Test status
Simulation time 1067270321 ps
CPU time 14.03 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:31 PM PDT 24
Peak memory 215932 kb
Host smart-f3cb242d-a286-4132-81bf-a75b51e022ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119383827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.119383827
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2317098999
Short name T586
Test name
Test status
Simulation time 420320889 ps
CPU time 3.39 seconds
Started Apr 16 12:46:20 PM PDT 24
Finished Apr 16 12:46:25 PM PDT 24
Peak memory 218272 kb
Host smart-c3978b99-08f6-4b64-8bbc-075a7ee6f5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317098999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2317098999
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1609565671
Short name T456
Test name
Test status
Simulation time 22626999 ps
CPU time 1.8 seconds
Started Apr 16 12:46:16 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 214512 kb
Host smart-9ea54959-9e97-4f58-8b50-4aa3699d91e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609565671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1609565671
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1968317635
Short name T80
Test name
Test status
Simulation time 201851161 ps
CPU time 5.68 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:16 PM PDT 24
Peak memory 214632 kb
Host smart-29782913-6606-4043-b2c8-6df7f715a4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968317635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1968317635
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.833471089
Short name T274
Test name
Test status
Simulation time 4970874868 ps
CPU time 99.22 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:47:56 PM PDT 24
Peak memory 231412 kb
Host smart-6d57b95f-744f-41a7-a50c-223f91a44871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833471089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.833471089
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1553863314
Short name T723
Test name
Test status
Simulation time 185786205 ps
CPU time 3.16 seconds
Started Apr 16 12:46:17 PM PDT 24
Finished Apr 16 12:46:23 PM PDT 24
Peak memory 220328 kb
Host smart-a178eb53-6dda-41db-b550-44e92bd6b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553863314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1553863314
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.294928624
Short name T501
Test name
Test status
Simulation time 83285589 ps
CPU time 4.3 seconds
Started Apr 16 12:46:11 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 214564 kb
Host smart-04cf5399-1f43-4d6a-a13b-1c0015637fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294928624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.294928624
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1763158849
Short name T582
Test name
Test status
Simulation time 233387036 ps
CPU time 6.78 seconds
Started Apr 16 12:46:10 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 208496 kb
Host smart-4dc8c290-267b-42e5-913f-d6de6bfb5dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763158849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1763158849
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.4065094440
Short name T686
Test name
Test status
Simulation time 100010657 ps
CPU time 2.62 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 207120 kb
Host smart-9df35175-3ece-4e07-adc0-6067cf68914d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065094440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4065094440
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2640965616
Short name T122
Test name
Test status
Simulation time 1495392431 ps
CPU time 36.01 seconds
Started Apr 16 12:46:01 PM PDT 24
Finished Apr 16 12:46:40 PM PDT 24
Peak memory 208268 kb
Host smart-d15d9816-0719-404a-9517-c2160415ef54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640965616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2640965616
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2865986065
Short name T514
Test name
Test status
Simulation time 75976394 ps
CPU time 3.55 seconds
Started Apr 16 12:46:37 PM PDT 24
Finished Apr 16 12:46:43 PM PDT 24
Peak memory 207100 kb
Host smart-f7884658-c9fa-4371-82e4-f4446e7f2581
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865986065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2865986065
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.4212570738
Short name T524
Test name
Test status
Simulation time 116638632 ps
CPU time 2.32 seconds
Started Apr 16 12:46:06 PM PDT 24
Finished Apr 16 12:46:13 PM PDT 24
Peak memory 207540 kb
Host smart-b82a1e5f-adfa-4d32-88c1-bcf713f28272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212570738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4212570738
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3819065850
Short name T194
Test name
Test status
Simulation time 204091902 ps
CPU time 3.23 seconds
Started Apr 16 12:46:17 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 208892 kb
Host smart-1b4eee52-e3fc-45c9-be9c-f84e5a53417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819065850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3819065850
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4173109397
Short name T502
Test name
Test status
Simulation time 15084999 ps
CPU time 0.74 seconds
Started Apr 16 12:46:25 PM PDT 24
Finished Apr 16 12:46:27 PM PDT 24
Peak memory 206212 kb
Host smart-c0db7fed-9ff3-435b-afc2-43cb85f7ac48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173109397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4173109397
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1603968752
Short name T245
Test name
Test status
Simulation time 439798906 ps
CPU time 4.45 seconds
Started Apr 16 12:46:18 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 207844 kb
Host smart-a5a29088-a3fd-41b1-bd18-a5887e32b10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603968752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1603968752
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2503722160
Short name T656
Test name
Test status
Simulation time 572459256 ps
CPU time 3.43 seconds
Started Apr 16 12:46:15 PM PDT 24
Finished Apr 16 12:46:25 PM PDT 24
Peak memory 210148 kb
Host smart-9fec5afc-3c3b-4064-ac92-d93936edabad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503722160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2503722160
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1404244805
Short name T402
Test name
Test status
Simulation time 12528987 ps
CPU time 0.76 seconds
Started Apr 16 12:45:02 PM PDT 24
Finished Apr 16 12:45:05 PM PDT 24
Peak memory 206144 kb
Host smart-bb03fc70-f0fd-4d31-891d-ca152c336615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404244805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1404244805
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2665131489
Short name T381
Test name
Test status
Simulation time 554488737 ps
CPU time 8.03 seconds
Started Apr 16 12:44:48 PM PDT 24
Finished Apr 16 12:44:57 PM PDT 24
Peak memory 214836 kb
Host smart-cd6e848e-c480-484d-9bf7-1d0d88ca52f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665131489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2665131489
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1468283521
Short name T213
Test name
Test status
Simulation time 847984071 ps
CPU time 23.46 seconds
Started Apr 16 12:45:01 PM PDT 24
Finished Apr 16 12:45:26 PM PDT 24
Peak memory 214508 kb
Host smart-259c09d5-1f37-478b-8469-65e3be8645bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468283521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1468283521
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2405497650
Short name T875
Test name
Test status
Simulation time 54460087 ps
CPU time 2.55 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 209768 kb
Host smart-9c21ad0f-4b0d-4d41-92d6-e6b8fa9d3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405497650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2405497650
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1472198283
Short name T1
Test name
Test status
Simulation time 1381103694 ps
CPU time 10.77 seconds
Started Apr 16 12:44:56 PM PDT 24
Finished Apr 16 12:45:08 PM PDT 24
Peak memory 214624 kb
Host smart-4a29b26d-957c-41ea-b430-10b59844e940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472198283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1472198283
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3502485551
Short name T90
Test name
Test status
Simulation time 300859334 ps
CPU time 4.28 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 210284 kb
Host smart-6f5b0702-275a-4643-9113-3f3c49b20e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502485551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3502485551
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.958002385
Short name T42
Test name
Test status
Simulation time 287400979 ps
CPU time 2.65 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:13 PM PDT 24
Peak memory 214580 kb
Host smart-80c6c4d9-12e0-4281-b5ad-58f8454b9592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958002385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.958002385
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2372018111
Short name T848
Test name
Test status
Simulation time 212884439 ps
CPU time 6.26 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 210148 kb
Host smart-0e570899-9970-431f-bc79-8f4ae00c5042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372018111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2372018111
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2467778949
Short name T11
Test name
Test status
Simulation time 787892805 ps
CPU time 17.04 seconds
Started Apr 16 12:45:04 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 240988 kb
Host smart-2b97e9d2-5231-42c1-bcc9-1fec2b1f8c22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467778949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2467778949
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.148846205
Short name T314
Test name
Test status
Simulation time 37555757 ps
CPU time 2.58 seconds
Started Apr 16 12:44:59 PM PDT 24
Finished Apr 16 12:45:03 PM PDT 24
Peak memory 208728 kb
Host smart-29add70f-9562-43a3-9c42-f1de7d4a32b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148846205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.148846205
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.722018555
Short name T590
Test name
Test status
Simulation time 206074120 ps
CPU time 2.86 seconds
Started Apr 16 12:45:03 PM PDT 24
Finished Apr 16 12:45:09 PM PDT 24
Peak memory 208760 kb
Host smart-b4666596-0413-4b08-a57f-5aff512f5315
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722018555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.722018555
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1020010757
Short name T338
Test name
Test status
Simulation time 2789419841 ps
CPU time 35.56 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:45 PM PDT 24
Peak memory 208808 kb
Host smart-f9e0a3f9-fc4d-4698-990b-ae45034c328b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020010757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1020010757
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1298735197
Short name T453
Test name
Test status
Simulation time 45628683 ps
CPU time 2.72 seconds
Started Apr 16 12:44:57 PM PDT 24
Finished Apr 16 12:45:01 PM PDT 24
Peak memory 207660 kb
Host smart-3fad757a-1fde-449e-b8f4-edaa1f2a3b4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298735197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1298735197
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1932346971
Short name T708
Test name
Test status
Simulation time 44402241 ps
CPU time 2.52 seconds
Started Apr 16 12:44:51 PM PDT 24
Finished Apr 16 12:44:54 PM PDT 24
Peak memory 207272 kb
Host smart-11e5055f-944a-49de-a1df-0ae4f644cd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932346971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1932346971
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.95316772
Short name T507
Test name
Test status
Simulation time 362031890 ps
CPU time 4.16 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 207308 kb
Host smart-a9bbd243-1969-440e-b8d5-6a0b69c2daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95316772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.95316772
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1802522187
Short name T132
Test name
Test status
Simulation time 4883562035 ps
CPU time 32.37 seconds
Started Apr 16 12:45:03 PM PDT 24
Finished Apr 16 12:45:38 PM PDT 24
Peak memory 222212 kb
Host smart-64f4b8f3-0783-4101-9c98-2972748fc23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802522187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1802522187
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.471145145
Short name T464
Test name
Test status
Simulation time 1911101813 ps
CPU time 46.04 seconds
Started Apr 16 12:44:44 PM PDT 24
Finished Apr 16 12:45:31 PM PDT 24
Peak memory 208824 kb
Host smart-836b69d9-b6c1-46a1-8bd1-af7b6df6ea1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471145145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.471145145
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2581800197
Short name T676
Test name
Test status
Simulation time 90278798 ps
CPU time 3.36 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 210112 kb
Host smart-ff64fc40-97d4-4c01-b2f0-2aab38cb33e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581800197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2581800197
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1346927957
Short name T629
Test name
Test status
Simulation time 9681414 ps
CPU time 0.82 seconds
Started Apr 16 12:46:12 PM PDT 24
Finished Apr 16 12:46:17 PM PDT 24
Peak memory 206184 kb
Host smart-5fd27a1d-417c-44b1-bf0b-c8f862e5f8c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346927957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1346927957
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3853413813
Short name T861
Test name
Test status
Simulation time 1909405996 ps
CPU time 4.4 seconds
Started Apr 16 12:46:12 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 218504 kb
Host smart-8ca8840a-80e6-43ba-8333-8aea1dbcfef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853413813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3853413813
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1696975671
Short name T76
Test name
Test status
Simulation time 117121941 ps
CPU time 5.43 seconds
Started Apr 16 12:46:35 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 214576 kb
Host smart-e503adb4-82f9-414b-948c-95da5a974617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696975671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1696975671
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.494647974
Short name T256
Test name
Test status
Simulation time 175188410 ps
CPU time 2.47 seconds
Started Apr 16 12:46:12 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 214568 kb
Host smart-c62dcea9-6f7c-4415-a98d-e898f03ce622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494647974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.494647974
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2748938476
Short name T483
Test name
Test status
Simulation time 157911727 ps
CPU time 4.09 seconds
Started Apr 16 12:46:15 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 214524 kb
Host smart-2f01af61-42f8-4ef3-b47a-91bafbf0e13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748938476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2748938476
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2733677726
Short name T202
Test name
Test status
Simulation time 670408353 ps
CPU time 5.92 seconds
Started Apr 16 12:46:09 PM PDT 24
Finished Apr 16 12:46:18 PM PDT 24
Peak memory 209940 kb
Host smart-a3349b28-20c1-4522-b508-a7e5ea46aab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733677726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2733677726
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2561249746
Short name T412
Test name
Test status
Simulation time 3643714483 ps
CPU time 37.38 seconds
Started Apr 16 12:46:21 PM PDT 24
Finished Apr 16 12:47:00 PM PDT 24
Peak memory 208832 kb
Host smart-40eab05e-7ac2-45dd-a9d6-a1e3d4052424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561249746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2561249746
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2851443537
Short name T539
Test name
Test status
Simulation time 1003731249 ps
CPU time 25.55 seconds
Started Apr 16 12:46:09 PM PDT 24
Finished Apr 16 12:46:38 PM PDT 24
Peak memory 208688 kb
Host smart-b280b826-257e-4c49-a71c-1180ec926279
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851443537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2851443537
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3174528247
Short name T207
Test name
Test status
Simulation time 64505894 ps
CPU time 3.35 seconds
Started Apr 16 12:46:28 PM PDT 24
Finished Apr 16 12:46:34 PM PDT 24
Peak memory 209156 kb
Host smart-4aa745df-bf3f-4e6b-9527-e14fd0010d5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174528247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3174528247
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.151708049
Short name T405
Test name
Test status
Simulation time 59930369 ps
CPU time 2.34 seconds
Started Apr 16 12:46:17 PM PDT 24
Finished Apr 16 12:46:32 PM PDT 24
Peak memory 206936 kb
Host smart-9a708ea2-dc40-4994-91c5-c0877dda9daa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151708049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.151708049
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.79057238
Short name T334
Test name
Test status
Simulation time 154077874 ps
CPU time 4.52 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 218732 kb
Host smart-331007fa-f567-43ee-b613-1c5f8fd21045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79057238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.79057238
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.252675801
Short name T449
Test name
Test status
Simulation time 1697296905 ps
CPU time 37.4 seconds
Started Apr 16 12:46:35 PM PDT 24
Finished Apr 16 12:47:15 PM PDT 24
Peak memory 208028 kb
Host smart-ae2939e3-f257-48cf-b537-d4ce5b9e4d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252675801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.252675801
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.566543624
Short name T764
Test name
Test status
Simulation time 380236614 ps
CPU time 18.16 seconds
Started Apr 16 12:46:18 PM PDT 24
Finished Apr 16 12:46:38 PM PDT 24
Peak memory 216616 kb
Host smart-62fec6d4-244b-4d29-8ea9-3cb483de0b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566543624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.566543624
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1464102448
Short name T899
Test name
Test status
Simulation time 905115729 ps
CPU time 23.23 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:49 PM PDT 24
Peak memory 219924 kb
Host smart-d54e2ec6-3292-48c7-befd-6589c623aa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464102448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1464102448
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.272776553
Short name T808
Test name
Test status
Simulation time 167030848 ps
CPU time 2.76 seconds
Started Apr 16 12:46:16 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 210216 kb
Host smart-d25d9f08-14a2-45ed-b1c0-3b62da1ddfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272776553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.272776553
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1397081105
Short name T411
Test name
Test status
Simulation time 14380048 ps
CPU time 0.7 seconds
Started Apr 16 12:46:28 PM PDT 24
Finished Apr 16 12:46:31 PM PDT 24
Peak memory 206304 kb
Host smart-3fea45c3-6057-44d6-a059-49c2c2a34fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397081105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1397081105
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.781387318
Short name T328
Test name
Test status
Simulation time 726254205 ps
CPU time 3.86 seconds
Started Apr 16 12:46:23 PM PDT 24
Finished Apr 16 12:46:28 PM PDT 24
Peak memory 215244 kb
Host smart-37d7857a-d36e-4bb0-a47b-54015f9e940d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=781387318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.781387318
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.828518242
Short name T8
Test name
Test status
Simulation time 38135295 ps
CPU time 1.54 seconds
Started Apr 16 12:46:18 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 217176 kb
Host smart-b47ece3b-98b4-488a-ab48-3416e460891f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828518242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.828518242
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2795242613
Short name T709
Test name
Test status
Simulation time 126749365 ps
CPU time 2.15 seconds
Started Apr 16 12:46:18 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 208440 kb
Host smart-f7455110-b62a-46b1-9999-8b953ae94d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795242613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2795242613
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1717612048
Short name T23
Test name
Test status
Simulation time 144231990 ps
CPU time 5.15 seconds
Started Apr 16 12:46:08 PM PDT 24
Finished Apr 16 12:46:17 PM PDT 24
Peak memory 214540 kb
Host smart-a146dc73-e010-4c44-8782-91b014dbec25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717612048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1717612048
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2601176360
Short name T350
Test name
Test status
Simulation time 1006923364 ps
CPU time 34.63 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:51 PM PDT 24
Peak memory 211508 kb
Host smart-690e2dba-f33c-4c8c-937a-25ea9c651001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601176360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2601176360
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.491130515
Short name T784
Test name
Test status
Simulation time 288866893 ps
CPU time 3.6 seconds
Started Apr 16 12:46:12 PM PDT 24
Finished Apr 16 12:46:19 PM PDT 24
Peak memory 208496 kb
Host smart-9c7cc55d-ba86-44c8-88e0-a5e50156e52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491130515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.491130515
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1556766614
Short name T279
Test name
Test status
Simulation time 518049306 ps
CPU time 4.62 seconds
Started Apr 16 12:46:19 PM PDT 24
Finished Apr 16 12:46:25 PM PDT 24
Peak memory 210488 kb
Host smart-a17739b1-322e-4747-a7ab-04298acb2fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556766614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1556766614
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2459830510
Short name T800
Test name
Test status
Simulation time 1198505140 ps
CPU time 28.02 seconds
Started Apr 16 12:46:50 PM PDT 24
Finished Apr 16 12:47:20 PM PDT 24
Peak memory 208404 kb
Host smart-4eae7f08-5c85-4304-8ec6-06e1937e4e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459830510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2459830510
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.4179561976
Short name T523
Test name
Test status
Simulation time 150047973 ps
CPU time 2.69 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 209128 kb
Host smart-442e70f1-ad6e-402e-826e-c5c01b1ffe3f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179561976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.4179561976
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1972687039
Short name T574
Test name
Test status
Simulation time 125106597 ps
CPU time 2.29 seconds
Started Apr 16 12:46:15 PM PDT 24
Finished Apr 16 12:46:20 PM PDT 24
Peak memory 208892 kb
Host smart-76d66f47-01c1-4d06-b985-cb6322469a63
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972687039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1972687039
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.263269283
Short name T475
Test name
Test status
Simulation time 709739289 ps
CPU time 10.82 seconds
Started Apr 16 12:46:30 PM PDT 24
Finished Apr 16 12:46:43 PM PDT 24
Peak memory 208504 kb
Host smart-baa1bd9e-d81a-4e3b-87ad-7dd35c3e9ea3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263269283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.263269283
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1653167369
Short name T735
Test name
Test status
Simulation time 75785865 ps
CPU time 3.74 seconds
Started Apr 16 12:46:50 PM PDT 24
Finished Apr 16 12:46:55 PM PDT 24
Peak memory 210036 kb
Host smart-2f5f8f2b-04a1-4f61-8a69-554347d72f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653167369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1653167369
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2246962056
Short name T834
Test name
Test status
Simulation time 654150533 ps
CPU time 3.42 seconds
Started Apr 16 12:46:16 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 206940 kb
Host smart-f4724014-b934-4431-a784-da83e04ff83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246962056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2246962056
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1438830836
Short name T325
Test name
Test status
Simulation time 33734987968 ps
CPU time 578.91 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:56:05 PM PDT 24
Peak memory 225032 kb
Host smart-76b3cec3-341d-4ba9-b50a-cfedf954aa8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438830836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1438830836
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1749587513
Short name T438
Test name
Test status
Simulation time 482208302 ps
CPU time 5.34 seconds
Started Apr 16 12:46:23 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 214604 kb
Host smart-354efd01-08e5-4dac-9133-94be5a0366ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749587513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1749587513
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1914550725
Short name T145
Test name
Test status
Simulation time 140358522 ps
CPU time 2.09 seconds
Started Apr 16 12:46:23 PM PDT 24
Finished Apr 16 12:46:27 PM PDT 24
Peak memory 210404 kb
Host smart-8827a538-f536-4119-88e7-dd0bb9bef0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914550725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1914550725
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3179568696
Short name T838
Test name
Test status
Simulation time 15871758 ps
CPU time 0.78 seconds
Started Apr 16 12:46:32 PM PDT 24
Finished Apr 16 12:46:36 PM PDT 24
Peak memory 206200 kb
Host smart-49337c24-eb0e-4e6e-8566-baaaaaf23f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179568696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3179568696
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.238026476
Short name T326
Test name
Test status
Simulation time 225329844 ps
CPU time 6.26 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 214552 kb
Host smart-ceda86a2-4265-443f-af91-04c9915c0a26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=238026476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.238026476
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3347241465
Short name T794
Test name
Test status
Simulation time 49973694 ps
CPU time 2.61 seconds
Started Apr 16 12:46:36 PM PDT 24
Finished Apr 16 12:46:41 PM PDT 24
Peak memory 209980 kb
Host smart-006f29e9-604a-4cc0-bfd9-ac1234ea6f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347241465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3347241465
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1823909389
Short name T869
Test name
Test status
Simulation time 144134770 ps
CPU time 1.92 seconds
Started Apr 16 12:46:20 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 208964 kb
Host smart-d03f5cc2-65d3-4ea7-8f84-7f71d88dc8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823909389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1823909389
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2218335464
Short name T832
Test name
Test status
Simulation time 134825862 ps
CPU time 3.54 seconds
Started Apr 16 12:46:29 PM PDT 24
Finished Apr 16 12:46:35 PM PDT 24
Peak memory 214688 kb
Host smart-db78c05f-9fdd-4ebd-bd18-e5fa3ea8dd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218335464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2218335464
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1035393520
Short name T198
Test name
Test status
Simulation time 75165118 ps
CPU time 3.68 seconds
Started Apr 16 12:46:35 PM PDT 24
Finished Apr 16 12:46:42 PM PDT 24
Peak memory 214800 kb
Host smart-be1f6ee6-ca7e-47aa-95a3-9dd0c39aa871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035393520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1035393520
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.403184020
Short name T788
Test name
Test status
Simulation time 170325415 ps
CPU time 3.22 seconds
Started Apr 16 12:46:25 PM PDT 24
Finished Apr 16 12:46:30 PM PDT 24
Peak memory 216584 kb
Host smart-24af649f-8e9e-4f8a-aa63-f7f70cf75fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403184020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.403184020
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2730418470
Short name T125
Test name
Test status
Simulation time 1051399033 ps
CPU time 8.71 seconds
Started Apr 16 12:46:45 PM PDT 24
Finished Apr 16 12:46:56 PM PDT 24
Peak memory 210788 kb
Host smart-3d544f43-00af-42be-a20e-00859a6f7d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730418470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2730418470
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1696362360
Short name T309
Test name
Test status
Simulation time 122434694 ps
CPU time 3.02 seconds
Started Apr 16 12:46:33 PM PDT 24
Finished Apr 16 12:46:40 PM PDT 24
Peak memory 207092 kb
Host smart-eae71607-025c-4be5-823a-190252f6f974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696362360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1696362360
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3855667092
Short name T694
Test name
Test status
Simulation time 997689383 ps
CPU time 3.56 seconds
Started Apr 16 12:46:23 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 207004 kb
Host smart-e57da62e-5b97-4f54-8abf-86d68dbe8827
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855667092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3855667092
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.289146926
Short name T787
Test name
Test status
Simulation time 85169768 ps
CPU time 3.74 seconds
Started Apr 16 12:46:28 PM PDT 24
Finished Apr 16 12:46:34 PM PDT 24
Peak memory 208884 kb
Host smart-fc3295cd-e742-448e-aa8a-512a968a45cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289146926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.289146926
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2453578472
Short name T294
Test name
Test status
Simulation time 840372240 ps
CPU time 3.93 seconds
Started Apr 16 12:46:21 PM PDT 24
Finished Apr 16 12:46:26 PM PDT 24
Peak memory 207240 kb
Host smart-084e7c01-d463-4678-afae-ddf8cbd12cf3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453578472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2453578472
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3612784473
Short name T605
Test name
Test status
Simulation time 1397780088 ps
CPU time 9.27 seconds
Started Apr 16 12:46:58 PM PDT 24
Finished Apr 16 12:47:11 PM PDT 24
Peak memory 209988 kb
Host smart-132f5adb-c892-4b90-8179-9a29c3fe40e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612784473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3612784473
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2956100485
Short name T442
Test name
Test status
Simulation time 243122245 ps
CPU time 2.2 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:28 PM PDT 24
Peak memory 206856 kb
Host smart-e65e6af2-d812-4faf-ab06-c48b18525f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956100485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2956100485
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3651382782
Short name T718
Test name
Test status
Simulation time 1040231514 ps
CPU time 11.28 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 209728 kb
Host smart-f061f407-14c4-4c2b-a41f-ab38244bf576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651382782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3651382782
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2898770619
Short name T34
Test name
Test status
Simulation time 43710535 ps
CPU time 2.69 seconds
Started Apr 16 12:46:29 PM PDT 24
Finished Apr 16 12:46:34 PM PDT 24
Peak memory 210000 kb
Host smart-677e4664-62bb-422b-84d2-958875768696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898770619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2898770619
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2102466649
Short name T533
Test name
Test status
Simulation time 70175779 ps
CPU time 0.99 seconds
Started Apr 16 12:46:27 PM PDT 24
Finished Apr 16 12:46:30 PM PDT 24
Peak memory 206336 kb
Host smart-5062a52e-189e-4e72-8d85-269a5c42e3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102466649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2102466649
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2913353736
Short name T235
Test name
Test status
Simulation time 175422800 ps
CPU time 8.71 seconds
Started Apr 16 12:46:23 PM PDT 24
Finished Apr 16 12:46:33 PM PDT 24
Peak memory 215244 kb
Host smart-a50ec1a4-cc7c-4db4-88bf-1208319dc29d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913353736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2913353736
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3078031144
Short name T780
Test name
Test status
Simulation time 173177472 ps
CPU time 4.62 seconds
Started Apr 16 12:46:43 PM PDT 24
Finished Apr 16 12:46:49 PM PDT 24
Peak memory 210408 kb
Host smart-50219324-3549-44ae-98b6-a57fcef5bef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078031144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3078031144
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3446576288
Short name T24
Test name
Test status
Simulation time 896528592 ps
CPU time 3.75 seconds
Started Apr 16 12:46:28 PM PDT 24
Finished Apr 16 12:46:34 PM PDT 24
Peak memory 208956 kb
Host smart-5b78b4ad-4a03-4935-b339-9031a7fcbd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446576288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3446576288
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3430895463
Short name T840
Test name
Test status
Simulation time 186436142 ps
CPU time 2.99 seconds
Started Apr 16 12:46:26 PM PDT 24
Finished Apr 16 12:46:30 PM PDT 24
Peak memory 218552 kb
Host smart-a45b038f-bf97-4382-884e-9ee24b1e1925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430895463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3430895463
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.225829375
Short name T856
Test name
Test status
Simulation time 288677918 ps
CPU time 7.65 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:24 PM PDT 24
Peak memory 208376 kb
Host smart-4de31f65-8cae-4272-a5f8-f8200956ed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225829375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.225829375
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2401801989
Short name T67
Test name
Test status
Simulation time 95166737 ps
CPU time 3.88 seconds
Started Apr 16 12:46:23 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 208776 kb
Host smart-3ae9f3cb-aa35-4e84-84d5-5a50c112dcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401801989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2401801989
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1009520587
Short name T595
Test name
Test status
Simulation time 449746891 ps
CPU time 3.78 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 207596 kb
Host smart-49678b54-363b-43ab-82e2-c81577c4e758
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009520587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1009520587
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2225350937
Short name T496
Test name
Test status
Simulation time 237401455 ps
CPU time 3.13 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 207168 kb
Host smart-2daa5539-6e37-484c-91f9-c2a769ae4c82
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225350937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2225350937
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.107799497
Short name T311
Test name
Test status
Simulation time 64707548 ps
CPU time 2.34 seconds
Started Apr 16 12:46:33 PM PDT 24
Finished Apr 16 12:46:38 PM PDT 24
Peak memory 207108 kb
Host smart-aa9818de-33a7-4edb-bac6-552e8d3a5efe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107799497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.107799497
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2357861837
Short name T540
Test name
Test status
Simulation time 53315603 ps
CPU time 1.67 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:28 PM PDT 24
Peak memory 207788 kb
Host smart-a2079915-f55b-402b-a3f7-ac084699e489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357861837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2357861837
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.344382731
Short name T654
Test name
Test status
Simulation time 233109654 ps
CPU time 3.03 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 207092 kb
Host smart-d9c1c8c0-39c0-46f4-bdf1-2046d5034379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344382731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.344382731
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1889867497
Short name T344
Test name
Test status
Simulation time 2638930662 ps
CPU time 65.02 seconds
Started Apr 16 12:46:33 PM PDT 24
Finished Apr 16 12:47:41 PM PDT 24
Peak memory 222840 kb
Host smart-c17f945a-7c0a-4cb2-aa3f-664bad990de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889867497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1889867497
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.751388774
Short name T732
Test name
Test status
Simulation time 661729490 ps
CPU time 4.93 seconds
Started Apr 16 12:46:23 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 214612 kb
Host smart-3a636dc0-b958-4a49-898e-aa0900758be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751388774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.751388774
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.82015076
Short name T668
Test name
Test status
Simulation time 38553627 ps
CPU time 1.6 seconds
Started Apr 16 12:46:33 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 210036 kb
Host smart-8f35a694-99d6-447a-aeb8-73afbb3f9a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82015076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.82015076
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3508357084
Short name T575
Test name
Test status
Simulation time 11619232 ps
CPU time 0.87 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:26 PM PDT 24
Peak memory 206296 kb
Host smart-a8456204-034e-4eea-b4fa-fe00b348bb28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508357084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3508357084
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1915544324
Short name T643
Test name
Test status
Simulation time 961891483 ps
CPU time 36.88 seconds
Started Apr 16 12:46:31 PM PDT 24
Finished Apr 16 12:47:10 PM PDT 24
Peak memory 222644 kb
Host smart-28d4ba8a-15ae-435e-a0fd-67649b8faf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915544324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1915544324
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.932417854
Short name T886
Test name
Test status
Simulation time 211203840 ps
CPU time 1.88 seconds
Started Apr 16 12:46:32 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 208432 kb
Host smart-02642495-49b6-4823-8e0f-a6ddff84b07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932417854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.932417854
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2719667384
Short name T890
Test name
Test status
Simulation time 630201895 ps
CPU time 6.14 seconds
Started Apr 16 12:46:13 PM PDT 24
Finished Apr 16 12:46:22 PM PDT 24
Peak memory 209312 kb
Host smart-71c32562-0cc7-48f5-bec0-0dde4e8920fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719667384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2719667384
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1176566199
Short name T319
Test name
Test status
Simulation time 74122822 ps
CPU time 4.3 seconds
Started Apr 16 12:46:26 PM PDT 24
Finished Apr 16 12:46:32 PM PDT 24
Peak memory 222744 kb
Host smart-82e35311-1896-47b4-abf7-69c08ed850be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176566199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1176566199
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1417475374
Short name T38
Test name
Test status
Simulation time 1435314798 ps
CPU time 3.49 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 210308 kb
Host smart-b8b609c1-8a02-4363-b7dc-f629185dbae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417475374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1417475374
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3885302015
Short name T246
Test name
Test status
Simulation time 1112303999 ps
CPU time 5.46 seconds
Started Apr 16 12:46:26 PM PDT 24
Finished Apr 16 12:46:32 PM PDT 24
Peak memory 207144 kb
Host smart-67064152-78c1-43ec-b67c-40ed426ff60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885302015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3885302015
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2256536892
Short name T587
Test name
Test status
Simulation time 46952722 ps
CPU time 2.6 seconds
Started Apr 16 12:46:28 PM PDT 24
Finished Apr 16 12:46:33 PM PDT 24
Peak memory 208696 kb
Host smart-7b4de6fd-4cc7-45fd-a09b-c33c9ae593b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256536892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2256536892
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.310119171
Short name T180
Test name
Test status
Simulation time 208229739 ps
CPU time 4.8 seconds
Started Apr 16 12:46:32 PM PDT 24
Finished Apr 16 12:46:40 PM PDT 24
Peak memory 206996 kb
Host smart-8001b81e-ff6b-4111-89b8-9fd3a5052cce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310119171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.310119171
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1518099588
Short name T770
Test name
Test status
Simulation time 59928067 ps
CPU time 2.95 seconds
Started Apr 16 12:46:23 PM PDT 24
Finished Apr 16 12:46:28 PM PDT 24
Peak memory 208796 kb
Host smart-c3f56409-090e-4b23-a4d0-e6b389dacea7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518099588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1518099588
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1223271213
Short name T559
Test name
Test status
Simulation time 49624197 ps
CPU time 2.76 seconds
Started Apr 16 12:46:27 PM PDT 24
Finished Apr 16 12:46:32 PM PDT 24
Peak memory 206964 kb
Host smart-370d3b71-93fc-49f8-8546-fde015f55bb6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223271213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1223271213
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.539031005
Short name T549
Test name
Test status
Simulation time 154837891 ps
CPU time 3.4 seconds
Started Apr 16 12:46:21 PM PDT 24
Finished Apr 16 12:46:26 PM PDT 24
Peak memory 214624 kb
Host smart-e958a88b-f05a-4710-aca9-d6a9b8c20e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539031005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.539031005
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2964518715
Short name T374
Test name
Test status
Simulation time 120787580 ps
CPU time 4.49 seconds
Started Apr 16 12:46:38 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 208036 kb
Host smart-eefd5e59-4c3e-420f-91c7-dc66d3302172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964518715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2964518715
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3531255204
Short name T45
Test name
Test status
Simulation time 2039522698 ps
CPU time 51.02 seconds
Started Apr 16 12:46:21 PM PDT 24
Finished Apr 16 12:47:14 PM PDT 24
Peak memory 222896 kb
Host smart-1d91a226-cdac-4e1b-b55d-3dd06d68734a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531255204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3531255204
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3008685960
Short name T399
Test name
Test status
Simulation time 40721356 ps
CPU time 2.76 seconds
Started Apr 16 12:46:14 PM PDT 24
Finished Apr 16 12:46:21 PM PDT 24
Peak memory 214592 kb
Host smart-f5cb0210-2f8d-4177-ab80-bd9cfb1421c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008685960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3008685960
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2653052049
Short name T889
Test name
Test status
Simulation time 64459350 ps
CPU time 2.25 seconds
Started Apr 16 12:46:38 PM PDT 24
Finished Apr 16 12:46:42 PM PDT 24
Peak memory 210716 kb
Host smart-46d54ea2-9134-4cfb-8a87-23851defb2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653052049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2653052049
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2834486089
Short name T403
Test name
Test status
Simulation time 47466156 ps
CPU time 0.81 seconds
Started Apr 16 12:46:36 PM PDT 24
Finished Apr 16 12:46:40 PM PDT 24
Peak memory 206212 kb
Host smart-198c4b03-f1a1-4b5e-8810-2de023e54617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834486089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2834486089
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.406942669
Short name T29
Test name
Test status
Simulation time 126912691 ps
CPU time 4.21 seconds
Started Apr 16 12:46:33 PM PDT 24
Finished Apr 16 12:46:40 PM PDT 24
Peak memory 214540 kb
Host smart-c91e2a36-85c2-4d28-b426-4dc43739f2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406942669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.406942669
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3804771304
Short name T291
Test name
Test status
Simulation time 313681986 ps
CPU time 2.76 seconds
Started Apr 16 12:46:35 PM PDT 24
Finished Apr 16 12:46:41 PM PDT 24
Peak memory 207552 kb
Host smart-55b239d6-2320-482b-89f4-480a0b9a2a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804771304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3804771304
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1504361592
Short name T608
Test name
Test status
Simulation time 848621109 ps
CPU time 4.86 seconds
Started Apr 16 12:46:47 PM PDT 24
Finished Apr 16 12:46:53 PM PDT 24
Peak memory 218256 kb
Host smart-97efa9dd-95a9-49eb-91c9-503a94f64f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504361592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1504361592
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.4239869278
Short name T650
Test name
Test status
Simulation time 273427383 ps
CPU time 3.79 seconds
Started Apr 16 12:46:43 PM PDT 24
Finished Apr 16 12:46:48 PM PDT 24
Peak memory 211952 kb
Host smart-7340f919-eae0-4bd2-a192-2da70fedc110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239869278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.4239869278
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1413532701
Short name T43
Test name
Test status
Simulation time 781505885 ps
CPU time 5.04 seconds
Started Apr 16 12:46:53 PM PDT 24
Finished Apr 16 12:47:00 PM PDT 24
Peak memory 209932 kb
Host smart-aedd48d5-9de8-4191-80a0-79a2fe0096fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413532701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1413532701
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2556504229
Short name T664
Test name
Test status
Simulation time 35508719 ps
CPU time 2.56 seconds
Started Apr 16 12:46:40 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 214516 kb
Host smart-0eb69563-7dcd-44f1-acb1-a81e2c53d6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556504229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2556504229
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1637199302
Short name T887
Test name
Test status
Simulation time 398317223 ps
CPU time 4.36 seconds
Started Apr 16 12:46:31 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 208644 kb
Host smart-3c9735b6-6530-4cba-9a51-fb9d57cb7444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637199302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1637199302
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.866961477
Short name T543
Test name
Test status
Simulation time 193678889 ps
CPU time 2.94 seconds
Started Apr 16 12:46:27 PM PDT 24
Finished Apr 16 12:46:32 PM PDT 24
Peak memory 207112 kb
Host smart-4ba8f81d-8bc3-4809-a0ff-a5bfccbfad17
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866961477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.866961477
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3635741625
Short name T854
Test name
Test status
Simulation time 118875145 ps
CPU time 4.44 seconds
Started Apr 16 12:46:30 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 206840 kb
Host smart-da01c8bc-0c91-47c7-95d7-c9906733bd27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635741625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3635741625
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2353028840
Short name T715
Test name
Test status
Simulation time 91894134 ps
CPU time 3.3 seconds
Started Apr 16 12:46:36 PM PDT 24
Finished Apr 16 12:46:42 PM PDT 24
Peak memory 208472 kb
Host smart-e1b27958-236c-42a1-a5f4-1fa1027338a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353028840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2353028840
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.4225014058
Short name T680
Test name
Test status
Simulation time 293527389 ps
CPU time 5.51 seconds
Started Apr 16 12:46:34 PM PDT 24
Finished Apr 16 12:46:43 PM PDT 24
Peak memory 207588 kb
Host smart-c5c3ec82-ce57-41a8-a6e1-1e0b6ef828a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225014058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4225014058
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1763786584
Short name T368
Test name
Test status
Simulation time 199397407 ps
CPU time 2.8 seconds
Started Apr 16 12:46:26 PM PDT 24
Finished Apr 16 12:46:31 PM PDT 24
Peak memory 207024 kb
Host smart-eba20995-e4aa-4577-99f0-2ca012131671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763786584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1763786584
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1677826760
Short name T96
Test name
Test status
Simulation time 669213862 ps
CPU time 8.3 seconds
Started Apr 16 12:46:33 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 207852 kb
Host smart-b6715302-adb9-4fa6-a50b-42ae7ceb06ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677826760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1677826760
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3359603338
Short name T691
Test name
Test status
Simulation time 38283369 ps
CPU time 1.64 seconds
Started Apr 16 12:46:36 PM PDT 24
Finished Apr 16 12:46:40 PM PDT 24
Peak memory 209888 kb
Host smart-367b31ab-1cde-46b3-8d84-171d57a82b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359603338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3359603338
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2149481286
Short name T436
Test name
Test status
Simulation time 26521733 ps
CPU time 0.76 seconds
Started Apr 16 12:46:43 PM PDT 24
Finished Apr 16 12:46:46 PM PDT 24
Peak memory 206236 kb
Host smart-4ba0581c-271d-49a3-b0a4-e9fae3a55557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149481286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2149481286
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2942702972
Short name T109
Test name
Test status
Simulation time 525050018 ps
CPU time 14.13 seconds
Started Apr 16 12:46:43 PM PDT 24
Finished Apr 16 12:46:59 PM PDT 24
Peak memory 214512 kb
Host smart-e42d808d-33f4-446a-9a9c-90b936633439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942702972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2942702972
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1247467277
Short name T635
Test name
Test status
Simulation time 29054586 ps
CPU time 1.52 seconds
Started Apr 16 12:46:56 PM PDT 24
Finished Apr 16 12:47:01 PM PDT 24
Peak memory 208280 kb
Host smart-fd32ae7f-3cc1-4645-b1ad-cdb5416cd9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247467277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1247467277
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1285817556
Short name T552
Test name
Test status
Simulation time 219414127 ps
CPU time 4.14 seconds
Started Apr 16 12:46:44 PM PDT 24
Finished Apr 16 12:46:50 PM PDT 24
Peak memory 208708 kb
Host smart-6a4fbac8-9c8c-4f54-8d6e-0700c4d837f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285817556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1285817556
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2630900137
Short name T318
Test name
Test status
Simulation time 375952462 ps
CPU time 8.15 seconds
Started Apr 16 12:46:40 PM PDT 24
Finished Apr 16 12:46:49 PM PDT 24
Peak memory 222668 kb
Host smart-e569426c-a0d5-4b81-8424-c77f4854283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630900137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2630900137
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3842619704
Short name T624
Test name
Test status
Simulation time 160988566 ps
CPU time 3.73 seconds
Started Apr 16 12:46:22 PM PDT 24
Finished Apr 16 12:46:27 PM PDT 24
Peak memory 206480 kb
Host smart-4e258862-42e1-48e3-af11-e753b1496196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842619704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3842619704
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.504287754
Short name T237
Test name
Test status
Simulation time 120385669 ps
CPU time 4.87 seconds
Started Apr 16 12:46:35 PM PDT 24
Finished Apr 16 12:46:42 PM PDT 24
Peak memory 214632 kb
Host smart-0c1cae31-2cf8-41a6-bf38-5f1432394818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504287754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.504287754
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.624207809
Short name T340
Test name
Test status
Simulation time 56779057 ps
CPU time 2.27 seconds
Started Apr 16 12:46:41 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 209088 kb
Host smart-1f28c1e0-2758-44fb-b7ac-440039525d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624207809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.624207809
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1039360108
Short name T443
Test name
Test status
Simulation time 248987139 ps
CPU time 2.01 seconds
Started Apr 16 12:46:33 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 209008 kb
Host smart-f70f5deb-ebbe-4219-8e9b-083f4c5b6de2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039360108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1039360108
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.166349283
Short name T817
Test name
Test status
Simulation time 234741687 ps
CPU time 3.29 seconds
Started Apr 16 12:46:30 PM PDT 24
Finished Apr 16 12:46:36 PM PDT 24
Peak memory 207648 kb
Host smart-55e30bb2-c874-48b8-aa83-f23fcbfe9dad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166349283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.166349283
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1434784877
Short name T598
Test name
Test status
Simulation time 138670636 ps
CPU time 3.55 seconds
Started Apr 16 12:46:41 PM PDT 24
Finished Apr 16 12:46:46 PM PDT 24
Peak memory 208808 kb
Host smart-9a5a9879-b97d-41b8-a9c3-ac79de05a98c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434784877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1434784877
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2485993668
Short name T193
Test name
Test status
Simulation time 136578512 ps
CPU time 4.94 seconds
Started Apr 16 12:46:23 PM PDT 24
Finished Apr 16 12:46:29 PM PDT 24
Peak memory 209612 kb
Host smart-eccd0d4a-9e06-4da2-a81a-ff09134cd8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485993668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2485993668
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2336037395
Short name T755
Test name
Test status
Simulation time 47082086 ps
CPU time 2.49 seconds
Started Apr 16 12:46:32 PM PDT 24
Finished Apr 16 12:46:36 PM PDT 24
Peak memory 207000 kb
Host smart-ed62f1ef-9f5e-476f-8885-fdee90f986f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336037395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2336037395
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2416770089
Short name T254
Test name
Test status
Simulation time 1148910842 ps
CPU time 24.7 seconds
Started Apr 16 12:46:38 PM PDT 24
Finished Apr 16 12:47:04 PM PDT 24
Peak memory 216612 kb
Host smart-a2ca0e1d-5b91-4ce4-8e02-38cb38df516b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416770089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2416770089
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.761859113
Short name T388
Test name
Test status
Simulation time 663141213 ps
CPU time 9.61 seconds
Started Apr 16 12:46:47 PM PDT 24
Finished Apr 16 12:46:58 PM PDT 24
Peak memory 209732 kb
Host smart-416568a1-c606-465b-aa5e-51ee537e624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761859113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.761859113
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.334634700
Short name T499
Test name
Test status
Simulation time 341068455 ps
CPU time 2.87 seconds
Started Apr 16 12:46:32 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 210452 kb
Host smart-ae3b752a-8a9f-4576-8638-9ba52c3cc87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334634700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.334634700
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1564869946
Short name T545
Test name
Test status
Simulation time 36325489 ps
CPU time 0.73 seconds
Started Apr 16 12:46:35 PM PDT 24
Finished Apr 16 12:46:39 PM PDT 24
Peak memory 206276 kb
Host smart-c68399e7-63d6-49fd-adb5-b34b3585aae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564869946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1564869946
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3739056463
Short name T130
Test name
Test status
Simulation time 45312446 ps
CPU time 3.62 seconds
Started Apr 16 12:46:42 PM PDT 24
Finished Apr 16 12:46:47 PM PDT 24
Peak memory 215892 kb
Host smart-3b65a2cb-40b7-479d-9d05-b1f7b6ee7d73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739056463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3739056463
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2253691709
Short name T53
Test name
Test status
Simulation time 140781908 ps
CPU time 3.56 seconds
Started Apr 16 12:46:54 PM PDT 24
Finished Apr 16 12:47:00 PM PDT 24
Peak memory 214872 kb
Host smart-5245d0d3-a7f2-43b6-a4b7-de4b7db4edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253691709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2253691709
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2077944538
Short name T849
Test name
Test status
Simulation time 32830795 ps
CPU time 1.27 seconds
Started Apr 16 12:46:31 PM PDT 24
Finished Apr 16 12:46:34 PM PDT 24
Peak memory 207408 kb
Host smart-ceddcb0a-6234-4f4f-add5-849d4b3af0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077944538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2077944538
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.916156908
Short name T354
Test name
Test status
Simulation time 92120749 ps
CPU time 4.03 seconds
Started Apr 16 12:46:28 PM PDT 24
Finished Apr 16 12:46:35 PM PDT 24
Peak memory 214604 kb
Host smart-0d94e6ca-c47d-4608-9b18-d1c1583c8eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916156908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.916156908
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1355509300
Short name T827
Test name
Test status
Simulation time 263024530 ps
CPU time 3.44 seconds
Started Apr 16 12:46:28 PM PDT 24
Finished Apr 16 12:46:33 PM PDT 24
Peak memory 209764 kb
Host smart-93b18dff-fef0-42bf-b465-8c0fd89e3141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355509300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1355509300
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.23199804
Short name T592
Test name
Test status
Simulation time 329923413 ps
CPU time 9.44 seconds
Started Apr 16 12:46:37 PM PDT 24
Finished Apr 16 12:46:49 PM PDT 24
Peak memory 218616 kb
Host smart-795cd73d-387f-4874-ae8c-b36de9f99024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23199804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.23199804
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2983969070
Short name T204
Test name
Test status
Simulation time 84103270 ps
CPU time 3.41 seconds
Started Apr 16 12:46:38 PM PDT 24
Finished Apr 16 12:46:43 PM PDT 24
Peak memory 207068 kb
Host smart-51b49ec5-9608-4ee9-8358-4bb46cdb75cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983969070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2983969070
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3062634536
Short name T761
Test name
Test status
Simulation time 62117938 ps
CPU time 2.87 seconds
Started Apr 16 12:46:32 PM PDT 24
Finished Apr 16 12:46:37 PM PDT 24
Peak memory 207552 kb
Host smart-6a5f555e-f276-4744-bab2-c302f808d469
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062634536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3062634536
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.615690207
Short name T404
Test name
Test status
Simulation time 965982262 ps
CPU time 10.6 seconds
Started Apr 16 12:46:37 PM PDT 24
Finished Apr 16 12:46:50 PM PDT 24
Peak memory 208240 kb
Host smart-9a30f615-b205-4d20-862a-36ded4e8bf47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615690207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.615690207
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2018783537
Short name T701
Test name
Test status
Simulation time 7144416824 ps
CPU time 47.32 seconds
Started Apr 16 12:46:35 PM PDT 24
Finished Apr 16 12:47:25 PM PDT 24
Peak memory 209180 kb
Host smart-cfc4d40b-e1f6-43b8-a460-37f5e2df3411
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018783537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2018783537
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2052049125
Short name T468
Test name
Test status
Simulation time 42875465 ps
CPU time 1.78 seconds
Started Apr 16 12:46:31 PM PDT 24
Finished Apr 16 12:46:35 PM PDT 24
Peak memory 214536 kb
Host smart-856c1f88-f387-4c61-b58e-1e2ce309e692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052049125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2052049125
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2227105596
Short name T375
Test name
Test status
Simulation time 568448093 ps
CPU time 3.56 seconds
Started Apr 16 12:46:39 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 207260 kb
Host smart-f077b8ab-b7d0-476e-bb93-acb81bcef1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227105596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2227105596
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2889635125
Short name T603
Test name
Test status
Simulation time 610835332 ps
CPU time 7.65 seconds
Started Apr 16 12:46:44 PM PDT 24
Finished Apr 16 12:46:53 PM PDT 24
Peak memory 221032 kb
Host smart-a36550ae-1f0b-49b2-a3f7-9182f9cf7c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889635125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2889635125
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3059640664
Short name T120
Test name
Test status
Simulation time 91271748 ps
CPU time 6.02 seconds
Started Apr 16 12:46:34 PM PDT 24
Finished Apr 16 12:46:43 PM PDT 24
Peak memory 221144 kb
Host smart-d9f7fd95-dc41-4ab9-a9bf-2bb4d1fef8ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059640664 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3059640664
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1823695076
Short name T387
Test name
Test status
Simulation time 82625658 ps
CPU time 3.85 seconds
Started Apr 16 12:46:38 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 209232 kb
Host smart-71c56d20-4d63-46ff-b751-579313d79df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823695076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1823695076
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2330917993
Short name T563
Test name
Test status
Simulation time 13597775 ps
CPU time 0.91 seconds
Started Apr 16 12:46:42 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 206392 kb
Host smart-1579d8a1-6560-4e44-8d35-fd9733a9bdf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330917993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2330917993
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.42982530
Short name T100
Test name
Test status
Simulation time 1715548926 ps
CPU time 6.95 seconds
Started Apr 16 12:46:56 PM PDT 24
Finished Apr 16 12:47:07 PM PDT 24
Peak memory 215560 kb
Host smart-d71fb566-6bef-455a-bc58-1d105041bb65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42982530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.42982530
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4257456954
Short name T51
Test name
Test status
Simulation time 427209205 ps
CPU time 3.84 seconds
Started Apr 16 12:46:48 PM PDT 24
Finished Apr 16 12:46:53 PM PDT 24
Peak memory 209092 kb
Host smart-e0e9a054-e164-4e49-a1f9-3f7878ab1fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257456954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4257456954
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2399015305
Short name T240
Test name
Test status
Simulation time 566903182 ps
CPU time 3.5 seconds
Started Apr 16 12:46:34 PM PDT 24
Finished Apr 16 12:46:40 PM PDT 24
Peak memory 210048 kb
Host smart-15773190-88fb-4afc-a71c-56081e6f7234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399015305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2399015305
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.410763146
Short name T355
Test name
Test status
Simulation time 151004984 ps
CPU time 5.25 seconds
Started Apr 16 12:46:41 PM PDT 24
Finished Apr 16 12:46:47 PM PDT 24
Peak memory 214544 kb
Host smart-5ace4bd3-93c6-4bf3-8ad2-e2d8dcaca35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410763146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.410763146
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3715401584
Short name T257
Test name
Test status
Simulation time 319874482 ps
CPU time 4.44 seconds
Started Apr 16 12:46:48 PM PDT 24
Finished Apr 16 12:46:54 PM PDT 24
Peak memory 210700 kb
Host smart-1c294048-a9ce-4e06-b6a0-9998eb6a6db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715401584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3715401584
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2557816656
Short name T5
Test name
Test status
Simulation time 9588478876 ps
CPU time 17.33 seconds
Started Apr 16 12:46:50 PM PDT 24
Finished Apr 16 12:47:08 PM PDT 24
Peak memory 209456 kb
Host smart-25a98f04-6e53-435e-8366-85f53e52824d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557816656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2557816656
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3223100503
Short name T288
Test name
Test status
Simulation time 95102976 ps
CPU time 4.26 seconds
Started Apr 16 12:46:40 PM PDT 24
Finished Apr 16 12:46:45 PM PDT 24
Peak memory 209068 kb
Host smart-ad1a27c4-112d-4ff6-8e7c-792bba0df352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223100503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3223100503
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.209580465
Short name T628
Test name
Test status
Simulation time 203199409 ps
CPU time 5.55 seconds
Started Apr 16 12:46:47 PM PDT 24
Finished Apr 16 12:46:54 PM PDT 24
Peak memory 208832 kb
Host smart-8a62573b-e2c1-4053-b7d4-a3112cb220de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209580465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.209580465
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3490660580
Short name T19
Test name
Test status
Simulation time 227555580 ps
CPU time 3.04 seconds
Started Apr 16 12:46:32 PM PDT 24
Finished Apr 16 12:46:38 PM PDT 24
Peak memory 208780 kb
Host smart-ddae8478-3f09-4c59-89bd-ad50462cc000
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490660580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3490660580
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.565046139
Short name T749
Test name
Test status
Simulation time 189586636 ps
CPU time 2.64 seconds
Started Apr 16 12:46:44 PM PDT 24
Finished Apr 16 12:46:48 PM PDT 24
Peak memory 207108 kb
Host smart-5cb45c45-53cf-4bb7-8b95-9cd6c1710310
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565046139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.565046139
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3359546023
Short name T759
Test name
Test status
Simulation time 220760931 ps
CPU time 4.77 seconds
Started Apr 16 12:46:38 PM PDT 24
Finished Apr 16 12:46:45 PM PDT 24
Peak memory 208604 kb
Host smart-cb47a77c-e59c-490b-acf6-239b25b84283
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359546023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3359546023
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.932442352
Short name T879
Test name
Test status
Simulation time 67664900 ps
CPU time 2.76 seconds
Started Apr 16 12:46:40 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 210276 kb
Host smart-125f2fd3-e2af-4b58-a3be-0d443cd05d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932442352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.932442352
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3580517757
Short name T783
Test name
Test status
Simulation time 702303216 ps
CPU time 15.12 seconds
Started Apr 16 12:46:34 PM PDT 24
Finished Apr 16 12:46:52 PM PDT 24
Peak memory 208192 kb
Host smart-d35585a8-b900-40ff-ad58-aaaca52d0fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580517757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3580517757
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.604839351
Short name T126
Test name
Test status
Simulation time 281249725 ps
CPU time 5.39 seconds
Started Apr 16 12:46:35 PM PDT 24
Finished Apr 16 12:46:43 PM PDT 24
Peak memory 209364 kb
Host smart-0d7388a7-52d7-4acb-82b8-d22f63649580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604839351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.604839351
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.451980799
Short name T797
Test name
Test status
Simulation time 228330761 ps
CPU time 2.9 seconds
Started Apr 16 12:46:47 PM PDT 24
Finished Apr 16 12:46:52 PM PDT 24
Peak memory 210720 kb
Host smart-ef5cf212-bdb2-44e9-afb3-2fb5dbc1d818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451980799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.451980799
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1761346375
Short name T818
Test name
Test status
Simulation time 19639947 ps
CPU time 0.89 seconds
Started Apr 16 12:46:31 PM PDT 24
Finished Apr 16 12:46:34 PM PDT 24
Peak memory 206260 kb
Host smart-2e19a2cd-7866-434c-a479-944389cb300f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761346375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1761346375
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3403982813
Short name T555
Test name
Test status
Simulation time 96318682 ps
CPU time 3.52 seconds
Started Apr 16 12:46:37 PM PDT 24
Finished Apr 16 12:46:43 PM PDT 24
Peak memory 216524 kb
Host smart-1fa3b898-39f1-473a-89a6-59ed5e7bf296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403982813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3403982813
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.456278651
Short name T679
Test name
Test status
Simulation time 139598629 ps
CPU time 3.09 seconds
Started Apr 16 12:46:42 PM PDT 24
Finished Apr 16 12:46:46 PM PDT 24
Peak memory 208304 kb
Host smart-66c35fb8-b4a3-4d11-a7ba-db19fa76ecee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456278651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.456278651
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.732084150
Short name T258
Test name
Test status
Simulation time 52264423 ps
CPU time 2.68 seconds
Started Apr 16 12:46:48 PM PDT 24
Finished Apr 16 12:46:52 PM PDT 24
Peak memory 210840 kb
Host smart-982cc6f4-4628-49d8-bec0-6d055f091ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732084150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.732084150
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.4065810004
Short name T615
Test name
Test status
Simulation time 122947751 ps
CPU time 2.38 seconds
Started Apr 16 12:46:24 PM PDT 24
Finished Apr 16 12:46:28 PM PDT 24
Peak memory 210116 kb
Host smart-4b9b1776-0894-487c-b505-d418361ebdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065810004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.4065810004
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2730868608
Short name T515
Test name
Test status
Simulation time 841929291 ps
CPU time 3.79 seconds
Started Apr 16 12:46:50 PM PDT 24
Finished Apr 16 12:47:02 PM PDT 24
Peak memory 214644 kb
Host smart-56c5aa7a-6d71-4b90-baef-1818c5d31b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730868608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2730868608
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.373460748
Short name T513
Test name
Test status
Simulation time 91137636 ps
CPU time 3.16 seconds
Started Apr 16 12:46:34 PM PDT 24
Finished Apr 16 12:46:40 PM PDT 24
Peak memory 207024 kb
Host smart-993b01b8-e939-469a-8565-b0643bfdb03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373460748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.373460748
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2296439867
Short name T568
Test name
Test status
Simulation time 139530708 ps
CPU time 5.32 seconds
Started Apr 16 12:46:44 PM PDT 24
Finished Apr 16 12:46:51 PM PDT 24
Peak memory 209328 kb
Host smart-db015d07-bc79-4669-aa65-7389b6de9346
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296439867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2296439867
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3213152597
Short name T599
Test name
Test status
Simulation time 61114809 ps
CPU time 3.06 seconds
Started Apr 16 12:46:45 PM PDT 24
Finished Apr 16 12:46:50 PM PDT 24
Peak memory 207212 kb
Host smart-e522e51a-41f6-4755-ba17-16760ffb7e6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213152597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3213152597
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2336239152
Short name T480
Test name
Test status
Simulation time 78857228 ps
CPU time 3.68 seconds
Started Apr 16 12:46:39 PM PDT 24
Finished Apr 16 12:46:44 PM PDT 24
Peak memory 208820 kb
Host smart-2c8e10d3-7bb5-40ac-bf0e-c3e1de5f5a77
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336239152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2336239152
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1586227085
Short name T750
Test name
Test status
Simulation time 358955068 ps
CPU time 2.08 seconds
Started Apr 16 12:46:50 PM PDT 24
Finished Apr 16 12:46:53 PM PDT 24
Peak memory 208456 kb
Host smart-41af385a-077d-41ba-889e-02235e50c969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586227085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1586227085
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1525444425
Short name T413
Test name
Test status
Simulation time 379187196 ps
CPU time 7.29 seconds
Started Apr 16 12:46:39 PM PDT 24
Finished Apr 16 12:46:48 PM PDT 24
Peak memory 207024 kb
Host smart-c1b04828-763f-454c-9445-7bb2ddd3e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525444425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1525444425
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1024102514
Short name T272
Test name
Test status
Simulation time 3670614761 ps
CPU time 15.6 seconds
Started Apr 16 12:46:38 PM PDT 24
Finished Apr 16 12:46:56 PM PDT 24
Peak memory 222532 kb
Host smart-44205201-69c8-4f90-a824-9b5209e4917e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024102514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1024102514
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3347631007
Short name T821
Test name
Test status
Simulation time 131485366 ps
CPU time 4.83 seconds
Started Apr 16 12:46:41 PM PDT 24
Finished Apr 16 12:46:47 PM PDT 24
Peak memory 209516 kb
Host smart-19620d95-5f3e-4faf-9c12-f68c20956183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347631007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3347631007
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1288101521
Short name T189
Test name
Test status
Simulation time 547060679 ps
CPU time 1.97 seconds
Started Apr 16 12:46:37 PM PDT 24
Finished Apr 16 12:46:41 PM PDT 24
Peak memory 209972 kb
Host smart-b0843303-f694-42a4-bd0b-15be30793fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288101521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1288101521
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2536572378
Short name T675
Test name
Test status
Simulation time 12568355 ps
CPU time 0.72 seconds
Started Apr 16 12:44:50 PM PDT 24
Finished Apr 16 12:44:52 PM PDT 24
Peak memory 206160 kb
Host smart-16f74e8b-ad0c-4e7d-97af-37731adfa9ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536572378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2536572378
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1039138124
Short name T378
Test name
Test status
Simulation time 3356097683 ps
CPU time 15.51 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:30 PM PDT 24
Peak memory 214676 kb
Host smart-3983306e-1923-461e-b6fb-194e77bce9aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039138124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1039138124
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2274352540
Short name T22
Test name
Test status
Simulation time 153090946 ps
CPU time 3.1 seconds
Started Apr 16 12:45:04 PM PDT 24
Finished Apr 16 12:45:10 PM PDT 24
Peak memory 210808 kb
Host smart-52219a4a-68dc-4269-a6b3-e1328531657c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274352540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2274352540
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1138024322
Short name T631
Test name
Test status
Simulation time 56249370 ps
CPU time 2.31 seconds
Started Apr 16 12:44:53 PM PDT 24
Finished Apr 16 12:44:56 PM PDT 24
Peak memory 207544 kb
Host smart-91a76d8e-2da0-42ed-852a-6c3597b70888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138024322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1138024322
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.364667134
Short name T88
Test name
Test status
Simulation time 483327871 ps
CPU time 5.8 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 214604 kb
Host smart-30686565-4d95-42b5-a479-61ca008bff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364667134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.364667134
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4080800469
Short name T283
Test name
Test status
Simulation time 194946290 ps
CPU time 6.68 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 214560 kb
Host smart-8f5969cc-f43f-4184-8772-6602b611aa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080800469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4080800469
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1794719813
Short name T220
Test name
Test status
Simulation time 49843273 ps
CPU time 2.64 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 214528 kb
Host smart-d7aeacbd-a2fc-4312-9390-9db8519d6884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794719813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1794719813
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2206848427
Short name T199
Test name
Test status
Simulation time 8217092134 ps
CPU time 84.67 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:46:35 PM PDT 24
Peak memory 209160 kb
Host smart-26413fe0-26d0-4662-a235-3778722af8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206848427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2206848427
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3663616287
Short name T591
Test name
Test status
Simulation time 220840391 ps
CPU time 3.41 seconds
Started Apr 16 12:45:00 PM PDT 24
Finished Apr 16 12:45:05 PM PDT 24
Peak memory 208872 kb
Host smart-c5eeed3f-8ee8-481f-9a19-c916e1d07f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663616287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3663616287
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2583997969
Short name T789
Test name
Test status
Simulation time 116748533 ps
CPU time 2.37 seconds
Started Apr 16 12:44:58 PM PDT 24
Finished Apr 16 12:45:03 PM PDT 24
Peak memory 207072 kb
Host smart-f2ccef85-3004-4539-8d2d-ce99dd5cc408
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583997969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2583997969
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1216692450
Short name T331
Test name
Test status
Simulation time 4503285810 ps
CPU time 58.05 seconds
Started Apr 16 12:45:00 PM PDT 24
Finished Apr 16 12:45:59 PM PDT 24
Peak memory 209312 kb
Host smart-266b2729-d7d6-4885-b9f2-14cf49f15583
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216692450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1216692450
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.184860657
Short name T611
Test name
Test status
Simulation time 460141862 ps
CPU time 4.32 seconds
Started Apr 16 12:45:05 PM PDT 24
Finished Apr 16 12:45:12 PM PDT 24
Peak memory 208936 kb
Host smart-be897c46-d616-4873-a276-29874f81c1d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184860657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.184860657
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2507450724
Short name T820
Test name
Test status
Simulation time 23287228 ps
CPU time 1.67 seconds
Started Apr 16 12:45:01 PM PDT 24
Finished Apr 16 12:45:05 PM PDT 24
Peak memory 210132 kb
Host smart-1c3d284e-e88f-436e-8db6-8974ecde3c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507450724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2507450724
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2804885891
Short name T506
Test name
Test status
Simulation time 134412591 ps
CPU time 3.01 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 208512 kb
Host smart-24ad2e0b-6213-4620-a7b1-245ab07e447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804885891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2804885891
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1736311578
Short name T40
Test name
Test status
Simulation time 2543992151 ps
CPU time 50.52 seconds
Started Apr 16 12:44:50 PM PDT 24
Finished Apr 16 12:45:42 PM PDT 24
Peak memory 216128 kb
Host smart-1978ce7e-cb45-4545-a566-bf6f124cc0ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736311578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1736311578
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2196138497
Short name T118
Test name
Test status
Simulation time 1340942249 ps
CPU time 20.04 seconds
Started Apr 16 12:45:02 PM PDT 24
Finished Apr 16 12:45:25 PM PDT 24
Peak memory 222888 kb
Host smart-c708d5f4-2c72-4fcb-9a36-804860b79acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196138497 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2196138497
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2800220319
Short name T648
Test name
Test status
Simulation time 95294337 ps
CPU time 4.61 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 207700 kb
Host smart-89dc25a8-3a57-466c-9d09-7e180174c7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800220319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2800220319
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3371613299
Short name T192
Test name
Test status
Simulation time 47882599 ps
CPU time 2.45 seconds
Started Apr 16 12:44:54 PM PDT 24
Finished Apr 16 12:44:57 PM PDT 24
Peak memory 210128 kb
Host smart-a2f7c22f-2bf6-40b4-a898-afd7825c7302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371613299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3371613299
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2029974177
Short name T439
Test name
Test status
Simulation time 11564782 ps
CPU time 0.77 seconds
Started Apr 16 12:44:57 PM PDT 24
Finished Apr 16 12:44:59 PM PDT 24
Peak memory 206260 kb
Host smart-b6c0e9e3-ea69-4074-ac1a-c16fd586295a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029974177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2029974177
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1947005849
Short name T395
Test name
Test status
Simulation time 251579013 ps
CPU time 6.15 seconds
Started Apr 16 12:44:59 PM PDT 24
Finished Apr 16 12:45:07 PM PDT 24
Peak memory 214464 kb
Host smart-a54cc968-4294-490b-846f-6848ad154197
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947005849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1947005849
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2294074739
Short name T228
Test name
Test status
Simulation time 1368241527 ps
CPU time 5.12 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 214496 kb
Host smart-58fc8416-3c11-4789-b16a-19917784953d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294074739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2294074739
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3578105158
Short name T365
Test name
Test status
Simulation time 109685500 ps
CPU time 4.43 seconds
Started Apr 16 12:45:01 PM PDT 24
Finished Apr 16 12:45:07 PM PDT 24
Peak memory 218360 kb
Host smart-ae38b4d6-8850-46ba-9bef-955feffc3ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578105158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3578105158
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3684590057
Short name T337
Test name
Test status
Simulation time 158558434 ps
CPU time 2.92 seconds
Started Apr 16 12:45:13 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 214612 kb
Host smart-f7b7c59a-5a7a-4df1-b6ad-1c098352bb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684590057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3684590057
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.934267975
Short name T498
Test name
Test status
Simulation time 283389441 ps
CPU time 8.17 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 210828 kb
Host smart-070ccd72-8c39-48ab-9bac-1106e2048755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934267975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.934267975
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1484523521
Short name T830
Test name
Test status
Simulation time 117137529 ps
CPU time 4.27 seconds
Started Apr 16 12:44:51 PM PDT 24
Finished Apr 16 12:44:56 PM PDT 24
Peak memory 214624 kb
Host smart-329ddf5a-3211-41ff-9246-67450eb47015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484523521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1484523521
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3101931712
Short name T772
Test name
Test status
Simulation time 137772846 ps
CPU time 2.68 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 208856 kb
Host smart-6cb808f0-c40c-4cea-b5ba-c56bfad94807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101931712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3101931712
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2847164827
Short name T602
Test name
Test status
Simulation time 66693266 ps
CPU time 3.37 seconds
Started Apr 16 12:45:04 PM PDT 24
Finished Apr 16 12:45:09 PM PDT 24
Peak memory 209180 kb
Host smart-05067d6a-cd72-4996-9911-220dd599c69f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847164827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2847164827
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2903942986
Short name T746
Test name
Test status
Simulation time 758555021 ps
CPU time 5.39 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 207112 kb
Host smart-349fd67d-7730-4c47-8aef-0b6bed25ba2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903942986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2903942986
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2584538027
Short name T491
Test name
Test status
Simulation time 20924207 ps
CPU time 1.81 seconds
Started Apr 16 12:45:00 PM PDT 24
Finished Apr 16 12:45:09 PM PDT 24
Peak memory 206884 kb
Host smart-e81b3e55-e1c4-4c29-8f6d-d1ce73d9f7a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584538027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2584538027
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3522100553
Short name T487
Test name
Test status
Simulation time 101518136 ps
CPU time 3.24 seconds
Started Apr 16 12:45:01 PM PDT 24
Finished Apr 16 12:45:07 PM PDT 24
Peak memory 209572 kb
Host smart-27699e34-0819-4208-a40d-6549081fe4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522100553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3522100553
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3064632166
Short name T424
Test name
Test status
Simulation time 341155467 ps
CPU time 5.22 seconds
Started Apr 16 12:45:05 PM PDT 24
Finished Apr 16 12:45:12 PM PDT 24
Peak memory 206976 kb
Host smart-756642df-613a-4797-b5d6-3aa8e0aff74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064632166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3064632166
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3384280236
Short name T238
Test name
Test status
Simulation time 1911567422 ps
CPU time 4.5 seconds
Started Apr 16 12:45:04 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 210280 kb
Host smart-9ee49c14-f58a-4bd1-bbfe-5c34f28d03ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384280236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3384280236
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3393110261
Short name T181
Test name
Test status
Simulation time 9001095747 ps
CPU time 36.63 seconds
Started Apr 16 12:45:18 PM PDT 24
Finished Apr 16 12:45:57 PM PDT 24
Peak memory 214624 kb
Host smart-275cc2e4-a22c-4228-b6e8-95e0da3c54e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393110261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3393110261
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3198432104
Short name T50
Test name
Test status
Simulation time 205819972 ps
CPU time 3.88 seconds
Started Apr 16 12:45:02 PM PDT 24
Finished Apr 16 12:45:08 PM PDT 24
Peak memory 210384 kb
Host smart-a0e45e2e-3e65-4dbe-8ea2-8f661ff95417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198432104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3198432104
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.566903152
Short name T477
Test name
Test status
Simulation time 38137671 ps
CPU time 0.88 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 206256 kb
Host smart-d89532cd-1d3b-490f-9cc4-9454ea3a445e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566903152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.566903152
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3657311019
Short name T398
Test name
Test status
Simulation time 88031989 ps
CPU time 3.63 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 214500 kb
Host smart-6fadae0c-26d5-4e09-b75b-1fa5f6ef855a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657311019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3657311019
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3935633304
Short name T9
Test name
Test status
Simulation time 275513116 ps
CPU time 3.11 seconds
Started Apr 16 12:45:03 PM PDT 24
Finished Apr 16 12:45:09 PM PDT 24
Peak memory 209032 kb
Host smart-98773772-ab32-4761-81a1-d9eca405a95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935633304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3935633304
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1199332931
Short name T558
Test name
Test status
Simulation time 1767878039 ps
CPU time 7.98 seconds
Started Apr 16 12:45:05 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 209280 kb
Host smart-8e2bd5bb-d6bf-4435-b28d-965e628fad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199332931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1199332931
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.443533686
Short name T25
Test name
Test status
Simulation time 207964553 ps
CPU time 7.27 seconds
Started Apr 16 12:45:01 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 220400 kb
Host smart-d34e8792-4b9f-44af-a3c4-2bd84b8d325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443533686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.443533686
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.233244442
Short name T242
Test name
Test status
Simulation time 2501257960 ps
CPU time 21.08 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 214608 kb
Host smart-a76a1cd8-052b-466a-a450-3ab848e3810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233244442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.233244442
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3359431228
Short name T567
Test name
Test status
Simulation time 67618451 ps
CPU time 3.51 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 208700 kb
Host smart-17fb31f0-5a04-46d8-9ee1-897c504709fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359431228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3359431228
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1355016014
Short name T253
Test name
Test status
Simulation time 765161182 ps
CPU time 6.9 seconds
Started Apr 16 12:45:02 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 209568 kb
Host smart-6ab6af51-15c2-49f1-8775-798b322c930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355016014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1355016014
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4124816029
Short name T509
Test name
Test status
Simulation time 262257920 ps
CPU time 3.23 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 207120 kb
Host smart-86422dcb-49bb-4b41-911e-785b9a06afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124816029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4124816029
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3430038412
Short name T811
Test name
Test status
Simulation time 383177186 ps
CPU time 9.63 seconds
Started Apr 16 12:45:02 PM PDT 24
Finished Apr 16 12:45:14 PM PDT 24
Peak memory 208800 kb
Host smart-d0cb4cfe-07d7-46f6-b750-9f4f2f592b30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430038412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3430038412
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2113710362
Short name T369
Test name
Test status
Simulation time 133080128 ps
CPU time 4.25 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 208632 kb
Host smart-60030deb-101d-4753-9f9b-9cbcc7bd0685
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113710362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2113710362
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.764663548
Short name T278
Test name
Test status
Simulation time 76664284 ps
CPU time 3.62 seconds
Started Apr 16 12:45:04 PM PDT 24
Finished Apr 16 12:45:10 PM PDT 24
Peak memory 208824 kb
Host smart-66df1db7-6ebd-4c92-9b92-80be10c7a51a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764663548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.764663548
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3103141219
Short name T828
Test name
Test status
Simulation time 4304323784 ps
CPU time 31.04 seconds
Started Apr 16 12:45:00 PM PDT 24
Finished Apr 16 12:45:33 PM PDT 24
Peak memory 218620 kb
Host smart-72ab616f-925c-4a75-9f9b-e01e744e45ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103141219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3103141219
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2089498097
Short name T542
Test name
Test status
Simulation time 4584348517 ps
CPU time 8.22 seconds
Started Apr 16 12:45:25 PM PDT 24
Finished Apr 16 12:45:35 PM PDT 24
Peak memory 208812 kb
Host smart-f7cb410d-6b0a-4f55-923c-813b3f5ecb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089498097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2089498097
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3264544941
Short name T771
Test name
Test status
Simulation time 16891489796 ps
CPU time 91.45 seconds
Started Apr 16 12:45:05 PM PDT 24
Finished Apr 16 12:46:39 PM PDT 24
Peak memory 222908 kb
Host smart-8c90e5bc-6f77-41f7-bb67-25daee5483ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264544941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3264544941
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3001377850
Short name T588
Test name
Test status
Simulation time 382765300 ps
CPU time 4.8 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 208236 kb
Host smart-c35482ab-4131-4529-8db6-7375d913f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001377850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3001377850
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1303809516
Short name T585
Test name
Test status
Simulation time 44244305 ps
CPU time 1.39 seconds
Started Apr 16 12:45:13 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 209660 kb
Host smart-ebbaa729-809d-4307-98aa-19c5d62ca22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303809516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1303809516
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2749231061
Short name T607
Test name
Test status
Simulation time 90942827 ps
CPU time 0.74 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:15 PM PDT 24
Peak memory 206252 kb
Host smart-f9ad50a4-d229-4b07-be4d-a082f8b331ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749231061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2749231061
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1436445435
Short name T27
Test name
Test status
Simulation time 68084127 ps
CPU time 3.59 seconds
Started Apr 16 12:45:22 PM PDT 24
Finished Apr 16 12:45:27 PM PDT 24
Peak memory 210500 kb
Host smart-e59667f7-cbd3-4341-ac75-e761e92c6a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436445435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1436445435
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4251734601
Short name T716
Test name
Test status
Simulation time 27798389 ps
CPU time 2.01 seconds
Started Apr 16 12:45:03 PM PDT 24
Finished Apr 16 12:45:08 PM PDT 24
Peak memory 210096 kb
Host smart-b3060bfd-4f3f-49da-8eeb-2448867b37e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251734601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4251734601
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3729211178
Short name T356
Test name
Test status
Simulation time 3006890474 ps
CPU time 10.45 seconds
Started Apr 16 12:45:02 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 219496 kb
Host smart-a227bc7c-4a15-4630-aece-54fba75c1859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729211178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3729211178
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2526114623
Short name T342
Test name
Test status
Simulation time 151183351 ps
CPU time 3.7 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 208024 kb
Host smart-82fa8e5e-da95-4817-a8e6-893c87c3ecfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526114623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2526114623
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2784221444
Short name T596
Test name
Test status
Simulation time 99294495 ps
CPU time 4.54 seconds
Started Apr 16 12:45:02 PM PDT 24
Finished Apr 16 12:45:09 PM PDT 24
Peak memory 210252 kb
Host smart-7f026c42-727b-49d6-ba21-581da85ddbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784221444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2784221444
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.830114441
Short name T801
Test name
Test status
Simulation time 40488653 ps
CPU time 2.52 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:16 PM PDT 24
Peak memory 208692 kb
Host smart-344c09d0-099a-4630-bf3d-dcd673b938af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830114441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.830114441
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1867987916
Short name T466
Test name
Test status
Simulation time 46307983 ps
CPU time 2.55 seconds
Started Apr 16 12:45:04 PM PDT 24
Finished Apr 16 12:45:09 PM PDT 24
Peak memory 208816 kb
Host smart-f09fbdaf-ca2e-4dec-ac5f-ec8549c62950
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867987916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1867987916
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1264884746
Short name T829
Test name
Test status
Simulation time 30579841 ps
CPU time 2.28 seconds
Started Apr 16 12:45:01 PM PDT 24
Finished Apr 16 12:45:05 PM PDT 24
Peak memory 209128 kb
Host smart-88f6ba91-775a-44a4-98ce-9834eec2cb39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264884746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1264884746
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.214376595
Short name T99
Test name
Test status
Simulation time 60759520 ps
CPU time 3.04 seconds
Started Apr 16 12:45:19 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 207180 kb
Host smart-0b8fc6fc-803d-4479-86d5-e9a5b64bc545
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214376595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.214376595
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2195003525
Short name T804
Test name
Test status
Simulation time 27064428 ps
CPU time 2.12 seconds
Started Apr 16 12:45:17 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 214612 kb
Host smart-9cc90a1b-7abc-4dd1-8180-5d2a02ac496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195003525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2195003525
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1492793452
Short name T571
Test name
Test status
Simulation time 47509441 ps
CPU time 2.51 seconds
Started Apr 16 12:44:58 PM PDT 24
Finished Apr 16 12:45:02 PM PDT 24
Peak memory 208080 kb
Host smart-bd74e1fe-81f2-40c4-b551-bd96738e50ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492793452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1492793452
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3895334870
Short name T634
Test name
Test status
Simulation time 427840515 ps
CPU time 14.37 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:23 PM PDT 24
Peak memory 222224 kb
Host smart-3432afbc-fa29-4323-83d5-3da2031c02c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895334870 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3895334870
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2880472644
Short name T841
Test name
Test status
Simulation time 190670028 ps
CPU time 5.14 seconds
Started Apr 16 12:45:14 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 208604 kb
Host smart-61296c9c-0098-4936-82fd-78582dd558fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880472644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2880472644
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1902155981
Short name T534
Test name
Test status
Simulation time 288230661 ps
CPU time 1.71 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 210388 kb
Host smart-647b57d8-337a-43d8-97db-d77b13e675ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902155981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1902155981
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.179060557
Short name T657
Test name
Test status
Simulation time 15822402 ps
CPU time 0.82 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:09 PM PDT 24
Peak memory 206280 kb
Host smart-3d64eacb-5256-4d2e-ba75-5995b020b420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179060557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.179060557
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2411449840
Short name T394
Test name
Test status
Simulation time 104298394 ps
CPU time 6.23 seconds
Started Apr 16 12:45:03 PM PDT 24
Finished Apr 16 12:45:12 PM PDT 24
Peak memory 215512 kb
Host smart-4371809d-a769-4901-8f2e-dce03c69f157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411449840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2411449840
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3575324305
Short name T214
Test name
Test status
Simulation time 123218973 ps
CPU time 2.71 seconds
Started Apr 16 12:45:06 PM PDT 24
Finished Apr 16 12:45:11 PM PDT 24
Peak memory 210104 kb
Host smart-5b3930e3-b5a7-45f5-b281-3d55c9d5a4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575324305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3575324305
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1165449650
Short name T273
Test name
Test status
Simulation time 118086107 ps
CPU time 4.26 seconds
Started Apr 16 12:45:10 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 207288 kb
Host smart-3ec389b8-99c2-46ac-8255-daafa1c75a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165449650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1165449650
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.781740139
Short name T286
Test name
Test status
Simulation time 295333547 ps
CPU time 4.95 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 208808 kb
Host smart-91c22d74-d783-4d9f-b404-c367cf0c1704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781740139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.781740139
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3837294172
Short name T82
Test name
Test status
Simulation time 473693206 ps
CPU time 7.19 seconds
Started Apr 16 12:45:11 PM PDT 24
Finished Apr 16 12:45:22 PM PDT 24
Peak memory 222716 kb
Host smart-5a6acbbf-1625-45a6-88c3-3d103929e792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837294172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3837294172
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.174239155
Short name T226
Test name
Test status
Simulation time 89248652 ps
CPU time 3.19 seconds
Started Apr 16 12:45:17 PM PDT 24
Finished Apr 16 12:45:23 PM PDT 24
Peak memory 220684 kb
Host smart-7e7ee890-9a4c-4334-be27-42339ee68809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174239155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.174239155
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2580002715
Short name T580
Test name
Test status
Simulation time 63456304 ps
CPU time 3.3 seconds
Started Apr 16 12:45:12 PM PDT 24
Finished Apr 16 12:45:19 PM PDT 24
Peak memory 210752 kb
Host smart-01c0986c-b1d2-4b90-a774-6a4fe9adde2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580002715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2580002715
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.374754021
Short name T236
Test name
Test status
Simulation time 750885858 ps
CPU time 6.27 seconds
Started Apr 16 12:45:14 PM PDT 24
Finished Apr 16 12:45:24 PM PDT 24
Peak memory 208244 kb
Host smart-1c325820-3200-42b1-9bc4-4d4c856363e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374754021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.374754021
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1725662848
Short name T572
Test name
Test status
Simulation time 427055771 ps
CPU time 9.12 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 208656 kb
Host smart-e44c1f02-3522-4cee-9627-7a4407d5e3f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725662848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1725662848
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1258346835
Short name T674
Test name
Test status
Simulation time 782273863 ps
CPU time 22.36 seconds
Started Apr 16 12:45:08 PM PDT 24
Finished Apr 16 12:45:34 PM PDT 24
Peak memory 208324 kb
Host smart-ef6bd87d-2879-407b-b8df-26c769f00791
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258346835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1258346835
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3806714879
Short name T760
Test name
Test status
Simulation time 279474988 ps
CPU time 10.06 seconds
Started Apr 16 12:45:07 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 208896 kb
Host smart-07dd9f74-a86c-41ab-91a6-31e705a3e7fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806714879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3806714879
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1137589376
Short name T785
Test name
Test status
Simulation time 374049622 ps
CPU time 6.99 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:20 PM PDT 24
Peak memory 209964 kb
Host smart-2e9edad5-d528-46df-b2f4-71aba6736155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137589376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1137589376
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2822565159
Short name T452
Test name
Test status
Simulation time 81763171 ps
CPU time 2.46 seconds
Started Apr 16 12:45:16 PM PDT 24
Finished Apr 16 12:45:21 PM PDT 24
Peak memory 206976 kb
Host smart-63c30b96-8d5c-4fc2-8b97-728fb815eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822565159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2822565159
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4181799223
Short name T658
Test name
Test status
Simulation time 524518906 ps
CPU time 4.87 seconds
Started Apr 16 12:45:09 PM PDT 24
Finished Apr 16 12:45:18 PM PDT 24
Peak memory 208816 kb
Host smart-7f7deb23-3b90-488d-9845-d06701fc647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181799223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4181799223
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3228627094
Short name T833
Test name
Test status
Simulation time 752438685 ps
CPU time 2.44 seconds
Started Apr 16 12:44:59 PM PDT 24
Finished Apr 16 12:45:03 PM PDT 24
Peak memory 210460 kb
Host smart-1a8ae80b-cdab-4a4e-9751-77389f08dc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228627094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3228627094
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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