Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4785

1

T2

8

T3

5

T4

5

auto[1]

570

1

T13

10

T15

4

T17

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4785

1

T2

8

T3

5

T4

5

auto[1]

570

1

T13

10

T15

4

T17

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4774

1

T2

8

T3

5

T4

5

auto[1]

581

1

T14

1

T26

7

T77

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4774

1

T2

8

T3

5

T4

5

auto[1]

581

1

T14

1

T26

7

T77

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	427	1			T3	1		T4	1		T13	4
auto[OpGenId]	1138	1			T2	3		T4	1		T13	2
auto[OpGenSwOut]	1150	1			T2	3		T3	2		T4	1
auto[OpGenHwOut]	2562	1			T2	2		T3	2		T4	2
auto[OpDisable]	78	1			T43	1		T39	2		T47	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	427	1			T3	1		T4	1		T13	4
auto[OpGenId]	1138	1			T2	3		T4	1		T13	2
auto[OpGenSwOut]	1150	1			T2	3		T3	2		T4	1
auto[OpGenHwOut]	2562	1			T2	2		T3	2		T4	2
auto[OpDisable]	78	1			T43	1		T39	2		T47	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4784

1

T2

7

T3

5

T4

5

auto[1]

571

1

T2

1

T26

7

T23

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4784

1

T2

7

T3

5

T4

5

auto[1]

571

1

T2

1

T26

7

T23

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5084

1

T2

8

T3

5

T4

5

auto[1]

271

1

T13

11

T117

11

T141

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1866	1			T2	2		T3	1		T4	1
auto[1]	703	1			T3	2		T14	1		T17	1
auto[2]	663	1			T2	2		T3	1		T4	1
auto[3]	673	1			T13	10		T14	1		T15	2
auto[4]	385	1			T2	1		T3	1		T4	1
auto[5]	328	1			T2	1		T4	1		T14	1
auto[6]	354	1			T2	1		T14	1		T15	2
auto[7]	383	1			T2	1		T4	1		T14	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1450	1			T2	4		T3	1		T4	3
clear_one[1]	703	1			T3	2		T14	1		T17	1
clear_one[2]	663	1			T2	2		T3	1		T4	1
clear_one[3]	673	1			T13	10		T14	1		T15	2
clear_none	1866	1			T2	2		T3	1		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	955	1			T2	2		T3	3		T4	1
auto[StInit]	737	1			T2	5		T3	1		T4	4
auto[StCreatorRootKey]	587	1			T3	1		T13	3		T14	1
auto[StOwnerIntKey]	504	1			T2	1		T13	2		T15	1
auto[StOwnerKey]	483	1			T13	2		T14	1		T15	1
auto[StDisabled]	1926	1			T13	6		T14	1		T15	4
auto[StInvalid]	163	1			T32	2		T33	2		T37	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	955	1			T2	2		T3	3		T4	1
auto[StInit]	737	1			T2	5		T3	1		T4	4
auto[StCreatorRootKey]	587	1			T3	1		T13	3		T14	1
auto[StOwnerIntKey]	504	1			T2	1		T13	2		T15	1
auto[StOwnerKey]	483	1			T13	2		T14	1		T15	1
auto[StDisabled]	1926	1			T13	6		T14	1		T15	4
auto[StInvalid]	163	1			T32	2		T33	2		T37	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpGenId]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[6]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	5	1			T13	1		T228	1		T260	1
auto[0]	auto[StReset]	auto[OpGenId]	165	1			T2	1		T4	1		T26	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	135	1			T3	1		T14	1		T26	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	257	1			T14	1		T15	1		T18	1
auto[0]	auto[StInit]	auto[OpAdvance]	36	1			T83	1		T79	1		T226	1
auto[0]	auto[StInit]	auto[OpGenId]	109	1			T2	1		T26	5		T24	2
auto[0]	auto[StInit]	auto[OpGenSwOut]	100	1			T26	1		T39	2		T233	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	182	1			T13	1		T38	1		T26	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	29	1			T39	1		T40	2		T74	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	57	1			T26	1		T39	1		T40	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	59	1			T16	1		T26	1		T39	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	71	1			T76	1		T234	1		T236	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	16	1			T13	1		T39	1		T40	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	32	1			T39	1		T74	1		T111	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T17	1		T40	1		T261	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	59	1			T26	1		T234	1		T262	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T97	1		T40	1		T263	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	24	1			T40	2		T194	1		T264	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	28	1			T13	2		T26	2		T39	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T15	1		T26	1		T39	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	35	1			T117	1		T141	1		T265	1
auto[0]	auto[StDisabled]	auto[OpGenId]	53	1			T39	2		T40	1		T74	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T26	1		T97	1		T40	3
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	186	1			T15	2		T18	1		T26	2
auto[0]	auto[StDisabled]	auto[OpDisable]	27	1			T47	1		T134	1		T194	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	9	1			T33	1		T37	1		T235	1
auto[0]	auto[StInvalid]	auto[OpGenId]	9	1			T224	1		T266	1		T267	2
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T25	1		T92	1		T80	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	19	1			T25	1		T80	1		T268	1
auto[1]	auto[StReset]	auto[OpGenId]	19	1			T81	1		T197	1		T127	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	20	1			T26	1		T23	1		T63	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	37	1			T3	1		T39	1		T60	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T3	1		T40	1		T79	1
auto[1]	auto[StInit]	auto[OpGenId]	13	1			T40	1		T269	2		T270	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	13	1			T129	1		T81	1		T271	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	29	1			T14	1		T24	1		T234	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T272	1		T273	1		T127	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T105	1		T274	1		T275	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	19	1			T232	1		T276	1		T107	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T18	1		T26	1		T231	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T97	1		T40	1		T276	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T220	1		T21	1		T194	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T82	1		T87	1		T277	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T76	1		T237	1		T5	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T39	1		T278	1		T279	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T228	1		T260	1		T196	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T38	1		T39	1		T263	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T280	1		T262	1		T71	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	22	1			T26	1		T96	1		T97	1
auto[1]	auto[StDisabled]	auto[OpGenId]	55	1			T17	1		T26	2		T136	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	64	1			T233	1		T61	1		T83	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	167	1			T18	3		T26	1		T76	1
auto[1]	auto[StDisabled]	auto[OpDisable]	6	1			T281	1		T7	1		T128	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T267	2		T282	1		T283	1
auto[1]	auto[StInvalid]	auto[OpGenId]	8	1			T224	1		T227	1		T284	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T32	1		T37	1		T227	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T224	1		T285	1		T286	1
auto[2]	auto[StReset]	auto[OpAdvance]	2	1			T276	1		T212	1		-	-
auto[2]	auto[StReset]	auto[OpGenId]	23	1			T34	1		T63	1		T133	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	24	1			T233	1		T287	1		T263	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	33	1			T288	2		T34	1		T73	2
auto[2]	auto[StInit]	auto[OpAdvance]	8	1			T263	1		T192	1		T289	1
auto[2]	auto[StInit]	auto[OpGenId]	8	1			T63	1		T290	1		T204	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	15	1			T2	1		T82	1		T79	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	24	1			T4	1		T291	1		T73	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T26	1		T292	1		T293	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T60	1		T233	1		T230	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T97	1		T194	1		T195	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T3	1		T23	1		T96	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T212	1		T190	1		T294	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T295	1		T290	1		T194	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T2	1		T40	1		T142	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T296	1		T297	1		T298	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T26	1		T107	1		T299	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	10	1			T40	1		T83	1		T215	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T109	1		T60	1		T287	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T77	1		T96	1		T231	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	25	1			T96	1		T265	1		T212	1
auto[2]	auto[StDisabled]	auto[OpGenId]	57	1			T220	1		T225	1		T40	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T40	1		T194	1		T212	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T26	1		T76	2		T77	2
auto[2]	auto[StDisabled]	auto[OpDisable]	6	1			T39	1		T194	1		T300	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T266	1		T301	1		T302	1
auto[2]	auto[StInvalid]	auto[OpGenId]	2	1			T37	1		T303	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T33	1		T37	1		T227	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T37	1		T304	1		T305	1
auto[3]	auto[StReset]	auto[OpGenId]	21	1			T26	1		T129	1		T5	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	16	1			T196	1		T28	1		T306	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	37	1			T15	1		T234	1		T33	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T23	1		T87	1		T145	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T23	1		T98	1		T307	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	16	1			T79	1		T290	1		T308	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	17	1			T269	1		T309	1		T263	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T196	1		T310	1		T306	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T13	1		T225	1		T196	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T14	1		T260	1		T65	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	49	1			T13	2		T15	1		T288	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T13	1		T197	1		T311	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T225	1		T129	1		T194	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T96	1		T39	1		T312	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	33	1			T77	1		T291	1		T231	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T313	1		T314	1		T315	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	25	1			T225	1		T105	1		T316	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T317	1		T102	1		T318	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	30	1			T17	1		T237	1		T233	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	23	1			T13	1		T39	1		T5	1
auto[3]	auto[StDisabled]	auto[OpGenId]	53	1			T13	1		T26	5		T312	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T13	3		T39	2		T313	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	153	1			T13	1		T26	1		T76	1
auto[3]	auto[StDisabled]	auto[OpDisable]	13	1			T39	1		T319	1		T196	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	1	1			T301	1		-	-		-	-
auto[3]	auto[StInvalid]	auto[OpGenId]	2	1			T320	1		T321	1		-	-
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T25	1		T322	2		T320	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T224	1		T268	1		T323	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T324	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T26	1		T40	1		T271	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T3	1		T40	1		T277	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	19	1			T291	1		T40	1		T297	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T269	1		T81	1		T325	1
auto[4]	auto[StInit]	auto[OpGenId]	12	1			T142	1		T308	1		T324	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T2	1		T4	1		T142	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	17	1			T77	1		T237	1		T307	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T82	1		T326	1		T327	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T328	1		T329	1		T70	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T263	1		T255	1		T192	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T280	1		T262	1		T330	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T293	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T331	1		T67	1		T293	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T332	1		T112	1		T277	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T287	1		T333	1		T334	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T335	1		T293	1		T252	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	10	1			T57	1		T67	1		T336	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T146	1		T337	1		T263	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T76	1		T298	1		T290	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	13	1			T40	1		T142	1		T194	1
auto[4]	auto[StDisabled]	auto[OpGenId]	35	1			T74	1		T5	1		T312	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T61	1		T40	1		T132	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	98	1			T15	1		T234	1		T288	2
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T129	1		T338	1		T69	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T286	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T224	1		T322	1		T339	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T301	1		T285	1		T340	1
auto[5]	auto[StReset]	auto[OpGenId]	9	1			T14	1		T80	1		T271	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	8	1			T39	1		T32	2		T57	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	15	1			T18	1		T337	1		T263	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T4	1		T341	1		T342	2
auto[5]	auto[StInit]	auto[OpGenId]	2	1			T327	1		T246	1		-	-
auto[5]	auto[StInit]	auto[OpGenSwOut]	4	1			T267	1		T343	1		T344	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	12	1			T2	1		T15	1		T64	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T74	1		T142	1		T345	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T287	1		T145	1		T346	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T35	1		T223	1		T347	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T194	1		T348	1		T349	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T238	1		T350	1		T182	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T41	1		T328	1		T271	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T67	1		T338	1		T351	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T38	1		T280	1		T71	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T87	1		T352	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	9	1			T40	1		T132	1		T67	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T195	1		T277	1		T353	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T18	1		T214	1		T354	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T194	1		T255	1		T70	1
auto[5]	auto[StDisabled]	auto[OpGenId]	25	1			T26	1		T194	1		T111	3
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T26	1		T313	1		T355	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T17	1		T77	1		T237	1
auto[5]	auto[StDisabled]	auto[OpDisable]	7	1			T5	1		T196	1		T255	1
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T268	1		T304	1		T356	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T357	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T235	1		T341	1		T358	1
auto[6]	auto[StReset]	auto[OpGenId]	13	1			T97	1		T203	1		T316	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T37	1		T40	1		T241	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	20	1			T15	1		T297	1		T194	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T146	1		T294	1		T359	1
auto[6]	auto[StInit]	auto[OpGenId]	8	1			T312	1		T81	1		T360	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	7	1			T133	1		T361	1		T362	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	15	1			T2	1		T18	1		T40	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T313	1		T44	1		T363	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T203	1		T146	4		T364	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T365	1		T146	1		T366	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T291	1		T206	1		T334	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T145	1		-	-		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T39	1		T255	1		T256	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T146	1		T241	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T15	1		T288	1		T40	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	3	1			T361	1		T367	1		T368	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T203	1		T369	1		T370	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T72	1		T73	1		T145	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	18	1			T14	1		T275	2		T196	1
auto[6]	auto[StDisabled]	auto[OpGenId]	26	1			T39	1		T5	1		T83	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	35	1			T17	1		T26	1		T40	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T26	1		T225	1		T73	2
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T338	1		T371	1		T372	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T373	1		T305	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T25	1		T374	1		T375	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T376	1		T377	1		T378	2
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T80	1		T301	1		-	-
auto[7]	auto[StReset]	auto[OpGenId]	12	1			T2	1		T26	1		T65	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	12	1			T276	1		T275	1		T145	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T26	1		T234	1		T233	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T141	1		T379	1		T329	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T263	1		T380	1		T381	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	13	1			T32	1		T97	1		T79	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	21	1			T4	1		T39	1		T288	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T39	1		T382	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T141	1		T316	1		T127	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T61	1		T383	1		T69	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T77	1		T237	1		T71	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T26	1		T317	1		T241	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T194	1		T384	1		T385	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T26	1		T112	1		T386	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T18	1		T73	1		T226	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T338	1		T387	1		T388	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	10	1			T74	1		T111	1		T389	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T39	1		T276	1		T30	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T14	1		T234	1		T39	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	19	1			T26	1		T141	1		T194	1
auto[7]	auto[StDisabled]	auto[OpGenId]	32	1			T26	2		T233	1		T40	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T263	1		T196	1		T338	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T15	1		T97	1		T291	1
auto[7]	auto[StDisabled]	auto[OpDisable]	7	1			T43	1		T40	1		T64	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T235	1		T301	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T32	1		T341	1		T282	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T92	1		T341	1		T285	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T92	1		T284	1		T301	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1450

1

T2

4

T3

1

T4

3

clear_one[1]

auto[0]

auto[0]

auto[0]

415

1

T3

2

T14

1

T17

1

clear_one[1]

auto[0]

auto[0]

auto[1]

118

1

T26

2

T234

1

T237

2

clear_one[1]

auto[0]

auto[1]

auto[0]

127

1

T26

2

T39

1

T232

1

clear_one[1]

auto[0]

auto[1]

auto[1]

43

1

T225

1

T61

1

T40

2

clear_one[2]

auto[0]

auto[0]

auto[0]

376

1

T2

1

T3

1

T4

1

clear_one[2]

auto[0]

auto[0]

auto[1]

115

1

T2

1

T23

1

T220

1

clear_one[2]

auto[1]

auto[0]

auto[0]

135

1

T76

2

T96

1

T39

1

clear_one[2]

auto[1]

auto[0]

auto[1]

37

1

T26

1

T96

1

T39

1

clear_one[3]

auto[0]

auto[0]

auto[0]

398

1

T13

3

T15

1

T26

2

clear_one[3]

auto[0]

auto[1]

auto[0]

113

1

T14

1

T26

1

T77

1

clear_one[3]

auto[1]

auto[0]

auto[0]

108

1

T13

7

T15

1

T17

1

clear_one[3]

auto[1]

auto[1]

auto[0]

54

1

T26

2

T39

2

T312

2

clear_none

auto[0]

auto[0]

auto[0]

1300

1

T2

2

T3

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

162

1

T26

2

T234

3

T237

1

clear_none

auto[0]

auto[1]

auto[0]

138

1

T26

1

T77

1

T43

1

clear_none

auto[0]

auto[1]

auto[1]

30

1

T40

2

T117

1

T143

1

clear_none

auto[1]

auto[0]

auto[0]

128

1

T13

3

T15

3

T18

1

clear_none

auto[1]

auto[0]

auto[1]

32

1

T26

1

T220

1

T40

1

clear_none

auto[1]

auto[1]

auto[0]

42

1

T39

2

T236

1

T55

1

clear_none

auto[1]

auto[1]

auto[1]

34

1

T26

1

T39

1

T40

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1367	1			T2	4		T3	1		T4	3
clear_all	auto[1]	83	1			T141	3		T142	7		T276	2
clear_one[1]	auto[0]	667	1			T3	2		T14	1		T17	1
clear_one[1]	auto[1]	36	1			T228	6		T142	2		T260	3
clear_one[2]	auto[0]	627	1			T2	2		T3	1		T4	1
clear_one[2]	auto[1]	36	1			T276	2		T107	1		T313	1
clear_one[3]	auto[0]	632	1			T13	2		T14	1		T15	2
clear_one[3]	auto[1]	41	1			T13	8		T260	2		T313	1
clear_none	auto[0]	1791	1			T2	2		T3	1		T4	1
clear_none	auto[1]	75	1			T13	3		T117	11		T141	1