Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11759

1

T1

4

T2

18

T3

17

auto[Attestation]

8620

1

T1

5

T2

11

T3

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3076	1			T1	2		T2	3		T3	2
auto[Aes]	3602	1			T1	1		T2	7		T3	3
auto[Kmac]	3561	1			T1	2		T2	3		T3	6
auto[Otbn]	3673	1			T2	5		T3	3		T4	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8239	1			T1	4		T2	8		T3	3
auto[OpGenId]	6467	1			T1	4		T2	11		T3	5
auto[OpGenSwOut]	6464	1			T1	4		T2	7		T3	4
auto[OpGenHwOut]	7448	1			T1	1		T2	11		T3	10
auto[OpDisable]	144	1			T26	2		T43	1		T39	4

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10928

1

T1

10

T2

8

T3

8

auto[OpDoneFail]

17834

1

T1

3

T2

29

T3

14

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6370	1			T1	2		T2	9		T3	15
auto[StInit]	4374	1			T1	3		T2	22		T3	1
auto[StCreatorRootKey]	3323	1			T1	2		T2	2		T3	3
auto[StOwnerIntKey]	2832	1			T1	3		T2	4		T3	3
auto[StOwnerKey]	2551	1			T1	3		T13	6		T14	2
auto[StDisabled]	8249	1			T13	10		T14	16		T15	7
auto[StInvalid]	1063	1			T32	24		T33	31		T37	22

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	325	1			T2	1		T14	3		T26	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	110	1			T4	1		T26	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	93	1			T26	1		T23	1		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	68	1			T26	2		T43	1		T39	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	72	1			T1	1		T13	1		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	227	1			T26	2		T39	1		T220	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	27	1			T33	3		T25	1		T92	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	325	1			T2	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T17	1		T24	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T26	2		T109	1		T39	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	76	1			T2	2		T26	2		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	63	1			T26	4		T39	2		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	224	1			T14	1		T75	1		T26	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	42	1			T33	1		T37	1		T92	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	310	1			T3	2		T14	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	114	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T16	1		T26	3		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T1	1		T26	1		T221	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	38	1			T26	2		T222	1		T223	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	234	1			T13	1		T17	1		T26	6
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	27	1			T33	1		T25	1		T92	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	319	1			T3	1		T4	1		T26	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	156	1			T17	1		T23	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T26	1		T97	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T17	1		T26	2		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	66	1			T26	1		T109	2		T39	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	223	1			T17	1		T26	2		T96	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	30	1			T32	3		T33	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	82	1			T26	2		T40	4		T74	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	128	1			T4	1		T16	1		T26	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	85	1			T14	1		T17	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	82	1			T26	1		T23	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	79	1			T13	1		T39	2		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	233	1			T13	1		T17	2		T38	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	44	1			T25	1		T224	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	70	1			T26	2		T39	1		T40	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	128	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	86	1			T39	2		T58	1		T40	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	74	1			T39	2		T225	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T17	1		T26	2		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	247	1			T13	1		T14	3		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	29	1			T32	4		T37	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	84	1			T26	5		T39	4		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	138	1			T2	1		T26	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T16	1		T39	2		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	59	1			T17	1		T26	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	65	1			T38	1		T26	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	225	1			T26	6		T39	3		T225	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	35	1			T32	2		T80	2		T227	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	70	1			T26	4		T39	1		T32	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	105	1			T4	1		T26	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	70	1			T23	1		T109	1		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	82	1			T16	1		T23	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	56	1			T13	1		T26	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	224	1			T75	1		T26	6		T221	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	34	1			T33	2		T37	2		T92	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	269	1			T14	2		T27	3		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	120	1			T38	1		T26	1		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T3	2		T39	2		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T96	1		T39	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T133	1		T228	1		T229	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	213	1			T14	1		T17	2		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	28	1			T32	1		T33	1		T224	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	403	1			T3	1		T14	1		T15	8
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	135	1			T2	2		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	126	1			T18	1		T26	3		T230	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	95	1			T3	1		T15	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	77	1			T76	1		T39	2		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	300	1			T13	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	28	1			T33	1		T92	1		T224	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	394	1			T2	1		T3	3		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	139	1			T4	1		T26	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	117	1			T26	3		T109	1		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T26	3		T58	1		T232	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	92	1			T23	1		T77	1		T233	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	271	1			T26	5		T77	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	42	1			T32	2		T33	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	459	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	123	1			T2	1		T4	2		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T26	1		T23	1		T234	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	103	1			T14	1		T38	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	99	1			T23	1		T109	2		T234	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	327	1			T13	1		T14	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	28	1			T32	1		T37	1		T235	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	82	1			T39	2		T40	4		T74	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T2	1		T4	1		T26	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T23	1		T60	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	54	1			T1	1		T2	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	62	1			T13	2		T26	2		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	189	1			T38	1		T26	1		T96	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	25	1			T33	1		T92	1		T224	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	76	1			T26	3		T39	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	125	1			T2	1		T4	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	110	1			T13	1		T15	1		T26	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	98	1			T18	1		T38	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	78	1			T15	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	269	1			T15	3		T17	3		T18	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	38	1			T32	1		T33	3		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	66	1			T26	1		T39	3		T40	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	147	1			T26	1		T32	1		T232	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T14	1		T26	1		T236	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T3	1		T26	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	87	1			T14	1		T26	1		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	296	1			T38	1		T26	4		T77	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	37	1			T33	1		T25	2		T92	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T26	3		T39	4		T40	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	137	1			T2	2		T26	2		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	117	1			T2	1		T237	1		T236	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	111	1			T3	1		T26	1		T237	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	85	1			T26	1		T96	1		T237	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	298	1			T26	6		T234	2		T39	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T33	1		T37	2		T25	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	211	1			T1	1		T13	1		T26	5
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	711	1			T2	1		T4	1		T14	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	228	1			T2	2		T26	6		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	719	1			T2	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	183	1			T1	1		T16	1		T26	6
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	704	1			T1	1		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T17	1		T26	3		T109	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	745	1			T3	1		T4	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	227	1			T13	1		T14	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	506	1			T4	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	210	1			T17	1		T26	2		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	487	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	195	1			T16	1		T17	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	491	1			T2	1		T26	12		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	198	1			T13	1		T16	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	443	1			T4	1		T75	1		T26	11
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	178	1			T3	2		T96	1		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	649	1			T14	3		T17	2		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	282	1			T3	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	882	1			T2	2		T3	1		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	282	1			T26	6		T23	1		T109	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	864	1			T2	1		T3	3		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	285	1			T14	1		T38	1		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	953	1			T2	2		T3	1		T4	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	184	1			T1	1		T2	1		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	410	1			T2	1		T4	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	274	1			T13	1		T15	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	520	1			T2	1		T4	1		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T3	1		T14	2		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	565	1			T38	1		T26	8		T77	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	295	1			T2	1		T3	1		T26	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	548	1			T2	2		T26	11		T23	1