Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33003

1

T1

15

T2

41

T3

23

auto[1]

273

1

T13

2

T96

2

T117

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33013	1			T1	15		T2	41		T3	23
auto[134217728:268435455]	10	1			T212	1		T411	2		T352	1
auto[268435456:402653183]	10	1			T228	1		T144	2		T346	1
auto[402653184:536870911]	12	1			T276	1		T212	1		T144	1
auto[536870912:671088639]	6	1			T412	2		T346	3		T413	1
auto[671088640:805306367]	8	1			T96	1		T141	1		T228	1
auto[805306368:939524095]	13	1			T142	2		T313	1		T346	1
auto[939524096:1073741823]	11	1			T318	1		T412	2		T346	1
auto[1073741824:1207959551]	8	1			T313	1		T212	1		T412	1
auto[1207959552:1342177279]	10	1			T313	1		T144	2		T335	1
auto[1342177280:1476395007]	11	1			T13	1		T260	1		T143	1
auto[1476395008:1610612735]	9	1			T96	1		T313	1		T411	1
auto[1610612736:1744830463]	8	1			T276	1		T212	1		T146	1
auto[1744830464:1879048191]	5	1			T318	1		T346	2		T315	1
auto[1879048192:2013265919]	4	1			T117	1		T276	1		T352	1
auto[2013265920:2147483647]	5	1			T367	1		T414	2		T415	1
auto[2147483648:2281701375]	6	1			T13	1		T142	1		T411	1
auto[2281701376:2415919103]	5	1			T276	1		T212	1		T352	1
auto[2415919104:2550136831]	8	1			T144	1		T412	1		T346	2
auto[2550136832:2684354559]	5	1			T144	1		T412	1		T315	1
auto[2684354560:2818572287]	13	1			T142	2		T276	1		T313	1
auto[2818572288:2952790015]	11	1			T313	1		T145	2		T146	1
auto[2952790016:3087007743]	6	1			T142	1		T279	1		T388	1
auto[3087007744:3221225471]	12	1			T117	1		T313	1		T318	1
auto[3221225472:3355443199]	6	1			T142	1		T146	1		T324	1
auto[3355443200:3489660927]	7	1			T260	1		T313	1		T318	1
auto[3489660928:3623878655]	8	1			T412	1		T346	1		T314	1
auto[3623878656:3758096383]	9	1			T142	2		T313	1		T143	1
auto[3758096384:3892314111]	6	1			T142	1		T146	1		T352	1
auto[3892314112:4026531839]	11	1			T117	2		T228	1		T276	1
auto[4026531840:4160749567]	11	1			T142	1		T260	1		T212	1
auto[4160749568:4294967295]	9	1			T117	1		T144	1		T412	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33003	1			T1	15		T2	41		T3	23
auto[0:134217727]	auto[1]	10	1			T228	1		T212	1		T272	1
auto[134217728:268435455]	auto[1]	10	1			T212	1		T411	2		T352	1
auto[268435456:402653183]	auto[1]	10	1			T228	1		T144	2		T346	1
auto[402653184:536870911]	auto[1]	12	1			T276	1		T212	1		T144	1
auto[536870912:671088639]	auto[1]	6	1			T412	2		T346	3		T413	1
auto[671088640:805306367]	auto[1]	8	1			T96	1		T141	1		T228	1
auto[805306368:939524095]	auto[1]	13	1			T142	2		T313	1		T346	1
auto[939524096:1073741823]	auto[1]	11	1			T318	1		T412	2		T346	1
auto[1073741824:1207959551]	auto[1]	8	1			T313	1		T212	1		T412	1
auto[1207959552:1342177279]	auto[1]	10	1			T313	1		T144	2		T335	1
auto[1342177280:1476395007]	auto[1]	11	1			T13	1		T260	1		T143	1
auto[1476395008:1610612735]	auto[1]	9	1			T96	1		T313	1		T411	1
auto[1610612736:1744830463]	auto[1]	8	1			T276	1		T212	1		T146	1
auto[1744830464:1879048191]	auto[1]	5	1			T318	1		T346	2		T315	1
auto[1879048192:2013265919]	auto[1]	4	1			T117	1		T276	1		T352	1
auto[2013265920:2147483647]	auto[1]	5	1			T367	1		T414	2		T415	1
auto[2147483648:2281701375]	auto[1]	6	1			T13	1		T142	1		T411	1
auto[2281701376:2415919103]	auto[1]	5	1			T276	1		T212	1		T352	1
auto[2415919104:2550136831]	auto[1]	8	1			T144	1		T412	1		T346	2
auto[2550136832:2684354559]	auto[1]	5	1			T144	1		T412	1		T315	1
auto[2684354560:2818572287]	auto[1]	13	1			T142	2		T276	1		T313	1
auto[2818572288:2952790015]	auto[1]	11	1			T313	1		T145	2		T146	1
auto[2952790016:3087007743]	auto[1]	6	1			T142	1		T279	1		T388	1
auto[3087007744:3221225471]	auto[1]	12	1			T117	1		T313	1		T318	1
auto[3221225472:3355443199]	auto[1]	6	1			T142	1		T146	1		T324	1
auto[3355443200:3489660927]	auto[1]	7	1			T260	1		T313	1		T318	1
auto[3489660928:3623878655]	auto[1]	8	1			T412	1		T346	1		T314	1
auto[3623878656:3758096383]	auto[1]	9	1			T142	2		T313	1		T143	1
auto[3758096384:3892314111]	auto[1]	6	1			T142	1		T146	1		T352	1
auto[3892314112:4026531839]	auto[1]	11	1			T117	2		T228	1		T276	1
auto[4026531840:4160749567]	auto[1]	11	1			T142	1		T260	1		T212	1
auto[4160749568:4294967295]	auto[1]	9	1			T117	1		T144	1		T412	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1580

1

T2

4

T3

2

T13

2

auto[1]

1821

1

T2

2

T3

2

T4

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T43	1		T39	1		T220	1
auto[134217728:268435455]	96	1			T26	2		T96	1		T39	2
auto[268435456:402653183]	101	1			T26	5		T39	1		T47	1
auto[402653184:536870911]	99	1			T26	1		T24	1		T225	1
auto[536870912:671088639]	99	1			T26	1		T39	3		T32	1
auto[671088640:805306367]	106	1			T2	1		T26	1		T39	1
auto[805306368:939524095]	97	1			T43	1		T39	1		T220	1
auto[939524096:1073741823]	88	1			T23	1		T39	3		T92	1
auto[1073741824:1207959551]	115	1			T3	1		T26	2		T24	1
auto[1207959552:1342177279]	103	1			T13	1		T38	1		T26	2
auto[1342177280:1476395007]	87	1			T2	1		T14	1		T26	1
auto[1476395008:1610612735]	115	1			T13	1		T38	1		T26	2
auto[1610612736:1744830463]	122	1			T4	1		T17	1		T26	2
auto[1744830464:1879048191]	93	1			T2	1		T23	1		T39	4
auto[1879048192:2013265919]	108	1			T16	1		T17	1		T26	1
auto[2013265920:2147483647]	110	1			T4	1		T26	1		T39	3
auto[2147483648:2281701375]	119	1			T2	1		T17	2		T38	1
auto[2281701376:2415919103]	112	1			T14	1		T23	1		T27	1
auto[2415919104:2550136831]	106	1			T3	1		T17	1		T26	1
auto[2550136832:2684354559]	122	1			T2	1		T26	1		T109	1
auto[2684354560:2818572287]	127	1			T4	1		T39	3		T49	1
auto[2818572288:2952790015]	116	1			T16	1		T23	1		T96	1
auto[2952790016:3087007743]	96	1			T3	1		T26	2		T39	1
auto[3087007744:3221225471]	106	1			T16	1		T26	2		T33	2
auto[3221225472:3355443199]	122	1			T13	1		T26	2		T39	1
auto[3355443200:3489660927]	89	1			T26	5		T48	1		T49	1
auto[3489660928:3623878655]	95	1			T2	1		T26	1		T109	1
auto[3623878656:3758096383]	105	1			T13	1		T26	3		T109	1
auto[3758096384:3892314111]	87	1			T3	1		T39	1		T220	1
auto[3892314112:4026531839]	119	1			T14	1		T38	2		T26	2
auto[4026531840:4160749567]	109	1			T26	1		T109	1		T58	1
auto[4160749568:4294967295]	118	1			T14	1		T39	2		T58	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T43	1		T39	1		T220	1
auto[0:134217727]	auto[1]	65	1			T40	1		T312	1		T80	1
auto[134217728:268435455]	auto[0]	54	1			T26	1		T96	1		T39	1
auto[134217728:268435455]	auto[1]	42	1			T26	1		T39	1		T80	1
auto[268435456:402653183]	auto[0]	43	1			T26	1		T39	1		T48	1
auto[268435456:402653183]	auto[1]	58	1			T26	4		T47	1		T40	1
auto[402653184:536870911]	auto[0]	52	1			T26	1		T24	1		T225	1
auto[402653184:536870911]	auto[1]	47	1			T22	1		T204	1		T313	2
auto[536870912:671088639]	auto[0]	38	1			T290	1		T274	1		T334	1
auto[536870912:671088639]	auto[1]	61	1			T26	1		T39	3		T32	1
auto[671088640:805306367]	auto[0]	53	1			T2	1		T26	1		T40	2
auto[671088640:805306367]	auto[1]	53	1			T39	1		T228	2		T312	1
auto[805306368:939524095]	auto[0]	41	1			T220	1		T40	2		T74	1
auto[805306368:939524095]	auto[1]	56	1			T43	1		T39	1		T40	1
auto[939524096:1073741823]	auto[0]	45	1			T23	1		T39	3		T92	1
auto[939524096:1073741823]	auto[1]	43	1			T132	1		T134	1		T141	2
auto[1073741824:1207959551]	auto[0]	43	1			T26	1		T39	1		T32	1
auto[1073741824:1207959551]	auto[1]	72	1			T3	1		T26	1		T24	1
auto[1207959552:1342177279]	auto[0]	51	1			T13	1		T38	1		T26	1
auto[1207959552:1342177279]	auto[1]	52	1			T26	1		T97	1		T41	1
auto[1342177280:1476395007]	auto[0]	41	1			T2	1		T26	1		T23	1
auto[1342177280:1476395007]	auto[1]	46	1			T14	1		T24	1		T39	4
auto[1476395008:1610612735]	auto[0]	59	1			T38	1		T23	1		T39	3
auto[1476395008:1610612735]	auto[1]	56	1			T13	1		T26	2		T60	1
auto[1610612736:1744830463]	auto[0]	58	1			T17	1		T26	1		T97	1
auto[1610612736:1744830463]	auto[1]	64	1			T4	1		T26	1		T39	3
auto[1744830464:1879048191]	auto[0]	47	1			T2	1		T23	1		T39	2
auto[1744830464:1879048191]	auto[1]	46	1			T39	2		T33	1		T117	1
auto[1879048192:2013265919]	auto[0]	51	1			T16	1		T17	1		T47	1
auto[1879048192:2013265919]	auto[1]	57	1			T26	1		T37	1		T82	1
auto[2013265920:2147483647]	auto[0]	45	1			T39	1		T74	1		T41	1
auto[2013265920:2147483647]	auto[1]	65	1			T4	1		T26	1		T39	2
auto[2147483648:2281701375]	auto[0]	56	1			T17	1		T38	1		T26	1
auto[2147483648:2281701375]	auto[1]	63	1			T2	1		T17	1		T26	2
auto[2281701376:2415919103]	auto[0]	48	1			T23	1		T39	2		T41	1
auto[2281701376:2415919103]	auto[1]	64	1			T14	1		T27	1		T39	1
auto[2415919104:2550136831]	auto[0]	55	1			T3	1		T17	1		T26	1
auto[2415919104:2550136831]	auto[1]	51	1			T23	1		T312	1		T226	1
auto[2550136832:2684354559]	auto[0]	54	1			T39	1		T49	1		T32	1
auto[2550136832:2684354559]	auto[1]	68	1			T2	1		T26	1		T109	1
auto[2684354560:2818572287]	auto[0]	54	1			T39	2		T49	1		T32	1
auto[2684354560:2818572287]	auto[1]	73	1			T4	1		T39	1		T32	1
auto[2818572288:2952790015]	auto[0]	55	1			T96	1		T43	1		T5	1
auto[2818572288:2952790015]	auto[1]	61	1			T16	1		T23	1		T37	1
auto[2952790016:3087007743]	auto[0]	52	1			T26	2		T39	1		T225	1
auto[2952790016:3087007743]	auto[1]	44	1			T3	1		T98	1		T8	1
auto[3087007744:3221225471]	auto[0]	56	1			T16	1		T26	1		T33	1
auto[3087007744:3221225471]	auto[1]	50	1			T26	1		T33	1		T92	1
auto[3221225472:3355443199]	auto[0]	57	1			T40	2		T129	1		T79	1
auto[3221225472:3355443199]	auto[1]	65	1			T13	1		T26	2		T39	1
auto[3355443200:3489660927]	auto[0]	43	1			T26	2		T74	1		T92	1
auto[3355443200:3489660927]	auto[1]	46	1			T26	3		T48	1		T49	1
auto[3489660928:3623878655]	auto[0]	43	1			T2	1		T109	1		T39	2
auto[3489660928:3623878655]	auto[1]	52	1			T26	1		T39	1		T32	1
auto[3623878656:3758096383]	auto[0]	53	1			T13	1		T26	3		T109	1
auto[3623878656:3758096383]	auto[1]	52	1			T39	1		T74	1		T290	1
auto[3758096384:3892314111]	auto[0]	33	1			T3	1		T49	1		T97	1
auto[3758096384:3892314111]	auto[1]	54	1			T39	1		T220	1		T134	1
auto[3892314112:4026531839]	auto[0]	48	1			T38	1		T26	2		T23	1
auto[3892314112:4026531839]	auto[1]	71	1			T14	1		T38	1		T24	1
auto[4026531840:4160749567]	auto[0]	47	1			T109	1		T34	1		T74	1
auto[4026531840:4160749567]	auto[1]	62	1			T26	1		T58	1		T5	1
auto[4160749568:4294967295]	auto[0]	56	1			T39	1		T60	1		T129	1
auto[4160749568:4294967295]	auto[1]	62	1			T14	1		T39	1		T58	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1561

1

T2

4

T3

2

T13

2

auto[1]

1839

1

T2

2

T3

2

T4

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T17	1		T26	3		T39	1
auto[134217728:268435455]	95	1			T26	2		T23	2		T39	1
auto[268435456:402653183]	112	1			T26	1		T39	1		T47	1
auto[402653184:536870911]	107	1			T4	1		T23	1		T96	1
auto[536870912:671088639]	100	1			T17	1		T26	1		T39	2
auto[671088640:805306367]	112	1			T4	1		T14	2		T17	1
auto[805306368:939524095]	88	1			T2	1		T13	1		T39	1
auto[939524096:1073741823]	115	1			T2	1		T26	1		T39	2
auto[1073741824:1207959551]	105	1			T14	1		T26	1		T27	1
auto[1207959552:1342177279]	115	1			T23	1		T39	1		T40	1
auto[1342177280:1476395007]	119	1			T2	1		T26	2		T39	3
auto[1476395008:1610612735]	105	1			T3	1		T26	1		T24	1
auto[1610612736:1744830463]	107	1			T26	1		T27	1		T39	3
auto[1744830464:1879048191]	117	1			T38	1		T26	4		T23	1
auto[1879048192:2013265919]	99	1			T17	1		T38	1		T26	1
auto[2013265920:2147483647]	109	1			T26	4		T23	1		T48	1
auto[2147483648:2281701375]	92	1			T23	1		T109	1		T96	1
auto[2281701376:2415919103]	113	1			T26	1		T23	1		T109	1
auto[2415919104:2550136831]	123	1			T2	1		T38	1		T26	2
auto[2550136832:2684354559]	101	1			T16	1		T26	2		T39	2
auto[2684354560:2818572287]	104	1			T3	1		T26	2		T39	2
auto[2818572288:2952790015]	105	1			T39	2		T40	1		T74	1
auto[2952790016:3087007743]	111	1			T14	1		T26	1		T39	3
auto[3087007744:3221225471]	99	1			T60	1		T97	1		T40	1
auto[3221225472:3355443199]	122	1			T26	5		T39	5		T32	1
auto[3355443200:3489660927]	72	1			T13	1		T26	1		T109	1
auto[3489660928:3623878655]	126	1			T13	1		T16	2		T26	1
auto[3623878656:3758096383]	95	1			T3	1		T26	1		T109	1
auto[3758096384:3892314111]	113	1			T26	1		T24	1		T39	1
auto[3892314112:4026531839]	98	1			T2	1		T17	1		T26	1
auto[4026531840:4160749567]	103	1			T4	1		T38	1		T26	3
auto[4160749568:4294967295]	108	1			T2	1		T3	1		T13	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T17	1		T26	3		T39	1
auto[0:134217727]	auto[1]	56	1			T97	1		T33	1		T40	2
auto[134217728:268435455]	auto[0]	41	1			T39	1		T74	1		T5	1
auto[134217728:268435455]	auto[1]	54	1			T26	2		T23	2		T33	1
auto[268435456:402653183]	auto[0]	52	1			T26	1		T47	1		T32	1
auto[268435456:402653183]	auto[1]	60	1			T39	1		T32	1		T40	1
auto[402653184:536870911]	auto[0]	54	1			T96	1		T39	1		T74	1
auto[402653184:536870911]	auto[1]	53	1			T4	1		T23	1		T39	1
auto[536870912:671088639]	auto[0]	41	1			T39	1		T40	1		T41	1
auto[536870912:671088639]	auto[1]	59	1			T17	1		T26	1		T39	1
auto[671088640:805306367]	auto[0]	53	1			T17	1		T38	1		T43	1
auto[671088640:805306367]	auto[1]	59	1			T4	1		T14	2		T39	1
auto[805306368:939524095]	auto[0]	46	1			T2	1		T13	1		T39	1
auto[805306368:939524095]	auto[1]	42	1			T32	1		T37	1		T40	2
auto[939524096:1073741823]	auto[0]	49	1			T2	1		T39	1		T48	1
auto[939524096:1073741823]	auto[1]	66	1			T26	1		T39	1		T32	1
auto[1073741824:1207959551]	auto[0]	47	1			T24	1		T96	1		T39	1
auto[1073741824:1207959551]	auto[1]	58	1			T14	1		T26	1		T27	1
auto[1207959552:1342177279]	auto[0]	53	1			T23	1		T74	1		T41	1
auto[1207959552:1342177279]	auto[1]	62	1			T39	1		T40	1		T84	1
auto[1342177280:1476395007]	auto[0]	59	1			T2	1		T26	1		T39	3
auto[1342177280:1476395007]	auto[1]	60	1			T26	1		T230	1		T40	3
auto[1476395008:1610612735]	auto[0]	54	1			T3	1		T39	2		T33	1
auto[1476395008:1610612735]	auto[1]	51	1			T26	1		T24	1		T32	1
auto[1610612736:1744830463]	auto[0]	57	1			T39	1		T220	1		T61	1
auto[1610612736:1744830463]	auto[1]	50	1			T26	1		T27	1		T39	2
auto[1744830464:1879048191]	auto[0]	58	1			T38	1		T26	2		T23	1
auto[1744830464:1879048191]	auto[1]	59	1			T26	2		T96	1		T39	1
auto[1879048192:2013265919]	auto[0]	43	1			T17	1		T40	1		T5	1
auto[1879048192:2013265919]	auto[1]	56	1			T38	1		T26	1		T39	1
auto[2013265920:2147483647]	auto[0]	51	1			T26	3		T23	1		T97	1
auto[2013265920:2147483647]	auto[1]	58	1			T26	1		T48	1		T58	1
auto[2147483648:2281701375]	auto[0]	44	1			T23	1		T109	1		T96	1
auto[2147483648:2281701375]	auto[1]	48	1			T39	1		T40	1		T134	1
auto[2281701376:2415919103]	auto[0]	49	1			T26	1		T23	1		T39	1
auto[2281701376:2415919103]	auto[1]	64	1			T109	1		T96	1		T39	3
auto[2415919104:2550136831]	auto[0]	48	1			T38	1		T39	1		T49	1
auto[2415919104:2550136831]	auto[1]	75	1			T2	1		T26	2		T37	1
auto[2550136832:2684354559]	auto[0]	43	1			T16	1		T39	1		T40	2
auto[2550136832:2684354559]	auto[1]	58	1			T26	2		T39	1		T37	1
auto[2684354560:2818572287]	auto[0]	43	1			T26	1		T39	1		T74	2
auto[2684354560:2818572287]	auto[1]	61	1			T3	1		T26	1		T39	1
auto[2818572288:2952790015]	auto[0]	51	1			T39	2		T40	1		T92	1
auto[2818572288:2952790015]	auto[1]	54	1			T74	1		T20	1		T82	1
auto[2952790016:3087007743]	auto[0]	40	1			T26	1		T39	1		T74	1
auto[2952790016:3087007743]	auto[1]	71	1			T14	1		T39	2		T41	1
auto[3087007744:3221225471]	auto[0]	45	1			T60	1		T40	1		T224	1
auto[3087007744:3221225471]	auto[1]	54	1			T97	1		T34	1		T328	1
auto[3221225472:3355443199]	auto[0]	51	1			T26	1		T39	3		T32	1
auto[3221225472:3355443199]	auto[1]	71	1			T26	4		T39	2		T97	1
auto[3355443200:3489660927]	auto[0]	38	1			T109	1		T39	1		T8	1
auto[3355443200:3489660927]	auto[1]	34	1			T13	1		T26	1		T39	1
auto[3489660928:3623878655]	auto[0]	60	1			T13	1		T16	1		T26	1
auto[3489660928:3623878655]	auto[1]	66	1			T16	1		T63	1		T317	1
auto[3623878656:3758096383]	auto[0]	46	1			T3	1		T109	1		T40	2
auto[3623878656:3758096383]	auto[1]	49	1			T26	1		T24	1		T74	1
auto[3758096384:3892314111]	auto[0]	54	1			T26	1		T33	1		T40	2
auto[3758096384:3892314111]	auto[1]	59	1			T24	1		T39	1		T102	1
auto[3892314112:4026531839]	auto[0]	38	1			T48	1		T40	1		T82	1
auto[3892314112:4026531839]	auto[1]	60	1			T2	1		T17	1		T26	1
auto[4026531840:4160749567]	auto[0]	46	1			T38	1		T26	2		T47	1
auto[4026531840:4160749567]	auto[1]	57	1			T4	1		T26	1		T32	1
auto[4160749568:4294967295]	auto[0]	53	1			T2	1		T40	1		T92	1
auto[4160749568:4294967295]	auto[1]	55	1			T3	1		T13	1		T26	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1557

1

T2

3

T3

2

T13

2

auto[1]

1843

1

T2

3

T3

2

T4

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T17	1		T24	1		T39	1
auto[134217728:268435455]	106	1			T26	1		T220	1		T32	3
auto[268435456:402653183]	103	1			T16	1		T26	1		T39	5
auto[402653184:536870911]	107	1			T14	1		T17	1		T26	1
auto[536870912:671088639]	91	1			T26	1		T39	1		T97	1
auto[671088640:805306367]	95	1			T3	1		T26	2		T39	1
auto[805306368:939524095]	104	1			T109	1		T39	2		T33	2
auto[939524096:1073741823]	104	1			T109	1		T39	3		T40	2
auto[1073741824:1207959551]	96	1			T3	1		T38	1		T26	2
auto[1207959552:1342177279]	116	1			T16	1		T38	1		T26	1
auto[1342177280:1476395007]	116	1			T2	1		T26	1		T23	1
auto[1476395008:1610612735]	99	1			T26	2		T23	1		T27	1
auto[1610612736:1744830463]	101	1			T13	1		T17	1		T38	1
auto[1744830464:1879048191]	118	1			T13	2		T26	3		T39	5
auto[1879048192:2013265919]	114	1			T26	1		T40	2		T141	1
auto[2013265920:2147483647]	110	1			T3	1		T14	1		T26	1
auto[2147483648:2281701375]	113	1			T26	1		T96	1		T47	1
auto[2281701376:2415919103]	93	1			T26	2		T39	3		T220	1
auto[2415919104:2550136831]	108	1			T2	1		T14	1		T26	1
auto[2550136832:2684354559]	120	1			T26	3		T23	1		T97	1
auto[2684354560:2818572287]	92	1			T3	1		T26	3		T39	1
auto[2818572288:2952790015]	116	1			T4	1		T17	1		T38	1
auto[2952790016:3087007743]	102	1			T26	1		T39	2		T32	1
auto[3087007744:3221225471]	99	1			T26	2		T23	1		T96	1
auto[3221225472:3355443199]	116	1			T26	2		T27	1		T24	1
auto[3355443200:3489660927]	106	1			T2	1		T26	1		T39	1
auto[3489660928:3623878655]	110	1			T4	1		T38	1		T26	1
auto[3623878656:3758096383]	106	1			T2	2		T4	1		T17	1
auto[3758096384:3892314111]	95	1			T26	2		T39	3		T48	1
auto[3892314112:4026531839]	123	1			T2	1		T14	1		T16	1
auto[4026531840:4160749567]	104	1			T26	1		T39	1		T58	1
auto[4160749568:4294967295]	106	1			T13	1		T26	1		T39	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T39	1		T97	1		T92	2
auto[0:134217727]	auto[1]	70	1			T17	1		T24	1		T49	1
auto[134217728:268435455]	auto[0]	51	1			T26	1		T32	2		T5	1
auto[134217728:268435455]	auto[1]	55	1			T220	1		T32	1		T97	1
auto[268435456:402653183]	auto[0]	43	1			T40	1		T92	1		T84	1
auto[268435456:402653183]	auto[1]	60	1			T16	1		T26	1		T39	5
auto[402653184:536870911]	auto[0]	55	1			T26	1		T39	3		T49	1
auto[402653184:536870911]	auto[1]	52	1			T14	1		T17	1		T39	2
auto[536870912:671088639]	auto[0]	37	1			T97	1		T40	1		T5	1
auto[536870912:671088639]	auto[1]	54	1			T26	1		T39	1		T238	2
auto[671088640:805306367]	auto[0]	51	1			T3	1		T26	1		T40	2
auto[671088640:805306367]	auto[1]	44	1			T26	1		T39	1		T332	1
auto[805306368:939524095]	auto[0]	45	1			T109	1		T39	1		T33	1
auto[805306368:939524095]	auto[1]	59	1			T39	1		T33	1		T40	1
auto[939524096:1073741823]	auto[0]	50	1			T109	1		T39	3		T40	1
auto[939524096:1073741823]	auto[1]	54	1			T40	1		T41	1		T134	1
auto[1073741824:1207959551]	auto[0]	52	1			T26	1		T23	1		T74	1
auto[1073741824:1207959551]	auto[1]	44	1			T3	1		T38	1		T26	1
auto[1207959552:1342177279]	auto[0]	62	1			T16	1		T38	1		T26	1
auto[1207959552:1342177279]	auto[1]	54	1			T39	1		T60	2		T41	1
auto[1342177280:1476395007]	auto[0]	53	1			T220	1		T40	1		T74	2
auto[1342177280:1476395007]	auto[1]	63	1			T2	1		T26	1		T23	1
auto[1476395008:1610612735]	auto[0]	47	1			T26	1		T23	1		T39	1
auto[1476395008:1610612735]	auto[1]	52	1			T26	1		T27	1		T37	1
auto[1610612736:1744830463]	auto[0]	45	1			T17	1		T38	1		T26	2
auto[1610612736:1744830463]	auto[1]	56	1			T13	1		T43	2		T39	2
auto[1744830464:1879048191]	auto[0]	46	1			T13	1		T26	2		T39	1
auto[1744830464:1879048191]	auto[1]	72	1			T13	1		T26	1		T39	4
auto[1879048192:2013265919]	auto[0]	59	1			T40	1		T317	1		T229	1
auto[1879048192:2013265919]	auto[1]	55	1			T26	1		T40	1		T141	1
auto[2013265920:2147483647]	auto[0]	51	1			T23	1		T74	2		T84	1
auto[2013265920:2147483647]	auto[1]	59	1			T3	1		T14	1		T26	1
auto[2147483648:2281701375]	auto[0]	56	1			T26	1		T47	1		T48	1
auto[2147483648:2281701375]	auto[1]	57	1			T96	1		T40	1		T41	1
auto[2281701376:2415919103]	auto[0]	28	1			T26	1		T34	1		T117	1
auto[2281701376:2415919103]	auto[1]	65	1			T26	1		T39	3		T220	1
auto[2415919104:2550136831]	auto[0]	46	1			T2	1		T26	1		T109	1
auto[2415919104:2550136831]	auto[1]	62	1			T14	1		T39	1		T34	1
auto[2550136832:2684354559]	auto[0]	65	1			T26	2		T225	1		T74	1
auto[2550136832:2684354559]	auto[1]	55	1			T26	1		T23	1		T97	1
auto[2684354560:2818572287]	auto[0]	37	1			T3	1		T39	1		T74	2
auto[2684354560:2818572287]	auto[1]	55	1			T26	3		T117	1		T5	1
auto[2818572288:2952790015]	auto[0]	50	1			T17	1		T38	1		T40	1
auto[2818572288:2952790015]	auto[1]	66	1			T4	1		T96	1		T39	2
auto[2952790016:3087007743]	auto[0]	52	1			T39	1		T33	1		T129	1
auto[2952790016:3087007743]	auto[1]	50	1			T26	1		T39	1		T32	1
auto[3087007744:3221225471]	auto[0]	50	1			T23	1		T39	1		T74	1
auto[3087007744:3221225471]	auto[1]	49	1			T26	2		T96	1		T39	1
auto[3221225472:3355443199]	auto[0]	54	1			T24	1		T96	1		T39	2
auto[3221225472:3355443199]	auto[1]	62	1			T26	2		T27	1		T39	1
auto[3355443200:3489660927]	auto[0]	49	1			T33	1		T40	1		T92	1
auto[3355443200:3489660927]	auto[1]	57	1			T2	1		T26	1		T39	1
auto[3489660928:3623878655]	auto[0]	41	1			T26	1		T225	1		T98	1
auto[3489660928:3623878655]	auto[1]	69	1			T4	1		T38	1		T39	1
auto[3623878656:3758096383]	auto[0]	49	1			T2	1		T17	1		T26	1
auto[3623878656:3758096383]	auto[1]	57	1			T2	1		T4	1		T61	1
auto[3758096384:3892314111]	auto[0]	39	1			T26	1		T39	1		T61	1
auto[3758096384:3892314111]	auto[1]	56	1			T26	1		T39	2		T48	1
auto[3892314112:4026531839]	auto[0]	60	1			T2	1		T16	1		T26	1
auto[3892314112:4026531839]	auto[1]	63	1			T14	1		T26	2		T63	1
auto[4026531840:4160749567]	auto[0]	44	1			T39	1		T25	1		T63	1
auto[4026531840:4160749567]	auto[1]	60	1			T26	1		T58	1		T40	1
auto[4160749568:4294967295]	auto[0]	49	1			T13	1		T26	1		T40	1
auto[4160749568:4294967295]	auto[1]	57	1			T39	1		T58	1		T236	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1534

1

T2

4

T3

2

T13

2

auto[1]

1867

1

T2

2

T3

2

T4

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T3	1		T38	1		T26	1
auto[134217728:268435455]	124	1			T2	1		T26	1		T96	1
auto[268435456:402653183]	100	1			T3	1		T26	2		T39	3
auto[402653184:536870911]	110	1			T23	1		T24	1		T39	2
auto[536870912:671088639]	98	1			T26	1		T39	3		T225	1
auto[671088640:805306367]	126	1			T4	1		T13	1		T23	1
auto[805306368:939524095]	103	1			T4	1		T23	1		T39	1
auto[939524096:1073741823]	94	1			T26	1		T43	1		T39	1
auto[1073741824:1207959551]	119	1			T23	1		T37	1		T40	3
auto[1207959552:1342177279]	118	1			T2	1		T16	1		T17	1
auto[1342177280:1476395007]	103	1			T17	1		T38	1		T23	1
auto[1476395008:1610612735]	102	1			T58	1		T97	1		T230	1
auto[1610612736:1744830463]	102	1			T16	1		T26	1		T39	2
auto[1744830464:1879048191]	128	1			T13	1		T16	1		T26	5
auto[1879048192:2013265919]	110	1			T26	2		T23	1		T39	1
auto[2013265920:2147483647]	109	1			T2	2		T26	2		T39	2
auto[2147483648:2281701375]	114	1			T26	2		T24	1		T39	4
auto[2281701376:2415919103]	106	1			T2	1		T3	2		T26	1
auto[2415919104:2550136831]	111	1			T38	2		T26	2		T43	1
auto[2550136832:2684354559]	108	1			T26	3		T27	1		T39	1
auto[2684354560:2818572287]	101	1			T4	1		T14	2		T39	2
auto[2818572288:2952790015]	94	1			T26	4		T96	1		T39	1
auto[2952790016:3087007743]	103	1			T17	1		T26	1		T39	2
auto[3087007744:3221225471]	100	1			T26	1		T39	1		T33	1
auto[3221225472:3355443199]	99	1			T17	1		T26	2		T96	1
auto[3355443200:3489660927]	111	1			T14	2		T26	1		T27	1
auto[3489660928:3623878655]	109	1			T26	2		T39	2		T97	1
auto[3623878656:3758096383]	101	1			T2	1		T17	1		T26	1
auto[3758096384:3892314111]	94	1			T38	1		T26	2		T23	1
auto[3892314112:4026531839]	86	1			T26	1		T109	2		T39	1
auto[4026531840:4160749567]	108	1			T13	1		T26	3		T39	3
auto[4160749568:4294967295]	101	1			T13	1		T26	1		T39	2