Unified Coverage Report :: Group Instance : salt_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3035

1

T2

6

T3

4

T4

3

auto[1]

238

1

T13

4

T117

9

T228

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T2	1		T4	1		T26	1
auto[134217728:268435455]	90	1			T13	1		T17	1		T26	2
auto[268435456:402653183]	90	1			T4	1		T26	2		T23	1
auto[402653184:536870911]	96	1			T13	1		T26	1		T23	1
auto[536870912:671088639]	107	1			T109	1		T39	2		T40	1
auto[671088640:805306367]	94	1			T3	1		T26	1		T39	5
auto[805306368:939524095]	101	1			T14	1		T26	1		T39	3
auto[939524096:1073741823]	102	1			T17	1		T38	1		T26	1
auto[1073741824:1207959551]	91	1			T13	1		T26	2		T39	2
auto[1207959552:1342177279]	131	1			T2	2		T3	1		T14	1
auto[1342177280:1476395007]	100	1			T3	1		T24	1		T39	1
auto[1476395008:1610612735]	114	1			T13	1		T14	1		T26	1
auto[1610612736:1744830463]	94	1			T26	1		T39	1		T74	1
auto[1744830464:1879048191]	117	1			T38	1		T39	1		T32	1
auto[1879048192:2013265919]	87	1			T26	1		T33	1		T40	1
auto[2013265920:2147483647]	94	1			T13	1		T26	1		T220	1
auto[2147483648:2281701375]	107	1			T24	1		T39	2		T47	1
auto[2281701376:2415919103]	100	1			T2	1		T17	1		T43	1
auto[2415919104:2550136831]	114	1			T2	1		T38	1		T23	3
auto[2550136832:2684354559]	115	1			T14	1		T26	1		T96	1
auto[2684354560:2818572287]	99	1			T2	1		T60	1		T74	1
auto[2818572288:2952790015]	98	1			T24	1		T39	1		T40	1
auto[2952790016:3087007743]	102	1			T3	1		T4	1		T27	1
auto[3087007744:3221225471]	103	1			T16	1		T26	2		T23	1
auto[3221225472:3355443199]	90	1			T13	1		T26	1		T96	1
auto[3355443200:3489660927]	116	1			T16	1		T17	1		T23	1
auto[3489660928:3623878655]	108	1			T26	3		T39	1		T220	2
auto[3623878656:3758096383]	107	1			T13	1		T26	1		T39	1
auto[3758096384:3892314111]	95	1			T26	2		T39	1		T32	1
auto[3892314112:4026531839]	117	1			T38	1		T43	1		T39	2
auto[4026531840:4160749567]	79	1			T13	1		T38	1		T26	1
auto[4160749568:4294967295]	114	1			T17	1		T26	2		T23	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	96	1			T2	1		T4	1		T26	1
auto[0:134217727]	auto[1]	5	1			T143	1		T318	1		T335	1
auto[134217728:268435455]	auto[0]	82	1			T17	1		T26	2		T109	1
auto[134217728:268435455]	auto[1]	8	1			T13	1		T412	1		T273	1
auto[268435456:402653183]	auto[0]	85	1			T4	1		T26	2		T23	1
auto[268435456:402653183]	auto[1]	5	1			T144	1		T411	1		T388	1
auto[402653184:536870911]	auto[0]	93	1			T13	1		T26	1		T23	1
auto[402653184:536870911]	auto[1]	3	1			T228	1		T352	1		T345	1
auto[536870912:671088639]	auto[0]	97	1			T109	1		T39	2		T40	1
auto[536870912:671088639]	auto[1]	10	1			T117	1		T146	1		T273	1
auto[671088640:805306367]	auto[0]	87	1			T3	1		T26	1		T39	5
auto[671088640:805306367]	auto[1]	7	1			T142	2		T318	1		T335	1
auto[805306368:939524095]	auto[0]	95	1			T14	1		T26	1		T39	3
auto[805306368:939524095]	auto[1]	6	1			T146	1		T419	1		T388	1
auto[939524096:1073741823]	auto[0]	96	1			T17	1		T38	1		T26	1
auto[939524096:1073741823]	auto[1]	6	1			T212	1		T144	1		T145	1
auto[1073741824:1207959551]	auto[0]	79	1			T26	2		T39	2		T33	1
auto[1073741824:1207959551]	auto[1]	12	1			T13	1		T318	1		T146	2
auto[1207959552:1342177279]	auto[0]	124	1			T2	2		T3	1		T14	1
auto[1207959552:1342177279]	auto[1]	7	1			T228	1		T107	1		T318	1
auto[1342177280:1476395007]	auto[0]	89	1			T3	1		T24	1		T39	1
auto[1342177280:1476395007]	auto[1]	11	1			T117	2		T276	1		T144	1
auto[1476395008:1610612735]	auto[0]	105	1			T14	1		T26	1		T24	1
auto[1476395008:1610612735]	auto[1]	9	1			T13	1		T228	1		T412	1
auto[1610612736:1744830463]	auto[0]	88	1			T26	1		T39	1		T74	1
auto[1610612736:1744830463]	auto[1]	6	1			T318	1		T273	1		T324	1
auto[1744830464:1879048191]	auto[0]	109	1			T38	1		T39	1		T32	1
auto[1744830464:1879048191]	auto[1]	8	1			T260	1		T335	1		T423	1
auto[1879048192:2013265919]	auto[0]	79	1			T26	1		T33	1		T40	1
auto[1879048192:2013265919]	auto[1]	8	1			T117	2		T142	1		T315	1
auto[2013265920:2147483647]	auto[0]	89	1			T26	1		T220	1		T32	1
auto[2013265920:2147483647]	auto[1]	5	1			T13	1		T117	1		T272	1
auto[2147483648:2281701375]	auto[0]	97	1			T24	1		T39	2		T47	1
auto[2147483648:2281701375]	auto[1]	10	1			T313	1		T144	1		T412	1
auto[2281701376:2415919103]	auto[0]	91	1			T2	1		T17	1		T43	1
auto[2281701376:2415919103]	auto[1]	9	1			T335	1		T324	1		T419	1
auto[2415919104:2550136831]	auto[0]	105	1			T2	1		T38	1		T23	3
auto[2415919104:2550136831]	auto[1]	9	1			T142	1		T276	1		T318	2
auto[2550136832:2684354559]	auto[0]	106	1			T14	1		T26	1		T96	1
auto[2550136832:2684354559]	auto[1]	9	1			T424	1		T419	1		T388	1
auto[2684354560:2818572287]	auto[0]	95	1			T2	1		T60	1		T74	1
auto[2684354560:2818572287]	auto[1]	4	1			T107	1		T411	1		T346	1
auto[2818572288:2952790015]	auto[0]	93	1			T24	1		T39	1		T40	1
auto[2818572288:2952790015]	auto[1]	5	1			T260	1		T318	1		T273	1
auto[2952790016:3087007743]	auto[0]	90	1			T3	1		T4	1		T27	1
auto[2952790016:3087007743]	auto[1]	12	1			T107	1		T144	1		T318	1
auto[3087007744:3221225471]	auto[0]	95	1			T16	1		T26	2		T23	1
auto[3087007744:3221225471]	auto[1]	8	1			T107	1		T145	1		T292	1
auto[3221225472:3355443199]	auto[0]	86	1			T13	1		T26	1		T96	1
auto[3221225472:3355443199]	auto[1]	4	1			T313	1		T279	2		T425	1
auto[3355443200:3489660927]	auto[0]	111	1			T16	1		T17	1		T23	1
auto[3355443200:3489660927]	auto[1]	5	1			T412	1		T324	1		T352	1
auto[3489660928:3623878655]	auto[0]	100	1			T26	3		T39	1		T220	2
auto[3489660928:3623878655]	auto[1]	8	1			T143	1		T318	1		T335	1
auto[3623878656:3758096383]	auto[0]	99	1			T13	1		T26	1		T39	1
auto[3623878656:3758096383]	auto[1]	8	1			T117	1		T228	1		T144	1
auto[3758096384:3892314111]	auto[0]	85	1			T26	2		T39	1		T32	1
auto[3758096384:3892314111]	auto[1]	10	1			T228	1		T276	1		T313	1
auto[3892314112:4026531839]	auto[0]	108	1			T38	1		T43	1		T39	2
auto[3892314112:4026531839]	auto[1]	9	1			T117	2		T276	1		T318	1
auto[4026531840:4160749567]	auto[0]	75	1			T13	1		T38	1		T26	1
auto[4026531840:4160749567]	auto[1]	4	1			T314	1		T414	1		T413	2
auto[4160749568:4294967295]	auto[0]	106	1			T17	1		T26	2		T23	1
auto[4160749568:4294967295]	auto[1]	8	1			T313	1		T143	1		T346	1