Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.81 99.07 98.18 98.33 100.00 99.11 98.41 91.58


Total test records in report: 1075
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T1009 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1577567446 Apr 18 12:32:25 PM PDT 24 Apr 18 12:32:28 PM PDT 24 31200233 ps
T1010 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.474094751 Apr 18 12:32:21 PM PDT 24 Apr 18 12:32:22 PM PDT 24 20622538 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2812302904 Apr 18 12:32:12 PM PDT 24 Apr 18 12:32:17 PM PDT 24 205641645 ps
T1012 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.500517330 Apr 18 12:32:13 PM PDT 24 Apr 18 12:32:22 PM PDT 24 190062882 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1433909493 Apr 18 12:32:14 PM PDT 24 Apr 18 12:32:17 PM PDT 24 16572840 ps
T156 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.920171025 Apr 18 12:32:18 PM PDT 24 Apr 18 12:32:25 PM PDT 24 196034245 ps
T1014 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3199172455 Apr 18 12:32:15 PM PDT 24 Apr 18 12:32:19 PM PDT 24 145390212 ps
T1015 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2603272998 Apr 18 12:32:20 PM PDT 24 Apr 18 12:32:25 PM PDT 24 137786831 ps
T158 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1569068260 Apr 18 12:32:26 PM PDT 24 Apr 18 12:32:38 PM PDT 24 386037964 ps
T1016 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.611743832 Apr 18 12:32:28 PM PDT 24 Apr 18 12:32:30 PM PDT 24 38122113 ps
T1017 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.39589354 Apr 18 12:32:38 PM PDT 24 Apr 18 12:32:39 PM PDT 24 15910232 ps
T1018 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2302230682 Apr 18 12:32:14 PM PDT 24 Apr 18 12:32:21 PM PDT 24 122767241 ps
T1019 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.494512170 Apr 18 12:32:21 PM PDT 24 Apr 18 12:32:24 PM PDT 24 27601111 ps
T1020 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.113846359 Apr 18 12:32:41 PM PDT 24 Apr 18 12:32:42 PM PDT 24 60079619 ps
T1021 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2430625958 Apr 18 12:32:24 PM PDT 24 Apr 18 12:32:25 PM PDT 24 17699791 ps
T159 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2877714760 Apr 18 12:32:00 PM PDT 24 Apr 18 12:32:17 PM PDT 24 1982192625 ps
T1022 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2512819583 Apr 18 12:32:12 PM PDT 24 Apr 18 12:32:18 PM PDT 24 220202019 ps
T1023 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1133274472 Apr 18 12:32:28 PM PDT 24 Apr 18 12:32:30 PM PDT 24 16251821 ps
T1024 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3992928257 Apr 18 12:32:17 PM PDT 24 Apr 18 12:32:20 PM PDT 24 24350344 ps
T1025 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2433175280 Apr 18 12:32:30 PM PDT 24 Apr 18 12:32:31 PM PDT 24 25468792 ps
T1026 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.288186326 Apr 18 12:32:32 PM PDT 24 Apr 18 12:32:34 PM PDT 24 42538153 ps
T1027 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2096044198 Apr 18 12:32:39 PM PDT 24 Apr 18 12:32:41 PM PDT 24 87919717 ps
T1028 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4287623095 Apr 18 12:32:11 PM PDT 24 Apr 18 12:32:17 PM PDT 24 392888077 ps
T1029 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1641460272 Apr 18 12:32:20 PM PDT 24 Apr 18 12:32:22 PM PDT 24 43973482 ps
T1030 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.551244599 Apr 18 12:31:59 PM PDT 24 Apr 18 12:32:04 PM PDT 24 169008369 ps
T1031 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3505232103 Apr 18 12:32:36 PM PDT 24 Apr 18 12:32:54 PM PDT 24 3605203424 ps
T1032 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.529756290 Apr 18 12:32:11 PM PDT 24 Apr 18 12:32:15 PM PDT 24 70568866 ps
T392 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1509811978 Apr 18 12:32:10 PM PDT 24 Apr 18 12:32:15 PM PDT 24 536085486 ps
T1033 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2708438683 Apr 18 12:32:42 PM PDT 24 Apr 18 12:32:45 PM PDT 24 657874532 ps
T1034 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1288628002 Apr 18 12:32:28 PM PDT 24 Apr 18 12:32:29 PM PDT 24 13675247 ps
T1035 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.765081986 Apr 18 12:33:19 PM PDT 24 Apr 18 12:33:23 PM PDT 24 154823392 ps
T1036 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.600858537 Apr 18 12:32:15 PM PDT 24 Apr 18 12:32:22 PM PDT 24 92688102 ps
T1037 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2405649049 Apr 18 12:32:40 PM PDT 24 Apr 18 12:32:42 PM PDT 24 18521533 ps
T1038 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2884014612 Apr 18 12:32:36 PM PDT 24 Apr 18 12:32:48 PM PDT 24 1758466843 ps
T1039 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1665975873 Apr 18 12:32:11 PM PDT 24 Apr 18 12:32:13 PM PDT 24 38700080 ps
T1040 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3593980777 Apr 18 12:32:19 PM PDT 24 Apr 18 12:32:31 PM PDT 24 427933008 ps
T1041 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.522052152 Apr 18 12:32:22 PM PDT 24 Apr 18 12:32:28 PM PDT 24 188774351 ps
T1042 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3886204201 Apr 18 12:31:59 PM PDT 24 Apr 18 12:32:11 PM PDT 24 158978379 ps
T1043 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.754965652 Apr 18 12:32:19 PM PDT 24 Apr 18 12:32:21 PM PDT 24 13850113 ps
T1044 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2217024696 Apr 18 12:32:30 PM PDT 24 Apr 18 12:32:36 PM PDT 24 317024055 ps
T1045 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2689185660 Apr 18 12:32:11 PM PDT 24 Apr 18 12:32:23 PM PDT 24 164853989 ps
T1046 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3982561288 Apr 18 12:32:28 PM PDT 24 Apr 18 12:32:32 PM PDT 24 84433605 ps
T1047 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1560376853 Apr 18 12:32:44 PM PDT 24 Apr 18 12:32:48 PM PDT 24 47965916 ps
T1048 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3490561006 Apr 18 12:32:14 PM PDT 24 Apr 18 12:32:25 PM PDT 24 130183601 ps
T1049 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.775062248 Apr 18 12:32:45 PM PDT 24 Apr 18 12:32:47 PM PDT 24 23456321 ps
T1050 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3749937321 Apr 18 12:32:32 PM PDT 24 Apr 18 12:32:40 PM PDT 24 341496414 ps
T164 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2314347464 Apr 18 12:32:33 PM PDT 24 Apr 18 12:32:46 PM PDT 24 445352928 ps
T168 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.758966694 Apr 18 12:32:34 PM PDT 24 Apr 18 12:32:45 PM PDT 24 983527744 ps
T1051 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1502564279 Apr 18 12:32:13 PM PDT 24 Apr 18 12:32:17 PM PDT 24 24584677 ps
T1052 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.103383173 Apr 18 12:33:35 PM PDT 24 Apr 18 12:33:36 PM PDT 24 9179061 ps
T1053 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.267387800 Apr 18 12:32:50 PM PDT 24 Apr 18 12:32:53 PM PDT 24 46336149 ps
T1054 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.28607675 Apr 18 12:32:11 PM PDT 24 Apr 18 12:32:14 PM PDT 24 34416341 ps
T1055 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3785860437 Apr 18 12:32:09 PM PDT 24 Apr 18 12:32:11 PM PDT 24 29388204 ps
T1056 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1288043097 Apr 18 12:32:31 PM PDT 24 Apr 18 12:32:36 PM PDT 24 98330363 ps
T1057 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2710100098 Apr 18 12:32:00 PM PDT 24 Apr 18 12:32:18 PM PDT 24 1041680880 ps
T1058 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.168804140 Apr 18 12:32:35 PM PDT 24 Apr 18 12:32:38 PM PDT 24 80069573 ps
T1059 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3381608740 Apr 18 12:31:58 PM PDT 24 Apr 18 12:32:07 PM PDT 24 2739097632 ps
T1060 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.529380554 Apr 18 12:32:12 PM PDT 24 Apr 18 12:32:17 PM PDT 24 802827078 ps
T1061 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.171187639 Apr 18 12:32:12 PM PDT 24 Apr 18 12:32:18 PM PDT 24 250535550 ps
T1062 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3655480399 Apr 18 12:32:34 PM PDT 24 Apr 18 12:32:39 PM PDT 24 107325916 ps
T1063 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2891989476 Apr 18 12:32:15 PM PDT 24 Apr 18 12:32:22 PM PDT 24 525917850 ps
T1064 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2825133315 Apr 18 12:32:04 PM PDT 24 Apr 18 12:32:09 PM PDT 24 430876065 ps
T1065 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1122891715 Apr 18 12:31:57 PM PDT 24 Apr 18 12:32:01 PM PDT 24 24698722 ps
T1066 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.71825677 Apr 18 12:32:16 PM PDT 24 Apr 18 12:32:20 PM PDT 24 149661181 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.570765099 Apr 18 12:32:13 PM PDT 24 Apr 18 12:32:16 PM PDT 24 103051489 ps
T1068 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1810044404 Apr 18 12:32:28 PM PDT 24 Apr 18 12:32:35 PM PDT 24 11187311 ps
T1069 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1303592357 Apr 18 12:32:18 PM PDT 24 Apr 18 12:32:20 PM PDT 24 54466927 ps
T1070 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3897590283 Apr 18 12:32:17 PM PDT 24 Apr 18 12:32:20 PM PDT 24 45594326 ps
T1071 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4247998433 Apr 18 12:32:26 PM PDT 24 Apr 18 12:32:29 PM PDT 24 106454416 ps
T1072 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2714859278 Apr 18 12:32:34 PM PDT 24 Apr 18 12:32:37 PM PDT 24 42524124 ps
T161 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3753543129 Apr 18 12:32:42 PM PDT 24 Apr 18 12:32:56 PM PDT 24 699497855 ps
T1073 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1526376492 Apr 18 12:32:11 PM PDT 24 Apr 18 12:32:14 PM PDT 24 123191297 ps
T1074 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.976699026 Apr 18 12:31:57 PM PDT 24 Apr 18 12:32:02 PM PDT 24 124174064 ps
T1075 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4228442926 Apr 18 12:32:00 PM PDT 24 Apr 18 12:32:08 PM PDT 24 3195088026 ps
T169 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1599614210 Apr 18 12:32:12 PM PDT 24 Apr 18 12:32:25 PM PDT 24 1030614210 ps

Test location /workspace/coverage/default/28.keymgr_random.221851877
Short name T17
Test name
Test status
Simulation time 942020022 ps
CPU time 21.93 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 208284 kb
Host smart-b398b888-1cc8-45cd-bed1-30cf6c33b6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221851877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.221851877
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1494042823
Short name T39
Test name
Test status
Simulation time 1156630795 ps
CPU time 29.45 seconds
Started Apr 18 12:36:14 PM PDT 24
Finished Apr 18 12:36:45 PM PDT 24
Peak memory 215948 kb
Host smart-fd0e1b16-ede7-4522-a738-a68be408e033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494042823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1494042823
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2998201643
Short name T26
Test name
Test status
Simulation time 1399725209 ps
CPU time 38.66 seconds
Started Apr 18 12:34:11 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 216328 kb
Host smart-962f3eef-c03c-4833-994a-c778c8f04a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998201643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2998201643
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.319798036
Short name T6
Test name
Test status
Simulation time 23887486756 ps
CPU time 128.34 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:36:13 PM PDT 24
Peak memory 275816 kb
Host smart-9d057eea-63bc-430b-8009-d8fc27fa553d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319798036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.319798036
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1939578380
Short name T140
Test name
Test status
Simulation time 293455754 ps
CPU time 10.54 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:35:04 PM PDT 24
Peak memory 222764 kb
Host smart-6fe81635-1550-48aa-b172-953f75f962fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939578380 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1939578380
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2480028299
Short name T56
Test name
Test status
Simulation time 272288963 ps
CPU time 12.86 seconds
Started Apr 18 12:33:55 PM PDT 24
Finished Apr 18 12:34:12 PM PDT 24
Peak memory 220576 kb
Host smart-0f4a8b19-e115-4dc2-9a6c-8854ae163739
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480028299 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2480028299
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1763460629
Short name T33
Test name
Test status
Simulation time 394462099 ps
CPU time 5.53 seconds
Started Apr 18 12:35:19 PM PDT 24
Finished Apr 18 12:35:25 PM PDT 24
Peak memory 214388 kb
Host smart-91d47aed-86f9-4510-9015-17dd034904c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763460629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1763460629
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1851070106
Short name T117
Test name
Test status
Simulation time 5620294639 ps
CPU time 76.79 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:36:13 PM PDT 24
Peak memory 216636 kb
Host smart-279efa8f-afae-47a9-a32b-23a59008093d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851070106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1851070106
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1897348507
Short name T40
Test name
Test status
Simulation time 1749338441 ps
CPU time 25.4 seconds
Started Apr 18 12:35:11 PM PDT 24
Finished Apr 18 12:35:37 PM PDT 24
Peak memory 216648 kb
Host smart-e3ce1279-9743-45d3-95f9-b6fac12c1710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897348507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1897348507
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3261432553
Short name T114
Test name
Test status
Simulation time 675671072 ps
CPU time 12.32 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:24 PM PDT 24
Peak memory 214228 kb
Host smart-60e7868a-fcf8-455b-8ab6-b4096186daa1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261432553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3261432553
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3291210706
Short name T8
Test name
Test status
Simulation time 113965271 ps
CPU time 3.31 seconds
Started Apr 18 12:36:05 PM PDT 24
Finished Apr 18 12:36:09 PM PDT 24
Peak memory 221276 kb
Host smart-1ee718f2-f564-48a0-a982-574ccc222be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291210706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3291210706
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1438943991
Short name T44
Test name
Test status
Simulation time 2043570811 ps
CPU time 39.34 seconds
Started Apr 18 12:35:20 PM PDT 24
Finished Apr 18 12:36:00 PM PDT 24
Peak memory 215936 kb
Host smart-f2f41826-f873-4346-b34a-049a020a71cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438943991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1438943991
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.279982186
Short name T346
Test name
Test status
Simulation time 1916778221 ps
CPU time 100.74 seconds
Started Apr 18 12:35:37 PM PDT 24
Finished Apr 18 12:37:19 PM PDT 24
Peak memory 215520 kb
Host smart-df100933-ad40-45cb-9aa4-ecd8a23689e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279982186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.279982186
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3392134597
Short name T23
Test name
Test status
Simulation time 103433512 ps
CPU time 4.31 seconds
Started Apr 18 12:35:27 PM PDT 24
Finished Apr 18 12:35:32 PM PDT 24
Peak memory 214520 kb
Host smart-1412b92f-1e74-4de8-a85e-36a1eb0b48c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392134597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3392134597
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.693349123
Short name T142
Test name
Test status
Simulation time 1151492727 ps
CPU time 63.11 seconds
Started Apr 18 12:35:36 PM PDT 24
Finished Apr 18 12:36:40 PM PDT 24
Peak memory 215604 kb
Host smart-7d7a411e-363c-4d83-bd28-bc95e23b7bd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693349123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.693349123
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2034492369
Short name T194
Test name
Test status
Simulation time 11597019725 ps
CPU time 269.12 seconds
Started Apr 18 12:35:06 PM PDT 24
Finished Apr 18 12:39:36 PM PDT 24
Peak memory 218248 kb
Host smart-47fdf235-2afc-4e98-a628-702e86e2eea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034492369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2034492369
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3504310293
Short name T413
Test name
Test status
Simulation time 198852591 ps
CPU time 10.13 seconds
Started Apr 18 12:36:03 PM PDT 24
Finished Apr 18 12:36:15 PM PDT 24
Peak memory 214564 kb
Host smart-caa72ff0-03dd-4847-bbda-73b051c8b2b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3504310293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3504310293
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1862489552
Short name T13
Test name
Test status
Simulation time 6241186058 ps
CPU time 83.03 seconds
Started Apr 18 12:33:56 PM PDT 24
Finished Apr 18 12:35:23 PM PDT 24
Peak memory 222352 kb
Host smart-a706d2c9-f667-451e-a1c2-3e4d55cd790f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862489552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1862489552
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1192351292
Short name T32
Test name
Test status
Simulation time 1367019892 ps
CPU time 10.52 seconds
Started Apr 18 12:36:13 PM PDT 24
Finished Apr 18 12:36:25 PM PDT 24
Peak memory 222788 kb
Host smart-4a13d6fa-6c74-4ab4-ad00-2602ef2aa259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192351292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1192351292
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1000412380
Short name T81
Test name
Test status
Simulation time 2924974098 ps
CPU time 28.07 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:36:04 PM PDT 24
Peak memory 222804 kb
Host smart-8364e948-7536-4e42-a25e-6da99189ad3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000412380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1000412380
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4292784890
Short name T113
Test name
Test status
Simulation time 304566840 ps
CPU time 4.65 seconds
Started Apr 18 12:32:21 PM PDT 24
Finished Apr 18 12:32:26 PM PDT 24
Peak memory 214380 kb
Host smart-22746556-d3bd-4e0f-afe7-c133418a3326
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292784890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.4292784890
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3968972284
Short name T367
Test name
Test status
Simulation time 9206707972 ps
CPU time 118.97 seconds
Started Apr 18 12:33:56 PM PDT 24
Finished Apr 18 12:35:59 PM PDT 24
Peak memory 215916 kb
Host smart-8a673c59-9f3d-4ff4-b24a-3076bc909492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3968972284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3968972284
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.4066161026
Short name T34
Test name
Test status
Simulation time 5436843990 ps
CPU time 53.03 seconds
Started Apr 18 12:34:49 PM PDT 24
Finished Apr 18 12:35:43 PM PDT 24
Peak memory 214548 kb
Host smart-b95a0fc8-6111-4bed-aba9-cf2943b4272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066161026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.4066161026
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1846550036
Short name T111
Test name
Test status
Simulation time 223726173 ps
CPU time 14.29 seconds
Started Apr 18 12:36:21 PM PDT 24
Finished Apr 18 12:36:36 PM PDT 24
Peak memory 222840 kb
Host smart-18380e68-4f01-477c-84eb-bddc95d405de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846550036 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1846550036
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.829899947
Short name T263
Test name
Test status
Simulation time 626734690 ps
CPU time 29.6 seconds
Started Apr 18 12:35:29 PM PDT 24
Finished Apr 18 12:36:00 PM PDT 24
Peak memory 222716 kb
Host smart-16c8566c-cd9d-401b-87cf-4ef568f75e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829899947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.829899947
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1548953628
Short name T433
Test name
Test status
Simulation time 8694520 ps
CPU time 0.73 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:54 PM PDT 24
Peak memory 206124 kb
Host smart-e503e730-f42d-4945-a0c0-7df67441d960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548953628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1548953628
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3300400398
Short name T27
Test name
Test status
Simulation time 526417085 ps
CPU time 4.6 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:52 PM PDT 24
Peak memory 214296 kb
Host smart-9e15d779-150c-4639-81ab-02be9f2c7f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300400398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3300400398
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1973565436
Short name T345
Test name
Test status
Simulation time 763145857 ps
CPU time 6.25 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:55 PM PDT 24
Peak memory 215164 kb
Host smart-68de24dd-17ac-4227-b505-a1228fef1afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973565436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1973565436
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.4021773677
Short name T90
Test name
Test status
Simulation time 163120911 ps
CPU time 5.27 seconds
Started Apr 18 12:35:28 PM PDT 24
Finished Apr 18 12:35:35 PM PDT 24
Peak memory 218404 kb
Host smart-cb479d6f-1e9a-49b8-8d6a-140b786109a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021773677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.4021773677
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1798868230
Short name T338
Test name
Test status
Simulation time 653810135 ps
CPU time 32.18 seconds
Started Apr 18 12:34:30 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 215936 kb
Host smart-a11696fa-f275-44ab-a754-84e6a5ded8cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798868230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1798868230
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.397331117
Short name T22
Test name
Test status
Simulation time 145630153 ps
CPU time 2.43 seconds
Started Apr 18 12:34:57 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 223068 kb
Host smart-526c39f8-bd89-401e-8d94-94c345cab8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397331117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.397331117
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2314347464
Short name T164
Test name
Test status
Simulation time 445352928 ps
CPU time 11.79 seconds
Started Apr 18 12:32:33 PM PDT 24
Finished Apr 18 12:32:46 PM PDT 24
Peak memory 213840 kb
Host smart-e768c177-0775-4b1e-a9c2-1c545515e6ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314347464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2314347464
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3518837738
Short name T155
Test name
Test status
Simulation time 170710081 ps
CPU time 3.11 seconds
Started Apr 18 12:34:36 PM PDT 24
Finished Apr 18 12:34:40 PM PDT 24
Peak memory 210084 kb
Host smart-5c20537e-6740-4242-9818-4b8e4fdd7f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518837738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3518837738
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.648736606
Short name T177
Test name
Test status
Simulation time 69380787 ps
CPU time 3.43 seconds
Started Apr 18 12:35:21 PM PDT 24
Finished Apr 18 12:35:25 PM PDT 24
Peak memory 215752 kb
Host smart-82471b84-ef6a-4c49-bab6-f8696501f645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648736606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.648736606
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.4030776973
Short name T5
Test name
Test status
Simulation time 340240569 ps
CPU time 12.37 seconds
Started Apr 18 12:35:13 PM PDT 24
Finished Apr 18 12:35:26 PM PDT 24
Peak memory 222504 kb
Host smart-eda34c70-6f77-43c6-8bef-ce1871437f3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030776973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4030776973
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2641672981
Short name T146
Test name
Test status
Simulation time 184084156 ps
CPU time 10.37 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:59 PM PDT 24
Peak memory 215400 kb
Host smart-8c914135-3292-4d40-9f9f-ee43696578b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641672981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2641672981
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.346453453
Short name T771
Test name
Test status
Simulation time 83077921 ps
CPU time 3.99 seconds
Started Apr 18 12:34:32 PM PDT 24
Finished Apr 18 12:34:37 PM PDT 24
Peak memory 215540 kb
Host smart-085a2a07-6fbf-4e9c-a55e-5226527dc045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=346453453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.346453453
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2128153205
Short name T313
Test name
Test status
Simulation time 114101827 ps
CPU time 4.36 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 215820 kb
Host smart-06089c42-12d1-4465-b46f-404dad85b0cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128153205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2128153205
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1007341992
Short name T224
Test name
Test status
Simulation time 2486662101 ps
CPU time 88.24 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:37:01 PM PDT 24
Peak memory 230964 kb
Host smart-d20b8aaa-deb4-4dfd-9f66-164df13bd9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007341992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1007341992
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2061494203
Short name T198
Test name
Test status
Simulation time 1708801851 ps
CPU time 42.26 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:35:35 PM PDT 24
Peak memory 215220 kb
Host smart-b5f53472-4bbd-45e7-ad25-3b3c1c345dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061494203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2061494203
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.434479245
Short name T301
Test name
Test status
Simulation time 34680631 ps
CPU time 2.7 seconds
Started Apr 18 12:35:46 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 211384 kb
Host smart-f9268a34-b1db-4f06-a238-226acb7b85b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434479245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.434479245
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3009759855
Short name T160
Test name
Test status
Simulation time 340232249 ps
CPU time 12.07 seconds
Started Apr 18 12:32:35 PM PDT 24
Finished Apr 18 12:32:48 PM PDT 24
Peak memory 208992 kb
Host smart-ee7da326-47c1-4f55-9e61-1caa4eac482b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009759855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3009759855
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2877714760
Short name T159
Test name
Test status
Simulation time 1982192625 ps
CPU time 13.71 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 209040 kb
Host smart-870d1c38-f381-453b-bb18-605e8f7ce16b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877714760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2877714760
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2195970963
Short name T96
Test name
Test status
Simulation time 31517243 ps
CPU time 2.46 seconds
Started Apr 18 12:34:43 PM PDT 24
Finished Apr 18 12:34:47 PM PDT 24
Peak memory 214516 kb
Host smart-1670da27-7cb4-4d39-a53a-957f0f24da24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195970963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2195970963
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2032818044
Short name T141
Test name
Test status
Simulation time 157311989 ps
CPU time 2.51 seconds
Started Apr 18 12:34:09 PM PDT 24
Finished Apr 18 12:34:12 PM PDT 24
Peak memory 214664 kb
Host smart-1751d5d5-5497-4159-8d57-f9aee36980fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032818044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2032818044
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.548166999
Short name T245
Test name
Test status
Simulation time 1490388100 ps
CPU time 52.88 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:35:12 PM PDT 24
Peak memory 215584 kb
Host smart-70e7cd7a-4aa6-4785-8b62-20b2cf776824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548166999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.548166999
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.920171025
Short name T156
Test name
Test status
Simulation time 196034245 ps
CPU time 5.47 seconds
Started Apr 18 12:32:18 PM PDT 24
Finished Apr 18 12:32:25 PM PDT 24
Peak memory 209100 kb
Host smart-a1315173-4b45-4953-93aa-8dff8257f133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920171025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.920171025
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2630342914
Short name T82
Test name
Test status
Simulation time 138098842 ps
CPU time 2.74 seconds
Started Apr 18 12:36:21 PM PDT 24
Finished Apr 18 12:36:24 PM PDT 24
Peak memory 214532 kb
Host smart-cf51b1ee-ea61-48f6-8c69-de7c3fc48555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630342914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2630342914
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3383655628
Short name T324
Test name
Test status
Simulation time 35106642 ps
CPU time 2.87 seconds
Started Apr 18 12:35:32 PM PDT 24
Finished Apr 18 12:35:37 PM PDT 24
Peak memory 215512 kb
Host smart-28065834-2458-4735-9944-0551f77c29b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383655628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3383655628
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1634173942
Short name T293
Test name
Test status
Simulation time 127677740 ps
CPU time 3.2 seconds
Started Apr 18 12:36:17 PM PDT 24
Finished Apr 18 12:36:21 PM PDT 24
Peak memory 215548 kb
Host smart-2d6e9e47-eb0d-4684-bc14-cee7d7ac3131
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634173942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1634173942
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1798108380
Short name T174
Test name
Test status
Simulation time 2835606563 ps
CPU time 22.36 seconds
Started Apr 18 12:35:43 PM PDT 24
Finished Apr 18 12:36:07 PM PDT 24
Peak memory 218388 kb
Host smart-a204bde3-9a54-4a82-a8d2-650f9e7c3e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798108380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1798108380
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1074416692
Short name T175
Test name
Test status
Simulation time 515673004 ps
CPU time 3.48 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 217816 kb
Host smart-7cd3f95d-ed65-4329-ab54-ac8490086954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074416692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1074416692
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4131811831
Short name T139
Test name
Test status
Simulation time 85828029 ps
CPU time 1.32 seconds
Started Apr 18 12:34:35 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 209644 kb
Host smart-6c7f40ad-5f49-4e8e-8ba3-a0b5802dcb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131811831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4131811831
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1608167647
Short name T241
Test name
Test status
Simulation time 40033598588 ps
CPU time 201.85 seconds
Started Apr 18 12:35:08 PM PDT 24
Finished Apr 18 12:38:31 PM PDT 24
Peak memory 218492 kb
Host smart-1ee484d9-8f76-440f-9ad2-988ac65504d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608167647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1608167647
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1352981258
Short name T372
Test name
Test status
Simulation time 13906715168 ps
CPU time 67.33 seconds
Started Apr 18 12:36:15 PM PDT 24
Finished Apr 18 12:37:23 PM PDT 24
Peak memory 222792 kb
Host smart-45b50f8e-ba20-4458-aa48-e952741971eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352981258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1352981258
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3922574368
Short name T276
Test name
Test status
Simulation time 49794065 ps
CPU time 3.85 seconds
Started Apr 18 12:36:06 PM PDT 24
Finished Apr 18 12:36:12 PM PDT 24
Peak memory 215676 kb
Host smart-3da42778-24e8-436c-9a44-e765b46da5de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922574368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3922574368
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1927249394
Short name T162
Test name
Test status
Simulation time 334035444 ps
CPU time 9.3 seconds
Started Apr 18 12:32:41 PM PDT 24
Finished Apr 18 12:32:51 PM PDT 24
Peak memory 209528 kb
Host smart-f8e26103-545d-42cf-a9e0-ad099b4b186d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927249394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1927249394
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.613595773
Short name T123
Test name
Test status
Simulation time 145278544 ps
CPU time 3.39 seconds
Started Apr 18 12:32:19 PM PDT 24
Finished Apr 18 12:32:23 PM PDT 24
Peak memory 214244 kb
Host smart-f0dcfb2f-9319-47d6-a374-b239ecf6853d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613595773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.613595773
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.373824441
Short name T92
Test name
Test status
Simulation time 40737566 ps
CPU time 2.81 seconds
Started Apr 18 12:33:56 PM PDT 24
Finished Apr 18 12:34:03 PM PDT 24
Peak memory 211060 kb
Host smart-c27700f2-b8c3-421b-9275-5418ae762563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373824441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.373824441
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1963138014
Short name T305
Test name
Test status
Simulation time 118141253 ps
CPU time 2.71 seconds
Started Apr 18 12:34:45 PM PDT 24
Finished Apr 18 12:34:49 PM PDT 24
Peak memory 211596 kb
Host smart-fbd5a4af-858a-411e-a4a4-1d8a2a86f8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963138014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1963138014
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2720831928
Short name T526
Test name
Test status
Simulation time 220809729 ps
CPU time 4.81 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 207000 kb
Host smart-21f9fab5-f140-4f9a-a3cf-f7c5af53952e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720831928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2720831928
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.417558538
Short name T238
Test name
Test status
Simulation time 105202167 ps
CPU time 3.25 seconds
Started Apr 18 12:35:54 PM PDT 24
Finished Apr 18 12:35:58 PM PDT 24
Peak memory 214460 kb
Host smart-6ba6e3b2-0c8e-4504-a33e-9e2e6f63d0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417558538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.417558538
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.896373718
Short name T16
Test name
Test status
Simulation time 135657654 ps
CPU time 5.76 seconds
Started Apr 18 12:34:49 PM PDT 24
Finished Apr 18 12:34:56 PM PDT 24
Peak memory 218900 kb
Host smart-256914c3-64f5-4775-b892-374254670a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896373718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.896373718
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1644719681
Short name T176
Test name
Test status
Simulation time 259200246 ps
CPU time 4.43 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:54 PM PDT 24
Peak memory 222916 kb
Host smart-e18b9acc-fe57-4d0d-8043-2800905efe81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644719681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1644719681
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1171232534
Short name T339
Test name
Test status
Simulation time 187944675 ps
CPU time 7.73 seconds
Started Apr 18 12:34:25 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 214532 kb
Host smart-b3927ddf-c6f3-4cb8-844c-fc10473db13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171232534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1171232534
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2977269073
Short name T61
Test name
Test status
Simulation time 44246692 ps
CPU time 2.88 seconds
Started Apr 18 12:34:32 PM PDT 24
Finished Apr 18 12:34:36 PM PDT 24
Peak memory 209408 kb
Host smart-e7273310-b44b-4bf0-b7da-9633db78c156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977269073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2977269073
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.517599575
Short name T327
Test name
Test status
Simulation time 1625977106 ps
CPU time 17.92 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:35:05 PM PDT 24
Peak memory 222732 kb
Host smart-234e6fb4-65de-493e-9c5d-8cde16ff40f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517599575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.517599575
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2535365097
Short name T70
Test name
Test status
Simulation time 1437056943 ps
CPU time 39.93 seconds
Started Apr 18 12:34:51 PM PDT 24
Finished Apr 18 12:35:32 PM PDT 24
Peak memory 215912 kb
Host smart-8b6e036a-1fc4-4096-8906-4c03f5eecbbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535365097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2535365097
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1079180921
Short name T411
Test name
Test status
Simulation time 82357791 ps
CPU time 3.58 seconds
Started Apr 18 12:34:48 PM PDT 24
Finished Apr 18 12:34:53 PM PDT 24
Peak memory 214548 kb
Host smart-95b1e617-0d39-4602-8ec3-b8f9be92f696
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079180921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1079180921
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1125769704
Short name T87
Test name
Test status
Simulation time 123045183 ps
CPU time 2.51 seconds
Started Apr 18 12:34:58 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 221508 kb
Host smart-4f590149-fae9-4534-bc0d-877602777e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125769704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1125769704
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3079728781
Short name T259
Test name
Test status
Simulation time 11678129764 ps
CPU time 134.69 seconds
Started Apr 18 12:35:21 PM PDT 24
Finished Apr 18 12:37:37 PM PDT 24
Peak memory 222772 kb
Host smart-21cc2add-74f5-4c16-b63b-07cc1ac457c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079728781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3079728781
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3560695604
Short name T71
Test name
Test status
Simulation time 342860327 ps
CPU time 6.6 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 208216 kb
Host smart-e5475ce0-d16c-4040-ac6e-f87645c4e968
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560695604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3560695604
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1246884595
Short name T379
Test name
Test status
Simulation time 60263961 ps
CPU time 3.01 seconds
Started Apr 18 12:34:00 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 214528 kb
Host smart-1230075f-7f44-45f6-a2e7-fa9bdbec81fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246884595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1246884595
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.466407659
Short name T272
Test name
Test status
Simulation time 63946533 ps
CPU time 2.77 seconds
Started Apr 18 12:35:34 PM PDT 24
Finished Apr 18 12:35:38 PM PDT 24
Peak memory 214488 kb
Host smart-13a80176-4429-48f9-af7e-8484a8458a76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466407659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.466407659
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3162148434
Short name T267
Test name
Test status
Simulation time 250436366 ps
CPU time 7.51 seconds
Started Apr 18 12:35:39 PM PDT 24
Finished Apr 18 12:35:48 PM PDT 24
Peak memory 222592 kb
Host smart-5aaab3c2-7a83-41b1-bd76-43c4ba14a32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162148434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3162148434
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2097182955
Short name T172
Test name
Test status
Simulation time 366916689 ps
CPU time 9.36 seconds
Started Apr 18 12:32:34 PM PDT 24
Finished Apr 18 12:32:45 PM PDT 24
Peak memory 209352 kb
Host smart-7bf2011e-e3fa-40be-aa81-4be807066044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097182955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2097182955
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3831573094
Short name T167
Test name
Test status
Simulation time 2647984670 ps
CPU time 9.38 seconds
Started Apr 18 12:32:29 PM PDT 24
Finished Apr 18 12:32:39 PM PDT 24
Peak memory 213976 kb
Host smart-36500cfe-3bae-42f6-82b3-c94ddfd3b8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831573094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3831573094
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1599614210
Short name T169
Test name
Test status
Simulation time 1030614210 ps
CPU time 11.2 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:25 PM PDT 24
Peak memory 208948 kb
Host smart-72e636d8-6ee0-4c12-891c-b2e1631e28d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599614210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1599614210
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2392180593
Short name T348
Test name
Test status
Simulation time 49251382 ps
CPU time 2.58 seconds
Started Apr 18 12:33:48 PM PDT 24
Finished Apr 18 12:33:52 PM PDT 24
Peak memory 208916 kb
Host smart-8409be5c-4869-4fdc-9310-e53495cda419
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392180593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2392180593
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2086652004
Short name T28
Test name
Test status
Simulation time 289158838 ps
CPU time 4.33 seconds
Started Apr 18 12:34:32 PM PDT 24
Finished Apr 18 12:34:37 PM PDT 24
Peak memory 214468 kb
Host smart-ea9447f9-75fb-4fab-8e13-74588bf86964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086652004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2086652004
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3265563443
Short name T500
Test name
Test status
Simulation time 102124655 ps
CPU time 2.85 seconds
Started Apr 18 12:34:30 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 209692 kb
Host smart-790eb9ec-e215-4fbb-877d-096fc5271344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265563443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3265563443
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1617880763
Short name T825
Test name
Test status
Simulation time 401570791 ps
CPU time 11.51 seconds
Started Apr 18 12:34:47 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 222616 kb
Host smart-eace6079-d74c-456c-bf0a-93fe03fa78af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617880763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1617880763
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2449139462
Short name T244
Test name
Test status
Simulation time 33040935 ps
CPU time 2.53 seconds
Started Apr 18 12:34:41 PM PDT 24
Finished Apr 18 12:34:44 PM PDT 24
Peak memory 220536 kb
Host smart-ee973f48-52e9-4d87-9ce4-1d65b066694f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449139462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2449139462
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2210069751
Short name T341
Test name
Test status
Simulation time 78729478 ps
CPU time 3.79 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:07 PM PDT 24
Peak memory 214476 kb
Host smart-9c4f7ddd-9534-4c56-86a3-e8c7418d4fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210069751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2210069751
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.491532372
Short name T180
Test name
Test status
Simulation time 269108473 ps
CPU time 8.32 seconds
Started Apr 18 12:33:59 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 219744 kb
Host smart-adadf05c-e32e-41b8-aac0-6a6f748d0641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491532372 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.491532372
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2986869384
Short name T321
Test name
Test status
Simulation time 930138075 ps
CPU time 5.46 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 210428 kb
Host smart-caf5f0d8-c108-4ef7-aa91-3f847c6b0578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986869384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2986869384
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1612992947
Short name T303
Test name
Test status
Simulation time 524034146 ps
CPU time 5.7 seconds
Started Apr 18 12:35:23 PM PDT 24
Finished Apr 18 12:35:30 PM PDT 24
Peak memory 222712 kb
Host smart-3d4eb917-fa88-48ff-8457-e8e139663a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612992947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1612992947
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.627572221
Short name T252
Test name
Test status
Simulation time 536118311 ps
CPU time 17.28 seconds
Started Apr 18 12:35:20 PM PDT 24
Finished Apr 18 12:35:38 PM PDT 24
Peak memory 222944 kb
Host smart-c8f38fa1-2626-4cac-9359-622030ca9ec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627572221 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.627572221
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.751679837
Short name T378
Test name
Test status
Simulation time 807275300 ps
CPU time 6.65 seconds
Started Apr 18 12:34:00 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 211480 kb
Host smart-2cbab028-a532-4ad6-85cc-2fb115012b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751679837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.751679837
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1605279998
Short name T256
Test name
Test status
Simulation time 777345931 ps
CPU time 37.18 seconds
Started Apr 18 12:35:53 PM PDT 24
Finished Apr 18 12:36:31 PM PDT 24
Peak memory 216600 kb
Host smart-5d108848-76d6-46ce-99f7-178c6bc23b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605279998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1605279998
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1857999490
Short name T755
Test name
Test status
Simulation time 729448760 ps
CPU time 5.04 seconds
Started Apr 18 12:35:41 PM PDT 24
Finished Apr 18 12:35:47 PM PDT 24
Peak memory 208444 kb
Host smart-f4dbe466-9bf0-43e3-9454-252a67d925a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857999490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1857999490
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2711496428
Short name T286
Test name
Test status
Simulation time 461776666 ps
CPU time 12.61 seconds
Started Apr 18 12:36:09 PM PDT 24
Finished Apr 18 12:36:23 PM PDT 24
Peak memory 222596 kb
Host smart-4b5d2cf4-18db-4587-b694-c55b7c4bf9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711496428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2711496428
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2998204699
Short name T357
Test name
Test status
Simulation time 103058416 ps
CPU time 4.97 seconds
Started Apr 18 12:36:19 PM PDT 24
Finished Apr 18 12:36:25 PM PDT 24
Peak memory 222656 kb
Host smart-a61174b4-b04b-4a0b-81b5-2366af88068c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998204699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2998204699
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.41148068
Short name T145
Test name
Test status
Simulation time 49585069 ps
CPU time 3.68 seconds
Started Apr 18 12:34:19 PM PDT 24
Finished Apr 18 12:34:24 PM PDT 24
Peak memory 215956 kb
Host smart-c3b55061-69d7-45f1-b97b-87ff052a4934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41148068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.41148068
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3886204201
Short name T1042
Test name
Test status
Simulation time 158978379 ps
CPU time 8.55 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:11 PM PDT 24
Peak memory 205728 kb
Host smart-6d173af8-dd78-4bbc-9b02-ac415d260474
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886204201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
886204201
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2710100098
Short name T1057
Test name
Test status
Simulation time 1041680880 ps
CPU time 15.34 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 205824 kb
Host smart-31701cd4-3627-4d43-8878-8d9f84522dc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710100098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
710100098
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3844778063
Short name T947
Test name
Test status
Simulation time 207350965 ps
CPU time 1.14 seconds
Started Apr 18 12:32:07 PM PDT 24
Finished Apr 18 12:32:10 PM PDT 24
Peak memory 205764 kb
Host smart-53b5a3d8-57ab-4aef-8af4-c9495a67a49b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844778063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
844778063
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.946959536
Short name T976
Test name
Test status
Simulation time 41163102 ps
CPU time 1.11 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:12 PM PDT 24
Peak memory 205816 kb
Host smart-39797c8d-7ca7-4ee8-bb8d-8822edb291cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946959536 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.946959536
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3785860437
Short name T1055
Test name
Test status
Simulation time 29388204 ps
CPU time 0.93 seconds
Started Apr 18 12:32:09 PM PDT 24
Finished Apr 18 12:32:11 PM PDT 24
Peak memory 205572 kb
Host smart-3a845359-0182-47ef-ab37-92d38d56793f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785860437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3785860437
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1665975873
Short name T1039
Test name
Test status
Simulation time 38700080 ps
CPU time 0.73 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:13 PM PDT 24
Peak memory 205368 kb
Host smart-1f69dc16-3125-4648-bdd0-9442d3e63475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665975873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1665975873
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3715884176
Short name T151
Test name
Test status
Simulation time 146442263 ps
CPU time 2.29 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:06 PM PDT 24
Peak memory 205800 kb
Host smart-6c3d3407-cf0f-4f6c-9832-c601487e7710
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715884176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3715884176
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3381608740
Short name T1059
Test name
Test status
Simulation time 2739097632 ps
CPU time 5.92 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 214264 kb
Host smart-de1eee23-c24d-4ac2-bb2e-2c04fe0b52a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381608740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3381608740
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.4228442926
Short name T1075
Test name
Test status
Simulation time 3195088026 ps
CPU time 5.3 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:08 PM PDT 24
Peak memory 214332 kb
Host smart-a12f00a1-296a-4142-b0f7-1fd9b9f405b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228442926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.4228442926
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3540104245
Short name T919
Test name
Test status
Simulation time 26292877 ps
CPU time 1.65 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 213936 kb
Host smart-9a8f39cb-9c63-4fea-8cb5-de4e412a12bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540104245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3540104245
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2263559101
Short name T996
Test name
Test status
Simulation time 73370333 ps
CPU time 3.97 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:07 PM PDT 24
Peak memory 205740 kb
Host smart-3d7020af-a1aa-4c3f-ad51-f0185baf661e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263559101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
263559101
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4014529464
Short name T965
Test name
Test status
Simulation time 375273031 ps
CPU time 14.2 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:26 PM PDT 24
Peak memory 205668 kb
Host smart-21abcec4-2c0e-4f82-85f5-e87078bf2922
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014529464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4
014529464
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2468094538
Short name T993
Test name
Test status
Simulation time 50824118 ps
CPU time 1.12 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 205756 kb
Host smart-2b10645f-bdc9-4555-8151-85670400bbf2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468094538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
468094538
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.551244599
Short name T1030
Test name
Test status
Simulation time 169008369 ps
CPU time 1.42 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 214012 kb
Host smart-05eea61f-6952-4fc0-b0d7-2bf623703216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551244599 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.551244599
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.754965652
Short name T1043
Test name
Test status
Simulation time 13850113 ps
CPU time 1.05 seconds
Started Apr 18 12:32:19 PM PDT 24
Finished Apr 18 12:32:21 PM PDT 24
Peak memory 205660 kb
Host smart-01b830c8-8911-4832-8d6d-1e4bd502ebf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754965652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.754965652
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.584079954
Short name T936
Test name
Test status
Simulation time 9726969 ps
CPU time 0.7 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:03 PM PDT 24
Peak memory 205452 kb
Host smart-58440bdb-59a2-406c-9507-3e17604eda78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584079954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.584079954
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3183228481
Short name T995
Test name
Test status
Simulation time 65491136 ps
CPU time 2.37 seconds
Started Apr 18 12:32:01 PM PDT 24
Finished Apr 18 12:32:06 PM PDT 24
Peak memory 205736 kb
Host smart-7a9d2978-f472-4842-b265-cb8bc5e0e558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183228481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3183228481
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3222922748
Short name T975
Test name
Test status
Simulation time 332743402 ps
CPU time 4.28 seconds
Started Apr 18 12:31:58 PM PDT 24
Finished Apr 18 12:32:06 PM PDT 24
Peak memory 214176 kb
Host smart-2ee9cb70-a1dd-41a7-9fd3-cfa930bb378c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222922748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3222922748
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.500517330
Short name T1012
Test name
Test status
Simulation time 190062882 ps
CPU time 6.63 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:22 PM PDT 24
Peak memory 220416 kb
Host smart-d4e76c22-42a3-4d5a-ab81-2b3d58492483
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500517330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.500517330
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3758375414
Short name T934
Test name
Test status
Simulation time 206735182 ps
CPU time 2.18 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 215212 kb
Host smart-80e57b86-e6cf-4f3e-a2ae-90affb842da9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758375414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3758375414
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3092849430
Short name T395
Test name
Test status
Simulation time 115491965 ps
CPU time 4.93 seconds
Started Apr 18 12:32:08 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 209016 kb
Host smart-8bea1d61-1a4a-4e0e-b6fe-7deae88c80f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092849430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3092849430
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.591098715
Short name T910
Test name
Test status
Simulation time 16862210 ps
CPU time 1.23 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 205832 kb
Host smart-4de93c36-05df-41e1-aa9d-f7d8c9c7e3b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591098715 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.591098715
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2741198457
Short name T931
Test name
Test status
Simulation time 50374938 ps
CPU time 0.95 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 205552 kb
Host smart-5716c7cd-c5ec-479b-aaec-44d1faeb79b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741198457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2741198457
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3072681339
Short name T917
Test name
Test status
Simulation time 43906520 ps
CPU time 0.86 seconds
Started Apr 18 12:32:41 PM PDT 24
Finished Apr 18 12:32:43 PM PDT 24
Peak memory 205500 kb
Host smart-82a25adf-0b99-4eeb-8e26-cf4ca6d623f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072681339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3072681339
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.920541151
Short name T954
Test name
Test status
Simulation time 156202275 ps
CPU time 2.32 seconds
Started Apr 18 12:32:31 PM PDT 24
Finished Apr 18 12:32:34 PM PDT 24
Peak memory 205792 kb
Host smart-e8d1fe9f-1d33-4993-b856-4f5f798ca9ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920541151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.920541151
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.171187639
Short name T1061
Test name
Test status
Simulation time 250535550 ps
CPU time 4.27 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 214636 kb
Host smart-078791a9-eb17-40cd-bdca-bfa77c371fa1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171187639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.171187639
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3553468833
Short name T966
Test name
Test status
Simulation time 2540586841 ps
CPU time 7.36 seconds
Started Apr 18 12:32:41 PM PDT 24
Finished Apr 18 12:32:49 PM PDT 24
Peak memory 220416 kb
Host smart-f1b65bd3-44ca-4bcf-b7fc-35485528f5fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553468833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3553468833
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2512819583
Short name T1022
Test name
Test status
Simulation time 220202019 ps
CPU time 2.94 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 213844 kb
Host smart-bc2b5abb-b0d9-4923-a640-b1f7e5b66ef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512819583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2512819583
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.611743832
Short name T1016
Test name
Test status
Simulation time 38122113 ps
CPU time 1.3 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:30 PM PDT 24
Peak memory 214148 kb
Host smart-30d29b9b-9cde-4fcf-a275-5cbfa780b053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611743832 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.611743832
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1270556933
Short name T1000
Test name
Test status
Simulation time 55882974 ps
CPU time 1.29 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 205856 kb
Host smart-d9b39570-126e-4e42-91c7-2f5a3a3cea7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270556933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1270556933
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2763075339
Short name T943
Test name
Test status
Simulation time 7329400 ps
CPU time 0.8 seconds
Started Apr 18 12:32:32 PM PDT 24
Finished Apr 18 12:32:34 PM PDT 24
Peak memory 205444 kb
Host smart-02178516-8d6d-4b3f-a3f3-f3a825b221bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763075339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2763075339
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2427847567
Short name T953
Test name
Test status
Simulation time 49099251 ps
CPU time 2.09 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:30 PM PDT 24
Peak memory 205796 kb
Host smart-5f394ca1-325d-464f-8a84-1361d2774f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427847567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2427847567
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.529380554
Short name T1060
Test name
Test status
Simulation time 802827078 ps
CPU time 3.03 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 214352 kb
Host smart-eecee816-ab0b-490b-8d09-fff38bb95756
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529380554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.529380554
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3490561006
Short name T1048
Test name
Test status
Simulation time 130183601 ps
CPU time 5.31 seconds
Started Apr 18 12:32:14 PM PDT 24
Finished Apr 18 12:32:25 PM PDT 24
Peak memory 214244 kb
Host smart-f4eb6e50-9873-490e-b4bf-a521d4eca99c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490561006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3490561006
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4287623095
Short name T1028
Test name
Test status
Simulation time 392888077 ps
CPU time 3.76 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 217052 kb
Host smart-5a05c778-f4b7-4dbe-8811-905917bdac15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287623095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.4287623095
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1569068260
Short name T158
Test name
Test status
Simulation time 386037964 ps
CPU time 10.52 seconds
Started Apr 18 12:32:26 PM PDT 24
Finished Apr 18 12:32:38 PM PDT 24
Peak memory 208972 kb
Host smart-1ec8f6be-cb26-401a-aff4-dacac53f8e57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569068260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1569068260
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2887059376
Short name T950
Test name
Test status
Simulation time 30577185 ps
CPU time 1.48 seconds
Started Apr 18 12:32:35 PM PDT 24
Finished Apr 18 12:32:38 PM PDT 24
Peak memory 214044 kb
Host smart-5b5c8565-6b52-4815-bcbd-1449429511bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887059376 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2887059376
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2481826042
Short name T152
Test name
Test status
Simulation time 39211504 ps
CPU time 1 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 205644 kb
Host smart-1f52971d-b3e4-4417-8769-b2fecebb2562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481826042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2481826042
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.28607675
Short name T1054
Test name
Test status
Simulation time 34416341 ps
CPU time 0.73 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 205448 kb
Host smart-2fef008c-a2f1-458d-b19b-4336dc427547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28607675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.28607675
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3617441978
Short name T147
Test name
Test status
Simulation time 1179060480 ps
CPU time 2.52 seconds
Started Apr 18 12:32:42 PM PDT 24
Finished Apr 18 12:32:46 PM PDT 24
Peak memory 205760 kb
Host smart-89560dbf-7374-48d6-ac72-018f135f1d8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617441978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3617441978
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2689185660
Short name T1045
Test name
Test status
Simulation time 164853989 ps
CPU time 4.82 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:23 PM PDT 24
Peak memory 214236 kb
Host smart-0ef18fe4-cb61-46f5-b499-a89eb30f07bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689185660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2689185660
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2425697262
Short name T924
Test name
Test status
Simulation time 90296387 ps
CPU time 2.48 seconds
Started Apr 18 12:32:31 PM PDT 24
Finished Apr 18 12:32:35 PM PDT 24
Peak memory 215056 kb
Host smart-8a83f4fa-4380-44f2-868c-f4b0768c5d2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425697262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2425697262
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.975025393
Short name T933
Test name
Test status
Simulation time 206233784 ps
CPU time 1.54 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 213964 kb
Host smart-23e8a32b-86c3-4fdb-b984-d22ce8a44c8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975025393 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.975025393
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2433175280
Short name T1025
Test name
Test status
Simulation time 25468792 ps
CPU time 0.96 seconds
Started Apr 18 12:32:30 PM PDT 24
Finished Apr 18 12:32:31 PM PDT 24
Peak memory 204976 kb
Host smart-d863d219-86fc-4937-9361-3a64785228b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433175280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2433175280
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1202901509
Short name T989
Test name
Test status
Simulation time 35943699 ps
CPU time 0.69 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 205448 kb
Host smart-6c4abc03-a8be-40a4-a625-b84e3f0bb130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202901509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1202901509
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3897590283
Short name T1070
Test name
Test status
Simulation time 45594326 ps
CPU time 1.5 seconds
Started Apr 18 12:32:17 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 205720 kb
Host smart-b9c48f48-78d6-4ce0-8ab2-1024640afdab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897590283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3897590283
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2603272998
Short name T1015
Test name
Test status
Simulation time 137786831 ps
CPU time 4.12 seconds
Started Apr 18 12:32:20 PM PDT 24
Finished Apr 18 12:32:25 PM PDT 24
Peak memory 221868 kb
Host smart-0916e0d2-a89b-4512-baa1-bd3a273179d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603272998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2603272998
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2530371116
Short name T912
Test name
Test status
Simulation time 105271086 ps
CPU time 3.41 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 213908 kb
Host smart-5b674d9b-d16d-4007-944e-16c548735732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530371116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2530371116
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3753543129
Short name T161
Test name
Test status
Simulation time 699497855 ps
CPU time 13.31 seconds
Started Apr 18 12:32:42 PM PDT 24
Finished Apr 18 12:32:56 PM PDT 24
Peak memory 214064 kb
Host smart-0c9153b4-cf3e-40bd-9120-4ab470d56522
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753543129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3753543129
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1358416715
Short name T949
Test name
Test status
Simulation time 34225364 ps
CPU time 2.35 seconds
Started Apr 18 12:32:18 PM PDT 24
Finished Apr 18 12:32:21 PM PDT 24
Peak memory 213936 kb
Host smart-e2dd22f8-a95c-4640-b675-84d6397c4664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358416715 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1358416715
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.570765099
Short name T1067
Test name
Test status
Simulation time 103051489 ps
CPU time 1.12 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:16 PM PDT 24
Peak memory 205632 kb
Host smart-197aef95-e57d-4fc7-8449-579f1871d85b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570765099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.570765099
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2430625958
Short name T1021
Test name
Test status
Simulation time 17699791 ps
CPU time 0.75 seconds
Started Apr 18 12:32:24 PM PDT 24
Finished Apr 18 12:32:25 PM PDT 24
Peak memory 205416 kb
Host smart-985809eb-2efd-4183-85f2-575e8bb9a903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430625958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2430625958
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2422093023
Short name T941
Test name
Test status
Simulation time 39204225 ps
CPU time 1.55 seconds
Started Apr 18 12:32:30 PM PDT 24
Finished Apr 18 12:32:32 PM PDT 24
Peak memory 205816 kb
Host smart-c5b74e4c-7d75-4277-8856-34fed4fa7f22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422093023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2422093023
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2488217870
Short name T118
Test name
Test status
Simulation time 87615618 ps
CPU time 2.82 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 222492 kb
Host smart-528dac5f-84cf-4a44-9b61-84b4bed3c817
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488217870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2488217870
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2815982404
Short name T1002
Test name
Test status
Simulation time 332257729 ps
CPU time 8.27 seconds
Started Apr 18 12:32:34 PM PDT 24
Finished Apr 18 12:32:44 PM PDT 24
Peak memory 214276 kb
Host smart-6dc3260d-bf5f-4f04-80a4-69826e824dcf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815982404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2815982404
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4247998433
Short name T1071
Test name
Test status
Simulation time 106454416 ps
CPU time 1.64 seconds
Started Apr 18 12:32:26 PM PDT 24
Finished Apr 18 12:32:29 PM PDT 24
Peak memory 213904 kb
Host smart-29b265bc-a841-4385-9691-863638852886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247998433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.4247998433
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1509811978
Short name T392
Test name
Test status
Simulation time 536085486 ps
CPU time 4.97 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 209496 kb
Host smart-3bea6477-e6a8-4463-97db-43f7b34e266f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509811978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1509811978
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3801540412
Short name T964
Test name
Test status
Simulation time 27232120 ps
CPU time 1.18 seconds
Started Apr 18 12:32:24 PM PDT 24
Finished Apr 18 12:32:26 PM PDT 24
Peak memory 205812 kb
Host smart-26d5b131-f1f4-4849-9c9c-9e5d718ff3a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801540412 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3801540412
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3730975461
Short name T928
Test name
Test status
Simulation time 17936422 ps
CPU time 0.9 seconds
Started Apr 18 12:32:10 PM PDT 24
Finished Apr 18 12:32:12 PM PDT 24
Peak memory 205420 kb
Host smart-a459ef84-2d6e-467c-bdd4-e1fbca01f4b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730975461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3730975461
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2118909410
Short name T918
Test name
Test status
Simulation time 10341471 ps
CPU time 0.69 seconds
Started Apr 18 12:32:33 PM PDT 24
Finished Apr 18 12:32:35 PM PDT 24
Peak memory 205336 kb
Host smart-dc8d41a3-14b4-48b6-874c-32b5370b9082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118909410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2118909410
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3199172455
Short name T1014
Test name
Test status
Simulation time 145390212 ps
CPU time 2.38 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:19 PM PDT 24
Peak memory 205748 kb
Host smart-4abe2718-44b5-4707-8749-fe73b973e894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199172455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3199172455
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.974700649
Short name T116
Test name
Test status
Simulation time 400485102 ps
CPU time 2.97 seconds
Started Apr 18 12:32:22 PM PDT 24
Finished Apr 18 12:32:26 PM PDT 24
Peak memory 214388 kb
Host smart-8612d7be-c9b5-4ec0-bcde-931449cc7930
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974700649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.974700649
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3780949843
Short name T961
Test name
Test status
Simulation time 205383607 ps
CPU time 5.19 seconds
Started Apr 18 12:33:33 PM PDT 24
Finished Apr 18 12:33:39 PM PDT 24
Peak memory 214268 kb
Host smart-d9613817-87eb-4c4a-9640-01d5b19d00a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780949843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3780949843
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1167257664
Short name T920
Test name
Test status
Simulation time 410379666 ps
CPU time 1.86 seconds
Started Apr 18 12:32:22 PM PDT 24
Finished Apr 18 12:32:25 PM PDT 24
Peak memory 213896 kb
Host smart-ff818eb4-1653-4645-9f65-534db2fa35ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167257664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1167257664
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1687841891
Short name T958
Test name
Test status
Simulation time 56503301 ps
CPU time 1.51 seconds
Started Apr 18 12:33:19 PM PDT 24
Finished Apr 18 12:33:22 PM PDT 24
Peak memory 212068 kb
Host smart-d1b0186d-9ae2-4ff4-a69d-b544866e1d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687841891 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1687841891
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3492426547
Short name T1006
Test name
Test status
Simulation time 146199513 ps
CPU time 0.88 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 205552 kb
Host smart-54219a81-bad3-493b-9055-59c192c7dc86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492426547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3492426547
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1288628002
Short name T1034
Test name
Test status
Simulation time 13675247 ps
CPU time 0.77 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:29 PM PDT 24
Peak memory 205380 kb
Host smart-a2728f68-b69c-4d2f-9e59-824eca4c3310
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288628002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1288628002
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3417223304
Short name T983
Test name
Test status
Simulation time 73618751 ps
CPU time 1.98 seconds
Started Apr 18 12:33:19 PM PDT 24
Finished Apr 18 12:33:22 PM PDT 24
Peak memory 203800 kb
Host smart-c8ed3ebc-8def-4b7c-b3cb-9dca2a4ad5a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417223304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3417223304
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1574046256
Short name T986
Test name
Test status
Simulation time 102165553 ps
CPU time 2.92 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 222400 kb
Host smart-85a2e762-1c90-41b1-a18f-8eb1c331314f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574046256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1574046256
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2760930826
Short name T1008
Test name
Test status
Simulation time 312268001 ps
CPU time 3.79 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:19 PM PDT 24
Peak memory 220240 kb
Host smart-b9b7f5dc-ea4c-40fe-948b-35bba8b99fa2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760930826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2760930826
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1817795730
Short name T945
Test name
Test status
Simulation time 25786974 ps
CPU time 1.52 seconds
Started Apr 18 12:32:33 PM PDT 24
Finished Apr 18 12:32:36 PM PDT 24
Peak memory 213440 kb
Host smart-7cae086f-39c1-417b-ad70-3a339a805edd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817795730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1817795730
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.523031503
Short name T154
Test name
Test status
Simulation time 164067413 ps
CPU time 6.06 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:19 PM PDT 24
Peak memory 209244 kb
Host smart-4f2608fe-6ae5-4d7c-998b-b616464c1443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523031503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.523031503
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1576253674
Short name T982
Test name
Test status
Simulation time 24965631 ps
CPU time 1.4 seconds
Started Apr 18 12:32:19 PM PDT 24
Finished Apr 18 12:32:21 PM PDT 24
Peak memory 214096 kb
Host smart-b994642a-2ecc-48c9-ab1e-13be1c11bc1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576253674 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1576253674
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.71825677
Short name T1066
Test name
Test status
Simulation time 149661181 ps
CPU time 1.5 seconds
Started Apr 18 12:32:16 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 205568 kb
Host smart-5153684a-43ed-4e72-9223-a8e104126987
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71825677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.71825677
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1502564279
Short name T1051
Test name
Test status
Simulation time 24584677 ps
CPU time 0.99 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 205688 kb
Host smart-5b2fa6c6-458d-459e-89ce-8b5cbeec204c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502564279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1502564279
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3992928257
Short name T1024
Test name
Test status
Simulation time 24350344 ps
CPU time 1.69 seconds
Started Apr 18 12:32:17 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 205884 kb
Host smart-f8b3d7a2-f1f9-4eff-bdd3-5fa258a39811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992928257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3992928257
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3956149392
Short name T1007
Test name
Test status
Simulation time 162618031 ps
CPU time 4.48 seconds
Started Apr 18 12:33:19 PM PDT 24
Finished Apr 18 12:33:25 PM PDT 24
Peak memory 221028 kb
Host smart-bb40540f-b3b6-42c4-ab6f-7f1f5f7e5f78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956149392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3956149392
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3671927574
Short name T120
Test name
Test status
Simulation time 293608472 ps
CPU time 8.8 seconds
Started Apr 18 12:33:37 PM PDT 24
Finished Apr 18 12:33:47 PM PDT 24
Peak memory 214268 kb
Host smart-28af2b5e-ce83-4416-b001-500015c95acd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671927574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3671927574
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.765081986
Short name T1035
Test name
Test status
Simulation time 154823392 ps
CPU time 3.02 seconds
Started Apr 18 12:33:19 PM PDT 24
Finished Apr 18 12:33:23 PM PDT 24
Peak memory 212560 kb
Host smart-250dd59c-5002-4f55-a2db-f101c941883f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765081986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.765081986
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2547076130
Short name T939
Test name
Test status
Simulation time 174671873 ps
CPU time 1.81 seconds
Started Apr 18 12:32:42 PM PDT 24
Finished Apr 18 12:32:45 PM PDT 24
Peak memory 214064 kb
Host smart-e50f3825-ee46-4812-b3a6-227b2e5fe941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547076130 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2547076130
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3141806175
Short name T987
Test name
Test status
Simulation time 44836746 ps
CPU time 1.05 seconds
Started Apr 18 12:32:39 PM PDT 24
Finished Apr 18 12:32:41 PM PDT 24
Peak memory 205612 kb
Host smart-ec4ac632-216b-4211-bffc-e28be89f01ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141806175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3141806175
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.474094751
Short name T1010
Test name
Test status
Simulation time 20622538 ps
CPU time 0.85 seconds
Started Apr 18 12:32:21 PM PDT 24
Finished Apr 18 12:32:22 PM PDT 24
Peak memory 205572 kb
Host smart-ac7c60d8-1a47-433a-9901-1c428afa6274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474094751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.474094751
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1560376853
Short name T1047
Test name
Test status
Simulation time 47965916 ps
CPU time 2.49 seconds
Started Apr 18 12:32:44 PM PDT 24
Finished Apr 18 12:32:48 PM PDT 24
Peak memory 205756 kb
Host smart-a2baf08f-95c2-43e5-b8e7-ba05d894f429
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560376853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1560376853
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3328587453
Short name T121
Test name
Test status
Simulation time 171824047 ps
CPU time 5.38 seconds
Started Apr 18 12:32:31 PM PDT 24
Finished Apr 18 12:32:36 PM PDT 24
Peak memory 214192 kb
Host smart-cd1c8873-ff11-4896-89e4-a90f5541cad2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328587453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3328587453
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3866517080
Short name T955
Test name
Test status
Simulation time 26131196 ps
CPU time 1.57 seconds
Started Apr 18 12:32:17 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 213940 kb
Host smart-c8b66f46-2fa0-4766-a25e-13f04a7768b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866517080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3866517080
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.758966694
Short name T168
Test name
Test status
Simulation time 983527744 ps
CPU time 9.85 seconds
Started Apr 18 12:32:34 PM PDT 24
Finished Apr 18 12:32:45 PM PDT 24
Peak memory 214028 kb
Host smart-5fc1a43a-6377-4650-8761-5b4755a6044b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758966694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.758966694
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1503502483
Short name T981
Test name
Test status
Simulation time 63577116 ps
CPU time 1.62 seconds
Started Apr 18 12:32:36 PM PDT 24
Finished Apr 18 12:32:39 PM PDT 24
Peak memory 213944 kb
Host smart-397174c1-4712-47cf-aef3-667d9bb4dc0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503502483 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1503502483
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3188905929
Short name T970
Test name
Test status
Simulation time 208786279 ps
CPU time 1.11 seconds
Started Apr 18 12:32:37 PM PDT 24
Finished Apr 18 12:32:39 PM PDT 24
Peak memory 205680 kb
Host smart-b1e09001-b916-448b-b326-84f7982fbe37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188905929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3188905929
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3560123495
Short name T978
Test name
Test status
Simulation time 11503543 ps
CPU time 0.86 seconds
Started Apr 18 12:32:33 PM PDT 24
Finished Apr 18 12:32:35 PM PDT 24
Peak memory 205400 kb
Host smart-f4b014fa-c29e-42dd-a7b5-9a9b5ee2df43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560123495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3560123495
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1303592357
Short name T1069
Test name
Test status
Simulation time 54466927 ps
CPU time 1.37 seconds
Started Apr 18 12:32:18 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 205632 kb
Host smart-cc86c4ee-832d-4779-a39b-cc807d269155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303592357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1303592357
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3890685591
Short name T967
Test name
Test status
Simulation time 267431064 ps
CPU time 6.5 seconds
Started Apr 18 12:32:44 PM PDT 24
Finished Apr 18 12:32:51 PM PDT 24
Peak memory 222436 kb
Host smart-26ff64bc-5b23-4073-87fd-e4ae82533c88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890685591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3890685591
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.784330507
Short name T979
Test name
Test status
Simulation time 6814001492 ps
CPU time 15.7 seconds
Started Apr 18 12:32:30 PM PDT 24
Finished Apr 18 12:32:46 PM PDT 24
Peak memory 214376 kb
Host smart-6ff0f24d-e61c-4b0f-a4d1-4f3de50f2a7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784330507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.784330507
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1288043097
Short name T1056
Test name
Test status
Simulation time 98330363 ps
CPU time 3.74 seconds
Started Apr 18 12:32:31 PM PDT 24
Finished Apr 18 12:32:36 PM PDT 24
Peak memory 213924 kb
Host smart-4c7e1226-06b8-4705-9f23-61227f52eb48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288043097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1288043097
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2302230682
Short name T1018
Test name
Test status
Simulation time 122767241 ps
CPU time 5.24 seconds
Started Apr 18 12:32:14 PM PDT 24
Finished Apr 18 12:32:21 PM PDT 24
Peak memory 209300 kb
Host smart-14626941-f6f0-4b97-8d97-2039b3116fad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302230682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2302230682
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1370325434
Short name T973
Test name
Test status
Simulation time 453606874 ps
CPU time 10.49 seconds
Started Apr 18 12:32:03 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 205700 kb
Host smart-3305ccfe-3801-4b5c-8e5b-9dffcb90ce1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370325434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
370325434
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2127741614
Short name T208
Test name
Test status
Simulation time 2439120299 ps
CPU time 14.95 seconds
Started Apr 18 12:32:07 PM PDT 24
Finished Apr 18 12:32:23 PM PDT 24
Peak memory 205844 kb
Host smart-0180f74c-188c-4692-8238-041fa3c80a14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127741614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
127741614
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1141760768
Short name T971
Test name
Test status
Simulation time 121803336 ps
CPU time 1.1 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:30 PM PDT 24
Peak memory 205728 kb
Host smart-057faeca-bd0e-4d8b-98b2-3274c2dd0ac8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141760768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
141760768
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2275270056
Short name T926
Test name
Test status
Simulation time 59514161 ps
CPU time 1.15 seconds
Started Apr 18 12:32:36 PM PDT 24
Finished Apr 18 12:32:38 PM PDT 24
Peak memory 205820 kb
Host smart-94f84d88-3bac-4b62-b102-9f716102b917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275270056 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2275270056
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1433909493
Short name T1013
Test name
Test status
Simulation time 16572840 ps
CPU time 1.24 seconds
Started Apr 18 12:32:14 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 205664 kb
Host smart-6ec9d335-af71-454d-85e4-33f311e72181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433909493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1433909493
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.288186326
Short name T1026
Test name
Test status
Simulation time 42538153 ps
CPU time 0.87 seconds
Started Apr 18 12:32:32 PM PDT 24
Finished Apr 18 12:32:34 PM PDT 24
Peak memory 205420 kb
Host smart-c494fc14-a396-4b9b-8894-d207a1007c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288186326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.288186326
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3053840745
Short name T972
Test name
Test status
Simulation time 23056062 ps
CPU time 1.62 seconds
Started Apr 18 12:31:59 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 205932 kb
Host smart-ce1f64cc-0f91-421a-a823-57755bbac872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053840745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3053840745
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2126260128
Short name T942
Test name
Test status
Simulation time 234015077 ps
CPU time 6.24 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:22 PM PDT 24
Peak memory 214224 kb
Host smart-8e321a07-81b1-40fc-b1ac-d23547a62cfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126260128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2126260128
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1475186217
Short name T115
Test name
Test status
Simulation time 287251671 ps
CPU time 3.54 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:19 PM PDT 24
Peak memory 219564 kb
Host smart-676b17de-88f1-40ea-9171-5fccb7e2f544
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475186217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1475186217
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2825133315
Short name T1064
Test name
Test status
Simulation time 430876065 ps
CPU time 3.46 seconds
Started Apr 18 12:32:04 PM PDT 24
Finished Apr 18 12:32:09 PM PDT 24
Peak memory 213944 kb
Host smart-2607f681-4358-493f-81ea-aedbe89f099d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825133315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2825133315
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.621806812
Short name T1003
Test name
Test status
Simulation time 38119430 ps
CPU time 0.68 seconds
Started Apr 18 12:32:48 PM PDT 24
Finished Apr 18 12:32:50 PM PDT 24
Peak memory 205408 kb
Host smart-8f6e8d81-e033-4c76-8d74-a8346cf0b362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621806812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.621806812
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2952088015
Short name T913
Test name
Test status
Simulation time 23136025 ps
CPU time 0.84 seconds
Started Apr 18 12:32:27 PM PDT 24
Finished Apr 18 12:32:29 PM PDT 24
Peak memory 205432 kb
Host smart-86dac67e-e674-4d9c-bb98-d862bb937d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952088015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2952088015
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2901469496
Short name T922
Test name
Test status
Simulation time 10063278 ps
CPU time 0.7 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 205432 kb
Host smart-0b1b1e19-08ee-4384-a256-0527d7d0a4a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901469496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2901469496
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2096044198
Short name T1027
Test name
Test status
Simulation time 87919717 ps
CPU time 0.87 seconds
Started Apr 18 12:32:39 PM PDT 24
Finished Apr 18 12:32:41 PM PDT 24
Peak memory 205420 kb
Host smart-62ce72ae-86f1-434b-a11a-17a91c54337f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096044198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2096044198
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1111966069
Short name T915
Test name
Test status
Simulation time 23595063 ps
CPU time 0.76 seconds
Started Apr 18 12:33:33 PM PDT 24
Finished Apr 18 12:33:35 PM PDT 24
Peak memory 205448 kb
Host smart-f40a1b5b-c374-49ca-8052-7df65f3de132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111966069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1111966069
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.103383173
Short name T1052
Test name
Test status
Simulation time 9179061 ps
CPU time 0.7 seconds
Started Apr 18 12:33:35 PM PDT 24
Finished Apr 18 12:33:36 PM PDT 24
Peak memory 205448 kb
Host smart-8da70438-1419-46b5-8c97-6c8bba7545ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103383173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.103383173
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.113846359
Short name T1020
Test name
Test status
Simulation time 60079619 ps
CPU time 0.79 seconds
Started Apr 18 12:32:41 PM PDT 24
Finished Apr 18 12:32:42 PM PDT 24
Peak memory 205404 kb
Host smart-15739054-301c-4085-9b47-ad9c366fed24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113846359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.113846359
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3604389385
Short name T977
Test name
Test status
Simulation time 40218363 ps
CPU time 0.73 seconds
Started Apr 18 12:32:35 PM PDT 24
Finished Apr 18 12:32:37 PM PDT 24
Peak memory 205416 kb
Host smart-01ca7bee-773b-468a-9f25-3a26735f66ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604389385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3604389385
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3877283273
Short name T969
Test name
Test status
Simulation time 26395795 ps
CPU time 0.71 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:32:53 PM PDT 24
Peak memory 205332 kb
Host smart-d5502c2a-68ad-4d21-b173-36153f27e864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877283273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3877283273
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2035197144
Short name T937
Test name
Test status
Simulation time 11774409 ps
CPU time 0.77 seconds
Started Apr 18 12:32:38 PM PDT 24
Finished Apr 18 12:32:40 PM PDT 24
Peak memory 205488 kb
Host smart-1f9b1641-2f1e-4c89-a813-bed274a1e990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035197144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2035197144
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2217000792
Short name T927
Test name
Test status
Simulation time 257000020 ps
CPU time 8.67 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:12 PM PDT 24
Peak memory 205800 kb
Host smart-b5652758-2123-4132-bc41-714e1ecfefa9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217000792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
217000792
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2101713418
Short name T988
Test name
Test status
Simulation time 903610518 ps
CPU time 25.56 seconds
Started Apr 18 12:31:56 PM PDT 24
Finished Apr 18 12:32:25 PM PDT 24
Peak memory 205812 kb
Host smart-e2acdc5f-8b08-4e94-9002-0f554a442a5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101713418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
101713418
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1854977079
Short name T929
Test name
Test status
Simulation time 157591114 ps
CPU time 1.09 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 205948 kb
Host smart-61d37cfd-d596-49b5-839f-55031e33f1e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854977079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
854977079
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.361322950
Short name T999
Test name
Test status
Simulation time 54416872 ps
CPU time 1.3 seconds
Started Apr 18 12:32:34 PM PDT 24
Finished Apr 18 12:32:37 PM PDT 24
Peak memory 214024 kb
Host smart-7acd51e4-5d8d-46d8-a9f0-8f8772a1f74a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361322950 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.361322950
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1122891715
Short name T1065
Test name
Test status
Simulation time 24698722 ps
CPU time 1.4 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:01 PM PDT 24
Peak memory 205740 kb
Host smart-f40e938b-2609-482f-9e29-69ef1c43976b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122891715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1122891715
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2785896421
Short name T908
Test name
Test status
Simulation time 28230375 ps
CPU time 0.86 seconds
Started Apr 18 12:32:00 PM PDT 24
Finished Apr 18 12:32:04 PM PDT 24
Peak memory 205520 kb
Host smart-705b67b0-c4fd-4f12-b324-0392b9b674da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785896421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2785896421
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.976699026
Short name T1074
Test name
Test status
Simulation time 124174064 ps
CPU time 2.62 seconds
Started Apr 18 12:31:57 PM PDT 24
Finished Apr 18 12:32:02 PM PDT 24
Peak memory 205768 kb
Host smart-4a197958-063d-490a-aea2-d9599162b7c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976699026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.976699026
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3920543291
Short name T1001
Test name
Test status
Simulation time 654657855 ps
CPU time 16.9 seconds
Started Apr 18 12:32:07 PM PDT 24
Finished Apr 18 12:32:25 PM PDT 24
Peak memory 222340 kb
Host smart-42051f1e-88ef-40d1-83ca-88a77fdddf9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920543291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3920543291
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1582992487
Short name T994
Test name
Test status
Simulation time 203251741 ps
CPU time 6.41 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:22 PM PDT 24
Peak memory 214172 kb
Host smart-74400071-294b-4e11-9d4d-faa5d2f015b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582992487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1582992487
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1823537786
Short name T914
Test name
Test status
Simulation time 106922353 ps
CPU time 3.32 seconds
Started Apr 18 12:32:09 PM PDT 24
Finished Apr 18 12:32:13 PM PDT 24
Peak memory 213868 kb
Host smart-e628a1fc-efe3-4f69-bf11-f2878d8e9d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823537786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1823537786
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2697284473
Short name T952
Test name
Test status
Simulation time 35324734 ps
CPU time 0.69 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:35 PM PDT 24
Peak memory 205356 kb
Host smart-f51477e1-e4ab-44c6-8cf8-c5d8310655ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697284473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2697284473
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2094311359
Short name T957
Test name
Test status
Simulation time 38128810 ps
CPU time 0.7 seconds
Started Apr 18 12:32:45 PM PDT 24
Finished Apr 18 12:32:47 PM PDT 24
Peak memory 205416 kb
Host smart-08f41aaf-8210-4bbe-939e-4e04837ddf8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094311359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2094311359
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2749076564
Short name T951
Test name
Test status
Simulation time 24563397 ps
CPU time 0.74 seconds
Started Apr 18 12:32:36 PM PDT 24
Finished Apr 18 12:32:38 PM PDT 24
Peak memory 205308 kb
Host smart-29237e6d-847a-4408-b9ee-eda09bcf6fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749076564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2749076564
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1810044404
Short name T1068
Test name
Test status
Simulation time 11187311 ps
CPU time 0.72 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:35 PM PDT 24
Peak memory 205432 kb
Host smart-2016405a-9714-41d1-a2eb-5913ba243ef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810044404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1810044404
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1057238915
Short name T985
Test name
Test status
Simulation time 7564733 ps
CPU time 0.77 seconds
Started Apr 18 12:32:44 PM PDT 24
Finished Apr 18 12:32:46 PM PDT 24
Peak memory 205352 kb
Host smart-b4dd226c-6c96-4d17-9739-f9087aaa7ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057238915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1057238915
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.267387800
Short name T1053
Test name
Test status
Simulation time 46336149 ps
CPU time 0.73 seconds
Started Apr 18 12:32:50 PM PDT 24
Finished Apr 18 12:32:53 PM PDT 24
Peak memory 205460 kb
Host smart-ca5cbae9-98b1-4582-bff8-34421cbd0e4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267387800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.267387800
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1703381007
Short name T932
Test name
Test status
Simulation time 8247666 ps
CPU time 0.78 seconds
Started Apr 18 12:32:39 PM PDT 24
Finished Apr 18 12:32:40 PM PDT 24
Peak memory 205428 kb
Host smart-46b1efc0-0ac2-42f5-9a4c-aed310533593
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703381007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1703381007
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.342529329
Short name T916
Test name
Test status
Simulation time 40651743 ps
CPU time 0.8 seconds
Started Apr 18 12:32:59 PM PDT 24
Finished Apr 18 12:33:00 PM PDT 24
Peak memory 205308 kb
Host smart-4bcd2d3d-d366-4986-a57b-50b0d65779c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342529329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.342529329
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.168804140
Short name T1058
Test name
Test status
Simulation time 80069573 ps
CPU time 0.74 seconds
Started Apr 18 12:32:35 PM PDT 24
Finished Apr 18 12:32:38 PM PDT 24
Peak memory 205468 kb
Host smart-3f6aa6e9-9535-40fc-8c6e-60f3594610af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168804140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.168804140
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3845574681
Short name T956
Test name
Test status
Simulation time 38467718 ps
CPU time 0.8 seconds
Started Apr 18 12:32:27 PM PDT 24
Finished Apr 18 12:32:28 PM PDT 24
Peak memory 205472 kb
Host smart-2cec4f42-f07a-4e9d-bc52-77f16f1502d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845574681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3845574681
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3707241247
Short name T1004
Test name
Test status
Simulation time 935557590 ps
CPU time 8.94 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:21 PM PDT 24
Peak memory 205608 kb
Host smart-09e782b9-4ce9-4404-90db-0409a834b78a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707241247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
707241247
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3505232103
Short name T1031
Test name
Test status
Simulation time 3605203424 ps
CPU time 16.06 seconds
Started Apr 18 12:32:36 PM PDT 24
Finished Apr 18 12:32:54 PM PDT 24
Peak memory 205872 kb
Host smart-d7f7fd9c-c5c5-4467-ba30-5ba0437a4ae5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505232103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
505232103
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1643570055
Short name T944
Test name
Test status
Simulation time 18391366 ps
CPU time 1.03 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 205664 kb
Host smart-e01a63cd-0003-4212-9320-587dfd2ef05e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643570055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
643570055
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4272463567
Short name T968
Test name
Test status
Simulation time 77861496 ps
CPU time 1.07 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:16 PM PDT 24
Peak memory 205828 kb
Host smart-c4f1136c-900d-41a4-b73d-29496f31bad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272463567 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4272463567
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1553368247
Short name T980
Test name
Test status
Simulation time 192171875 ps
CPU time 1.17 seconds
Started Apr 18 12:32:33 PM PDT 24
Finished Apr 18 12:32:36 PM PDT 24
Peak memory 205828 kb
Host smart-3debc79b-2956-4374-8e04-a7a225413919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553368247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1553368247
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1173747739
Short name T909
Test name
Test status
Simulation time 10467601 ps
CPU time 0.74 seconds
Started Apr 18 12:32:35 PM PDT 24
Finished Apr 18 12:32:37 PM PDT 24
Peak memory 205388 kb
Host smart-a3fb6fb3-cdf4-47f8-90d0-818e6ab5ff0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173747739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1173747739
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2708438683
Short name T1033
Test name
Test status
Simulation time 657874532 ps
CPU time 2.07 seconds
Started Apr 18 12:32:42 PM PDT 24
Finished Apr 18 12:32:45 PM PDT 24
Peak memory 205688 kb
Host smart-4f1d1a2b-71f2-42c3-8c02-c71c76656e67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708438683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2708438683
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2520531120
Short name T122
Test name
Test status
Simulation time 916604483 ps
CPU time 3.02 seconds
Started Apr 18 12:32:43 PM PDT 24
Finished Apr 18 12:32:47 PM PDT 24
Peak memory 214228 kb
Host smart-6b3abceb-934a-4ba5-9d3a-17ca487bc54c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520531120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2520531120
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3749937321
Short name T1050
Test name
Test status
Simulation time 341496414 ps
CPU time 6.97 seconds
Started Apr 18 12:32:32 PM PDT 24
Finished Apr 18 12:32:40 PM PDT 24
Peak memory 214268 kb
Host smart-78fdd3d5-7564-4bec-9123-843aecfabc39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749937321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3749937321
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3737165599
Short name T991
Test name
Test status
Simulation time 85464770 ps
CPU time 1.85 seconds
Started Apr 18 12:32:14 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 214100 kb
Host smart-60d4450b-7119-4c30-872b-8da91fdba48f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737165599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3737165599
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2405649049
Short name T1037
Test name
Test status
Simulation time 18521533 ps
CPU time 0.71 seconds
Started Apr 18 12:32:40 PM PDT 24
Finished Apr 18 12:32:42 PM PDT 24
Peak memory 205308 kb
Host smart-6a1270f3-522b-40d0-b4b5-bd90b280e285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405649049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2405649049
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1051749112
Short name T959
Test name
Test status
Simulation time 11068798 ps
CPU time 0.75 seconds
Started Apr 18 12:32:45 PM PDT 24
Finished Apr 18 12:32:47 PM PDT 24
Peak memory 205428 kb
Host smart-ff4e087a-0fba-4744-a321-415da94d68b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051749112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1051749112
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.287739012
Short name T925
Test name
Test status
Simulation time 10893067 ps
CPU time 0.68 seconds
Started Apr 18 12:32:44 PM PDT 24
Finished Apr 18 12:32:46 PM PDT 24
Peak memory 205492 kb
Host smart-dbf857d9-ba31-44a2-ad0c-c9b44130dcdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287739012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.287739012
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.39589354
Short name T1017
Test name
Test status
Simulation time 15910232 ps
CPU time 0.89 seconds
Started Apr 18 12:32:38 PM PDT 24
Finished Apr 18 12:32:39 PM PDT 24
Peak memory 205596 kb
Host smart-e97d04c6-3cd1-472d-aac8-9e0ee1052a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39589354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.39589354
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.775062248
Short name T1049
Test name
Test status
Simulation time 23456321 ps
CPU time 0.85 seconds
Started Apr 18 12:32:45 PM PDT 24
Finished Apr 18 12:32:47 PM PDT 24
Peak memory 205380 kb
Host smart-1326c1fc-fb00-4d19-b9cc-22a4fa48aba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775062248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.775062248
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.4028122948
Short name T984
Test name
Test status
Simulation time 9009413 ps
CPU time 0.75 seconds
Started Apr 18 12:32:36 PM PDT 24
Finished Apr 18 12:32:38 PM PDT 24
Peak memory 205488 kb
Host smart-2b58267e-4564-4774-9d24-bf54cfbefdeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028122948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4028122948
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2714859278
Short name T1072
Test name
Test status
Simulation time 42524124 ps
CPU time 0.74 seconds
Started Apr 18 12:32:34 PM PDT 24
Finished Apr 18 12:32:37 PM PDT 24
Peak memory 205448 kb
Host smart-937f07c9-629f-41f4-a700-27251325d6f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714859278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2714859278
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1292719374
Short name T946
Test name
Test status
Simulation time 91601107 ps
CPU time 0.75 seconds
Started Apr 18 12:32:40 PM PDT 24
Finished Apr 18 12:32:42 PM PDT 24
Peak memory 205416 kb
Host smart-1f9f7b9f-e77a-40a2-add6-15991b3daf2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292719374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1292719374
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2094260070
Short name T992
Test name
Test status
Simulation time 11053920 ps
CPU time 0.73 seconds
Started Apr 18 12:32:47 PM PDT 24
Finished Apr 18 12:32:50 PM PDT 24
Peak memory 205476 kb
Host smart-47bda6d4-4234-4d97-ab5b-d82870ace61e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094260070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2094260070
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.554918344
Short name T935
Test name
Test status
Simulation time 20016316 ps
CPU time 0.72 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:29 PM PDT 24
Peak memory 205380 kb
Host smart-3ace3cf5-5137-47e9-b20d-dfc3b92f4d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554918344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.554918344
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1537400712
Short name T183
Test name
Test status
Simulation time 109844305 ps
CPU time 1.15 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 205828 kb
Host smart-05c72c3c-c864-4e78-9173-b90dd21b5a42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537400712 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1537400712
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2303515182
Short name T148
Test name
Test status
Simulation time 11661740 ps
CPU time 0.91 seconds
Started Apr 18 12:32:08 PM PDT 24
Finished Apr 18 12:32:10 PM PDT 24
Peak memory 205496 kb
Host smart-ec1de9a1-03b0-48c8-8ccd-e647c691d554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303515182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2303515182
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1169447186
Short name T948
Test name
Test status
Simulation time 10579044 ps
CPU time 0.84 seconds
Started Apr 18 12:32:16 PM PDT 24
Finished Apr 18 12:32:19 PM PDT 24
Peak memory 205292 kb
Host smart-c75e6f85-9b15-4319-819c-57b6e78c6edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169447186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1169447186
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3528333086
Short name T153
Test name
Test status
Simulation time 72641124 ps
CPU time 2.58 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 205844 kb
Host smart-f4dbe3a8-35fc-42fc-804c-4d400ad9ae9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528333086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3528333086
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2413792559
Short name T997
Test name
Test status
Simulation time 964183864 ps
CPU time 4.28 seconds
Started Apr 18 12:32:31 PM PDT 24
Finished Apr 18 12:32:36 PM PDT 24
Peak memory 222340 kb
Host smart-3df2ca77-1e85-4f4f-b8bb-4d115b451352
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413792559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2413792559
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3593980777
Short name T1040
Test name
Test status
Simulation time 427933008 ps
CPU time 5.29 seconds
Started Apr 18 12:32:19 PM PDT 24
Finished Apr 18 12:32:31 PM PDT 24
Peak memory 214356 kb
Host smart-58b5ee37-f0ff-458e-855c-c06159bce734
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593980777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3593980777
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.494512170
Short name T1019
Test name
Test status
Simulation time 27601111 ps
CPU time 1.78 seconds
Started Apr 18 12:32:21 PM PDT 24
Finished Apr 18 12:32:24 PM PDT 24
Peak memory 213880 kb
Host smart-51e44f98-bb3e-497b-ab13-ff8d94d7b813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494512170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.494512170
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2680725206
Short name T911
Test name
Test status
Simulation time 372549718 ps
CPU time 3.33 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 208968 kb
Host smart-03930538-b117-463e-9103-9856fb6680a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680725206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2680725206
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1577567446
Short name T1009
Test name
Test status
Simulation time 31200233 ps
CPU time 1.96 seconds
Started Apr 18 12:32:25 PM PDT 24
Finished Apr 18 12:32:28 PM PDT 24
Peak memory 214000 kb
Host smart-a427d108-4bbb-4276-82a8-c665eda46861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577567446 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1577567446
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.960965193
Short name T923
Test name
Test status
Simulation time 22959478 ps
CPU time 1.09 seconds
Started Apr 18 12:32:16 PM PDT 24
Finished Apr 18 12:32:19 PM PDT 24
Peak memory 205804 kb
Host smart-8115407f-5e5d-4f8b-a2cb-2907d4efc467
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960965193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.960965193
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4001557553
Short name T998
Test name
Test status
Simulation time 30349823 ps
CPU time 0.68 seconds
Started Apr 18 12:32:30 PM PDT 24
Finished Apr 18 12:32:31 PM PDT 24
Peak memory 205372 kb
Host smart-c5f7eab1-4231-44d9-a108-870d461d1125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001557553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4001557553
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1843838571
Short name T960
Test name
Test status
Simulation time 445148860 ps
CPU time 2.7 seconds
Started Apr 18 12:32:31 PM PDT 24
Finished Apr 18 12:32:35 PM PDT 24
Peak memory 205696 kb
Host smart-21831185-b012-4180-90a5-a1a3fcde9fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843838571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1843838571
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2217024696
Short name T1044
Test name
Test status
Simulation time 317024055 ps
CPU time 4.92 seconds
Started Apr 18 12:32:30 PM PDT 24
Finished Apr 18 12:32:36 PM PDT 24
Peak memory 214288 kb
Host smart-c1b15af8-bd26-4a75-b5be-3ebcd80a016b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217024696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2217024696
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2884014612
Short name T1038
Test name
Test status
Simulation time 1758466843 ps
CPU time 9.96 seconds
Started Apr 18 12:32:36 PM PDT 24
Finished Apr 18 12:32:48 PM PDT 24
Peak memory 222516 kb
Host smart-0197e31a-166a-4852-acc3-9b20f3b68b9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884014612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2884014612
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4134887032
Short name T974
Test name
Test status
Simulation time 205952103 ps
CPU time 2.25 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 222104 kb
Host smart-c30c64d0-69e9-4ca1-96a0-63a1e41e8021
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134887032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4134887032
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1363719306
Short name T166
Test name
Test status
Simulation time 165102649 ps
CPU time 5.32 seconds
Started Apr 18 12:32:16 PM PDT 24
Finished Apr 18 12:32:23 PM PDT 24
Peak memory 209436 kb
Host smart-cdc90b73-c7b5-4ac9-8082-63ef7db56ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363719306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1363719306
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2670686993
Short name T962
Test name
Test status
Simulation time 40040264 ps
CPU time 1.65 seconds
Started Apr 18 12:32:33 PM PDT 24
Finished Apr 18 12:32:36 PM PDT 24
Peak memory 213952 kb
Host smart-7519cb1c-a5a9-4109-96ac-e40c56922db5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670686993 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2670686993
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2159432636
Short name T149
Test name
Test status
Simulation time 274119306 ps
CPU time 1.25 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 205768 kb
Host smart-2fa78519-0fe0-4425-b216-d06bf0fd096b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159432636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2159432636
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.479106321
Short name T930
Test name
Test status
Simulation time 43664586 ps
CPU time 0.83 seconds
Started Apr 18 12:32:14 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 205616 kb
Host smart-a255c7e1-a8bd-4591-b790-77f4635536a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479106321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.479106321
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3046015174
Short name T150
Test name
Test status
Simulation time 234246402 ps
CPU time 2.91 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:20 PM PDT 24
Peak memory 205820 kb
Host smart-894129bf-af52-4f1b-8635-f463e440e291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046015174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3046015174
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.522052152
Short name T1041
Test name
Test status
Simulation time 188774351 ps
CPU time 5.39 seconds
Started Apr 18 12:32:22 PM PDT 24
Finished Apr 18 12:32:28 PM PDT 24
Peak memory 214200 kb
Host smart-82620092-f4a1-4694-97b7-c460612853fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522052152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.522052152
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3655480399
Short name T1062
Test name
Test status
Simulation time 107325916 ps
CPU time 4.19 seconds
Started Apr 18 12:32:34 PM PDT 24
Finished Apr 18 12:32:39 PM PDT 24
Peak memory 220360 kb
Host smart-04cdd736-c7ff-47cb-aa4a-069f35be1bf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655480399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3655480399
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1748418815
Short name T990
Test name
Test status
Simulation time 234838717 ps
CPU time 3.52 seconds
Started Apr 18 12:32:25 PM PDT 24
Finished Apr 18 12:32:30 PM PDT 24
Peak memory 214020 kb
Host smart-30acd9af-b94a-415e-b23f-4adb1f1f96c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748418815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1748418815
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2370248880
Short name T163
Test name
Test status
Simulation time 100236799 ps
CPU time 5.54 seconds
Started Apr 18 12:32:13 PM PDT 24
Finished Apr 18 12:32:21 PM PDT 24
Peak memory 214008 kb
Host smart-94ae30bf-e900-41a0-a583-d2c57cb6d0f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370248880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2370248880
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1641460272
Short name T1029
Test name
Test status
Simulation time 43973482 ps
CPU time 1.41 seconds
Started Apr 18 12:32:20 PM PDT 24
Finished Apr 18 12:32:22 PM PDT 24
Peak memory 214012 kb
Host smart-4747ceb8-0deb-4fda-a126-e967791aba4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641460272 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1641460272
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1717226364
Short name T963
Test name
Test status
Simulation time 16964395 ps
CPU time 0.88 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 205484 kb
Host smart-69f36612-b551-48e9-ade1-437a2daf1230
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717226364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1717226364
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3383073558
Short name T940
Test name
Test status
Simulation time 14901764 ps
CPU time 0.73 seconds
Started Apr 18 12:32:34 PM PDT 24
Finished Apr 18 12:32:36 PM PDT 24
Peak memory 205476 kb
Host smart-a55c2630-5008-4794-9157-134bb7c2f47a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383073558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3383073558
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.931480438
Short name T1005
Test name
Test status
Simulation time 126095139 ps
CPU time 1.95 seconds
Started Apr 18 12:32:22 PM PDT 24
Finished Apr 18 12:32:24 PM PDT 24
Peak memory 214052 kb
Host smart-bf6c846c-6fac-47d8-b787-418a956e57cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931480438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.931480438
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2812302904
Short name T1011
Test name
Test status
Simulation time 205641645 ps
CPU time 3.04 seconds
Started Apr 18 12:32:12 PM PDT 24
Finished Apr 18 12:32:17 PM PDT 24
Peak memory 214140 kb
Host smart-f3ea801a-d56a-407f-b237-5d521c07cc6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812302904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2812302904
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.600858537
Short name T1036
Test name
Test status
Simulation time 92688102 ps
CPU time 4.17 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:22 PM PDT 24
Peak memory 214276 kb
Host smart-71021a01-46a4-4a42-8645-534988ff5e34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600858537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.600858537
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.23728002
Short name T938
Test name
Test status
Simulation time 180354155 ps
CPU time 1.91 seconds
Started Apr 18 12:32:32 PM PDT 24
Finished Apr 18 12:32:35 PM PDT 24
Peak memory 213988 kb
Host smart-b608072d-0803-46e0-acea-b10647e3a325
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23728002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.23728002
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2153530150
Short name T165
Test name
Test status
Simulation time 563607881 ps
CPU time 15.19 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:32 PM PDT 24
Peak memory 208960 kb
Host smart-8c4811cc-bb18-4eb3-b0bf-2d298e60a900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153530150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2153530150
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.296147648
Short name T921
Test name
Test status
Simulation time 85268660 ps
CPU time 1.55 seconds
Started Apr 18 12:32:29 PM PDT 24
Finished Apr 18 12:32:31 PM PDT 24
Peak memory 214076 kb
Host smart-3075545f-ee47-4833-be12-8a1d67346e3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296147648 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.296147648
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.529756290
Short name T1032
Test name
Test status
Simulation time 70568866 ps
CPU time 1.03 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:15 PM PDT 24
Peak memory 205628 kb
Host smart-ba0c1250-ebb3-4991-8708-a7961cdcb82f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529756290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.529756290
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1133274472
Short name T1023
Test name
Test status
Simulation time 16251821 ps
CPU time 0.72 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:30 PM PDT 24
Peak memory 205432 kb
Host smart-f72b3bd2-d901-4140-a8ca-1f13fc86c106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133274472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1133274472
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1526376492
Short name T1073
Test name
Test status
Simulation time 123191297 ps
CPU time 1.43 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:14 PM PDT 24
Peak memory 205696 kb
Host smart-f20ac87a-e96b-464a-9c41-533841d7cb1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526376492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1526376492
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3002111570
Short name T119
Test name
Test status
Simulation time 2058403658 ps
CPU time 3.27 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:16 PM PDT 24
Peak memory 222428 kb
Host smart-58f9c6f9-f5f9-486a-9697-df4136419da7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002111570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3002111570
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2891989476
Short name T1063
Test name
Test status
Simulation time 525917850 ps
CPU time 4.88 seconds
Started Apr 18 12:32:15 PM PDT 24
Finished Apr 18 12:32:22 PM PDT 24
Peak memory 214628 kb
Host smart-28e1132c-492d-4554-9b15-15f34ee9b6cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891989476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2891989476
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3982561288
Short name T1046
Test name
Test status
Simulation time 84433605 ps
CPU time 3.09 seconds
Started Apr 18 12:32:28 PM PDT 24
Finished Apr 18 12:32:32 PM PDT 24
Peak memory 213980 kb
Host smart-59fa956a-5875-493c-92ec-37c7aadc41b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982561288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3982561288
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3377985274
Short name T171
Test name
Test status
Simulation time 919502687 ps
CPU time 4.7 seconds
Started Apr 18 12:32:11 PM PDT 24
Finished Apr 18 12:32:18 PM PDT 24
Peak memory 208912 kb
Host smart-a6fc1154-499e-4fcc-b7d5-caba20063987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377985274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3377985274
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1765092658
Short name T497
Test name
Test status
Simulation time 20778829 ps
CPU time 0.89 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 206112 kb
Host smart-42514a3c-a3c0-470a-90f0-169c3b1473a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765092658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1765092658
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.196884658
Short name T821
Test name
Test status
Simulation time 495467501 ps
CPU time 3.88 seconds
Started Apr 18 12:33:53 PM PDT 24
Finished Apr 18 12:34:01 PM PDT 24
Peak memory 222896 kb
Host smart-7a9a6824-9fd1-4739-8eeb-24e15acae115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196884658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.196884658
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.53656626
Short name T68
Test name
Test status
Simulation time 382560087 ps
CPU time 2.91 seconds
Started Apr 18 12:33:55 PM PDT 24
Finished Apr 18 12:34:02 PM PDT 24
Peak memory 207440 kb
Host smart-56ef9e83-b016-4644-9854-a96b97a8b993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53656626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.53656626
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2436305571
Short name T450
Test name
Test status
Simulation time 117486329 ps
CPU time 3.23 seconds
Started Apr 18 12:33:55 PM PDT 24
Finished Apr 18 12:34:02 PM PDT 24
Peak memory 209064 kb
Host smart-9aa73dcf-1083-46e3-9191-4b51efeae13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436305571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2436305571
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.677116125
Short name T311
Test name
Test status
Simulation time 263023333 ps
CPU time 3.42 seconds
Started Apr 18 12:33:52 PM PDT 24
Finished Apr 18 12:33:59 PM PDT 24
Peak memory 208724 kb
Host smart-d1ae1585-961b-4b0e-b388-fd21ea184997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677116125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.677116125
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3799090459
Short name T904
Test name
Test status
Simulation time 133473250 ps
CPU time 6.63 seconds
Started Apr 18 12:33:53 PM PDT 24
Finished Apr 18 12:34:04 PM PDT 24
Peak memory 218460 kb
Host smart-ad6f4181-fe0d-4699-b59f-21102a2102bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799090459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3799090459
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1724654545
Short name T99
Test name
Test status
Simulation time 869549543 ps
CPU time 14.87 seconds
Started Apr 18 12:33:54 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 238764 kb
Host smart-82b62780-dd34-4af4-a097-568006c30d42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724654545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1724654545
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2309834182
Short name T587
Test name
Test status
Simulation time 26912169 ps
CPU time 1.9 seconds
Started Apr 18 12:33:52 PM PDT 24
Finished Apr 18 12:33:57 PM PDT 24
Peak memory 208556 kb
Host smart-e356f61e-9b3f-4720-a834-2002e5f58c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309834182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2309834182
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3521110461
Short name T491
Test name
Test status
Simulation time 1065234204 ps
CPU time 28.22 seconds
Started Apr 18 12:33:49 PM PDT 24
Finished Apr 18 12:34:19 PM PDT 24
Peak memory 208388 kb
Host smart-8881a6fd-d534-48ce-ae49-5b93dc8c691c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521110461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3521110461
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.772403778
Short name T468
Test name
Test status
Simulation time 36136701 ps
CPU time 2.42 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:07 PM PDT 24
Peak memory 206868 kb
Host smart-027026d0-1383-4210-bac7-0a34bc40b43e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772403778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.772403778
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3183055056
Short name T3
Test name
Test status
Simulation time 417146530 ps
CPU time 3.34 seconds
Started Apr 18 12:33:53 PM PDT 24
Finished Apr 18 12:33:59 PM PDT 24
Peak memory 214636 kb
Host smart-96f1c73b-e48e-4392-8e29-8ef09f86c4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183055056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3183055056
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.454701787
Short name T460
Test name
Test status
Simulation time 34950022 ps
CPU time 2.38 seconds
Started Apr 18 12:33:50 PM PDT 24
Finished Apr 18 12:33:56 PM PDT 24
Peak memory 208440 kb
Host smart-d21d45ab-5e23-4083-a82a-dbc0ffd5df95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454701787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.454701787
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.184148276
Short name T42
Test name
Test status
Simulation time 878016072 ps
CPU time 11.66 seconds
Started Apr 18 12:33:55 PM PDT 24
Finished Apr 18 12:34:11 PM PDT 24
Peak memory 216356 kb
Host smart-71668433-45af-4549-afef-007afabf458d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184148276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.184148276
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.417007863
Short name T902
Test name
Test status
Simulation time 84545107 ps
CPU time 4.24 seconds
Started Apr 18 12:33:54 PM PDT 24
Finished Apr 18 12:34:02 PM PDT 24
Peak memory 207768 kb
Host smart-f2b63254-da44-4fda-ac21-fd21f49dfb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417007863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.417007863
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1997204339
Short name T602
Test name
Test status
Simulation time 898556796 ps
CPU time 10.52 seconds
Started Apr 18 12:33:54 PM PDT 24
Finished Apr 18 12:34:08 PM PDT 24
Peak memory 210936 kb
Host smart-2e0f21d9-7901-4a39-8eda-eadb01fad1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997204339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1997204339
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3784896506
Short name T540
Test name
Test status
Simulation time 14791933 ps
CPU time 0.78 seconds
Started Apr 18 12:33:56 PM PDT 24
Finished Apr 18 12:34:01 PM PDT 24
Peak memory 206152 kb
Host smart-badc155f-2a0a-44f8-b4ef-f9fa2cfdea55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784896506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3784896506
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1119116799
Short name T762
Test name
Test status
Simulation time 192505741 ps
CPU time 3.56 seconds
Started Apr 18 12:34:01 PM PDT 24
Finished Apr 18 12:34:07 PM PDT 24
Peak memory 221380 kb
Host smart-f2a28c31-0d04-4b67-8103-20f1f89ed634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119116799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1119116799
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3857385122
Short name T613
Test name
Test status
Simulation time 60605479 ps
CPU time 2.83 seconds
Started Apr 18 12:33:54 PM PDT 24
Finished Apr 18 12:34:02 PM PDT 24
Peak memory 210752 kb
Host smart-704f2393-0159-4b2d-b281-d2bfd03d30d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857385122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3857385122
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.592933137
Short name T364
Test name
Test status
Simulation time 45740996 ps
CPU time 2.8 seconds
Started Apr 18 12:33:52 PM PDT 24
Finished Apr 18 12:33:58 PM PDT 24
Peak memory 209136 kb
Host smart-a9f3a37e-2b24-421e-98cf-a67e0b54c66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592933137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.592933137
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3554484274
Short name T227
Test name
Test status
Simulation time 315032164 ps
CPU time 8.25 seconds
Started Apr 18 12:33:54 PM PDT 24
Finished Apr 18 12:34:06 PM PDT 24
Peak memory 214552 kb
Host smart-299e54a5-f409-478f-ba43-ad91f720d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554484274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3554484274
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2185830567
Short name T41
Test name
Test status
Simulation time 284824427 ps
CPU time 3.6 seconds
Started Apr 18 12:33:52 PM PDT 24
Finished Apr 18 12:33:58 PM PDT 24
Peak memory 208272 kb
Host smart-6a70c56e-f817-4a95-a5dd-0d3988e21ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185830567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2185830567
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3404357893
Short name T757
Test name
Test status
Simulation time 1058792905 ps
CPU time 6.28 seconds
Started Apr 18 12:33:54 PM PDT 24
Finished Apr 18 12:34:04 PM PDT 24
Peak memory 209088 kb
Host smart-fbe26eab-327e-483a-b7a1-3192bb9b5d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404357893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3404357893
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.30786155
Short name T12
Test name
Test status
Simulation time 1266977850 ps
CPU time 21.02 seconds
Started Apr 18 12:33:55 PM PDT 24
Finished Apr 18 12:34:20 PM PDT 24
Peak memory 233444 kb
Host smart-6be967e3-0883-4953-aad6-3efbcead0cd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30786155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.30786155
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1883542855
Short name T565
Test name
Test status
Simulation time 584278395 ps
CPU time 2.36 seconds
Started Apr 18 12:33:54 PM PDT 24
Finished Apr 18 12:34:01 PM PDT 24
Peak memory 206740 kb
Host smart-dfaa3146-b573-4e3d-bce4-802d9fcc6e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883542855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1883542855
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1575478862
Short name T429
Test name
Test status
Simulation time 106785551 ps
CPU time 2.87 seconds
Started Apr 18 12:33:56 PM PDT 24
Finished Apr 18 12:34:03 PM PDT 24
Peak memory 207064 kb
Host smart-9cb7ccf9-05b8-4afa-ac90-cc4303e9c535
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575478862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1575478862
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.480670939
Short name T750
Test name
Test status
Simulation time 41672749 ps
CPU time 2.53 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:06 PM PDT 24
Peak memory 207012 kb
Host smart-7cf725b6-fc41-4fe9-b083-b2f5e3066ca2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480670939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.480670939
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1252464221
Short name T482
Test name
Test status
Simulation time 302758651 ps
CPU time 5.69 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 208068 kb
Host smart-4ff745a2-fdb7-416f-a548-b147b0215be9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252464221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1252464221
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4053165025
Short name T421
Test name
Test status
Simulation time 530235644 ps
CPU time 8.33 seconds
Started Apr 18 12:33:51 PM PDT 24
Finished Apr 18 12:34:03 PM PDT 24
Peak memory 208188 kb
Host smart-fa45838e-50e2-4f56-9fee-104a442db5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053165025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4053165025
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3595328909
Short name T604
Test name
Test status
Simulation time 1622463901 ps
CPU time 33.41 seconds
Started Apr 18 12:33:55 PM PDT 24
Finished Apr 18 12:34:32 PM PDT 24
Peak memory 208304 kb
Host smart-02285378-62eb-415c-b86a-e80a1c4ce860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595328909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3595328909
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.280482005
Short name T689
Test name
Test status
Simulation time 792652276 ps
CPU time 41.26 seconds
Started Apr 18 12:34:01 PM PDT 24
Finished Apr 18 12:34:45 PM PDT 24
Peak memory 222740 kb
Host smart-52a5b852-e7d4-4e38-8139-1f87fd0fd5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280482005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.280482005
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1979762704
Short name T760
Test name
Test status
Simulation time 365887440 ps
CPU time 10.22 seconds
Started Apr 18 12:33:55 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 220244 kb
Host smart-2d0cd4f1-6135-43aa-8829-10dd1356b4a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979762704 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1979762704
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3828128178
Short name T207
Test name
Test status
Simulation time 345567666 ps
CPU time 4.12 seconds
Started Apr 18 12:33:55 PM PDT 24
Finished Apr 18 12:34:03 PM PDT 24
Peak memory 207480 kb
Host smart-5f52db0c-fda5-49c4-90e6-99f907d65b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828128178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3828128178
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3060250031
Short name T725
Test name
Test status
Simulation time 66067036 ps
CPU time 1.46 seconds
Started Apr 18 12:33:54 PM PDT 24
Finished Apr 18 12:34:00 PM PDT 24
Peak memory 210008 kb
Host smart-8fda81b0-49e0-41d7-ad77-4f0dbb619c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060250031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3060250031
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2336579478
Short name T518
Test name
Test status
Simulation time 14153893 ps
CPU time 0.89 seconds
Started Apr 18 12:34:29 PM PDT 24
Finished Apr 18 12:34:30 PM PDT 24
Peak memory 206148 kb
Host smart-53595bb7-31c1-4a12-930d-07a0afc6b291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336579478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2336579478
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.4125878641
Short name T419
Test name
Test status
Simulation time 2199544879 ps
CPU time 9.03 seconds
Started Apr 18 12:34:25 PM PDT 24
Finished Apr 18 12:34:35 PM PDT 24
Peak memory 214820 kb
Host smart-bc237c71-06df-4dbc-9018-5cea79caaa02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125878641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.4125878641
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2284780261
Short name T334
Test name
Test status
Simulation time 541058603 ps
CPU time 16.02 seconds
Started Apr 18 12:34:26 PM PDT 24
Finished Apr 18 12:34:43 PM PDT 24
Peak memory 218384 kb
Host smart-a933d2f9-c753-4fcd-93a1-6c18c31f180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284780261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2284780261
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3372100974
Short name T756
Test name
Test status
Simulation time 320147008 ps
CPU time 4.13 seconds
Started Apr 18 12:34:33 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 208820 kb
Host smart-1cab0501-07c5-433b-b899-04ecd3ca7f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372100974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3372100974
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_random.2980949429
Short name T781
Test name
Test status
Simulation time 447006991 ps
CPU time 4.78 seconds
Started Apr 18 12:34:24 PM PDT 24
Finished Apr 18 12:34:30 PM PDT 24
Peak memory 210116 kb
Host smart-38aeb394-76c1-4eb0-a121-8276756757fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980949429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2980949429
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3083457851
Short name T492
Test name
Test status
Simulation time 98301159 ps
CPU time 2.87 seconds
Started Apr 18 12:34:31 PM PDT 24
Finished Apr 18 12:34:40 PM PDT 24
Peak memory 206956 kb
Host smart-d2fb4341-6191-4fc2-914f-8b1d3eaeecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083457851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3083457851
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3466413534
Short name T490
Test name
Test status
Simulation time 3882043400 ps
CPU time 9.68 seconds
Started Apr 18 12:34:26 PM PDT 24
Finished Apr 18 12:34:37 PM PDT 24
Peak memory 208772 kb
Host smart-5b33be88-758f-4d69-9d96-c606050c9a51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466413534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3466413534
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3743986153
Short name T333
Test name
Test status
Simulation time 354401941 ps
CPU time 3.54 seconds
Started Apr 18 12:34:32 PM PDT 24
Finished Apr 18 12:34:36 PM PDT 24
Peak memory 207156 kb
Host smart-31dc744b-daeb-4fb6-acbd-723b1ba25c2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743986153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3743986153
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3840301146
Short name T721
Test name
Test status
Simulation time 576062038 ps
CPU time 3.08 seconds
Started Apr 18 12:34:23 PM PDT 24
Finished Apr 18 12:34:27 PM PDT 24
Peak memory 207164 kb
Host smart-2cd13eea-5b6b-447f-9053-469a28674ac4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840301146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3840301146
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3213089597
Short name T774
Test name
Test status
Simulation time 594629784 ps
CPU time 4.25 seconds
Started Apr 18 12:34:31 PM PDT 24
Finished Apr 18 12:34:36 PM PDT 24
Peak memory 209876 kb
Host smart-b8a28800-dff8-4250-ac4e-1af52708b0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213089597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3213089597
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.4126042480
Short name T466
Test name
Test status
Simulation time 448287039 ps
CPU time 3.58 seconds
Started Apr 18 12:34:29 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 208576 kb
Host smart-5cd33f81-176e-462a-a362-a672e591748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126042480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.4126042480
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3400956332
Short name T577
Test name
Test status
Simulation time 251842462 ps
CPU time 3.48 seconds
Started Apr 18 12:34:26 PM PDT 24
Finished Apr 18 12:34:30 PM PDT 24
Peak memory 209176 kb
Host smart-9eeb53ee-5037-4db5-9678-4799a293ee22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400956332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3400956332
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3591794584
Short name T790
Test name
Test status
Simulation time 17681004 ps
CPU time 0.7 seconds
Started Apr 18 12:34:51 PM PDT 24
Finished Apr 18 12:34:52 PM PDT 24
Peak memory 206264 kb
Host smart-36b60bf5-a03c-4ead-a59e-d484dd44af8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591794584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3591794584
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.540672892
Short name T30
Test name
Test status
Simulation time 3668979618 ps
CPU time 38.14 seconds
Started Apr 18 12:34:36 PM PDT 24
Finished Apr 18 12:35:15 PM PDT 24
Peak memory 223060 kb
Host smart-9dc8b3ee-a2d0-435c-b04f-e7d733292c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540672892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.540672892
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1193267436
Short name T445
Test name
Test status
Simulation time 152062790 ps
CPU time 1.97 seconds
Started Apr 18 12:34:31 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 209504 kb
Host smart-990d1362-c09f-4360-9e02-17615bd3ee7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193267436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1193267436
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2946165256
Short name T782
Test name
Test status
Simulation time 5531816244 ps
CPU time 27.95 seconds
Started Apr 18 12:34:28 PM PDT 24
Finished Apr 18 12:34:56 PM PDT 24
Peak memory 222700 kb
Host smart-390bf55f-9bf5-4e1d-afce-1007a7599dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946165256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2946165256
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2377254407
Short name T743
Test name
Test status
Simulation time 231340561 ps
CPU time 4.01 seconds
Started Apr 18 12:34:30 PM PDT 24
Finished Apr 18 12:34:35 PM PDT 24
Peak memory 209796 kb
Host smart-263bad8d-02ae-4327-bb22-053271b23f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377254407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2377254407
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.148438379
Short name T767
Test name
Test status
Simulation time 65187311 ps
CPU time 2.52 seconds
Started Apr 18 12:34:30 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 208020 kb
Host smart-0f6acdaf-a44b-458a-ab6b-325611c3264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148438379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.148438379
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2537631399
Short name T529
Test name
Test status
Simulation time 31706815 ps
CPU time 2.33 seconds
Started Apr 18 12:34:30 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 206940 kb
Host smart-88fed195-bc69-459b-af37-e67fba3ac353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537631399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2537631399
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.484777379
Short name T459
Test name
Test status
Simulation time 70848271 ps
CPU time 3.44 seconds
Started Apr 18 12:34:30 PM PDT 24
Finished Apr 18 12:34:34 PM PDT 24
Peak memory 208800 kb
Host smart-1d9c7a0a-ae2e-47f8-ab86-89705b23854a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484777379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.484777379
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2364934606
Short name T784
Test name
Test status
Simulation time 10562677168 ps
CPU time 25.6 seconds
Started Apr 18 12:34:28 PM PDT 24
Finished Apr 18 12:34:55 PM PDT 24
Peak memory 208664 kb
Host smart-0e1f58db-4c15-4095-8541-77a11b077cc0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364934606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2364934606
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2852814979
Short name T72
Test name
Test status
Simulation time 44163551 ps
CPU time 2.62 seconds
Started Apr 18 12:34:32 PM PDT 24
Finished Apr 18 12:34:35 PM PDT 24
Peak memory 208776 kb
Host smart-7c8646f7-186b-4940-8be2-5772dc2fe8c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852814979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2852814979
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1349167910
Short name T270
Test name
Test status
Simulation time 79803305 ps
CPU time 3.47 seconds
Started Apr 18 12:34:34 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 210140 kb
Host smart-521d3b8b-9387-471e-8db6-513ce77d8710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349167910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1349167910
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1643151933
Short name T641
Test name
Test status
Simulation time 59024874 ps
CPU time 2.22 seconds
Started Apr 18 12:34:30 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 207344 kb
Host smart-8437354f-4224-48b3-84e9-c13054cf8258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643151933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1643151933
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1610445432
Short name T197
Test name
Test status
Simulation time 2836708962 ps
CPU time 17.6 seconds
Started Apr 18 12:34:35 PM PDT 24
Finished Apr 18 12:34:54 PM PDT 24
Peak memory 220264 kb
Host smart-447a0d32-98e1-408f-9380-c66157cc2dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610445432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1610445432
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2161629293
Short name T799
Test name
Test status
Simulation time 123547747 ps
CPU time 3.76 seconds
Started Apr 18 12:34:32 PM PDT 24
Finished Apr 18 12:34:36 PM PDT 24
Peak memory 218600 kb
Host smart-493694c0-eb94-4f97-b9ea-a37b071d53ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161629293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2161629293
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3511661786
Short name T798
Test name
Test status
Simulation time 15572670 ps
CPU time 0.96 seconds
Started Apr 18 12:34:39 PM PDT 24
Finished Apr 18 12:34:41 PM PDT 24
Peak memory 206416 kb
Host smart-5b1f58ff-b55d-4b1f-a0e4-9df3deded927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511661786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3511661786
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.707435457
Short name T352
Test name
Test status
Simulation time 223325108 ps
CPU time 3.63 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:51 PM PDT 24
Peak memory 215492 kb
Host smart-cc2206f8-5eb2-407c-8f91-ca8a5895faff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707435457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.707435457
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1707725080
Short name T595
Test name
Test status
Simulation time 331949309 ps
CPU time 2.68 seconds
Started Apr 18 12:34:36 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 217204 kb
Host smart-6e220051-ef99-4b86-8c19-be9ce08ea206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707725080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1707725080
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2919977687
Short name T58
Test name
Test status
Simulation time 98791723 ps
CPU time 2.48 seconds
Started Apr 18 12:34:38 PM PDT 24
Finished Apr 18 12:34:42 PM PDT 24
Peak memory 215764 kb
Host smart-8a604e8c-03f8-438c-86bc-19f680f713de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919977687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2919977687
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3465542441
Short name T84
Test name
Test status
Simulation time 126157153 ps
CPU time 3.83 seconds
Started Apr 18 12:34:34 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 217280 kb
Host smart-6dfd46fa-2062-4cab-bbba-c392a323df95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465542441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3465542441
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.700545637
Short name T793
Test name
Test status
Simulation time 89759869 ps
CPU time 3.26 seconds
Started Apr 18 12:34:36 PM PDT 24
Finished Apr 18 12:34:40 PM PDT 24
Peak memory 208792 kb
Host smart-45672e2d-a7d4-4849-91b7-b63f6997d270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700545637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.700545637
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3482832119
Short name T628
Test name
Test status
Simulation time 396292703 ps
CPU time 6.3 seconds
Started Apr 18 12:34:34 PM PDT 24
Finished Apr 18 12:34:40 PM PDT 24
Peak memory 208800 kb
Host smart-565b88da-638b-4cb7-b045-130b54caad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482832119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3482832119
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.585446255
Short name T731
Test name
Test status
Simulation time 9999112263 ps
CPU time 45.42 seconds
Started Apr 18 12:34:36 PM PDT 24
Finished Apr 18 12:35:22 PM PDT 24
Peak memory 209224 kb
Host smart-fd5be5bc-68d2-456b-881a-9ae832abb3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585446255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.585446255
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3559044737
Short name T18
Test name
Test status
Simulation time 122568934 ps
CPU time 4.69 seconds
Started Apr 18 12:34:37 PM PDT 24
Finished Apr 18 12:34:43 PM PDT 24
Peak memory 208388 kb
Host smart-d73f7a88-334b-4bf2-9158-1fe0e04331d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559044737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3559044737
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2105416852
Short name T405
Test name
Test status
Simulation time 86758804 ps
CPU time 1.8 seconds
Started Apr 18 12:34:37 PM PDT 24
Finished Apr 18 12:34:40 PM PDT 24
Peak memory 207016 kb
Host smart-5436c9eb-ff13-43c8-adac-95e5fc967c8b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105416852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2105416852
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3528447413
Short name T309
Test name
Test status
Simulation time 165384170 ps
CPU time 5.2 seconds
Started Apr 18 12:34:36 PM PDT 24
Finished Apr 18 12:34:42 PM PDT 24
Peak memory 208460 kb
Host smart-f9925a60-7f28-43da-af4c-5fcaca0a89cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528447413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3528447413
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.410386151
Short name T523
Test name
Test status
Simulation time 319439623 ps
CPU time 8.05 seconds
Started Apr 18 12:34:40 PM PDT 24
Finished Apr 18 12:34:49 PM PDT 24
Peak memory 214556 kb
Host smart-a4a6cc1f-e5ae-4cf2-a290-240b01b35a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410386151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.410386151
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2577760187
Short name T776
Test name
Test status
Simulation time 42821637 ps
CPU time 1.84 seconds
Started Apr 18 12:34:35 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 208680 kb
Host smart-93f6381c-6b04-4dfb-b954-c901c0fa2da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577760187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2577760187
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2815603177
Short name T97
Test name
Test status
Simulation time 1665742022 ps
CPU time 5.11 seconds
Started Apr 18 12:34:40 PM PDT 24
Finished Apr 18 12:34:46 PM PDT 24
Peak memory 219204 kb
Host smart-0c278631-9b41-4bb8-bbb2-c11da0b37526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815603177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2815603177
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2671896547
Short name T758
Test name
Test status
Simulation time 101505507 ps
CPU time 4.72 seconds
Started Apr 18 12:34:35 PM PDT 24
Finished Apr 18 12:34:41 PM PDT 24
Peak memory 207912 kb
Host smart-a0ce579e-447c-4d1f-a3ed-a5e6dbcd7c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671896547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2671896547
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4221965418
Short name T228
Test name
Test status
Simulation time 110081186 ps
CPU time 6.2 seconds
Started Apr 18 12:34:36 PM PDT 24
Finished Apr 18 12:34:43 PM PDT 24
Peak memory 214764 kb
Host smart-a17abf95-c91b-4e87-8dfd-4385e553bf1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221965418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4221965418
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2369880270
Short name T795
Test name
Test status
Simulation time 69303164 ps
CPU time 2.44 seconds
Started Apr 18 12:34:41 PM PDT 24
Finished Apr 18 12:34:44 PM PDT 24
Peak memory 210192 kb
Host smart-57e0fc34-46e4-49ab-a188-5608f0022450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369880270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2369880270
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.758669429
Short name T835
Test name
Test status
Simulation time 149408338 ps
CPU time 3.09 seconds
Started Apr 18 12:34:41 PM PDT 24
Finished Apr 18 12:34:45 PM PDT 24
Peak memory 209284 kb
Host smart-3b76df83-5540-47d2-a4ca-ac275ca63b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758669429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.758669429
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3220259915
Short name T302
Test name
Test status
Simulation time 277081326 ps
CPU time 10.02 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 209992 kb
Host smart-cc6a48b4-b7c1-47ce-befa-afb6247fc6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220259915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3220259915
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.2340246686
Short name T804
Test name
Test status
Simulation time 139920522 ps
CPU time 4.27 seconds
Started Apr 18 12:34:36 PM PDT 24
Finished Apr 18 12:34:41 PM PDT 24
Peak memory 214516 kb
Host smart-09b4c1e9-453b-43ca-899f-a413ef1f687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340246686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2340246686
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1056204606
Short name T849
Test name
Test status
Simulation time 191393354 ps
CPU time 2.42 seconds
Started Apr 18 12:34:39 PM PDT 24
Finished Apr 18 12:34:43 PM PDT 24
Peak memory 207084 kb
Host smart-754636ee-3a21-4725-9ffa-44f8bb709fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056204606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1056204606
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.608943595
Short name T837
Test name
Test status
Simulation time 442701743 ps
CPU time 3.53 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:51 PM PDT 24
Peak memory 206976 kb
Host smart-8cd3f2ae-613a-4744-8036-efd9a3979f8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608943595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.608943595
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3962592311
Short name T855
Test name
Test status
Simulation time 96070373 ps
CPU time 2.08 seconds
Started Apr 18 12:34:40 PM PDT 24
Finished Apr 18 12:34:43 PM PDT 24
Peak memory 208624 kb
Host smart-2211632d-4611-49be-b0a3-68b5ab25c756
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962592311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3962592311
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1844313311
Short name T716
Test name
Test status
Simulation time 296134335 ps
CPU time 2.27 seconds
Started Apr 18 12:34:37 PM PDT 24
Finished Apr 18 12:34:40 PM PDT 24
Peak memory 207076 kb
Host smart-5da7f0c5-94e6-45dd-974f-fe5ec0b1a5a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844313311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1844313311
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.614401837
Short name T104
Test name
Test status
Simulation time 147862679 ps
CPU time 2.56 seconds
Started Apr 18 12:34:43 PM PDT 24
Finished Apr 18 12:34:47 PM PDT 24
Peak memory 210204 kb
Host smart-6b20a775-8460-47ab-a3b2-9995c0bbd9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614401837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.614401837
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3826390411
Short name T787
Test name
Test status
Simulation time 80084992 ps
CPU time 2.93 seconds
Started Apr 18 12:34:38 PM PDT 24
Finished Apr 18 12:34:42 PM PDT 24
Peak memory 208588 kb
Host smart-a60ee1cb-61fb-48fd-921c-e89f01e04597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826390411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3826390411
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1118752015
Short name T196
Test name
Test status
Simulation time 1467959583 ps
CPU time 33.25 seconds
Started Apr 18 12:34:44 PM PDT 24
Finished Apr 18 12:35:18 PM PDT 24
Peak memory 215848 kb
Host smart-c61b1370-3c10-4e5e-ba2f-bb31afd6c367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118752015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1118752015
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.4178822560
Short name T125
Test name
Test status
Simulation time 504916903 ps
CPU time 8.88 seconds
Started Apr 18 12:34:45 PM PDT 24
Finished Apr 18 12:34:55 PM PDT 24
Peak memory 223000 kb
Host smart-ee5459d1-089f-49d6-b36b-4d9282786d0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178822560 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.4178822560
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.555780264
Short name T446
Test name
Test status
Simulation time 869434905 ps
CPU time 9.31 seconds
Started Apr 18 12:34:48 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 214508 kb
Host smart-6b13a3c0-ffed-488b-88cf-15938625b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555780264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.555780264
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3362407659
Short name T138
Test name
Test status
Simulation time 56549525 ps
CPU time 2.61 seconds
Started Apr 18 12:34:51 PM PDT 24
Finished Apr 18 12:34:54 PM PDT 24
Peak memory 210056 kb
Host smart-63756813-b820-4004-b8b7-e551e1ad4483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362407659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3362407659
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1239610704
Short name T493
Test name
Test status
Simulation time 10941393 ps
CPU time 0.81 seconds
Started Apr 18 12:34:45 PM PDT 24
Finished Apr 18 12:34:47 PM PDT 24
Peak memory 206184 kb
Host smart-62c3f6b6-591b-4872-a118-e1c5bb58b313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239610704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1239610704
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1753189406
Short name T212
Test name
Test status
Simulation time 344931939 ps
CPU time 5.3 seconds
Started Apr 18 12:34:51 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 215480 kb
Host smart-0f6ab193-8d37-4cff-9dca-474b1cffa4a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1753189406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1753189406
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2021154066
Short name T723
Test name
Test status
Simulation time 52114393 ps
CPU time 2 seconds
Started Apr 18 12:34:56 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 207220 kb
Host smart-158736d9-e3dc-4407-bf73-5e462b1f8bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021154066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2021154066
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1183054691
Short name T308
Test name
Test status
Simulation time 812921970 ps
CPU time 8.91 seconds
Started Apr 18 12:34:42 PM PDT 24
Finished Apr 18 12:34:52 PM PDT 24
Peak memory 209652 kb
Host smart-7b3b8fc6-55bb-43db-8dec-3fcba3056fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183054691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1183054691
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2945731314
Short name T373
Test name
Test status
Simulation time 1011609094 ps
CPU time 31.74 seconds
Started Apr 18 12:34:43 PM PDT 24
Finished Apr 18 12:35:15 PM PDT 24
Peak memory 217140 kb
Host smart-976ca7c0-7b53-419b-8b5f-e36b5d7930b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945731314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2945731314
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_random.2004846486
Short name T873
Test name
Test status
Simulation time 835201431 ps
CPU time 21.02 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:19 PM PDT 24
Peak memory 209144 kb
Host smart-0b5dd9e0-9867-486a-b752-1d5dacb1c6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004846486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2004846486
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3137192450
Short name T386
Test name
Test status
Simulation time 177373318 ps
CPU time 2.6 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 208384 kb
Host smart-c32d3ed0-02cd-411f-8118-53098bc8b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137192450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3137192450
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1636346542
Short name T834
Test name
Test status
Simulation time 189406521 ps
CPU time 3.5 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:51 PM PDT 24
Peak memory 208848 kb
Host smart-5d519440-5aa8-46c4-b0ff-880e7fbbb1a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636346542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1636346542
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.697932093
Short name T665
Test name
Test status
Simulation time 2841601347 ps
CPU time 31.83 seconds
Started Apr 18 12:34:42 PM PDT 24
Finished Apr 18 12:35:15 PM PDT 24
Peak memory 208268 kb
Host smart-3ba18dae-13f7-4561-b41e-5be1a89e7521
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697932093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.697932093
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2717293473
Short name T702
Test name
Test status
Simulation time 205685068 ps
CPU time 5.28 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:38 PM PDT 24
Peak memory 208388 kb
Host smart-4bfb2fd0-25ea-4cf9-8a35-9a5779c8313d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717293473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2717293473
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1365322690
Short name T693
Test name
Test status
Simulation time 598759744 ps
CPU time 4.23 seconds
Started Apr 18 12:34:43 PM PDT 24
Finished Apr 18 12:34:49 PM PDT 24
Peak memory 209056 kb
Host smart-3cdf0227-1d1f-4155-9e87-82ea86ce534b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365322690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1365322690
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.23575541
Short name T606
Test name
Test status
Simulation time 334374344 ps
CPU time 4.98 seconds
Started Apr 18 12:34:39 PM PDT 24
Finished Apr 18 12:34:45 PM PDT 24
Peak memory 208860 kb
Host smart-bb014f6e-bc7d-4b7a-998e-155da21ac11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23575541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.23575541
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3121397525
Short name T707
Test name
Test status
Simulation time 16794363798 ps
CPU time 184.53 seconds
Started Apr 18 12:34:39 PM PDT 24
Finished Apr 18 12:37:45 PM PDT 24
Peak memory 217232 kb
Host smart-08b19fbc-a03e-4c99-8510-132c15dc9c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121397525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3121397525
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2579544567
Short name T45
Test name
Test status
Simulation time 1311611962 ps
CPU time 10.87 seconds
Started Apr 18 12:35:03 PM PDT 24
Finished Apr 18 12:35:15 PM PDT 24
Peak memory 222892 kb
Host smart-dee576de-64d4-4aa3-baa3-8276e6e5b77c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579544567 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2579544567
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3921833159
Short name T637
Test name
Test status
Simulation time 219423929 ps
CPU time 4.91 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 210688 kb
Host smart-d946d5ba-8bb0-49d3-b149-efefd4aa48a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921833159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3921833159
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3113859940
Short name T59
Test name
Test status
Simulation time 1088895759 ps
CPU time 24.22 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:35:18 PM PDT 24
Peak memory 222612 kb
Host smart-2395f3c1-a591-4917-8dc2-47e17f9df1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113859940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3113859940
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1044003688
Short name T886
Test name
Test status
Simulation time 74795759 ps
CPU time 0.81 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:55 PM PDT 24
Peak memory 206160 kb
Host smart-74c1d8a2-530b-4a8e-9147-52ecd8277a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044003688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1044003688
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.550317605
Short name T388
Test name
Test status
Simulation time 908198990 ps
CPU time 12.48 seconds
Started Apr 18 12:34:44 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 214948 kb
Host smart-2deb150b-5eb1-44a2-af9d-eb239fb825f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550317605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.550317605
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4123103639
Short name T398
Test name
Test status
Simulation time 214523418 ps
CPU time 3.03 seconds
Started Apr 18 12:34:41 PM PDT 24
Finished Apr 18 12:34:45 PM PDT 24
Peak memory 214820 kb
Host smart-5764ec45-d7d0-4dd4-981d-33bc8c4a7857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123103639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4123103639
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1044542718
Short name T735
Test name
Test status
Simulation time 127452025 ps
CPU time 2.06 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 209612 kb
Host smart-5e0ba36e-8135-421d-a31d-607f8a99c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044542718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1044542718
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.4053646984
Short name T797
Test name
Test status
Simulation time 225801646 ps
CPU time 5.37 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 220176 kb
Host smart-3fea71a1-a27f-4710-8655-a7c22486003f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053646984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.4053646984
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2526175884
Short name T229
Test name
Test status
Simulation time 268129484 ps
CPU time 9.6 seconds
Started Apr 18 12:34:45 PM PDT 24
Finished Apr 18 12:34:56 PM PDT 24
Peak memory 222824 kb
Host smart-06756602-7b8d-470a-acaf-9e8f672d7fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526175884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2526175884
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3194549726
Short name T879
Test name
Test status
Simulation time 316178011 ps
CPU time 4.46 seconds
Started Apr 18 12:34:40 PM PDT 24
Finished Apr 18 12:34:45 PM PDT 24
Peak memory 206980 kb
Host smart-7b345cd8-3e2c-46a9-a7f1-002fa93a2c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194549726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3194549726
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3919779584
Short name T448
Test name
Test status
Simulation time 247044408 ps
CPU time 4.23 seconds
Started Apr 18 12:34:43 PM PDT 24
Finished Apr 18 12:34:48 PM PDT 24
Peak memory 208884 kb
Host smart-7e39f402-1a41-408d-b152-df3c57997a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919779584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3919779584
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2461217153
Short name T524
Test name
Test status
Simulation time 1079037891 ps
CPU time 21.69 seconds
Started Apr 18 12:34:49 PM PDT 24
Finished Apr 18 12:35:12 PM PDT 24
Peak memory 208416 kb
Host smart-1e145f36-ae46-42ef-b629-684cea6935a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461217153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2461217153
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.636068990
Short name T701
Test name
Test status
Simulation time 37087684 ps
CPU time 2.48 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 208468 kb
Host smart-4b1b38ca-c7a4-443e-9ef9-f8a2d175f77c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636068990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.636068990
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.752198902
Short name T478
Test name
Test status
Simulation time 273337941 ps
CPU time 3.92 seconds
Started Apr 18 12:34:51 PM PDT 24
Finished Apr 18 12:34:56 PM PDT 24
Peak memory 207060 kb
Host smart-668dabc1-2f28-4faa-abf9-2d1229147e71
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752198902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.752198902
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3341537624
Short name T264
Test name
Test status
Simulation time 361974626 ps
CPU time 7.13 seconds
Started Apr 18 12:34:42 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 209012 kb
Host smart-6ec07476-4705-4c01-b156-add5fb811edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341537624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3341537624
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3957257457
Short name T402
Test name
Test status
Simulation time 62119615 ps
CPU time 2.87 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 208856 kb
Host smart-d53b7460-f37c-4d57-b92d-a121f35cd58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957257457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3957257457
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.771683760
Short name T901
Test name
Test status
Simulation time 111552213 ps
CPU time 2.54 seconds
Started Apr 18 12:34:56 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 207896 kb
Host smart-bf9bb057-a391-46b1-a8df-fcd82ec5a957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771683760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.771683760
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3238797667
Short name T137
Test name
Test status
Simulation time 262470716 ps
CPU time 2.36 seconds
Started Apr 18 12:35:05 PM PDT 24
Finished Apr 18 12:35:08 PM PDT 24
Peak memory 210200 kb
Host smart-fb26fb56-4e76-409d-bd98-68537c37359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238797667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3238797667
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.253210730
Short name T537
Test name
Test status
Simulation time 106917669 ps
CPU time 0.97 seconds
Started Apr 18 12:34:57 PM PDT 24
Finished Apr 18 12:35:00 PM PDT 24
Peak memory 206416 kb
Host smart-32fd4e86-cb2a-45e4-9e95-7bed1908e062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253210730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.253210730
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3632863795
Short name T759
Test name
Test status
Simulation time 996267260 ps
CPU time 9.12 seconds
Started Apr 18 12:34:43 PM PDT 24
Finished Apr 18 12:34:53 PM PDT 24
Peak memory 218604 kb
Host smart-40323aa8-0269-4b7b-8256-4846faf34fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632863795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3632863795
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.4049550858
Short name T451
Test name
Test status
Simulation time 61227670 ps
CPU time 3.15 seconds
Started Apr 18 12:34:45 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 209056 kb
Host smart-3e247a68-f382-421c-92b4-2e708f48a5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049550858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.4049550858
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2880172558
Short name T343
Test name
Test status
Simulation time 465713510 ps
CPU time 8.3 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:55 PM PDT 24
Peak memory 208592 kb
Host smart-b73090d5-8b35-43cf-8d49-6d3faf069c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880172558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2880172558
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2879126166
Short name T860
Test name
Test status
Simulation time 469748706 ps
CPU time 5.54 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:53 PM PDT 24
Peak memory 211636 kb
Host smart-45dd63af-1024-4235-81c9-5298d7ba86e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879126166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2879126166
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3358968148
Short name T614
Test name
Test status
Simulation time 249218748 ps
CPU time 2.3 seconds
Started Apr 18 12:34:47 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 214544 kb
Host smart-ff02a7be-246f-4a01-a15a-8afe0ff35030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358968148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3358968148
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.4088588201
Short name T769
Test name
Test status
Simulation time 57248374 ps
CPU time 3.54 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 207424 kb
Host smart-f5fb825d-1df8-48fd-9d29-e0daf7f4ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088588201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4088588201
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3113200567
Short name T380
Test name
Test status
Simulation time 150043815 ps
CPU time 4.5 seconds
Started Apr 18 12:34:45 PM PDT 24
Finished Apr 18 12:34:51 PM PDT 24
Peak memory 208848 kb
Host smart-da161a98-5d9c-4e12-8a01-f57337033183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113200567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3113200567
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1448584405
Short name T103
Test name
Test status
Simulation time 615217176 ps
CPU time 3.03 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 208808 kb
Host smart-55f87cb4-6f46-4376-a4ae-d7c29a8048c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448584405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1448584405
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3911698141
Short name T475
Test name
Test status
Simulation time 6485272920 ps
CPU time 40.8 seconds
Started Apr 18 12:34:43 PM PDT 24
Finished Apr 18 12:35:25 PM PDT 24
Peak memory 208116 kb
Host smart-c8c34ef4-79dd-4489-9395-2be0e94fbb6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911698141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3911698141
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3691858965
Short name T455
Test name
Test status
Simulation time 89287832 ps
CPU time 1.95 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:34:56 PM PDT 24
Peak memory 207116 kb
Host smart-bef3c3c6-04b4-48a2-9203-4a0a42e8dd54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691858965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3691858965
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.748112789
Short name T295
Test name
Test status
Simulation time 735629023 ps
CPU time 2.96 seconds
Started Apr 18 12:34:42 PM PDT 24
Finished Apr 18 12:34:46 PM PDT 24
Peak memory 208720 kb
Host smart-3770b433-2c4a-45f1-be81-a856798a30c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748112789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.748112789
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2712033660
Short name T435
Test name
Test status
Simulation time 74227415 ps
CPU time 2.31 seconds
Started Apr 18 12:34:41 PM PDT 24
Finished Apr 18 12:34:44 PM PDT 24
Peak memory 206932 kb
Host smart-3d23a7b1-58f9-45fa-9458-f0732ae52dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712033660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2712033660
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1602857209
Short name T105
Test name
Test status
Simulation time 120595912 ps
CPU time 3.22 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:00 PM PDT 24
Peak memory 209424 kb
Host smart-f021057f-5129-4100-a5ee-1f5aab721895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602857209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1602857209
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2112686538
Short name T691
Test name
Test status
Simulation time 649275677 ps
CPU time 6.67 seconds
Started Apr 18 12:34:43 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 211236 kb
Host smart-49e49df5-e23d-4977-a4c1-95d88943dfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112686538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2112686538
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3177239073
Short name T443
Test name
Test status
Simulation time 32381274 ps
CPU time 0.77 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 206156 kb
Host smart-34fc018a-0e08-465e-84de-5860a8cb97f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177239073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3177239073
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2603284000
Short name T820
Test name
Test status
Simulation time 87954984 ps
CPU time 2.9 seconds
Started Apr 18 12:34:51 PM PDT 24
Finished Apr 18 12:34:55 PM PDT 24
Peak memory 214648 kb
Host smart-90fd4eed-20ad-44ce-a26b-b28572fcd5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603284000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2603284000
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.473641598
Short name T696
Test name
Test status
Simulation time 339151085 ps
CPU time 4.83 seconds
Started Apr 18 12:34:49 PM PDT 24
Finished Apr 18 12:34:55 PM PDT 24
Peak memory 208828 kb
Host smart-63c2f3e7-5397-43d5-9f15-3bb06b780f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473641598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.473641598
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.962976669
Short name T284
Test name
Test status
Simulation time 1444580748 ps
CPU time 40.3 seconds
Started Apr 18 12:34:49 PM PDT 24
Finished Apr 18 12:35:30 PM PDT 24
Peak memory 224284 kb
Host smart-883e9129-f8ff-4bc6-85f0-12ac06c1b33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962976669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.962976669
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3515914366
Short name T857
Test name
Test status
Simulation time 361808877 ps
CPU time 1.8 seconds
Started Apr 18 12:34:49 PM PDT 24
Finished Apr 18 12:34:51 PM PDT 24
Peak memory 206436 kb
Host smart-855f1eb1-e09f-44d4-8f68-78285c164ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515914366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3515914366
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.284097702
Short name T316
Test name
Test status
Simulation time 274085084 ps
CPU time 8.62 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 219788 kb
Host smart-c029dbbb-5cc3-4f3d-bde1-ca95a1bd9a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284097702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.284097702
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2372573078
Short name T655
Test name
Test status
Simulation time 299771792 ps
CPU time 8.63 seconds
Started Apr 18 12:34:48 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 207104 kb
Host smart-4622062a-ccb4-42a5-8da0-e058f33aa0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372573078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2372573078
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2912104626
Short name T634
Test name
Test status
Simulation time 305732955 ps
CPU time 6.71 seconds
Started Apr 18 12:35:01 PM PDT 24
Finished Apr 18 12:35:09 PM PDT 24
Peak memory 208204 kb
Host smart-c637defa-341f-4ae1-9524-87317be88576
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912104626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2912104626
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2636210156
Short name T237
Test name
Test status
Simulation time 148973308 ps
CPU time 4.51 seconds
Started Apr 18 12:34:49 PM PDT 24
Finished Apr 18 12:34:55 PM PDT 24
Peak memory 208904 kb
Host smart-564361d3-730a-4f4a-9592-ff8c45febcb4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636210156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2636210156
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.67624827
Short name T704
Test name
Test status
Simulation time 21402638 ps
CPU time 1.67 seconds
Started Apr 18 12:34:51 PM PDT 24
Finished Apr 18 12:34:54 PM PDT 24
Peak memory 207564 kb
Host smart-b75cbc2f-0585-424b-90e4-ea0996f1f9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67624827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.67624827
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1289971668
Short name T534
Test name
Test status
Simulation time 1138470938 ps
CPU time 9.24 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:56 PM PDT 24
Peak memory 208708 kb
Host smart-2c36830a-3247-4882-bcc4-cef7187b351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289971668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1289971668
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3025791795
Short name T223
Test name
Test status
Simulation time 1210632107 ps
CPU time 33.19 seconds
Started Apr 18 12:34:58 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 214596 kb
Host smart-b7ad99c4-b38a-4b29-a40f-368ea6df2e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025791795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3025791795
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1329194701
Short name T706
Test name
Test status
Simulation time 616315632 ps
CPU time 4.11 seconds
Started Apr 18 12:34:49 PM PDT 24
Finished Apr 18 12:34:55 PM PDT 24
Peak memory 210688 kb
Host smart-a58b2a1b-1d3c-4388-ab76-d367e2eebffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329194701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1329194701
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.923669003
Short name T848
Test name
Test status
Simulation time 14647945 ps
CPU time 0.76 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:34:56 PM PDT 24
Peak memory 206132 kb
Host smart-0167b250-f28e-426c-8028-58e2ce9c444e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923669003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.923669003
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3402540917
Short name T752
Test name
Test status
Simulation time 2992885817 ps
CPU time 6.49 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:05 PM PDT 24
Peak memory 221124 kb
Host smart-94507ba1-c9a4-4100-adc4-5ba3e5ef915a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402540917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3402540917
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2937295597
Short name T869
Test name
Test status
Simulation time 77337631 ps
CPU time 3.51 seconds
Started Apr 18 12:34:48 PM PDT 24
Finished Apr 18 12:34:52 PM PDT 24
Peak memory 218516 kb
Host smart-cd6f8423-e092-4ea2-a04a-d45b80bb4594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937295597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2937295597
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1486337487
Short name T553
Test name
Test status
Simulation time 70497646 ps
CPU time 2.92 seconds
Started Apr 18 12:34:48 PM PDT 24
Finished Apr 18 12:34:51 PM PDT 24
Peak memory 209828 kb
Host smart-01dbca15-b2d5-4372-baf9-d83488a28b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486337487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1486337487
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.143023288
Short name T608
Test name
Test status
Simulation time 86660200 ps
CPU time 3.14 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 214544 kb
Host smart-a40f24a0-6255-4afd-aeb5-3de6d65666ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143023288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.143023288
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2989360254
Short name T287
Test name
Test status
Simulation time 213563884 ps
CPU time 6.94 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 208936 kb
Host smart-291a5e4a-8ed5-4fa8-aa31-0af584a2a948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989360254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2989360254
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1954750708
Short name T591
Test name
Test status
Simulation time 307696063 ps
CPU time 3.55 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 207468 kb
Host smart-63a41bf5-4a7f-4cd2-b486-ca3a3e4176fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954750708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1954750708
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1453856017
Short name T892
Test name
Test status
Simulation time 249297698 ps
CPU time 3.33 seconds
Started Apr 18 12:35:05 PM PDT 24
Finished Apr 18 12:35:09 PM PDT 24
Peak memory 206972 kb
Host smart-e0bc0b0f-406d-42da-8865-382afa8391c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453856017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1453856017
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1850298554
Short name T880
Test name
Test status
Simulation time 52847280 ps
CPU time 2.13 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:34:56 PM PDT 24
Peak memory 208880 kb
Host smart-fd290c2b-73eb-466e-8982-1c7c90f8cbf1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850298554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1850298554
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.324525639
Short name T899
Test name
Test status
Simulation time 384230594 ps
CPU time 2.25 seconds
Started Apr 18 12:34:47 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 208420 kb
Host smart-0b391c12-78f3-4b28-b4b7-f9b82339e340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324525639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.324525639
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.911312230
Short name T432
Test name
Test status
Simulation time 247984224 ps
CPU time 3.21 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 207212 kb
Host smart-a922970a-9a95-4572-8000-8825acda776d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911312230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.911312230
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.186948936
Short name T387
Test name
Test status
Simulation time 1263830458 ps
CPU time 44.32 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:35:40 PM PDT 24
Peak memory 215024 kb
Host smart-48260d2c-2487-4f06-ad7a-d2bd2558430b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186948936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.186948936
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3989619813
Short name T675
Test name
Test status
Simulation time 55398456 ps
CPU time 2.16 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 208496 kb
Host smart-54df3129-7a50-4bc1-855f-e7d7be2eec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989619813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3989619813
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.909779101
Short name T170
Test name
Test status
Simulation time 425833029 ps
CPU time 2.74 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 210516 kb
Host smart-27c7af9a-b7a4-4806-be92-b4476ca3d2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909779101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.909779101
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.481229146
Short name T792
Test name
Test status
Simulation time 11821619 ps
CPU time 0.74 seconds
Started Apr 18 12:34:57 PM PDT 24
Finished Apr 18 12:35:00 PM PDT 24
Peak memory 206200 kb
Host smart-4f5ad3e1-a678-4f2d-85d3-d3cdf7657924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481229146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.481229146
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1892982114
Short name T412
Test name
Test status
Simulation time 1862083085 ps
CPU time 8.28 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 214432 kb
Host smart-d8c06976-c577-4a9a-a165-3fef41a0a9b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892982114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1892982114
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2374345257
Short name T36
Test name
Test status
Simulation time 151932983 ps
CPU time 3.6 seconds
Started Apr 18 12:34:47 PM PDT 24
Finished Apr 18 12:34:52 PM PDT 24
Peak memory 214556 kb
Host smart-be06d8f3-bc57-4a1d-8fba-008ca3eb2389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374345257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2374345257
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4125719421
Short name T469
Test name
Test status
Simulation time 61656743 ps
CPU time 2.82 seconds
Started Apr 18 12:34:49 PM PDT 24
Finished Apr 18 12:34:53 PM PDT 24
Peak memory 214708 kb
Host smart-37ed66be-58ad-4f34-bd67-f87b207f861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125719421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4125719421
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3708064198
Short name T89
Test name
Test status
Simulation time 119891808 ps
CPU time 3.82 seconds
Started Apr 18 12:35:06 PM PDT 24
Finished Apr 18 12:35:10 PM PDT 24
Peak memory 214492 kb
Host smart-aa9ce0da-1024-433b-b045-cb52ab8cbe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708064198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3708064198
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1360275441
Short name T235
Test name
Test status
Simulation time 289343630 ps
CPU time 3.95 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 210712 kb
Host smart-dd2af2e3-4450-4ea0-b80b-bde8236b0880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360275441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1360275441
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2713314719
Short name T827
Test name
Test status
Simulation time 517492123 ps
CPU time 4.37 seconds
Started Apr 18 12:34:56 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 220512 kb
Host smart-202448e5-4dda-40e7-ab02-945524ab91f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713314719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2713314719
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3407320071
Short name T464
Test name
Test status
Simulation time 715941747 ps
CPU time 5.72 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 209772 kb
Host smart-e859bcd9-5cad-4f2a-8bcd-631298852aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407320071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3407320071
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2170723811
Short name T503
Test name
Test status
Simulation time 178217227 ps
CPU time 4.22 seconds
Started Apr 18 12:34:56 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 207840 kb
Host smart-799e8e52-4c17-4fd7-9859-b516aeceed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170723811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2170723811
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.66422561
Short name T453
Test name
Test status
Simulation time 161138096 ps
CPU time 6.3 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:04 PM PDT 24
Peak memory 207060 kb
Host smart-7e150744-ace1-4c0b-a2f5-94df03d9d1b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66422561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.66422561
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2222805912
Short name T297
Test name
Test status
Simulation time 255410144 ps
CPU time 3.41 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 208732 kb
Host smart-caefd790-6030-46a8-a6f3-8d0ca1fc16a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222805912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2222805912
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3268415430
Short name T575
Test name
Test status
Simulation time 520343480 ps
CPU time 13.16 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:35:07 PM PDT 24
Peak memory 208856 kb
Host smart-7690514e-940d-4d3e-a85d-2657221c45c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268415430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3268415430
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2549855166
Short name T699
Test name
Test status
Simulation time 304036672 ps
CPU time 2.76 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 214544 kb
Host smart-b9032cb2-8e11-4951-ac0a-252219ac0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549855166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2549855166
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3688727901
Short name T838
Test name
Test status
Simulation time 190235774 ps
CPU time 2.77 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 206812 kb
Host smart-e6d21336-5a4a-4b70-a1d5-fa9231372a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688727901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3688727901
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3962380626
Short name T890
Test name
Test status
Simulation time 3126256876 ps
CPU time 32.18 seconds
Started Apr 18 12:35:03 PM PDT 24
Finished Apr 18 12:35:36 PM PDT 24
Peak memory 208436 kb
Host smart-b2b61b9f-ac1c-47c0-b694-cb1d012a6a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962380626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3962380626
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3047034636
Short name T807
Test name
Test status
Simulation time 66253853 ps
CPU time 2.38 seconds
Started Apr 18 12:34:46 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 210448 kb
Host smart-edae8cfc-dbcb-4596-90d7-b0ce7b2cab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047034636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3047034636
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.303407590
Short name T456
Test name
Test status
Simulation time 15347058 ps
CPU time 0.8 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 206152 kb
Host smart-1ff6c112-c9f7-4d4a-a33e-df0e486c8154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303407590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.303407590
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3342017815
Short name T422
Test name
Test status
Simulation time 54861613 ps
CPU time 3.28 seconds
Started Apr 18 12:33:59 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 215496 kb
Host smart-0e912689-3a30-4baa-80b3-888dd7e0ca08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3342017815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3342017815
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4007030549
Short name T661
Test name
Test status
Simulation time 37702565 ps
CPU time 2.59 seconds
Started Apr 18 12:34:01 PM PDT 24
Finished Apr 18 12:34:06 PM PDT 24
Peak memory 222492 kb
Host smart-b30dd879-2223-4128-98b2-dae46ef76951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007030549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4007030549
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3376664529
Short name T43
Test name
Test status
Simulation time 156781550 ps
CPU time 3.85 seconds
Started Apr 18 12:34:03 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 218460 kb
Host smart-ba45a32c-2ea2-41f8-90cf-1aca75e1f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376664529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3376664529
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4238809837
Short name T894
Test name
Test status
Simulation time 120418521 ps
CPU time 5.85 seconds
Started Apr 18 12:34:01 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 219240 kb
Host smart-40d710ff-6a27-4d7e-bbff-2dea962ca91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238809837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4238809837
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1852224916
Short name T505
Test name
Test status
Simulation time 76094106 ps
CPU time 4.02 seconds
Started Apr 18 12:34:01 PM PDT 24
Finished Apr 18 12:34:07 PM PDT 24
Peak memory 209308 kb
Host smart-89ef3011-d3c3-40a7-874d-31fc80537650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852224916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1852224916
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.186878732
Short name T711
Test name
Test status
Simulation time 895120986 ps
CPU time 21.96 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:26 PM PDT 24
Peak memory 209304 kb
Host smart-f8a31ad4-030d-4723-b998-8302f0eb1c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186878732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.186878732
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2918558886
Short name T11
Test name
Test status
Simulation time 1604920015 ps
CPU time 12.37 seconds
Started Apr 18 12:34:00 PM PDT 24
Finished Apr 18 12:34:15 PM PDT 24
Peak memory 230180 kb
Host smart-93455983-c6e6-47da-9413-16cea9f50d06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918558886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2918558886
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3039148188
Short name T903
Test name
Test status
Simulation time 180921248 ps
CPU time 2.59 seconds
Started Apr 18 12:34:00 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 206948 kb
Host smart-35fe1fa9-6ec9-439f-a47b-151480e4821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039148188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3039148188
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.4104183733
Short name T201
Test name
Test status
Simulation time 133176554 ps
CPU time 2.44 seconds
Started Apr 18 12:34:00 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 208760 kb
Host smart-bd71a3a2-a461-480d-aac3-cfcc392c483f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104183733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.4104183733
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1501973693
Short name T488
Test name
Test status
Simulation time 455801901 ps
CPU time 3.47 seconds
Started Apr 18 12:34:01 PM PDT 24
Finished Apr 18 12:34:07 PM PDT 24
Peak memory 208740 kb
Host smart-4dab6861-5db2-4b11-b3d7-0036c6edb3c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501973693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1501973693
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2189419403
Short name T574
Test name
Test status
Simulation time 68601279 ps
CPU time 3.35 seconds
Started Apr 18 12:34:12 PM PDT 24
Finished Apr 18 12:34:16 PM PDT 24
Peak memory 208868 kb
Host smart-18b3f96d-4446-41c2-8f22-2aa4c7941b00
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189419403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2189419403
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2880936563
Short name T563
Test name
Test status
Simulation time 110241423 ps
CPU time 4.42 seconds
Started Apr 18 12:33:59 PM PDT 24
Finished Apr 18 12:34:06 PM PDT 24
Peak memory 210032 kb
Host smart-5ef1d9bc-43a3-4b1b-8e59-d7851e9186fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880936563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2880936563
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2278104006
Short name T570
Test name
Test status
Simulation time 1941236741 ps
CPU time 12.32 seconds
Started Apr 18 12:33:55 PM PDT 24
Finished Apr 18 12:34:11 PM PDT 24
Peak memory 207700 kb
Host smart-30212275-2072-4b7d-9a71-943b39b0a75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278104006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2278104006
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.749864493
Short name T683
Test name
Test status
Simulation time 850918832 ps
CPU time 37.44 seconds
Started Apr 18 12:33:59 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 216664 kb
Host smart-587f76c3-db0c-4326-855e-d68ebe906113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749864493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.749864493
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1633649311
Short name T841
Test name
Test status
Simulation time 362596189 ps
CPU time 10.51 seconds
Started Apr 18 12:34:00 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 209192 kb
Host smart-5274ccec-61f1-4e82-9432-dfedd3db4f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633649311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1633649311
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3749744383
Short name T870
Test name
Test status
Simulation time 124036515 ps
CPU time 2.87 seconds
Started Apr 18 12:34:00 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 210668 kb
Host smart-6b51780a-8d91-416d-91e7-e419294e0582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749744383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3749744383
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.374962863
Short name T549
Test name
Test status
Simulation time 10836616 ps
CPU time 0.81 seconds
Started Apr 18 12:34:57 PM PDT 24
Finished Apr 18 12:35:00 PM PDT 24
Peak memory 206252 kb
Host smart-d9679d41-590b-4ce2-ab15-af7d1f6109f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374962863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.374962863
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.6678948
Short name T414
Test name
Test status
Simulation time 120722001 ps
CPU time 3.9 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 215416 kb
Host smart-b57fa832-4d29-4343-b312-d0334e4565a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6678948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.6678948
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1449354515
Short name T528
Test name
Test status
Simulation time 1074871952 ps
CPU time 12.25 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:35:06 PM PDT 24
Peak memory 218884 kb
Host smart-acb1c2ff-2638-4feb-8e88-33657ebd7b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449354515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1449354515
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1875589426
Short name T329
Test name
Test status
Simulation time 1144475112 ps
CPU time 33.47 seconds
Started Apr 18 12:34:58 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 214448 kb
Host smart-adbde2dd-6883-4d6b-a2a8-9417ce7da910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875589426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1875589426
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.742557890
Short name T713
Test name
Test status
Simulation time 85933324 ps
CPU time 4.4 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 214492 kb
Host smart-2b0c7ca2-51bc-4988-ab4d-583e8b044c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742557890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.742557890
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1740676611
Short name T520
Test name
Test status
Simulation time 75304540 ps
CPU time 1.76 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:55 PM PDT 24
Peak memory 206432 kb
Host smart-613c78f3-1e6c-4e7a-98aa-966b91939126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740676611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1740676611
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.928150947
Short name T494
Test name
Test status
Simulation time 251211243 ps
CPU time 8.85 seconds
Started Apr 18 12:35:14 PM PDT 24
Finished Apr 18 12:35:23 PM PDT 24
Peak memory 208172 kb
Host smart-fef512ee-76ff-4a1f-bd92-53fc0b0aae11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928150947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.928150947
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3085427132
Short name T785
Test name
Test status
Simulation time 252700725 ps
CPU time 6.55 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:05 PM PDT 24
Peak memory 208068 kb
Host smart-263a815c-6136-431f-a6bd-7824343d6371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085427132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3085427132
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2959534730
Short name T678
Test name
Test status
Simulation time 48737087 ps
CPU time 2.77 seconds
Started Apr 18 12:34:58 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 208924 kb
Host smart-1e83adba-6f20-416c-b5b3-909bd159f1b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959534730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2959534730
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.941820560
Short name T789
Test name
Test status
Simulation time 82580373 ps
CPU time 3.79 seconds
Started Apr 18 12:35:19 PM PDT 24
Finished Apr 18 12:35:23 PM PDT 24
Peak memory 208888 kb
Host smart-7542448b-ad61-409f-8c68-cad65c001027
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941820560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.941820560
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1136207251
Short name T664
Test name
Test status
Simulation time 97293688 ps
CPU time 1.9 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 214572 kb
Host smart-f3dd34c6-6f51-4c01-b0d7-18518a55287d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136207251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1136207251
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.141239420
Short name T487
Test name
Test status
Simulation time 119910586 ps
CPU time 2.89 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:00 PM PDT 24
Peak memory 206964 kb
Host smart-9c630869-1fd8-46f6-a187-86f8431ebca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141239420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.141239420
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1856156287
Short name T246
Test name
Test status
Simulation time 1577651339 ps
CPU time 52.82 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 215436 kb
Host smart-0b61ee35-8c24-48bc-a5df-d9eae78771e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856156287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1856156287
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2530434242
Short name T705
Test name
Test status
Simulation time 576326381 ps
CPU time 9.19 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:35:04 PM PDT 24
Peak memory 209160 kb
Host smart-e48550f4-976d-460e-b015-1300c9f6fa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530434242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2530434242
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3023347060
Short name T715
Test name
Test status
Simulation time 130628865 ps
CPU time 2.95 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 210420 kb
Host smart-6a7a97e3-ad68-4580-bae7-3a4ceeac782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023347060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3023347060
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2595448944
Short name T525
Test name
Test status
Simulation time 41644466 ps
CPU time 0.72 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:54 PM PDT 24
Peak memory 206132 kb
Host smart-59c1e430-3385-4777-8709-6797f2a3f73a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595448944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2595448944
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3712207999
Short name T424
Test name
Test status
Simulation time 397501729 ps
CPU time 4.26 seconds
Started Apr 18 12:35:09 PM PDT 24
Finished Apr 18 12:35:14 PM PDT 24
Peak memory 214536 kb
Host smart-665793d4-26ce-436f-a210-ce3c318cc981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712207999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3712207999
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2356668586
Short name T818
Test name
Test status
Simulation time 1125188568 ps
CPU time 8.36 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 217760 kb
Host smart-993d7b9a-2f60-4b40-8e08-1e7c34cd748b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356668586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2356668586
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1222428334
Short name T134
Test name
Test status
Simulation time 47341627 ps
CPU time 1.89 seconds
Started Apr 18 12:35:03 PM PDT 24
Finished Apr 18 12:35:06 PM PDT 24
Peak memory 214592 kb
Host smart-c16faa88-b6c3-4f9b-a38b-170dabb14f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222428334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1222428334
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1057853145
Short name T817
Test name
Test status
Simulation time 67182430 ps
CPU time 3.15 seconds
Started Apr 18 12:34:52 PM PDT 24
Finished Apr 18 12:34:57 PM PDT 24
Peak memory 208992 kb
Host smart-a50504ac-7452-4211-8733-89a5d9284c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057853145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1057853145
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2791116687
Short name T907
Test name
Test status
Simulation time 792389054 ps
CPU time 7.53 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:05 PM PDT 24
Peak memory 208992 kb
Host smart-96a8efea-eeca-47d6-be20-916c9559882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791116687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2791116687
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3818594849
Short name T48
Test name
Test status
Simulation time 31070793 ps
CPU time 1.95 seconds
Started Apr 18 12:34:58 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 208468 kb
Host smart-54b6f2a1-2447-4069-908d-6ad32b3638fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818594849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3818594849
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2254645231
Short name T370
Test name
Test status
Simulation time 561072697 ps
CPU time 4.83 seconds
Started Apr 18 12:35:08 PM PDT 24
Finished Apr 18 12:35:14 PM PDT 24
Peak memory 208248 kb
Host smart-2978de09-368d-4e66-b260-3264dd9f8eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254645231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2254645231
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1142957771
Short name T452
Test name
Test status
Simulation time 143129429 ps
CPU time 4.24 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 208764 kb
Host smart-7a8815e1-012c-43a2-975a-be00fe9ff972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142957771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1142957771
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.612707711
Short name T288
Test name
Test status
Simulation time 137342339 ps
CPU time 2.63 seconds
Started Apr 18 12:34:59 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 208756 kb
Host smart-a57149c2-64fd-4c54-abc8-ad65f2d6fd48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612707711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.612707711
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3881462287
Short name T773
Test name
Test status
Simulation time 589427666 ps
CPU time 3.63 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:34:59 PM PDT 24
Peak memory 206908 kb
Host smart-3b86b036-f8a3-44fc-add1-84423b63c434
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881462287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3881462287
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3829320723
Short name T262
Test name
Test status
Simulation time 1862991373 ps
CPU time 17.79 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:35:13 PM PDT 24
Peak memory 206856 kb
Host smart-729f6521-286d-4771-bdee-ef2eb5ac0b3a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829320723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3829320723
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3529087761
Short name T633
Test name
Test status
Simulation time 445961012 ps
CPU time 4.99 seconds
Started Apr 18 12:34:56 PM PDT 24
Finished Apr 18 12:35:04 PM PDT 24
Peak memory 218420 kb
Host smart-7d2188d6-79d0-41c4-afbb-125aa8e5f8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529087761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3529087761
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2816207199
Short name T430
Test name
Test status
Simulation time 2099740999 ps
CPU time 21.87 seconds
Started Apr 18 12:35:12 PM PDT 24
Finished Apr 18 12:35:35 PM PDT 24
Peak memory 208648 kb
Host smart-95b7830e-3823-45aa-9591-92a9c4cfe304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816207199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2816207199
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.4109993593
Short name T833
Test name
Test status
Simulation time 787151034 ps
CPU time 19.45 seconds
Started Apr 18 12:35:10 PM PDT 24
Finished Apr 18 12:35:30 PM PDT 24
Peak memory 221628 kb
Host smart-3d1edbde-1782-4b43-b1bb-ca7496b1c6ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109993593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.4109993593
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1123858858
Short name T749
Test name
Test status
Simulation time 424923349 ps
CPU time 4.58 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 214768 kb
Host smart-bf90f58b-6ff6-4547-a871-cae008db6e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123858858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1123858858
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.567275980
Short name T504
Test name
Test status
Simulation time 298455192 ps
CPU time 2.97 seconds
Started Apr 18 12:35:00 PM PDT 24
Finished Apr 18 12:35:04 PM PDT 24
Peak memory 210312 kb
Host smart-88d32454-8f6e-4ced-a754-7cf13f75887f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567275980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.567275980
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.734097963
Short name T596
Test name
Test status
Simulation time 13336979 ps
CPU time 0.86 seconds
Started Apr 18 12:35:17 PM PDT 24
Finished Apr 18 12:35:18 PM PDT 24
Peak memory 206248 kb
Host smart-31d14575-9687-4033-8f38-9ea311e192df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734097963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.734097963
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1221086859
Short name T143
Test name
Test status
Simulation time 128302126 ps
CPU time 2.76 seconds
Started Apr 18 12:34:58 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 214416 kb
Host smart-2e62968f-e76c-4255-b992-3b5be97f0666
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221086859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1221086859
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1832788839
Short name T544
Test name
Test status
Simulation time 124466176 ps
CPU time 3.91 seconds
Started Apr 18 12:34:56 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 214804 kb
Host smart-46b9c419-2217-4f3b-9f8c-0ab0c51a01c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832788839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1832788839
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1373563843
Short name T300
Test name
Test status
Simulation time 706130948 ps
CPU time 7.07 seconds
Started Apr 18 12:34:54 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 209624 kb
Host smart-50789d72-a77c-44f3-b45f-1c74d8607cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373563843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1373563843
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.886310176
Short name T862
Test name
Test status
Simulation time 326853916 ps
CPU time 4.04 seconds
Started Apr 18 12:34:57 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 208708 kb
Host smart-c7e7af42-11b0-4851-9eef-76b4d0faa697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886310176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.886310176
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.419529277
Short name T584
Test name
Test status
Simulation time 248444364 ps
CPU time 3.97 seconds
Started Apr 18 12:34:56 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 220988 kb
Host smart-195c3bde-6dfc-4f0f-878d-96561d0af92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419529277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.419529277
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1993254152
Short name T619
Test name
Test status
Simulation time 1418061649 ps
CPU time 6.89 seconds
Started Apr 18 12:34:57 PM PDT 24
Finished Apr 18 12:35:06 PM PDT 24
Peak memory 208540 kb
Host smart-f38ec38e-3acf-4c2f-8b2e-195786e073b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993254152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1993254152
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2102700989
Short name T734
Test name
Test status
Simulation time 966718695 ps
CPU time 6.18 seconds
Started Apr 18 12:34:58 PM PDT 24
Finished Apr 18 12:35:06 PM PDT 24
Peak memory 207272 kb
Host smart-30344613-4f89-4f85-b41e-2c25d6580873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102700989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2102700989
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.619064605
Short name T703
Test name
Test status
Simulation time 202116586 ps
CPU time 5.42 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 208004 kb
Host smart-7af27942-2282-444c-9c85-f739fd8bf622
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619064605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.619064605
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3882399700
Short name T465
Test name
Test status
Simulation time 3898796700 ps
CPU time 37 seconds
Started Apr 18 12:34:56 PM PDT 24
Finished Apr 18 12:35:36 PM PDT 24
Peak memory 209448 kb
Host smart-326d2c95-fc20-44a6-b769-babd46cdb278
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882399700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3882399700
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2496529774
Short name T775
Test name
Test status
Simulation time 225852147 ps
CPU time 7.81 seconds
Started Apr 18 12:34:53 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 208968 kb
Host smart-fc8ec6ca-ee90-46d0-b791-2f52fdca7c17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496529774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2496529774
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1819273679
Short name T896
Test name
Test status
Simulation time 47679900 ps
CPU time 1.97 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:00 PM PDT 24
Peak memory 208336 kb
Host smart-4017b2b4-f09c-4930-a620-61321382c442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819273679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1819273679
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3073004051
Short name T656
Test name
Test status
Simulation time 154751412 ps
CPU time 2.57 seconds
Started Apr 18 12:34:57 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 206260 kb
Host smart-9d5d5d70-c214-479f-a224-af3e6ac7a893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073004051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3073004051
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3817428381
Short name T545
Test name
Test status
Simulation time 486173014 ps
CPU time 8.48 seconds
Started Apr 18 12:35:01 PM PDT 24
Finished Apr 18 12:35:11 PM PDT 24
Peak memory 222328 kb
Host smart-2ea43e1f-67d8-4972-996b-6b4f17083810
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817428381 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3817428381
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2045584934
Short name T662
Test name
Test status
Simulation time 144133837 ps
CPU time 6.15 seconds
Started Apr 18 12:34:55 PM PDT 24
Finished Apr 18 12:35:04 PM PDT 24
Peak memory 209900 kb
Host smart-569ff23b-c812-40dc-a25f-dd1e7685f02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045584934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2045584934
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.374306557
Short name T708
Test name
Test status
Simulation time 522877050 ps
CPU time 2.92 seconds
Started Apr 18 12:35:08 PM PDT 24
Finished Apr 18 12:35:12 PM PDT 24
Peak memory 211128 kb
Host smart-739a94ec-22fa-451c-a8d4-a0676aeadb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374306557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.374306557
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1716955780
Short name T836
Test name
Test status
Simulation time 60204983 ps
CPU time 0.97 seconds
Started Apr 18 12:35:01 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 206364 kb
Host smart-7a33c1ca-c722-45ca-b16d-69c4612889ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716955780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1716955780
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2658772677
Short name T335
Test name
Test status
Simulation time 53645873 ps
CPU time 4 seconds
Started Apr 18 12:35:01 PM PDT 24
Finished Apr 18 12:35:06 PM PDT 24
Peak memory 214540 kb
Host smart-38091b70-0ba6-43f9-a11c-71ba98b7201b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658772677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2658772677
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.860550209
Short name T764
Test name
Test status
Simulation time 53523521 ps
CPU time 1.93 seconds
Started Apr 18 12:34:58 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 210908 kb
Host smart-a8f8efe8-6d64-4791-abd6-22ada7d8c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860550209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.860550209
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3451572610
Short name T668
Test name
Test status
Simulation time 59159070 ps
CPU time 2.17 seconds
Started Apr 18 12:35:13 PM PDT 24
Finished Apr 18 12:35:16 PM PDT 24
Peak memory 218504 kb
Host smart-dcf19a0c-cec6-4752-940a-6d58e07a63b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451572610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3451572610
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1295484839
Short name T768
Test name
Test status
Simulation time 121018589 ps
CPU time 4.12 seconds
Started Apr 18 12:35:08 PM PDT 24
Finished Apr 18 12:35:13 PM PDT 24
Peak memory 214564 kb
Host smart-c9947b02-c19f-473d-bf4d-fd02c5f14c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295484839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1295484839
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.724616610
Short name T217
Test name
Test status
Simulation time 96686683 ps
CPU time 4.49 seconds
Started Apr 18 12:35:17 PM PDT 24
Finished Apr 18 12:35:22 PM PDT 24
Peak memory 222668 kb
Host smart-34d62d22-6584-4c2e-8710-86ff0ab4f52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724616610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.724616610
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.4076188568
Short name T686
Test name
Test status
Simulation time 647149073 ps
CPU time 3.08 seconds
Started Apr 18 12:35:00 PM PDT 24
Finished Apr 18 12:35:05 PM PDT 24
Peak memory 207752 kb
Host smart-ce5cd2ad-1b33-4de3-9ef0-f9d1ce3d2516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076188568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4076188568
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2412650352
Short name T864
Test name
Test status
Simulation time 1980474470 ps
CPU time 15.55 seconds
Started Apr 18 12:35:15 PM PDT 24
Finished Apr 18 12:35:32 PM PDT 24
Peak memory 208584 kb
Host smart-b66c0fea-bed0-4f99-834e-de899f1f8307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412650352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2412650352
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1235718162
Short name T822
Test name
Test status
Simulation time 568532705 ps
CPU time 3.94 seconds
Started Apr 18 12:34:57 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 208828 kb
Host smart-013dbc1d-2ec2-4b85-937c-91345a9960b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235718162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1235718162
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2753860198
Short name T597
Test name
Test status
Simulation time 231119914 ps
CPU time 3.18 seconds
Started Apr 18 12:34:59 PM PDT 24
Finished Apr 18 12:35:08 PM PDT 24
Peak memory 207040 kb
Host smart-ed6c9695-70f5-4431-b4c3-9e9b7b6cd14e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753860198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2753860198
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2216460267
Short name T130
Test name
Test status
Simulation time 415139245 ps
CPU time 4.57 seconds
Started Apr 18 12:35:07 PM PDT 24
Finished Apr 18 12:35:12 PM PDT 24
Peak memory 206936 kb
Host smart-f1b4a8d5-47d7-4d4e-b0f8-09a211ba8812
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216460267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2216460267
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4184996169
Short name T501
Test name
Test status
Simulation time 74410534 ps
CPU time 1.95 seconds
Started Apr 18 12:35:21 PM PDT 24
Finished Apr 18 12:35:24 PM PDT 24
Peak memory 215848 kb
Host smart-fd32ea86-5511-4f72-8e5a-443e12781e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184996169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4184996169
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2015507575
Short name T447
Test name
Test status
Simulation time 45231171 ps
CPU time 1.84 seconds
Started Apr 18 12:35:09 PM PDT 24
Finished Apr 18 12:35:17 PM PDT 24
Peak memory 206868 kb
Host smart-1b6cec1e-ecfc-4c9a-886c-340cc3f2f4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015507575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2015507575
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2784897693
Short name T182
Test name
Test status
Simulation time 834035378 ps
CPU time 11.94 seconds
Started Apr 18 12:34:59 PM PDT 24
Finished Apr 18 12:35:12 PM PDT 24
Peak memory 222852 kb
Host smart-e6febbf0-541e-404f-980c-6d6c384e16b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784897693 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2784897693
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1390097857
Short name T763
Test name
Test status
Simulation time 296761423 ps
CPU time 5.16 seconds
Started Apr 18 12:35:00 PM PDT 24
Finished Apr 18 12:35:07 PM PDT 24
Peak memory 214524 kb
Host smart-0ff5a909-7448-47e0-be93-3ea2aabd0ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390097857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1390097857
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.66790100
Short name T391
Test name
Test status
Simulation time 234106889 ps
CPU time 3.92 seconds
Started Apr 18 12:35:15 PM PDT 24
Finished Apr 18 12:35:20 PM PDT 24
Peak memory 210520 kb
Host smart-4b67a9f9-6757-4979-9426-144b6014fd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66790100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.66790100
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1576081190
Short name T742
Test name
Test status
Simulation time 39794101 ps
CPU time 0.8 seconds
Started Apr 18 12:34:59 PM PDT 24
Finished Apr 18 12:35:01 PM PDT 24
Peak memory 206168 kb
Host smart-cbbad1a3-eef8-47fc-8e8e-51404b406e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576081190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1576081190
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1330151302
Short name T415
Test name
Test status
Simulation time 610238740 ps
CPU time 4.31 seconds
Started Apr 18 12:35:00 PM PDT 24
Finished Apr 18 12:35:06 PM PDT 24
Peak memory 214452 kb
Host smart-36cc42da-ce79-498f-bb69-b5fd37ef5566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330151302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1330151302
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.467512530
Short name T9
Test name
Test status
Simulation time 38707751 ps
CPU time 1.97 seconds
Started Apr 18 12:35:00 PM PDT 24
Finished Apr 18 12:35:03 PM PDT 24
Peak memory 210816 kb
Host smart-639f0e48-84b8-4b58-b815-47c318452fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467512530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.467512530
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.395996362
Short name T417
Test name
Test status
Simulation time 286752353 ps
CPU time 2.56 seconds
Started Apr 18 12:34:57 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 209272 kb
Host smart-f7843290-764b-47ea-89d9-19e30c14580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395996362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.395996362
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2119228362
Short name T86
Test name
Test status
Simulation time 266598442 ps
CPU time 3.63 seconds
Started Apr 18 12:35:00 PM PDT 24
Finished Apr 18 12:35:05 PM PDT 24
Peak memory 209704 kb
Host smart-cfaafb82-131f-413e-bb8e-5211dd3b31dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119228362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2119228362
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2532036822
Short name T358
Test name
Test status
Simulation time 359896552 ps
CPU time 5.79 seconds
Started Apr 18 12:35:25 PM PDT 24
Finished Apr 18 12:35:32 PM PDT 24
Peak memory 211828 kb
Host smart-88c38a93-b03c-4d76-82d5-4cd2f9d583ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532036822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2532036822
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2575670457
Short name T638
Test name
Test status
Simulation time 245681700 ps
CPU time 4.09 seconds
Started Apr 18 12:34:59 PM PDT 24
Finished Apr 18 12:35:04 PM PDT 24
Peak memory 209928 kb
Host smart-f13943ba-4805-4cfd-ac8a-2fbc38797c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575670457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2575670457
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2815304037
Short name T684
Test name
Test status
Simulation time 303018955 ps
CPU time 3.78 seconds
Started Apr 18 12:35:14 PM PDT 24
Finished Apr 18 12:35:18 PM PDT 24
Peak memory 214600 kb
Host smart-19c8a451-4c13-46a8-8ae7-12bdc666a424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815304037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2815304037
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1034386843
Short name T783
Test name
Test status
Simulation time 267018754 ps
CPU time 4.12 seconds
Started Apr 18 12:35:12 PM PDT 24
Finished Apr 18 12:35:17 PM PDT 24
Peak memory 208716 kb
Host smart-c7a461be-7936-45f2-bdbd-3b1a71bba488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034386843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1034386843
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.461077518
Short name T751
Test name
Test status
Simulation time 56296300 ps
CPU time 3.14 seconds
Started Apr 18 12:35:17 PM PDT 24
Finished Apr 18 12:35:21 PM PDT 24
Peak memory 209024 kb
Host smart-0f1c3896-6ec7-4ff7-9fc2-e8966d1954c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461077518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.461077518
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1026448580
Short name T73
Test name
Test status
Simulation time 221585777 ps
CPU time 6.57 seconds
Started Apr 18 12:35:00 PM PDT 24
Finished Apr 18 12:35:08 PM PDT 24
Peak memory 208872 kb
Host smart-a4700f6b-9141-43dc-ae9b-47b9876bd05d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026448580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1026448580
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1002096972
Short name T108
Test name
Test status
Simulation time 64403533 ps
CPU time 3.21 seconds
Started Apr 18 12:35:07 PM PDT 24
Finished Apr 18 12:35:10 PM PDT 24
Peak memory 208056 kb
Host smart-f31912d3-af08-487e-b54b-a51f9ba5c743
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002096972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1002096972
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3766721575
Short name T109
Test name
Test status
Simulation time 118212875 ps
CPU time 3.37 seconds
Started Apr 18 12:35:06 PM PDT 24
Finished Apr 18 12:35:09 PM PDT 24
Peak memory 214536 kb
Host smart-5e166a85-5d87-4b2b-985f-8ee28f6976e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766721575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3766721575
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1953596208
Short name T317
Test name
Test status
Simulation time 650342462 ps
CPU time 9.75 seconds
Started Apr 18 12:35:00 PM PDT 24
Finished Apr 18 12:35:11 PM PDT 24
Peak memory 218364 kb
Host smart-18fcb2cf-0a24-4ca5-9ad9-6e725f5345d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953596208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1953596208
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1873914316
Short name T560
Test name
Test status
Simulation time 1075815264 ps
CPU time 5.66 seconds
Started Apr 18 12:35:14 PM PDT 24
Finished Apr 18 12:35:21 PM PDT 24
Peak memory 210888 kb
Host smart-0e92d032-1b3f-4ffa-9080-45fc790a56c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873914316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1873914316
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1426630456
Short name T605
Test name
Test status
Simulation time 13116070 ps
CPU time 0.88 seconds
Started Apr 18 12:35:08 PM PDT 24
Finished Apr 18 12:35:10 PM PDT 24
Peak memory 206140 kb
Host smart-87fe1308-e907-4546-9754-7fde7f18dfd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426630456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1426630456
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.645113632
Short name T292
Test name
Test status
Simulation time 37266764 ps
CPU time 2.72 seconds
Started Apr 18 12:35:15 PM PDT 24
Finished Apr 18 12:35:18 PM PDT 24
Peak memory 214744 kb
Host smart-0ed45903-f950-4345-8d00-5e70b61b197a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645113632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.645113632
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.416141015
Short name T204
Test name
Test status
Simulation time 1203296470 ps
CPU time 15.84 seconds
Started Apr 18 12:35:09 PM PDT 24
Finished Apr 18 12:35:25 PM PDT 24
Peak memory 210460 kb
Host smart-57c7a7a2-c1b2-44e7-9dda-8b51a8316a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416141015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.416141015
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3660229568
Short name T647
Test name
Test status
Simulation time 34343329 ps
CPU time 2.25 seconds
Started Apr 18 12:35:13 PM PDT 24
Finished Apr 18 12:35:16 PM PDT 24
Peak memory 214640 kb
Host smart-8e410da1-43fa-4e68-94ab-dd4e7ac449ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660229568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3660229568
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3122623172
Short name T91
Test name
Test status
Simulation time 1254184453 ps
CPU time 18.03 seconds
Started Apr 18 12:35:17 PM PDT 24
Finished Apr 18 12:35:36 PM PDT 24
Peak memory 209524 kb
Host smart-a59c4d3f-0a45-44ef-b6b2-a4afc95fea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122623172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3122623172
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2694649597
Short name T895
Test name
Test status
Simulation time 123072172 ps
CPU time 5.86 seconds
Started Apr 18 12:35:27 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 210304 kb
Host smart-30e08f8d-d557-45d7-af86-7e335f231cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694649597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2694649597
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2852510270
Short name T220
Test name
Test status
Simulation time 101897230 ps
CPU time 3.14 seconds
Started Apr 18 12:35:13 PM PDT 24
Finished Apr 18 12:35:17 PM PDT 24
Peak memory 207920 kb
Host smart-6a257835-589b-4af4-8f64-8c7af61a5b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852510270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2852510270
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1873947291
Short name T564
Test name
Test status
Simulation time 37505815 ps
CPU time 2.39 seconds
Started Apr 18 12:35:18 PM PDT 24
Finished Apr 18 12:35:21 PM PDT 24
Peak memory 207012 kb
Host smart-39922907-d1ab-4635-8cad-c602b87327b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873947291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1873947291
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3549489062
Short name T657
Test name
Test status
Simulation time 872049324 ps
CPU time 10.08 seconds
Started Apr 18 12:35:04 PM PDT 24
Finished Apr 18 12:35:15 PM PDT 24
Peak memory 208220 kb
Host smart-503e5c63-612a-4a5b-900b-a0f1cea9f29e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549489062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3549489062
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.4067636541
Short name T811
Test name
Test status
Simulation time 258725153 ps
CPU time 3.11 seconds
Started Apr 18 12:35:16 PM PDT 24
Finished Apr 18 12:35:20 PM PDT 24
Peak memory 208760 kb
Host smart-8b7aadef-1330-4cc2-9963-8c65b065004c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067636541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4067636541
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3733259712
Short name T640
Test name
Test status
Simulation time 1591957654 ps
CPU time 38.19 seconds
Started Apr 18 12:35:04 PM PDT 24
Finished Apr 18 12:35:43 PM PDT 24
Peak memory 208392 kb
Host smart-c937caa8-3155-4450-bbae-569bfa111d35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733259712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3733259712
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1611890948
Short name T687
Test name
Test status
Simulation time 39713862 ps
CPU time 2.23 seconds
Started Apr 18 12:35:10 PM PDT 24
Finished Apr 18 12:35:13 PM PDT 24
Peak memory 207236 kb
Host smart-47c585cb-b192-466f-9fb9-b9f01f1058d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611890948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1611890948
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2872058968
Short name T477
Test name
Test status
Simulation time 166072595 ps
CPU time 3.74 seconds
Started Apr 18 12:35:13 PM PDT 24
Finished Apr 18 12:35:18 PM PDT 24
Peak memory 207440 kb
Host smart-251c3d26-87d2-4ff7-956e-11c363afa7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872058968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2872058968
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1452798682
Short name T846
Test name
Test status
Simulation time 533380665 ps
CPU time 21.39 seconds
Started Apr 18 12:35:22 PM PDT 24
Finished Apr 18 12:35:44 PM PDT 24
Peak memory 222876 kb
Host smart-957092f8-38b8-487a-a9ec-674a508cd149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452798682 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1452798682
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1347712169
Short name T325
Test name
Test status
Simulation time 125333920 ps
CPU time 5.04 seconds
Started Apr 18 12:35:20 PM PDT 24
Finished Apr 18 12:35:26 PM PDT 24
Peak memory 214632 kb
Host smart-f29ff164-def3-4dfc-91be-a58bdc99f3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347712169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1347712169
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1327246196
Short name T54
Test name
Test status
Simulation time 156250001 ps
CPU time 3.28 seconds
Started Apr 18 12:35:07 PM PDT 24
Finished Apr 18 12:35:11 PM PDT 24
Peak memory 210236 kb
Host smart-9938e6ef-45f7-44f8-9b4f-60a3698e02e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327246196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1327246196
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2449148651
Short name T461
Test name
Test status
Simulation time 13889733 ps
CPU time 0.72 seconds
Started Apr 18 12:35:18 PM PDT 24
Finished Apr 18 12:35:20 PM PDT 24
Peak memory 206080 kb
Host smart-477cfa03-b580-4fd4-822a-ffd09091aacf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449148651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2449148651
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.744476640
Short name T342
Test name
Test status
Simulation time 1366080910 ps
CPU time 73.26 seconds
Started Apr 18 12:35:11 PM PDT 24
Finished Apr 18 12:36:25 PM PDT 24
Peak memory 215764 kb
Host smart-cbefb25d-a1dd-40dd-b39b-23e4e269f2b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744476640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.744476640
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1942996319
Short name T191
Test name
Test status
Simulation time 496157635 ps
CPU time 8.14 seconds
Started Apr 18 12:35:03 PM PDT 24
Finished Apr 18 12:35:12 PM PDT 24
Peak memory 222944 kb
Host smart-fdcf7a3e-d4ed-4aaf-b84f-e64008e204e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942996319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1942996319
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.4185009137
Short name T474
Test name
Test status
Simulation time 97845525 ps
CPU time 1.28 seconds
Started Apr 18 12:35:03 PM PDT 24
Finished Apr 18 12:35:05 PM PDT 24
Peak memory 208336 kb
Host smart-5c477142-c221-4bbe-85b7-9f347c5b0786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185009137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.4185009137
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.785271960
Short name T4
Test name
Test status
Simulation time 364077535 ps
CPU time 7.79 seconds
Started Apr 18 12:35:04 PM PDT 24
Finished Apr 18 12:35:12 PM PDT 24
Peak memory 222372 kb
Host smart-f37c7aed-2cda-4036-9d72-1d419f42dc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785271960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.785271960
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1745480966
Short name T320
Test name
Test status
Simulation time 54972907 ps
CPU time 3.51 seconds
Started Apr 18 12:35:23 PM PDT 24
Finished Apr 18 12:35:28 PM PDT 24
Peak memory 221940 kb
Host smart-7641b556-44ab-4b18-aaa2-86c433268820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745480966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1745480966
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1928672457
Short name T242
Test name
Test status
Simulation time 168977871 ps
CPU time 2.47 seconds
Started Apr 18 12:35:07 PM PDT 24
Finished Apr 18 12:35:10 PM PDT 24
Peak memory 222612 kb
Host smart-4047c371-e7b5-4de6-8200-6fc897d64aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928672457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1928672457
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1665062938
Short name T499
Test name
Test status
Simulation time 799166259 ps
CPU time 5.07 seconds
Started Apr 18 12:35:12 PM PDT 24
Finished Apr 18 12:35:18 PM PDT 24
Peak memory 209244 kb
Host smart-e131b00a-e0fd-437a-b287-22709c20f0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665062938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1665062938
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3220732124
Short name T853
Test name
Test status
Simulation time 262387947 ps
CPU time 3.09 seconds
Started Apr 18 12:35:08 PM PDT 24
Finished Apr 18 12:35:12 PM PDT 24
Peak memory 207204 kb
Host smart-f121523d-6bb3-4935-86e6-610b6b82922a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220732124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3220732124
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.421677160
Short name T536
Test name
Test status
Simulation time 130667514 ps
CPU time 3.17 seconds
Started Apr 18 12:35:09 PM PDT 24
Finished Apr 18 12:35:13 PM PDT 24
Peak memory 207032 kb
Host smart-3aac7106-0fe8-477b-8a34-bf40cc1d613b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421677160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.421677160
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2315261888
Short name T676
Test name
Test status
Simulation time 25222333 ps
CPU time 1.86 seconds
Started Apr 18 12:35:10 PM PDT 24
Finished Apr 18 12:35:13 PM PDT 24
Peak memory 207004 kb
Host smart-d0adb9a9-6a91-435d-a5d3-b85c5f0d7178
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315261888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2315261888
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1640237435
Short name T694
Test name
Test status
Simulation time 174927397 ps
CPU time 5.57 seconds
Started Apr 18 12:35:08 PM PDT 24
Finished Apr 18 12:35:14 PM PDT 24
Peak memory 208064 kb
Host smart-7ba8f967-eaa3-48f5-a5e6-25099eb3a88a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640237435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1640237435
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1388943
Short name T858
Test name
Test status
Simulation time 362740867 ps
CPU time 2.93 seconds
Started Apr 18 12:35:17 PM PDT 24
Finished Apr 18 12:35:21 PM PDT 24
Peak memory 209060 kb
Host smart-134fd4eb-4403-4b4a-a7f2-c71473e43394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1388943
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.880495146
Short name T682
Test name
Test status
Simulation time 69193693 ps
CPU time 2.29 seconds
Started Apr 18 12:35:10 PM PDT 24
Finished Apr 18 12:35:13 PM PDT 24
Peak memory 206988 kb
Host smart-3f68afab-0c72-4e8c-ba6d-48635343a470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880495146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.880495146
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2679577389
Short name T190
Test name
Test status
Simulation time 134730594 ps
CPU time 5.21 seconds
Started Apr 18 12:35:11 PM PDT 24
Finished Apr 18 12:35:17 PM PDT 24
Peak memory 215916 kb
Host smart-e2b099a6-984f-4944-8b24-c5efe1010cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679577389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2679577389
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.164539120
Short name T517
Test name
Test status
Simulation time 672336237 ps
CPU time 8.22 seconds
Started Apr 18 12:35:28 PM PDT 24
Finished Apr 18 12:35:37 PM PDT 24
Peak memory 214668 kb
Host smart-97c8d37d-605b-4052-b580-1e607c90f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164539120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.164539120
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2714585
Short name T173
Test name
Test status
Simulation time 252127183 ps
CPU time 2.89 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:35 PM PDT 24
Peak memory 210772 kb
Host smart-2044f12f-922a-4419-9323-991e7b4c8002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2714585
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.567302875
Short name T576
Test name
Test status
Simulation time 42350598 ps
CPU time 0.74 seconds
Started Apr 18 12:35:22 PM PDT 24
Finished Apr 18 12:35:24 PM PDT 24
Peak memory 206180 kb
Host smart-5ca23594-e38b-46d8-8e8c-20c91e1117c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567302875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.567302875
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1040634931
Short name T406
Test name
Test status
Simulation time 58027832 ps
CPU time 3.38 seconds
Started Apr 18 12:35:29 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 208700 kb
Host smart-7047a78c-d981-40c9-9800-594ebbaafea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040634931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1040634931
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3394771834
Short name T129
Test name
Test status
Simulation time 345731475 ps
CPU time 3.6 seconds
Started Apr 18 12:35:17 PM PDT 24
Finished Apr 18 12:35:21 PM PDT 24
Peak memory 209336 kb
Host smart-150154a6-58dd-4648-aea5-c92621f0d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394771834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3394771834
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.457131790
Short name T282
Test name
Test status
Simulation time 602112030 ps
CPU time 4.88 seconds
Started Apr 18 12:35:21 PM PDT 24
Finished Apr 18 12:35:26 PM PDT 24
Peak memory 211168 kb
Host smart-7875a158-02a1-4405-9dae-34d7c8bdf375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457131790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.457131790
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1115761801
Short name T891
Test name
Test status
Simulation time 121980117 ps
CPU time 4.17 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:37 PM PDT 24
Peak memory 220476 kb
Host smart-ef0a75ae-b390-423e-b709-7d34f5dfe348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115761801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1115761801
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.4241161020
Short name T389
Test name
Test status
Simulation time 602732841 ps
CPU time 2.49 seconds
Started Apr 18 12:35:22 PM PDT 24
Finished Apr 18 12:35:25 PM PDT 24
Peak memory 208384 kb
Host smart-0f42499a-2027-411a-9dd3-72c98ab6a1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241161020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.4241161020
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3976824454
Short name T383
Test name
Test status
Simulation time 114592018 ps
CPU time 3.08 seconds
Started Apr 18 12:35:13 PM PDT 24
Finished Apr 18 12:35:17 PM PDT 24
Peak memory 209116 kb
Host smart-deb9051e-b7c9-4c10-bd6b-b399b245f8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976824454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3976824454
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3782342183
Short name T609
Test name
Test status
Simulation time 27963113 ps
CPU time 1.84 seconds
Started Apr 18 12:35:18 PM PDT 24
Finished Apr 18 12:35:21 PM PDT 24
Peak memory 207164 kb
Host smart-277f5dbf-7c07-44de-be94-4859f2fd5ff3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782342183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3782342183
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4259717291
Short name T580
Test name
Test status
Simulation time 123396910 ps
CPU time 3.25 seconds
Started Apr 18 12:35:13 PM PDT 24
Finished Apr 18 12:35:18 PM PDT 24
Peak memory 208928 kb
Host smart-be183021-c91e-45a7-b95d-927809118213
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259717291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4259717291
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2773150261
Short name T761
Test name
Test status
Simulation time 322078956 ps
CPU time 6.24 seconds
Started Apr 18 12:35:14 PM PDT 24
Finished Apr 18 12:35:21 PM PDT 24
Peak memory 208276 kb
Host smart-631321ca-952d-4fd3-9716-7db9bc4388b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773150261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2773150261
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1738685802
Short name T727
Test name
Test status
Simulation time 251335899 ps
CPU time 3.81 seconds
Started Apr 18 12:35:10 PM PDT 24
Finished Apr 18 12:35:15 PM PDT 24
Peak memory 207488 kb
Host smart-e13ee291-fdb5-43fb-bf44-fb96dcc60e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738685802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1738685802
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3502006554
Short name T826
Test name
Test status
Simulation time 167587021 ps
CPU time 2.65 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:35 PM PDT 24
Peak memory 206892 kb
Host smart-d19809c9-9392-4fc5-b412-3640303f63b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502006554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3502006554
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2319249810
Short name T745
Test name
Test status
Simulation time 883216959 ps
CPU time 16.7 seconds
Started Apr 18 12:35:16 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 215724 kb
Host smart-2ba5227f-a45f-4f4b-991d-d728cb894f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319249810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2319249810
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2475204484
Short name T669
Test name
Test status
Simulation time 556502634 ps
CPU time 3.69 seconds
Started Apr 18 12:35:27 PM PDT 24
Finished Apr 18 12:35:31 PM PDT 24
Peak memory 218680 kb
Host smart-7cd41e61-e3f1-4626-bd72-6f830a114549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475204484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2475204484
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3061290146
Short name T157
Test name
Test status
Simulation time 579906117 ps
CPU time 3.97 seconds
Started Apr 18 12:35:14 PM PDT 24
Finished Apr 18 12:35:19 PM PDT 24
Peak memory 210700 kb
Host smart-7e155dc4-e221-4bb5-8b32-41f37c46d80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061290146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3061290146
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.675890066
Short name T622
Test name
Test status
Simulation time 15435428 ps
CPU time 0.8 seconds
Started Apr 18 12:35:20 PM PDT 24
Finished Apr 18 12:35:22 PM PDT 24
Peak memory 206252 kb
Host smart-60413516-5600-4980-9b92-393f3ee5f57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675890066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.675890066
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1260435497
Short name T830
Test name
Test status
Simulation time 301148332 ps
CPU time 15.48 seconds
Started Apr 18 12:35:23 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 215664 kb
Host smart-a7ba0605-bd56-4415-abeb-13381a009f16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260435497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1260435497
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.149122210
Short name T770
Test name
Test status
Simulation time 168452825 ps
CPU time 2.31 seconds
Started Apr 18 12:35:38 PM PDT 24
Finished Apr 18 12:35:41 PM PDT 24
Peak memory 214412 kb
Host smart-f1baa2c1-d586-4b6b-b31c-dca37391ba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149122210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.149122210
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3965698967
Short name T805
Test name
Test status
Simulation time 1294968257 ps
CPU time 23.58 seconds
Started Apr 18 12:35:20 PM PDT 24
Finished Apr 18 12:35:45 PM PDT 24
Peak memory 209480 kb
Host smart-3cbcbd80-3a8c-4632-bf54-6a1184882668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965698967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3965698967
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1830425548
Short name T49
Test name
Test status
Simulation time 86369323 ps
CPU time 3.88 seconds
Started Apr 18 12:35:25 PM PDT 24
Finished Apr 18 12:35:29 PM PDT 24
Peak memory 206380 kb
Host smart-2d99af10-2fd9-4c21-a3d1-c0f13fe65ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830425548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1830425548
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3109331614
Short name T719
Test name
Test status
Simulation time 87770169 ps
CPU time 3.64 seconds
Started Apr 18 12:35:29 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 206952 kb
Host smart-c24b1d77-9d65-4670-854d-952e9e534520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109331614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3109331614
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3755219209
Short name T812
Test name
Test status
Simulation time 171176438 ps
CPU time 4.93 seconds
Started Apr 18 12:35:27 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 209032 kb
Host smart-655be7f9-bcad-4863-9060-39d6cc3b957a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755219209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3755219209
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.581730307
Short name T766
Test name
Test status
Simulation time 76456889 ps
CPU time 2.35 seconds
Started Apr 18 12:35:27 PM PDT 24
Finished Apr 18 12:35:31 PM PDT 24
Peak memory 206960 kb
Host smart-f52c4686-90cb-4c62-a407-b58e6e75ac49
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581730307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.581730307
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.4075606410
Short name T586
Test name
Test status
Simulation time 55919574 ps
CPU time 2.92 seconds
Started Apr 18 12:35:32 PM PDT 24
Finished Apr 18 12:35:36 PM PDT 24
Peak memory 208116 kb
Host smart-06eb5258-43a0-44e4-b8e2-0a9ae5536a6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075606410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4075606410
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1384120259
Short name T859
Test name
Test status
Simulation time 280269113 ps
CPU time 2.73 seconds
Started Apr 18 12:35:27 PM PDT 24
Finished Apr 18 12:35:31 PM PDT 24
Peak memory 209948 kb
Host smart-5151f6a7-1630-441e-993e-c31c60ab0c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384120259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1384120259
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.736149348
Short name T692
Test name
Test status
Simulation time 120510934 ps
CPU time 4.52 seconds
Started Apr 18 12:35:16 PM PDT 24
Finished Apr 18 12:35:21 PM PDT 24
Peak memory 208784 kb
Host smart-2a025fba-7ddf-4313-a22f-91dbee2cc459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736149348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.736149348
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1089350913
Short name T546
Test name
Test status
Simulation time 10856134347 ps
CPU time 26.37 seconds
Started Apr 18 12:35:39 PM PDT 24
Finished Apr 18 12:36:06 PM PDT 24
Peak memory 218072 kb
Host smart-71bf682c-bb30-4d39-abba-f6ed98b4cf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089350913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1089350913
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3483495987
Short name T842
Test name
Test status
Simulation time 354047593 ps
CPU time 3.64 seconds
Started Apr 18 12:35:15 PM PDT 24
Finished Apr 18 12:35:19 PM PDT 24
Peak memory 210608 kb
Host smart-294c9107-6dff-4c54-a0a7-ed4981c7222c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483495987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3483495987
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1386939276
Short name T607
Test name
Test status
Simulation time 27832878 ps
CPU time 0.93 seconds
Started Apr 18 12:35:29 PM PDT 24
Finished Apr 18 12:35:31 PM PDT 24
Peak memory 206320 kb
Host smart-1b864bf8-72e7-49c8-bad7-1c507447a3fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386939276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1386939276
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.4051228116
Short name T698
Test name
Test status
Simulation time 155542930 ps
CPU time 3.66 seconds
Started Apr 18 12:35:24 PM PDT 24
Finished Apr 18 12:35:29 PM PDT 24
Peak memory 217552 kb
Host smart-8163b1bc-0903-480a-a818-3e54e37dfd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051228116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.4051228116
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2460350200
Short name T654
Test name
Test status
Simulation time 867242406 ps
CPU time 3.92 seconds
Started Apr 18 12:35:38 PM PDT 24
Finished Apr 18 12:35:43 PM PDT 24
Peak memory 218604 kb
Host smart-4b038851-8c2d-4ec1-a80b-26605be21738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460350200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2460350200
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3002095452
Short name T801
Test name
Test status
Simulation time 417923126 ps
CPU time 3.24 seconds
Started Apr 18 12:35:24 PM PDT 24
Finished Apr 18 12:35:28 PM PDT 24
Peak memory 210012 kb
Host smart-c8d89261-154a-4dc3-ba2d-8fab11878b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002095452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3002095452
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.582959450
Short name T361
Test name
Test status
Simulation time 731887551 ps
CPU time 10.83 seconds
Started Apr 18 12:35:21 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 209536 kb
Host smart-93481330-4874-4192-877b-1d361082c51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582959450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.582959450
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3682898021
Short name T877
Test name
Test status
Simulation time 117647558 ps
CPU time 2.36 seconds
Started Apr 18 12:35:27 PM PDT 24
Finished Apr 18 12:35:30 PM PDT 24
Peak memory 206924 kb
Host smart-4683a36a-ec9a-4859-a923-39b40c55e8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682898021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3682898021
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2169196048
Short name T15
Test name
Test status
Simulation time 570381353 ps
CPU time 11.86 seconds
Started Apr 18 12:35:16 PM PDT 24
Finished Apr 18 12:35:29 PM PDT 24
Peak memory 208620 kb
Host smart-1712dce3-5d6f-4950-8610-efe719aea44c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169196048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2169196048
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1945607679
Short name T802
Test name
Test status
Simulation time 933633252 ps
CPU time 16.88 seconds
Started Apr 18 12:35:28 PM PDT 24
Finished Apr 18 12:35:46 PM PDT 24
Peak memory 208308 kb
Host smart-aa1cfab3-6dff-40f6-93f0-b4eac32bf772
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945607679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1945607679
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2043754405
Short name T507
Test name
Test status
Simulation time 75056464 ps
CPU time 1.75 seconds
Started Apr 18 12:35:33 PM PDT 24
Finished Apr 18 12:35:36 PM PDT 24
Peak memory 207184 kb
Host smart-a863a1c0-22a1-41e1-9c51-7d63d7bd31ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043754405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2043754405
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.937828377
Short name T714
Test name
Test status
Simulation time 149887294 ps
CPU time 2.28 seconds
Started Apr 18 12:35:29 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 209288 kb
Host smart-b4424e9d-0fb7-4b9d-8455-f8d32fb55fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937828377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.937828377
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3171334597
Short name T510
Test name
Test status
Simulation time 38768973 ps
CPU time 2.46 seconds
Started Apr 18 12:35:22 PM PDT 24
Finished Apr 18 12:35:26 PM PDT 24
Peak memory 207324 kb
Host smart-13cfadd1-423e-4106-bf65-7410610c161f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171334597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3171334597
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3009352831
Short name T353
Test name
Test status
Simulation time 3359935557 ps
CPU time 47.86 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:36:19 PM PDT 24
Peak memory 216920 kb
Host smart-ec71a4b8-57c2-4f99-bd59-a755b279c43b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009352831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3009352831
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3333675820
Short name T126
Test name
Test status
Simulation time 144698879 ps
CPU time 10.33 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:42 PM PDT 24
Peak memory 222896 kb
Host smart-9f948766-026a-4128-8af9-7ae269838a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333675820 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3333675820
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3780452028
Short name T368
Test name
Test status
Simulation time 188680514 ps
CPU time 3.44 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:36 PM PDT 24
Peak memory 210056 kb
Host smart-df448c11-18b8-41e8-b7cd-6e649f0f9633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780452028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3780452028
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3089445655
Short name T124
Test name
Test status
Simulation time 86979160 ps
CPU time 2.14 seconds
Started Apr 18 12:35:25 PM PDT 24
Finished Apr 18 12:35:28 PM PDT 24
Peak memory 210044 kb
Host smart-ec05d913-515e-4683-9664-0ff48a293062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089445655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3089445655
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.881290910
Short name T484
Test name
Test status
Simulation time 35843034 ps
CPU time 0.72 seconds
Started Apr 18 12:34:06 PM PDT 24
Finished Apr 18 12:34:08 PM PDT 24
Peak memory 206244 kb
Host smart-9aa7a46d-3214-4153-904e-5b41f4e73193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881290910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.881290910
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2953717754
Short name T611
Test name
Test status
Simulation time 47405715 ps
CPU time 3.14 seconds
Started Apr 18 12:33:59 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 210436 kb
Host smart-f221f99d-bdde-4da2-8406-f1651712a7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953717754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2953717754
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.180428932
Short name T730
Test name
Test status
Simulation time 53514443 ps
CPU time 2.22 seconds
Started Apr 18 12:33:59 PM PDT 24
Finished Apr 18 12:34:04 PM PDT 24
Peak memory 207608 kb
Host smart-9bfa212f-9353-47f1-ad0c-063aeb0de405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180428932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.180428932
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1098078149
Short name T823
Test name
Test status
Simulation time 767773632 ps
CPU time 5.27 seconds
Started Apr 18 12:34:00 PM PDT 24
Finished Apr 18 12:34:08 PM PDT 24
Peak memory 207204 kb
Host smart-98769490-4f56-4443-a072-5a0b268ffc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098078149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1098078149
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1591855210
Short name T14
Test name
Test status
Simulation time 180558939 ps
CPU time 5.99 seconds
Started Apr 18 12:33:59 PM PDT 24
Finished Apr 18 12:34:08 PM PDT 24
Peak memory 214504 kb
Host smart-e14bdc43-59e1-4dd5-af2f-0171e697c925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591855210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1591855210
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1552749925
Short name T861
Test name
Test status
Simulation time 156677266 ps
CPU time 5.37 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 208004 kb
Host smart-78f231bc-c4fe-44d4-aa82-e9e978c5dffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552749925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1552749925
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.33990409
Short name T559
Test name
Test status
Simulation time 48778824 ps
CPU time 2.61 seconds
Started Apr 18 12:34:01 PM PDT 24
Finished Apr 18 12:34:06 PM PDT 24
Peak memory 207080 kb
Host smart-bef432d3-f893-402a-b822-9b8fcb051f56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33990409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.33990409
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3114254150
Short name T186
Test name
Test status
Simulation time 208553041 ps
CPU time 5.9 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 207988 kb
Host smart-cf3c9f78-14c2-4154-8fc3-af7f5fd24b2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114254150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3114254150
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2829164963
Short name T234
Test name
Test status
Simulation time 607247310 ps
CPU time 5.01 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 208952 kb
Host smart-0b9219ae-89b8-41cd-9d92-4cbaee38ce3a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829164963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2829164963
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3643000944
Short name T583
Test name
Test status
Simulation time 32180238 ps
CPU time 1.9 seconds
Started Apr 18 12:34:03 PM PDT 24
Finished Apr 18 12:34:07 PM PDT 24
Peak memory 208244 kb
Host smart-f3dc3055-460b-41b5-82a0-4e053ad22eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643000944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3643000944
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3402510288
Short name T221
Test name
Test status
Simulation time 113263318 ps
CPU time 2.23 seconds
Started Apr 18 12:34:01 PM PDT 24
Finished Apr 18 12:34:05 PM PDT 24
Peak memory 207120 kb
Host smart-f3c885dc-ee40-4226-927b-11eca4bf3913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402510288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3402510288
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1037208915
Short name T199
Test name
Test status
Simulation time 572238085 ps
CPU time 19.77 seconds
Started Apr 18 12:34:03 PM PDT 24
Finished Apr 18 12:34:25 PM PDT 24
Peak memory 222616 kb
Host smart-0dd7b61f-6fd1-4322-bdab-b2792db5dbe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037208915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1037208915
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1400303153
Short name T885
Test name
Test status
Simulation time 156527724 ps
CPU time 5.94 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 223364 kb
Host smart-46c11de1-8bcd-4221-be10-f97d8630fd0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400303153 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1400303153
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3612482934
Short name T486
Test name
Test status
Simulation time 208669166 ps
CPU time 5.73 seconds
Started Apr 18 12:34:03 PM PDT 24
Finished Apr 18 12:34:11 PM PDT 24
Peak memory 214564 kb
Host smart-38d54b67-6e9a-4b6b-a497-97ef093ad6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612482934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3612482934
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3503428618
Short name T51
Test name
Test status
Simulation time 758929001 ps
CPU time 2.9 seconds
Started Apr 18 12:34:02 PM PDT 24
Finished Apr 18 12:34:07 PM PDT 24
Peak memory 210028 kb
Host smart-774172a5-4b5f-4530-afad-ce32760def9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503428618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3503428618
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3695289697
Short name T213
Test name
Test status
Simulation time 21321981 ps
CPU time 1.06 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:32 PM PDT 24
Peak memory 206304 kb
Host smart-c11b42fa-9772-4263-adbe-b06250f50b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695289697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3695289697
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4216924273
Short name T839
Test name
Test status
Simulation time 106535641 ps
CPU time 2 seconds
Started Apr 18 12:35:27 PM PDT 24
Finished Apr 18 12:35:30 PM PDT 24
Peak memory 214564 kb
Host smart-3b6c773f-9053-4e2c-a95d-988342922bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216924273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4216924273
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2977646090
Short name T732
Test name
Test status
Simulation time 426346992 ps
CPU time 13.23 seconds
Started Apr 18 12:35:28 PM PDT 24
Finished Apr 18 12:35:42 PM PDT 24
Peak memory 214512 kb
Host smart-a1339b02-7d40-4094-909f-5a90e9244ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977646090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2977646090
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1512342739
Short name T803
Test name
Test status
Simulation time 325791522 ps
CPU time 5.17 seconds
Started Apr 18 12:35:28 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 209736 kb
Host smart-ea02d40c-b904-4e0e-bedc-661d77d3d887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512342739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1512342739
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2210390885
Short name T881
Test name
Test status
Simulation time 52437019 ps
CPU time 1.92 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 206356 kb
Host smart-a024f701-7555-46b0-9f1e-c1ed6ca1bedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210390885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2210390885
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2844235265
Short name T498
Test name
Test status
Simulation time 101566179 ps
CPU time 5.28 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:37 PM PDT 24
Peak memory 207712 kb
Host smart-fec753bf-1f1a-4e92-b46a-7aa24485c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844235265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2844235265
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2679006758
Short name T557
Test name
Test status
Simulation time 2431618024 ps
CPU time 15.95 seconds
Started Apr 18 12:35:28 PM PDT 24
Finished Apr 18 12:35:45 PM PDT 24
Peak memory 208384 kb
Host smart-61863af2-9c40-4e00-9976-3468fb4abdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679006758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2679006758
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2460119664
Short name T495
Test name
Test status
Simulation time 154800233 ps
CPU time 3.08 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:35:45 PM PDT 24
Peak memory 207108 kb
Host smart-a80edf14-abd8-4ca2-b7db-2b7981606fa5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460119664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2460119664
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2796135300
Short name T905
Test name
Test status
Simulation time 106754414 ps
CPU time 3.55 seconds
Started Apr 18 12:35:45 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 207076 kb
Host smart-de1bb3f2-0eba-4f29-bb6f-c861f93dc29b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796135300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2796135300
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2812864974
Short name T462
Test name
Test status
Simulation time 822079865 ps
CPU time 6.04 seconds
Started Apr 18 12:35:23 PM PDT 24
Finished Apr 18 12:35:30 PM PDT 24
Peak memory 209124 kb
Host smart-eafa5f82-cd28-455e-bf23-73fea34e2e63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812864974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2812864974
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2091440488
Short name T679
Test name
Test status
Simulation time 186969980 ps
CPU time 4.25 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:35:41 PM PDT 24
Peak memory 214588 kb
Host smart-04c84687-eae6-4310-bd40-4971b015027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091440488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2091440488
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2530382764
Short name T649
Test name
Test status
Simulation time 247293274 ps
CPU time 3.02 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:35:44 PM PDT 24
Peak memory 206864 kb
Host smart-6a939d93-1c70-49a5-b5c8-c954d29c3228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530382764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2530382764
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.4292817696
Short name T874
Test name
Test status
Simulation time 570879024 ps
CPU time 6.69 seconds
Started Apr 18 12:35:23 PM PDT 24
Finished Apr 18 12:35:31 PM PDT 24
Peak memory 214508 kb
Host smart-872138ef-e1c9-496e-950c-32c15deda23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292817696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4292817696
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.255370035
Short name T620
Test name
Test status
Simulation time 144420016 ps
CPU time 3.54 seconds
Started Apr 18 12:35:25 PM PDT 24
Finished Apr 18 12:35:29 PM PDT 24
Peak memory 210752 kb
Host smart-56ca2829-c93b-49b2-b02b-0fdc7df7f8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255370035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.255370035
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.694939881
Short name T794
Test name
Test status
Simulation time 306720792 ps
CPU time 0.91 seconds
Started Apr 18 12:35:29 PM PDT 24
Finished Apr 18 12:35:32 PM PDT 24
Peak memory 206272 kb
Host smart-34098e19-6ab2-4e60-b02d-a285db322e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694939881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.694939881
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2895310877
Short name T425
Test name
Test status
Simulation time 49965390 ps
CPU time 3.73 seconds
Started Apr 18 12:35:22 PM PDT 24
Finished Apr 18 12:35:27 PM PDT 24
Peak memory 214536 kb
Host smart-4f62d7fb-d0c2-490a-8ff3-77ccdb9d2b81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2895310877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2895310877
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.475436662
Short name T136
Test name
Test status
Simulation time 272079975 ps
CPU time 2.42 seconds
Started Apr 18 12:35:19 PM PDT 24
Finished Apr 18 12:35:22 PM PDT 24
Peak memory 207492 kb
Host smart-1b621abe-46cf-4d3d-bead-ddb80818d2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475436662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.475436662
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.187540141
Short name T390
Test name
Test status
Simulation time 103582014 ps
CPU time 4.14 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:36 PM PDT 24
Peak memory 214536 kb
Host smart-12370f18-b212-4048-ad6c-8bcc488300f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187540141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.187540141
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3660464400
Short name T322
Test name
Test status
Simulation time 979060463 ps
CPU time 8.77 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:58 PM PDT 24
Peak memory 210840 kb
Host smart-61452a54-3ddb-4a3d-aada-02ed56263272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660464400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3660464400
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2947163281
Short name T566
Test name
Test status
Simulation time 121915508 ps
CPU time 3.5 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:35 PM PDT 24
Peak memory 209044 kb
Host smart-8cf3a4bc-88f4-4eed-b2b7-6058e8318d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947163281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2947163281
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3770700203
Short name T741
Test name
Test status
Simulation time 298408001 ps
CPU time 10.25 seconds
Started Apr 18 12:35:25 PM PDT 24
Finished Apr 18 12:35:36 PM PDT 24
Peak memory 214652 kb
Host smart-7ba76730-e7c8-4f62-8b16-2beb2131666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770700203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3770700203
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1739351229
Short name T233
Test name
Test status
Simulation time 97384330 ps
CPU time 4.26 seconds
Started Apr 18 12:35:32 PM PDT 24
Finished Apr 18 12:35:38 PM PDT 24
Peak memory 208972 kb
Host smart-69018e6d-4dfc-493f-b3cb-42ac60b8a945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739351229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1739351229
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3609056221
Short name T408
Test name
Test status
Simulation time 860261993 ps
CPU time 6.67 seconds
Started Apr 18 12:35:43 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 208256 kb
Host smart-7e77a24b-b048-4806-ae94-5d737e7917d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609056221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3609056221
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.563264946
Short name T623
Test name
Test status
Simulation time 229345066 ps
CPU time 3.21 seconds
Started Apr 18 12:35:34 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 208724 kb
Host smart-ce5b51aa-4fbc-4cca-a9a5-c8c56afabdc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563264946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.563264946
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1470201485
Short name T558
Test name
Test status
Simulation time 177975958 ps
CPU time 2.26 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 214464 kb
Host smart-704f5024-4886-4dd4-81fd-5f7f8a683f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470201485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1470201485
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2653468665
Short name T717
Test name
Test status
Simulation time 55330612 ps
CPU time 2.41 seconds
Started Apr 18 12:35:25 PM PDT 24
Finished Apr 18 12:35:28 PM PDT 24
Peak memory 206908 kb
Host smart-d07b96a2-c34c-4600-bc57-bf24700ebaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653468665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2653468665
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2485206542
Short name T578
Test name
Test status
Simulation time 184411789 ps
CPU time 5.09 seconds
Started Apr 18 12:35:32 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 208240 kb
Host smart-56f85d85-49b9-4546-a01f-4c395bf856e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485206542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2485206542
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4259862744
Short name T218
Test name
Test status
Simulation time 39362790 ps
CPU time 1.61 seconds
Started Apr 18 12:35:39 PM PDT 24
Finished Apr 18 12:35:42 PM PDT 24
Peak memory 210460 kb
Host smart-e7e537a6-0f0b-4897-a575-fdd3d17797f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259862744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4259862744
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2951582388
Short name T187
Test name
Test status
Simulation time 29327620 ps
CPU time 0.74 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:35:37 PM PDT 24
Peak memory 206208 kb
Host smart-95b8f867-5c96-4850-9369-397451860935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951582388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2951582388
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2779626165
Short name T624
Test name
Test status
Simulation time 108617161 ps
CPU time 3.5 seconds
Started Apr 18 12:35:29 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 208884 kb
Host smart-27a7bb1f-0b2c-4465-be64-e8b55f55fd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779626165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2779626165
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2525003411
Short name T88
Test name
Test status
Simulation time 349021525 ps
CPU time 4.03 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:35 PM PDT 24
Peak memory 208748 kb
Host smart-76c12ca5-826f-4ae0-b05a-c465e6acb137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525003411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2525003411
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3137542156
Short name T266
Test name
Test status
Simulation time 105290313 ps
CPU time 4.99 seconds
Started Apr 18 12:35:29 PM PDT 24
Finished Apr 18 12:35:35 PM PDT 24
Peak memory 214488 kb
Host smart-a354bd30-0634-46d3-be8f-334bcbcec719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137542156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3137542156
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3259394767
Short name T243
Test name
Test status
Simulation time 1605097368 ps
CPU time 4.05 seconds
Started Apr 18 12:35:44 PM PDT 24
Finished Apr 18 12:35:49 PM PDT 24
Peak memory 214472 kb
Host smart-c2c76de7-aa17-41ad-b5ad-92777aa45d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259394767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3259394767
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.452688643
Short name T666
Test name
Test status
Simulation time 1709329070 ps
CPU time 12 seconds
Started Apr 18 12:35:43 PM PDT 24
Finished Apr 18 12:35:56 PM PDT 24
Peak memory 214508 kb
Host smart-7fe937ff-66e5-46f6-84cc-4639682335dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452688643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.452688643
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3785283858
Short name T845
Test name
Test status
Simulation time 149516626 ps
CPU time 3.41 seconds
Started Apr 18 12:35:41 PM PDT 24
Finished Apr 18 12:35:46 PM PDT 24
Peak memory 207680 kb
Host smart-e0dab787-4317-4b2b-9dac-7e4ef35d09bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785283858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3785283858
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.776735790
Short name T850
Test name
Test status
Simulation time 73776372 ps
CPU time 2.5 seconds
Started Apr 18 12:35:37 PM PDT 24
Finished Apr 18 12:35:40 PM PDT 24
Peak memory 206836 kb
Host smart-d5521c5a-90eb-444a-a854-925985d10bb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776735790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.776735790
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2373682953
Short name T588
Test name
Test status
Simulation time 406920972 ps
CPU time 5.72 seconds
Started Apr 18 12:35:32 PM PDT 24
Finished Apr 18 12:35:40 PM PDT 24
Peak memory 209080 kb
Host smart-fd6461e1-6941-4fee-aaa4-b8e40f7dd52c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373682953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2373682953
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1951538018
Short name T521
Test name
Test status
Simulation time 550966152 ps
CPU time 6 seconds
Started Apr 18 12:35:51 PM PDT 24
Finished Apr 18 12:35:58 PM PDT 24
Peak memory 208132 kb
Host smart-3315538c-95f5-4c43-845a-c1465fa6d9ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951538018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1951538018
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.143252574
Short name T875
Test name
Test status
Simulation time 252187500 ps
CPU time 2.83 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:35 PM PDT 24
Peak memory 209324 kb
Host smart-812fa919-2b91-45d3-8f89-7dc5431f463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143252574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.143252574
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2731619599
Short name T568
Test name
Test status
Simulation time 192023625 ps
CPU time 4.97 seconds
Started Apr 18 12:35:44 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 207920 kb
Host smart-2e28d91d-4631-4488-84c5-45b0da5d947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731619599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2731619599
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2262666681
Short name T382
Test name
Test status
Simulation time 1239358521 ps
CPU time 15.02 seconds
Started Apr 18 12:35:26 PM PDT 24
Finished Apr 18 12:35:42 PM PDT 24
Peak memory 215344 kb
Host smart-ea2a0e6f-e3b0-4846-b171-5cd4fde053bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262666681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2262666681
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2167568425
Short name T57
Test name
Test status
Simulation time 2841244306 ps
CPU time 33.73 seconds
Started Apr 18 12:35:39 PM PDT 24
Finished Apr 18 12:36:14 PM PDT 24
Peak memory 222884 kb
Host smart-c261ca5d-f505-467e-aeae-a6152b1853f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167568425 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2167568425
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3815778751
Short name T310
Test name
Test status
Simulation time 8395867605 ps
CPU time 77.41 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:36:54 PM PDT 24
Peak memory 219376 kb
Host smart-0101f18a-b155-4815-abcf-5d1cd8fa71bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815778751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3815778751
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1050621317
Short name T210
Test name
Test status
Simulation time 40210767 ps
CPU time 1.91 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:35:43 PM PDT 24
Peak memory 210060 kb
Host smart-62d177b3-ee73-46a6-b055-22f5a53266c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050621317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1050621317
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3050217641
Short name T600
Test name
Test status
Simulation time 15023529 ps
CPU time 0.94 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 206404 kb
Host smart-a34090be-cacb-4819-80ed-b47e4b7b64bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050217641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3050217641
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2232081556
Short name T800
Test name
Test status
Simulation time 115679527 ps
CPU time 3.22 seconds
Started Apr 18 12:35:50 PM PDT 24
Finished Apr 18 12:35:59 PM PDT 24
Peak memory 210196 kb
Host smart-80ae15e8-1632-4e2c-940b-c8371c3ac7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232081556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2232081556
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2295733505
Short name T63
Test name
Test status
Simulation time 393840206 ps
CPU time 4.91 seconds
Started Apr 18 12:35:43 PM PDT 24
Finished Apr 18 12:35:49 PM PDT 24
Peak memory 214544 kb
Host smart-054b23cd-c757-4dcf-afd5-25b9648f16fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295733505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2295733505
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1771339463
Short name T24
Test name
Test status
Simulation time 1988621933 ps
CPU time 51.69 seconds
Started Apr 18 12:35:37 PM PDT 24
Finished Apr 18 12:36:30 PM PDT 24
Peak memory 209160 kb
Host smart-bc845917-41c0-4a9b-a498-f69bc0952562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771339463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1771339463
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.680396521
Short name T323
Test name
Test status
Simulation time 569873247 ps
CPU time 4.9 seconds
Started Apr 18 12:35:34 PM PDT 24
Finished Apr 18 12:35:41 PM PDT 24
Peak memory 214656 kb
Host smart-4186a5d9-d661-44e2-bf84-d0d2d7a1877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680396521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.680396521
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.612161641
Short name T359
Test name
Test status
Simulation time 294408823 ps
CPU time 5.7 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 220032 kb
Host smart-ca97aa33-23b7-49d3-9c53-cd641d1cb209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612161641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.612161641
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3646089662
Short name T594
Test name
Test status
Simulation time 112849615 ps
CPU time 4.91 seconds
Started Apr 18 12:35:26 PM PDT 24
Finished Apr 18 12:35:32 PM PDT 24
Peak memory 210864 kb
Host smart-afc411d3-a368-4fba-88f6-80fda058b003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646089662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3646089662
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3058602727
Short name T508
Test name
Test status
Simulation time 160296322 ps
CPU time 5.15 seconds
Started Apr 18 12:35:51 PM PDT 24
Finished Apr 18 12:35:57 PM PDT 24
Peak memory 208920 kb
Host smart-30618b9d-57f6-4dc4-ada8-42d54b20c887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058602727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3058602727
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2025382873
Short name T296
Test name
Test status
Simulation time 318219378 ps
CPU time 3.3 seconds
Started Apr 18 12:35:45 PM PDT 24
Finished Apr 18 12:35:49 PM PDT 24
Peak memory 206828 kb
Host smart-13e4816e-aaf8-462a-88c1-8c28cb6bb69d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025382873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2025382873
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.215400704
Short name T746
Test name
Test status
Simulation time 21116775 ps
CPU time 1.91 seconds
Started Apr 18 12:35:27 PM PDT 24
Finished Apr 18 12:35:30 PM PDT 24
Peak memory 206964 kb
Host smart-30208f80-aaca-4504-a2a6-86c126a30ec7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215400704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.215400704
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1047961456
Short name T778
Test name
Test status
Simulation time 116606080 ps
CPU time 2.51 seconds
Started Apr 18 12:35:34 PM PDT 24
Finished Apr 18 12:35:38 PM PDT 24
Peak memory 207644 kb
Host smart-9ebdef11-b56c-405c-a9a1-8928ec27fe06
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047961456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1047961456
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.523662106
Short name T667
Test name
Test status
Simulation time 95581422 ps
CPU time 2.76 seconds
Started Apr 18 12:35:50 PM PDT 24
Finished Apr 18 12:35:54 PM PDT 24
Peak memory 207892 kb
Host smart-f4fa37f2-6798-42d4-b10e-8a62b8f4e24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523662106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.523662106
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2656542433
Short name T644
Test name
Test status
Simulation time 111274721 ps
CPU time 3.21 seconds
Started Apr 18 12:35:42 PM PDT 24
Finished Apr 18 12:35:46 PM PDT 24
Peak memory 207892 kb
Host smart-bbfa0b8b-0785-4c67-8dcb-83c01e271abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656542433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2656542433
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1338025346
Short name T615
Test name
Test status
Simulation time 569080146 ps
CPU time 19.78 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 215464 kb
Host smart-33dce059-5ac8-47e7-b146-fc19ead28832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338025346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1338025346
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.279048561
Short name T328
Test name
Test status
Simulation time 709933882 ps
CPU time 4.77 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:35:42 PM PDT 24
Peak memory 207696 kb
Host smart-bc227d3b-8c5e-4ce8-904c-7ccac2f5b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279048561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.279048561
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.566526238
Short name T211
Test name
Test status
Simulation time 325786429 ps
CPU time 2.84 seconds
Started Apr 18 12:35:43 PM PDT 24
Finished Apr 18 12:35:48 PM PDT 24
Peak memory 209888 kb
Host smart-daf0e210-b819-47ba-8fcc-83ffb37896c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566526238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.566526238
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3854757758
Short name T454
Test name
Test status
Simulation time 16602650 ps
CPU time 0.73 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:35:41 PM PDT 24
Peak memory 206084 kb
Host smart-0d5fd374-59b6-4d2e-bd15-b750634e9f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854757758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3854757758
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1370052064
Short name T188
Test name
Test status
Simulation time 270113051 ps
CPU time 2.99 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:36 PM PDT 24
Peak memory 214488 kb
Host smart-c92bbd66-99b0-4ee3-90b9-d274384771ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370052064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1370052064
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.246791805
Short name T872
Test name
Test status
Simulation time 1499336315 ps
CPU time 45.73 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:36:37 PM PDT 24
Peak memory 222704 kb
Host smart-be36a964-34c9-4494-935c-910ec7c15893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246791805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.246791805
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.235094553
Short name T612
Test name
Test status
Simulation time 157031552 ps
CPU time 3.86 seconds
Started Apr 18 12:35:29 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 214640 kb
Host smart-e1a8fbc5-e79f-454e-84f3-e055c07458a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235094553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.235094553
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1788218855
Short name T2
Test name
Test status
Simulation time 597478212 ps
CPU time 5.68 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:35:42 PM PDT 24
Peak memory 221532 kb
Host smart-430755ec-4b9f-485e-803f-16c16409f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788218855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1788218855
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3038856570
Short name T375
Test name
Test status
Simulation time 203369045 ps
CPU time 5.31 seconds
Started Apr 18 12:35:32 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 214452 kb
Host smart-bd9cb758-c282-4e94-89a7-2743921efc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038856570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3038856570
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2381147185
Short name T660
Test name
Test status
Simulation time 623434532 ps
CPU time 2.95 seconds
Started Apr 18 12:35:38 PM PDT 24
Finished Apr 18 12:35:42 PM PDT 24
Peak memory 222776 kb
Host smart-df9f5144-9d84-4d50-91f0-3a5c50f59509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381147185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2381147185
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3347332690
Short name T336
Test name
Test status
Simulation time 80962009 ps
CPU time 4.11 seconds
Started Apr 18 12:35:43 PM PDT 24
Finished Apr 18 12:35:49 PM PDT 24
Peak memory 209236 kb
Host smart-967075c5-b77f-46b2-a615-c8febf934e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347332690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3347332690
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2795587829
Short name T513
Test name
Test status
Simulation time 50180426 ps
CPU time 2.75 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:52 PM PDT 24
Peak memory 207008 kb
Host smart-4b7286ef-db6e-4e1e-84c6-d0619c5d18fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795587829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2795587829
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.45618504
Short name T728
Test name
Test status
Simulation time 983182703 ps
CPU time 7.65 seconds
Started Apr 18 12:35:32 PM PDT 24
Finished Apr 18 12:35:42 PM PDT 24
Peak memory 208372 kb
Host smart-2859a6db-2651-4d4b-840d-f50e09b46037
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45618504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.45618504
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.412382536
Short name T847
Test name
Test status
Simulation time 274924990 ps
CPU time 3.27 seconds
Started Apr 18 12:35:39 PM PDT 24
Finished Apr 18 12:35:43 PM PDT 24
Peak memory 207148 kb
Host smart-3b2fb564-3891-4289-9c67-056dd6a5eb78
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412382536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.412382536
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.877439665
Short name T897
Test name
Test status
Simulation time 280490656 ps
CPU time 7.54 seconds
Started Apr 18 12:35:44 PM PDT 24
Finished Apr 18 12:35:52 PM PDT 24
Peak memory 208080 kb
Host smart-68d401f9-b6cb-4d6e-921a-f2f81c37dc82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877439665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.877439665
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2417900233
Short name T562
Test name
Test status
Simulation time 44967870 ps
CPU time 2.09 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:57 PM PDT 24
Peak memory 209588 kb
Host smart-3c860942-076d-4329-98e4-67c79383271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417900233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2417900233
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2063310128
Short name T554
Test name
Test status
Simulation time 446590318 ps
CPU time 2.08 seconds
Started Apr 18 12:35:31 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 208768 kb
Host smart-b48de5ac-25f1-4c90-911e-b3adf7dab577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063310128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2063310128
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2489527612
Short name T67
Test name
Test status
Simulation time 2890927834 ps
CPU time 55.84 seconds
Started Apr 18 12:35:34 PM PDT 24
Finished Apr 18 12:36:32 PM PDT 24
Peak memory 217500 kb
Host smart-cdeeee99-8fc1-4c8a-875f-f3dd11907ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489527612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2489527612
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1992884503
Short name T181
Test name
Test status
Simulation time 255179777 ps
CPU time 7.72 seconds
Started Apr 18 12:35:42 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 222944 kb
Host smart-182ebc23-caa2-4152-adc2-dbf261755cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992884503 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1992884503
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.571341573
Short name T312
Test name
Test status
Simulation time 128374576 ps
CPU time 5.74 seconds
Started Apr 18 12:35:46 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 210272 kb
Host smart-1e9299a9-5175-42fc-944e-962b139dfa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571341573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.571341573
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.191795476
Short name T110
Test name
Test status
Simulation time 190569936 ps
CPU time 1.85 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:33 PM PDT 24
Peak memory 210616 kb
Host smart-7da3d227-fd2f-4e9c-97be-38c8dbbb2389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191795476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.191795476
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1699709296
Short name T219
Test name
Test status
Simulation time 14660659 ps
CPU time 0.75 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:49 PM PDT 24
Peak memory 206172 kb
Host smart-eecd6180-dfc3-4c73-9ba9-ff2fbef9600d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699709296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1699709296
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2731290445
Short name T314
Test name
Test status
Simulation time 288078809 ps
CPU time 4.01 seconds
Started Apr 18 12:35:45 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 215184 kb
Host smart-b670086a-1961-4838-accd-ffb745a37bc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731290445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2731290445
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1262458916
Short name T31
Test name
Test status
Simulation time 118072181 ps
CPU time 5.01 seconds
Started Apr 18 12:35:39 PM PDT 24
Finished Apr 18 12:35:45 PM PDT 24
Peak memory 210384 kb
Host smart-064012ac-1c17-4d85-8de4-993bec449866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262458916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1262458916
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.799190913
Short name T601
Test name
Test status
Simulation time 556990883 ps
CPU time 4.49 seconds
Started Apr 18 12:35:39 PM PDT 24
Finished Apr 18 12:35:44 PM PDT 24
Peak memory 218604 kb
Host smart-cfadb948-5da4-46e9-bccb-da2eb9d67f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799190913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.799190913
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3620685802
Short name T739
Test name
Test status
Simulation time 111754055 ps
CPU time 4.75 seconds
Started Apr 18 12:35:46 PM PDT 24
Finished Apr 18 12:35:52 PM PDT 24
Peak memory 222764 kb
Host smart-e7b0f6c9-e806-4770-9698-1ff7c30bf346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620685802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3620685802
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1538204620
Short name T304
Test name
Test status
Simulation time 97530172 ps
CPU time 5 seconds
Started Apr 18 12:35:37 PM PDT 24
Finished Apr 18 12:35:43 PM PDT 24
Peak memory 222712 kb
Host smart-e34a884b-9094-4a9b-af0a-05f24248791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538204620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1538204620
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3263495840
Short name T457
Test name
Test status
Simulation time 244373016 ps
CPU time 3.36 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:58 PM PDT 24
Peak memory 214604 kb
Host smart-b9f5d5bb-191d-4d97-aa27-865022819a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263495840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3263495840
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1996901925
Short name T898
Test name
Test status
Simulation time 6035419417 ps
CPU time 14.21 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 209636 kb
Host smart-d3e694a9-8c04-4442-a028-7ee87ef257ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996901925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1996901925
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3796093081
Short name T829
Test name
Test status
Simulation time 3052324780 ps
CPU time 7.34 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:55 PM PDT 24
Peak memory 208724 kb
Host smart-d462c521-fe57-4ef6-a957-24c0afd8c167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796093081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3796093081
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.401020065
Short name T216
Test name
Test status
Simulation time 51094549 ps
CPU time 2.82 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:35:44 PM PDT 24
Peak memory 207024 kb
Host smart-d26bc3a5-edc4-4337-b03e-33c884c5444c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401020065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.401020065
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.360653951
Short name T709
Test name
Test status
Simulation time 77206339 ps
CPU time 1.76 seconds
Started Apr 18 12:35:44 PM PDT 24
Finished Apr 18 12:35:47 PM PDT 24
Peak memory 207748 kb
Host smart-39091fde-cb47-4c90-8b53-914a72ca381a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360653951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.360653951
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3847843509
Short name T434
Test name
Test status
Simulation time 132811098 ps
CPU time 2.53 seconds
Started Apr 18 12:35:51 PM PDT 24
Finished Apr 18 12:35:54 PM PDT 24
Peak memory 207552 kb
Host smart-9ed7eed3-c8c8-49a4-b7a6-f2f8e92f2e4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847843509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3847843509
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.746070248
Short name T643
Test name
Test status
Simulation time 104057993 ps
CPU time 3.42 seconds
Started Apr 18 12:35:42 PM PDT 24
Finished Apr 18 12:35:46 PM PDT 24
Peak memory 209076 kb
Host smart-2156cfe2-0b76-4e97-b35b-b8b812ff7b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746070248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.746070248
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.902031169
Short name T131
Test name
Test status
Simulation time 87910451 ps
CPU time 2.63 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 207116 kb
Host smart-efd153c4-f879-4de0-8f8e-bb91048e17bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902031169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.902031169
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2478695845
Short name T409
Test name
Test status
Simulation time 327231959 ps
CPU time 4.02 seconds
Started Apr 18 12:35:34 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 207620 kb
Host smart-738cd4c1-5cb1-4872-9c11-00c9827fb44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478695845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2478695845
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1922681109
Short name T95
Test name
Test status
Simulation time 39105215 ps
CPU time 1.84 seconds
Started Apr 18 12:35:30 PM PDT 24
Finished Apr 18 12:35:34 PM PDT 24
Peak memory 209688 kb
Host smart-a985f61c-c6e9-4b72-a1c0-effd05b57310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922681109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1922681109
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3935709335
Short name T626
Test name
Test status
Simulation time 26952823 ps
CPU time 0.88 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:49 PM PDT 24
Peak memory 206336 kb
Host smart-02ec71e1-1f45-4139-bc54-b3c15be48153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935709335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3935709335
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.309146183
Short name T900
Test name
Test status
Simulation time 205103461 ps
CPU time 2.02 seconds
Started Apr 18 12:35:51 PM PDT 24
Finished Apr 18 12:35:54 PM PDT 24
Peak memory 208320 kb
Host smart-3e1d37f7-4f39-4db9-834b-2591fcc5ee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309146183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.309146183
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1202397134
Short name T371
Test name
Test status
Simulation time 65092521 ps
CPU time 1.49 seconds
Started Apr 18 12:35:42 PM PDT 24
Finished Apr 18 12:35:44 PM PDT 24
Peak memory 208176 kb
Host smart-51a5d25a-fa31-4c95-9c15-de5a1da45629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202397134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1202397134
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4206322389
Short name T791
Test name
Test status
Simulation time 52407764 ps
CPU time 2.39 seconds
Started Apr 18 12:35:53 PM PDT 24
Finished Apr 18 12:35:56 PM PDT 24
Peak memory 209864 kb
Host smart-1e9ea6d4-9e61-4c99-8ecf-026c0f704c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206322389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4206322389
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3204870951
Short name T427
Test name
Test status
Simulation time 34490042331 ps
CPU time 93.14 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:37:09 PM PDT 24
Peak memory 209540 kb
Host smart-19fefceb-6a6a-4d50-a9a4-f53392242223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204870951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3204870951
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1074997315
Short name T101
Test name
Test status
Simulation time 135781002 ps
CPU time 5.05 seconds
Started Apr 18 12:35:56 PM PDT 24
Finished Apr 18 12:36:02 PM PDT 24
Peak memory 208544 kb
Host smart-5c7e4b80-1396-4137-9cf5-08850a22547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074997315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1074997315
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.700082180
Short name T502
Test name
Test status
Simulation time 31567051 ps
CPU time 2.14 seconds
Started Apr 18 12:35:34 PM PDT 24
Finished Apr 18 12:35:38 PM PDT 24
Peak memory 207040 kb
Host smart-5b6858d5-35e2-4456-9e5d-eb67793243e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700082180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.700082180
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1138359673
Short name T695
Test name
Test status
Simulation time 12384727246 ps
CPU time 16.62 seconds
Started Apr 18 12:35:46 PM PDT 24
Finished Apr 18 12:36:04 PM PDT 24
Peak memory 208148 kb
Host smart-a5641e68-084f-453a-99f7-be26b4483e5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138359673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1138359673
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2557293824
Short name T819
Test name
Test status
Simulation time 311011903 ps
CPU time 4.76 seconds
Started Apr 18 12:35:42 PM PDT 24
Finished Apr 18 12:35:48 PM PDT 24
Peak memory 208800 kb
Host smart-69436127-eb94-413d-8730-d25471bb3204
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557293824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2557293824
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.120308368
Short name T882
Test name
Test status
Simulation time 893436946 ps
CPU time 18.74 seconds
Started Apr 18 12:35:46 PM PDT 24
Finished Apr 18 12:36:06 PM PDT 24
Peak memory 209604 kb
Host smart-48614afa-bb4d-488a-81cc-2c1197344dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120308368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.120308368
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.363198949
Short name T867
Test name
Test status
Simulation time 172562025 ps
CPU time 2.25 seconds
Started Apr 18 12:35:57 PM PDT 24
Finished Apr 18 12:36:00 PM PDT 24
Peak memory 206772 kb
Host smart-b979ee2e-f511-4378-bc0e-08a819975600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363198949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.363198949
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2348908026
Short name T226
Test name
Test status
Simulation time 118876028 ps
CPU time 4.37 seconds
Started Apr 18 12:35:43 PM PDT 24
Finished Apr 18 12:35:49 PM PDT 24
Peak memory 209516 kb
Host smart-e5ef3569-14c2-4566-8581-ff89663985d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348908026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2348908026
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.4256384567
Short name T555
Test name
Test status
Simulation time 652606008 ps
CPU time 9.72 seconds
Started Apr 18 12:35:54 PM PDT 24
Finished Apr 18 12:36:04 PM PDT 24
Peak memory 208684 kb
Host smart-c7aca5ee-3a4b-4b98-9dea-8bb59b7404bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256384567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.4256384567
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.113579420
Short name T888
Test name
Test status
Simulation time 77748824 ps
CPU time 1.52 seconds
Started Apr 18 12:35:45 PM PDT 24
Finished Apr 18 12:35:48 PM PDT 24
Peak memory 209960 kb
Host smart-fca28d68-3a6b-4dc2-a69c-ddbd28987742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113579420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.113579420
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1146096536
Short name T94
Test name
Test status
Simulation time 67628527 ps
CPU time 0.83 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:49 PM PDT 24
Peak memory 206168 kb
Host smart-9c454acd-992c-47c0-a829-ce1e1af0898f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146096536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1146096536
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2900376283
Short name T107
Test name
Test status
Simulation time 71309390 ps
CPU time 3.05 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:52 PM PDT 24
Peak memory 214624 kb
Host smart-d9deb74b-3a1c-4445-9b07-0b4b3abd2e91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2900376283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2900376283
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3969703248
Short name T20
Test name
Test status
Simulation time 82570184 ps
CPU time 2.93 seconds
Started Apr 18 12:35:46 PM PDT 24
Finished Apr 18 12:36:00 PM PDT 24
Peak memory 222928 kb
Host smart-030db073-176e-40af-983d-6c4df4305e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969703248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3969703248
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1219130201
Short name T185
Test name
Test status
Simulation time 1273711372 ps
CPU time 9.6 seconds
Started Apr 18 12:35:52 PM PDT 24
Finished Apr 18 12:36:03 PM PDT 24
Peak memory 214512 kb
Host smart-4a2b9b71-9d81-42f5-9ff6-4e9f7d98ca92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219130201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1219130201
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.653998080
Short name T340
Test name
Test status
Simulation time 1430650287 ps
CPU time 15.71 seconds
Started Apr 18 12:35:58 PM PDT 24
Finished Apr 18 12:36:15 PM PDT 24
Peak memory 214488 kb
Host smart-6aeb0a3d-42fa-452d-be5f-67cd0930bfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653998080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.653998080
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4271380876
Short name T458
Test name
Test status
Simulation time 260187355 ps
CPU time 3.26 seconds
Started Apr 18 12:35:43 PM PDT 24
Finished Apr 18 12:35:48 PM PDT 24
Peak memory 208020 kb
Host smart-54f99001-482e-4357-b205-f7e6c3941390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271380876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4271380876
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.215075343
Short name T519
Test name
Test status
Simulation time 101908161 ps
CPU time 5.02 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:35:46 PM PDT 24
Peak memory 214512 kb
Host smart-4f1b27e6-7b03-4678-a222-e2bc3e0d2cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215075343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.215075343
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2260043310
Short name T133
Test name
Test status
Simulation time 127520912 ps
CPU time 3.67 seconds
Started Apr 18 12:35:35 PM PDT 24
Finished Apr 18 12:35:41 PM PDT 24
Peak memory 208848 kb
Host smart-74a05784-3831-459a-8721-227cc111cc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260043310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2260043310
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3846450180
Short name T231
Test name
Test status
Simulation time 141209998 ps
CPU time 2.42 seconds
Started Apr 18 12:35:50 PM PDT 24
Finished Apr 18 12:35:54 PM PDT 24
Peak memory 207056 kb
Host smart-439fdecc-8482-4ad1-b324-afd018a9ec3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846450180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3846450180
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2609072239
Short name T690
Test name
Test status
Simulation time 64440151 ps
CPU time 2.76 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 207012 kb
Host smart-a528ba25-4437-4d2e-8b81-95b00fdc3a77
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609072239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2609072239
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1257732568
Short name T206
Test name
Test status
Simulation time 85342499 ps
CPU time 1.86 seconds
Started Apr 18 12:35:45 PM PDT 24
Finished Apr 18 12:35:48 PM PDT 24
Peak memory 206952 kb
Host smart-ea3b6dec-fde7-4aee-af74-1604c7268e3c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257732568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1257732568
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3886207747
Short name T740
Test name
Test status
Simulation time 223838078 ps
CPU time 1.92 seconds
Started Apr 18 12:35:36 PM PDT 24
Finished Apr 18 12:35:40 PM PDT 24
Peak memory 209176 kb
Host smart-d7277b5d-f92b-4561-9e11-8d3cfb54deff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886207747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3886207747
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1220071373
Short name T636
Test name
Test status
Simulation time 298963911 ps
CPU time 2.79 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 208676 kb
Host smart-0b032abc-f382-4103-8bac-5db24b927c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220071373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1220071373
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2690373676
Short name T255
Test name
Test status
Simulation time 1151192645 ps
CPU time 31.76 seconds
Started Apr 18 12:35:43 PM PDT 24
Finished Apr 18 12:36:16 PM PDT 24
Peak memory 222860 kb
Host smart-9b053910-273e-47dc-bd5b-e6adc7fc2fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690373676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2690373676
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3668936007
Short name T355
Test name
Test status
Simulation time 195764228 ps
CPU time 4.76 seconds
Started Apr 18 12:35:45 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 214532 kb
Host smart-a9b5cb18-c00f-40d6-9428-79522d2488ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668936007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3668936007
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1460656396
Short name T1
Test name
Test status
Simulation time 107823616 ps
CPU time 1.82 seconds
Started Apr 18 12:35:54 PM PDT 24
Finished Apr 18 12:35:57 PM PDT 24
Peak memory 210112 kb
Host smart-00ac2851-a4c8-4a74-9373-53ce58a3dad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460656396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1460656396
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2652451375
Short name T828
Test name
Test status
Simulation time 22648787 ps
CPU time 0.73 seconds
Started Apr 18 12:35:38 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 206128 kb
Host smart-b3b922f9-7cc2-42d5-95fe-1dacb0b190c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652451375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2652451375
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3395219372
Short name T144
Test name
Test status
Simulation time 479268455 ps
CPU time 6.93 seconds
Started Apr 18 12:35:49 PM PDT 24
Finished Apr 18 12:35:57 PM PDT 24
Peak memory 214488 kb
Host smart-027f0240-2296-4bb0-90aa-97ec323f1547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395219372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3395219372
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.544973544
Short name T813
Test name
Test status
Simulation time 102742626 ps
CPU time 2 seconds
Started Apr 18 12:35:36 PM PDT 24
Finished Apr 18 12:35:39 PM PDT 24
Peak memory 210168 kb
Host smart-d633b5ca-6905-4290-a759-775f491c284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544973544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.544973544
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.591471570
Short name T736
Test name
Test status
Simulation time 221120037 ps
CPU time 2.99 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:35:44 PM PDT 24
Peak memory 209376 kb
Host smart-bebab1ac-2707-48f4-b300-20518f1d130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591471570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.591471570
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3655630054
Short name T362
Test name
Test status
Simulation time 13721561880 ps
CPU time 109.26 seconds
Started Apr 18 12:35:55 PM PDT 24
Finished Apr 18 12:37:45 PM PDT 24
Peak memory 214636 kb
Host smart-facf2ffc-0ce6-446e-8904-375e51ea46be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655630054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3655630054
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2159004635
Short name T248
Test name
Test status
Simulation time 102354260 ps
CPU time 2.32 seconds
Started Apr 18 12:35:51 PM PDT 24
Finished Apr 18 12:35:54 PM PDT 24
Peak memory 209056 kb
Host smart-590972f7-8f25-47c4-be05-cd22b7bc0d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159004635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2159004635
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.606897336
Short name T38
Test name
Test status
Simulation time 328254692 ps
CPU time 4.15 seconds
Started Apr 18 12:35:51 PM PDT 24
Finished Apr 18 12:35:56 PM PDT 24
Peak memory 207660 kb
Host smart-6f5ae764-dd35-45c9-a414-51f0bb648e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606897336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.606897336
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1904512785
Short name T539
Test name
Test status
Simulation time 399613347 ps
CPU time 5.62 seconds
Started Apr 18 12:35:39 PM PDT 24
Finished Apr 18 12:35:46 PM PDT 24
Peak memory 208280 kb
Host smart-73adc869-5012-4b08-b11f-72b581926f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904512785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1904512785
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.132229175
Short name T561
Test name
Test status
Simulation time 42926223 ps
CPU time 1.82 seconds
Started Apr 18 12:35:45 PM PDT 24
Finished Apr 18 12:35:48 PM PDT 24
Peak memory 207112 kb
Host smart-e4e72e43-0bbe-4c5e-9d0c-c85ca563d772
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132229175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.132229175
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3336448314
Short name T77
Test name
Test status
Simulation time 754694669 ps
CPU time 5.52 seconds
Started Apr 18 12:35:44 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 208720 kb
Host smart-121a5878-20d7-4e35-ad97-5500719bdd9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336448314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3336448314
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.954315784
Short name T551
Test name
Test status
Simulation time 1142203524 ps
CPU time 3.16 seconds
Started Apr 18 12:35:36 PM PDT 24
Finished Apr 18 12:35:40 PM PDT 24
Peak memory 208984 kb
Host smart-a2c4df0b-0e1c-470a-99f0-d70d8cfedebb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954315784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.954315784
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.909351181
Short name T712
Test name
Test status
Simulation time 152445506 ps
CPU time 4.12 seconds
Started Apr 18 12:35:53 PM PDT 24
Finished Apr 18 12:35:58 PM PDT 24
Peak memory 208352 kb
Host smart-cc1a951b-2be7-4321-ae14-5dddb457115b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909351181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.909351181
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3310528890
Short name T439
Test name
Test status
Simulation time 70406428 ps
CPU time 2.84 seconds
Started Apr 18 12:35:41 PM PDT 24
Finished Apr 18 12:35:45 PM PDT 24
Peak memory 208140 kb
Host smart-e8496ab9-bc5c-4bd8-bb88-8248c536e552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310528890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3310528890
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3706034464
Short name T69
Test name
Test status
Simulation time 183563143883 ps
CPU time 769.58 seconds
Started Apr 18 12:35:59 PM PDT 24
Finished Apr 18 12:48:50 PM PDT 24
Peak memory 230896 kb
Host smart-4f6b4c25-5ffc-44b2-a63f-eb481623bb1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706034464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3706034464
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3405733900
Short name T659
Test name
Test status
Simulation time 577957320 ps
CPU time 4.85 seconds
Started Apr 18 12:35:44 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 208364 kb
Host smart-ca0247b5-3505-4c59-aee6-4ad70cb3a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405733900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3405733900
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.935268893
Short name T598
Test name
Test status
Simulation time 68945058 ps
CPU time 2.35 seconds
Started Apr 18 12:36:02 PM PDT 24
Finished Apr 18 12:36:06 PM PDT 24
Peak memory 210480 kb
Host smart-38bc199a-e5e0-4128-ae30-114dd4d2d715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935268893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.935268893
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2260321370
Short name T202
Test name
Test status
Simulation time 16762025 ps
CPU time 0.97 seconds
Started Apr 18 12:35:54 PM PDT 24
Finished Apr 18 12:35:56 PM PDT 24
Peak memory 206320 kb
Host smart-330c1d85-3af8-46ce-814e-dcdf8003c0c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260321370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2260321370
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2974360526
Short name T273
Test name
Test status
Simulation time 182244137 ps
CPU time 2.99 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:35:45 PM PDT 24
Peak memory 222728 kb
Host smart-363c6e52-4d16-4c7d-aea7-edc9857df7b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974360526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2974360526
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.654185264
Short name T585
Test name
Test status
Simulation time 47381823 ps
CPU time 2.01 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 209896 kb
Host smart-3a39a5d0-cba8-41fb-ada4-e57a53b154bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654185264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.654185264
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2652287477
Short name T271
Test name
Test status
Simulation time 258713279 ps
CPU time 3.83 seconds
Started Apr 18 12:35:59 PM PDT 24
Finished Apr 18 12:36:04 PM PDT 24
Peak memory 209960 kb
Host smart-7969bc79-7e9b-4dd0-a4ff-1421e0289094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652287477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2652287477
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.855516873
Short name T806
Test name
Test status
Simulation time 575890006 ps
CPU time 3.88 seconds
Started Apr 18 12:35:46 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 214640 kb
Host smart-12d85345-aefa-42e6-b6cd-77c46b28a72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855516873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.855516873
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1751511894
Short name T268
Test name
Test status
Simulation time 2004896032 ps
CPU time 57.45 seconds
Started Apr 18 12:35:53 PM PDT 24
Finished Apr 18 12:36:52 PM PDT 24
Peak memory 231364 kb
Host smart-5939a4b5-2c8d-4003-b31c-f518623f286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751511894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1751511894
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_random.1230193346
Short name T889
Test name
Test status
Simulation time 90042164 ps
CPU time 4.18 seconds
Started Apr 18 12:35:49 PM PDT 24
Finished Apr 18 12:35:55 PM PDT 24
Peak memory 210564 kb
Host smart-0354e8f5-4a3f-4f71-a482-983a19cf3ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230193346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1230193346
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2476970373
Short name T533
Test name
Test status
Simulation time 2049582765 ps
CPU time 6.12 seconds
Started Apr 18 12:35:51 PM PDT 24
Finished Apr 18 12:35:58 PM PDT 24
Peak memory 207168 kb
Host smart-e9df3730-66ed-4124-84f9-ed96e6b1b3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476970373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2476970373
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.996501464
Short name T720
Test name
Test status
Simulation time 91595275 ps
CPU time 1.88 seconds
Started Apr 18 12:35:44 PM PDT 24
Finished Apr 18 12:35:47 PM PDT 24
Peak memory 206996 kb
Host smart-495fa722-2056-4670-a369-68bdf0960ed8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996501464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.996501464
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1312835681
Short name T844
Test name
Test status
Simulation time 49407723 ps
CPU time 2.19 seconds
Started Apr 18 12:35:42 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 208932 kb
Host smart-8ff33e21-1bdc-4a4b-ad46-1143390a583a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312835681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1312835681
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3087409392
Short name T722
Test name
Test status
Simulation time 7455160754 ps
CPU time 15.85 seconds
Started Apr 18 12:35:40 PM PDT 24
Finished Apr 18 12:35:57 PM PDT 24
Peak memory 209012 kb
Host smart-85a787b4-b51b-4a60-a789-86c6e283113e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087409392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3087409392
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1819868613
Short name T232
Test name
Test status
Simulation time 506890323 ps
CPU time 3.3 seconds
Started Apr 18 12:35:56 PM PDT 24
Finished Apr 18 12:36:01 PM PDT 24
Peak memory 208300 kb
Host smart-212c2b87-a76f-4b5a-b5ae-1dcdc8c81cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819868613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1819868613
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2352213316
Short name T581
Test name
Test status
Simulation time 194547839 ps
CPU time 2.33 seconds
Started Apr 18 12:35:51 PM PDT 24
Finished Apr 18 12:35:54 PM PDT 24
Peak memory 206864 kb
Host smart-215e761c-39c8-4c37-9dea-d7ae2dd76edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352213316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2352213316
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4050875217
Short name T351
Test name
Test status
Simulation time 1392283177 ps
CPU time 33.18 seconds
Started Apr 18 12:35:56 PM PDT 24
Finished Apr 18 12:36:31 PM PDT 24
Peak memory 220916 kb
Host smart-a0e04f98-4fad-41a5-bfa5-01fdb8e98e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050875217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4050875217
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2482947824
Short name T98
Test name
Test status
Simulation time 469976178 ps
CPU time 7.82 seconds
Started Apr 18 12:35:53 PM PDT 24
Finished Apr 18 12:36:02 PM PDT 24
Peak memory 222892 kb
Host smart-aac6319d-c802-47b6-8f31-8e60ac41b811
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482947824 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2482947824
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2761041487
Short name T515
Test name
Test status
Simulation time 111104596 ps
CPU time 2.37 seconds
Started Apr 18 12:35:44 PM PDT 24
Finished Apr 18 12:35:48 PM PDT 24
Peak memory 208028 kb
Host smart-1bb61519-3bbb-40cb-aa0e-a8a3c8fdcc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761041487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2761041487
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3429019497
Short name T511
Test name
Test status
Simulation time 111769622 ps
CPU time 2.69 seconds
Started Apr 18 12:36:00 PM PDT 24
Finished Apr 18 12:36:03 PM PDT 24
Peak memory 210032 kb
Host smart-4a50ecf5-31b6-48e9-a9de-854489e01825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429019497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3429019497
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1210196677
Short name T205
Test name
Test status
Simulation time 10675686 ps
CPU time 0.77 seconds
Started Apr 18 12:34:07 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 206236 kb
Host smart-fd1f4840-23f3-41e5-8b2c-ab170e6441fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210196677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1210196677
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1081648293
Short name T62
Test name
Test status
Simulation time 56477824 ps
CPU time 2.16 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 221548 kb
Host smart-6b190991-e48b-4080-9407-dc3ae8a2e140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081648293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1081648293
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.257081098
Short name T685
Test name
Test status
Simulation time 259026187 ps
CPU time 2.89 seconds
Started Apr 18 12:34:09 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 208712 kb
Host smart-9539c64c-923e-4279-a494-a96eb54335fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257081098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.257081098
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.499673630
Short name T307
Test name
Test status
Simulation time 103172864 ps
CPU time 3.61 seconds
Started Apr 18 12:34:07 PM PDT 24
Finished Apr 18 12:34:11 PM PDT 24
Peak memory 220812 kb
Host smart-877598b4-2c94-4c88-95d9-90739a486ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499673630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.499673630
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3946929204
Short name T257
Test name
Test status
Simulation time 517564536 ps
CPU time 3.1 seconds
Started Apr 18 12:34:07 PM PDT 24
Finished Apr 18 12:34:11 PM PDT 24
Peak memory 220572 kb
Host smart-a0dae6d8-d40e-43ab-90ef-f904c6820b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946929204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3946929204
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2790365870
Short name T225
Test name
Test status
Simulation time 40572103 ps
CPU time 2.73 seconds
Started Apr 18 12:34:08 PM PDT 24
Finished Apr 18 12:34:12 PM PDT 24
Peak memory 208052 kb
Host smart-98283cbe-a34a-4507-86ef-55328b78c52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790365870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2790365870
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2448900961
Short name T100
Test name
Test status
Simulation time 4980609144 ps
CPU time 23.59 seconds
Started Apr 18 12:34:08 PM PDT 24
Finished Apr 18 12:34:32 PM PDT 24
Peak memory 235556 kb
Host smart-053f4d64-e0fa-4821-a6ac-6d0a03889d66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448900961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2448900961
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3344128608
Short name T531
Test name
Test status
Simulation time 492720846 ps
CPU time 2.64 seconds
Started Apr 18 12:34:12 PM PDT 24
Finished Apr 18 12:34:16 PM PDT 24
Peak memory 207284 kb
Host smart-704fa700-f4ed-4c42-a73e-87e70f2d0876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344128608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3344128608
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.112229020
Short name T815
Test name
Test status
Simulation time 65503575 ps
CPU time 3.17 seconds
Started Apr 18 12:34:11 PM PDT 24
Finished Apr 18 12:34:15 PM PDT 24
Peak memory 207020 kb
Host smart-74d2f3e6-0b78-4504-9407-316a94ce8486
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112229020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.112229020
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.649044335
Short name T603
Test name
Test status
Simulation time 998398268 ps
CPU time 9.2 seconds
Started Apr 18 12:34:12 PM PDT 24
Finished Apr 18 12:34:22 PM PDT 24
Peak memory 208228 kb
Host smart-0613e6df-7dd6-4c32-a7be-2c72bb81fd64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649044335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.649044335
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.455427815
Short name T489
Test name
Test status
Simulation time 84306409 ps
CPU time 2.34 seconds
Started Apr 18 12:34:06 PM PDT 24
Finished Apr 18 12:34:09 PM PDT 24
Peak memory 207428 kb
Host smart-1c243b86-e69c-4544-b2db-acff36234f69
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455427815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.455427815
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2418350527
Short name T442
Test name
Test status
Simulation time 246210430 ps
CPU time 6.65 seconds
Started Apr 18 12:34:08 PM PDT 24
Finished Apr 18 12:34:16 PM PDT 24
Peak memory 209428 kb
Host smart-6a53bd7e-5305-4a3a-9c56-972b42989b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418350527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2418350527
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.93407510
Short name T428
Test name
Test status
Simulation time 680038418 ps
CPU time 15.16 seconds
Started Apr 18 12:34:15 PM PDT 24
Finished Apr 18 12:34:32 PM PDT 24
Peak memory 206980 kb
Host smart-ea76c4b2-3e9f-4e55-bba4-e29f63702217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93407510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.93407510
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3929645266
Short name T326
Test name
Test status
Simulation time 3177732866 ps
CPU time 19.88 seconds
Started Apr 18 12:34:08 PM PDT 24
Finished Apr 18 12:34:29 PM PDT 24
Peak memory 216620 kb
Host smart-467a4175-2f98-48ed-8a73-6b0f954d5efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929645266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3929645266
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3858829415
Short name T780
Test name
Test status
Simulation time 18582615281 ps
CPU time 55.1 seconds
Started Apr 18 12:34:06 PM PDT 24
Finished Apr 18 12:35:02 PM PDT 24
Peak memory 218860 kb
Host smart-f4753311-ecd4-4de8-bb97-34003c9b487b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858829415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3858829415
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.32230299
Short name T840
Test name
Test status
Simulation time 45919657 ps
CPU time 2.42 seconds
Started Apr 18 12:34:07 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 210076 kb
Host smart-4eb5e461-0535-4107-b1b7-1f1d9ead2658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32230299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.32230299
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2897456145
Short name T648
Test name
Test status
Simulation time 40866144 ps
CPU time 0.85 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 206208 kb
Host smart-4ea4774b-f75b-4ccf-befa-625aaa89087c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897456145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2897456145
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1523996735
Short name T423
Test name
Test status
Simulation time 38093927 ps
CPU time 2.79 seconds
Started Apr 18 12:36:17 PM PDT 24
Finished Apr 18 12:36:20 PM PDT 24
Peak memory 215492 kb
Host smart-5856aea8-44da-428e-8628-e0890007d423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523996735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1523996735
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1982602089
Short name T65
Test name
Test status
Simulation time 458277392 ps
CPU time 3.87 seconds
Started Apr 18 12:36:16 PM PDT 24
Finished Apr 18 12:36:21 PM PDT 24
Peak memory 210344 kb
Host smart-d887a3c8-db01-4483-bd8d-9c614278104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982602089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1982602089
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1406837191
Short name T332
Test name
Test status
Simulation time 477046077 ps
CPU time 3.8 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 208740 kb
Host smart-79854159-e511-4a74-b142-edeebde430a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406837191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1406837191
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.715270280
Short name T283
Test name
Test status
Simulation time 315177022 ps
CPU time 4.06 seconds
Started Apr 18 12:35:56 PM PDT 24
Finished Apr 18 12:36:01 PM PDT 24
Peak memory 210460 kb
Host smart-0ea310f8-a8d5-4063-943a-23ae2ba91a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715270280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.715270280
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1641939774
Short name T250
Test name
Test status
Simulation time 91112678 ps
CPU time 2.96 seconds
Started Apr 18 12:36:06 PM PDT 24
Finished Apr 18 12:36:11 PM PDT 24
Peak memory 209092 kb
Host smart-c1196bd1-7dad-4d37-bacd-cb586ca25c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641939774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1641939774
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2355933908
Short name T543
Test name
Test status
Simulation time 1185788267 ps
CPU time 12.55 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:36:06 PM PDT 24
Peak memory 208760 kb
Host smart-1a8f67d1-2dac-4dc2-a9fa-230a28b3cf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355933908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2355933908
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3080517990
Short name T631
Test name
Test status
Simulation time 214383746 ps
CPU time 3.56 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:52 PM PDT 24
Peak memory 208664 kb
Host smart-0e7b13c8-6476-4718-b4e9-fee0c10464a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080517990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3080517990
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2492746769
Short name T76
Test name
Test status
Simulation time 265741674 ps
CPU time 2.86 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 207160 kb
Host smart-373e5db4-c6a3-4be7-aff6-6b19437e2bb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492746769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2492746769
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2005229989
Short name T514
Test name
Test status
Simulation time 52410760 ps
CPU time 2.83 seconds
Started Apr 18 12:35:57 PM PDT 24
Finished Apr 18 12:36:01 PM PDT 24
Peak memory 208568 kb
Host smart-4f5d334c-8f2f-46b9-98ff-04bef2453f84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005229989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2005229989
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4251011617
Short name T483
Test name
Test status
Simulation time 1258752740 ps
CPU time 4.15 seconds
Started Apr 18 12:36:01 PM PDT 24
Finished Apr 18 12:36:06 PM PDT 24
Peak memory 209000 kb
Host smart-d91ff006-0807-4c3e-a435-9dc7796fe0b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251011617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4251011617
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1720122665
Short name T236
Test name
Test status
Simulation time 57049475 ps
CPU time 1.51 seconds
Started Apr 18 12:36:03 PM PDT 24
Finished Apr 18 12:36:05 PM PDT 24
Peak memory 207980 kb
Host smart-20542cf5-021b-4fec-83a2-cc894394022e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720122665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1720122665
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.594285843
Short name T189
Test name
Test status
Simulation time 51960717 ps
CPU time 2.28 seconds
Started Apr 18 12:35:53 PM PDT 24
Finished Apr 18 12:35:56 PM PDT 24
Peak memory 206992 kb
Host smart-03eb8dfa-07b4-4a77-ace8-de498f59aa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594285843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.594285843
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2533093038
Short name T319
Test name
Test status
Simulation time 451340994 ps
CPU time 14.58 seconds
Started Apr 18 12:35:58 PM PDT 24
Finished Apr 18 12:36:14 PM PDT 24
Peak memory 221992 kb
Host smart-d2a5bbaf-6643-4530-9ef0-b6c2bd744ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533093038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2533093038
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2964144163
Short name T384
Test name
Test status
Simulation time 20312019678 ps
CPU time 57.71 seconds
Started Apr 18 12:35:59 PM PDT 24
Finished Apr 18 12:36:58 PM PDT 24
Peak memory 214764 kb
Host smart-bcf5ac23-dc9d-4706-b206-e67e1b86e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964144163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2964144163
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2571735704
Short name T393
Test name
Test status
Simulation time 107861224 ps
CPU time 1.39 seconds
Started Apr 18 12:35:58 PM PDT 24
Finished Apr 18 12:36:01 PM PDT 24
Peak memory 209648 kb
Host smart-f7fc0136-3a34-4671-b572-8af21f970169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571735704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2571735704
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2682433410
Short name T552
Test name
Test status
Simulation time 53236284 ps
CPU time 0.94 seconds
Started Apr 18 12:36:04 PM PDT 24
Finished Apr 18 12:36:06 PM PDT 24
Peak memory 206276 kb
Host smart-b9223781-507d-4f59-873b-77ee2a34e71c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682433410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2682433410
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1244610369
Short name T868
Test name
Test status
Simulation time 102340287 ps
CPU time 3.99 seconds
Started Apr 18 12:35:58 PM PDT 24
Finished Apr 18 12:36:03 PM PDT 24
Peak memory 214508 kb
Host smart-206f51f3-8e6b-4f48-aef1-65ce5cfbf8c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244610369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1244610369
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2006469388
Short name T893
Test name
Test status
Simulation time 87670240 ps
CPU time 3.7 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 218548 kb
Host smart-4d554715-db9b-4829-a9e9-156794004e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006469388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2006469388
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2511868906
Short name T290
Test name
Test status
Simulation time 657388105 ps
CPU time 8.44 seconds
Started Apr 18 12:35:50 PM PDT 24
Finished Apr 18 12:36:00 PM PDT 24
Peak memory 214472 kb
Host smart-d76931d6-0ad5-4ed6-8d12-8693b320ec87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511868906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2511868906
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2881372817
Short name T80
Test name
Test status
Simulation time 275219627 ps
CPU time 10.5 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:59 PM PDT 24
Peak memory 222704 kb
Host smart-73a17682-1b6e-4042-aaea-0467e62959cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881372817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2881372817
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.4206055324
Short name T46
Test name
Test status
Simulation time 91310690 ps
CPU time 1.98 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 214580 kb
Host smart-3c48b497-1371-4a36-b6a9-90446ccc6faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206055324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4206055324
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.219880482
Short name T306
Test name
Test status
Simulation time 42045870 ps
CPU time 3.13 seconds
Started Apr 18 12:35:44 PM PDT 24
Finished Apr 18 12:35:49 PM PDT 24
Peak memory 219928 kb
Host smart-a71d2adc-ed75-4e7c-ab14-90a556779588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219880482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.219880482
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.973672343
Short name T617
Test name
Test status
Simulation time 211212676 ps
CPU time 4.91 seconds
Started Apr 18 12:35:59 PM PDT 24
Finished Apr 18 12:36:05 PM PDT 24
Peak memory 208272 kb
Host smart-bd7d2366-644f-40f6-bfb6-85ac00a96b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973672343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.973672343
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2842248262
Short name T697
Test name
Test status
Simulation time 165886780 ps
CPU time 2.55 seconds
Started Apr 18 12:36:08 PM PDT 24
Finished Apr 18 12:36:12 PM PDT 24
Peak memory 207056 kb
Host smart-d325aa88-02eb-4ade-9ea9-5987cc5bfc03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842248262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2842248262
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1018061283
Short name T651
Test name
Test status
Simulation time 90489512 ps
CPU time 1.79 seconds
Started Apr 18 12:36:08 PM PDT 24
Finished Apr 18 12:36:11 PM PDT 24
Peak memory 206924 kb
Host smart-eb47a73f-a01a-4231-a884-66c3c8e5b222
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018061283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1018061283
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.805287252
Short name T291
Test name
Test status
Simulation time 335166595 ps
CPU time 3.52 seconds
Started Apr 18 12:35:46 PM PDT 24
Finished Apr 18 12:35:51 PM PDT 24
Peak memory 209112 kb
Host smart-279f082c-f0db-40fc-9b4b-4f8e011a1162
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805287252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.805287252
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1155333357
Short name T621
Test name
Test status
Simulation time 131823731 ps
CPU time 3.05 seconds
Started Apr 18 12:35:54 PM PDT 24
Finished Apr 18 12:35:58 PM PDT 24
Peak memory 210172 kb
Host smart-1567917f-c610-4dac-94a4-1b069df00190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155333357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1155333357
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.567384073
Short name T441
Test name
Test status
Simulation time 24223824 ps
CPU time 1.94 seconds
Started Apr 18 12:36:05 PM PDT 24
Finished Apr 18 12:36:08 PM PDT 24
Peak memory 208800 kb
Host smart-9f1587a5-4cba-4817-8881-4a08aca21ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567384073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.567384073
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.617331262
Short name T74
Test name
Test status
Simulation time 691473688 ps
CPU time 11.28 seconds
Started Apr 18 12:36:04 PM PDT 24
Finished Apr 18 12:36:16 PM PDT 24
Peak memory 215576 kb
Host smart-f0c68b05-d6a4-406d-9bfd-66ec0cf1c60c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617331262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.617331262
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3852115861
Short name T809
Test name
Test status
Simulation time 192211773 ps
CPU time 6.63 seconds
Started Apr 18 12:35:58 PM PDT 24
Finished Apr 18 12:36:06 PM PDT 24
Peak memory 221080 kb
Host smart-1ace6fa7-f140-484b-b9ce-3986436508be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852115861 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3852115861
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1775996559
Short name T610
Test name
Test status
Simulation time 274384992 ps
CPU time 3.93 seconds
Started Apr 18 12:35:48 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 208032 kb
Host smart-5bc8b83c-3744-4687-b07b-f89a0e7d93c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775996559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1775996559
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.107824531
Short name T404
Test name
Test status
Simulation time 3751133899 ps
CPU time 29.6 seconds
Started Apr 18 12:36:05 PM PDT 24
Finished Apr 18 12:36:36 PM PDT 24
Peak memory 211940 kb
Host smart-f8de923e-dfd5-43aa-9c7c-3ede09f696be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107824531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.107824531
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.108413931
Short name T824
Test name
Test status
Simulation time 33933601 ps
CPU time 0.87 seconds
Started Apr 18 12:35:46 PM PDT 24
Finished Apr 18 12:35:48 PM PDT 24
Peak memory 206152 kb
Host smart-608bcf02-a0a4-4c40-a02c-a371c35f023c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108413931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.108413931
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1719299766
Short name T363
Test name
Test status
Simulation time 951028506 ps
CPU time 16.39 seconds
Started Apr 18 12:36:44 PM PDT 24
Finished Apr 18 12:37:01 PM PDT 24
Peak memory 216044 kb
Host smart-11a8d19d-1149-4c8e-ac64-9fb0301e44b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719299766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1719299766
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2373139451
Short name T35
Test name
Test status
Simulation time 410567347 ps
CPU time 3.5 seconds
Started Apr 18 12:35:55 PM PDT 24
Finished Apr 18 12:35:59 PM PDT 24
Peak memory 209152 kb
Host smart-74e3eeb9-b598-41c6-a87e-9476230dd20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373139451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2373139451
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.578932812
Short name T550
Test name
Test status
Simulation time 30467988 ps
CPU time 1.44 seconds
Started Apr 18 12:36:04 PM PDT 24
Finished Apr 18 12:36:06 PM PDT 24
Peak memory 207516 kb
Host smart-e76ba0d8-1f27-4d1c-8afb-4468152f8e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578932812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.578932812
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.643073418
Short name T269
Test name
Test status
Simulation time 362099067 ps
CPU time 4.69 seconds
Started Apr 18 12:36:02 PM PDT 24
Finished Apr 18 12:36:08 PM PDT 24
Peak memory 220652 kb
Host smart-f5ab0820-69dc-49a9-9620-21c732396ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643073418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.643073418
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1398393504
Short name T754
Test name
Test status
Simulation time 63529537 ps
CPU time 2.5 seconds
Started Apr 18 12:36:00 PM PDT 24
Finished Apr 18 12:36:04 PM PDT 24
Peak memory 209372 kb
Host smart-5d3627e3-8016-40f4-afa9-c024b8505e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398393504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1398393504
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.44108638
Short name T53
Test name
Test status
Simulation time 163901386 ps
CPU time 3.28 seconds
Started Apr 18 12:35:55 PM PDT 24
Finished Apr 18 12:35:59 PM PDT 24
Peak memory 209756 kb
Host smart-53454334-1666-4071-b18b-afc4ba83db2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44108638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.44108638
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3538889817
Short name T274
Test name
Test status
Simulation time 611074592 ps
CPU time 6.59 seconds
Started Apr 18 12:36:09 PM PDT 24
Finished Apr 18 12:36:17 PM PDT 24
Peak memory 218476 kb
Host smart-c5d6ce23-fd8b-4b80-baa9-0333d8a3b836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538889817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3538889817
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.932397757
Short name T618
Test name
Test status
Simulation time 336897527 ps
CPU time 4.19 seconds
Started Apr 18 12:35:45 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 206820 kb
Host smart-a2a3c7ca-703e-4c83-8ae8-bceb7ba94b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932397757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.932397757
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3459210794
Short name T681
Test name
Test status
Simulation time 42819306 ps
CPU time 1.83 seconds
Started Apr 18 12:35:49 PM PDT 24
Finished Apr 18 12:35:52 PM PDT 24
Peak memory 206948 kb
Host smart-da164a5b-0c6b-4cfb-96b2-32d7837732a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459210794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3459210794
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.649933290
Short name T632
Test name
Test status
Simulation time 112436593 ps
CPU time 3.24 seconds
Started Apr 18 12:36:02 PM PDT 24
Finished Apr 18 12:36:07 PM PDT 24
Peak memory 208888 kb
Host smart-6556038d-47f1-4440-9be9-a2cd251a64ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649933290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.649933290
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.4087193072
Short name T625
Test name
Test status
Simulation time 22140656 ps
CPU time 1.85 seconds
Started Apr 18 12:36:00 PM PDT 24
Finished Apr 18 12:36:03 PM PDT 24
Peak memory 207336 kb
Host smart-6b9f4917-15fb-4a88-a94d-627133cf4f4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087193072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.4087193072
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.78691987
Short name T230
Test name
Test status
Simulation time 30146468 ps
CPU time 2.07 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:35:50 PM PDT 24
Peak memory 208340 kb
Host smart-58280a78-bdbf-4cdb-b3df-860daa0c5548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78691987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.78691987
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3389902226
Short name T630
Test name
Test status
Simulation time 119547724 ps
CPU time 2.25 seconds
Started Apr 18 12:36:08 PM PDT 24
Finished Apr 18 12:36:12 PM PDT 24
Peak memory 207344 kb
Host smart-26fec5ea-0382-4e33-9da1-422631d01949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389902226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3389902226
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3528659970
Short name T294
Test name
Test status
Simulation time 1209550012 ps
CPU time 11.88 seconds
Started Apr 18 12:36:08 PM PDT 24
Finished Apr 18 12:36:22 PM PDT 24
Peak memory 220152 kb
Host smart-8d6f3f94-e4b0-4ae0-aa38-906c719f4acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528659970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3528659970
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3527089588
Short name T251
Test name
Test status
Simulation time 518437113 ps
CPU time 19.63 seconds
Started Apr 18 12:35:50 PM PDT 24
Finished Apr 18 12:36:11 PM PDT 24
Peak memory 222868 kb
Host smart-f7dd55bf-bf91-475e-a9d3-edc6ba6e89f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527089588 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3527089588
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2846272677
Short name T278
Test name
Test status
Simulation time 88820716 ps
CPU time 4.05 seconds
Started Apr 18 12:35:49 PM PDT 24
Finished Apr 18 12:35:54 PM PDT 24
Peak memory 208072 kb
Host smart-d3e381d4-6686-47c7-82b5-84813e5ca69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846272677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2846272677
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3280326315
Short name T481
Test name
Test status
Simulation time 158355622 ps
CPU time 2.68 seconds
Started Apr 18 12:35:49 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 210628 kb
Host smart-ef2bffa8-d649-4573-b695-72456f456490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280326315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3280326315
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1309805617
Short name T556
Test name
Test status
Simulation time 15277584 ps
CPU time 0.94 seconds
Started Apr 18 12:35:58 PM PDT 24
Finished Apr 18 12:36:01 PM PDT 24
Peak memory 206332 kb
Host smart-a20aa36c-27e8-48a3-80b4-ab8e47245d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309805617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1309805617
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1651950545
Short name T240
Test name
Test status
Simulation time 1668241537 ps
CPU time 18.32 seconds
Started Apr 18 12:35:57 PM PDT 24
Finished Apr 18 12:36:16 PM PDT 24
Peak memory 215092 kb
Host smart-cbfff634-62ff-438e-b096-bbb6ccc05684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651950545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1651950545
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.24720798
Short name T281
Test name
Test status
Simulation time 238888896 ps
CPU time 3.37 seconds
Started Apr 18 12:36:06 PM PDT 24
Finished Apr 18 12:36:11 PM PDT 24
Peak memory 210388 kb
Host smart-cea93289-fe72-4fd9-9722-e64950a7faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24720798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.24720798
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.221524856
Short name T808
Test name
Test status
Simulation time 200167363 ps
CPU time 4.66 seconds
Started Apr 18 12:35:54 PM PDT 24
Finished Apr 18 12:36:00 PM PDT 24
Peak memory 209124 kb
Host smart-2044f905-17f9-478d-8aa5-2bfe5593a321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221524856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.221524856
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.424290183
Short name T377
Test name
Test status
Simulation time 239924998 ps
CPU time 4.86 seconds
Started Apr 18 12:35:49 PM PDT 24
Finished Apr 18 12:35:56 PM PDT 24
Peak memory 209700 kb
Host smart-329a69e3-e89c-4511-84c2-9b996a25d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424290183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.424290183
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.248502589
Short name T258
Test name
Test status
Simulation time 413111887 ps
CPU time 5.94 seconds
Started Apr 18 12:36:22 PM PDT 24
Finished Apr 18 12:36:29 PM PDT 24
Peak memory 220460 kb
Host smart-7e738b65-faff-49d0-9b91-1499920c2ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248502589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.248502589
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4236467496
Short name T275
Test name
Test status
Simulation time 37621042 ps
CPU time 2.63 seconds
Started Apr 18 12:35:49 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 214580 kb
Host smart-fb30a6ce-a029-40f0-9024-23517bc8d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236467496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4236467496
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2785330513
Short name T645
Test name
Test status
Simulation time 275071426 ps
CPU time 4.13 seconds
Started Apr 18 12:35:58 PM PDT 24
Finished Apr 18 12:36:04 PM PDT 24
Peak memory 208564 kb
Host smart-c1f22172-df26-443d-8940-8448efb35480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785330513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2785330513
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3220750660
Short name T672
Test name
Test status
Simulation time 190837665 ps
CPU time 4.6 seconds
Started Apr 18 12:36:01 PM PDT 24
Finished Apr 18 12:36:07 PM PDT 24
Peak memory 207588 kb
Host smart-4f94ab83-6eff-4a50-9ff0-6af6fc34e44f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220750660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3220750660
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4196531249
Short name T572
Test name
Test status
Simulation time 235959971 ps
CPU time 4.11 seconds
Started Apr 18 12:35:56 PM PDT 24
Finished Apr 18 12:36:01 PM PDT 24
Peak memory 207212 kb
Host smart-0ced123a-f70c-4e7d-b94f-139fcc21709c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196531249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4196531249
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.4119442643
Short name T463
Test name
Test status
Simulation time 91331259 ps
CPU time 2.75 seconds
Started Apr 18 12:35:49 PM PDT 24
Finished Apr 18 12:35:53 PM PDT 24
Peak memory 208916 kb
Host smart-513d60c6-9e96-4d07-a26e-941c96e0a305
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119442643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4119442643
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1004855893
Short name T629
Test name
Test status
Simulation time 60296884 ps
CPU time 3.11 seconds
Started Apr 18 12:36:04 PM PDT 24
Finished Apr 18 12:36:08 PM PDT 24
Peak memory 210380 kb
Host smart-f9aa63dc-bd49-4d4b-b1f3-546767ac10b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004855893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1004855893
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3814895836
Short name T863
Test name
Test status
Simulation time 377370875 ps
CPU time 4.67 seconds
Started Apr 18 12:35:58 PM PDT 24
Finished Apr 18 12:36:04 PM PDT 24
Peak memory 208784 kb
Host smart-b7d92c85-1090-4117-86e9-cf105d27cdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814895836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3814895836
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2014371195
Short name T7
Test name
Test status
Simulation time 1709344380 ps
CPU time 50.75 seconds
Started Apr 18 12:35:59 PM PDT 24
Finished Apr 18 12:36:51 PM PDT 24
Peak memory 221936 kb
Host smart-6bf09936-f530-47c2-aa3b-c0e6ba1aadc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014371195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2014371195
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3888859894
Short name T132
Test name
Test status
Simulation time 871857974 ps
CPU time 23.71 seconds
Started Apr 18 12:35:57 PM PDT 24
Finished Apr 18 12:36:22 PM PDT 24
Peak memory 208676 kb
Host smart-9921315b-d5e7-430d-9cc1-918366fadd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888859894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3888859894
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2196289176
Short name T193
Test name
Test status
Simulation time 174035343 ps
CPU time 2.43 seconds
Started Apr 18 12:35:59 PM PDT 24
Finished Apr 18 12:36:02 PM PDT 24
Peak memory 210164 kb
Host smart-9023be1f-9ee9-47c0-ae63-359b05f3a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196289176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2196289176
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2170442729
Short name T135
Test name
Test status
Simulation time 37572921 ps
CPU time 0.95 seconds
Started Apr 18 12:35:53 PM PDT 24
Finished Apr 18 12:35:55 PM PDT 24
Peak memory 206196 kb
Host smart-aab0a958-64a9-4a85-a6d3-73405292670a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170442729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2170442729
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.615118928
Short name T426
Test name
Test status
Simulation time 7538579001 ps
CPU time 102.4 seconds
Started Apr 18 12:35:47 PM PDT 24
Finished Apr 18 12:37:30 PM PDT 24
Peak memory 214760 kb
Host smart-ddddd9db-a7a1-4518-99c7-5d5d05e87bde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615118928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.615118928
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3311000418
Short name T21
Test name
Test status
Simulation time 118994755 ps
CPU time 2.58 seconds
Started Apr 18 12:36:07 PM PDT 24
Finished Apr 18 12:36:12 PM PDT 24
Peak memory 222836 kb
Host smart-7df00f97-81be-43e0-b9a6-524f9ede2941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311000418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3311000418
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1772610548
Short name T60
Test name
Test status
Simulation time 82776326 ps
CPU time 3.41 seconds
Started Apr 18 12:36:07 PM PDT 24
Finished Apr 18 12:36:13 PM PDT 24
Peak memory 218480 kb
Host smart-3ed34314-b870-4bfc-a417-6d3c51faaf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772610548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1772610548
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2563268309
Short name T673
Test name
Test status
Simulation time 121358897 ps
CPU time 5.08 seconds
Started Apr 18 12:35:57 PM PDT 24
Finished Apr 18 12:36:03 PM PDT 24
Peak memory 209308 kb
Host smart-cade70a6-245a-4c7f-81c9-653052def3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563268309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2563268309
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2827808541
Short name T37
Test name
Test status
Simulation time 150826491 ps
CPU time 6.55 seconds
Started Apr 18 12:36:07 PM PDT 24
Finished Apr 18 12:36:15 PM PDT 24
Peak memory 222756 kb
Host smart-3af409a0-77df-41ef-bf23-77ce3cec978d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827808541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2827808541
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2754296100
Short name T653
Test name
Test status
Simulation time 87258799 ps
CPU time 2.67 seconds
Started Apr 18 12:36:03 PM PDT 24
Finished Apr 18 12:36:07 PM PDT 24
Peak memory 214472 kb
Host smart-47b947ca-39dd-4ce5-88c3-3195f0fa657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754296100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2754296100
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.739084755
Short name T876
Test name
Test status
Simulation time 1475457528 ps
CPU time 7.4 seconds
Started Apr 18 12:36:06 PM PDT 24
Finished Apr 18 12:36:14 PM PDT 24
Peak memory 208912 kb
Host smart-d3045939-d35b-4768-ab9b-4344673c2031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739084755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.739084755
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3622600386
Short name T203
Test name
Test status
Simulation time 3498143999 ps
CPU time 21.97 seconds
Started Apr 18 12:35:49 PM PDT 24
Finished Apr 18 12:36:12 PM PDT 24
Peak memory 209080 kb
Host smart-e85165e1-35f0-4ed1-89ab-82f2cdd01dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622600386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3622600386
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1530946568
Short name T349
Test name
Test status
Simulation time 1247926348 ps
CPU time 33.69 seconds
Started Apr 18 12:36:03 PM PDT 24
Finished Apr 18 12:36:37 PM PDT 24
Peak memory 208800 kb
Host smart-ed956299-5087-49d6-aaf0-395cd815e50e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530946568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1530946568
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3983644311
Short name T401
Test name
Test status
Simulation time 541014181 ps
CPU time 5.29 seconds
Started Apr 18 12:36:09 PM PDT 24
Finished Apr 18 12:36:16 PM PDT 24
Peak memory 208704 kb
Host smart-4d0877d8-f38d-4556-8dc1-201b2f4b59f0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983644311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3983644311
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2703143125
Short name T765
Test name
Test status
Simulation time 54215226 ps
CPU time 3 seconds
Started Apr 18 12:36:04 PM PDT 24
Finished Apr 18 12:36:08 PM PDT 24
Peak memory 207312 kb
Host smart-2d85a4f1-b9c4-492f-9ad4-a71f6ca67928
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703143125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2703143125
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.983987720
Short name T688
Test name
Test status
Simulation time 805542038 ps
CPU time 5.65 seconds
Started Apr 18 12:35:53 PM PDT 24
Finished Apr 18 12:36:00 PM PDT 24
Peak memory 208540 kb
Host smart-97ab4896-f594-4df9-87b3-849f9793a081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983987720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.983987720
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1059361118
Short name T548
Test name
Test status
Simulation time 68570699 ps
CPU time 3.16 seconds
Started Apr 18 12:36:06 PM PDT 24
Finished Apr 18 12:36:10 PM PDT 24
Peak memory 207964 kb
Host smart-72b7af5d-43e4-41e4-b5af-742f753106dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059361118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1059361118
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1575616465
Short name T195
Test name
Test status
Simulation time 348476736 ps
CPU time 7.59 seconds
Started Apr 18 12:36:02 PM PDT 24
Finished Apr 18 12:36:11 PM PDT 24
Peak memory 208244 kb
Host smart-4568d42a-ba61-46da-8b11-39c6bb39968c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575616465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1575616465
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3482047796
Short name T496
Test name
Test status
Simulation time 199932457 ps
CPU time 4.2 seconds
Started Apr 18 12:36:05 PM PDT 24
Finished Apr 18 12:36:10 PM PDT 24
Peak memory 215764 kb
Host smart-59f8cf81-8361-4ba8-8f13-38113ba90ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482047796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3482047796
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.705125443
Short name T93
Test name
Test status
Simulation time 71727119 ps
CPU time 0.78 seconds
Started Apr 18 12:36:09 PM PDT 24
Finished Apr 18 12:36:12 PM PDT 24
Peak memory 206120 kb
Host smart-9be38f43-9843-4c2c-8292-522fb21ceccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705125443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.705125443
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1388508847
Short name T318
Test name
Test status
Simulation time 2137493698 ps
CPU time 70.2 seconds
Started Apr 18 12:36:07 PM PDT 24
Finished Apr 18 12:37:19 PM PDT 24
Peak memory 216324 kb
Host smart-472b10cc-222e-48c1-a0f7-ab603c16756c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388508847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1388508847
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2392859849
Short name T744
Test name
Test status
Simulation time 575182670 ps
CPU time 5.89 seconds
Started Apr 18 12:36:13 PM PDT 24
Finished Apr 18 12:36:20 PM PDT 24
Peak memory 210528 kb
Host smart-fa41b78a-7221-4391-85ed-4f906c93c83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392859849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2392859849
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2032630928
Short name T416
Test name
Test status
Simulation time 376597223 ps
CPU time 3.97 seconds
Started Apr 18 12:36:13 PM PDT 24
Finished Apr 18 12:36:18 PM PDT 24
Peak memory 208308 kb
Host smart-7d91f081-bc73-403c-857e-b69fa5e919f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032630928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2032630928
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3287094542
Short name T83
Test name
Test status
Simulation time 3572064272 ps
CPU time 20.84 seconds
Started Apr 18 12:36:18 PM PDT 24
Finished Apr 18 12:36:39 PM PDT 24
Peak memory 220768 kb
Host smart-9eba28a4-e1fd-432d-9c60-c0499c5f0447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287094542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3287094542
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3054655377
Short name T249
Test name
Test status
Simulation time 133411987 ps
CPU time 4.07 seconds
Started Apr 18 12:36:18 PM PDT 24
Finished Apr 18 12:36:23 PM PDT 24
Peak memory 220628 kb
Host smart-8e4d64e2-a658-469e-bb98-06bb11202d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054655377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3054655377
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1761446198
Short name T663
Test name
Test status
Simulation time 152405191 ps
CPU time 3.26 seconds
Started Apr 18 12:36:02 PM PDT 24
Finished Apr 18 12:36:06 PM PDT 24
Peak memory 214628 kb
Host smart-af75bfa4-bdb3-44ab-bfb7-92bad3561edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761446198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1761446198
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1145742764
Short name T538
Test name
Test status
Simulation time 206714202 ps
CPU time 5.44 seconds
Started Apr 18 12:36:01 PM PDT 24
Finished Apr 18 12:36:07 PM PDT 24
Peak memory 208348 kb
Host smart-c91e79b3-4fb2-4bf8-8515-b606053b6707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145742764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1145742764
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2616268523
Short name T724
Test name
Test status
Simulation time 60651263 ps
CPU time 2.43 seconds
Started Apr 18 12:36:06 PM PDT 24
Finished Apr 18 12:36:10 PM PDT 24
Peak memory 207704 kb
Host smart-3459c708-4114-4846-9769-13f0aa66a987
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616268523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2616268523
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2639318675
Short name T330
Test name
Test status
Simulation time 315339368 ps
CPU time 5.29 seconds
Started Apr 18 12:36:08 PM PDT 24
Finished Apr 18 12:36:16 PM PDT 24
Peak memory 207048 kb
Host smart-30cbad33-9bc4-492a-bbe3-fb2478df4c51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639318675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2639318675
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2140824386
Short name T509
Test name
Test status
Simulation time 146942223 ps
CPU time 1.86 seconds
Started Apr 18 12:36:11 PM PDT 24
Finished Apr 18 12:36:14 PM PDT 24
Peak memory 207552 kb
Host smart-62036797-3d26-49c5-9f11-c2eb8eb572ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140824386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2140824386
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3850862751
Short name T652
Test name
Test status
Simulation time 822278532 ps
CPU time 5.12 seconds
Started Apr 18 12:36:08 PM PDT 24
Finished Apr 18 12:36:15 PM PDT 24
Peak memory 208884 kb
Host smart-c66abb6a-92cd-4225-98e3-4c57c7d1f515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850862751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3850862751
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1959963627
Short name T582
Test name
Test status
Simulation time 412600777 ps
CPU time 5.39 seconds
Started Apr 18 12:36:05 PM PDT 24
Finished Apr 18 12:36:11 PM PDT 24
Peak memory 207968 kb
Host smart-dc705a6e-2558-43ea-98d4-e988814bec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959963627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1959963627
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2769419723
Short name T866
Test name
Test status
Simulation time 201303158 ps
CPU time 8.31 seconds
Started Apr 18 12:36:19 PM PDT 24
Finished Apr 18 12:36:28 PM PDT 24
Peak memory 222944 kb
Host smart-0d5fd551-ca62-4621-89f1-2093f137aa0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769419723 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2769419723
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3402591724
Short name T473
Test name
Test status
Simulation time 2310720383 ps
CPU time 44.71 seconds
Started Apr 18 12:36:20 PM PDT 24
Finished Apr 18 12:37:05 PM PDT 24
Peak memory 220296 kb
Host smart-05d5d480-6606-4b11-8e55-3c7b37a71245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402591724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3402591724
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1024667406
Short name T541
Test name
Test status
Simulation time 238929253 ps
CPU time 3.33 seconds
Started Apr 18 12:36:16 PM PDT 24
Finished Apr 18 12:36:20 PM PDT 24
Peak memory 210664 kb
Host smart-074e71f8-4bce-4afc-bbe5-59150c9626bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024667406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1024667406
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3362381767
Short name T431
Test name
Test status
Simulation time 19054374 ps
CPU time 0.75 seconds
Started Apr 18 12:36:10 PM PDT 24
Finished Apr 18 12:36:12 PM PDT 24
Peak memory 206096 kb
Host smart-90c52e5f-8bbd-4a78-8cce-09d7e3f8ec4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362381767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3362381767
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2824724163
Short name T10
Test name
Test status
Simulation time 79266762 ps
CPU time 3.46 seconds
Started Apr 18 12:36:22 PM PDT 24
Finished Apr 18 12:36:26 PM PDT 24
Peak memory 222968 kb
Host smart-3f7119e0-8f9e-491e-ac3b-bf7d54ff7506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824724163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2824724163
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3763642299
Short name T856
Test name
Test status
Simulation time 280528077 ps
CPU time 2.98 seconds
Started Apr 18 12:36:09 PM PDT 24
Finished Apr 18 12:36:14 PM PDT 24
Peak memory 218484 kb
Host smart-fdfbc0cd-ce33-4953-871a-227b7a60b9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763642299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3763642299
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3045113856
Short name T381
Test name
Test status
Simulation time 465096707 ps
CPU time 5.75 seconds
Started Apr 18 12:36:05 PM PDT 24
Finished Apr 18 12:36:12 PM PDT 24
Peak memory 214436 kb
Host smart-e16ed521-df41-41ab-8851-1c97f0e77c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045113856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3045113856
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3998933972
Short name T772
Test name
Test status
Simulation time 2289131583 ps
CPU time 63.92 seconds
Started Apr 18 12:36:13 PM PDT 24
Finished Apr 18 12:37:18 PM PDT 24
Peak memory 239016 kb
Host smart-4b3b2143-ffb9-4152-a49f-bc0f1cf15e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998933972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3998933972
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3626817962
Short name T239
Test name
Test status
Simulation time 330875309 ps
CPU time 3.03 seconds
Started Apr 18 12:36:12 PM PDT 24
Finished Apr 18 12:36:16 PM PDT 24
Peak memory 206404 kb
Host smart-d8747baa-6d2d-4807-878e-68b19bcf3911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626817962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3626817962
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1683834157
Short name T467
Test name
Test status
Simulation time 66703629 ps
CPU time 4.05 seconds
Started Apr 18 12:36:04 PM PDT 24
Finished Apr 18 12:36:09 PM PDT 24
Peak memory 207028 kb
Host smart-c54de6a9-114d-4eb3-b01c-78ba708f7d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683834157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1683834157
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.859584248
Short name T403
Test name
Test status
Simulation time 218977761 ps
CPU time 4.91 seconds
Started Apr 18 12:36:03 PM PDT 24
Finished Apr 18 12:36:09 PM PDT 24
Peak memory 206840 kb
Host smart-efb724ed-b4c8-4403-bd79-37530c0b23ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859584248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.859584248
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3989372498
Short name T906
Test name
Test status
Simulation time 215286593 ps
CPU time 2.98 seconds
Started Apr 18 12:36:19 PM PDT 24
Finished Apr 18 12:36:22 PM PDT 24
Peak memory 206944 kb
Host smart-fbabb800-1fd9-45fd-8941-dfe8f4034ad9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989372498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3989372498
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.898428607
Short name T718
Test name
Test status
Simulation time 36552024 ps
CPU time 2.26 seconds
Started Apr 18 12:36:20 PM PDT 24
Finished Apr 18 12:36:23 PM PDT 24
Peak memory 207124 kb
Host smart-6d37d29d-770a-4ab4-9b3b-892c34b11f5a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898428607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.898428607
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.992467263
Short name T471
Test name
Test status
Simulation time 63688671 ps
CPU time 3.59 seconds
Started Apr 18 12:36:11 PM PDT 24
Finished Apr 18 12:36:16 PM PDT 24
Peak memory 208980 kb
Host smart-51271c87-3ff8-4a2d-b971-f6ff121388bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992467263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.992467263
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3548164997
Short name T106
Test name
Test status
Simulation time 160540484 ps
CPU time 4.39 seconds
Started Apr 18 12:36:07 PM PDT 24
Finished Apr 18 12:36:13 PM PDT 24
Peak memory 208344 kb
Host smart-060187a7-480d-44e3-89ee-878542bb2bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548164997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3548164997
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3902442622
Short name T222
Test name
Test status
Simulation time 2518674488 ps
CPU time 14.02 seconds
Started Apr 18 12:36:19 PM PDT 24
Finished Apr 18 12:36:34 PM PDT 24
Peak memory 208572 kb
Host smart-bb220fd7-29c2-43d3-9f12-63b9737c41fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902442622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3902442622
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.703929881
Short name T385
Test name
Test status
Simulation time 1351177543 ps
CPU time 35.77 seconds
Started Apr 18 12:36:09 PM PDT 24
Finished Apr 18 12:36:47 PM PDT 24
Peak memory 222708 kb
Host smart-f46374a4-1242-4b9a-9c94-7413f8f3eec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703929881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.703929881
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.900297150
Short name T480
Test name
Test status
Simulation time 80087098 ps
CPU time 4.09 seconds
Started Apr 18 12:36:15 PM PDT 24
Finished Apr 18 12:36:20 PM PDT 24
Peak memory 209348 kb
Host smart-823e84e0-d856-410f-89fb-52a0a48c573b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900297150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.900297150
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2203759038
Short name T747
Test name
Test status
Simulation time 111792437 ps
CPU time 1.82 seconds
Started Apr 18 12:36:06 PM PDT 24
Finished Apr 18 12:36:10 PM PDT 24
Peak memory 208904 kb
Host smart-ab0fae95-6031-48fb-a8e0-db3474b8938c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203759038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2203759038
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3723162791
Short name T865
Test name
Test status
Simulation time 13406959 ps
CPU time 0.73 seconds
Started Apr 18 12:36:16 PM PDT 24
Finished Apr 18 12:36:18 PM PDT 24
Peak memory 206156 kb
Host smart-52a99c72-9e0e-4ebb-ba2d-56401317b49e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723162791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3723162791
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3625648670
Short name T29
Test name
Test status
Simulation time 114640307 ps
CPU time 1.81 seconds
Started Apr 18 12:36:06 PM PDT 24
Finished Apr 18 12:36:09 PM PDT 24
Peak memory 218460 kb
Host smart-ab423319-36a6-4637-9d10-ad7da4d3006e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625648670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3625648670
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.202744276
Short name T66
Test name
Test status
Simulation time 97635727 ps
CPU time 4.01 seconds
Started Apr 18 12:36:12 PM PDT 24
Finished Apr 18 12:36:17 PM PDT 24
Peak memory 218400 kb
Host smart-67c33627-0665-4b61-a526-47b243073c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202744276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.202744276
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3077275328
Short name T530
Test name
Test status
Simulation time 296311291 ps
CPU time 4.14 seconds
Started Apr 18 12:36:22 PM PDT 24
Finished Apr 18 12:36:27 PM PDT 24
Peak memory 209576 kb
Host smart-bb4a98d6-43e1-4b40-9a62-57b45d2522c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077275328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3077275328
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3161478463
Short name T254
Test name
Test status
Simulation time 115502049 ps
CPU time 6.47 seconds
Started Apr 18 12:36:23 PM PDT 24
Finished Apr 18 12:36:30 PM PDT 24
Peak memory 209464 kb
Host smart-a34a2745-3fa5-42a5-9cdc-b573fd145043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161478463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3161478463
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1226199018
Short name T331
Test name
Test status
Simulation time 54122985 ps
CPU time 3.27 seconds
Started Apr 18 12:35:58 PM PDT 24
Finished Apr 18 12:36:02 PM PDT 24
Peak memory 207968 kb
Host smart-cb9fe427-bdd0-42c5-a86d-5cca9df30450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226199018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1226199018
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3967486842
Short name T779
Test name
Test status
Simulation time 80684339 ps
CPU time 2.81 seconds
Started Apr 18 12:36:05 PM PDT 24
Finished Apr 18 12:36:09 PM PDT 24
Peak memory 208608 kb
Host smart-8820ee5e-379e-4ebc-ac40-8a322828e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967486842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3967486842
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3548772350
Short name T214
Test name
Test status
Simulation time 119830959 ps
CPU time 3.15 seconds
Started Apr 18 12:36:06 PM PDT 24
Finished Apr 18 12:36:10 PM PDT 24
Peak memory 206988 kb
Host smart-7e54a9f1-4118-4e93-8a6d-eeac8dcffa62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548772350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3548772350
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.723076875
Short name T298
Test name
Test status
Simulation time 150954570 ps
CPU time 2.28 seconds
Started Apr 18 12:36:05 PM PDT 24
Finished Apr 18 12:36:08 PM PDT 24
Peak memory 207204 kb
Host smart-4a88f93e-68dd-4b81-8be1-e7df524ce5fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723076875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.723076875
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2568261546
Short name T753
Test name
Test status
Simulation time 24135270 ps
CPU time 2.02 seconds
Started Apr 18 12:36:16 PM PDT 24
Finished Apr 18 12:36:19 PM PDT 24
Peak memory 209044 kb
Host smart-4f73bdc6-8edf-4447-a198-cecd3fb2f9c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568261546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2568261546
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1181175373
Short name T476
Test name
Test status
Simulation time 35719874 ps
CPU time 1.86 seconds
Started Apr 18 12:36:21 PM PDT 24
Finished Apr 18 12:36:23 PM PDT 24
Peak memory 209668 kb
Host smart-11055b33-c6b4-486f-92e2-e592a953e627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181175373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1181175373
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.4287048798
Short name T399
Test name
Test status
Simulation time 135785499 ps
CPU time 3.82 seconds
Started Apr 18 12:36:03 PM PDT 24
Finished Apr 18 12:36:13 PM PDT 24
Peak memory 207260 kb
Host smart-d6e361bd-88b6-4cce-a855-586758cfd28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287048798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.4287048798
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2375003801
Short name T128
Test name
Test status
Simulation time 586150235 ps
CPU time 17.68 seconds
Started Apr 18 12:36:08 PM PDT 24
Finished Apr 18 12:36:28 PM PDT 24
Peak memory 223104 kb
Host smart-6e1bdea1-3604-4747-b66b-5245e695d894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375003801 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2375003801
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1456754171
Short name T878
Test name
Test status
Simulation time 68386982 ps
CPU time 3.49 seconds
Started Apr 18 12:36:23 PM PDT 24
Finished Apr 18 12:36:27 PM PDT 24
Peak memory 208488 kb
Host smart-1e643eb4-3ea7-4e7b-ab39-f02a91030505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456754171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1456754171
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1349390330
Short name T871
Test name
Test status
Simulation time 165140935 ps
CPU time 1.81 seconds
Started Apr 18 12:36:22 PM PDT 24
Finished Apr 18 12:36:24 PM PDT 24
Peak memory 210292 kb
Host smart-8f4b040e-d9de-4aa2-a997-80cb4184da4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349390330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1349390330
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2968901983
Short name T590
Test name
Test status
Simulation time 16321706 ps
CPU time 0.76 seconds
Started Apr 18 12:36:12 PM PDT 24
Finished Apr 18 12:36:14 PM PDT 24
Peak memory 206184 kb
Host smart-45925d50-3481-4fa9-b113-afc39a9306cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968901983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2968901983
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1135415612
Short name T315
Test name
Test status
Simulation time 402728276 ps
CPU time 5.77 seconds
Started Apr 18 12:36:21 PM PDT 24
Finished Apr 18 12:36:28 PM PDT 24
Peak memory 214548 kb
Host smart-aebfb9b6-76e9-47db-92d5-d66b26e36631
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135415612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1135415612
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1594809865
Short name T816
Test name
Test status
Simulation time 338958269 ps
CPU time 4.75 seconds
Started Apr 18 12:36:17 PM PDT 24
Finished Apr 18 12:36:23 PM PDT 24
Peak memory 210080 kb
Host smart-2c4ab555-3764-4b76-84b2-a33c944b8bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594809865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1594809865
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1725534527
Short name T440
Test name
Test status
Simulation time 184577393 ps
CPU time 4.96 seconds
Started Apr 18 12:36:13 PM PDT 24
Finished Apr 18 12:36:19 PM PDT 24
Peak memory 208568 kb
Host smart-a298b20c-892a-4d95-ab83-3b367d8e615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725534527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1725534527
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2764908683
Short name T650
Test name
Test status
Simulation time 342432869 ps
CPU time 3.92 seconds
Started Apr 18 12:36:12 PM PDT 24
Finished Apr 18 12:36:17 PM PDT 24
Peak memory 208320 kb
Host smart-fdf97ff1-ad3a-4201-bb11-5386e3d0e8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764908683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2764908683
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.828311074
Short name T374
Test name
Test status
Simulation time 120711603 ps
CPU time 5.91 seconds
Started Apr 18 12:36:12 PM PDT 24
Finished Apr 18 12:36:19 PM PDT 24
Peak memory 214484 kb
Host smart-fb82e069-97c5-4674-9627-492383180b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828311074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.828311074
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2710605892
Short name T535
Test name
Test status
Simulation time 174900923 ps
CPU time 5 seconds
Started Apr 18 12:36:10 PM PDT 24
Finished Apr 18 12:36:17 PM PDT 24
Peak memory 220624 kb
Host smart-caefdeae-37c2-4dde-961d-aa4709c1a3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710605892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2710605892
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.599314033
Short name T593
Test name
Test status
Simulation time 184400936 ps
CPU time 6.75 seconds
Started Apr 18 12:36:13 PM PDT 24
Finished Apr 18 12:36:21 PM PDT 24
Peak memory 209092 kb
Host smart-db60b810-e365-45b8-9622-7998ea83594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599314033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.599314033
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3320117772
Short name T884
Test name
Test status
Simulation time 49756758 ps
CPU time 2.63 seconds
Started Apr 18 12:36:21 PM PDT 24
Finished Apr 18 12:36:24 PM PDT 24
Peak memory 206856 kb
Host smart-da93f12e-d836-4b3d-aa56-f5b833850cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320117772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3320117772
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2219135509
Short name T852
Test name
Test status
Simulation time 829997444 ps
CPU time 3.63 seconds
Started Apr 18 12:36:23 PM PDT 24
Finished Apr 18 12:36:27 PM PDT 24
Peak memory 208864 kb
Host smart-d3d5f804-9f3f-48eb-b73e-f2eab3f2e21f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219135509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2219135509
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3732476573
Short name T670
Test name
Test status
Simulation time 263575868 ps
CPU time 3.58 seconds
Started Apr 18 12:36:11 PM PDT 24
Finished Apr 18 12:36:16 PM PDT 24
Peak memory 208648 kb
Host smart-02589ee4-6fb8-4240-8ecc-9dc685fbadb0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732476573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3732476573
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.763341062
Short name T527
Test name
Test status
Simulation time 471331021 ps
CPU time 6.75 seconds
Started Apr 18 12:36:16 PM PDT 24
Finished Apr 18 12:36:23 PM PDT 24
Peak memory 208712 kb
Host smart-5cf40d24-4521-4049-a99c-1d3c8c8ad26e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763341062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.763341062
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3752920741
Short name T569
Test name
Test status
Simulation time 2792789635 ps
CPU time 14.66 seconds
Started Apr 18 12:36:10 PM PDT 24
Finished Apr 18 12:36:27 PM PDT 24
Peak memory 209208 kb
Host smart-20e700e4-02cd-4179-961b-baa92a36adac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752920741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3752920741
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.587646079
Short name T854
Test name
Test status
Simulation time 267287094 ps
CPU time 6.16 seconds
Started Apr 18 12:36:19 PM PDT 24
Finished Apr 18 12:36:26 PM PDT 24
Peak memory 208432 kb
Host smart-6f0390a6-4e74-406f-8683-8973ed2c281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587646079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.587646079
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1639320770
Short name T277
Test name
Test status
Simulation time 386962936 ps
CPU time 19.37 seconds
Started Apr 18 12:36:26 PM PDT 24
Finished Apr 18 12:36:46 PM PDT 24
Peak memory 220740 kb
Host smart-43d8abf6-7361-48dc-bd0a-f8f0ffdf7227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639320770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1639320770
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1743730888
Short name T737
Test name
Test status
Simulation time 817216771 ps
CPU time 11.26 seconds
Started Apr 18 12:36:12 PM PDT 24
Finished Apr 18 12:36:25 PM PDT 24
Peak memory 222836 kb
Host smart-fc5771c9-3ca9-4614-866b-2ef7a4b8c10d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743730888 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1743730888
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.4238001724
Short name T599
Test name
Test status
Simulation time 170510033 ps
CPU time 3.5 seconds
Started Apr 18 12:36:15 PM PDT 24
Finished Apr 18 12:36:20 PM PDT 24
Peak memory 207940 kb
Host smart-fec837b5-557e-4c7f-8c7e-466eb94051e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238001724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.4238001724
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.975055112
Short name T796
Test name
Test status
Simulation time 667309615 ps
CPU time 2.49 seconds
Started Apr 18 12:36:24 PM PDT 24
Finished Apr 18 12:36:37 PM PDT 24
Peak memory 210628 kb
Host smart-88827e17-fed2-4e3c-8c79-6fa18209bb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975055112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.975055112
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1460949532
Short name T512
Test name
Test status
Simulation time 8970518 ps
CPU time 0.82 seconds
Started Apr 18 12:36:19 PM PDT 24
Finished Apr 18 12:36:21 PM PDT 24
Peak memory 206216 kb
Host smart-fe181318-28fb-4039-9515-2aa9d2b6a49f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460949532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1460949532
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2845232252
Short name T418
Test name
Test status
Simulation time 222757829 ps
CPU time 3.49 seconds
Started Apr 18 12:36:13 PM PDT 24
Finished Apr 18 12:36:18 PM PDT 24
Peak memory 214520 kb
Host smart-2babe22d-58de-4b8d-bd45-86853e313c29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845232252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2845232252
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1544654871
Short name T573
Test name
Test status
Simulation time 46194884 ps
CPU time 2.77 seconds
Started Apr 18 12:36:28 PM PDT 24
Finished Apr 18 12:36:32 PM PDT 24
Peak memory 219368 kb
Host smart-0adafd84-0732-44da-b3ec-43c43366492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544654871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1544654871
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2549496409
Short name T47
Test name
Test status
Simulation time 259108137 ps
CPU time 8.6 seconds
Started Apr 18 12:36:24 PM PDT 24
Finished Apr 18 12:36:38 PM PDT 24
Peak memory 218612 kb
Host smart-a74c5b1d-68f9-4d9b-8f06-35040fcd952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549496409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2549496409
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1972710553
Short name T470
Test name
Test status
Simulation time 47500941 ps
CPU time 2.36 seconds
Started Apr 18 12:36:28 PM PDT 24
Finished Apr 18 12:36:31 PM PDT 24
Peak memory 216044 kb
Host smart-4ba61b0e-74c0-49dc-a2f5-0308d94c8dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972710553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1972710553
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.379005885
Short name T265
Test name
Test status
Simulation time 7041535314 ps
CPU time 81.53 seconds
Started Apr 18 12:36:22 PM PDT 24
Finished Apr 18 12:37:44 PM PDT 24
Peak memory 222780 kb
Host smart-bbebd254-ff5e-436f-8413-2cb81e93ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379005885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.379005885
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1185891292
Short name T883
Test name
Test status
Simulation time 283971074 ps
CPU time 4.03 seconds
Started Apr 18 12:36:17 PM PDT 24
Finished Apr 18 12:36:22 PM PDT 24
Peak memory 208848 kb
Host smart-e23212b1-5e51-4faa-ae36-7bf668f1407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185891292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1185891292
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2784016939
Short name T444
Test name
Test status
Simulation time 783442758 ps
CPU time 9.84 seconds
Started Apr 18 12:36:15 PM PDT 24
Finished Apr 18 12:36:26 PM PDT 24
Peak memory 209208 kb
Host smart-d985e887-329c-449e-9d30-ad857465b448
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784016939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2784016939
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3950560185
Short name T354
Test name
Test status
Simulation time 366566266 ps
CPU time 2.65 seconds
Started Apr 18 12:36:20 PM PDT 24
Finished Apr 18 12:36:24 PM PDT 24
Peak memory 207776 kb
Host smart-127ca7eb-7ac4-4f53-bc08-906f9d94f7fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950560185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3950560185
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2016404353
Short name T532
Test name
Test status
Simulation time 126015611 ps
CPU time 2.29 seconds
Started Apr 18 12:36:39 PM PDT 24
Finished Apr 18 12:36:42 PM PDT 24
Peak memory 206972 kb
Host smart-c76f0c6b-f888-44d8-ba5a-9a9d9c723b6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016404353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2016404353
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1897216599
Short name T832
Test name
Test status
Simulation time 267306083 ps
CPU time 2.94 seconds
Started Apr 18 12:36:19 PM PDT 24
Finished Apr 18 12:36:23 PM PDT 24
Peak memory 214612 kb
Host smart-e679db1f-8feb-4864-9863-b1f907586630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897216599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1897216599
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2722421292
Short name T547
Test name
Test status
Simulation time 237574557 ps
CPU time 2.99 seconds
Started Apr 18 12:36:20 PM PDT 24
Finished Apr 18 12:36:24 PM PDT 24
Peak memory 208732 kb
Host smart-37b602dc-693a-423f-aefb-86040c9ae2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722421292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2722421292
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.914861287
Short name T52
Test name
Test status
Simulation time 153073762 ps
CPU time 4.26 seconds
Started Apr 18 12:36:22 PM PDT 24
Finished Apr 18 12:36:27 PM PDT 24
Peak memory 215412 kb
Host smart-254e338e-2fc8-4ae8-bd9a-be2dce8d65b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914861287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.914861287
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.4042750499
Short name T843
Test name
Test status
Simulation time 1113884482 ps
CPU time 23.43 seconds
Started Apr 18 12:36:27 PM PDT 24
Finished Apr 18 12:36:51 PM PDT 24
Peak memory 222808 kb
Host smart-10cbd224-a73b-4abc-9300-26829c11a14f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042750499 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.4042750499
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2303343255
Short name T397
Test name
Test status
Simulation time 7728109042 ps
CPU time 88.4 seconds
Started Apr 18 12:36:26 PM PDT 24
Finished Apr 18 12:37:56 PM PDT 24
Peak memory 209964 kb
Host smart-609045b9-d970-4b84-a1c3-b5ddfffd39d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303343255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2303343255
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.4235838794
Short name T394
Test name
Test status
Simulation time 33852555 ps
CPU time 1.28 seconds
Started Apr 18 12:36:27 PM PDT 24
Finished Apr 18 12:36:29 PM PDT 24
Peak memory 210156 kb
Host smart-4a52b34d-2266-4c15-b88a-9113bf767af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235838794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.4235838794
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2767611480
Short name T700
Test name
Test status
Simulation time 35893677 ps
CPU time 0.79 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:19 PM PDT 24
Peak memory 206184 kb
Host smart-cdc27235-c616-464d-90c4-b1bf85ca2744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767611480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2767611480
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.398171288
Short name T733
Test name
Test status
Simulation time 33593750 ps
CPU time 2.85 seconds
Started Apr 18 12:34:10 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 215324 kb
Host smart-dab3d586-9079-467e-a8b4-5e176e8d2836
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398171288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.398171288
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3729382694
Short name T19
Test name
Test status
Simulation time 1996633361 ps
CPU time 5.84 seconds
Started Apr 18 12:34:07 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 208272 kb
Host smart-c5d37c48-48cc-4237-91ba-2b7b1ed37f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729382694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3729382694
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1434551383
Short name T592
Test name
Test status
Simulation time 942759388 ps
CPU time 7.17 seconds
Started Apr 18 12:34:11 PM PDT 24
Finished Apr 18 12:34:19 PM PDT 24
Peak memory 214616 kb
Host smart-3b9ab54a-2729-4775-a253-7f72329dd7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434551383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1434551383
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.17108633
Short name T192
Test name
Test status
Simulation time 52740444 ps
CPU time 3.26 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:18 PM PDT 24
Peak memory 209228 kb
Host smart-c33651c6-f689-4c2f-a9ff-e3dde2469009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17108633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.17108633
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2229109358
Short name T851
Test name
Test status
Simulation time 1012769357 ps
CPU time 9.08 seconds
Started Apr 18 12:34:07 PM PDT 24
Finished Apr 18 12:34:18 PM PDT 24
Peak memory 214412 kb
Host smart-1b640b36-46eb-4faa-934b-66a3f7c8b21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229109358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2229109358
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.427077396
Short name T247
Test name
Test status
Simulation time 240730746 ps
CPU time 3.05 seconds
Started Apr 18 12:34:09 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 209276 kb
Host smart-711d217c-582b-4044-a713-f5d825921948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427077396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.427077396
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3774425997
Short name T646
Test name
Test status
Simulation time 983592550 ps
CPU time 7.97 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:22 PM PDT 24
Peak memory 214536 kb
Host smart-ff49a9f7-883e-485e-8509-61171dbaacf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774425997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3774425997
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2872226491
Short name T400
Test name
Test status
Simulation time 796174031 ps
CPU time 19.46 seconds
Started Apr 18 12:34:11 PM PDT 24
Finished Apr 18 12:34:31 PM PDT 24
Peak memory 208700 kb
Host smart-808f74fd-7973-4732-8c7c-4940ddd935d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872226491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2872226491
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3481905258
Short name T479
Test name
Test status
Simulation time 236997406 ps
CPU time 2.56 seconds
Started Apr 18 12:34:06 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 208532 kb
Host smart-fc6d66d1-02a8-4f88-8ca3-795adec2f469
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481905258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3481905258
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.919233336
Short name T710
Test name
Test status
Simulation time 212987260 ps
CPU time 2.82 seconds
Started Apr 18 12:34:09 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 207012 kb
Host smart-bb870a94-2e06-47ed-b425-f332197336ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919233336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.919233336
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.4171840156
Short name T522
Test name
Test status
Simulation time 2950925772 ps
CPU time 47.37 seconds
Started Apr 18 12:34:10 PM PDT 24
Finished Apr 18 12:34:58 PM PDT 24
Peak memory 208640 kb
Host smart-38007d6f-5e5e-4cd7-b65e-84aeb8ef9e4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171840156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.4171840156
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1493238959
Short name T729
Test name
Test status
Simulation time 60671352 ps
CPU time 2.74 seconds
Started Apr 18 12:34:07 PM PDT 24
Finished Apr 18 12:34:10 PM PDT 24
Peak memory 218616 kb
Host smart-50a545eb-9386-450c-bbb6-7fad2a02aa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493238959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1493238959
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3122167918
Short name T436
Test name
Test status
Simulation time 85912386 ps
CPU time 3.17 seconds
Started Apr 18 12:34:10 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 206840 kb
Host smart-a303535b-a1d0-4f0f-b6cf-d06708cbeb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122167918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3122167918
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3923971489
Short name T112
Test name
Test status
Simulation time 526204381 ps
CPU time 11.69 seconds
Started Apr 18 12:34:07 PM PDT 24
Finished Apr 18 12:34:20 PM PDT 24
Peak memory 220844 kb
Host smart-184ac5a3-f883-43f9-8352-3a426bef3216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923971489 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3923971489
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2232933295
Short name T360
Test name
Test status
Simulation time 2658911894 ps
CPU time 12.31 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:27 PM PDT 24
Peak memory 210572 kb
Host smart-756d4a2e-7bb9-4dd9-adff-4821f9abd30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232933295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2232933295
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2189545750
Short name T209
Test name
Test status
Simulation time 43354907 ps
CPU time 2.09 seconds
Started Apr 18 12:34:10 PM PDT 24
Finished Apr 18 12:34:13 PM PDT 24
Peak memory 210200 kb
Host smart-ee9fc1c0-0128-432f-b3b1-8e45ddf8e8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189545750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2189545750
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.177312106
Short name T635
Test name
Test status
Simulation time 18755323 ps
CPU time 0.85 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:15 PM PDT 24
Peak memory 206252 kb
Host smart-53bc460e-a56c-4adc-a70a-5ce90a18822c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177312106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.177312106
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3529215139
Short name T350
Test name
Test status
Simulation time 179887405 ps
CPU time 9.14 seconds
Started Apr 18 12:34:14 PM PDT 24
Finished Apr 18 12:34:24 PM PDT 24
Peak memory 216168 kb
Host smart-8c1104eb-6b92-429f-a018-0b449dcc3342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3529215139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3529215139
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2357780783
Short name T567
Test name
Test status
Simulation time 172828121 ps
CPU time 2.55 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 218228 kb
Host smart-398d031c-13da-4013-af72-ecaf7bd08893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357780783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2357780783
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4293092445
Short name T64
Test name
Test status
Simulation time 273555062 ps
CPU time 4.25 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:23 PM PDT 24
Peak memory 218600 kb
Host smart-bf218d86-ddf7-4de4-b2eb-1d39e775c025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293092445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4293092445
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.959530804
Short name T79
Test name
Test status
Simulation time 311116554 ps
CPU time 4.27 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:19 PM PDT 24
Peak memory 209472 kb
Host smart-bf5fa6b0-daee-4220-a5d8-2391abfd770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959530804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.959530804
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1468408420
Short name T376
Test name
Test status
Simulation time 568777384 ps
CPU time 5.25 seconds
Started Apr 18 12:34:15 PM PDT 24
Finished Apr 18 12:34:22 PM PDT 24
Peak memory 214528 kb
Host smart-66e1952c-7a3b-411d-9e58-b1da8200b78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468408420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1468408420
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1712976889
Short name T677
Test name
Test status
Simulation time 34664234 ps
CPU time 2.47 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 209692 kb
Host smart-92ca209e-91cc-4d3a-a597-4407251a5c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712976889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1712976889
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.974735944
Short name T102
Test name
Test status
Simulation time 441231858 ps
CPU time 8.48 seconds
Started Apr 18 12:34:11 PM PDT 24
Finished Apr 18 12:34:21 PM PDT 24
Peak memory 208316 kb
Host smart-9d01a38a-36bb-4241-bd20-80b4279b71a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974735944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.974735944
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4250028225
Short name T788
Test name
Test status
Simulation time 73296398 ps
CPU time 3.43 seconds
Started Apr 18 12:34:12 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 207000 kb
Host smart-18764587-6a42-43db-bdc3-dd5c5b615114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250028225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4250028225
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1681038893
Short name T786
Test name
Test status
Simulation time 964675497 ps
CPU time 2.94 seconds
Started Apr 18 12:34:15 PM PDT 24
Finished Apr 18 12:34:20 PM PDT 24
Peak memory 206940 kb
Host smart-ff0058f6-e34d-4c9c-9bd8-a51f8e400454
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681038893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1681038893
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2189090073
Short name T184
Test name
Test status
Simulation time 89357793 ps
CPU time 4.09 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:18 PM PDT 24
Peak memory 206932 kb
Host smart-a496759b-048b-48da-a77a-d307a5abecda
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189090073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2189090073
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2626873678
Short name T571
Test name
Test status
Simulation time 7709450989 ps
CPU time 55.69 seconds
Started Apr 18 12:34:15 PM PDT 24
Finished Apr 18 12:35:12 PM PDT 24
Peak memory 209016 kb
Host smart-0c6d3331-fbe6-464f-a2ec-26ae6a985950
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626873678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2626873678
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3093689569
Short name T200
Test name
Test status
Simulation time 182967291 ps
CPU time 2.2 seconds
Started Apr 18 12:34:12 PM PDT 24
Finished Apr 18 12:34:15 PM PDT 24
Peak memory 209224 kb
Host smart-dc367711-09e9-428e-96eb-7f2cbb46152a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093689569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3093689569
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.578085331
Short name T674
Test name
Test status
Simulation time 161866522 ps
CPU time 4.54 seconds
Started Apr 18 12:34:14 PM PDT 24
Finished Apr 18 12:34:20 PM PDT 24
Peak memory 208576 kb
Host smart-1ec1ebb8-6660-44e8-b4de-6fbae3144a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578085331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.578085331
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.738824909
Short name T289
Test name
Test status
Simulation time 10706233428 ps
CPU time 61.78 seconds
Started Apr 18 12:34:11 PM PDT 24
Finished Apr 18 12:35:13 PM PDT 24
Peak memory 222804 kb
Host smart-23ec7dff-f557-4cc6-aa90-c6eeeedfa08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738824909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.738824909
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3844672831
Short name T179
Test name
Test status
Simulation time 2791732022 ps
CPU time 23.25 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 222900 kb
Host smart-6b691bd7-8ad3-4539-8bf2-7c0d2d86ca99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844672831 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3844672831
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.329020175
Short name T777
Test name
Test status
Simulation time 226605686 ps
CPU time 3.61 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:18 PM PDT 24
Peak memory 208604 kb
Host smart-a8c75f41-220b-4963-a4b6-6ec76c32447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329020175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.329020175
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3054777425
Short name T50
Test name
Test status
Simulation time 62423450 ps
CPU time 1.49 seconds
Started Apr 18 12:34:11 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 210188 kb
Host smart-a466c468-e4b7-4d1d-bbee-2619f8ad3cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054777425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3054777425
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3143014604
Short name T437
Test name
Test status
Simulation time 43697196 ps
CPU time 0.74 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:20 PM PDT 24
Peak memory 206192 kb
Host smart-4ea1e6ad-2b2d-4aab-9793-8b3cfba95717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143014604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3143014604
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3778356218
Short name T279
Test name
Test status
Simulation time 135281764 ps
CPU time 6.81 seconds
Started Apr 18 12:34:12 PM PDT 24
Finished Apr 18 12:34:20 PM PDT 24
Peak memory 215424 kb
Host smart-a2d0ac4f-7089-4871-8c47-023447017f73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778356218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3778356218
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2488614876
Short name T887
Test name
Test status
Simulation time 254130323 ps
CPU time 5.84 seconds
Started Apr 18 12:34:16 PM PDT 24
Finished Apr 18 12:34:23 PM PDT 24
Peak memory 218924 kb
Host smart-de5351bc-7a52-4ee3-a683-5d383fb80bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488614876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2488614876
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1798581905
Short name T810
Test name
Test status
Simulation time 238152964 ps
CPU time 3.02 seconds
Started Apr 18 12:34:10 PM PDT 24
Finished Apr 18 12:34:14 PM PDT 24
Peak memory 208824 kb
Host smart-44e890ee-83b6-43b2-b717-bd772aef9adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798581905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1798581905
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3786097206
Short name T85
Test name
Test status
Simulation time 2654792071 ps
CPU time 9.93 seconds
Started Apr 18 12:34:17 PM PDT 24
Finished Apr 18 12:34:28 PM PDT 24
Peak memory 214672 kb
Host smart-e62b62e8-021f-408d-b894-50c74a0a9b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786097206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3786097206
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3476305566
Short name T285
Test name
Test status
Simulation time 1552354968 ps
CPU time 11.25 seconds
Started Apr 18 12:34:24 PM PDT 24
Finished Apr 18 12:34:36 PM PDT 24
Peak memory 222676 kb
Host smart-4ea4f121-ce90-4257-a492-a33cc2db53b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476305566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3476305566
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.416903990
Short name T472
Test name
Test status
Simulation time 129647277 ps
CPU time 4.26 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:19 PM PDT 24
Peak memory 214516 kb
Host smart-eb8a6ecb-8875-4a41-92c3-a20a3f3db550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416903990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.416903990
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4165889396
Short name T369
Test name
Test status
Simulation time 687752395 ps
CPU time 5.84 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:21 PM PDT 24
Peak memory 218768 kb
Host smart-1680bcd4-e183-4d17-8a1d-1b32d1b031ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165889396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4165889396
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4020961632
Short name T366
Test name
Test status
Simulation time 86385870 ps
CPU time 3.85 seconds
Started Apr 18 12:34:15 PM PDT 24
Finished Apr 18 12:34:20 PM PDT 24
Peak memory 208824 kb
Host smart-938a610e-9c62-4117-8ebc-857b4beda1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020961632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4020961632
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.325523566
Short name T516
Test name
Test status
Simulation time 34600597 ps
CPU time 2.37 seconds
Started Apr 18 12:34:12 PM PDT 24
Finished Apr 18 12:34:15 PM PDT 24
Peak memory 207104 kb
Host smart-9c2df7fc-3123-4180-a8b9-2c0f4c4d75ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325523566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.325523566
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2466559398
Short name T639
Test name
Test status
Simulation time 64359950 ps
CPU time 3.19 seconds
Started Apr 18 12:34:15 PM PDT 24
Finished Apr 18 12:34:20 PM PDT 24
Peak memory 206956 kb
Host smart-01e7c913-7050-42c2-9e5e-16dcea348c2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466559398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2466559398
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1891783343
Short name T726
Test name
Test status
Simulation time 140712579 ps
CPU time 3.39 seconds
Started Apr 18 12:34:11 PM PDT 24
Finished Apr 18 12:34:16 PM PDT 24
Peak memory 208852 kb
Host smart-272ba3f2-e02b-4220-97cc-e573e3f6855d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891783343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1891783343
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3736040883
Short name T261
Test name
Test status
Simulation time 806237982 ps
CPU time 7.91 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:27 PM PDT 24
Peak memory 208668 kb
Host smart-90e22488-08a7-472f-b11b-e9fa2ad1f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736040883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3736040883
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.398036154
Short name T75
Test name
Test status
Simulation time 55447215 ps
CPU time 2.87 seconds
Started Apr 18 12:34:13 PM PDT 24
Finished Apr 18 12:34:17 PM PDT 24
Peak memory 206988 kb
Host smart-e777241a-2bc0-4a7b-8cb6-625cc1a62cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398036154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.398036154
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1651957514
Short name T347
Test name
Test status
Simulation time 991324922 ps
CPU time 4.86 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:24 PM PDT 24
Peak memory 218560 kb
Host smart-e3f8035b-0a2d-44f5-9837-1987510a3346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651957514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1651957514
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3739122670
Short name T579
Test name
Test status
Simulation time 3766468684 ps
CPU time 21.72 seconds
Started Apr 18 12:34:16 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 212232 kb
Host smart-1af5b9a5-e95e-40d6-94f8-1f61099b784f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739122670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3739122670
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2255082603
Short name T78
Test name
Test status
Simulation time 22644606 ps
CPU time 0.72 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:19 PM PDT 24
Peak memory 206268 kb
Host smart-e00d5f59-5867-4753-be00-81ac7abda0d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255082603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2255082603
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.802738466
Short name T831
Test name
Test status
Simulation time 207448124 ps
CPU time 2.62 seconds
Started Apr 18 12:34:23 PM PDT 24
Finished Apr 18 12:34:27 PM PDT 24
Peak memory 210184 kb
Host smart-2b7b05a2-c33d-4fcf-a2b9-f7c4291e216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802738466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.802738466
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4281969450
Short name T410
Test name
Test status
Simulation time 31830892 ps
CPU time 2.34 seconds
Started Apr 18 12:34:24 PM PDT 24
Finished Apr 18 12:34:27 PM PDT 24
Peak memory 210556 kb
Host smart-7573d649-f9a8-459a-9ff2-d25b1726435b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281969450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4281969450
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3067259006
Short name T344
Test name
Test status
Simulation time 1068188061 ps
CPU time 7.46 seconds
Started Apr 18 12:34:17 PM PDT 24
Finished Apr 18 12:34:26 PM PDT 24
Peak memory 209804 kb
Host smart-0c4f85d0-2d79-4a55-9054-967763d15637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067259006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3067259006
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3238515474
Short name T356
Test name
Test status
Simulation time 2083502544 ps
CPU time 14.27 seconds
Started Apr 18 12:34:23 PM PDT 24
Finished Apr 18 12:34:38 PM PDT 24
Peak memory 214544 kb
Host smart-f121b00f-3fe9-481e-9760-431d31e2d58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238515474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3238515474
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.984690620
Short name T55
Test name
Test status
Simulation time 76241423 ps
CPU time 3.08 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:22 PM PDT 24
Peak memory 218444 kb
Host smart-e35b094b-cc7e-4e6b-b464-0d5d0e049f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984690620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.984690620
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.544841900
Short name T627
Test name
Test status
Simulation time 109757303 ps
CPU time 5.23 seconds
Started Apr 18 12:34:24 PM PDT 24
Finished Apr 18 12:34:30 PM PDT 24
Peak memory 214464 kb
Host smart-bfbca8a6-42a0-4fd6-a3a5-618fe767539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544841900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.544841900
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2427993668
Short name T658
Test name
Test status
Simulation time 79135715 ps
CPU time 2.65 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:22 PM PDT 24
Peak memory 208548 kb
Host smart-13557b8a-7089-4d65-85b1-5ee34d9dd520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427993668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2427993668
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1707178942
Short name T542
Test name
Test status
Simulation time 37140073 ps
CPU time 2.01 seconds
Started Apr 18 12:34:21 PM PDT 24
Finished Apr 18 12:34:24 PM PDT 24
Peak memory 208192 kb
Host smart-811ad217-fa12-4d9c-9742-0b5fd8079c98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707178942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1707178942
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2355762287
Short name T407
Test name
Test status
Simulation time 3159128847 ps
CPU time 11.78 seconds
Started Apr 18 12:34:20 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 207032 kb
Host smart-59a01940-e488-4fb9-91cc-83f84242713c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355762287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2355762287
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3992010468
Short name T738
Test name
Test status
Simulation time 151941824 ps
CPU time 2.97 seconds
Started Apr 18 12:34:20 PM PDT 24
Finished Apr 18 12:34:23 PM PDT 24
Peak memory 207844 kb
Host smart-fc00e01d-efeb-4baa-9176-4189165e67b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992010468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3992010468
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1026021571
Short name T814
Test name
Test status
Simulation time 47793684 ps
CPU time 2.55 seconds
Started Apr 18 12:34:19 PM PDT 24
Finished Apr 18 12:34:22 PM PDT 24
Peak memory 209568 kb
Host smart-98e19c88-81a9-4a2e-8440-f6936b5e2dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026021571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1026021571
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3515447137
Short name T449
Test name
Test status
Simulation time 83055718 ps
CPU time 2.79 seconds
Started Apr 18 12:34:22 PM PDT 24
Finished Apr 18 12:34:26 PM PDT 24
Peak memory 209040 kb
Host smart-18bcdf93-e915-4e11-89c5-3c4762b242bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515447137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3515447137
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1298476316
Short name T178
Test name
Test status
Simulation time 944460973 ps
CPU time 8.68 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:28 PM PDT 24
Peak memory 218232 kb
Host smart-7fa6f7b5-847c-4e1b-a05f-a67033c4a8b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298476316 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1298476316
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1400968100
Short name T299
Test name
Test status
Simulation time 643720673 ps
CPU time 5.53 seconds
Started Apr 18 12:34:19 PM PDT 24
Finished Apr 18 12:34:26 PM PDT 24
Peak memory 207808 kb
Host smart-13cf0bb3-b402-4325-8592-010de8e0f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400968100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1400968100
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1787510973
Short name T616
Test name
Test status
Simulation time 219208137 ps
CPU time 3.27 seconds
Started Apr 18 12:34:20 PM PDT 24
Finished Apr 18 12:34:24 PM PDT 24
Peak memory 210248 kb
Host smart-0a66511c-c7b0-43fd-8865-2a9fe5e3429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787510973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1787510973
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1739591297
Short name T589
Test name
Test status
Simulation time 45393813 ps
CPU time 0.86 seconds
Started Apr 18 12:34:29 PM PDT 24
Finished Apr 18 12:34:30 PM PDT 24
Peak memory 206096 kb
Host smart-921e9f8b-3b4d-459e-82a8-8dd7c39030fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739591297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1739591297
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1411941223
Short name T260
Test name
Test status
Simulation time 327104946 ps
CPU time 9.78 seconds
Started Apr 18 12:34:24 PM PDT 24
Finished Apr 18 12:34:34 PM PDT 24
Peak memory 214864 kb
Host smart-dd5b9e7c-e98d-4055-8a18-f86bbee06a37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411941223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1411941223
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1626056215
Short name T680
Test name
Test status
Simulation time 288093015 ps
CPU time 5.1 seconds
Started Apr 18 12:34:28 PM PDT 24
Finished Apr 18 12:34:33 PM PDT 24
Peak memory 209908 kb
Host smart-c7638959-7685-4849-993d-6081eb31105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626056215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1626056215
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4051156511
Short name T215
Test name
Test status
Simulation time 303735017 ps
CPU time 4.54 seconds
Started Apr 18 12:34:24 PM PDT 24
Finished Apr 18 12:34:30 PM PDT 24
Peak memory 209280 kb
Host smart-a9f70c7e-b6b8-4650-8104-934f3cd287a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051156511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4051156511
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1176594534
Short name T671
Test name
Test status
Simulation time 216032634 ps
CPU time 5.29 seconds
Started Apr 18 12:34:29 PM PDT 24
Finished Apr 18 12:34:34 PM PDT 24
Peak memory 214464 kb
Host smart-60456081-5019-4758-ad7b-f05d12b3523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176594534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1176594534
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.817209953
Short name T25
Test name
Test status
Simulation time 1003061881 ps
CPU time 25.57 seconds
Started Apr 18 12:34:26 PM PDT 24
Finished Apr 18 12:34:53 PM PDT 24
Peak memory 222668 kb
Host smart-4ad447b1-fdca-43ae-b4b7-f8ba23b9e59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817209953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.817209953
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3952574796
Short name T748
Test name
Test status
Simulation time 82463137 ps
CPU time 2.78 seconds
Started Apr 18 12:34:32 PM PDT 24
Finished Apr 18 12:34:36 PM PDT 24
Peak memory 214616 kb
Host smart-bb216f81-4c0a-419d-87de-4cf167a439ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952574796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3952574796
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1923980516
Short name T396
Test name
Test status
Simulation time 53746024 ps
CPU time 3.71 seconds
Started Apr 18 12:34:26 PM PDT 24
Finished Apr 18 12:34:31 PM PDT 24
Peak memory 210392 kb
Host smart-646a4bef-8bdf-4e1d-8884-d67b95c96646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923980516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1923980516
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1039865702
Short name T365
Test name
Test status
Simulation time 156850971 ps
CPU time 3.12 seconds
Started Apr 18 12:34:18 PM PDT 24
Finished Apr 18 12:34:22 PM PDT 24
Peak memory 206732 kb
Host smart-0a47937d-a00f-4802-acfa-bf127f13daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039865702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1039865702
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1481059481
Short name T438
Test name
Test status
Simulation time 5735531935 ps
CPU time 33.14 seconds
Started Apr 18 12:34:26 PM PDT 24
Finished Apr 18 12:35:00 PM PDT 24
Peak memory 209208 kb
Host smart-27c12581-a077-4737-9991-b997aaf26387
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481059481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1481059481
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3439432845
Short name T280
Test name
Test status
Simulation time 257235736 ps
CPU time 3.5 seconds
Started Apr 18 12:34:23 PM PDT 24
Finished Apr 18 12:34:28 PM PDT 24
Peak memory 207112 kb
Host smart-0bc4cd82-d61d-4986-be0b-22ee85e6b0b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439432845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3439432845
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1149460610
Short name T642
Test name
Test status
Simulation time 870707618 ps
CPU time 3.82 seconds
Started Apr 18 12:34:26 PM PDT 24
Finished Apr 18 12:34:30 PM PDT 24
Peak memory 208088 kb
Host smart-bba4596e-4743-4d15-b6bc-82120c38124d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149460610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1149460610
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.67480065
Short name T420
Test name
Test status
Simulation time 45165853 ps
CPU time 2.11 seconds
Started Apr 18 12:34:27 PM PDT 24
Finished Apr 18 12:34:30 PM PDT 24
Peak memory 207912 kb
Host smart-f22e1793-ae83-491a-a9a3-60495a91cde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67480065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.67480065
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.729068121
Short name T506
Test name
Test status
Simulation time 424787268 ps
CPU time 10.17 seconds
Started Apr 18 12:34:24 PM PDT 24
Finished Apr 18 12:34:35 PM PDT 24
Peak memory 208080 kb
Host smart-1e6e8ae8-9982-49e2-8913-a7b9b41cfb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729068121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.729068121
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.422966935
Short name T253
Test name
Test status
Simulation time 2527108156 ps
CPU time 21.59 seconds
Started Apr 18 12:34:28 PM PDT 24
Finished Apr 18 12:34:50 PM PDT 24
Peak memory 216212 kb
Host smart-1b357fcd-389f-4224-a56d-e21c2501df7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422966935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.422966935
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3398031559
Short name T127
Test name
Test status
Simulation time 88223287 ps
CPU time 5.58 seconds
Started Apr 18 12:34:33 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 222904 kb
Host smart-23348d98-abea-4bc1-8e8b-668bc0f12b5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398031559 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3398031559
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2270420185
Short name T337
Test name
Test status
Simulation time 161404270 ps
CPU time 6.14 seconds
Started Apr 18 12:34:32 PM PDT 24
Finished Apr 18 12:34:39 PM PDT 24
Peak memory 214616 kb
Host smart-a88150c5-5730-4bd2-9e07-a8e5415f4008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270420185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2270420185
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2515675734
Short name T485
Test name
Test status
Simulation time 69336802 ps
CPU time 3.25 seconds
Started Apr 18 12:34:22 PM PDT 24
Finished Apr 18 12:34:26 PM PDT 24
Peak memory 210360 kb
Host smart-1bb53ad6-b8ed-46b0-9d68-168416232af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515675734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2515675734
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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