Summary for Variable op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
1 |
4 |
80.00 |
Automatically Generated Bins for op_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OpDisable] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[OpAdvance] |
43 |
1 |
|
|
T5 |
1 |
|
T40 |
1 |
|
T41 |
1 |
auto[OpGenId] |
12 |
1 |
|
|
T35 |
1 |
|
T203 |
1 |
|
T190 |
1 |
auto[OpGenSwOut] |
18 |
1 |
|
|
T44 |
1 |
|
T28 |
1 |
|
T49 |
1 |
auto[OpGenHwOut] |
12 |
1 |
|
|
T5 |
1 |
|
T11 |
1 |
|
T42 |
1 |
Summary for Variable state_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
7 |
0 |
7 |
100.00 |
Automatically Generated Bins for state_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
1808 |
1 |
|
|
T5 |
1 |
|
T6 |
90 |
|
T7 |
180 |
auto[StInit] |
79 |
1 |
|
|
T11 |
1 |
|
T44 |
1 |
|
T35 |
1 |
auto[StCreatorRootKey] |
55 |
1 |
|
|
T34 |
1 |
|
T36 |
1 |
|
T28 |
1 |
auto[StOwnerIntKey] |
42 |
1 |
|
|
T100 |
1 |
|
T31 |
1 |
|
T55 |
1 |
auto[StOwnerKey] |
35 |
1 |
|
|
T5 |
1 |
|
T18 |
1 |
|
T61 |
1 |
auto[StDisabled] |
399 |
1 |
|
|
T5 |
14 |
|
T98 |
3 |
|
T8 |
1 |
auto[StInvalid] |
47 |
1 |
|
|
T23 |
1 |
|
T39 |
1 |
|
T76 |
1 |
Summary for Variable wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wip_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3455 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
85 |
1 |
|
|
T5 |
2 |
|
T11 |
1 |
|
T44 |
1 |
Summary for Cross state_x_wip_cross
Samples crossed: state_cp wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
14 |
1 |
13 |
92.86 |
1 |
Automatically Generated Cross Bins for state_x_wip_cross
Uncovered bins
state_cp | wip_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
state_cp | wip_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[0] |
1804 |
1 |
|
|
T5 |
1 |
|
T6 |
90 |
|
T7 |
180 |
auto[StReset] |
auto[1] |
4 |
1 |
|
|
T45 |
1 |
|
T46 |
1 |
|
T204 |
1 |
auto[StInit] |
auto[0] |
39 |
1 |
|
|
T27 |
1 |
|
T19 |
1 |
|
T100 |
2 |
auto[StInit] |
auto[1] |
40 |
1 |
|
|
T11 |
1 |
|
T44 |
1 |
|
T35 |
1 |
auto[StCreatorRootKey] |
auto[0] |
42 |
1 |
|
|
T34 |
1 |
|
T36 |
1 |
|
T53 |
1 |
auto[StCreatorRootKey] |
auto[1] |
13 |
1 |
|
|
T28 |
1 |
|
T154 |
1 |
|
T55 |
1 |
auto[StOwnerIntKey] |
auto[0] |
30 |
1 |
|
|
T100 |
1 |
|
T57 |
1 |
|
T56 |
1 |
auto[StOwnerIntKey] |
auto[1] |
12 |
1 |
|
|
T31 |
1 |
|
T55 |
1 |
|
T73 |
1 |
auto[StOwnerKey] |
auto[0] |
28 |
1 |
|
|
T18 |
1 |
|
T61 |
1 |
|
T59 |
1 |
auto[StOwnerKey] |
auto[1] |
7 |
1 |
|
|
T5 |
1 |
|
T205 |
1 |
|
T206 |
1 |
auto[StDisabled] |
auto[0] |
390 |
1 |
|
|
T5 |
13 |
|
T98 |
3 |
|
T8 |
1 |
auto[StDisabled] |
auto[1] |
9 |
1 |
|
|
T5 |
1 |
|
T41 |
1 |
|
T207 |
1 |
auto[StInvalid] |
auto[0] |
47 |
1 |
|
|
T23 |
1 |
|
T39 |
1 |
|
T76 |
1 |
Summary for Cross state_x_op_cross
Samples crossed: state_cp op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
35 |
14 |
21 |
60.00 |
14 |
Automatically Generated Cross Bins for state_x_op_cross
Element holes
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
* |
-- |
-- |
5 |
|
Uncovered bins
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StReset]] |
[auto[OpGenId]] |
0 |
1 |
1 |
|
[auto[StReset]] |
[auto[OpGenHwOut] , auto[OpDisable]] |
-- |
-- |
2 |
|
[auto[StInit]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StCreatorRootKey]] |
[auto[OpGenHwOut] , auto[OpDisable]] |
-- |
-- |
2 |
|
[auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]] |
[auto[OpDisable]] |
-- |
-- |
3 |
|
Covered bins
state_cp | op_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[OpAdvance] |
3 |
1 |
|
|
T45 |
1 |
|
T46 |
1 |
|
T47 |
1 |
auto[StReset] |
auto[OpGenSwOut] |
1 |
1 |
|
|
T204 |
1 |
|
- |
- |
|
- |
- |
auto[StInit] |
auto[OpAdvance] |
19 |
1 |
|
|
T40 |
1 |
|
T208 |
1 |
|
T30 |
1 |
auto[StInit] |
auto[OpGenId] |
6 |
1 |
|
|
T35 |
1 |
|
T203 |
1 |
|
T209 |
1 |
auto[StInit] |
auto[OpGenSwOut] |
9 |
1 |
|
|
T44 |
1 |
|
T49 |
1 |
|
T210 |
2 |
auto[StInit] |
auto[OpGenHwOut] |
6 |
1 |
|
|
T11 |
1 |
|
T42 |
1 |
|
T9 |
1 |
auto[StCreatorRootKey] |
auto[OpAdvance] |
9 |
1 |
|
|
T154 |
1 |
|
T55 |
1 |
|
T211 |
1 |
auto[StCreatorRootKey] |
auto[OpGenId] |
2 |
1 |
|
|
T190 |
1 |
|
T212 |
1 |
|
- |
- |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T28 |
1 |
|
T213 |
1 |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpAdvance] |
6 |
1 |
|
|
T31 |
1 |
|
T73 |
1 |
|
T214 |
1 |
auto[StOwnerIntKey] |
auto[OpGenId] |
1 |
1 |
|
|
T215 |
1 |
|
- |
- |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T216 |
1 |
|
T217 |
1 |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
3 |
1 |
|
|
T55 |
1 |
|
T218 |
1 |
|
T219 |
1 |
auto[StOwnerKey] |
auto[OpAdvance] |
2 |
1 |
|
|
T5 |
1 |
|
T205 |
1 |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenId] |
2 |
1 |
|
|
T220 |
1 |
|
T75 |
1 |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T206 |
1 |
|
T221 |
1 |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenHwOut] |
1 |
1 |
|
|
T222 |
1 |
|
- |
- |
|
- |
- |
auto[StDisabled] |
auto[OpAdvance] |
4 |
1 |
|
|
T41 |
1 |
|
T205 |
1 |
|
T223 |
1 |
auto[StDisabled] |
auto[OpGenId] |
1 |
1 |
|
|
T215 |
1 |
|
- |
- |
|
- |
- |
auto[StDisabled] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T224 |
1 |
|
T225 |
1 |
|
- |
- |
auto[StDisabled] |
auto[OpGenHwOut] |
2 |
1 |
|
|
T5 |
1 |
|
T207 |
1 |
|
- |
- |