Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4601

1

T1

1

T2

17

T3

8

auto[1]

597

1

T1

1

T2

1

T5

5

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4601

1

T1

1

T2

17

T3

8

auto[1]

597

1

T1

1

T2

1

T5

5

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4626

1

T1

1

T2

14

T3

8

auto[1]

572

1

T1

1

T2

4

T4

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4626

1

T1

1

T2

14

T3

8

auto[1]

572

1

T1

1

T2

4

T4

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	418	1			T2	4		T4	2		T5	11
auto[OpGenId]	1086	1			T1	1		T2	6		T4	2
auto[OpGenSwOut]	1119	1			T2	6		T14	1		T15	1
auto[OpGenHwOut]	2509	1			T2	2		T3	8		T4	1
auto[OpDisable]	66	1			T1	1		T5	1		T50	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	418	1			T2	4		T4	2		T5	11
auto[OpGenId]	1086	1			T1	1		T2	6		T4	2
auto[OpGenSwOut]	1119	1			T2	6		T14	1		T15	1
auto[OpGenHwOut]	2509	1			T2	2		T3	8		T4	1
auto[OpDisable]	66	1			T1	1		T5	1		T50	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4665

1

T1

2

T2

18

T3

4

auto[1]

533

1

T3

4

T13

2

T5

6

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4665

1

T1

2

T2

18

T3

4

auto[1]

533

1

T3

4

T13

2

T5

6

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4875

1

T1

2

T2

9

T3

8

auto[1]

323

1

T2

9

T116

6

T117

6

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1804	1			T1	1		T2	2		T3	3
auto[1]	642	1			T3	1		T13	1		T15	1
auto[2]	667	1			T2	2		T3	1		T13	1
auto[3]	723	1			T1	1		T2	11		T4	1
auto[4]	366	1			T4	1		T13	2		T5	6
auto[5]	338	1			T2	3		T3	1		T15	1
auto[6]	365	1			T4	1		T13	2		T5	4
auto[7]	293	1			T3	2		T4	1		T13	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1362	1			T2	3		T3	3		T4	3
clear_one[1]	642	1			T3	1		T13	1		T15	1
clear_one[2]	667	1			T2	2		T3	1		T13	1
clear_one[3]	723	1			T1	1		T2	11		T4	1
clear_none	1804	1			T1	1		T2	2		T3	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	976	1			T2	3		T13	1		T15	2
auto[StInit]	755	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	541	1			T3	1		T13	1		T14	1
auto[StOwnerIntKey]	499	1			T2	3		T3	1		T13	1
auto[StOwnerKey]	464	1			T2	1		T3	1		T4	1
auto[StDisabled]	1781	1			T1	1		T2	10		T3	4
auto[StInvalid]	182	1			T23	4		T39	1		T76	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	976	1			T2	3		T13	1		T15	2
auto[StInit]	755	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	541	1			T3	1		T13	1		T14	1
auto[StOwnerIntKey]	499	1			T2	3		T3	1		T13	1
auto[StOwnerKey]	464	1			T2	1		T3	1		T4	1
auto[StDisabled]	1781	1			T1	1		T2	10		T3	4
auto[StInvalid]	182	1			T23	4		T39	1		T76	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StOwnerIntKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T226	1		T227	1		T228	1
auto[0]	auto[StReset]	auto[OpGenId]	158	1			T5	3		T11	1		T44	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	149	1			T2	2		T5	3		T81	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	252	1			T13	1		T15	1		T5	2
auto[0]	auto[StInit]	auto[OpAdvance]	41	1			T5	1		T76	1		T24	1
auto[0]	auto[StInit]	auto[OpGenId]	78	1			T1	1		T50	1		T192	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	108	1			T5	1		T98	1		T43	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	188	1			T3	1		T5	1		T200	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	24	1			T197	1		T140	1		T52	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	51	1			T5	2		T100	1		T133	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	35	1			T14	1		T152	2		T51	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	69	1			T229	1		T139	1		T152	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	17	1			T57	1		T210	1		T230	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	25	1			T98	1		T231	1		T232	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	28	1			T5	1		T43	1		T106	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	52	1			T3	1		T196	1		T77	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T4	1		T57	1		T213	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	26	1			T17	1		T59	1		T51	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T5	1		T136	1		T60	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	50	1			T80	1		T229	1		T79	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	30	1			T5	1		T142	1		T42	1
auto[0]	auto[StDisabled]	auto[OpGenId]	86	1			T5	2		T104	2		T100	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	64	1			T5	1		T192	1		T52	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T3	1		T5	1		T80	1
auto[0]	auto[StDisabled]	auto[OpDisable]	23	1			T50	1		T233	1		T52	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	6	1			T234	1		T235	1		T236	1
auto[0]	auto[StInvalid]	auto[OpGenId]	16	1			T39	1		T25	1		T99	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T23	1		T76	2		T99	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T237	1		T234	2		T195	1
auto[1]	auto[StReset]	auto[OpGenId]	20	1			T15	1		T11	1		T202	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	22	1			T59	1		T90	1		T213	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	53	1			T5	1		T80	1		T82	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T238	1		T213	1		T239	1
auto[1]	auto[StInit]	auto[OpGenId]	17	1			T24	1		T90	2		T240	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	20	1			T108	1		T41	2		T90	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	22	1			T82	1		T202	1		T139	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T238	1		T241	1		T242	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T124	1		T243	1		T244	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T81	1		T245	1		T246	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T77	1		T247	1		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T5	1		T45	1		T249	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T64	1		T45	1		T241	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T5	1		T45	1		T250	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T68	1		T251	1		T252	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T5	1		T241	1		T253	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	10	1			T248	1		T42	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T52	1		T241	1		T255	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T98	1		T106	1		T100	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	19	1			T152	1		T256	1		T241	1
auto[1]	auto[StDisabled]	auto[OpGenId]	39	1			T17	1		T104	1		T50	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T52	1		T42	1		T232	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T3	1		T13	1		T5	2
auto[1]	auto[StDisabled]	auto[OpDisable]	1	1			T5	1		-	-		-	-
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T99	1		T257	1		T235	1
auto[1]	auto[StInvalid]	auto[OpGenId]	8	1			T78	1		T258	1		T259	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T260	1		T236	1		T261	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T99	1		T237	1		T257	1
auto[2]	auto[StReset]	auto[OpGenId]	15	1			T78	1		T51	1		T115	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	15	1			T81	1		T108	1		T153	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	42	1			T5	1		T11	1		T82	1
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T27	1		T262	1		T263	1
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T52	1		T249	1		T264	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	15	1			T153	1		T45	1		T265	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	32	1			T5	1		T24	1		T266	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T5	1		T117	1		T267	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T268	1		T269	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T42	1		T57	1		T265	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T80	1		T79	1		T271	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T5	1		T137	1		T249	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T5	1		T100	1		T142	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T5	1		T117	1		T142	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T13	1		T79	1		T139	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T192	1		T133	1		T249	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	4	1			T262	1		T210	1		T272	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T5	1		T42	1		T205	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	49	1			T3	1		T5	1		T201	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	17	1			T137	1		T248	1		T242	1
auto[2]	auto[StDisabled]	auto[OpGenId]	58	1			T5	3		T117	1		T152	2
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T2	1		T108	1		T98	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	134	1			T2	1		T80	2		T229	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T41	1		T42	1		T245	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T273	1		T274	1		T275	1
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T25	1		T78	1		T276	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T23	2		T76	1		T277	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T25	1		T99	2		T235	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T278	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	16	1			T2	1		T5	1		T89	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	22	1			T22	1		T116	1		T78	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	47	1			T82	1		T105	1		T116	1
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T2	1		T90	1		T279	1
auto[3]	auto[StInit]	auto[OpGenId]	20	1			T100	1		T89	1		T280	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	15	1			T89	1		T281	1		T264	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	28	1			T80	1		T22	1		T105	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T5	1		T116	1		T282	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	21	1			T116	1		T153	1		T42	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T5	1		T68	1		T213	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T103	1		T283	1		T284	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T2	1		T116	2		T285	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T2	2		T197	1		T153	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T116	1		T42	1		T57	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T82	1		T229	1		T134	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T116	1		T272	1		T286	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T117	4		T287	1		T71	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T98	1		T45	1		T71	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T2	1		T200	1		T77	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	22	1			T2	2		T83	1		T41	1
auto[3]	auto[StDisabled]	auto[OpGenId]	44	1			T4	1		T22	1		T48	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	72	1			T2	3		T116	1		T117	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	147	1			T13	1		T80	1		T82	1
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T1	1		T68	1		T254	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T237	1		T258	1		T276	1
auto[3]	auto[StInvalid]	auto[OpGenId]	5	1			T288	1		T260	1		T289	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T276	1		T273	1		T290	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T273	1		T291	1		T289	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T48	1		T86	1		T292	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	15	1			T5	1		T54	1		T71	2
auto[4]	auto[StReset]	auto[OpGenHwOut]	27	1			T139	1		T100	1		T293	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T168	1		T294	1		T295	1
auto[4]	auto[StInit]	auto[OpGenId]	12	1			T24	1		T254	1		T264	2
auto[4]	auto[StInit]	auto[OpGenSwOut]	11	1			T24	1		T90	1		T94	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	15	1			T201	1		T89	1		T52	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T296	1		T255	2		T297	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T51	1		T226	2		T298	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T299	1		T205	1		T300	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T13	1		T5	1		T105	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T301	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T255	1		T189	1		T302	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T226	1		T303	1		T216	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T5	1		T105	1		T138	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T228	1		T304	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T45	1		T305	1		T73	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T306	1		T307	1		T308	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T5	1		T105	1		T284	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	17	1			T5	1		T309	1		T189	1
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T4	1		T17	1		T196	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T5	1		T64	1		T280	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T13	1		T17	1		T22	1
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T310	1		T311	1		T73	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T257	1		T312	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	2	1			T291	1		T236	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T25	1		T313	1		T275	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T195	1		T288	1		T257	1
auto[5]	auto[StReset]	auto[OpGenId]	13	1			T35	1		T98	1		T67	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	6	1			T71	1		T125	1		T314	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	24	1			T79	1		T59	1		T315	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T205	1		T88	1		T316	1
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T59	1		T189	1		T190	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T98	1		T292	1		T88	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T42	1		T317	1		T55	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T5	1		T225	1		T92	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T137	1		T318	1		T319	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T15	1		T280	1		T320	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T3	1		T200	1		T131	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T254	1		T311	1		T71	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T321	1		T322	1		T323	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T81	1		T240	1		T324	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T142	2		T325	1		T326	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T142	2		T269	1		T205	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T5	1		T193	1		T302	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T103	1		T131	1		T271	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	17	1			T5	2		T136	1		T52	1
auto[5]	auto[StDisabled]	auto[OpGenId]	23	1			T2	3		T98	1		T327	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	16	1			T98	1		T42	1		T45	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T200	2		T43	1		T116	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T328	1		T73	1		T214	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T329	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T237	1		T274	1		T330	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T277	1		T257	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T331	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T11	1		T35	1		T27	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T24	1		T238	1		T332	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	14	1			T105	1		T279	1		T333	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T281	1		T334	1		T335	1
auto[6]	auto[StInit]	auto[OpGenId]	8	1			T42	2		T88	1		T334	2
auto[6]	auto[StInit]	auto[OpGenSwOut]	11	1			T26	1		T90	1		T264	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	15	1			T13	1		T132	1		T115	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T22	1		T52	1		T223	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T45	1		T55	1		T74	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T50	1		T254	1		T336	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T82	1		T201	1		T337	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T152	1		T238	1		T338	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T339	1		T267	1		T340	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T242	1		T341	1		T92	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T80	1		T200	1		T342	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T152	1		T75	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T152	1		T343	1		T344	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T57	1		T188	1		T345	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T129	1		T134	1		T346	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	11	1			T133	1		T71	1		T345	1
auto[6]	auto[StDisabled]	auto[OpGenId]	29	1			T5	2		T81	1		T64	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T5	2		T152	2		T153	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	91	1			T4	1		T13	1		T108	1
auto[6]	auto[StDisabled]	auto[OpDisable]	7	1			T51	1		T42	1		T347	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T78	1		T348	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T76	1		T86	1		T195	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T235	1		T349	1		T236	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T23	1		T235	1		T260	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T52	1		T58	1		T350	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	10	1			T83	2		T351	1		T297	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	15	1			T5	1		T337	1		T352	1
auto[7]	auto[StInit]	auto[OpAdvance]	6	1			T88	1		T353	1		T354	1
auto[7]	auto[StInit]	auto[OpGenId]	13	1			T292	1		T57	1		T230	3
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T355	1		T356	1		T168	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	8	1			T77	1		T48	1		T320	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T64	1		T357	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T65	1		T75	1		T358	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T359	2		T75	1		T185	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T132	1		T134	1		T315	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T299	1		T188	2		T189	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T243	1		T357	1		T360	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T320	1		T269	1		T361	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T103	1		T201	1		T132	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T299	1		T217	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T256	1		T299	1		T243	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T189	1		T362	1		T363	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T13	1		T82	1		T293	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	9	1			T4	1		T230	1		T244	1
auto[7]	auto[StDisabled]	auto[OpGenId]	23	1			T197	1		T64	1		T238	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T5	1		T98	1		T192	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	57	1			T3	2		T82	1		T201	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T269	1		T203	1		T364	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T235	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T365	1		T275	1		T329	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T25	1		T288	1		T289	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T195	1		T273	1		T366	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1362

1

T2

3

T3

3

T4

3

clear_one[1]

auto[0]

auto[0]

auto[0]

386

1

T15

1

T5

3

T17

1

clear_one[1]

auto[0]

auto[0]

auto[1]

114

1

T3

1

T13

1

T5

1

clear_one[1]

auto[0]

auto[1]

auto[0]

101

1

T5

2

T200

1

T106

2

clear_one[1]

auto[0]

auto[1]

auto[1]

41

1

T5

1

T41

1

T248

1

clear_one[2]

auto[0]

auto[0]

auto[0]

407

1

T2

1

T5

10

T11

1

clear_one[2]

auto[0]

auto[0]

auto[1]

93

1

T3

1

T13

1

T108

1

clear_one[2]

auto[1]

auto[0]

auto[0]

136

1

T2

1

T5

1

T80

3

clear_one[2]

auto[1]

auto[0]

auto[1]

31

1

T136

1

T199

1

T367

1

clear_one[3]

auto[0]

auto[0]

auto[0]

430

1

T2

7

T13

1

T5

3

clear_one[3]

auto[0]

auto[1]

auto[0]

124

1

T2

4

T4

1

T98

1

clear_one[3]

auto[1]

auto[0]

auto[0]

116

1

T80

1

T103

1

T77

1

clear_one[3]

auto[1]

auto[1]

auto[0]

53

1

T1

1

T106

1

T117

1

clear_none

auto[0]

auto[0]

auto[0]

1242

1

T1

1

T2

2

T3

1

clear_none

auto[0]

auto[0]

auto[1]

129

1

T3

2

T5

1

T196

1

clear_none

auto[0]

auto[1]

auto[0]

143

1

T14

1

T5

1

T200

1

clear_none

auto[0]

auto[1]

auto[1]

29

1

T5

1

T52

1

T42

1

clear_none

auto[1]

auto[0]

auto[0]

126

1

T5

2

T80

2

T196

1

clear_none

auto[1]

auto[0]

auto[1]

54

1

T5

1

T60

1

T52

1

clear_none

auto[1]

auto[1]

auto[0]

39

1

T17

1

T100

1

T41

1

clear_none

auto[1]

auto[1]

auto[1]

42

1

T5

1

T136

1

T52

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1282	1			T2	1		T3	3		T4	3
clear_all	auto[1]	80	1			T2	2		T152	5		T238	2
clear_one[1]	auto[0]	604	1			T3	1		T13	1		T15	1
clear_one[1]	auto[1]	38	1			T116	1		T238	2		T256	3
clear_one[2]	auto[0]	625	1			T2	1		T3	1		T13	1
clear_one[2]	auto[1]	42	1			T2	1		T117	2		T152	3
clear_one[3]	auto[0]	658	1			T1	1		T2	5		T4	1
clear_one[3]	auto[1]	65	1			T2	6		T116	5		T117	4
clear_none	auto[0]	1706	1			T1	1		T2	2		T3	3
clear_none	auto[1]	98	1			T152	2		T199	2		T142	2