Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10944

1

T1

5

T2

20

T3

2

auto[Attestation]

8156

1

T1

7

T2

18

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2813	1			T1	1		T2	3		T4	4
auto[Aes]	3469	1			T1	4		T2	7		T4	2
auto[Kmac]	3473	1			T1	2		T2	8		T4	2
auto[Otbn]	3419	1			T1	2		T2	2		T3	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7748	1			T1	3		T2	8		T3	8
auto[OpGenId]	5926	1			T1	3		T2	18		T4	5
auto[OpGenSwOut]	6126	1			T1	6		T2	13		T4	6
auto[OpGenHwOut]	7048	1			T1	3		T2	7		T3	8
auto[OpDisable]	123	1			T1	1		T5	2		T43	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10165

1

T1

10

T2

18

T3

8

auto[OpDoneFail]

16806

1

T1

6

T2

28

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5963	1			T1	1		T2	12		T3	1
auto[StInit]	4348	1			T1	4		T2	2		T3	2
auto[StCreatorRootKey]	3069	1			T1	4		T2	6		T3	2
auto[StOwnerIntKey]	2662	1			T1	4		T2	5		T3	2
auto[StOwnerKey]	2344	1			T2	5		T3	2		T4	1
auto[StDisabled]	7475	1			T1	3		T2	16		T3	7
auto[StInvalid]	1110	1			T23	26		T39	20		T76	25

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	293	1			T5	2		T81	2		T44	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T4	1		T22	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T1	1		T5	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	79	1			T4	1		T5	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	60	1			T5	2		T106	1		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	201	1			T2	1		T5	2		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	27	1			T78	1		T86	1		T99	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	315	1			T2	2		T5	5		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	130	1			T5	1		T16	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	69	1			T5	2		T192	1		T8	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	60	1			T2	1		T5	2		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	51	1			T5	3		T100	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	204	1			T5	5		T98	2		T194	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	33	1			T39	1		T25	2		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	279	1			T2	2		T5	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	128	1			T5	1		T17	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T81	1		T104	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T5	1		T106	1		T117	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	44	1			T5	3		T81	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	218	1			T1	1		T4	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	31	1			T76	1		T25	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	298	1			T2	1		T5	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T4	1		T5	3		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	89	1			T5	1		T107	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T197	1		T194	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	48	1			T22	1		T61	2		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	227	1			T4	1		T5	7		T107	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	41	1			T23	1		T76	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	83	1			T5	2		T51	5		T41	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	127	1			T4	1		T196	2		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	98	1			T2	1		T14	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T5	3		T61	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T5	2		T100	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	206	1			T5	4		T16	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T76	1		T78	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	89	1			T5	4		T100	2		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	135	1			T1	1		T107	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	94	1			T5	4		T34	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	72	1			T1	2		T5	2		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	73	1			T2	1		T5	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	207	1			T2	1		T5	4		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T39	1		T25	3		T86	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	92	1			T5	5		T100	1		T51	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	129	1			T14	1		T5	4		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T15	1		T5	2		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T5	2		T98	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	47	1			T5	1		T22	1		T152	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	203	1			T2	2		T5	5		T98	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	31	1			T23	2		T39	1		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	67	1			T5	3		T98	2		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	140	1			T5	2		T98	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	63	1			T2	1		T28	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T16	1		T17	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T198	1		T52	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	212	1			T1	1		T5	5		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	39	1			T23	2		T76	1		T86	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	233	1			T15	1		T5	2		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T5	3		T18	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	59	1			T199	1		T42	2		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	56	1			T68	1		T59	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	64	1			T5	1		T18	1		T136	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	174	1			T5	7		T197	2		T104	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	31	1			T39	2		T76	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	419	1			T2	1		T5	4		T80	6
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	134	1			T5	1		T80	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T1	1		T14	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	98	1			T15	1		T5	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T5	1		T17	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	254	1			T2	1		T5	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	37	1			T39	1		T76	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	448	1			T2	1		T15	2		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	147	1			T5	2		T22	2		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T14	1		T34	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	85	1			T5	1		T17	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	73	1			T2	1		T5	3		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	266	1			T5	4		T200	1		T104	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	34	1			T76	2		T25	1		T99	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	458	1			T13	2		T5	3		T82	13
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T82	1		T22	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T5	2		T105	1		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	84	1			T13	1		T15	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T13	1		T5	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	241	1			T3	2		T13	3		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	28	1			T76	2		T25	2		T78	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	55	1			T100	1		T51	2		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	109	1			T5	1		T35	1		T202	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T5	2		T117	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T4	1		T5	2		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T2	1		T98	1		T117	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	177	1			T5	1		T17	2		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T23	1		T76	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	64	1			T5	1		T98	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	143	1			T4	1		T5	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	98	1			T80	1		T103	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	95	1			T5	2		T18	1		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	84	1			T5	1		T18	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	263	1			T4	1		T5	4		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	44	1			T23	4		T39	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	58	1			T5	1		T51	1		T41	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	136	1			T5	1		T22	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T1	1		T2	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	109	1			T5	2		T98	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	102	1			T5	1		T200	1		T117	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	255	1			T4	1		T5	5		T200	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	36	1			T23	1		T39	1		T76	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T5	1		T100	2		T41	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	128	1			T3	1		T13	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	121	1			T3	1		T13	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T3	1		T5	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	75	1			T3	1		T5	2		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	259	1			T1	1		T3	2		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	36	1			T23	1		T39	2		T25	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	199	1			T1	1		T4	1		T5	5
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	647	1			T2	1		T4	1		T5	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	166	1			T2	1		T5	7		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	696	1			T2	2		T5	11		T16	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	188	1			T5	3		T81	2		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	669	1			T1	1		T2	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T5	1		T107	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	696	1			T2	1		T4	2		T5	12
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	219	1			T2	1		T14	1		T5	6
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	466	1			T4	1		T5	6		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	224	1			T1	2		T2	1		T5	7
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	476	1			T1	1		T2	1		T5	8
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T15	1		T5	5		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	471	1			T2	2		T14	1		T5	14
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	166	1			T2	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	475	1			T1	1		T5	10		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	170	1			T5	1		T18	1		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	551	1			T15	1		T5	12		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	263	1			T1	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	853	1			T2	2		T5	6		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	259	1			T2	1		T14	1		T5	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	913	1			T2	1		T15	2		T5	8
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	256	1			T13	2		T15	1		T5	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	863	1			T3	2		T13	5		T5	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	169	1			T2	1		T5	4		T98	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	392	1			T4	1		T5	2		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	267	1			T5	3		T80	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	524	1			T4	2		T5	6		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	302	1			T1	1		T2	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	496	1			T4	1		T5	8		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	270	1			T3	3		T13	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	500	1			T1	1		T3	3		T4	1