Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2890

1

T1

2

T2

4

T4

6

auto[1]

306

1

T2

12

T116

4

T117

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T4	1		T5	2		T202	1
auto[134217728:268435455]	90	1			T5	2		T22	1		T35	1
auto[268435456:402653183]	91	1			T2	1		T5	3		T197	1
auto[402653184:536870911]	105	1			T17	1		T202	1		T104	1
auto[536870912:671088639]	96	1			T44	1		T43	1		T24	1
auto[671088640:805306367]	97	1			T2	1		T5	2		T11	1
auto[805306368:939524095]	84	1			T5	1		T117	1		T67	1
auto[939524096:1073741823]	106	1			T2	2		T196	1		T116	1
auto[1073741824:1207959551]	101	1			T1	1		T15	1		T44	1
auto[1207959552:1342177279]	100	1			T2	2		T5	1		T202	1
auto[1342177280:1476395007]	103	1			T1	1		T2	1		T5	1
auto[1476395008:1610612735]	103	1			T5	1		T39	1		T116	1
auto[1610612736:1744830463]	101	1			T78	1		T26	1		T136	1
auto[1744830464:1879048191]	104	1			T5	3		T22	1		T25	1
auto[1879048192:2013265919]	105	1			T5	1		T17	1		T202	1
auto[2013265920:2147483647]	102	1			T2	1		T4	1		T76	1
auto[2147483648:2281701375]	110	1			T2	1		T17	1		T11	1
auto[2281701376:2415919103]	98	1			T15	1		T5	1		T44	1
auto[2415919104:2550136831]	91	1			T15	1		T5	4		T116	1
auto[2550136832:2684354559]	102	1			T2	1		T15	1		T5	3
auto[2684354560:2818572287]	82	1			T2	1		T5	2		T117	1
auto[2818572288:2952790015]	118	1			T2	2		T4	1		T5	2
auto[2952790016:3087007743]	105	1			T23	1		T76	2		T26	1
auto[3087007744:3221225471]	98	1			T5	2		T197	1		T48	1
auto[3221225472:3355443199]	102	1			T2	1		T5	1		T196	1
auto[3355443200:3489660927]	95	1			T4	1		T5	2		T28	1
auto[3489660928:3623878655]	104	1			T202	1		T78	1		T26	1
auto[3623878656:3758096383]	99	1			T4	1		T5	1		T22	2
auto[3758096384:3892314111]	114	1			T2	1		T4	1		T5	3
auto[3892314112:4026531839]	94	1			T5	3		T17	1		T43	1
auto[4026531840:4160749567]	87	1			T5	1		T23	1		T116	1
auto[4160749568:4294967295]	100	1			T2	1		T5	1		T78	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	100	1			T4	1		T5	2		T202	1
auto[0:134217727]	auto[1]	9	1			T144	1		T241	1		T230	1
auto[134217728:268435455]	auto[0]	86	1			T5	2		T22	1		T35	1
auto[134217728:268435455]	auto[1]	4	1			T249	1		T299	1		T263	1
auto[268435456:402653183]	auto[0]	78	1			T5	3		T197	1		T25	1
auto[268435456:402653183]	auto[1]	13	1			T2	1		T116	1		T152	1
auto[402653184:536870911]	auto[0]	92	1			T17	1		T202	1		T104	1
auto[402653184:536870911]	auto[1]	13	1			T116	1		T262	1		T144	1
auto[536870912:671088639]	auto[0]	89	1			T44	1		T43	1		T24	1
auto[536870912:671088639]	auto[1]	7	1			T238	1		T144	1		T278	1
auto[671088640:805306367]	auto[0]	87	1			T5	2		T11	1		T44	1
auto[671088640:805306367]	auto[1]	10	1			T2	1		T153	1		T255	1
auto[805306368:939524095]	auto[0]	77	1			T5	1		T67	1		T152	1
auto[805306368:939524095]	auto[1]	7	1			T117	1		T230	1		T384	1
auto[939524096:1073741823]	auto[0]	98	1			T196	1		T116	1		T25	1
auto[939524096:1073741823]	auto[1]	8	1			T2	2		T241	1		T375	1
auto[1073741824:1207959551]	auto[0]	90	1			T1	1		T15	1		T44	1
auto[1073741824:1207959551]	auto[1]	11	1			T153	1		T262	1		T226	2
auto[1207959552:1342177279]	auto[0]	88	1			T5	1		T202	1		T104	1
auto[1207959552:1342177279]	auto[1]	12	1			T2	2		T152	2		T256	1
auto[1342177280:1476395007]	auto[0]	94	1			T1	1		T5	1		T196	1
auto[1342177280:1476395007]	auto[1]	9	1			T2	1		T142	1		T285	1
auto[1476395008:1610612735]	auto[0]	94	1			T5	1		T39	1		T116	1
auto[1476395008:1610612735]	auto[1]	9	1			T249	1		T265	1		T392	1
auto[1610612736:1744830463]	auto[0]	94	1			T78	1		T26	1		T136	1
auto[1610612736:1744830463]	auto[1]	7	1			T142	1		T230	1		T263	1
auto[1744830464:1879048191]	auto[0]	93	1			T5	3		T22	1		T25	1
auto[1744830464:1879048191]	auto[1]	11	1			T117	1		T152	1		T238	1
auto[1879048192:2013265919]	auto[0]	96	1			T5	1		T17	1		T202	1
auto[1879048192:2013265919]	auto[1]	9	1			T238	1		T375	1		T255	2
auto[2013265920:2147483647]	auto[0]	89	1			T4	1		T76	1		T78	1
auto[2013265920:2147483647]	auto[1]	13	1			T2	1		T262	1		T299	1
auto[2147483648:2281701375]	auto[0]	100	1			T2	1		T17	1		T11	1
auto[2147483648:2281701375]	auto[1]	10	1			T238	1		T314	1		T357	1
auto[2281701376:2415919103]	auto[0]	92	1			T15	1		T5	1		T44	1
auto[2281701376:2415919103]	auto[1]	6	1			T144	2		T265	1		T230	1
auto[2415919104:2550136831]	auto[0]	88	1			T15	1		T5	4		T116	1
auto[2415919104:2550136831]	auto[1]	3	1			T262	1		T255	1		T282	1
auto[2550136832:2684354559]	auto[0]	94	1			T15	1		T5	3		T86	1
auto[2550136832:2684354559]	auto[1]	8	1			T2	1		T309	1		T384	1
auto[2684354560:2818572287]	auto[0]	79	1			T5	2		T117	1		T136	1
auto[2684354560:2818572287]	auto[1]	3	1			T2	1		T357	1		T325	1
auto[2818572288:2952790015]	auto[0]	101	1			T2	2		T4	1		T5	2
auto[2818572288:2952790015]	auto[1]	17	1			T117	1		T153	1		T230	1
auto[2952790016:3087007743]	auto[0]	93	1			T23	1		T76	2		T26	1
auto[2952790016:3087007743]	auto[1]	12	1			T144	2		T256	2		T249	1
auto[3087007744:3221225471]	auto[0]	86	1			T5	2		T197	1		T48	1
auto[3087007744:3221225471]	auto[1]	12	1			T241	1		T255	1		T230	1
auto[3221225472:3355443199]	auto[0]	90	1			T5	1		T196	1		T23	1
auto[3221225472:3355443199]	auto[1]	12	1			T2	1		T199	1		T262	1
auto[3355443200:3489660927]	auto[0]	89	1			T4	1		T5	2		T28	1
auto[3355443200:3489660927]	auto[1]	6	1			T249	1		T226	1		T314	1
auto[3489660928:3623878655]	auto[0]	93	1			T202	1		T78	1		T26	1
auto[3489660928:3623878655]	auto[1]	11	1			T142	1		T262	1		T144	2
auto[3623878656:3758096383]	auto[0]	85	1			T4	1		T5	1		T22	2
auto[3623878656:3758096383]	auto[1]	14	1			T117	1		T152	1		T142	1
auto[3758096384:3892314111]	auto[0]	104	1			T4	1		T5	3		T22	1
auto[3758096384:3892314111]	auto[1]	10	1			T2	1		T116	1		T241	1
auto[3892314112:4026531839]	auto[0]	85	1			T5	3		T17	1		T43	1
auto[3892314112:4026531839]	auto[1]	9	1			T238	1		T144	1		T241	1
auto[4026531840:4160749567]	auto[0]	75	1			T5	1		T23	1		T40	1
auto[4026531840:4160749567]	auto[1]	12	1			T116	1		T152	1		T142	1
auto[4160749568:4294967295]	auto[0]	91	1			T2	1		T5	1		T78	1
auto[4160749568:4294967295]	auto[1]	9	1			T238	1		T262	1		T256	1