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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2891 1 T1 2 T2 4 T4 6
auto[1] 349 1 T2 8 T116 2 T117 4


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 76 1 T2 1 T26 2 T117 1
auto[134217728:268435455] 111 1 T4 1 T5 1 T116 1
auto[268435456:402653183] 118 1 T5 2 T104 1 T48 1
auto[402653184:536870911] 93 1 T4 1 T15 1 T5 1
auto[536870912:671088639] 89 1 T2 1 T4 1 T5 2
auto[671088640:805306367] 109 1 T5 2 T11 1 T67 1
auto[805306368:939524095] 104 1 T5 1 T22 1 T35 1
auto[939524096:1073741823] 112 1 T15 1 T5 2 T17 1
auto[1073741824:1207959551] 111 1 T5 2 T197 1 T23 1
auto[1207959552:1342177279] 122 1 T5 1 T22 1 T35 1
auto[1342177280:1476395007] 116 1 T2 2 T4 1 T197 1
auto[1476395008:1610612735] 93 1 T5 2 T23 1 T24 1
auto[1610612736:1744830463] 104 1 T2 1 T5 3 T116 1
auto[1744830464:1879048191] 72 1 T17 1 T202 1 T192 1
auto[1879048192:2013265919] 102 1 T1 1 T2 2 T5 4
auto[2013265920:2147483647] 71 1 T5 1 T11 1 T196 1
auto[2147483648:2281701375] 102 1 T5 1 T202 1 T43 1
auto[2281701376:2415919103] 94 1 T2 1 T5 2 T44 1
auto[2415919104:2550136831] 119 1 T15 1 T202 1 T104 1
auto[2550136832:2684354559] 110 1 T5 1 T196 1 T197 1
auto[2684354560:2818572287] 111 1 T2 1 T5 1 T196 1
auto[2818572288:2952790015] 106 1 T2 1 T4 1 T15 1
auto[2952790016:3087007743] 105 1 T5 2 T104 1 T86 1
auto[3087007744:3221225471] 111 1 T5 1 T17 1 T22 1
auto[3221225472:3355443199] 94 1 T5 1 T48 1 T78 1
auto[3355443200:3489660927] 106 1 T5 2 T116 1 T25 1
auto[3489660928:3623878655] 92 1 T5 2 T78 1 T8 1
auto[3623878656:3758096383] 87 1 T192 1 T86 1 T117 1
auto[3758096384:3892314111] 106 1 T5 3 T196 1 T76 1
auto[3892314112:4026531839] 91 1 T1 1 T2 1 T4 1
auto[4026531840:4160749567] 107 1 T5 1 T116 1 T76 1
auto[4160749568:4294967295] 96 1 T2 1 T43 1 T106 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 70 1 T26 2 T117 1 T51 1
auto[0:134217727] auto[1] 6 1 T2 1 T263 1 T397 1
auto[134217728:268435455] auto[0] 97 1 T4 1 T5 1 T116 1
auto[134217728:268435455] auto[1] 14 1 T142 2 T262 1 T144 1
auto[268435456:402653183] auto[0] 110 1 T5 2 T104 1 T48 1
auto[268435456:402653183] auto[1] 8 1 T299 1 T230 1 T309 1
auto[402653184:536870911] auto[0] 80 1 T4 1 T15 1 T5 1
auto[402653184:536870911] auto[1] 13 1 T152 3 T262 1 T144 1
auto[536870912:671088639] auto[0] 82 1 T2 1 T4 1 T5 2
auto[536870912:671088639] auto[1] 7 1 T152 1 T230 1 T226 1
auto[671088640:805306367] auto[0] 100 1 T5 2 T11 1 T67 1
auto[671088640:805306367] auto[1] 9 1 T144 1 T256 1 T230 1
auto[805306368:939524095] auto[0] 94 1 T5 1 T22 1 T35 1
auto[805306368:939524095] auto[1] 10 1 T238 1 T144 1 T374 1
auto[939524096:1073741823] auto[0] 96 1 T15 1 T5 2 T17 1
auto[939524096:1073741823] auto[1] 16 1 T152 1 T238 1 T142 1
auto[1073741824:1207959551] auto[0] 103 1 T5 2 T197 1 T23 1
auto[1073741824:1207959551] auto[1] 8 1 T117 1 T152 1 T256 1
auto[1207959552:1342177279] auto[0] 104 1 T5 1 T22 1 T35 1
auto[1207959552:1342177279] auto[1] 18 1 T238 1 T144 1 T256 1
auto[1342177280:1476395007] auto[0] 102 1 T4 1 T197 1 T106 1
auto[1342177280:1476395007] auto[1] 14 1 T2 2 T199 1 T238 1
auto[1476395008:1610612735] auto[0] 85 1 T5 2 T23 1 T24 1
auto[1476395008:1610612735] auto[1] 8 1 T142 1 T249 1 T226 1
auto[1610612736:1744830463] auto[0] 94 1 T5 3 T116 1 T78 1
auto[1610612736:1744830463] auto[1] 10 1 T2 1 T117 1 T255 1
auto[1744830464:1879048191] auto[0] 66 1 T17 1 T202 1 T192 1
auto[1744830464:1879048191] auto[1] 6 1 T152 1 T230 1 T253 1
auto[1879048192:2013265919] auto[0] 91 1 T1 1 T5 4 T17 1
auto[1879048192:2013265919] auto[1] 11 1 T2 2 T153 1 T256 1
auto[2013265920:2147483647] auto[0] 61 1 T5 1 T11 1 T196 1
auto[2013265920:2147483647] auto[1] 10 1 T153 1 T238 1 T256 1
auto[2147483648:2281701375] auto[0] 95 1 T5 1 T202 1 T43 1
auto[2147483648:2281701375] auto[1] 7 1 T249 1 T230 1 T226 1
auto[2281701376:2415919103] auto[0] 83 1 T2 1 T5 2 T44 1
auto[2281701376:2415919103] auto[1] 11 1 T152 1 T238 1 T241 1
auto[2415919104:2550136831] auto[0] 107 1 T15 1 T202 1 T104 1
auto[2415919104:2550136831] auto[1] 12 1 T152 1 T256 1 T241 1
auto[2550136832:2684354559] auto[0] 96 1 T5 1 T196 1 T197 1
auto[2550136832:2684354559] auto[1] 14 1 T152 1 T199 1 T256 1
auto[2684354560:2818572287] auto[0] 104 1 T2 1 T5 1 T196 1
auto[2684354560:2818572287] auto[1] 7 1 T153 1 T374 1 T392 1
auto[2818572288:2952790015] auto[0] 93 1 T4 1 T15 1 T5 1
auto[2818572288:2952790015] auto[1] 13 1 T2 1 T152 1 T238 1
auto[2952790016:3087007743] auto[0] 95 1 T5 2 T104 1 T86 1
auto[2952790016:3087007743] auto[1] 10 1 T144 2 T226 1 T278 1
auto[3087007744:3221225471] auto[0] 96 1 T5 1 T17 1 T22 1
auto[3087007744:3221225471] auto[1] 15 1 T238 3 T241 1 T226 2
auto[3221225472:3355443199] auto[0] 79 1 T5 1 T48 1 T78 1
auto[3221225472:3355443199] auto[1] 15 1 T117 1 T262 1 T249 2
auto[3355443200:3489660927] auto[0] 98 1 T5 2 T25 1 T64 1
auto[3355443200:3489660927] auto[1] 8 1 T116 1 T357 2 T278 1
auto[3489660928:3623878655] auto[0] 83 1 T5 2 T78 1 T8 1
auto[3489660928:3623878655] auto[1] 9 1 T152 1 T255 1 T226 1
auto[3623878656:3758096383] auto[0] 80 1 T192 1 T86 1 T117 1
auto[3623878656:3758096383] auto[1] 7 1 T238 1 T255 1 T226 1
auto[3758096384:3892314111] auto[0] 88 1 T5 3 T196 1 T76 1
auto[3758096384:3892314111] auto[1] 18 1 T152 1 T238 2 T249 1
auto[3892314112:4026531839] auto[0] 83 1 T1 1 T4 1 T5 1
auto[3892314112:4026531839] auto[1] 8 1 T2 1 T117 1 T262 1
auto[4026531840:4160749567] auto[0] 95 1 T5 1 T76 1 T25 1
auto[4026531840:4160749567] auto[1] 12 1 T116 1 T238 1 T262 2
auto[4160749568:4294967295] auto[0] 81 1 T2 1 T43 1 T106 1
auto[4160749568:4294967295] auto[1] 15 1 T238 1 T262 1 T256 1

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