Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.82 99.07 98.06 98.34 100.00 99.19 98.41 91.63


Total test records in report: 1075
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T1006 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4240450598 Apr 21 12:19:04 PM PDT 24 Apr 21 12:19:07 PM PDT 24 137870034 ps
T1007 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.901438774 Apr 21 12:23:52 PM PDT 24 Apr 21 12:23:56 PM PDT 24 560127786 ps
T163 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2528697238 Apr 21 12:21:36 PM PDT 24 Apr 21 12:22:13 PM PDT 24 1404544411 ps
T1008 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.82719691 Apr 21 12:19:00 PM PDT 24 Apr 21 12:19:02 PM PDT 24 28386111 ps
T177 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4038930964 Apr 21 12:22:52 PM PDT 24 Apr 21 12:23:13 PM PDT 24 1279278982 ps
T1009 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2626596427 Apr 21 12:22:49 PM PDT 24 Apr 21 12:22:52 PM PDT 24 61512375 ps
T1010 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.774580317 Apr 21 12:22:35 PM PDT 24 Apr 21 12:22:38 PM PDT 24 16600654 ps
T1011 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1249789550 Apr 21 12:22:54 PM PDT 24 Apr 21 12:23:09 PM PDT 24 385505902 ps
T1012 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4268648588 Apr 21 12:23:47 PM PDT 24 Apr 21 12:23:51 PM PDT 24 90370877 ps
T1013 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1569610996 Apr 21 12:24:08 PM PDT 24 Apr 21 12:24:10 PM PDT 24 56142302 ps
T1014 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1747129279 Apr 21 12:18:11 PM PDT 24 Apr 21 12:18:12 PM PDT 24 27686111 ps
T1015 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3268708557 Apr 21 12:21:17 PM PDT 24 Apr 21 12:21:19 PM PDT 24 22748902 ps
T1016 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3690753051 Apr 21 12:22:51 PM PDT 24 Apr 21 12:22:53 PM PDT 24 44790753 ps
T1017 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.178607750 Apr 21 12:21:02 PM PDT 24 Apr 21 12:21:08 PM PDT 24 576303487 ps
T1018 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1113245413 Apr 21 12:22:36 PM PDT 24 Apr 21 12:22:38 PM PDT 24 94740323 ps
T1019 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.365623302 Apr 21 12:22:52 PM PDT 24 Apr 21 12:23:02 PM PDT 24 551859668 ps
T1020 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.203872773 Apr 21 12:22:03 PM PDT 24 Apr 21 12:22:04 PM PDT 24 51440351 ps
T1021 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3210385639 Apr 21 12:23:01 PM PDT 24 Apr 21 12:23:03 PM PDT 24 15456556 ps
T1022 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3804438110 Apr 21 12:22:47 PM PDT 24 Apr 21 12:22:49 PM PDT 24 56965991 ps
T165 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2824910071 Apr 21 12:22:35 PM PDT 24 Apr 21 12:22:42 PM PDT 24 160840939 ps
T1023 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.476157253 Apr 21 12:23:36 PM PDT 24 Apr 21 12:23:48 PM PDT 24 1003272555 ps
T1024 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2936820923 Apr 21 12:22:51 PM PDT 24 Apr 21 12:22:52 PM PDT 24 10366325 ps
T1025 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2711689485 Apr 21 12:22:48 PM PDT 24 Apr 21 12:22:56 PM PDT 24 797497770 ps
T1026 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1159528949 Apr 21 12:23:17 PM PDT 24 Apr 21 12:23:19 PM PDT 24 38983813 ps
T1027 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1611677219 Apr 21 12:23:10 PM PDT 24 Apr 21 12:23:11 PM PDT 24 32522559 ps
T1028 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.185138712 Apr 21 12:23:44 PM PDT 24 Apr 21 12:23:55 PM PDT 24 9868297 ps
T1029 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2010737381 Apr 21 12:20:54 PM PDT 24 Apr 21 12:20:57 PM PDT 24 15267665 ps
T1030 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4194807371 Apr 21 12:21:53 PM PDT 24 Apr 21 12:21:55 PM PDT 24 162585353 ps
T1031 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.316937732 Apr 21 12:23:02 PM PDT 24 Apr 21 12:23:05 PM PDT 24 278134455 ps
T1032 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2623233094 Apr 21 12:19:30 PM PDT 24 Apr 21 12:19:32 PM PDT 24 183706684 ps
T1033 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2775234624 Apr 21 12:22:35 PM PDT 24 Apr 21 12:22:42 PM PDT 24 628324660 ps
T181 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3238249423 Apr 21 12:22:35 PM PDT 24 Apr 21 12:22:42 PM PDT 24 698516800 ps
T1034 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1445134360 Apr 21 12:22:51 PM PDT 24 Apr 21 12:22:59 PM PDT 24 534891937 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2310705530 Apr 21 12:22:52 PM PDT 24 Apr 21 12:22:56 PM PDT 24 276642669 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3499243683 Apr 21 12:21:46 PM PDT 24 Apr 21 12:21:49 PM PDT 24 48804659 ps
T1037 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1313373255 Apr 21 12:19:45 PM PDT 24 Apr 21 12:19:50 PM PDT 24 111922391 ps
T1038 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3841170835 Apr 21 12:21:29 PM PDT 24 Apr 21 12:21:30 PM PDT 24 106065041 ps
T1039 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1320509863 Apr 21 12:18:37 PM PDT 24 Apr 21 12:18:42 PM PDT 24 180125878 ps
T1040 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.963743169 Apr 21 12:23:01 PM PDT 24 Apr 21 12:23:05 PM PDT 24 763573543 ps
T1041 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.577508667 Apr 21 12:19:43 PM PDT 24 Apr 21 12:19:44 PM PDT 24 21988260 ps
T1042 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1773638149 Apr 21 12:23:17 PM PDT 24 Apr 21 12:23:23 PM PDT 24 1902848158 ps
T1043 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3160830122 Apr 21 12:20:12 PM PDT 24 Apr 21 12:20:16 PM PDT 24 505724800 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2183350001 Apr 21 12:18:10 PM PDT 24 Apr 21 12:18:16 PM PDT 24 440735289 ps
T1045 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.186006460 Apr 21 12:23:56 PM PDT 24 Apr 21 12:23:59 PM PDT 24 344182000 ps
T1046 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2922128310 Apr 21 12:24:33 PM PDT 24 Apr 21 12:24:46 PM PDT 24 2135070916 ps
T1047 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.752650111 Apr 21 12:21:30 PM PDT 24 Apr 21 12:21:32 PM PDT 24 81725077 ps
T1048 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1186390997 Apr 21 12:23:01 PM PDT 24 Apr 21 12:23:20 PM PDT 24 1332527632 ps
T1049 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2468482980 Apr 21 12:18:30 PM PDT 24 Apr 21 12:18:32 PM PDT 24 52840029 ps
T1050 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.388691557 Apr 21 12:22:47 PM PDT 24 Apr 21 12:22:53 PM PDT 24 1657358707 ps
T167 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.842142811 Apr 21 12:24:38 PM PDT 24 Apr 21 12:24:51 PM PDT 24 1947149773 ps
T1051 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3849790749 Apr 21 12:22:35 PM PDT 24 Apr 21 12:22:38 PM PDT 24 128015799 ps
T1052 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3921072268 Apr 21 12:22:57 PM PDT 24 Apr 21 12:22:59 PM PDT 24 189361106 ps
T1053 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3945130605 Apr 21 12:23:14 PM PDT 24 Apr 21 12:23:16 PM PDT 24 17126417 ps
T1054 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3974573896 Apr 21 12:22:51 PM PDT 24 Apr 21 12:22:53 PM PDT 24 63701294 ps
T1055 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2809238998 Apr 21 12:19:12 PM PDT 24 Apr 21 12:19:14 PM PDT 24 87610437 ps
T1056 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.137217623 Apr 21 12:22:50 PM PDT 24 Apr 21 12:22:52 PM PDT 24 27818408 ps
T1057 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1079103960 Apr 21 12:23:36 PM PDT 24 Apr 21 12:23:52 PM PDT 24 466805633 ps
T1058 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4139997431 Apr 21 12:23:47 PM PDT 24 Apr 21 12:23:48 PM PDT 24 69059126 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2616804226 Apr 21 12:20:05 PM PDT 24 Apr 21 12:20:08 PM PDT 24 213015468 ps
T1060 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.122922369 Apr 21 12:23:05 PM PDT 24 Apr 21 12:23:09 PM PDT 24 64228428 ps
T1061 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.269596652 Apr 21 12:23:01 PM PDT 24 Apr 21 12:23:06 PM PDT 24 1097415471 ps
T1062 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3043797046 Apr 21 12:22:50 PM PDT 24 Apr 21 12:23:28 PM PDT 24 1353457802 ps
T1063 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3795431477 Apr 21 12:22:36 PM PDT 24 Apr 21 12:22:38 PM PDT 24 29269090 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.246473836 Apr 21 12:24:41 PM PDT 24 Apr 21 12:24:42 PM PDT 24 50421814 ps
T1065 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4234342825 Apr 21 12:20:53 PM PDT 24 Apr 21 12:20:57 PM PDT 24 115764210 ps
T1066 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.599745129 Apr 21 12:18:40 PM PDT 24 Apr 21 12:18:41 PM PDT 24 19667098 ps
T1067 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2349066312 Apr 21 12:21:52 PM PDT 24 Apr 21 12:21:53 PM PDT 24 17501310 ps
T1068 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.55520206 Apr 21 12:22:35 PM PDT 24 Apr 21 12:22:43 PM PDT 24 157127817 ps
T1069 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3060550340 Apr 21 12:21:21 PM PDT 24 Apr 21 12:21:26 PM PDT 24 220548415 ps
T1070 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2034959721 Apr 21 12:18:33 PM PDT 24 Apr 21 12:18:45 PM PDT 24 912483001 ps
T1071 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1304419315 Apr 21 12:23:37 PM PDT 24 Apr 21 12:23:39 PM PDT 24 49512160 ps
T1072 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1299666422 Apr 21 12:22:48 PM PDT 24 Apr 21 12:22:54 PM PDT 24 480838513 ps
T1073 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2553340013 Apr 21 12:22:35 PM PDT 24 Apr 21 12:22:45 PM PDT 24 418328758 ps
T1074 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3045670418 Apr 21 12:23:33 PM PDT 24 Apr 21 12:23:35 PM PDT 24 124991307 ps
T1075 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1286929210 Apr 21 12:24:13 PM PDT 24 Apr 21 12:24:18 PM PDT 24 300741114 ps

Test location /workspace/coverage/default/11.keymgr_stress_all.3062394178
Short name T5
Test name
Test status
Simulation time 945408236 ps
CPU time 26.86 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:25:18 PM PDT 24
Peak memory 222272 kb
Host smart-ae45503c-177e-4cc0-92c0-a42b6063221b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062394178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3062394178
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3973873389
Short name T51
Test name
Test status
Simulation time 2571158431 ps
CPU time 19.55 seconds
Started Apr 21 12:26:55 PM PDT 24
Finished Apr 21 12:27:16 PM PDT 24
Peak memory 219528 kb
Host smart-d6481c05-6605-43af-977e-57ab64cd4a9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973873389 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3973873389
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2394793311
Short name T7
Test name
Test status
Simulation time 1131086937 ps
CPU time 18.42 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 238492 kb
Host smart-c0261d37-6ca0-4a75-bce8-f5302c23c6c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394793311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2394793311
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3665310892
Short name T45
Test name
Test status
Simulation time 1154334579 ps
CPU time 39.55 seconds
Started Apr 21 12:26:38 PM PDT 24
Finished Apr 21 12:27:19 PM PDT 24
Peak memory 216488 kb
Host smart-2e30bbd4-9202-4a9e-b36e-5a450fc33e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665310892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3665310892
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.4254720982
Short name T78
Test name
Test status
Simulation time 217802448 ps
CPU time 4.06 seconds
Started Apr 21 12:26:13 PM PDT 24
Finished Apr 21 12:26:18 PM PDT 24
Peak memory 222352 kb
Host smart-ba720074-ac1e-4ece-b76e-01328be0b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254720982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4254720982
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3201503881
Short name T2
Test name
Test status
Simulation time 681799186 ps
CPU time 9.01 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:25:03 PM PDT 24
Peak memory 215496 kb
Host smart-4ec7e4b2-a8b2-47aa-b318-c5a52d88ec2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201503881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3201503881
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3181911716
Short name T57
Test name
Test status
Simulation time 2509175453 ps
CPU time 59.73 seconds
Started Apr 21 12:25:56 PM PDT 24
Finished Apr 21 12:26:56 PM PDT 24
Peak memory 222388 kb
Host smart-5f8dd2bf-be91-47bd-82b5-b4b16021133b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181911716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3181911716
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3934063664
Short name T8
Test name
Test status
Simulation time 83442596 ps
CPU time 2.73 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 221772 kb
Host smart-09777b59-e527-44ee-9f22-5621170f8f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934063664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3934063664
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3396341250
Short name T111
Test name
Test status
Simulation time 881172684 ps
CPU time 8.02 seconds
Started Apr 21 12:21:17 PM PDT 24
Finished Apr 21 12:21:25 PM PDT 24
Peak memory 213024 kb
Host smart-823fdf66-a896-4ac9-890b-9c5152454300
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396341250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3396341250
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.800822008
Short name T152
Test name
Test status
Simulation time 286617019 ps
CPU time 14.19 seconds
Started Apr 21 12:24:38 PM PDT 24
Finished Apr 21 12:24:53 PM PDT 24
Peak memory 214088 kb
Host smart-9381998c-05f2-4085-a5b2-edd73182b739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800822008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.800822008
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2380153633
Short name T26
Test name
Test status
Simulation time 527241631 ps
CPU time 5.47 seconds
Started Apr 21 12:26:13 PM PDT 24
Finished Apr 21 12:26:19 PM PDT 24
Peak memory 221292 kb
Host smart-8179579b-26a4-4a54-8671-41a231e1ec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380153633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2380153633
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.883542539
Short name T238
Test name
Test status
Simulation time 222022548 ps
CPU time 6.05 seconds
Started Apr 21 12:26:51 PM PDT 24
Finished Apr 21 12:26:57 PM PDT 24
Peak memory 215396 kb
Host smart-2cc2a443-f931-494b-95a2-160ec8f9b50e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883542539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.883542539
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.172163893
Short name T42
Test name
Test status
Simulation time 784441934 ps
CPU time 27.72 seconds
Started Apr 21 12:24:27 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 215348 kb
Host smart-cab335c7-58b7-4d37-8a02-eaeba2dea2c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172163893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.172163893
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.4082675681
Short name T359
Test name
Test status
Simulation time 552323397 ps
CPU time 12.2 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 215216 kb
Host smart-08e8e63d-a560-4adf-978a-a2ec3e310cc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082675681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.4082675681
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1274826367
Short name T334
Test name
Test status
Simulation time 971027207 ps
CPU time 13.84 seconds
Started Apr 21 12:25:05 PM PDT 24
Finished Apr 21 12:25:19 PM PDT 24
Peak memory 215312 kb
Host smart-96aafe6b-92f5-4771-8edf-474ad458457f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274826367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1274826367
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2486477983
Short name T52
Test name
Test status
Simulation time 9384890335 ps
CPU time 212.45 seconds
Started Apr 21 12:25:15 PM PDT 24
Finished Apr 21 12:28:48 PM PDT 24
Peak memory 218856 kb
Host smart-33c62d95-7901-4ed2-b40b-2cd6ede036b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486477983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2486477983
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.25034895
Short name T115
Test name
Test status
Simulation time 1584488066 ps
CPU time 19.82 seconds
Started Apr 21 12:26:10 PM PDT 24
Finished Apr 21 12:26:31 PM PDT 24
Peak memory 220804 kb
Host smart-573af700-f832-4441-9d18-44a4e46e0420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25034895 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.25034895
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.367687479
Short name T263
Test name
Test status
Simulation time 1332662908 ps
CPU time 65.29 seconds
Started Apr 21 12:26:24 PM PDT 24
Finished Apr 21 12:27:30 PM PDT 24
Peak memory 222272 kb
Host smart-879e6eaa-7a08-448e-8df3-d6ac590cae03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367687479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.367687479
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1925783503
Short name T113
Test name
Test status
Simulation time 93816658 ps
CPU time 1.98 seconds
Started Apr 21 12:23:02 PM PDT 24
Finished Apr 21 12:23:05 PM PDT 24
Peak memory 222200 kb
Host smart-4d254e15-18ce-4163-8904-e09d93690351
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925783503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1925783503
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1210771988
Short name T23
Test name
Test status
Simulation time 237970155 ps
CPU time 5.81 seconds
Started Apr 21 12:25:55 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 214100 kb
Host smart-120620be-361b-4c45-85e9-df3a5aafd912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210771988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1210771988
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3795357035
Short name T35
Test name
Test status
Simulation time 71437660 ps
CPU time 2.46 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:25:27 PM PDT 24
Peak memory 214132 kb
Host smart-5d094380-47f9-4c0d-a851-2cf07c9ff98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795357035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3795357035
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3116313043
Short name T28
Test name
Test status
Simulation time 118080767 ps
CPU time 4.65 seconds
Started Apr 21 12:24:43 PM PDT 24
Finished Apr 21 12:24:48 PM PDT 24
Peak memory 209052 kb
Host smart-386c9d52-2369-413d-82e8-5064b08aaeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116313043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3116313043
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3591489626
Short name T91
Test name
Test status
Simulation time 423238206 ps
CPU time 4.11 seconds
Started Apr 21 12:26:00 PM PDT 24
Finished Apr 21 12:26:05 PM PDT 24
Peak memory 214184 kb
Host smart-d577e655-0857-4a0f-b6a8-f8955566f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591489626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3591489626
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2008960296
Short name T95
Test name
Test status
Simulation time 12488418 ps
CPU time 0.88 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:47 PM PDT 24
Peak memory 205652 kb
Host smart-2c252385-39a2-4efc-9090-158e198316b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008960296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2008960296
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3785630038
Short name T55
Test name
Test status
Simulation time 4399231502 ps
CPU time 25 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:59 PM PDT 24
Peak memory 215536 kb
Host smart-8b1affbd-ff4a-41d1-803c-29103e27bd28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785630038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3785630038
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4053236019
Short name T226
Test name
Test status
Simulation time 4866096069 ps
CPU time 130.61 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:28:42 PM PDT 24
Peak memory 215012 kb
Host smart-5b577680-8858-443e-aae5-a80f4e6c8d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053236019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4053236019
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2254276116
Short name T61
Test name
Test status
Simulation time 58981594 ps
CPU time 2.19 seconds
Started Apr 21 12:25:52 PM PDT 24
Finished Apr 21 12:26:00 PM PDT 24
Peak memory 209748 kb
Host smart-ffe8a59d-29b3-4803-9035-a1c0fceae219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254276116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2254276116
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1453131310
Short name T230
Test name
Test status
Simulation time 190481850 ps
CPU time 9.22 seconds
Started Apr 21 12:25:22 PM PDT 24
Finished Apr 21 12:25:32 PM PDT 24
Peak memory 214728 kb
Host smart-db0a3e80-9c6b-4c25-aec7-f63d039ce1a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1453131310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1453131310
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2912677548
Short name T18
Test name
Test status
Simulation time 296285280 ps
CPU time 3.13 seconds
Started Apr 21 12:26:20 PM PDT 24
Finished Apr 21 12:26:23 PM PDT 24
Peak memory 208700 kb
Host smart-0dcecd3c-3ef0-44a4-955c-ac1ce98256e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912677548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2912677548
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2892879385
Short name T203
Test name
Test status
Simulation time 16664126611 ps
CPU time 137.07 seconds
Started Apr 21 12:26:11 PM PDT 24
Finished Apr 21 12:28:28 PM PDT 24
Peak memory 222432 kb
Host smart-bb841972-6cf3-4472-8b2c-dcddf834d123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892879385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2892879385
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2999548852
Short name T157
Test name
Test status
Simulation time 34879746 ps
CPU time 2.61 seconds
Started Apr 21 12:25:35 PM PDT 24
Finished Apr 21 12:25:39 PM PDT 24
Peak memory 217892 kb
Host smart-22d4c4ef-0fef-4057-8fd6-70cf4183ff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999548852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2999548852
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2215789435
Short name T99
Test name
Test status
Simulation time 244140110 ps
CPU time 3.46 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 210460 kb
Host smart-ad14a994-977b-4346-9282-9df442adf46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215789435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2215789435
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.230309694
Short name T189
Test name
Test status
Simulation time 8380802888 ps
CPU time 55.28 seconds
Started Apr 21 12:26:22 PM PDT 24
Finished Apr 21 12:27:18 PM PDT 24
Peak memory 216108 kb
Host smart-21e14f73-68ae-4b73-8990-6ff5f4a0a959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230309694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.230309694
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.699811444
Short name T142
Test name
Test status
Simulation time 347962457 ps
CPU time 4.02 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 214128 kb
Host smart-a4394d23-7eb1-4e8f-b2c8-4c50901798e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699811444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.699811444
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1181345499
Short name T41
Test name
Test status
Simulation time 339089463 ps
CPU time 13.81 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:49 PM PDT 24
Peak memory 220304 kb
Host smart-eb7d9663-2f81-46e1-8ec1-f24c00325f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181345499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1181345499
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3305810720
Short name T170
Test name
Test status
Simulation time 1720000440 ps
CPU time 17.72 seconds
Started Apr 21 12:17:51 PM PDT 24
Finished Apr 21 12:18:09 PM PDT 24
Peak memory 214180 kb
Host smart-d5c8a325-3aeb-46bf-96c5-ca3d2614a9d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305810720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3305810720
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1345670379
Short name T119
Test name
Test status
Simulation time 373034350 ps
CPU time 8.41 seconds
Started Apr 21 12:22:49 PM PDT 24
Finished Apr 21 12:22:59 PM PDT 24
Peak memory 213328 kb
Host smart-b370024b-fff0-4279-af5e-f7678b36c087
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345670379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1345670379
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1683866931
Short name T22
Test name
Test status
Simulation time 355926317 ps
CPU time 4.4 seconds
Started Apr 21 12:26:04 PM PDT 24
Finished Apr 21 12:26:08 PM PDT 24
Peak memory 218884 kb
Host smart-44fa0f9a-4ebc-495b-8fa4-b803273f4cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683866931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1683866931
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2229478251
Short name T195
Test name
Test status
Simulation time 76355601 ps
CPU time 3.9 seconds
Started Apr 21 12:26:26 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 214012 kb
Host smart-0659ad72-5a04-4cff-bacf-353597192d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229478251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2229478251
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4117120300
Short name T282
Test name
Test status
Simulation time 4632657276 ps
CPU time 68.24 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:27:43 PM PDT 24
Peak memory 222348 kb
Host smart-a8d73a70-8658-4bbe-93ff-46fa14382f54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117120300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4117120300
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.842142811
Short name T167
Test name
Test status
Simulation time 1947149773 ps
CPU time 12.21 seconds
Started Apr 21 12:24:38 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 208976 kb
Host smart-badda5f5-e663-4440-9af2-cc8831a90c70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842142811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
842142811
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2824910071
Short name T165
Test name
Test status
Simulation time 160840939 ps
CPU time 5.5 seconds
Started Apr 21 12:22:35 PM PDT 24
Finished Apr 21 12:22:42 PM PDT 24
Peak memory 211588 kb
Host smart-f0149908-a523-4029-be98-585750ac92cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824910071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2824910071
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1601337745
Short name T328
Test name
Test status
Simulation time 840379694 ps
CPU time 11.83 seconds
Started Apr 21 12:25:29 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 214168 kb
Host smart-d3a6a7d9-80e2-4e2a-a4d8-a36e27224300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601337745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1601337745
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.588638347
Short name T273
Test name
Test status
Simulation time 210678685 ps
CPU time 2.94 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 222292 kb
Host smart-4cf5a8bf-af98-4e67-a46c-db70449e0b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588638347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.588638347
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1115570751
Short name T299
Test name
Test status
Simulation time 205016898 ps
CPU time 3.8 seconds
Started Apr 21 12:25:09 PM PDT 24
Finished Apr 21 12:25:13 PM PDT 24
Peak memory 214676 kb
Host smart-52443533-eeac-4058-af0d-d942d7611c38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115570751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1115570751
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.4177103220
Short name T82
Test name
Test status
Simulation time 325185114 ps
CPU time 4.18 seconds
Started Apr 21 12:25:27 PM PDT 24
Finished Apr 21 12:25:32 PM PDT 24
Peak memory 208412 kb
Host smart-ffbeebd4-8d02-482d-b422-defbf0c460f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177103220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4177103220
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1135263276
Short name T75
Test name
Test status
Simulation time 739876120 ps
CPU time 35.29 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:26:16 PM PDT 24
Peak memory 215516 kb
Host smart-a31e3c06-4cd9-4a8f-a9c2-88f2a9ca93d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135263276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1135263276
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3670213572
Short name T262
Test name
Test status
Simulation time 239408968 ps
CPU time 4.35 seconds
Started Apr 21 12:26:21 PM PDT 24
Finished Apr 21 12:26:26 PM PDT 24
Peak memory 214164 kb
Host smart-5c2f78fa-50bd-4ce2-b385-a34993dfc6c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3670213572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3670213572
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2636306095
Short name T154
Test name
Test status
Simulation time 925104346 ps
CPU time 10.92 seconds
Started Apr 21 12:25:07 PM PDT 24
Finished Apr 21 12:25:18 PM PDT 24
Peak memory 217520 kb
Host smart-90cb3600-bc5a-472c-843c-7536e6cb1080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636306095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2636306095
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3616404439
Short name T33
Test name
Test status
Simulation time 319619254 ps
CPU time 2.35 seconds
Started Apr 21 12:25:31 PM PDT 24
Finished Apr 21 12:25:33 PM PDT 24
Peak memory 207828 kb
Host smart-f6aa475d-de1b-4d30-8e0a-970c52ffa484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616404439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3616404439
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2557568091
Short name T155
Test name
Test status
Simulation time 32664863 ps
CPU time 2.21 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 215244 kb
Host smart-aa62873f-082b-4746-a8bd-94cd0aaccd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557568091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2557568091
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1827930707
Short name T67
Test name
Test status
Simulation time 6707203780 ps
CPU time 46.61 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:26:27 PM PDT 24
Peak memory 222712 kb
Host smart-ac4d66bb-2d5f-46c0-9df3-c19d98c1578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827930707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1827930707
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1003583933
Short name T711
Test name
Test status
Simulation time 5232706841 ps
CPU time 31.88 seconds
Started Apr 21 12:26:19 PM PDT 24
Finished Apr 21 12:26:52 PM PDT 24
Peak memory 215248 kb
Host smart-aaa3cffa-5d6d-48f6-ba3f-296a88ca690f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003583933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1003583933
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3420873584
Short name T222
Test name
Test status
Simulation time 17291533034 ps
CPU time 326.36 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:31:17 PM PDT 24
Peak memory 222380 kb
Host smart-1c5329d0-d4db-4cef-8ddc-60ba3cddf90d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420873584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3420873584
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1038893485
Short name T236
Test name
Test status
Simulation time 516978311 ps
CPU time 6.28 seconds
Started Apr 21 12:26:02 PM PDT 24
Finished Apr 21 12:26:09 PM PDT 24
Peak memory 209964 kb
Host smart-d2f7ec6d-23ea-45c1-abcf-84dece579ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038893485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1038893485
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.153189131
Short name T178
Test name
Test status
Simulation time 54733238 ps
CPU time 1.92 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:37 PM PDT 24
Peak memory 210148 kb
Host smart-b37a04db-b825-44f6-ab71-c601e0679ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153189131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.153189131
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2528697238
Short name T163
Test name
Test status
Simulation time 1404544411 ps
CPU time 36.92 seconds
Started Apr 21 12:21:36 PM PDT 24
Finished Apr 21 12:22:13 PM PDT 24
Peak memory 210044 kb
Host smart-8cd23cfa-158c-42ef-99e0-338ba6df1c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528697238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2528697238
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1745852210
Short name T87
Test name
Test status
Simulation time 58623725 ps
CPU time 3.3 seconds
Started Apr 21 12:26:46 PM PDT 24
Finished Apr 21 12:26:50 PM PDT 24
Peak memory 213988 kb
Host smart-b16f34c8-b5db-480f-9728-b7b087c4ff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745852210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1745852210
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1661720755
Short name T357
Test name
Test status
Simulation time 1432565228 ps
CPU time 7.48 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 222268 kb
Host smart-ca59b0bf-496f-4cb0-9563-fbd7a3b0a8ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661720755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1661720755
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1092432392
Short name T156
Test name
Test status
Simulation time 47483971 ps
CPU time 3.61 seconds
Started Apr 21 12:25:52 PM PDT 24
Finished Apr 21 12:25:56 PM PDT 24
Peak memory 218236 kb
Host smart-57bba6bf-1ac0-4d7e-9524-00aa4911845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092432392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1092432392
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2173214853
Short name T609
Test name
Test status
Simulation time 342750815 ps
CPU time 2.17 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:24:47 PM PDT 24
Peak memory 209536 kb
Host smart-a291686d-2b75-401c-9304-3a754513cdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173214853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2173214853
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.359335430
Short name T25
Test name
Test status
Simulation time 428473728 ps
CPU time 6.46 seconds
Started Apr 21 12:24:54 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 222224 kb
Host smart-549e0153-7777-4792-b271-d06b085998bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359335430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.359335430
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2146455184
Short name T324
Test name
Test status
Simulation time 189022509 ps
CPU time 3.38 seconds
Started Apr 21 12:25:13 PM PDT 24
Finished Apr 21 12:25:17 PM PDT 24
Peak memory 206388 kb
Host smart-63e9f14f-ad76-43b5-bb68-b20427f3981e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146455184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2146455184
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3367704498
Short name T318
Test name
Test status
Simulation time 56555947 ps
CPU time 2.35 seconds
Started Apr 21 12:25:20 PM PDT 24
Finished Apr 21 12:25:23 PM PDT 24
Peak memory 214292 kb
Host smart-79c552a9-4345-4e96-9fe9-c58f3bedff38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367704498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3367704498
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.449430325
Short name T114
Test name
Test status
Simulation time 909024764 ps
CPU time 16.7 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 220504 kb
Host smart-9b9c22a8-d0d2-4326-9951-d0a78a2ee67c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449430325 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.449430325
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3740132950
Short name T362
Test name
Test status
Simulation time 939584160 ps
CPU time 34.98 seconds
Started Apr 21 12:25:21 PM PDT 24
Finished Apr 21 12:25:56 PM PDT 24
Peak memory 215240 kb
Host smart-0b633e76-fc87-4601-9ad3-15132c11342c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740132950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3740132950
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3613127445
Short name T251
Test name
Test status
Simulation time 138164162 ps
CPU time 5.3 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:39 PM PDT 24
Peak memory 207216 kb
Host smart-7aa4ff28-d20a-420f-a4fa-7795688fca64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613127445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3613127445
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3318877175
Short name T228
Test name
Test status
Simulation time 1028043236 ps
CPU time 11.74 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 215528 kb
Host smart-94ff8451-bcaf-4fc3-b459-9b943e3c9935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3318877175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3318877175
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2898318047
Short name T205
Test name
Test status
Simulation time 1057888242 ps
CPU time 10.03 seconds
Started Apr 21 12:25:45 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 214652 kb
Host smart-41149e03-90b0-4033-bce2-4bdf3b0099f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898318047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2898318047
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.381586062
Short name T71
Test name
Test status
Simulation time 2890227529 ps
CPU time 42.33 seconds
Started Apr 21 12:26:03 PM PDT 24
Finished Apr 21 12:26:46 PM PDT 24
Peak memory 215944 kb
Host smart-dd4e58d8-d48b-4607-9569-32fc633ba729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381586062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.381586062
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1561025395
Short name T215
Test name
Test status
Simulation time 5505602213 ps
CPU time 34.64 seconds
Started Apr 21 12:25:53 PM PDT 24
Finished Apr 21 12:26:28 PM PDT 24
Peak memory 215492 kb
Host smart-616fefbd-870e-413a-b719-45af80b1af35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561025395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1561025395
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3442179669
Short name T329
Test name
Test status
Simulation time 288459535 ps
CPU time 3.66 seconds
Started Apr 21 12:26:16 PM PDT 24
Finished Apr 21 12:26:20 PM PDT 24
Peak memory 211460 kb
Host smart-5e7b8520-0a62-4f01-ab95-385bdee1ab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442179669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3442179669
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2204353287
Short name T257
Test name
Test status
Simulation time 295313809 ps
CPU time 8.7 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:38 PM PDT 24
Peak memory 210404 kb
Host smart-488c5786-d52a-4026-84a2-0c210b8ff042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204353287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2204353287
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1601706048
Short name T241
Test name
Test status
Simulation time 2914174768 ps
CPU time 9.41 seconds
Started Apr 21 12:24:49 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 214264 kb
Host smart-9e6e0cbd-b755-4eff-90f6-f5105953f35f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1601706048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1601706048
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3955275534
Short name T183
Test name
Test status
Simulation time 1284962907 ps
CPU time 22.1 seconds
Started Apr 21 12:22:57 PM PDT 24
Finished Apr 21 12:23:20 PM PDT 24
Peak memory 212916 kb
Host smart-2aa6f0c8-4c97-4d11-9208-9f2c94523bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955275534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3955275534
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4038930964
Short name T177
Test name
Test status
Simulation time 1279278982 ps
CPU time 20.9 seconds
Started Apr 21 12:22:52 PM PDT 24
Finished Apr 21 12:23:13 PM PDT 24
Peak memory 213412 kb
Host smart-b27973ee-9394-4d29-85d2-2c5b739ffc6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038930964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4038930964
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.4008520330
Short name T182
Test name
Test status
Simulation time 368639613 ps
CPU time 11.36 seconds
Started Apr 21 12:23:14 PM PDT 24
Finished Apr 21 12:23:26 PM PDT 24
Peak memory 213224 kb
Host smart-81d3aa09-b057-4d55-8298-32f7dafded05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008520330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.4008520330
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.122961381
Short name T175
Test name
Test status
Simulation time 329560243 ps
CPU time 5.2 seconds
Started Apr 21 12:22:35 PM PDT 24
Finished Apr 21 12:22:42 PM PDT 24
Peak memory 207616 kb
Host smart-012c96d0-c18b-4c0d-a9c0-3b1fbdf43d37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122961381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
122961381
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2833513927
Short name T93
Test name
Test status
Simulation time 489012868 ps
CPU time 5.76 seconds
Started Apr 21 12:26:01 PM PDT 24
Finished Apr 21 12:26:08 PM PDT 24
Peak memory 214164 kb
Host smart-158063ac-2e6b-48c9-a57a-a4060d6f0e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833513927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2833513927
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2360016654
Short name T158
Test name
Test status
Simulation time 613752066 ps
CPU time 7.04 seconds
Started Apr 21 12:26:01 PM PDT 24
Finished Apr 21 12:26:09 PM PDT 24
Peak memory 222568 kb
Host smart-481664e3-00a6-4233-b610-6a5633441d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360016654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2360016654
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3960664512
Short name T173
Test name
Test status
Simulation time 1575585142 ps
CPU time 30.42 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:23:21 PM PDT 24
Peak memory 208440 kb
Host smart-3463b479-f41f-43e9-a89e-d8f519437310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960664512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3960664512
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3167590728
Short name T310
Test name
Test status
Simulation time 211776662 ps
CPU time 3.38 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 207168 kb
Host smart-a3d53aab-ef0d-447c-9091-38b1cf760446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167590728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3167590728
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.4196937303
Short name T105
Test name
Test status
Simulation time 115987709 ps
CPU time 4.51 seconds
Started Apr 21 12:24:35 PM PDT 24
Finished Apr 21 12:24:40 PM PDT 24
Peak memory 208264 kb
Host smart-d11364e4-b225-4d62-85bb-e2188dbe18bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196937303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4196937303
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3321169100
Short name T340
Test name
Test status
Simulation time 25822926 ps
CPU time 1.94 seconds
Started Apr 21 12:25:28 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 222384 kb
Host smart-b807048f-9476-4be9-9f9c-db2977d0f315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321169100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3321169100
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2017480931
Short name T168
Test name
Test status
Simulation time 2173467981 ps
CPU time 16.6 seconds
Started Apr 21 12:25:02 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 221284 kb
Host smart-9d9fe035-a390-4680-adbc-79f48df38ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017480931 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2017480931
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1256233834
Short name T348
Test name
Test status
Simulation time 95805725 ps
CPU time 3.93 seconds
Started Apr 21 12:25:00 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 213804 kb
Host smart-3c91f1e8-a975-4bb0-9522-cdb30123a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256233834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1256233834
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2549969920
Short name T301
Test name
Test status
Simulation time 574843541 ps
CPU time 4.62 seconds
Started Apr 21 12:25:25 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 213376 kb
Host smart-03e78f9d-22c2-4151-876a-959b1169c3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549969920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2549969920
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2246495340
Short name T331
Test name
Test status
Simulation time 1306123011 ps
CPU time 9.61 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 210508 kb
Host smart-f5121243-8fff-4b9a-b65e-d00b0490b7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246495340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2246495340
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.756528632
Short name T308
Test name
Test status
Simulation time 766326738 ps
CPU time 6.26 seconds
Started Apr 21 12:25:03 PM PDT 24
Finished Apr 21 12:25:10 PM PDT 24
Peak memory 214124 kb
Host smart-7e8eea18-433d-46cb-9a4d-b2af080b3291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756528632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.756528632
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_random.4088661851
Short name T861
Test name
Test status
Simulation time 505122478 ps
CPU time 6.81 seconds
Started Apr 21 12:25:20 PM PDT 24
Finished Apr 21 12:25:27 PM PDT 24
Peak memory 218232 kb
Host smart-841da84c-750f-44dc-b3b4-9c77f7078e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088661851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4088661851
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1452088230
Short name T92
Test name
Test status
Simulation time 195065993 ps
CPU time 4.77 seconds
Started Apr 21 12:25:28 PM PDT 24
Finished Apr 21 12:25:33 PM PDT 24
Peak memory 209488 kb
Host smart-a460616b-07ca-4a77-a6e8-89fa71d603b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452088230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1452088230
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.441258785
Short name T204
Test name
Test status
Simulation time 42694286 ps
CPU time 2.86 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:36 PM PDT 24
Peak memory 222568 kb
Host smart-ae547649-2727-4313-b9be-2e6fc14b31d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441258785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.441258785
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2754839233
Short name T278
Test name
Test status
Simulation time 148283140 ps
CPU time 7.1 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 215232 kb
Host smart-b3e0f313-4260-4ddb-b800-19927afbd865
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754839233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2754839233
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3004356929
Short name T212
Test name
Test status
Simulation time 800658045 ps
CPU time 5.19 seconds
Started Apr 21 12:25:41 PM PDT 24
Finished Apr 21 12:25:48 PM PDT 24
Peak memory 209916 kb
Host smart-86d66e3a-f480-40f8-a7db-c70aa1b21211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004356929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3004356929
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.173440619
Short name T274
Test name
Test status
Simulation time 248022311 ps
CPU time 3.2 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 214276 kb
Host smart-aaa6a74e-e369-44df-b27c-5c3d834674b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173440619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.173440619
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.652195240
Short name T235
Test name
Test status
Simulation time 90414124 ps
CPU time 3.93 seconds
Started Apr 21 12:25:55 PM PDT 24
Finished Apr 21 12:26:00 PM PDT 24
Peak memory 214056 kb
Host smart-85c395ed-9bf0-4678-b535-277714b0c67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652195240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.652195240
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.204140829
Short name T221
Test name
Test status
Simulation time 213360300 ps
CPU time 4.89 seconds
Started Apr 21 12:26:14 PM PDT 24
Finished Apr 21 12:26:19 PM PDT 24
Peak memory 221600 kb
Host smart-12066c56-34fe-4e58-a2a2-626a2aed102a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204140829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.204140829
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3319252579
Short name T225
Test name
Test status
Simulation time 170861711 ps
CPU time 7.1 seconds
Started Apr 21 12:26:09 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 214180 kb
Host smart-7bc10886-f47a-4361-85a2-a56057309644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319252579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3319252579
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3732030054
Short name T369
Test name
Test status
Simulation time 366556042 ps
CPU time 3.94 seconds
Started Apr 21 12:26:32 PM PDT 24
Finished Apr 21 12:26:37 PM PDT 24
Peak memory 209188 kb
Host smart-24ceeb5f-0ddf-4e76-a7da-97598bf09cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732030054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3732030054
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3817437970
Short name T217
Test name
Test status
Simulation time 9915052585 ps
CPU time 214.78 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:30:09 PM PDT 24
Peak memory 217796 kb
Host smart-04ea831e-9b1c-4c0a-8da3-3b678d03b4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817437970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3817437970
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3585413332
Short name T936
Test name
Test status
Simulation time 707868266 ps
CPU time 10.25 seconds
Started Apr 21 12:22:41 PM PDT 24
Finished Apr 21 12:22:53 PM PDT 24
Peak memory 204744 kb
Host smart-020ec450-2074-42c8-bc63-b9098cacec59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585413332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
585413332
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.476157253
Short name T1023
Test name
Test status
Simulation time 1003272555 ps
CPU time 11.44 seconds
Started Apr 21 12:23:36 PM PDT 24
Finished Apr 21 12:23:48 PM PDT 24
Peak memory 204668 kb
Host smart-0ad681d6-1b14-454d-919f-a124d7633f17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476157253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.476157253
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.726912505
Short name T931
Test name
Test status
Simulation time 108145984 ps
CPU time 1.1 seconds
Started Apr 21 12:22:52 PM PDT 24
Finished Apr 21 12:22:54 PM PDT 24
Peak memory 205532 kb
Host smart-a5815bb4-dbca-4561-87fe-2762706cfe6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726912505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.726912505
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2491326773
Short name T917
Test name
Test status
Simulation time 40612541 ps
CPU time 1.63 seconds
Started Apr 21 12:20:47 PM PDT 24
Finished Apr 21 12:20:49 PM PDT 24
Peak memory 213920 kb
Host smart-716630fb-d161-4695-b812-07d6bf19bbbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491326773 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2491326773
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.642311548
Short name T979
Test name
Test status
Simulation time 86270013 ps
CPU time 1.14 seconds
Started Apr 21 12:21:31 PM PDT 24
Finished Apr 21 12:21:33 PM PDT 24
Peak memory 205620 kb
Host smart-7a5543d3-fb69-4bb2-b34b-5d596d15058d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642311548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.642311548
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2936820923
Short name T1024
Test name
Test status
Simulation time 10366325 ps
CPU time 0.84 seconds
Started Apr 21 12:22:51 PM PDT 24
Finished Apr 21 12:22:52 PM PDT 24
Peak memory 205036 kb
Host smart-706b7e20-be38-4c55-9703-3423a8134c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936820923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2936820923
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3639148106
Short name T977
Test name
Test status
Simulation time 359286334 ps
CPU time 2.45 seconds
Started Apr 21 12:22:51 PM PDT 24
Finished Apr 21 12:22:54 PM PDT 24
Peak memory 213584 kb
Host smart-0e007cfc-3e5a-4b8a-9d02-c13fa28d05fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639148106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3639148106
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.478538462
Short name T123
Test name
Test status
Simulation time 520743230 ps
CPU time 2.75 seconds
Started Apr 21 12:24:00 PM PDT 24
Finished Apr 21 12:24:03 PM PDT 24
Peak memory 222260 kb
Host smart-9d5c5ccf-fa03-47ef-b46e-8eb025d0da46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478538462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.478538462
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.762267309
Short name T960
Test name
Test status
Simulation time 1591834479 ps
CPU time 10 seconds
Started Apr 21 12:17:56 PM PDT 24
Finished Apr 21 12:18:07 PM PDT 24
Peak memory 214412 kb
Host smart-96b9ecb6-02cd-4337-a780-02a8d167f53d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762267309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.762267309
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4240450598
Short name T1006
Test name
Test status
Simulation time 137870034 ps
CPU time 3.23 seconds
Started Apr 21 12:19:04 PM PDT 24
Finished Apr 21 12:19:07 PM PDT 24
Peak memory 213344 kb
Host smart-0bd957a7-827f-40d4-af3c-d300246a5a21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240450598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.4240450598
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3238249423
Short name T181
Test name
Test status
Simulation time 698516800 ps
CPU time 6.18 seconds
Started Apr 21 12:22:35 PM PDT 24
Finished Apr 21 12:22:42 PM PDT 24
Peak memory 207732 kb
Host smart-1feef328-381e-447e-b0d5-fd0a4df79f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238249423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3238249423
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3060878702
Short name T965
Test name
Test status
Simulation time 2605164649 ps
CPU time 14.14 seconds
Started Apr 21 12:19:38 PM PDT 24
Finished Apr 21 12:19:53 PM PDT 24
Peak memory 205748 kb
Host smart-4f911765-68f6-42e2-934d-c3daad84bf78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060878702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
060878702
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2472648233
Short name T954
Test name
Test status
Simulation time 274747695 ps
CPU time 6.37 seconds
Started Apr 21 12:20:00 PM PDT 24
Finished Apr 21 12:20:07 PM PDT 24
Peak memory 205912 kb
Host smart-43be3327-cba2-4967-b6dc-d217fc68d13d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472648233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
472648233
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2670243724
Short name T982
Test name
Test status
Simulation time 14080714 ps
CPU time 0.89 seconds
Started Apr 21 12:22:36 PM PDT 24
Finished Apr 21 12:22:37 PM PDT 24
Peak memory 205120 kb
Host smart-43df6550-bb6b-46a1-a747-879092804ef5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670243724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
670243724
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1569610996
Short name T1013
Test name
Test status
Simulation time 56142302 ps
CPU time 2.02 seconds
Started Apr 21 12:24:08 PM PDT 24
Finished Apr 21 12:24:10 PM PDT 24
Peak memory 213880 kb
Host smart-fbfe87d2-f317-42bb-90ad-450b51fb49fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569610996 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1569610996
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3690753051
Short name T1016
Test name
Test status
Simulation time 44790753 ps
CPU time 1.19 seconds
Started Apr 21 12:22:51 PM PDT 24
Finished Apr 21 12:22:53 PM PDT 24
Peak memory 205360 kb
Host smart-b41db758-0586-453c-8401-02b99a017238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690753051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3690753051
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1214876757
Short name T997
Test name
Test status
Simulation time 178603156 ps
CPU time 1.01 seconds
Started Apr 21 12:23:37 PM PDT 24
Finished Apr 21 12:23:39 PM PDT 24
Peak memory 205300 kb
Host smart-b031bc15-47f4-4fd2-9a33-e1dcb93ea9ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214876757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1214876757
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2941440770
Short name T950
Test name
Test status
Simulation time 136476722 ps
CPU time 1.43 seconds
Started Apr 21 12:22:51 PM PDT 24
Finished Apr 21 12:22:53 PM PDT 24
Peak memory 205320 kb
Host smart-7f53e979-768b-47d6-8b83-c396deefa7b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941440770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2941440770
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2483185080
Short name T949
Test name
Test status
Simulation time 1586752857 ps
CPU time 4.91 seconds
Started Apr 21 12:22:49 PM PDT 24
Finished Apr 21 12:22:55 PM PDT 24
Peak memory 222184 kb
Host smart-8a180320-423b-4fdd-9f7e-93a17c0e65c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483185080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2483185080
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.971943168
Short name T122
Test name
Test status
Simulation time 144423057 ps
CPU time 4.29 seconds
Started Apr 21 12:18:51 PM PDT 24
Finished Apr 21 12:18:55 PM PDT 24
Peak memory 213664 kb
Host smart-01f33cef-87a8-4a9d-895a-266527824788
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971943168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.971943168
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1117395924
Short name T920
Test name
Test status
Simulation time 246853815 ps
CPU time 2.21 seconds
Started Apr 21 12:20:54 PM PDT 24
Finished Apr 21 12:20:58 PM PDT 24
Peak memory 214148 kb
Host smart-d009d520-f177-4162-9a93-424d978253fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117395924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1117395924
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.365208860
Short name T923
Test name
Test status
Simulation time 1408792557 ps
CPU time 8.29 seconds
Started Apr 21 12:24:25 PM PDT 24
Finished Apr 21 12:24:34 PM PDT 24
Peak memory 208332 kb
Host smart-bcbafa29-8dbc-4ad2-a949-87238cdeae62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365208860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
365208860
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.82719691
Short name T1008
Test name
Test status
Simulation time 28386111 ps
CPU time 1.26 seconds
Started Apr 21 12:19:00 PM PDT 24
Finished Apr 21 12:19:02 PM PDT 24
Peak memory 213940 kb
Host smart-81e2ac06-09f1-462d-90d5-8e1a174317a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82719691 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.82719691
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.774580317
Short name T1010
Test name
Test status
Simulation time 16600654 ps
CPU time 1.09 seconds
Started Apr 21 12:22:35 PM PDT 24
Finished Apr 21 12:22:38 PM PDT 24
Peak memory 203284 kb
Host smart-e059847d-2e27-4d3a-98b2-67acfd7284bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774580317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.774580317
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3359612512
Short name T921
Test name
Test status
Simulation time 41362488 ps
CPU time 0.72 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:51 PM PDT 24
Peak memory 203176 kb
Host smart-c2bab65c-5460-4fed-8912-c44c7012a33f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359612512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3359612512
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.645149632
Short name T941
Test name
Test status
Simulation time 108338395 ps
CPU time 1.98 seconds
Started Apr 21 12:24:40 PM PDT 24
Finished Apr 21 12:24:42 PM PDT 24
Peak memory 205540 kb
Host smart-e46ab77f-69f3-4bd2-8b96-b3b5739bcda0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645149632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.645149632
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.963743169
Short name T1040
Test name
Test status
Simulation time 763573543 ps
CPU time 3.36 seconds
Started Apr 21 12:23:01 PM PDT 24
Finished Apr 21 12:23:05 PM PDT 24
Peak memory 214128 kb
Host smart-ed0b341f-a63e-486f-a4ba-7e53ae35dc70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963743169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.963743169
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2060790586
Short name T942
Test name
Test status
Simulation time 1851311863 ps
CPU time 10.72 seconds
Started Apr 21 12:23:01 PM PDT 24
Finished Apr 21 12:23:12 PM PDT 24
Peak memory 214052 kb
Host smart-8aa0e3ef-93ea-4069-b450-5da5ebaebce3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060790586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2060790586
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3160830122
Short name T1043
Test name
Test status
Simulation time 505724800 ps
CPU time 3.27 seconds
Started Apr 21 12:20:12 PM PDT 24
Finished Apr 21 12:20:16 PM PDT 24
Peak memory 215620 kb
Host smart-0faec06e-9be8-4233-b62f-3cb54984995d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160830122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3160830122
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2669462800
Short name T952
Test name
Test status
Simulation time 32187945 ps
CPU time 1.38 seconds
Started Apr 21 12:19:14 PM PDT 24
Finished Apr 21 12:19:16 PM PDT 24
Peak memory 205584 kb
Host smart-c0d70f6f-e880-44f8-ab3b-19a74e7cd4cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669462800 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2669462800
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2974548005
Short name T948
Test name
Test status
Simulation time 439226326 ps
CPU time 1.35 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:24:06 PM PDT 24
Peak memory 205324 kb
Host smart-f7231024-e072-441f-826c-c92b290bef14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974548005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2974548005
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3216282289
Short name T908
Test name
Test status
Simulation time 34671072 ps
CPU time 0.77 seconds
Started Apr 21 12:22:35 PM PDT 24
Finished Apr 21 12:22:37 PM PDT 24
Peak memory 203360 kb
Host smart-c4833839-2033-4456-a8c1-3b5803076560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216282289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3216282289
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3045670418
Short name T1074
Test name
Test status
Simulation time 124991307 ps
CPU time 1.7 seconds
Started Apr 21 12:23:33 PM PDT 24
Finished Apr 21 12:23:35 PM PDT 24
Peak memory 205192 kb
Host smart-86c69db7-07fa-4c62-9abe-12bfa3b5c82e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045670418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3045670418
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2553340013
Short name T1073
Test name
Test status
Simulation time 418328758 ps
CPU time 8.51 seconds
Started Apr 21 12:22:35 PM PDT 24
Finished Apr 21 12:22:45 PM PDT 24
Peak memory 211908 kb
Host smart-c94760e3-a976-4e51-821d-9732bf1d25f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553340013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2553340013
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1559615732
Short name T951
Test name
Test status
Simulation time 269543004 ps
CPU time 4.68 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:56 PM PDT 24
Peak memory 213380 kb
Host smart-f5094e78-19a4-4aca-911f-5af63475fe43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559615732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1559615732
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2856892045
Short name T179
Test name
Test status
Simulation time 561537878 ps
CPU time 5.86 seconds
Started Apr 21 12:24:13 PM PDT 24
Finished Apr 21 12:24:20 PM PDT 24
Peak memory 207648 kb
Host smart-33c6ad9e-79e8-4963-853c-f8a55c8c505c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856892045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2856892045
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.316937732
Short name T1031
Test name
Test status
Simulation time 278134455 ps
CPU time 1.92 seconds
Started Apr 21 12:23:02 PM PDT 24
Finished Apr 21 12:23:05 PM PDT 24
Peak memory 213844 kb
Host smart-bd4fe50b-f7e8-4af2-9028-da6d62f023a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316937732 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.316937732
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4064016494
Short name T934
Test name
Test status
Simulation time 72796007 ps
CPU time 0.92 seconds
Started Apr 21 12:23:03 PM PDT 24
Finished Apr 21 12:23:04 PM PDT 24
Peak memory 205416 kb
Host smart-feb3d2b8-10ef-426c-9e53-63b5e51fd668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064016494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4064016494
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.393401933
Short name T970
Test name
Test status
Simulation time 25560370 ps
CPU time 0.74 seconds
Started Apr 21 12:21:04 PM PDT 24
Finished Apr 21 12:21:05 PM PDT 24
Peak memory 205340 kb
Host smart-5e7cc1af-847b-4ed9-8736-25095d005f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393401933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.393401933
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.594901234
Short name T151
Test name
Test status
Simulation time 62939881 ps
CPU time 1.61 seconds
Started Apr 21 12:24:09 PM PDT 24
Finished Apr 21 12:24:11 PM PDT 24
Peak memory 204752 kb
Host smart-4e0caa35-8261-4ae7-83f1-3a2b420cf06b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594901234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.594901234
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3043797046
Short name T1062
Test name
Test status
Simulation time 1353457802 ps
CPU time 37.53 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:23:28 PM PDT 24
Peak memory 229572 kb
Host smart-70a9efa1-27c6-4eea-a184-ff5d23369113
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043797046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3043797046
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2884093454
Short name T995
Test name
Test status
Simulation time 657055188 ps
CPU time 4.57 seconds
Started Apr 21 12:23:01 PM PDT 24
Finished Apr 21 12:23:06 PM PDT 24
Peak memory 214120 kb
Host smart-d0bbe2c1-84a0-452c-95e8-7083d7979765
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884093454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2884093454
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3177621615
Short name T905
Test name
Test status
Simulation time 559413538 ps
CPU time 3.68 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:55 PM PDT 24
Peak memory 221496 kb
Host smart-33e487d9-6c86-49e5-ba25-87f4a1cc4132
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177621615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3177621615
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2273169807
Short name T938
Test name
Test status
Simulation time 382314895 ps
CPU time 5.46 seconds
Started Apr 21 12:23:27 PM PDT 24
Finished Apr 21 12:23:33 PM PDT 24
Peak memory 212908 kb
Host smart-ff4d2f09-b45f-4cac-a4f9-9906f412c7b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273169807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2273169807
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.15915733
Short name T963
Test name
Test status
Simulation time 109500265 ps
CPU time 2.19 seconds
Started Apr 21 12:22:37 PM PDT 24
Finished Apr 21 12:22:40 PM PDT 24
Peak memory 212684 kb
Host smart-3a789cef-e359-472e-852a-33693cfe1828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15915733 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.15915733
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.577508667
Short name T1041
Test name
Test status
Simulation time 21988260 ps
CPU time 1.32 seconds
Started Apr 21 12:19:43 PM PDT 24
Finished Apr 21 12:19:44 PM PDT 24
Peak memory 205980 kb
Host smart-e28f5b34-5493-4b27-a3ad-0fc748ad75ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577508667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.577508667
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.330766643
Short name T998
Test name
Test status
Simulation time 45608024 ps
CPU time 0.66 seconds
Started Apr 21 12:23:03 PM PDT 24
Finished Apr 21 12:23:04 PM PDT 24
Peak memory 205200 kb
Host smart-244ac4c5-935b-4a77-a14f-b02869552798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330766643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.330766643
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2367236214
Short name T924
Test name
Test status
Simulation time 224970580 ps
CPU time 1.68 seconds
Started Apr 21 12:22:37 PM PDT 24
Finished Apr 21 12:22:39 PM PDT 24
Peak memory 204316 kb
Host smart-b3e39d04-eb9c-4600-a2d0-c914823d5055
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367236214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2367236214
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3377633310
Short name T994
Test name
Test status
Simulation time 255376703 ps
CPU time 2.45 seconds
Started Apr 21 12:23:34 PM PDT 24
Finished Apr 21 12:23:42 PM PDT 24
Peak memory 213332 kb
Host smart-4de89e04-4799-46d9-bb35-28e733303ad6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377633310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3377633310
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.178607750
Short name T1017
Test name
Test status
Simulation time 576303487 ps
CPU time 6.24 seconds
Started Apr 21 12:21:02 PM PDT 24
Finished Apr 21 12:21:08 PM PDT 24
Peak memory 214148 kb
Host smart-bbcffc78-8b63-491a-a94b-50a8c587ddc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178607750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.178607750
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.374843021
Short name T987
Test name
Test status
Simulation time 561174166 ps
CPU time 5.01 seconds
Started Apr 21 12:20:54 PM PDT 24
Finished Apr 21 12:21:01 PM PDT 24
Peak memory 213464 kb
Host smart-3b044b83-a5c9-48f3-827c-bf2e1ef1214e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374843021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.374843021
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.122922369
Short name T1060
Test name
Test status
Simulation time 64228428 ps
CPU time 3.32 seconds
Started Apr 21 12:23:05 PM PDT 24
Finished Apr 21 12:23:09 PM PDT 24
Peak memory 213844 kb
Host smart-8a57d706-f6b4-40cf-8111-b1b7baa0471b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122922369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.122922369
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1220847794
Short name T909
Test name
Test status
Simulation time 45879329 ps
CPU time 1.89 seconds
Started Apr 21 12:21:18 PM PDT 24
Finished Apr 21 12:21:20 PM PDT 24
Peak memory 213436 kb
Host smart-02d0cbb5-2ce9-4ded-b751-1747a8e4c065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220847794 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1220847794
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1913621334
Short name T961
Test name
Test status
Simulation time 50699255 ps
CPU time 1.11 seconds
Started Apr 21 12:22:59 PM PDT 24
Finished Apr 21 12:23:00 PM PDT 24
Peak memory 205180 kb
Host smart-a173542a-c986-4572-888f-51992fa576c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913621334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1913621334
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1502124426
Short name T986
Test name
Test status
Simulation time 6579371 ps
CPU time 0.67 seconds
Started Apr 21 12:22:53 PM PDT 24
Finished Apr 21 12:22:54 PM PDT 24
Peak memory 205204 kb
Host smart-39ac32e8-c179-4bb4-93b0-fc1245de8939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502124426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1502124426
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3644087694
Short name T146
Test name
Test status
Simulation time 101177210 ps
CPU time 3.69 seconds
Started Apr 21 12:22:37 PM PDT 24
Finished Apr 21 12:22:41 PM PDT 24
Peak memory 205648 kb
Host smart-5dbf738b-f1d4-4607-9803-7fc0afe1076c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644087694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3644087694
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1320509863
Short name T1039
Test name
Test status
Simulation time 180125878 ps
CPU time 4.15 seconds
Started Apr 21 12:18:37 PM PDT 24
Finished Apr 21 12:18:42 PM PDT 24
Peak memory 213660 kb
Host smart-7e60a5e0-53fe-497a-bbfa-4135cf9e5c7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320509863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1320509863
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2974344974
Short name T973
Test name
Test status
Simulation time 381389989 ps
CPU time 8.71 seconds
Started Apr 21 12:22:59 PM PDT 24
Finished Apr 21 12:23:08 PM PDT 24
Peak memory 213868 kb
Host smart-051841fc-7d7b-4a9c-936b-e8963b35b989
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974344974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2974344974
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3432776227
Short name T1005
Test name
Test status
Simulation time 140384455 ps
CPU time 2.76 seconds
Started Apr 21 12:22:59 PM PDT 24
Finished Apr 21 12:23:02 PM PDT 24
Peak memory 213576 kb
Host smart-84e032f6-4373-484c-bf36-585d0c947c46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432776227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3432776227
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3268708557
Short name T1015
Test name
Test status
Simulation time 22748902 ps
CPU time 1.51 seconds
Started Apr 21 12:21:17 PM PDT 24
Finished Apr 21 12:21:19 PM PDT 24
Peak memory 213152 kb
Host smart-4125769a-33c5-4f1b-8a83-5c2dd4cc2237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268708557 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3268708557
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1550320542
Short name T1004
Test name
Test status
Simulation time 12793171 ps
CPU time 1.18 seconds
Started Apr 21 12:23:00 PM PDT 24
Finished Apr 21 12:23:02 PM PDT 24
Peak memory 204696 kb
Host smart-da90d2f2-d7ea-45ce-97c5-be9097777d2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550320542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1550320542
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3974573896
Short name T1054
Test name
Test status
Simulation time 63701294 ps
CPU time 0.85 seconds
Started Apr 21 12:22:51 PM PDT 24
Finished Apr 21 12:22:53 PM PDT 24
Peak memory 204252 kb
Host smart-813e03ef-8350-4483-bb73-b12263fb29cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974573896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3974573896
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.901438774
Short name T1007
Test name
Test status
Simulation time 560127786 ps
CPU time 2.96 seconds
Started Apr 21 12:23:52 PM PDT 24
Finished Apr 21 12:23:56 PM PDT 24
Peak memory 205636 kb
Host smart-0459f74b-58e8-4adc-927d-2d9be3795b6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901438774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.901438774
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.388691557
Short name T1050
Test name
Test status
Simulation time 1657358707 ps
CPU time 4.97 seconds
Started Apr 21 12:22:47 PM PDT 24
Finished Apr 21 12:22:53 PM PDT 24
Peak memory 213364 kb
Host smart-33995589-4682-480e-a159-c413bf5e1f6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388691557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.388691557
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1959909067
Short name T112
Test name
Test status
Simulation time 1232095759 ps
CPU time 6.9 seconds
Started Apr 21 12:20:44 PM PDT 24
Finished Apr 21 12:20:51 PM PDT 24
Peak memory 214340 kb
Host smart-766c9730-5e85-4017-9c97-1174c15dfc8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959909067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1959909067
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1745820260
Short name T928
Test name
Test status
Simulation time 73333811 ps
CPU time 1.5 seconds
Started Apr 21 12:20:47 PM PDT 24
Finished Apr 21 12:20:49 PM PDT 24
Peak memory 213808 kb
Host smart-0edd0abd-69e9-4d9a-884c-f120f2256986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745820260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1745820260
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.999455229
Short name T993
Test name
Test status
Simulation time 87019619 ps
CPU time 1.83 seconds
Started Apr 21 12:17:58 PM PDT 24
Finished Apr 21 12:18:00 PM PDT 24
Peak memory 213484 kb
Host smart-7517ca03-b2f7-4547-9b83-62496d34bd26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999455229 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.999455229
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3210385639
Short name T1021
Test name
Test status
Simulation time 15456556 ps
CPU time 1.14 seconds
Started Apr 21 12:23:01 PM PDT 24
Finished Apr 21 12:23:03 PM PDT 24
Peak memory 204848 kb
Host smart-3ca93813-046f-4ec1-8c86-b61a062e96a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210385639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3210385639
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2061914245
Short name T974
Test name
Test status
Simulation time 21229797 ps
CPU time 0.75 seconds
Started Apr 21 12:23:17 PM PDT 24
Finished Apr 21 12:23:18 PM PDT 24
Peak memory 203496 kb
Host smart-5c9ca6ad-92ac-4128-a3da-fd73e6f131db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061914245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2061914245
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1159528949
Short name T1026
Test name
Test status
Simulation time 38983813 ps
CPU time 1.41 seconds
Started Apr 21 12:23:17 PM PDT 24
Finished Apr 21 12:23:19 PM PDT 24
Peak memory 203852 kb
Host smart-db7372b3-fcbb-483c-9156-360e86db7dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159528949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1159528949
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2268901429
Short name T992
Test name
Test status
Simulation time 1544664224 ps
CPU time 4.57 seconds
Started Apr 21 12:23:01 PM PDT 24
Finished Apr 21 12:23:06 PM PDT 24
Peak memory 213452 kb
Host smart-2adf166a-a6d3-47ce-9bbe-014d35ac2399
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268901429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2268901429
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1747145665
Short name T984
Test name
Test status
Simulation time 72207276 ps
CPU time 2.03 seconds
Started Apr 21 12:18:56 PM PDT 24
Finished Apr 21 12:18:58 PM PDT 24
Peak memory 222212 kb
Host smart-353b7fb5-0912-42c2-9021-e0e70727a6d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747145665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1747145665
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1704835938
Short name T180
Test name
Test status
Simulation time 586130925 ps
CPU time 4.8 seconds
Started Apr 21 12:23:48 PM PDT 24
Finished Apr 21 12:23:53 PM PDT 24
Peak memory 213672 kb
Host smart-baf75f56-ce2c-425c-9823-e5d30f24abb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704835938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1704835938
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2329190016
Short name T947
Test name
Test status
Simulation time 39486755 ps
CPU time 1.87 seconds
Started Apr 21 12:24:05 PM PDT 24
Finished Apr 21 12:24:07 PM PDT 24
Peak memory 213788 kb
Host smart-e8487a1a-bde9-41b2-b9c6-4a3f415c62a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329190016 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2329190016
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3795431477
Short name T1063
Test name
Test status
Simulation time 29269090 ps
CPU time 1.2 seconds
Started Apr 21 12:22:36 PM PDT 24
Finished Apr 21 12:22:38 PM PDT 24
Peak memory 205380 kb
Host smart-dd0b3554-3fe7-459b-acc8-fcc960f70a29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795431477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3795431477
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.246473836
Short name T1064
Test name
Test status
Simulation time 50421814 ps
CPU time 0.82 seconds
Started Apr 21 12:24:41 PM PDT 24
Finished Apr 21 12:24:42 PM PDT 24
Peak memory 205292 kb
Host smart-9a373d39-2f97-48c1-adcc-269a2dd60b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246473836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.246473836
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2343743235
Short name T148
Test name
Test status
Simulation time 80217226 ps
CPU time 3.17 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:54 PM PDT 24
Peak memory 205104 kb
Host smart-deddd7d2-17e5-4af8-9c88-d45472a7ea17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343743235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2343743235
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1773638149
Short name T1042
Test name
Test status
Simulation time 1902848158 ps
CPU time 5.45 seconds
Started Apr 21 12:23:17 PM PDT 24
Finished Apr 21 12:23:23 PM PDT 24
Peak memory 212740 kb
Host smart-09f096f5-13cb-4627-8014-60401d62564a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773638149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1773638149
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.269596652
Short name T1061
Test name
Test status
Simulation time 1097415471 ps
CPU time 5.04 seconds
Started Apr 21 12:23:01 PM PDT 24
Finished Apr 21 12:23:06 PM PDT 24
Peak memory 213512 kb
Host smart-2ac637b7-323f-4752-a0af-83a083147bfe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269596652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.269596652
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3978580513
Short name T981
Test name
Test status
Simulation time 354027134 ps
CPU time 5.59 seconds
Started Apr 21 12:21:22 PM PDT 24
Finished Apr 21 12:21:28 PM PDT 24
Peak memory 213824 kb
Host smart-2e2b2934-23ee-4a32-a61f-2806e16c9798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978580513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3978580513
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2809238998
Short name T1055
Test name
Test status
Simulation time 87610437 ps
CPU time 1.81 seconds
Started Apr 21 12:19:12 PM PDT 24
Finished Apr 21 12:19:14 PM PDT 24
Peak memory 213828 kb
Host smart-4c310339-4333-4ced-b42e-6bb939bd2c43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809238998 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2809238998
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2321045478
Short name T1000
Test name
Test status
Simulation time 10936373 ps
CPU time 0.99 seconds
Started Apr 21 12:21:57 PM PDT 24
Finished Apr 21 12:21:59 PM PDT 24
Peak memory 205348 kb
Host smart-28c08ae6-cd1d-4149-b4ea-ff24655dfb29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321045478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2321045478
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1506432065
Short name T1003
Test name
Test status
Simulation time 35703804 ps
CPU time 0.79 seconds
Started Apr 21 12:22:36 PM PDT 24
Finished Apr 21 12:22:38 PM PDT 24
Peak memory 204928 kb
Host smart-89141882-b6c0-48c5-a3dc-169fed1817fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506432065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1506432065
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2956206256
Short name T959
Test name
Test status
Simulation time 38949448 ps
CPU time 2.71 seconds
Started Apr 21 12:21:02 PM PDT 24
Finished Apr 21 12:21:05 PM PDT 24
Peak memory 205624 kb
Host smart-41257d44-f116-47e0-aa8f-38b235319d64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956206256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2956206256
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3961908356
Short name T120
Test name
Test status
Simulation time 53044098 ps
CPU time 2.22 seconds
Started Apr 21 12:24:04 PM PDT 24
Finished Apr 21 12:24:06 PM PDT 24
Peak memory 213732 kb
Host smart-78f85dbf-0644-4721-ba29-27c5efeacd7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961908356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3961908356
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2922128310
Short name T1046
Test name
Test status
Simulation time 2135070916 ps
CPU time 12.75 seconds
Started Apr 21 12:24:33 PM PDT 24
Finished Apr 21 12:24:46 PM PDT 24
Peak memory 214100 kb
Host smart-818eb5fb-0485-486d-9ce0-a1e736e5a5f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922128310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2922128310
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.924140326
Short name T927
Test name
Test status
Simulation time 50509674 ps
CPU time 1.89 seconds
Started Apr 21 12:24:03 PM PDT 24
Finished Apr 21 12:24:06 PM PDT 24
Peak memory 221092 kb
Host smart-b5876dcc-e0e3-4a18-b279-a6876bf5038b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924140326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.924140326
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3921072268
Short name T1052
Test name
Test status
Simulation time 189361106 ps
CPU time 1.95 seconds
Started Apr 21 12:22:57 PM PDT 24
Finished Apr 21 12:22:59 PM PDT 24
Peak memory 213040 kb
Host smart-5eca2266-1ed6-4d26-8646-5060b212b8e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921072268 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3921072268
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1867070422
Short name T945
Test name
Test status
Simulation time 31909668 ps
CPU time 1.86 seconds
Started Apr 21 12:18:57 PM PDT 24
Finished Apr 21 12:18:59 PM PDT 24
Peak memory 205608 kb
Host smart-ac149be8-513f-4644-8f39-90db11fa124f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867070422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1867070422
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2010737381
Short name T1029
Test name
Test status
Simulation time 15267665 ps
CPU time 0.7 seconds
Started Apr 21 12:20:54 PM PDT 24
Finished Apr 21 12:20:57 PM PDT 24
Peak memory 204976 kb
Host smart-c9993c4c-989f-4b8b-aa5e-ed0495adf412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010737381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2010737381
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4268648588
Short name T1012
Test name
Test status
Simulation time 90370877 ps
CPU time 3.59 seconds
Started Apr 21 12:23:47 PM PDT 24
Finished Apr 21 12:23:51 PM PDT 24
Peak memory 205096 kb
Host smart-6bc845b7-5b7e-4147-9c51-3a759ac37bdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268648588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.4268648588
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3933516506
Short name T969
Test name
Test status
Simulation time 4689238691 ps
CPU time 5.75 seconds
Started Apr 21 12:20:54 PM PDT 24
Finished Apr 21 12:21:02 PM PDT 24
Peak memory 213920 kb
Host smart-8e2b20ef-1ade-4e0e-8800-06fb37d9e89b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933516506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3933516506
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1249789550
Short name T1011
Test name
Test status
Simulation time 385505902 ps
CPU time 13.41 seconds
Started Apr 21 12:22:54 PM PDT 24
Finished Apr 21 12:23:09 PM PDT 24
Peak memory 213472 kb
Host smart-24286143-cccd-4d1b-9b34-047947f39684
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249789550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1249789550
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1965223824
Short name T988
Test name
Test status
Simulation time 110596248 ps
CPU time 3.51 seconds
Started Apr 21 12:20:53 PM PDT 24
Finished Apr 21 12:20:57 PM PDT 24
Peak memory 213296 kb
Host smart-315eca59-7871-45cf-87f7-0302894c42ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965223824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1965223824
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4234342825
Short name T1065
Test name
Test status
Simulation time 115764210 ps
CPU time 3.63 seconds
Started Apr 21 12:20:53 PM PDT 24
Finished Apr 21 12:20:57 PM PDT 24
Peak memory 213088 kb
Host smart-d39f0fca-bae3-4dfe-afe1-4512346ab758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234342825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.4234342825
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1291956622
Short name T915
Test name
Test status
Simulation time 272611181 ps
CPU time 3.97 seconds
Started Apr 21 12:21:46 PM PDT 24
Finished Apr 21 12:21:50 PM PDT 24
Peak memory 205576 kb
Host smart-8604c37e-5f48-4e6b-8b74-8259a18d394e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291956622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
291956622
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.23525441
Short name T918
Test name
Test status
Simulation time 497502894 ps
CPU time 5.93 seconds
Started Apr 21 12:23:39 PM PDT 24
Finished Apr 21 12:23:45 PM PDT 24
Peak memory 205588 kb
Host smart-0c5170df-0857-46aa-9cd0-d1775a2dc3f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23525441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.23525441
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.203872773
Short name T1020
Test name
Test status
Simulation time 51440351 ps
CPU time 1.19 seconds
Started Apr 21 12:22:03 PM PDT 24
Finished Apr 21 12:22:04 PM PDT 24
Peak memory 205660 kb
Host smart-d583e28e-e144-49a9-9c7a-bd97fd01a2c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203872773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.203872773
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4194807371
Short name T1030
Test name
Test status
Simulation time 162585353 ps
CPU time 1.76 seconds
Started Apr 21 12:21:53 PM PDT 24
Finished Apr 21 12:21:55 PM PDT 24
Peak memory 213812 kb
Host smart-0c74fcc7-40b5-45cf-8207-26af55c53575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194807371 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4194807371
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2637806466
Short name T940
Test name
Test status
Simulation time 219526082 ps
CPU time 0.96 seconds
Started Apr 21 12:22:48 PM PDT 24
Finished Apr 21 12:22:50 PM PDT 24
Peak memory 204980 kb
Host smart-965b16c8-518f-4afa-bff4-0bbc92f51c83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637806466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2637806466
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.185138712
Short name T1028
Test name
Test status
Simulation time 9868297 ps
CPU time 0.8 seconds
Started Apr 21 12:23:44 PM PDT 24
Finished Apr 21 12:23:55 PM PDT 24
Peak memory 205292 kb
Host smart-32483a99-2ec5-44fe-bdec-ae24c78553c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185138712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.185138712
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3738481160
Short name T922
Test name
Test status
Simulation time 118512285 ps
CPU time 2.66 seconds
Started Apr 21 12:21:12 PM PDT 24
Finished Apr 21 12:21:15 PM PDT 24
Peak memory 205468 kb
Host smart-497d3080-94a0-438f-bc08-c9c24e2581f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738481160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3738481160
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2310705530
Short name T1035
Test name
Test status
Simulation time 276642669 ps
CPU time 2.62 seconds
Started Apr 21 12:22:52 PM PDT 24
Finished Apr 21 12:22:56 PM PDT 24
Peak memory 214036 kb
Host smart-16283b36-29f3-409f-9f06-25172e9acc26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310705530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2310705530
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2454190216
Short name T121
Test name
Test status
Simulation time 1048667849 ps
CPU time 4.94 seconds
Started Apr 21 12:17:59 PM PDT 24
Finished Apr 21 12:18:04 PM PDT 24
Peak memory 214488 kb
Host smart-5fdb30b7-df1b-4060-bec2-a75ff7dcc4cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454190216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2454190216
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3849790749
Short name T1051
Test name
Test status
Simulation time 128015799 ps
CPU time 1.89 seconds
Started Apr 21 12:22:35 PM PDT 24
Finished Apr 21 12:22:38 PM PDT 24
Peak memory 212504 kb
Host smart-feebb072-e9c9-4813-a0f3-500a51185136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849790749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3849790749
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.495147062
Short name T937
Test name
Test status
Simulation time 16912812 ps
CPU time 0.77 seconds
Started Apr 21 12:18:42 PM PDT 24
Finished Apr 21 12:18:43 PM PDT 24
Peak memory 205292 kb
Host smart-fc1a636f-e7a1-44cf-8e7b-963c2d6aa03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495147062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.495147062
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2116866329
Short name T902
Test name
Test status
Simulation time 63781339 ps
CPU time 0.75 seconds
Started Apr 21 12:22:37 PM PDT 24
Finished Apr 21 12:22:39 PM PDT 24
Peak memory 205048 kb
Host smart-e92b8c33-96eb-4a3b-8403-cb19c813b96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116866329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2116866329
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3206037514
Short name T953
Test name
Test status
Simulation time 9935100 ps
CPU time 0.83 seconds
Started Apr 21 12:22:37 PM PDT 24
Finished Apr 21 12:22:38 PM PDT 24
Peak memory 203908 kb
Host smart-a2c3216a-3e9c-4700-a834-d62aa4485daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206037514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3206037514
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2514358680
Short name T919
Test name
Test status
Simulation time 25486303 ps
CPU time 0.77 seconds
Started Apr 21 12:22:36 PM PDT 24
Finished Apr 21 12:22:37 PM PDT 24
Peak memory 205060 kb
Host smart-5e6a1ebf-bc60-440d-a8e4-413d63022189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514358680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2514358680
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2975037719
Short name T991
Test name
Test status
Simulation time 34826426 ps
CPU time 0.7 seconds
Started Apr 21 12:22:41 PM PDT 24
Finished Apr 21 12:22:43 PM PDT 24
Peak memory 205056 kb
Host smart-9ed089d9-883a-42ad-8609-6661cd4a89a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975037719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2975037719
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.261810568
Short name T907
Test name
Test status
Simulation time 39890884 ps
CPU time 0.76 seconds
Started Apr 21 12:22:40 PM PDT 24
Finished Apr 21 12:22:42 PM PDT 24
Peak memory 204296 kb
Host smart-204821cb-a653-4dfc-a049-1a450c4638a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261810568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.261810568
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1208899747
Short name T939
Test name
Test status
Simulation time 31536883 ps
CPU time 0.68 seconds
Started Apr 21 12:21:19 PM PDT 24
Finished Apr 21 12:21:20 PM PDT 24
Peak memory 205308 kb
Host smart-8bf7eabe-af97-4eb6-b5fd-f3ec372c2d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208899747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1208899747
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.664493148
Short name T935
Test name
Test status
Simulation time 12250154 ps
CPU time 0.67 seconds
Started Apr 21 12:21:44 PM PDT 24
Finished Apr 21 12:21:45 PM PDT 24
Peak memory 205316 kb
Host smart-e7eda58e-0571-4108-a941-f53f9aa498c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664493148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.664493148
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2989595536
Short name T900
Test name
Test status
Simulation time 37108026 ps
CPU time 0.75 seconds
Started Apr 21 12:18:24 PM PDT 24
Finished Apr 21 12:18:25 PM PDT 24
Peak memory 205632 kb
Host smart-b1473ba9-a395-4e83-a2dd-56326087b6dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989595536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2989595536
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1747129279
Short name T1014
Test name
Test status
Simulation time 27686111 ps
CPU time 0.82 seconds
Started Apr 21 12:18:11 PM PDT 24
Finished Apr 21 12:18:12 PM PDT 24
Peak memory 204780 kb
Host smart-9a9e1f48-34f5-4691-b652-406d24398001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747129279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1747129279
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.365623302
Short name T1019
Test name
Test status
Simulation time 551859668 ps
CPU time 8.63 seconds
Started Apr 21 12:22:52 PM PDT 24
Finished Apr 21 12:23:02 PM PDT 24
Peak memory 205576 kb
Host smart-524a90ec-b9f8-4487-8f9c-edce6203e836
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365623302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.365623302
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2183350001
Short name T1044
Test name
Test status
Simulation time 440735289 ps
CPU time 6.41 seconds
Started Apr 21 12:18:10 PM PDT 24
Finished Apr 21 12:18:16 PM PDT 24
Peak memory 205860 kb
Host smart-088354c6-acda-42a6-a642-8274edc67cd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183350001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
183350001
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3850616334
Short name T906
Test name
Test status
Simulation time 61772810 ps
CPU time 1.02 seconds
Started Apr 21 12:23:38 PM PDT 24
Finished Apr 21 12:23:40 PM PDT 24
Peak memory 204748 kb
Host smart-20ce96b7-a108-4417-bf6a-1031f16cd54a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850616334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
850616334
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1304419315
Short name T1071
Test name
Test status
Simulation time 49512160 ps
CPU time 1.46 seconds
Started Apr 21 12:23:37 PM PDT 24
Finished Apr 21 12:23:39 PM PDT 24
Peak memory 213796 kb
Host smart-18846ff6-0fa1-4960-a67a-5d508a3dae18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304419315 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1304419315
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.889404755
Short name T978
Test name
Test status
Simulation time 22010070 ps
CPU time 1.06 seconds
Started Apr 21 12:19:04 PM PDT 24
Finished Apr 21 12:19:06 PM PDT 24
Peak memory 204988 kb
Host smart-2a677c5b-dda7-4507-a659-7ce650b641e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889404755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.889404755
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2349066312
Short name T1067
Test name
Test status
Simulation time 17501310 ps
CPU time 0.7 seconds
Started Apr 21 12:21:52 PM PDT 24
Finished Apr 21 12:21:53 PM PDT 24
Peak memory 205264 kb
Host smart-c088f570-d100-4aea-9dc7-2f3b075cce37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349066312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2349066312
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.186006460
Short name T1045
Test name
Test status
Simulation time 344182000 ps
CPU time 2.47 seconds
Started Apr 21 12:23:56 PM PDT 24
Finished Apr 21 12:23:59 PM PDT 24
Peak memory 204716 kb
Host smart-ce550d4c-b2bc-432f-ab8d-98a57bcac206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186006460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.186006460
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2616804226
Short name T1059
Test name
Test status
Simulation time 213015468 ps
CPU time 2.58 seconds
Started Apr 21 12:20:05 PM PDT 24
Finished Apr 21 12:20:08 PM PDT 24
Peak memory 214340 kb
Host smart-d49d8ed2-114c-4ceb-83f3-7d702d0a1378
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616804226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2616804226
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1079103960
Short name T1057
Test name
Test status
Simulation time 466805633 ps
CPU time 15.21 seconds
Started Apr 21 12:23:36 PM PDT 24
Finished Apr 21 12:23:52 PM PDT 24
Peak memory 213300 kb
Host smart-8d874f31-1a3c-48bf-8e50-22c784c1143d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079103960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1079103960
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3499243683
Short name T1036
Test name
Test status
Simulation time 48804659 ps
CPU time 3.01 seconds
Started Apr 21 12:21:46 PM PDT 24
Finished Apr 21 12:21:49 PM PDT 24
Peak memory 213716 kb
Host smart-b3599187-6b75-4de1-8918-2d007ff7bb99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499243683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3499243683
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2034959721
Short name T1070
Test name
Test status
Simulation time 912483001 ps
CPU time 9.01 seconds
Started Apr 21 12:18:33 PM PDT 24
Finished Apr 21 12:18:45 PM PDT 24
Peak memory 209240 kb
Host smart-35094567-2144-4849-b407-8f32ce4e5684
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034959721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2034959721
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.599745129
Short name T1066
Test name
Test status
Simulation time 19667098 ps
CPU time 0.77 seconds
Started Apr 21 12:18:40 PM PDT 24
Finished Apr 21 12:18:41 PM PDT 24
Peak memory 205232 kb
Host smart-f6436ec5-a67b-4bbc-b988-78a6297cd3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599745129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.599745129
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3271792254
Short name T911
Test name
Test status
Simulation time 34224240 ps
CPU time 0.82 seconds
Started Apr 21 12:22:46 PM PDT 24
Finished Apr 21 12:22:49 PM PDT 24
Peak memory 204496 kb
Host smart-cf1ee0ed-c14c-41f0-a8e0-9a896c57250d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271792254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3271792254
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.331343812
Short name T903
Test name
Test status
Simulation time 11718538 ps
CPU time 0.94 seconds
Started Apr 21 12:22:46 PM PDT 24
Finished Apr 21 12:22:49 PM PDT 24
Peak memory 204588 kb
Host smart-f0c3fae8-3496-4057-ac43-c4746ed43834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331343812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.331343812
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3562101657
Short name T944
Test name
Test status
Simulation time 16555160 ps
CPU time 0.79 seconds
Started Apr 21 12:22:33 PM PDT 24
Finished Apr 21 12:22:35 PM PDT 24
Peak memory 204012 kb
Host smart-5ce9af44-5936-4d81-8297-c39667e952be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562101657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3562101657
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3327794299
Short name T966
Test name
Test status
Simulation time 20826733 ps
CPU time 0.78 seconds
Started Apr 21 12:22:52 PM PDT 24
Finished Apr 21 12:22:53 PM PDT 24
Peak memory 204996 kb
Host smart-b49b554b-1181-401f-8746-731b019308ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327794299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3327794299
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2775764535
Short name T929
Test name
Test status
Simulation time 23019738 ps
CPU time 0.87 seconds
Started Apr 21 12:18:28 PM PDT 24
Finished Apr 21 12:18:30 PM PDT 24
Peak memory 205292 kb
Host smart-d13bf67f-2fd0-4130-a93b-47f90859ca70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775764535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2775764535
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3804438110
Short name T1022
Test name
Test status
Simulation time 56965991 ps
CPU time 0.72 seconds
Started Apr 21 12:22:47 PM PDT 24
Finished Apr 21 12:22:49 PM PDT 24
Peak memory 204840 kb
Host smart-988cd69c-14ee-44aa-a0b5-67621129bfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804438110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3804438110
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1634143772
Short name T904
Test name
Test status
Simulation time 29340592 ps
CPU time 0.7 seconds
Started Apr 21 12:23:27 PM PDT 24
Finished Apr 21 12:23:29 PM PDT 24
Peak memory 204376 kb
Host smart-b3c8042b-b7c0-42fd-854c-d35faf631f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634143772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1634143772
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3849120214
Short name T930
Test name
Test status
Simulation time 11993442 ps
CPU time 0.84 seconds
Started Apr 21 12:22:34 PM PDT 24
Finished Apr 21 12:22:36 PM PDT 24
Peak memory 204916 kb
Host smart-5da18637-1ec3-43a3-8181-34acea5a65ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849120214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3849120214
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2468482980
Short name T1049
Test name
Test status
Simulation time 52840029 ps
CPU time 0.8 seconds
Started Apr 21 12:18:30 PM PDT 24
Finished Apr 21 12:18:32 PM PDT 24
Peak memory 205220 kb
Host smart-a2956158-5987-4675-b5f5-0c148fa1001d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468482980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2468482980
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3019691868
Short name T914
Test name
Test status
Simulation time 1447439840 ps
CPU time 14.18 seconds
Started Apr 21 12:21:56 PM PDT 24
Finished Apr 21 12:22:11 PM PDT 24
Peak memory 205520 kb
Host smart-680b403a-7a7f-4a31-86f8-3b5ec71f7db0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019691868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
019691868
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1186390997
Short name T1048
Test name
Test status
Simulation time 1332527632 ps
CPU time 18.73 seconds
Started Apr 21 12:23:01 PM PDT 24
Finished Apr 21 12:23:20 PM PDT 24
Peak memory 205556 kb
Host smart-a7d89b19-26e7-4404-bb82-81e1e948c678
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186390997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
186390997
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.338601355
Short name T943
Test name
Test status
Simulation time 41529687 ps
CPU time 1.39 seconds
Started Apr 21 12:22:39 PM PDT 24
Finished Apr 21 12:22:41 PM PDT 24
Peak memory 205464 kb
Host smart-ef3c1eb0-22ad-43ce-9a46-3585785e3287
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338601355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.338601355
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2704635095
Short name T996
Test name
Test status
Simulation time 59233288 ps
CPU time 1.07 seconds
Started Apr 21 12:17:55 PM PDT 24
Finished Apr 21 12:17:56 PM PDT 24
Peak memory 213860 kb
Host smart-f9adb56d-ea3d-46c7-bf22-a7df0a215c48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704635095 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2704635095
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2348025948
Short name T980
Test name
Test status
Simulation time 56206109 ps
CPU time 1.06 seconds
Started Apr 21 12:21:15 PM PDT 24
Finished Apr 21 12:21:16 PM PDT 24
Peak memory 205620 kb
Host smart-86b6b1dd-8770-4f36-8caf-ac441735b647
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348025948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2348025948
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2680383048
Short name T957
Test name
Test status
Simulation time 15976831 ps
CPU time 0.85 seconds
Started Apr 21 12:19:47 PM PDT 24
Finished Apr 21 12:19:48 PM PDT 24
Peak memory 205316 kb
Host smart-7bca04ee-7c39-41ab-9765-15e95e9847ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680383048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2680383048
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.701309639
Short name T1002
Test name
Test status
Simulation time 107811150 ps
CPU time 3.84 seconds
Started Apr 21 12:19:14 PM PDT 24
Finished Apr 21 12:19:18 PM PDT 24
Peak memory 205840 kb
Host smart-0d3dd6f6-2253-48bd-8099-ba9e646baf31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701309639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.701309639
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1445134360
Short name T1034
Test name
Test status
Simulation time 534891937 ps
CPU time 7.16 seconds
Started Apr 21 12:22:51 PM PDT 24
Finished Apr 21 12:22:59 PM PDT 24
Peak memory 213924 kb
Host smart-10c4ad77-8523-44c3-948f-da6c635bac92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445134360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1445134360
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.249615338
Short name T118
Test name
Test status
Simulation time 5085892773 ps
CPU time 12.45 seconds
Started Apr 21 12:20:51 PM PDT 24
Finished Apr 21 12:21:04 PM PDT 24
Peak memory 212704 kb
Host smart-de1240b8-6d5c-47a8-a70e-025cba96b37b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249615338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.249615338
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3908255751
Short name T971
Test name
Test status
Simulation time 46660476 ps
CPU time 1.9 seconds
Started Apr 21 12:18:03 PM PDT 24
Finished Apr 21 12:18:05 PM PDT 24
Peak memory 217044 kb
Host smart-9fe5ab8b-f4de-4deb-81bf-c470634896f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908255751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3908255751
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1883014966
Short name T912
Test name
Test status
Simulation time 595229409 ps
CPU time 4.33 seconds
Started Apr 21 12:20:51 PM PDT 24
Finished Apr 21 12:20:56 PM PDT 24
Peak memory 207224 kb
Host smart-419bd889-e7df-4d8b-9a4b-a2e45082e219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883014966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1883014966
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1262497766
Short name T985
Test name
Test status
Simulation time 39701914 ps
CPU time 0.74 seconds
Started Apr 21 12:22:51 PM PDT 24
Finished Apr 21 12:22:53 PM PDT 24
Peak memory 204240 kb
Host smart-ab7d43e9-8a70-4e55-9751-d18ce9355806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262497766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1262497766
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3158741864
Short name T926
Test name
Test status
Simulation time 27630899 ps
CPU time 0.76 seconds
Started Apr 21 12:23:51 PM PDT 24
Finished Apr 21 12:23:52 PM PDT 24
Peak memory 204340 kb
Host smart-e67634d1-ee2a-4d33-ac60-84f745e39b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158741864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3158741864
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2048214157
Short name T976
Test name
Test status
Simulation time 20442823 ps
CPU time 0.93 seconds
Started Apr 21 12:23:51 PM PDT 24
Finished Apr 21 12:23:52 PM PDT 24
Peak memory 204592 kb
Host smart-447098b0-9e57-42c8-85b7-84e418a16594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048214157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2048214157
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.162501723
Short name T999
Test name
Test status
Simulation time 13269904 ps
CPU time 0.75 seconds
Started Apr 21 12:19:04 PM PDT 24
Finished Apr 21 12:19:05 PM PDT 24
Peak memory 205296 kb
Host smart-7d8fa5c7-120d-40aa-b8dc-a48457546572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162501723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.162501723
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3140570646
Short name T990
Test name
Test status
Simulation time 10529926 ps
CPU time 0.7 seconds
Started Apr 21 12:21:44 PM PDT 24
Finished Apr 21 12:21:45 PM PDT 24
Peak memory 205324 kb
Host smart-7943b6e7-17d3-4bed-af1b-7e31dffb07a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140570646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3140570646
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3945130605
Short name T1053
Test name
Test status
Simulation time 17126417 ps
CPU time 0.68 seconds
Started Apr 21 12:23:14 PM PDT 24
Finished Apr 21 12:23:16 PM PDT 24
Peak memory 204744 kb
Host smart-7b7c4367-ec1a-4895-8eba-e7e1534eddc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945130605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3945130605
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2098315416
Short name T933
Test name
Test status
Simulation time 48117777 ps
CPU time 0.71 seconds
Started Apr 21 12:19:42 PM PDT 24
Finished Apr 21 12:19:43 PM PDT 24
Peak memory 205632 kb
Host smart-f36b221a-921a-4dd1-92e7-729e698c4708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098315416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2098315416
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4003707028
Short name T983
Test name
Test status
Simulation time 23932117 ps
CPU time 0.88 seconds
Started Apr 21 12:24:03 PM PDT 24
Finished Apr 21 12:24:05 PM PDT 24
Peak memory 204520 kb
Host smart-e8bc66cb-1e48-4766-a9a0-a975af63ed29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003707028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4003707028
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2485755193
Short name T964
Test name
Test status
Simulation time 26653781 ps
CPU time 0.75 seconds
Started Apr 21 12:23:02 PM PDT 24
Finished Apr 21 12:23:04 PM PDT 24
Peak memory 205316 kb
Host smart-a7daef8d-ac37-4ba1-a248-e00b94f58a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485755193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2485755193
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1611677219
Short name T1027
Test name
Test status
Simulation time 32522559 ps
CPU time 0.77 seconds
Started Apr 21 12:23:10 PM PDT 24
Finished Apr 21 12:23:11 PM PDT 24
Peak memory 205288 kb
Host smart-fcb4cc2e-b45c-43a0-8356-4cc31c129a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611677219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1611677219
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.7103798
Short name T932
Test name
Test status
Simulation time 89560285 ps
CPU time 1.42 seconds
Started Apr 21 12:23:47 PM PDT 24
Finished Apr 21 12:23:49 PM PDT 24
Peak memory 213084 kb
Host smart-501fd8a9-8b45-4ba8-9b01-1be59ed961f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7103798 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.7103798
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.398829351
Short name T956
Test name
Test status
Simulation time 37243061 ps
CPU time 0.98 seconds
Started Apr 21 12:19:27 PM PDT 24
Finished Apr 21 12:19:29 PM PDT 24
Peak memory 204928 kb
Host smart-79dd47dd-7a4f-4a98-9bff-a84d1a4e84e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398829351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.398829351
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1148440882
Short name T946
Test name
Test status
Simulation time 18795662 ps
CPU time 0.75 seconds
Started Apr 21 12:22:37 PM PDT 24
Finished Apr 21 12:22:39 PM PDT 24
Peak memory 204320 kb
Host smart-f2bd7f91-6bc0-429f-8ca1-79394a8c6f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148440882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1148440882
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1603089106
Short name T149
Test name
Test status
Simulation time 190762861 ps
CPU time 1.82 seconds
Started Apr 21 12:22:46 PM PDT 24
Finished Apr 21 12:22:50 PM PDT 24
Peak memory 204500 kb
Host smart-d1b2559d-0093-4418-a173-aa20b0bcba97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603089106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1603089106
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.936288623
Short name T968
Test name
Test status
Simulation time 173809058 ps
CPU time 3.13 seconds
Started Apr 21 12:20:52 PM PDT 24
Finished Apr 21 12:20:55 PM PDT 24
Peak memory 213708 kb
Host smart-85093520-09c3-4fb7-9d92-34ff4341baef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936288623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.936288623
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1286929210
Short name T1075
Test name
Test status
Simulation time 300741114 ps
CPU time 4.47 seconds
Started Apr 21 12:24:13 PM PDT 24
Finished Apr 21 12:24:18 PM PDT 24
Peak memory 212596 kb
Host smart-7e5b2da6-d951-4a23-86d2-ea175f242013
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286929210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1286929210
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.907358381
Short name T925
Test name
Test status
Simulation time 172729261 ps
CPU time 1.6 seconds
Started Apr 21 12:22:38 PM PDT 24
Finished Apr 21 12:22:41 PM PDT 24
Peak memory 213576 kb
Host smart-cd4a7a7f-c6a5-42eb-8d9f-ca9eb44d236c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907358381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.907358381
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2317374337
Short name T1001
Test name
Test status
Simulation time 50599244 ps
CPU time 2 seconds
Started Apr 21 12:19:27 PM PDT 24
Finished Apr 21 12:19:30 PM PDT 24
Peak memory 213552 kb
Host smart-1f35fafe-f254-4e58-b4a3-fd52deaf62f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317374337 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2317374337
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1113245413
Short name T1018
Test name
Test status
Simulation time 94740323 ps
CPU time 1.24 seconds
Started Apr 21 12:22:36 PM PDT 24
Finished Apr 21 12:22:38 PM PDT 24
Peak memory 205260 kb
Host smart-0a200a68-1539-4f74-847e-b52b1393402c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113245413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1113245413
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4053872861
Short name T913
Test name
Test status
Simulation time 9459228 ps
CPU time 0.82 seconds
Started Apr 21 12:22:46 PM PDT 24
Finished Apr 21 12:22:49 PM PDT 24
Peak memory 204184 kb
Host smart-ade63717-0941-4a94-a9d5-52b2e306469d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053872861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4053872861
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2626596427
Short name T1009
Test name
Test status
Simulation time 61512375 ps
CPU time 2.22 seconds
Started Apr 21 12:22:49 PM PDT 24
Finished Apr 21 12:22:52 PM PDT 24
Peak memory 205268 kb
Host smart-7845e762-fdaa-4c63-8d7c-c218352ef058
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626596427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2626596427
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3060550340
Short name T1069
Test name
Test status
Simulation time 220548415 ps
CPU time 5.07 seconds
Started Apr 21 12:21:21 PM PDT 24
Finished Apr 21 12:21:26 PM PDT 24
Peak memory 214044 kb
Host smart-67dd8ee3-3a6f-443a-9c09-a8bc343d9b43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060550340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3060550340
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4068307214
Short name T901
Test name
Test status
Simulation time 111093087 ps
CPU time 2.61 seconds
Started Apr 21 12:22:48 PM PDT 24
Finished Apr 21 12:22:52 PM PDT 24
Peak memory 211992 kb
Host smart-759de0dc-fd95-480c-a866-aa289bcc0556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068307214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4068307214
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1420735522
Short name T159
Test name
Test status
Simulation time 397429085 ps
CPU time 4.27 seconds
Started Apr 21 12:20:51 PM PDT 24
Finished Apr 21 12:20:56 PM PDT 24
Peak memory 212284 kb
Host smart-ff8e535b-3893-4a7c-b5f9-d7b27b0a0cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420735522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1420735522
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2623233094
Short name T1032
Test name
Test status
Simulation time 183706684 ps
CPU time 1.75 seconds
Started Apr 21 12:19:30 PM PDT 24
Finished Apr 21 12:19:32 PM PDT 24
Peak memory 213796 kb
Host smart-2dcdc0fb-705e-4e4f-a836-77eaf366c994
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623233094 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2623233094
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3841170835
Short name T1038
Test name
Test status
Simulation time 106065041 ps
CPU time 1.14 seconds
Started Apr 21 12:21:29 PM PDT 24
Finished Apr 21 12:21:30 PM PDT 24
Peak memory 205592 kb
Host smart-b96eadd7-06d6-4fdc-b96d-b02f1c81332a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841170835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3841170835
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1158246600
Short name T972
Test name
Test status
Simulation time 30922877 ps
CPU time 0.68 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:52 PM PDT 24
Peak memory 204808 kb
Host smart-61952df6-bb4b-44b2-8aa2-e5af9e28370a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158246600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1158246600
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3267459312
Short name T975
Test name
Test status
Simulation time 207092463 ps
CPU time 3.87 seconds
Started Apr 21 12:23:00 PM PDT 24
Finished Apr 21 12:23:04 PM PDT 24
Peak memory 205552 kb
Host smart-29d8ce41-70c1-4006-a922-a4e61c19d72c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267459312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3267459312
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3841414773
Short name T958
Test name
Test status
Simulation time 1148738235 ps
CPU time 6.44 seconds
Started Apr 21 12:22:49 PM PDT 24
Finished Apr 21 12:22:56 PM PDT 24
Peak memory 213756 kb
Host smart-5bfbafa1-943c-44d2-a362-041a1bc8b18d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841414773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3841414773
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2711689485
Short name T1025
Test name
Test status
Simulation time 797497770 ps
CPU time 6.68 seconds
Started Apr 21 12:22:48 PM PDT 24
Finished Apr 21 12:22:56 PM PDT 24
Peak memory 212340 kb
Host smart-a5635523-e588-402b-80ea-41ca419f41e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711689485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2711689485
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3048311961
Short name T962
Test name
Test status
Simulation time 171532539 ps
CPU time 2.67 seconds
Started Apr 21 12:22:38 PM PDT 24
Finished Apr 21 12:22:41 PM PDT 24
Peak memory 213592 kb
Host smart-1c2c67b3-2af7-4ba7-b553-870df65bbb58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048311961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3048311961
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2499643444
Short name T967
Test name
Test status
Simulation time 192180016 ps
CPU time 1.62 seconds
Started Apr 21 12:21:44 PM PDT 24
Finished Apr 21 12:21:47 PM PDT 24
Peak memory 213828 kb
Host smart-51a2053e-dc2f-4906-a303-e7acd5d72728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499643444 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2499643444
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3214508474
Short name T147
Test name
Test status
Simulation time 186349384 ps
CPU time 1.21 seconds
Started Apr 21 12:22:49 PM PDT 24
Finished Apr 21 12:22:51 PM PDT 24
Peak memory 205312 kb
Host smart-3fc09a22-d4df-4884-9b4e-1668391aafa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214508474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3214508474
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2167469345
Short name T910
Test name
Test status
Simulation time 33859688 ps
CPU time 0.8 seconds
Started Apr 21 12:22:48 PM PDT 24
Finished Apr 21 12:22:50 PM PDT 24
Peak memory 203268 kb
Host smart-4e2affbd-fcd1-4c75-ac69-338580e5b1de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167469345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2167469345
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.761131695
Short name T150
Test name
Test status
Simulation time 25867635 ps
CPU time 1.76 seconds
Started Apr 21 12:19:17 PM PDT 24
Finished Apr 21 12:19:19 PM PDT 24
Peak memory 205152 kb
Host smart-c0ff0465-d15d-4419-b5d9-7d660483c035
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761131695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.761131695
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2740664920
Short name T955
Test name
Test status
Simulation time 148803346 ps
CPU time 3.45 seconds
Started Apr 21 12:21:48 PM PDT 24
Finished Apr 21 12:21:52 PM PDT 24
Peak memory 214032 kb
Host smart-f9396c4c-f469-444e-b9ce-1207a6a26bb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740664920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2740664920
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.55520206
Short name T1068
Test name
Test status
Simulation time 157127817 ps
CPU time 6.24 seconds
Started Apr 21 12:22:35 PM PDT 24
Finished Apr 21 12:22:43 PM PDT 24
Peak memory 211988 kb
Host smart-c7d1d123-4c7f-4182-9daf-4489157fdc17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55520206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.55520206
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1313373255
Short name T1037
Test name
Test status
Simulation time 111922391 ps
CPU time 4.54 seconds
Started Apr 21 12:19:45 PM PDT 24
Finished Apr 21 12:19:50 PM PDT 24
Peak memory 216872 kb
Host smart-397e17b1-c95b-4d0d-9065-cd62af627338
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313373255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1313373255
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1784490867
Short name T916
Test name
Test status
Simulation time 31102275 ps
CPU time 1.18 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:52 PM PDT 24
Peak memory 203680 kb
Host smart-a31953a8-cedf-4054-a598-ff9d517d4de4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784490867 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1784490867
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4139997431
Short name T1058
Test name
Test status
Simulation time 69059126 ps
CPU time 0.93 seconds
Started Apr 21 12:23:47 PM PDT 24
Finished Apr 21 12:23:48 PM PDT 24
Peak memory 205044 kb
Host smart-3acf7640-b66a-4521-962d-ca60b9de0a95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139997431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4139997431
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.137217623
Short name T1056
Test name
Test status
Simulation time 27818408 ps
CPU time 0.7 seconds
Started Apr 21 12:22:50 PM PDT 24
Finished Apr 21 12:22:52 PM PDT 24
Peak memory 204756 kb
Host smart-609461d5-3667-4ece-b3c1-3165958f1c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137217623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.137217623
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1832953368
Short name T145
Test name
Test status
Simulation time 463978047 ps
CPU time 2.75 seconds
Started Apr 21 12:23:00 PM PDT 24
Finished Apr 21 12:23:03 PM PDT 24
Peak memory 205480 kb
Host smart-662b10e1-8862-4de3-8c8d-8e3cc8c1af49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832953368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1832953368
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3464625331
Short name T989
Test name
Test status
Simulation time 721826276 ps
CPU time 4.46 seconds
Started Apr 21 12:23:02 PM PDT 24
Finished Apr 21 12:23:07 PM PDT 24
Peak memory 218876 kb
Host smart-965fced2-13c5-4f2b-8062-2c23491a81e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464625331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3464625331
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1299666422
Short name T1072
Test name
Test status
Simulation time 480838513 ps
CPU time 4.66 seconds
Started Apr 21 12:22:48 PM PDT 24
Finished Apr 21 12:22:54 PM PDT 24
Peak memory 218404 kb
Host smart-a738d59f-7fa3-48f4-a07b-8e83f6a60e4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299666422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1299666422
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.752650111
Short name T1047
Test name
Test status
Simulation time 81725077 ps
CPU time 1.98 seconds
Started Apr 21 12:21:30 PM PDT 24
Finished Apr 21 12:21:32 PM PDT 24
Peak memory 213732 kb
Host smart-e20b3d28-72e4-4f73-b329-b8e66617114c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752650111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.752650111
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2775234624
Short name T1033
Test name
Test status
Simulation time 628324660 ps
CPU time 4.94 seconds
Started Apr 21 12:22:35 PM PDT 24
Finished Apr 21 12:22:42 PM PDT 24
Peak memory 211556 kb
Host smart-e5d43984-78b8-4c52-b529-a07779561be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775234624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2775234624
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1689503794
Short name T571
Test name
Test status
Simulation time 12770930 ps
CPU time 0.78 seconds
Started Apr 21 12:24:36 PM PDT 24
Finished Apr 21 12:24:37 PM PDT 24
Peak memory 205716 kb
Host smart-abaa7615-37c7-4423-a8d6-0ca71d9e20eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689503794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1689503794
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2943579137
Short name T9
Test name
Test status
Simulation time 186019508 ps
CPU time 2.81 seconds
Started Apr 21 12:24:41 PM PDT 24
Finished Apr 21 12:24:44 PM PDT 24
Peak memory 208080 kb
Host smart-1a60a507-a544-493c-89f3-a165e3f0e691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943579137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2943579137
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.703999311
Short name T264
Test name
Test status
Simulation time 32965964 ps
CPU time 2.38 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 214020 kb
Host smart-e5bd717d-1a7f-48a5-ac5d-cd35f142192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703999311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.703999311
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2105114629
Short name T851
Test name
Test status
Simulation time 361439439 ps
CPU time 4.91 seconds
Started Apr 21 12:24:41 PM PDT 24
Finished Apr 21 12:24:46 PM PDT 24
Peak memory 210076 kb
Host smart-b31fd83d-dd9c-4d8d-9d68-9bd2c311438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105114629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2105114629
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3949137961
Short name T49
Test name
Test status
Simulation time 354648643 ps
CPU time 3.08 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 219636 kb
Host smart-c74021c1-5cd2-4ff2-8532-1c6917ddef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949137961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3949137961
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.4262211107
Short name T548
Test name
Test status
Simulation time 1544769580 ps
CPU time 5.58 seconds
Started Apr 21 12:24:29 PM PDT 24
Finished Apr 21 12:24:35 PM PDT 24
Peak memory 209652 kb
Host smart-e9212679-facc-42cb-8728-53535cf595df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262211107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.4262211107
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1783116958
Short name T101
Test name
Test status
Simulation time 3156220316 ps
CPU time 86.69 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:26:11 PM PDT 24
Peak memory 243756 kb
Host smart-7adaee98-db38-4997-8712-d08e2c1a5cbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783116958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1783116958
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1431958391
Short name T426
Test name
Test status
Simulation time 486246338 ps
CPU time 7.4 seconds
Started Apr 21 12:24:41 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 208484 kb
Host smart-c9dc72e6-5a52-4a83-b796-068f3eadd6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431958391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1431958391
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1980440632
Short name T437
Test name
Test status
Simulation time 100907607 ps
CPU time 2.78 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:24:53 PM PDT 24
Peak memory 206476 kb
Host smart-8658f2d7-0c5e-47bb-904b-dfa632b75b87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980440632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1980440632
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3930845333
Short name T458
Test name
Test status
Simulation time 70672275 ps
CPU time 2.29 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 206596 kb
Host smart-8b64d0bd-8ccf-468b-82b6-497a1d11a0e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930845333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3930845333
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2257644149
Short name T15
Test name
Test status
Simulation time 24416999 ps
CPU time 1.98 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 209836 kb
Host smart-d5553cc0-5249-4d4e-9202-8924f34fa9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257644149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2257644149
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1385805892
Short name T587
Test name
Test status
Simulation time 45001244 ps
CPU time 2.5 seconds
Started Apr 21 12:24:38 PM PDT 24
Finished Apr 21 12:24:41 PM PDT 24
Peak memory 208124 kb
Host smart-f28a7974-026c-4f8b-a74a-1efb8385f97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385805892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1385805892
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3339297880
Short name T192
Test name
Test status
Simulation time 79708964 ps
CPU time 3.87 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 209180 kb
Host smart-b0c54a41-1438-464e-bd98-fb3d19cd92ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339297880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3339297880
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3010356556
Short name T265
Test name
Test status
Simulation time 187694020 ps
CPU time 2.74 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:24:53 PM PDT 24
Peak memory 214400 kb
Host smart-c363715a-00ba-4bd2-9ec0-53a5782ad6f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010356556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3010356556
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1411264978
Short name T347
Test name
Test status
Simulation time 140512057 ps
CPU time 4.47 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:24:48 PM PDT 24
Peak memory 207648 kb
Host smart-1807ec18-0186-4a81-a246-bae7123fe841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411264978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1411264978
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1476579047
Short name T94
Test name
Test status
Simulation time 4334326938 ps
CPU time 9.97 seconds
Started Apr 21 12:25:03 PM PDT 24
Finished Apr 21 12:25:14 PM PDT 24
Peak memory 209528 kb
Host smart-6f2f2eab-13d5-4027-b4b3-2860eb7c453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476579047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1476579047
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2179265609
Short name T276
Test name
Test status
Simulation time 158858900 ps
CPU time 3.05 seconds
Started Apr 21 12:24:49 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 210296 kb
Host smart-b8ac1b7b-2856-48a0-86b9-2401b7bc0a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179265609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2179265609
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2773646720
Short name T207
Test name
Test status
Simulation time 109082883 ps
CPU time 4.71 seconds
Started Apr 21 12:24:49 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 209564 kb
Host smart-ec47ff49-43d8-4a6a-bb08-55b1e4f2bba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773646720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2773646720
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.90437769
Short name T873
Test name
Test status
Simulation time 123571856 ps
CPU time 3.98 seconds
Started Apr 21 12:24:40 PM PDT 24
Finished Apr 21 12:24:45 PM PDT 24
Peak memory 207184 kb
Host smart-ae3eafca-b40c-4e61-a314-e2aeb2262817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90437769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.90437769
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1616939624
Short name T6
Test name
Test status
Simulation time 8955179328 ps
CPU time 18.29 seconds
Started Apr 21 12:24:37 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 239264 kb
Host smart-9d4e99e9-2b9e-46a4-bf0f-166e49f90233
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616939624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1616939624
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3333197176
Short name T440
Test name
Test status
Simulation time 50786853 ps
CPU time 2.78 seconds
Started Apr 21 12:24:29 PM PDT 24
Finished Apr 21 12:24:33 PM PDT 24
Peak memory 206488 kb
Host smart-2a63a931-c8bf-4afa-abcf-d4c714c7a231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333197176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3333197176
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.900125652
Short name T622
Test name
Test status
Simulation time 89824489 ps
CPU time 2.45 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 206460 kb
Host smart-d2283114-2e63-4d4e-a9af-02aeb701d5e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900125652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.900125652
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2954011562
Short name T649
Test name
Test status
Simulation time 822889400 ps
CPU time 9.07 seconds
Started Apr 21 12:24:41 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 208656 kb
Host smart-e62a13b7-7539-4cbc-9caf-7aa31b368086
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954011562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2954011562
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1544465933
Short name T252
Test name
Test status
Simulation time 341290767 ps
CPU time 5.49 seconds
Started Apr 21 12:24:43 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 208216 kb
Host smart-a4f24b8e-ee33-4610-a09e-cf8e8ddd048c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544465933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1544465933
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3191966478
Short name T423
Test name
Test status
Simulation time 562816380 ps
CPU time 2.18 seconds
Started Apr 21 12:24:55 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 210124 kb
Host smart-c6480d4d-1060-4010-9072-1beacd4372e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191966478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3191966478
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1569320627
Short name T722
Test name
Test status
Simulation time 1517421098 ps
CPU time 29.06 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:25:12 PM PDT 24
Peak memory 207304 kb
Host smart-82ceb803-6cb8-4d35-8b40-e06d9b86e577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569320627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1569320627
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1153816275
Short name T659
Test name
Test status
Simulation time 1866539919 ps
CPU time 23.77 seconds
Started Apr 21 12:25:10 PM PDT 24
Finished Apr 21 12:25:34 PM PDT 24
Peak memory 215084 kb
Host smart-50c10bf4-be46-44c3-845e-ca00e31bca43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153816275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1153816275
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.439117472
Short name T516
Test name
Test status
Simulation time 1681644387 ps
CPU time 41.15 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:25:23 PM PDT 24
Peak memory 219488 kb
Host smart-0bcc066b-189c-4c3b-a5d5-c4e36e2a6f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439117472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.439117472
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.99458093
Short name T818
Test name
Test status
Simulation time 61946570 ps
CPU time 1.87 seconds
Started Apr 21 12:25:00 PM PDT 24
Finished Apr 21 12:25:03 PM PDT 24
Peak memory 210076 kb
Host smart-063f21f5-4105-4c56-acaf-b2da2cf579b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99458093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.99458093
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.748948941
Short name T695
Test name
Test status
Simulation time 30562825 ps
CPU time 0.71 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:47 PM PDT 24
Peak memory 205776 kb
Host smart-1b8f8341-7fdf-4a49-985b-069395049cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748948941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.748948941
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3358994059
Short name T30
Test name
Test status
Simulation time 4643835773 ps
CPU time 8.87 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:25:02 PM PDT 24
Peak memory 213960 kb
Host smart-0d87e824-e856-479c-bf0d-3600b71693e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358994059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3358994059
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3954841430
Short name T381
Test name
Test status
Simulation time 379147918 ps
CPU time 4.29 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 209376 kb
Host smart-ef870974-109d-4259-8aae-b1d855844dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954841430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3954841430
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.4090447257
Short name T368
Test name
Test status
Simulation time 1017915714 ps
CPU time 12 seconds
Started Apr 21 12:24:49 PM PDT 24
Finished Apr 21 12:25:02 PM PDT 24
Peak memory 217676 kb
Host smart-f7d0317d-7c39-4132-8196-ffff76a24f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090447257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.4090447257
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.737194959
Short name T750
Test name
Test status
Simulation time 141469172 ps
CPU time 2.75 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 214188 kb
Host smart-a39c130c-4ac1-46d4-9cdf-352f55033216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737194959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.737194959
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.4253263376
Short name T198
Test name
Test status
Simulation time 210646964 ps
CPU time 5.63 seconds
Started Apr 21 12:24:55 PM PDT 24
Finished Apr 21 12:25:02 PM PDT 24
Peak memory 208464 kb
Host smart-e24d2375-0c3b-48e3-8ece-652465de69d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253263376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4253263376
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3320397550
Short name T879
Test name
Test status
Simulation time 364316134 ps
CPU time 2.61 seconds
Started Apr 21 12:24:57 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 206572 kb
Host smart-b99d9ed3-56e7-45be-9e0c-e58d535c4bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320397550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3320397550
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2050746859
Short name T342
Test name
Test status
Simulation time 131533528 ps
CPU time 4.1 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 207568 kb
Host smart-90c8a234-e290-466f-b2b7-2640e243ed56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050746859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2050746859
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.736754538
Short name T857
Test name
Test status
Simulation time 352727252 ps
CPU time 1.87 seconds
Started Apr 21 12:24:59 PM PDT 24
Finished Apr 21 12:25:02 PM PDT 24
Peak memory 208400 kb
Host smart-a83c7919-b408-46ac-a81d-b19130539211
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736754538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.736754538
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.4108177843
Short name T677
Test name
Test status
Simulation time 2015580406 ps
CPU time 45.87 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:25:39 PM PDT 24
Peak memory 208644 kb
Host smart-c7d3e474-8f37-4128-b86e-a390a6314846
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108177843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4108177843
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1979976066
Short name T395
Test name
Test status
Simulation time 424991801 ps
CPU time 4.54 seconds
Started Apr 21 12:25:06 PM PDT 24
Finished Apr 21 12:25:11 PM PDT 24
Peak memory 208492 kb
Host smart-d494f0c9-b451-4792-b581-a2aaa898c469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979976066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1979976066
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2221789436
Short name T16
Test name
Test status
Simulation time 26780662 ps
CPU time 1.97 seconds
Started Apr 21 12:25:08 PM PDT 24
Finished Apr 21 12:25:10 PM PDT 24
Peak memory 208592 kb
Host smart-d689ca55-1fee-4122-a503-a493719760cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221789436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2221789436
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1969908432
Short name T303
Test name
Test status
Simulation time 1626790490 ps
CPU time 16.22 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 220700 kb
Host smart-45233d70-daeb-421e-bf99-29060551e9e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969908432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1969908432
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3001194845
Short name T197
Test name
Test status
Simulation time 33170766 ps
CPU time 2.39 seconds
Started Apr 21 12:24:57 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 207260 kb
Host smart-56bc6fa2-f595-4f7a-a669-03af4c1e8f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001194845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3001194845
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1388807925
Short name T372
Test name
Test status
Simulation time 113639425 ps
CPU time 2.71 seconds
Started Apr 21 12:25:06 PM PDT 24
Finished Apr 21 12:25:09 PM PDT 24
Peak memory 210156 kb
Host smart-d1951e30-6ebc-44cc-b7b6-d8af5949237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388807925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1388807925
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1680179050
Short name T752
Test name
Test status
Simulation time 106684638 ps
CPU time 0.8 seconds
Started Apr 21 12:25:06 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 205740 kb
Host smart-a00bb8ff-3051-48ff-a55b-5c0d1f0bd520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680179050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1680179050
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3001781565
Short name T800
Test name
Test status
Simulation time 638156181 ps
CPU time 3.98 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 218176 kb
Host smart-a1e2f5bd-11f8-4858-ad52-6b16742bb5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001781565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3001781565
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1878846271
Short name T790
Test name
Test status
Simulation time 243967483 ps
CPU time 3.19 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 208804 kb
Host smart-3446f3c1-5484-4291-a786-7fc398ecc6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878846271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1878846271
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.780309275
Short name T259
Test name
Test status
Simulation time 594173958 ps
CPU time 7 seconds
Started Apr 21 12:25:14 PM PDT 24
Finished Apr 21 12:25:22 PM PDT 24
Peak memory 222308 kb
Host smart-7f697474-0224-4fa5-bb5f-95f5455f1222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780309275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.780309275
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2481914526
Short name T11
Test name
Test status
Simulation time 385035006 ps
CPU time 2.19 seconds
Started Apr 21 12:25:14 PM PDT 24
Finished Apr 21 12:25:16 PM PDT 24
Peak memory 209680 kb
Host smart-c5a18e91-8380-4a24-b681-7cd0bc6416d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481914526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2481914526
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.453851290
Short name T807
Test name
Test status
Simulation time 3429766198 ps
CPU time 14.91 seconds
Started Apr 21 12:25:17 PM PDT 24
Finished Apr 21 12:25:32 PM PDT 24
Peak memory 208528 kb
Host smart-01aee84c-0cb3-4e15-b843-7ff82b0f00f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453851290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.453851290
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1607763562
Short name T839
Test name
Test status
Simulation time 173649788 ps
CPU time 2.92 seconds
Started Apr 21 12:25:35 PM PDT 24
Finished Apr 21 12:25:39 PM PDT 24
Peak memory 207856 kb
Host smart-37edba44-69e9-4f92-aba9-76eeb565f5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607763562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1607763562
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2194166379
Short name T461
Test name
Test status
Simulation time 329439207 ps
CPU time 3.17 seconds
Started Apr 21 12:25:00 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 208528 kb
Host smart-0e137e16-985b-4139-86eb-e70b799bbd03
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194166379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2194166379
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3547449375
Short name T420
Test name
Test status
Simulation time 108413889 ps
CPU time 2.65 seconds
Started Apr 21 12:25:09 PM PDT 24
Finished Apr 21 12:25:13 PM PDT 24
Peak memory 206808 kb
Host smart-62ccb54d-ce2b-4a70-a201-6a9f4c858d2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547449375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3547449375
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.461182018
Short name T512
Test name
Test status
Simulation time 156528918 ps
CPU time 2.38 seconds
Started Apr 21 12:25:01 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 206564 kb
Host smart-b04d7249-60ab-4e1b-97bc-da4dcbb9a017
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461182018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.461182018
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.849161581
Short name T279
Test name
Test status
Simulation time 46585239 ps
CPU time 2.5 seconds
Started Apr 21 12:25:13 PM PDT 24
Finished Apr 21 12:25:16 PM PDT 24
Peak memory 217944 kb
Host smart-d44a9853-6643-4f05-a231-9d3649181de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849161581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.849161581
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2544024426
Short name T465
Test name
Test status
Simulation time 112362372 ps
CPU time 2.74 seconds
Started Apr 21 12:25:13 PM PDT 24
Finished Apr 21 12:25:17 PM PDT 24
Peak memory 208176 kb
Host smart-4734ebd5-6f56-408f-816c-a5636a726de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544024426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2544024426
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1914581121
Short name T124
Test name
Test status
Simulation time 158425532 ps
CPU time 4.15 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:38 PM PDT 24
Peak memory 221948 kb
Host smart-69f3593b-8829-41f9-bc30-851105328061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914581121 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1914581121
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.221318549
Short name T725
Test name
Test status
Simulation time 109133546 ps
CPU time 4.34 seconds
Started Apr 21 12:25:35 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 207772 kb
Host smart-047190e1-2d11-4c9e-88a7-ab456f876c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221318549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.221318549
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2202124242
Short name T164
Test name
Test status
Simulation time 126014493 ps
CPU time 2.56 seconds
Started Apr 21 12:25:09 PM PDT 24
Finished Apr 21 12:25:17 PM PDT 24
Peak memory 209512 kb
Host smart-30465f48-a3f8-435c-b274-63e636473e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202124242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2202124242
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.240904747
Short name T405
Test name
Test status
Simulation time 88323970 ps
CPU time 0.89 seconds
Started Apr 21 12:25:13 PM PDT 24
Finished Apr 21 12:25:15 PM PDT 24
Peak memory 205648 kb
Host smart-202ed165-d8e9-4d91-b2f3-0d53c0570664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240904747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.240904747
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.186753128
Short name T353
Test name
Test status
Simulation time 55670424 ps
CPU time 2.21 seconds
Started Apr 21 12:25:05 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 215244 kb
Host smart-94c29000-e62c-43d1-84c9-82ddcc401b0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186753128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.186753128
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.244755688
Short name T38
Test name
Test status
Simulation time 1737440673 ps
CPU time 16.21 seconds
Started Apr 21 12:24:59 PM PDT 24
Finished Apr 21 12:25:17 PM PDT 24
Peak memory 218028 kb
Host smart-b85197ce-0fa0-4aa1-9648-e0e3cc454e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244755688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.244755688
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.651389404
Short name T254
Test name
Test status
Simulation time 91380214 ps
CPU time 3.2 seconds
Started Apr 21 12:25:11 PM PDT 24
Finished Apr 21 12:25:15 PM PDT 24
Peak memory 214120 kb
Host smart-fbe53979-6afa-4151-9584-c256853eb001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651389404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.651389404
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2189008416
Short name T829
Test name
Test status
Simulation time 256290543 ps
CPU time 5.41 seconds
Started Apr 21 12:25:05 PM PDT 24
Finished Apr 21 12:25:11 PM PDT 24
Peak memory 209636 kb
Host smart-1c4b2fd4-79b7-4dc4-b17c-840251c6daa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189008416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2189008416
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3545116216
Short name T365
Test name
Test status
Simulation time 187557228 ps
CPU time 4.79 seconds
Started Apr 21 12:24:59 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 211288 kb
Host smart-a33ec5ad-c0eb-4260-afe4-6769981cd895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545116216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3545116216
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.1195063710
Short name T696
Test name
Test status
Simulation time 9306741842 ps
CPU time 73.98 seconds
Started Apr 21 12:25:00 PM PDT 24
Finished Apr 21 12:26:15 PM PDT 24
Peak memory 209376 kb
Host smart-7c40c477-7a4d-4fc7-80b3-a7d21e73038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195063710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1195063710
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.65925816
Short name T455
Test name
Test status
Simulation time 58301960 ps
CPU time 2.28 seconds
Started Apr 21 12:24:57 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 205632 kb
Host smart-cf09d16b-edd9-4cdf-a153-9373fa2c2d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65925816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.65925816
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.595112133
Short name T497
Test name
Test status
Simulation time 120755974 ps
CPU time 2.43 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 206412 kb
Host smart-ff930870-0151-4ea8-ab9f-bba8ad6e5397
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595112133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.595112133
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2452335499
Short name T475
Test name
Test status
Simulation time 188137578 ps
CPU time 2.58 seconds
Started Apr 21 12:24:55 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 207116 kb
Host smart-dcabdd1d-39c7-4598-b3b4-a7207adf39b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452335499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2452335499
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3646454273
Short name T377
Test name
Test status
Simulation time 121833709 ps
CPU time 2.41 seconds
Started Apr 21 12:25:13 PM PDT 24
Finished Apr 21 12:25:16 PM PDT 24
Peak memory 208332 kb
Host smart-8fa137d7-2800-4e35-b117-f6383e18ee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646454273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3646454273
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3164924776
Short name T588
Test name
Test status
Simulation time 7569607673 ps
CPU time 67.58 seconds
Started Apr 21 12:25:08 PM PDT 24
Finished Apr 21 12:26:16 PM PDT 24
Peak memory 208292 kb
Host smart-5afe14bf-45af-4e57-9425-431554a64588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164924776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3164924776
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1974337469
Short name T459
Test name
Test status
Simulation time 191109169 ps
CPU time 3.69 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 208688 kb
Host smart-85e9da17-49e8-4221-968f-75aaf82b7d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974337469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1974337469
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2588781841
Short name T517
Test name
Test status
Simulation time 97723080 ps
CPU time 3.67 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 209576 kb
Host smart-fbeab047-a3b0-40f3-8226-3b57c5fa8c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588781841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2588781841
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3298249361
Short name T509
Test name
Test status
Simulation time 15846521 ps
CPU time 0.74 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 205644 kb
Host smart-452f95b5-0100-44d3-b5e9-ffc5ab763f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298249361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3298249361
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2093753925
Short name T795
Test name
Test status
Simulation time 847208446 ps
CPU time 14.26 seconds
Started Apr 21 12:25:21 PM PDT 24
Finished Apr 21 12:25:36 PM PDT 24
Peak memory 215108 kb
Host smart-162d04db-63c9-4c3a-a161-bcebff198a31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093753925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2093753925
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.4190950217
Short name T66
Test name
Test status
Simulation time 584598923 ps
CPU time 19.49 seconds
Started Apr 21 12:25:17 PM PDT 24
Finished Apr 21 12:25:37 PM PDT 24
Peak memory 222544 kb
Host smart-e2686ac7-2b2f-407d-8b69-9b8818347c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190950217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.4190950217
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3999851722
Short name T825
Test name
Test status
Simulation time 75899509 ps
CPU time 2.85 seconds
Started Apr 21 12:25:17 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 208532 kb
Host smart-55f8b5cb-c756-4013-8dd0-2481908b1969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999851722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3999851722
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3384175045
Short name T466
Test name
Test status
Simulation time 279668925 ps
CPU time 10.03 seconds
Started Apr 21 12:25:06 PM PDT 24
Finished Apr 21 12:25:17 PM PDT 24
Peak memory 220352 kb
Host smart-9c8371d9-0d89-492a-8794-66335e11adea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384175045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3384175045
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1081107858
Short name T792
Test name
Test status
Simulation time 1200060943 ps
CPU time 41.02 seconds
Started Apr 21 12:25:23 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 223448 kb
Host smart-ecc972eb-f4a8-4cf5-a2b3-30c47b12101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081107858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1081107858
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.190726978
Short name T624
Test name
Test status
Simulation time 112744132 ps
CPU time 5.17 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:40 PM PDT 24
Peak memory 219700 kb
Host smart-918d61e5-adce-4d3f-b311-069dc75c135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190726978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.190726978
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.672018321
Short name T740
Test name
Test status
Simulation time 2470185490 ps
CPU time 7.84 seconds
Started Apr 21 12:25:06 PM PDT 24
Finished Apr 21 12:25:14 PM PDT 24
Peak memory 208380 kb
Host smart-fa3b4389-80f4-46d8-99c9-2e92e1044477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672018321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.672018321
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1662125221
Short name T507
Test name
Test status
Simulation time 4570628627 ps
CPU time 21.03 seconds
Started Apr 21 12:25:19 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 208044 kb
Host smart-26e89b9c-64bc-4069-a1c6-51510b67a987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662125221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1662125221
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.355376867
Short name T778
Test name
Test status
Simulation time 334545135 ps
CPU time 4.11 seconds
Started Apr 21 12:25:07 PM PDT 24
Finished Apr 21 12:25:12 PM PDT 24
Peak memory 206540 kb
Host smart-63eaa652-9dbd-4817-ac0c-09376de0eb62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355376867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.355376867
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2137360897
Short name T864
Test name
Test status
Simulation time 691416318 ps
CPU time 3.3 seconds
Started Apr 21 12:24:57 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 208564 kb
Host smart-c8f52a31-dbcd-4045-86ee-19b026a475b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137360897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2137360897
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2951213186
Short name T597
Test name
Test status
Simulation time 815827666 ps
CPU time 3.75 seconds
Started Apr 21 12:25:03 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 208568 kb
Host smart-895b6e90-5344-4c6d-8964-a13cccb8fc51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951213186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2951213186
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3529842690
Short name T568
Test name
Test status
Simulation time 52365688 ps
CPU time 2.37 seconds
Started Apr 21 12:25:18 PM PDT 24
Finished Apr 21 12:25:21 PM PDT 24
Peak memory 215444 kb
Host smart-fafe9710-5167-44c3-9b55-04952744c178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529842690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3529842690
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1964977102
Short name T376
Test name
Test status
Simulation time 149238382 ps
CPU time 5.77 seconds
Started Apr 21 12:25:12 PM PDT 24
Finished Apr 21 12:25:18 PM PDT 24
Peak memory 206492 kb
Host smart-d5a9cdc5-5cae-4fc5-bb1e-9e0545a213f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964977102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1964977102
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1377745791
Short name T804
Test name
Test status
Simulation time 144354272 ps
CPU time 4.31 seconds
Started Apr 21 12:25:02 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 207336 kb
Host smart-03941ed7-9a26-4021-80f9-4149dcc1b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377745791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1377745791
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3654678402
Short name T758
Test name
Test status
Simulation time 169496232 ps
CPU time 1.89 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:42 PM PDT 24
Peak memory 209460 kb
Host smart-2692f088-33ee-46f6-ba71-79888ccd592b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654678402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3654678402
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3288186784
Short name T452
Test name
Test status
Simulation time 40643376 ps
CPU time 0.87 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:25:25 PM PDT 24
Peak memory 205844 kb
Host smart-10e22314-b29c-4091-9068-4f7c4b1edc66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288186784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3288186784
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1272793394
Short name T392
Test name
Test status
Simulation time 4047220043 ps
CPU time 45.44 seconds
Started Apr 21 12:24:59 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 214876 kb
Host smart-ec80cd9e-5e9d-4b27-8ecb-466beb51fc8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272793394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1272793394
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1279876638
Short name T218
Test name
Test status
Simulation time 198301758 ps
CPU time 5.63 seconds
Started Apr 21 12:25:01 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 214440 kb
Host smart-fde57d9f-96c8-407f-91cb-0bd83d826455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279876638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1279876638
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2908353355
Short name T658
Test name
Test status
Simulation time 364010858 ps
CPU time 6.74 seconds
Started Apr 21 12:25:03 PM PDT 24
Finished Apr 21 12:25:10 PM PDT 24
Peak memory 208612 kb
Host smart-0478e53d-2e1b-4e67-aa37-790ebb089c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908353355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2908353355
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_random.4004523241
Short name T821
Test name
Test status
Simulation time 977695358 ps
CPU time 4.26 seconds
Started Apr 21 12:25:17 PM PDT 24
Finished Apr 21 12:25:21 PM PDT 24
Peak memory 207960 kb
Host smart-e08dd83e-aa12-45f5-9930-c2e818488fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004523241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4004523241
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.701227102
Short name T691
Test name
Test status
Simulation time 126419814 ps
CPU time 2.35 seconds
Started Apr 21 12:25:27 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 206640 kb
Host smart-691f145f-fac5-4efc-8e03-24bf52e3820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701227102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.701227102
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2674316452
Short name T468
Test name
Test status
Simulation time 119879185 ps
CPU time 3.18 seconds
Started Apr 21 12:25:17 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 206680 kb
Host smart-1ec45698-24ec-42d5-ae3c-328427272f2e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674316452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2674316452
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1160600208
Short name T541
Test name
Test status
Simulation time 70453192 ps
CPU time 2.27 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:43 PM PDT 24
Peak memory 206676 kb
Host smart-e1ac3c9a-dcb4-412c-aac4-875b1be20801
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160600208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1160600208
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3981767237
Short name T682
Test name
Test status
Simulation time 3956429197 ps
CPU time 38.17 seconds
Started Apr 21 12:25:16 PM PDT 24
Finished Apr 21 12:25:54 PM PDT 24
Peak memory 208652 kb
Host smart-321c28a1-2550-407a-9d95-cf8d6d2ce0a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981767237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3981767237
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3935602464
Short name T635
Test name
Test status
Simulation time 42975117 ps
CPU time 2.53 seconds
Started Apr 21 12:25:12 PM PDT 24
Finished Apr 21 12:25:15 PM PDT 24
Peak memory 207016 kb
Host smart-323499a2-050b-438d-857c-02a2d4a80847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935602464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3935602464
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2357839615
Short name T893
Test name
Test status
Simulation time 164423886 ps
CPU time 2.78 seconds
Started Apr 21 12:25:04 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 206568 kb
Host smart-8878f3f5-e81f-40e4-9691-f230a13fa772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357839615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2357839615
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.459073350
Short name T627
Test name
Test status
Simulation time 75939772 ps
CPU time 4.38 seconds
Started Apr 21 12:25:14 PM PDT 24
Finished Apr 21 12:25:19 PM PDT 24
Peak memory 219684 kb
Host smart-364f47cd-6339-40df-a393-d4c95435253e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459073350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.459073350
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1140180604
Short name T127
Test name
Test status
Simulation time 234115673 ps
CPU time 6.52 seconds
Started Apr 21 12:24:57 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 222496 kb
Host smart-921e4893-f4d0-4398-8778-90244d4d1ffd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140180604 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1140180604
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.252142160
Short name T681
Test name
Test status
Simulation time 40841832 ps
CPU time 3.09 seconds
Started Apr 21 12:25:11 PM PDT 24
Finished Apr 21 12:25:15 PM PDT 24
Peak memory 218412 kb
Host smart-4d8bb1e6-92ef-49a6-a1f4-5d259fe4ae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252142160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.252142160
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2046919348
Short name T62
Test name
Test status
Simulation time 5738918962 ps
CPU time 14.45 seconds
Started Apr 21 12:25:06 PM PDT 24
Finished Apr 21 12:25:21 PM PDT 24
Peak memory 211380 kb
Host smart-c943419b-8a96-49e0-a4e6-766dbd0d7afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046919348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2046919348
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3740249722
Short name T130
Test name
Test status
Simulation time 43525277 ps
CPU time 0.74 seconds
Started Apr 21 12:25:06 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 205836 kb
Host smart-c100c3e3-8272-4e3d-bb6f-abc6632554ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740249722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3740249722
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.4120338707
Short name T508
Test name
Test status
Simulation time 136801182 ps
CPU time 3.65 seconds
Started Apr 21 12:25:07 PM PDT 24
Finished Apr 21 12:25:11 PM PDT 24
Peak memory 208252 kb
Host smart-07e0211d-1d0e-47e9-b17e-1819ae6e71c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120338707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.4120338707
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2013261504
Short name T85
Test name
Test status
Simulation time 118281269 ps
CPU time 3.07 seconds
Started Apr 21 12:25:09 PM PDT 24
Finished Apr 21 12:25:13 PM PDT 24
Peak memory 209912 kb
Host smart-405fc276-65f6-479b-9836-1d6fbbeefad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013261504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2013261504
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2053064414
Short name T653
Test name
Test status
Simulation time 378182372 ps
CPU time 3.03 seconds
Started Apr 21 12:25:11 PM PDT 24
Finished Apr 21 12:25:14 PM PDT 24
Peak memory 205888 kb
Host smart-c14bc65f-e460-4193-9f4a-76966e3cf3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053064414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2053064414
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.501070296
Short name T445
Test name
Test status
Simulation time 412455222 ps
CPU time 6.04 seconds
Started Apr 21 12:25:23 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 208240 kb
Host smart-6da3d252-f024-4e50-b6e3-9e24c16c0100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501070296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.501070296
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2065851506
Short name T783
Test name
Test status
Simulation time 2948496090 ps
CPU time 17.32 seconds
Started Apr 21 12:25:02 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 208040 kb
Host smart-ff16faa3-8e77-4bbb-998e-95594f5de429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065851506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2065851506
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2254098790
Short name T79
Test name
Test status
Simulation time 301274556 ps
CPU time 3.6 seconds
Started Apr 21 12:25:12 PM PDT 24
Finished Apr 21 12:25:16 PM PDT 24
Peak memory 208332 kb
Host smart-32a2aba9-679e-49db-811a-23257b4a23a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254098790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2254098790
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.207245558
Short name T782
Test name
Test status
Simulation time 58082255 ps
CPU time 2.97 seconds
Started Apr 21 12:25:17 PM PDT 24
Finished Apr 21 12:25:21 PM PDT 24
Peak memory 206616 kb
Host smart-f71b3bd7-5692-4735-91e4-e445f51fbfb4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207245558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.207245558
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2717522210
Short name T872
Test name
Test status
Simulation time 226464667 ps
CPU time 6.23 seconds
Started Apr 21 12:25:17 PM PDT 24
Finished Apr 21 12:25:24 PM PDT 24
Peak memory 208696 kb
Host smart-16acc045-703a-4f0b-aa62-a13d4a148577
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717522210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2717522210
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_smoke.4122366939
Short name T513
Test name
Test status
Simulation time 139221416 ps
CPU time 2.25 seconds
Started Apr 21 12:25:03 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 206488 kb
Host smart-e6e41f09-7d03-4405-b3b5-a13639518818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122366939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4122366939
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.4039295742
Short name T302
Test name
Test status
Simulation time 75920780708 ps
CPU time 204.96 seconds
Started Apr 21 12:25:12 PM PDT 24
Finished Apr 21 12:28:38 PM PDT 24
Peak memory 222324 kb
Host smart-fd373df6-76e6-4de4-9c72-2835f89e9b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039295742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4039295742
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1782382331
Short name T741
Test name
Test status
Simulation time 200648705 ps
CPU time 6.65 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:48 PM PDT 24
Peak memory 222416 kb
Host smart-df4bc56f-b799-4d7f-89c2-d09acc6abbcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782382331 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1782382331
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.4174399866
Short name T715
Test name
Test status
Simulation time 89024087 ps
CPU time 4.03 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:45 PM PDT 24
Peak memory 214144 kb
Host smart-7f471204-fb17-4d71-bc6b-4fce3e65f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174399866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.4174399866
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1062228223
Short name T176
Test name
Test status
Simulation time 214326705 ps
CPU time 2.32 seconds
Started Apr 21 12:25:14 PM PDT 24
Finished Apr 21 12:25:22 PM PDT 24
Peak memory 209596 kb
Host smart-fa7ac30a-4308-4697-9ff2-90cb410dc078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062228223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1062228223
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.157100885
Short name T412
Test name
Test status
Simulation time 52818614 ps
CPU time 0.7 seconds
Started Apr 21 12:25:20 PM PDT 24
Finished Apr 21 12:25:21 PM PDT 24
Peak memory 205656 kb
Host smart-88a1dc93-ed42-499e-ba2a-8212a34d5690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157100885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.157100885
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3116245814
Short name T253
Test name
Test status
Simulation time 169719929 ps
CPU time 3.61 seconds
Started Apr 21 12:25:27 PM PDT 24
Finished Apr 21 12:25:31 PM PDT 24
Peak memory 214168 kb
Host smart-37845bc3-0742-43c5-a567-64d26999b045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116245814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3116245814
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.498057009
Short name T618
Test name
Test status
Simulation time 4402652901 ps
CPU time 53.5 seconds
Started Apr 21 12:25:19 PM PDT 24
Finished Apr 21 12:26:13 PM PDT 24
Peak memory 222596 kb
Host smart-b7efc3b4-bd60-45c9-a525-fc0f07870231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498057009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.498057009
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.136525218
Short name T311
Test name
Test status
Simulation time 63871107 ps
CPU time 2.28 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 208904 kb
Host smart-aaabdbdb-df32-41d9-a889-207d63f64e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136525218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.136525218
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1255860975
Short name T779
Test name
Test status
Simulation time 305185497 ps
CPU time 3.11 seconds
Started Apr 21 12:25:25 PM PDT 24
Finished Apr 21 12:25:28 PM PDT 24
Peak memory 214184 kb
Host smart-16f9e416-dbed-4990-9d64-f779043a4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255860975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1255860975
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3053209208
Short name T810
Test name
Test status
Simulation time 96962161 ps
CPU time 5.17 seconds
Started Apr 21 12:25:22 PM PDT 24
Finished Apr 21 12:25:28 PM PDT 24
Peak memory 213964 kb
Host smart-45be6479-3eca-45ce-aff5-409b39dc7950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053209208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3053209208
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4228892133
Short name T350
Test name
Test status
Simulation time 67065530 ps
CPU time 3.07 seconds
Started Apr 21 12:25:20 PM PDT 24
Finished Apr 21 12:25:24 PM PDT 24
Peak memory 214240 kb
Host smart-4769c008-4763-4608-affa-28d00a666953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228892133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4228892133
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1070271075
Short name T867
Test name
Test status
Simulation time 52929123 ps
CPU time 2.34 seconds
Started Apr 21 12:25:20 PM PDT 24
Finished Apr 21 12:25:23 PM PDT 24
Peak memory 206420 kb
Host smart-0a7efd53-aad9-4d8d-8ea8-fc1ca895a980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070271075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1070271075
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.160696123
Short name T579
Test name
Test status
Simulation time 168521029 ps
CPU time 4.08 seconds
Started Apr 21 12:25:13 PM PDT 24
Finished Apr 21 12:25:17 PM PDT 24
Peak memory 206576 kb
Host smart-fe24358d-51d1-41f3-9fa6-3db66b763be2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160696123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.160696123
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2909921322
Short name T481
Test name
Test status
Simulation time 84984496 ps
CPU time 3.85 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:25:29 PM PDT 24
Peak memory 208228 kb
Host smart-e0bb5c30-8558-45fb-b0ca-8b814c1258d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909921322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2909921322
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.584402941
Short name T854
Test name
Test status
Simulation time 48109671 ps
CPU time 2.25 seconds
Started Apr 21 12:25:31 PM PDT 24
Finished Apr 21 12:25:34 PM PDT 24
Peak memory 208352 kb
Host smart-eee77f48-c1e9-479a-acfa-78b98a6b4e41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584402941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.584402941
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3414048110
Short name T354
Test name
Test status
Simulation time 27223291 ps
CPU time 2.16 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:36 PM PDT 24
Peak memory 209592 kb
Host smart-0124990a-5253-435e-9aa5-adf815e81cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414048110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3414048110
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3201954337
Short name T414
Test name
Test status
Simulation time 123419087 ps
CPU time 4.44 seconds
Started Apr 21 12:25:26 PM PDT 24
Finished Apr 21 12:25:31 PM PDT 24
Peak memory 206592 kb
Host smart-4112d40f-5f07-4eb1-98e9-dee96bdf70b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201954337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3201954337
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.659898025
Short name T449
Test name
Test status
Simulation time 1161058479 ps
CPU time 5.89 seconds
Started Apr 21 12:26:36 PM PDT 24
Finished Apr 21 12:26:43 PM PDT 24
Peak memory 206716 kb
Host smart-05235f73-8e6d-4cb5-b64f-f3c7d5a78e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659898025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.659898025
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.904136416
Short name T53
Test name
Test status
Simulation time 155132896 ps
CPU time 2.18 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:25:27 PM PDT 24
Peak memory 209584 kb
Host smart-d0f1ce35-bf78-44e3-8939-0b30dccd3ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904136416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.904136416
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.420154759
Short name T786
Test name
Test status
Simulation time 161450278 ps
CPU time 0.93 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:34 PM PDT 24
Peak memory 205956 kb
Host smart-b272e96a-81fd-4406-97ae-fe4ecad1c553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420154759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.420154759
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2705633223
Short name T388
Test name
Test status
Simulation time 76972186 ps
CPU time 3.17 seconds
Started Apr 21 12:25:14 PM PDT 24
Finished Apr 21 12:25:17 PM PDT 24
Peak memory 209860 kb
Host smart-2beb07ba-c8cd-44b3-849e-e9337c85454d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705633223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2705633223
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2466620036
Short name T735
Test name
Test status
Simulation time 80775515 ps
CPU time 1.86 seconds
Started Apr 21 12:25:25 PM PDT 24
Finished Apr 21 12:25:27 PM PDT 24
Peak memory 214164 kb
Host smart-c578d892-c0ee-4c6a-87d6-f5783ffbaed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466620036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2466620036
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2395338674
Short name T389
Test name
Test status
Simulation time 117151633 ps
CPU time 4.94 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 209508 kb
Host smart-64946b58-e79e-4519-8c94-5ade40f59f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395338674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2395338674
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2137649925
Short name T645
Test name
Test status
Simulation time 859793359 ps
CPU time 19.96 seconds
Started Apr 21 12:25:23 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 222232 kb
Host smart-3f42726d-ae2f-4e0e-8b22-76bdc84937f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137649925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2137649925
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.703889143
Short name T208
Test name
Test status
Simulation time 568229732 ps
CPU time 2.48 seconds
Started Apr 21 12:25:26 PM PDT 24
Finished Apr 21 12:25:29 PM PDT 24
Peak memory 214092 kb
Host smart-7a777b9b-12cc-423a-b9a6-de6c54049cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703889143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.703889143
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.532252212
Short name T505
Test name
Test status
Simulation time 271582283 ps
CPU time 5.45 seconds
Started Apr 21 12:25:31 PM PDT 24
Finished Apr 21 12:25:37 PM PDT 24
Peak memory 214128 kb
Host smart-d5e153ae-da83-4ade-a637-e85d7035c77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532252212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.532252212
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1013617542
Short name T403
Test name
Test status
Simulation time 39651688 ps
CPU time 2.96 seconds
Started Apr 21 12:25:28 PM PDT 24
Finished Apr 21 12:25:31 PM PDT 24
Peak memory 208772 kb
Host smart-5e79cedc-d697-4e18-a75b-b22d41c44644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013617542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1013617542
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.683472640
Short name T871
Test name
Test status
Simulation time 1778432102 ps
CPU time 32.45 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 207832 kb
Host smart-34fd8634-bd2f-4de4-a790-8e3e0f71c3ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683472640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.683472640
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1367954129
Short name T683
Test name
Test status
Simulation time 25241540 ps
CPU time 2.01 seconds
Started Apr 21 12:25:19 PM PDT 24
Finished Apr 21 12:25:21 PM PDT 24
Peak memory 208480 kb
Host smart-2adcb251-99ed-4309-b3be-4f2839dd3fcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367954129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1367954129
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2330133950
Short name T737
Test name
Test status
Simulation time 127679967 ps
CPU time 2.98 seconds
Started Apr 21 12:25:19 PM PDT 24
Finished Apr 21 12:25:23 PM PDT 24
Peak memory 206620 kb
Host smart-c95e13ce-6327-4483-88d3-add73be807fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330133950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2330133950
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3589411263
Short name T444
Test name
Test status
Simulation time 316350785 ps
CPU time 4.12 seconds
Started Apr 21 12:25:30 PM PDT 24
Finished Apr 21 12:25:35 PM PDT 24
Peak memory 214064 kb
Host smart-d9d24146-4bf6-4dbf-9fce-448ec8835347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589411263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3589411263
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2420490887
Short name T644
Test name
Test status
Simulation time 1545173909 ps
CPU time 24.67 seconds
Started Apr 21 12:25:12 PM PDT 24
Finished Apr 21 12:25:38 PM PDT 24
Peak memory 207768 kb
Host smart-59f2a152-73e5-408f-8ee0-71c7ff63419f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420490887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2420490887
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2498794232
Short name T591
Test name
Test status
Simulation time 570338357 ps
CPU time 14.77 seconds
Started Apr 21 12:25:20 PM PDT 24
Finished Apr 21 12:25:35 PM PDT 24
Peak memory 219648 kb
Host smart-21183ae6-1095-4634-a181-20f9ad0eaec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498794232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2498794232
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.109096779
Short name T136
Test name
Test status
Simulation time 276831356 ps
CPU time 3.61 seconds
Started Apr 21 12:25:19 PM PDT 24
Finished Apr 21 12:25:23 PM PDT 24
Peak memory 207404 kb
Host smart-abfde133-616f-4203-95a4-819af5d35260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109096779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.109096779
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1028391632
Short name T172
Test name
Test status
Simulation time 87940674 ps
CPU time 2.96 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:25:45 PM PDT 24
Peak memory 209772 kb
Host smart-d1ebfe80-b4cd-404b-a79c-0415ec9cebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028391632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1028391632
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2698685265
Short name T720
Test name
Test status
Simulation time 50523920 ps
CPU time 0.93 seconds
Started Apr 21 12:25:32 PM PDT 24
Finished Apr 21 12:25:33 PM PDT 24
Peak memory 205912 kb
Host smart-6bfb2abd-8cdb-44c8-9346-53ae865b5f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698685265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2698685265
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3231154652
Short name T793
Test name
Test status
Simulation time 1632076850 ps
CPU time 78.05 seconds
Started Apr 21 12:25:43 PM PDT 24
Finished Apr 21 12:27:02 PM PDT 24
Peak memory 214124 kb
Host smart-e9898656-2eba-4b3f-bb1d-b19bb46ab13f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231154652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3231154652
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2731390674
Short name T442
Test name
Test status
Simulation time 536879579 ps
CPU time 2.44 seconds
Started Apr 21 12:25:48 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 207924 kb
Host smart-6726dbc4-9d8f-4408-a556-acf5d93fb176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731390674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2731390674
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3968016761
Short name T551
Test name
Test status
Simulation time 1696385224 ps
CPU time 3.33 seconds
Started Apr 21 12:25:28 PM PDT 24
Finished Apr 21 12:25:32 PM PDT 24
Peak memory 214192 kb
Host smart-1a8da560-9a8a-4d80-bd7b-76028389013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968016761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3968016761
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2584521552
Short name T730
Test name
Test status
Simulation time 109230242 ps
CPU time 4.93 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:40 PM PDT 24
Peak memory 222304 kb
Host smart-b88b97af-8a7d-40f0-9520-d7602f268703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584521552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2584521552
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.687074193
Short name T650
Test name
Test status
Simulation time 111770890 ps
CPU time 3.85 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:25:29 PM PDT 24
Peak memory 206476 kb
Host smart-6c5fdfff-3f35-4e24-bde4-0afb0ad6fefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687074193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.687074193
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3883519854
Short name T887
Test name
Test status
Simulation time 391241807 ps
CPU time 5.99 seconds
Started Apr 21 12:25:26 PM PDT 24
Finished Apr 21 12:25:32 PM PDT 24
Peak memory 207580 kb
Host smart-2a558992-c438-4261-8a4b-a22560a7dff8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883519854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3883519854
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.784029333
Short name T724
Test name
Test status
Simulation time 1621096805 ps
CPU time 50.37 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:26:15 PM PDT 24
Peak memory 208676 kb
Host smart-c33ab21b-7cab-4059-8ec1-aaae001f91ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784029333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.784029333
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3019326720
Short name T467
Test name
Test status
Simulation time 528500946 ps
CPU time 3.66 seconds
Started Apr 21 12:25:15 PM PDT 24
Finished Apr 21 12:25:19 PM PDT 24
Peak memory 206468 kb
Host smart-5f4c1883-a1c0-42f7-8fce-35175a8764be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019326720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3019326720
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1886596586
Short name T717
Test name
Test status
Simulation time 65096099 ps
CPU time 1.5 seconds
Started Apr 21 12:25:26 PM PDT 24
Finished Apr 21 12:25:28 PM PDT 24
Peak memory 207728 kb
Host smart-78cf7965-d5ea-48d9-9102-1103a75cd197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886596586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1886596586
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1742826889
Short name T704
Test name
Test status
Simulation time 52845161 ps
CPU time 2.63 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 206528 kb
Host smart-f3c92cbb-ba68-43fb-a17b-165b6cbbafc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742826889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1742826889
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.706343681
Short name T742
Test name
Test status
Simulation time 1198938918 ps
CPU time 23.71 seconds
Started Apr 21 12:25:32 PM PDT 24
Finished Apr 21 12:25:56 PM PDT 24
Peak memory 214776 kb
Host smart-83a50d12-0fa4-45ef-9521-2188d7da8dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706343681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.706343681
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3818474591
Short name T686
Test name
Test status
Simulation time 34229336 ps
CPU time 2.35 seconds
Started Apr 21 12:25:44 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 207108 kb
Host smart-899b4596-05a8-47ec-9401-8db3c8d24be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818474591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3818474591
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1722208945
Short name T166
Test name
Test status
Simulation time 142018036 ps
CPU time 2.52 seconds
Started Apr 21 12:25:16 PM PDT 24
Finished Apr 21 12:25:18 PM PDT 24
Peak memory 209872 kb
Host smart-fe485338-24d6-4674-930b-975ff2e4db25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722208945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1722208945
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.979594353
Short name T542
Test name
Test status
Simulation time 18621771 ps
CPU time 0.69 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:36 PM PDT 24
Peak memory 205752 kb
Host smart-7bf50806-b5f8-4fbc-80dd-35ad4824aa4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979594353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.979594353
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.4255336124
Short name T116
Test name
Test status
Simulation time 212219426 ps
CPU time 3.64 seconds
Started Apr 21 12:25:32 PM PDT 24
Finished Apr 21 12:25:36 PM PDT 24
Peak memory 215132 kb
Host smart-e2b2f2ba-84f8-4da1-ac53-66e3294fdff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4255336124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.4255336124
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1445264085
Short name T865
Test name
Test status
Simulation time 334408767 ps
CPU time 4.06 seconds
Started Apr 21 12:25:26 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 222280 kb
Host smart-61bdddd7-0ae3-4025-852e-a03f9857dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445264085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1445264085
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2679415487
Short name T763
Test name
Test status
Simulation time 63815242 ps
CPU time 3.85 seconds
Started Apr 21 12:25:35 PM PDT 24
Finished Apr 21 12:25:40 PM PDT 24
Peak memory 214108 kb
Host smart-a24e6f3a-7b8c-4151-a7e7-7e7a5ca4c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679415487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2679415487
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.709689420
Short name T196
Test name
Test status
Simulation time 686857587 ps
CPU time 5.26 seconds
Started Apr 21 12:25:54 PM PDT 24
Finished Apr 21 12:26:00 PM PDT 24
Peak memory 208360 kb
Host smart-82201d83-2356-4e41-a518-4e643acd0afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709689420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.709689420
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1865986414
Short name T341
Test name
Test status
Simulation time 225603354 ps
CPU time 2.24 seconds
Started Apr 21 12:25:27 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 206432 kb
Host smart-b126d399-f4f1-4c5c-94fd-9b25c3abe379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865986414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1865986414
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2550779092
Short name T570
Test name
Test status
Simulation time 163454502 ps
CPU time 4.84 seconds
Started Apr 21 12:25:32 PM PDT 24
Finished Apr 21 12:25:37 PM PDT 24
Peak memory 208080 kb
Host smart-1b3d0a24-2e87-42fe-9136-9f0416cb011b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550779092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2550779092
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2173527107
Short name T432
Test name
Test status
Simulation time 60380108 ps
CPU time 2.16 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 206492 kb
Host smart-8374765c-e9da-4ccf-9be5-c1d63e16654b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173527107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2173527107
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2671592848
Short name T586
Test name
Test status
Simulation time 226063300 ps
CPU time 3.08 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:25:45 PM PDT 24
Peak memory 208232 kb
Host smart-959c9d44-097c-4950-ac15-e21371f7382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671592848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2671592848
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3551558566
Short name T401
Test name
Test status
Simulation time 109305158 ps
CPU time 3.92 seconds
Started Apr 21 12:26:01 PM PDT 24
Finished Apr 21 12:26:06 PM PDT 24
Peak memory 207280 kb
Host smart-3f52594b-8eb1-4b85-b476-36f223abc4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551558566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3551558566
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.971894907
Short name T268
Test name
Test status
Simulation time 310715130 ps
CPU time 8.53 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:43 PM PDT 24
Peak memory 214224 kb
Host smart-df0215c0-b7bd-4d59-bcfc-ae7f537ef102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971894907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.971894907
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2597530649
Short name T169
Test name
Test status
Simulation time 71035859 ps
CPU time 2.53 seconds
Started Apr 21 12:26:45 PM PDT 24
Finished Apr 21 12:26:48 PM PDT 24
Peak memory 209828 kb
Host smart-22a4dd01-ff6f-4c6f-886a-0d67a914f18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597530649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2597530649
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1697474553
Short name T651
Test name
Test status
Simulation time 16291723 ps
CPU time 0.76 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:48 PM PDT 24
Peak memory 205720 kb
Host smart-97fe5e6b-06cd-4ae0-b672-f82c7c7f01fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697474553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1697474553
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3686345623
Short name T393
Test name
Test status
Simulation time 41000985 ps
CPU time 3.09 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 214956 kb
Host smart-ede745f1-5c12-4b98-b080-fab9bf3e37db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686345623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3686345623
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3454076417
Short name T32
Test name
Test status
Simulation time 80731043 ps
CPU time 2.82 seconds
Started Apr 21 12:24:48 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 214424 kb
Host smart-915118e7-53c4-470a-88d3-022d2d9f7eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454076417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3454076417
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.982343246
Short name T629
Test name
Test status
Simulation time 67652129 ps
CPU time 1.94 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 207352 kb
Host smart-36151176-1b4e-4319-bc6d-b8ccce3a26fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982343246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.982343246
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2819891914
Short name T823
Test name
Test status
Simulation time 241269011 ps
CPU time 8.63 seconds
Started Apr 21 12:24:54 PM PDT 24
Finished Apr 21 12:25:03 PM PDT 24
Peak memory 214108 kb
Host smart-ec8b4f17-671f-40b6-99b6-22fca90c3dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819891914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2819891914
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.4073719805
Short name T211
Test name
Test status
Simulation time 87149054 ps
CPU time 4.62 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 222320 kb
Host smart-86eabc0c-b1bc-4f7b-8af2-badc6cb2ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073719805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.4073719805
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.438881460
Short name T344
Test name
Test status
Simulation time 244296568 ps
CPU time 6.42 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:53 PM PDT 24
Peak memory 207440 kb
Host smart-b425e788-0d64-4949-bcfa-7a7c9fa238af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438881460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.438881460
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.908517103
Short name T102
Test name
Test status
Simulation time 95301802023 ps
CPU time 494.04 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:33:08 PM PDT 24
Peak memory 329572 kb
Host smart-90b25dce-a204-4510-927a-dc1bd46a2c39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908517103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.908517103
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3822236127
Short name T232
Test name
Test status
Simulation time 60489907 ps
CPU time 2.78 seconds
Started Apr 21 12:24:40 PM PDT 24
Finished Apr 21 12:24:43 PM PDT 24
Peak memory 206464 kb
Host smart-2f0e4fd4-52b8-4fa5-9bf0-333b8410ef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822236127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3822236127
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1519104353
Short name T443
Test name
Test status
Simulation time 382308913 ps
CPU time 7.6 seconds
Started Apr 21 12:24:48 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 208188 kb
Host smart-ea519b9a-ce71-4807-a502-4ab69f9e7e39
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519104353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1519104353
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2156738846
Short name T853
Test name
Test status
Simulation time 78957950 ps
CPU time 1.78 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:53 PM PDT 24
Peak memory 207232 kb
Host smart-6b46e8ca-ccbf-4b40-b333-b53954b0da6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156738846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2156738846
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1074933576
Short name T129
Test name
Test status
Simulation time 4667690880 ps
CPU time 53.9 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 208192 kb
Host smart-0ced5ae4-daa2-4074-913c-caae6bd310fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074933576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1074933576
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.41837317
Short name T702
Test name
Test status
Simulation time 70040815 ps
CPU time 2.14 seconds
Started Apr 21 12:25:05 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 209140 kb
Host smart-1dbe17c2-0720-4f4a-a44a-de540c98e3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41837317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.41837317
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3326164352
Short name T630
Test name
Test status
Simulation time 110939455 ps
CPU time 2.85 seconds
Started Apr 21 12:24:29 PM PDT 24
Finished Apr 21 12:24:32 PM PDT 24
Peak memory 206464 kb
Host smart-18c25a0b-b6fe-49c7-ba0c-9858c315a8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326164352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3326164352
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.435041027
Short name T473
Test name
Test status
Simulation time 1503357638 ps
CPU time 15.91 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:14 PM PDT 24
Peak memory 216300 kb
Host smart-4167d17a-a393-484c-aa46-0891ae9712a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435041027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.435041027
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1957631047
Short name T784
Test name
Test status
Simulation time 176833244 ps
CPU time 6.62 seconds
Started Apr 21 12:24:27 PM PDT 24
Finished Apr 21 12:24:34 PM PDT 24
Peak memory 208452 kb
Host smart-7cf59bed-9b13-4021-8990-418325bbe484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957631047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1957631047
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1759194568
Short name T184
Test name
Test status
Simulation time 213339114 ps
CPU time 4.75 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 210712 kb
Host smart-08ded1e8-3c03-4953-8938-ac8dc9d33e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759194568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1759194568
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.548533971
Short name T700
Test name
Test status
Simulation time 37040977 ps
CPU time 0.68 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:36 PM PDT 24
Peak memory 205708 kb
Host smart-65ad4c7b-ecad-46b1-ac9f-be9b5828713f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548533971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.548533971
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1172377718
Short name T43
Test name
Test status
Simulation time 546958753 ps
CPU time 6.05 seconds
Started Apr 21 12:25:23 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 209256 kb
Host smart-c7cea199-9618-49a4-880c-2a90ddfb23df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172377718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1172377718
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2982749722
Short name T771
Test name
Test status
Simulation time 413179066 ps
CPU time 7.3 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:42 PM PDT 24
Peak memory 208372 kb
Host smart-64de8eef-754d-4c6f-9772-6c345101df02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982749722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2982749722
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3323139483
Short name T288
Test name
Test status
Simulation time 130760598 ps
CPU time 5.68 seconds
Started Apr 21 12:25:29 PM PDT 24
Finished Apr 21 12:25:35 PM PDT 24
Peak memory 222276 kb
Host smart-16a20433-5cb3-4135-8c8f-d7adfab84d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323139483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3323139483
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.837598330
Short name T574
Test name
Test status
Simulation time 156549274 ps
CPU time 3.34 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:43 PM PDT 24
Peak memory 214200 kb
Host smart-6ee78d08-d84d-4fc2-8fba-d9b3fba5ac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837598330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.837598330
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2619135271
Short name T824
Test name
Test status
Simulation time 127231010 ps
CPU time 3.26 seconds
Started Apr 21 12:25:15 PM PDT 24
Finished Apr 21 12:25:19 PM PDT 24
Peak memory 207632 kb
Host smart-bc923bf9-ae4d-46c6-a55c-b0821e7decac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619135271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2619135271
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2517185037
Short name T298
Test name
Test status
Simulation time 1475740914 ps
CPU time 4.02 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:38 PM PDT 24
Peak memory 206508 kb
Host smart-acbec762-cb2b-4280-a370-ee37cf4d4905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517185037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2517185037
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1734931081
Short name T537
Test name
Test status
Simulation time 10549193920 ps
CPU time 62.22 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:26:40 PM PDT 24
Peak memory 208468 kb
Host smart-4028d8dd-df8e-4102-9d27-6b07c013621d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734931081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1734931081
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1305981601
Short name T582
Test name
Test status
Simulation time 755602315 ps
CPU time 14.63 seconds
Started Apr 21 12:25:22 PM PDT 24
Finished Apr 21 12:25:37 PM PDT 24
Peak memory 207968 kb
Host smart-ec2819e8-7b72-420e-b678-305c8e228f3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305981601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1305981601
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2411331673
Short name T561
Test name
Test status
Simulation time 918350095 ps
CPU time 27.55 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:26:18 PM PDT 24
Peak memory 208104 kb
Host smart-4746d9fc-15cb-47dc-aebc-da8661a2ba07
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411331673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2411331673
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.984342601
Short name T598
Test name
Test status
Simulation time 146652439 ps
CPU time 2.73 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:38 PM PDT 24
Peak memory 208124 kb
Host smart-cded76af-487f-45c5-ba19-dc0f8a42b085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984342601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.984342601
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1957571711
Short name T436
Test name
Test status
Simulation time 833276830 ps
CPU time 8.32 seconds
Started Apr 21 12:25:18 PM PDT 24
Finished Apr 21 12:25:27 PM PDT 24
Peak memory 208412 kb
Host smart-4e093d23-dd63-4081-b783-5d275bfcb8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957571711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1957571711
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4195627107
Short name T104
Test name
Test status
Simulation time 93234446 ps
CPU time 3.78 seconds
Started Apr 21 12:25:32 PM PDT 24
Finished Apr 21 12:25:36 PM PDT 24
Peak memory 208324 kb
Host smart-a0cd1ca9-c4f7-40da-9f3a-8ed453b8f686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195627107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4195627107
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1293713846
Short name T528
Test name
Test status
Simulation time 743091447 ps
CPU time 2.61 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 210520 kb
Host smart-b8303ba9-20a3-46b7-b32a-fab4190a9c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293713846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1293713846
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2813631499
Short name T590
Test name
Test status
Simulation time 41278889 ps
CPU time 0.82 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 205808 kb
Host smart-05fa1658-297d-4a39-a1d9-febd2bf9f0f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813631499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2813631499
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.602547222
Short name T592
Test name
Test status
Simulation time 56705085 ps
CPU time 2.9 seconds
Started Apr 21 12:25:32 PM PDT 24
Finished Apr 21 12:25:35 PM PDT 24
Peak memory 208964 kb
Host smart-d8c101ca-cb84-483a-9517-5ae7125d49d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602547222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.602547222
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1307831820
Short name T828
Test name
Test status
Simulation time 32852241 ps
CPU time 2.28 seconds
Started Apr 21 12:25:26 PM PDT 24
Finished Apr 21 12:25:28 PM PDT 24
Peak memory 208908 kb
Host smart-f5a3a01b-aad3-4dc3-8dfc-a82f790456ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307831820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1307831820
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3724480463
Short name T846
Test name
Test status
Simulation time 385273383 ps
CPU time 12.84 seconds
Started Apr 21 12:25:28 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 209988 kb
Host smart-b7856a0a-9cee-46a3-b0b5-2d269a7679c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724480463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3724480463
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.715575419
Short name T64
Test name
Test status
Simulation time 38431418 ps
CPU time 2.76 seconds
Started Apr 21 12:25:35 PM PDT 24
Finished Apr 21 12:25:39 PM PDT 24
Peak memory 214148 kb
Host smart-5a4a03c2-4f75-4ddc-8ded-6b03eb2834a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715575419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.715575419
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2901538385
Short name T496
Test name
Test status
Simulation time 33131553 ps
CPU time 2.47 seconds
Started Apr 21 12:25:25 PM PDT 24
Finished Apr 21 12:25:28 PM PDT 24
Peak memory 206428 kb
Host smart-e0af6598-ac2e-4f8c-9bdc-604edc5a196a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901538385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2901538385
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.4165840096
Short name T108
Test name
Test status
Simulation time 55062881 ps
CPU time 2.63 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:43 PM PDT 24
Peak memory 208212 kb
Host smart-e588b694-e685-4c67-8e63-7573e54e1a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165840096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.4165840096
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.369265378
Short name T139
Test name
Test status
Simulation time 2247229130 ps
CPU time 4.01 seconds
Started Apr 21 12:25:22 PM PDT 24
Finished Apr 21 12:25:26 PM PDT 24
Peak memory 208612 kb
Host smart-e4be73b0-f2ee-4667-a827-1ca91660f36c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369265378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.369265378
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.178381433
Short name T521
Test name
Test status
Simulation time 265564298 ps
CPU time 3.17 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:43 PM PDT 24
Peak memory 206396 kb
Host smart-1c0fca28-a1b4-4922-b99b-1fbe40b4684a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178381433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.178381433
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3813909486
Short name T447
Test name
Test status
Simulation time 92403332 ps
CPU time 3.52 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:25:27 PM PDT 24
Peak memory 208200 kb
Host smart-64493cfb-80ab-4cab-aa55-dcdfad84b051
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813909486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3813909486
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1541985864
Short name T529
Test name
Test status
Simulation time 67384100 ps
CPU time 2.42 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:25:27 PM PDT 24
Peak memory 208504 kb
Host smart-7562f17e-27ca-4e09-9d31-634560f7d4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541985864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1541985864
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1584152813
Short name T406
Test name
Test status
Simulation time 298620809 ps
CPU time 3.58 seconds
Started Apr 21 12:25:35 PM PDT 24
Finished Apr 21 12:25:40 PM PDT 24
Peak memory 206456 kb
Host smart-e6575e0e-beed-412d-84d2-ca30095abd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584152813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1584152813
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.606889420
Short name T358
Test name
Test status
Simulation time 967697005 ps
CPU time 7.91 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 222460 kb
Host smart-b1953999-5fe7-409e-8ace-f137b76718af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606889420 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.606889420
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2989713531
Short name T862
Test name
Test status
Simulation time 95476013 ps
CPU time 4.35 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:39 PM PDT 24
Peak memory 207292 kb
Host smart-29f56e5c-84d4-4d70-bd67-ccdf403dcac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989713531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2989713531
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2043444087
Short name T36
Test name
Test status
Simulation time 453917582 ps
CPU time 2.66 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:40 PM PDT 24
Peak memory 210196 kb
Host smart-cab6b905-4cc9-494a-bbd6-9d87df3d9d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043444087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2043444087
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3030722857
Short name T556
Test name
Test status
Simulation time 99927260 ps
CPU time 0.73 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 205696 kb
Host smart-0bfb3fa2-e18f-415e-926e-41e50f41507b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030722857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3030722857
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.329913656
Short name T565
Test name
Test status
Simulation time 27764029 ps
CPU time 1.93 seconds
Started Apr 21 12:25:54 PM PDT 24
Finished Apr 21 12:25:57 PM PDT 24
Peak memory 222264 kb
Host smart-2286fc52-b611-4c8c-9eaf-ddd24594df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329913656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.329913656
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3921489776
Short name T258
Test name
Test status
Simulation time 1155182886 ps
CPU time 5.02 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:40 PM PDT 24
Peak memory 214044 kb
Host smart-b0543c49-e46d-4652-a293-46aeda5c3be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921489776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3921489776
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3243164703
Short name T569
Test name
Test status
Simulation time 2091809343 ps
CPU time 25.34 seconds
Started Apr 21 12:26:46 PM PDT 24
Finished Apr 21 12:27:11 PM PDT 24
Peak memory 222188 kb
Host smart-0629bc00-6c04-4717-b430-6637af0be35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243164703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3243164703
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.4069693291
Short name T250
Test name
Test status
Simulation time 1058088699 ps
CPU time 8.01 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 207212 kb
Host smart-1c3bd3fa-d287-4315-9703-e8ce9b020bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069693291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4069693291
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2072890283
Short name T844
Test name
Test status
Simulation time 1666135210 ps
CPU time 42.71 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:26:20 PM PDT 24
Peak memory 208136 kb
Host smart-9aaca577-8a34-4b0c-84e8-bcda70f06af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072890283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2072890283
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2328732955
Short name T471
Test name
Test status
Simulation time 894980869 ps
CPU time 6.9 seconds
Started Apr 21 12:25:51 PM PDT 24
Finished Apr 21 12:25:59 PM PDT 24
Peak memory 207836 kb
Host smart-6b412016-d20c-4707-922c-e1e949bf847e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328732955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2328732955
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1319764839
Short name T134
Test name
Test status
Simulation time 437458399 ps
CPU time 3.83 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 208392 kb
Host smart-798e05e2-b407-4961-8460-db7362d250ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319764839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1319764839
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.13757746
Short name T3
Test name
Test status
Simulation time 260049820 ps
CPU time 2.62 seconds
Started Apr 21 12:26:46 PM PDT 24
Finished Apr 21 12:26:49 PM PDT 24
Peak memory 206436 kb
Host smart-c5e7c0cb-f08b-4379-97b6-b67a62eae728
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.13757746
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1766081083
Short name T464
Test name
Test status
Simulation time 743091024 ps
CPU time 10.63 seconds
Started Apr 21 12:25:31 PM PDT 24
Finished Apr 21 12:25:48 PM PDT 24
Peak memory 214188 kb
Host smart-2488d4c8-1d5d-4b85-a92b-06f37a345f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766081083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1766081083
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3203170664
Short name T378
Test name
Test status
Simulation time 38751912 ps
CPU time 2.42 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 208236 kb
Host smart-2b931c87-9e7e-4e80-a083-d57caef88c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203170664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3203170664
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.177512393
Short name T17
Test name
Test status
Simulation time 106327796 ps
CPU time 4.41 seconds
Started Apr 21 12:26:46 PM PDT 24
Finished Apr 21 12:26:50 PM PDT 24
Peak memory 207832 kb
Host smart-26130bd7-c33f-45ee-9417-c2be75a7097b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177512393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.177512393
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3682085888
Short name T599
Test name
Test status
Simulation time 126351202 ps
CPU time 1.68 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 209796 kb
Host smart-44f47aba-7bf2-46cc-bc7b-a5d022874133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682085888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3682085888
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3222304395
Short name T536
Test name
Test status
Simulation time 21505978 ps
CPU time 0.84 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 206024 kb
Host smart-272a78a9-85c6-4ef2-8138-78d56eb5463d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222304395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3222304395
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2206116689
Short name T894
Test name
Test status
Simulation time 454812680 ps
CPU time 8.31 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 209664 kb
Host smart-164ccf65-bfe9-4346-a105-3e3fa9e09baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206116689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2206116689
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3675369058
Short name T895
Test name
Test status
Simulation time 120436324 ps
CPU time 3.15 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 208580 kb
Host smart-24a5f0d8-124a-4c0c-a02d-43b16e577c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675369058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3675369058
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3409371378
Short name T281
Test name
Test status
Simulation time 200147460 ps
CPU time 5.77 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 214140 kb
Host smart-024d5c1c-1590-4768-a39b-58650f25b096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409371378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3409371378
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2965899210
Short name T366
Test name
Test status
Simulation time 194419063 ps
CPU time 7.31 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 222344 kb
Host smart-4355a5f0-fcfe-4c05-9848-05485911200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965899210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2965899210
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.510867897
Short name T555
Test name
Test status
Simulation time 716163744 ps
CPU time 8.23 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 222200 kb
Host smart-3a5ffb63-3f9e-4272-9af5-1e2e33601e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510867897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.510867897
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3068420146
Short name T300
Test name
Test status
Simulation time 1130264141 ps
CPU time 5.24 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:56 PM PDT 24
Peak memory 218992 kb
Host smart-e5ec7bb8-ae5c-4a8b-9da4-d5329ae5188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068420146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3068420146
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1079326859
Short name T656
Test name
Test status
Simulation time 72055007 ps
CPU time 1.69 seconds
Started Apr 21 12:26:08 PM PDT 24
Finished Apr 21 12:26:10 PM PDT 24
Peak memory 206468 kb
Host smart-dc0f686d-1476-442b-8abb-5b2c5b4a12fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079326859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1079326859
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3066485404
Short name T616
Test name
Test status
Simulation time 96694735 ps
CPU time 3.22 seconds
Started Apr 21 12:25:33 PM PDT 24
Finished Apr 21 12:25:38 PM PDT 24
Peak memory 206632 kb
Host smart-01e3407b-811c-42dc-aed8-dda1cba20dc8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066485404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3066485404
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3715234936
Short name T407
Test name
Test status
Simulation time 276622689 ps
CPU time 7.58 seconds
Started Apr 21 12:25:35 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 207628 kb
Host smart-bac397fb-feee-42aa-ae69-decf61439304
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715234936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3715234936
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.976185233
Short name T416
Test name
Test status
Simulation time 733144603 ps
CPU time 11.56 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 209160 kb
Host smart-c1ecb77c-29c7-4bc5-8fd5-3aba36401569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976185233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.976185233
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1387813737
Short name T400
Test name
Test status
Simulation time 2657528529 ps
CPU time 23.37 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 208756 kb
Host smart-36be3c92-9600-4981-b91c-921e6706af73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387813737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1387813737
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3975076661
Short name T319
Test name
Test status
Simulation time 273272118 ps
CPU time 6.92 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:45 PM PDT 24
Peak memory 208924 kb
Host smart-006fc045-738f-4c36-98b8-e916a046c04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975076661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3975076661
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2428562445
Short name T304
Test name
Test status
Simulation time 357269180 ps
CPU time 13.33 seconds
Started Apr 21 12:25:30 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 222504 kb
Host smart-60accfd3-b57f-4449-9629-5428260bb71d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428562445 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2428562445
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2470153099
Short name T492
Test name
Test status
Simulation time 580889392 ps
CPU time 7.55 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 208892 kb
Host smart-fb78e3e5-f050-4e98-8f39-442daeee4e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470153099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2470153099
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3609975603
Short name T160
Test name
Test status
Simulation time 142335658 ps
CPU time 1.77 seconds
Started Apr 21 12:25:41 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 209648 kb
Host smart-39a09abb-c5eb-4f10-a80e-c429a24181cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609975603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3609975603
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.4021656141
Short name T96
Test name
Test status
Simulation time 91529857 ps
CPU time 0.84 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 205760 kb
Host smart-19a43c22-6650-4af8-a46a-9df72c5d8e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021656141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4021656141
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.853048499
Short name T396
Test name
Test status
Simulation time 93739881 ps
CPU time 2.52 seconds
Started Apr 21 12:26:06 PM PDT 24
Finished Apr 21 12:26:09 PM PDT 24
Peak memory 214212 kb
Host smart-d29b3bde-f9ca-423a-8832-79bb87b84225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853048499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.853048499
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1898367377
Short name T434
Test name
Test status
Simulation time 3309065771 ps
CPU time 22.16 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 214192 kb
Host smart-e9438738-aac8-4460-8467-04993a0fbc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898367377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1898367377
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2520276640
Short name T619
Test name
Test status
Simulation time 77583017 ps
CPU time 2.69 seconds
Started Apr 21 12:25:44 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 208492 kb
Host smart-30381822-8b10-4567-aec7-55bb543c3f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520276640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2520276640
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1765243
Short name T705
Test name
Test status
Simulation time 65685853 ps
CPU time 3.84 seconds
Started Apr 21 12:25:48 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 211160 kb
Host smart-b6d7cfde-ef0b-4263-b066-e32058937165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1765243
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.785306063
Short name T289
Test name
Test status
Simulation time 214342993 ps
CPU time 6.51 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 214096 kb
Host smart-422dc420-45c6-4e0a-934b-5d32d940ca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785306063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.785306063
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1130781954
Short name T759
Test name
Test status
Simulation time 208130646 ps
CPU time 4.75 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:43 PM PDT 24
Peak memory 207328 kb
Host smart-753ecd1f-db36-4f68-9f96-9004edc070e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130781954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1130781954
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1670828955
Short name T545
Test name
Test status
Simulation time 89187076 ps
CPU time 4.07 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:42 PM PDT 24
Peak memory 208984 kb
Host smart-5a907047-0372-4736-9e04-0ab451bd9742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670828955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1670828955
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1465271573
Short name T480
Test name
Test status
Simulation time 373796867 ps
CPU time 4.66 seconds
Started Apr 21 12:25:58 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 206616 kb
Host smart-e21aaba4-c85f-48f5-98e5-968d567962ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465271573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1465271573
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2249885557
Short name T131
Test name
Test status
Simulation time 75676722 ps
CPU time 3.17 seconds
Started Apr 21 12:25:41 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 208104 kb
Host smart-1e28d6cd-d6b7-458c-8efb-168c07813b59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249885557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2249885557
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1432250572
Short name T538
Test name
Test status
Simulation time 88475435 ps
CPU time 1.91 seconds
Started Apr 21 12:25:29 PM PDT 24
Finished Apr 21 12:25:31 PM PDT 24
Peak memory 208344 kb
Host smart-1251553c-eb1e-4449-9a3d-7b8738cdd7d3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432250572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1432250572
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3023548260
Short name T448
Test name
Test status
Simulation time 214391693 ps
CPU time 5.1 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:56 PM PDT 24
Peak memory 206504 kb
Host smart-45658f4d-597a-4af8-9f87-5e11b588c8ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023548260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3023548260
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.924117486
Short name T886
Test name
Test status
Simulation time 487173013 ps
CPU time 2.23 seconds
Started Apr 21 12:25:41 PM PDT 24
Finished Apr 21 12:25:45 PM PDT 24
Peak memory 207848 kb
Host smart-ca554752-5888-4c4a-981e-e2ddfa899f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924117486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.924117486
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1613019706
Short name T830
Test name
Test status
Simulation time 85615583 ps
CPU time 2.85 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 207576 kb
Host smart-127ff64e-8759-40c7-ab0e-d5add4e76199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613019706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1613019706
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2394761031
Short name T693
Test name
Test status
Simulation time 5604634037 ps
CPU time 14.8 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 218036 kb
Host smart-e7734199-f96f-4248-be67-e014f2d6d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394761031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2394761031
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.943945223
Short name T110
Test name
Test status
Simulation time 182856229 ps
CPU time 2.61 seconds
Started Apr 21 12:25:27 PM PDT 24
Finished Apr 21 12:25:30 PM PDT 24
Peak memory 210024 kb
Host smart-c1ad0a54-0aea-4512-aa60-ba9073cbc757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943945223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.943945223
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1938290609
Short name T408
Test name
Test status
Simulation time 58028360 ps
CPU time 0.9 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:48 PM PDT 24
Peak memory 205988 kb
Host smart-9b942311-5d9b-4b20-94ff-d7fe4e3e6ddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938290609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1938290609
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3593069694
Short name T255
Test name
Test status
Simulation time 604518593 ps
CPU time 15.87 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 214600 kb
Host smart-0dff9ee6-a51b-4c6e-9da1-8f054183175f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3593069694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3593069694
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3998399092
Short name T385
Test name
Test status
Simulation time 85624648 ps
CPU time 3.74 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 218252 kb
Host smart-929b47ab-e1b7-4217-8261-be9d2f26cf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998399092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3998399092
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3377308907
Short name T76
Test name
Test status
Simulation time 786418824 ps
CPU time 6.61 seconds
Started Apr 21 12:25:54 PM PDT 24
Finished Apr 21 12:26:02 PM PDT 24
Peak memory 222204 kb
Host smart-cd029312-8a97-45a0-b113-2e53a2b82152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377308907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3377308907
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1071938172
Short name T456
Test name
Test status
Simulation time 22233289 ps
CPU time 1.88 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:40 PM PDT 24
Peak memory 219912 kb
Host smart-74f63ee6-90cb-4234-8309-b05be04893e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071938172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1071938172
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2270634963
Short name T133
Test name
Test status
Simulation time 325351658 ps
CPU time 8.1 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 207528 kb
Host smart-54faa0fd-fa17-4dcc-8084-7f3d04e0fb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270634963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2270634963
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3184271561
Short name T307
Test name
Test status
Simulation time 195891283 ps
CPU time 7.09 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:42 PM PDT 24
Peak memory 207628 kb
Host smart-0099d311-a44f-4ebd-a840-1ef8235b5952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184271561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3184271561
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.670788089
Short name T138
Test name
Test status
Simulation time 150749166 ps
CPU time 2.57 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 206564 kb
Host smart-1e10b6ff-fcc1-4704-b857-a744f658644b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670788089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.670788089
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2510615466
Short name T510
Test name
Test status
Simulation time 81614203 ps
CPU time 3.27 seconds
Started Apr 21 12:25:53 PM PDT 24
Finished Apr 21 12:25:57 PM PDT 24
Peak memory 208256 kb
Host smart-072e576a-3a9c-460e-a212-ba1fa1ac9e99
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510615466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2510615466
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3442144907
Short name T518
Test name
Test status
Simulation time 556919902 ps
CPU time 2.33 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:48 PM PDT 24
Peak memory 206592 kb
Host smart-19746d94-31e3-4584-87a6-a60af7716e6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442144907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3442144907
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3537862986
Short name T339
Test name
Test status
Simulation time 192127924 ps
CPU time 3.1 seconds
Started Apr 21 12:25:44 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 218236 kb
Host smart-8900224c-d9d1-465f-86e7-e2516a9ac91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537862986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3537862986
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1132665654
Short name T884
Test name
Test status
Simulation time 35997792 ps
CPU time 2.26 seconds
Started Apr 21 12:25:48 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 206864 kb
Host smart-ae72699f-d649-4fa0-a043-bdfc99aaa25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132665654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1132665654
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.649507943
Short name T214
Test name
Test status
Simulation time 1344434079 ps
CPU time 8.75 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 215480 kb
Host smart-d427aa79-0ad7-43bc-9ae7-6ff52688bc57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649507943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.649507943
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2151338549
Short name T171
Test name
Test status
Simulation time 710325115 ps
CPU time 7.84 seconds
Started Apr 21 12:25:24 PM PDT 24
Finished Apr 21 12:25:32 PM PDT 24
Peak memory 218648 kb
Host smart-2b5c9312-8a5b-4960-9457-b63dd5e5458b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151338549 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2151338549
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1023699521
Short name T811
Test name
Test status
Simulation time 107207228 ps
CPU time 4.55 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 207300 kb
Host smart-57198430-360c-4f3e-85b8-c8c431f17157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023699521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1023699521
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1535241253
Short name T109
Test name
Test status
Simulation time 139132102 ps
CPU time 2.05 seconds
Started Apr 21 12:26:00 PM PDT 24
Finished Apr 21 12:26:03 PM PDT 24
Peak memory 209600 kb
Host smart-53ea4c7c-7225-4096-8c8e-5d29fd319b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535241253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1535241253
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1331761545
Short name T419
Test name
Test status
Simulation time 21046911 ps
CPU time 0.87 seconds
Started Apr 21 12:26:02 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 205836 kb
Host smart-b6fb93c5-2bef-4c57-ad79-e38227f21704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331761545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1331761545
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3433620660
Short name T374
Test name
Test status
Simulation time 44700189 ps
CPU time 3.05 seconds
Started Apr 21 12:25:53 PM PDT 24
Finished Apr 21 12:25:57 PM PDT 24
Peak memory 214188 kb
Host smart-8fa4c66b-57c6-4425-b76c-f2a4213e938b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3433620660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3433620660
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2732291977
Short name T559
Test name
Test status
Simulation time 65784546 ps
CPU time 2.12 seconds
Started Apr 21 12:26:13 PM PDT 24
Finished Apr 21 12:26:15 PM PDT 24
Peak memory 206464 kb
Host smart-5cfe2789-a386-4b67-b5f5-65198dee9b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732291977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2732291977
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.607243100
Short name T88
Test name
Test status
Simulation time 603568782 ps
CPU time 5.17 seconds
Started Apr 21 12:25:48 PM PDT 24
Finished Apr 21 12:25:54 PM PDT 24
Peak memory 214132 kb
Host smart-3e8d28f3-1dd1-4c46-b35a-43ff78b7f21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607243100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.607243100
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2016658890
Short name T788
Test name
Test status
Simulation time 6662036478 ps
CPU time 45.32 seconds
Started Apr 21 12:25:57 PM PDT 24
Finished Apr 21 12:26:44 PM PDT 24
Peak memory 222240 kb
Host smart-4c64a67b-273e-4b45-a30c-089a1af0d246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016658890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2016658890
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2128957231
Short name T774
Test name
Test status
Simulation time 664679410 ps
CPU time 3.59 seconds
Started Apr 21 12:25:45 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 220468 kb
Host smart-16414cc2-a048-4482-929d-4f2e06719a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128957231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2128957231
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.594722651
Short name T617
Test name
Test status
Simulation time 394594292 ps
CPU time 5 seconds
Started Apr 21 12:25:52 PM PDT 24
Finished Apr 21 12:25:57 PM PDT 24
Peak memory 208408 kb
Host smart-51a8c8a7-cec7-4629-b5bb-9573eba2fb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594722651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.594722651
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2629276730
Short name T566
Test name
Test status
Simulation time 374090235 ps
CPU time 5.02 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 206580 kb
Host smart-48ae1492-981a-49da-b9ad-c13320c4a947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629276730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2629276730
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.616498686
Short name T77
Test name
Test status
Simulation time 517272722 ps
CPU time 15.98 seconds
Started Apr 21 12:25:44 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 208632 kb
Host smart-bbe85b65-a525-482b-86dd-0563ea334f9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616498686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.616498686
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1303793467
Short name T838
Test name
Test status
Simulation time 243977733 ps
CPU time 6.83 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 207616 kb
Host smart-3e0f5fec-a133-4936-9e0f-f0b913f77443
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303793467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1303793467
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1303456706
Short name T546
Test name
Test status
Simulation time 726788874 ps
CPU time 17.11 seconds
Started Apr 21 12:25:51 PM PDT 24
Finished Apr 21 12:26:09 PM PDT 24
Peak memory 208452 kb
Host smart-b018e520-9c5e-44c9-a971-576f92629059
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303456706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1303456706
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2468583129
Short name T878
Test name
Test status
Simulation time 55735080 ps
CPU time 1.82 seconds
Started Apr 21 12:25:48 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 209712 kb
Host smart-56b494c9-ebef-4f9a-bda9-6464e0fa0204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468583129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2468583129
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.4236494478
Short name T526
Test name
Test status
Simulation time 53737206 ps
CPU time 2.65 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 206480 kb
Host smart-098615f1-9301-4243-9944-49de5bb233f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236494478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4236494478
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4253195821
Short name T286
Test name
Test status
Simulation time 1035044413 ps
CPU time 19.41 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:26:03 PM PDT 24
Peak memory 216000 kb
Host smart-7d6cc46d-d52a-4eb3-bf2b-019c1e65a5b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253195821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4253195821
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1626966690
Short name T46
Test name
Test status
Simulation time 581774782 ps
CPU time 18.92 seconds
Started Apr 21 12:25:56 PM PDT 24
Finished Apr 21 12:26:16 PM PDT 24
Peak memory 222428 kb
Host smart-25bf69f0-aea3-4d32-85ab-0d251da389e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626966690 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1626966690
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1818093152
Short name T306
Test name
Test status
Simulation time 366867389 ps
CPU time 4.87 seconds
Started Apr 21 12:25:54 PM PDT 24
Finished Apr 21 12:26:00 PM PDT 24
Peak memory 209668 kb
Host smart-d1991e70-258a-4645-a07f-72a13ec08366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818093152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1818093152
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.278688159
Short name T679
Test name
Test status
Simulation time 63642845 ps
CPU time 2.47 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 209820 kb
Host smart-09bd2011-4b7a-4025-a74e-9d594ba2e8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278688159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.278688159
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3692401393
Short name T877
Test name
Test status
Simulation time 18541768 ps
CPU time 0.72 seconds
Started Apr 21 12:25:51 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 205692 kb
Host smart-f476a7b4-38de-4809-8d26-7f56d58abe33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692401393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3692401393
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2848374362
Short name T394
Test name
Test status
Simulation time 547936837 ps
CPU time 4.8 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 214728 kb
Host smart-848d4237-9628-4c11-a2bf-4c9f2b2506ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2848374362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2848374362
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3800759262
Short name T669
Test name
Test status
Simulation time 1024662920 ps
CPU time 32.44 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:26:22 PM PDT 24
Peak memory 214168 kb
Host smart-55dc02ec-1dfe-44b4-a991-4366b6813a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800759262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3800759262
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1230459592
Short name T672
Test name
Test status
Simulation time 443173500 ps
CPU time 7.96 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 208620 kb
Host smart-faf792ba-f4e6-40cd-9785-a6fc18bb5ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230459592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1230459592
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.919551145
Short name T386
Test name
Test status
Simulation time 75215740 ps
CPU time 3.47 seconds
Started Apr 21 12:25:57 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 209512 kb
Host smart-7e1fefa3-1f1a-4c04-8292-e2c8275a304b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919551145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.919551145
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.328334080
Short name T834
Test name
Test status
Simulation time 523272580 ps
CPU time 5.45 seconds
Started Apr 21 12:25:56 PM PDT 24
Finished Apr 21 12:26:02 PM PDT 24
Peak memory 214048 kb
Host smart-355d1d6c-a7b6-4019-a197-f17d55eab48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328334080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.328334080
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3990753741
Short name T326
Test name
Test status
Simulation time 635699091 ps
CPU time 5.44 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 220424 kb
Host smart-5cb895ec-1322-49cd-8611-6df59b5c70e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990753741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3990753741
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3928447332
Short name T757
Test name
Test status
Simulation time 325154808 ps
CPU time 3.74 seconds
Started Apr 21 12:25:35 PM PDT 24
Finished Apr 21 12:25:40 PM PDT 24
Peak memory 208660 kb
Host smart-706fe588-3868-455a-8def-4af4d207c2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928447332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3928447332
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.71990599
Short name T897
Test name
Test status
Simulation time 134154902 ps
CPU time 2.5 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:48 PM PDT 24
Peak memory 206596 kb
Host smart-b3c5898d-2d50-4bb5-848a-b3ad7ca37b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71990599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.71990599
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3951817943
Short name T478
Test name
Test status
Simulation time 745085161 ps
CPU time 3.34 seconds
Started Apr 21 12:25:51 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 206568 kb
Host smart-7f81f9c5-1146-436f-b1a0-2668ac63e5a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951817943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3951817943
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3916814271
Short name T431
Test name
Test status
Simulation time 45312953 ps
CPU time 1.72 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:25:44 PM PDT 24
Peak memory 206580 kb
Host smart-8d8bd0a1-ec0c-49c5-9c44-ca0c6404057e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916814271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3916814271
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3911742290
Short name T490
Test name
Test status
Simulation time 55842013 ps
CPU time 2.87 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:31 PM PDT 24
Peak memory 206616 kb
Host smart-b089bd76-ce31-4758-8ede-a26624c2cf20
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911742290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3911742290
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.4178528282
Short name T898
Test name
Test status
Simulation time 72848918 ps
CPU time 3.03 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:42 PM PDT 24
Peak memory 208920 kb
Host smart-2484b605-04f8-48fb-83bb-98e9a532abc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178528282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.4178528282
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.76786305
Short name T441
Test name
Test status
Simulation time 107195534 ps
CPU time 3.33 seconds
Started Apr 21 12:26:18 PM PDT 24
Finished Apr 21 12:26:21 PM PDT 24
Peak memory 207988 kb
Host smart-a9e4f2bf-0a8d-4ce3-ba0e-57c97252a444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76786305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.76786305
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3105390776
Short name T272
Test name
Test status
Simulation time 775661832 ps
CPU time 21.27 seconds
Started Apr 21 12:26:00 PM PDT 24
Finished Apr 21 12:26:22 PM PDT 24
Peak memory 215468 kb
Host smart-d88d89e6-7cb2-4d41-9973-586dfe5bf0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105390776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3105390776
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1579413788
Short name T660
Test name
Test status
Simulation time 616191509 ps
CPU time 7.02 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 208052 kb
Host smart-25307f40-a061-42cf-b002-e4cd0687eeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579413788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1579413788
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3556258311
Short name T128
Test name
Test status
Simulation time 248949605 ps
CPU time 2.85 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:43 PM PDT 24
Peak memory 209728 kb
Host smart-de819140-9929-44d1-8d95-07bb56827a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556258311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3556258311
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1985025860
Short name T418
Test name
Test status
Simulation time 15987174 ps
CPU time 0.75 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 205792 kb
Host smart-41580c9e-0804-49ef-9ff4-bfe4acf7c96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985025860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1985025860
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.772537897
Short name T535
Test name
Test status
Simulation time 78468577 ps
CPU time 3.21 seconds
Started Apr 21 12:25:41 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 214400 kb
Host smart-77e44b26-e0d2-4289-93f2-b4f7874097a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772537897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.772537897
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.513343213
Short name T667
Test name
Test status
Simulation time 92321256 ps
CPU time 2.21 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:54 PM PDT 24
Peak memory 210032 kb
Host smart-a5f6ff4f-b6fe-4a34-8404-66b577ece2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513343213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.513343213
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2105990533
Short name T863
Test name
Test status
Simulation time 40693281 ps
CPU time 2.89 seconds
Started Apr 21 12:25:43 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 208916 kb
Host smart-6ce914ab-676e-4676-982d-3eb478c5e0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105990533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2105990533
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3815338418
Short name T291
Test name
Test status
Simulation time 1167402442 ps
CPU time 16.47 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 214176 kb
Host smart-39ce2a5d-afe5-42e5-992b-9eedd9de2151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815338418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3815338418
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.4283570065
Short name T58
Test name
Test status
Simulation time 162137875 ps
CPU time 6.56 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:57 PM PDT 24
Peak memory 214236 kb
Host smart-cc1a4a7a-10c9-4ae4-bdd0-6ee62a4d81c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283570065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.4283570065
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2826126202
Short name T868
Test name
Test status
Simulation time 12777219448 ps
CPU time 85.89 seconds
Started Apr 21 12:25:45 PM PDT 24
Finished Apr 21 12:27:11 PM PDT 24
Peak memory 209480 kb
Host smart-89382fed-555a-44ed-a353-6fb7c0f0634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826126202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2826126202
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3394172290
Short name T81
Test name
Test status
Simulation time 393073686 ps
CPU time 5.91 seconds
Started Apr 21 12:25:35 PM PDT 24
Finished Apr 21 12:25:42 PM PDT 24
Peak memory 208132 kb
Host smart-7ce7495e-be07-408c-bdb4-41b0da65d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394172290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3394172290
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4234083984
Short name T415
Test name
Test status
Simulation time 39301440 ps
CPU time 2.49 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 207152 kb
Host smart-4263e41e-b4b1-431e-a577-e1e3f1f945ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234083984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4234083984
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3342289970
Short name T575
Test name
Test status
Simulation time 91580685 ps
CPU time 2.84 seconds
Started Apr 21 12:26:00 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 206448 kb
Host smart-07ce2ac9-1b7f-423a-af92-e0fba92a07d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342289970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3342289970
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2661976315
Short name T744
Test name
Test status
Simulation time 385832919 ps
CPU time 4.17 seconds
Started Apr 21 12:25:48 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 208604 kb
Host smart-6f54af5f-176b-4b69-93a6-a9aa568b4466
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661976315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2661976315
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4253051556
Short name T294
Test name
Test status
Simulation time 80483131 ps
CPU time 3.23 seconds
Started Apr 21 12:25:53 PM PDT 24
Finished Apr 21 12:25:57 PM PDT 24
Peak memory 210108 kb
Host smart-a9dd117a-a779-432b-ad64-f2ca0ee33327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253051556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4253051556
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.927265954
Short name T809
Test name
Test status
Simulation time 59811134 ps
CPU time 2.16 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 206896 kb
Host smart-3013d1d2-3607-4cbc-af92-e69649343132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927265954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.927265954
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2518339070
Short name T706
Test name
Test status
Simulation time 39994994 ps
CPU time 2.69 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 218048 kb
Host smart-fa5e4b1d-0757-465d-bf1b-20ebcc436441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518339070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2518339070
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2168014905
Short name T187
Test name
Test status
Simulation time 77857786 ps
CPU time 3.32 seconds
Started Apr 21 12:25:41 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 209844 kb
Host smart-b124b194-9f87-4440-9a73-a92242a30741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168014905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2168014905
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.479558675
Short name T639
Test name
Test status
Simulation time 11376897 ps
CPU time 0.72 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 205760 kb
Host smart-9d86149b-bf1a-4fe5-8bd2-badf1fbb59dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479558675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.479558675
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3624600240
Short name T375
Test name
Test status
Simulation time 199025402 ps
CPU time 3.68 seconds
Started Apr 21 12:25:59 PM PDT 24
Finished Apr 21 12:26:03 PM PDT 24
Peak memory 214192 kb
Host smart-a8c77d7c-d9e5-4f5f-b0f6-327712ba14f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624600240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3624600240
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.464903354
Short name T504
Test name
Test status
Simulation time 148329679 ps
CPU time 3.96 seconds
Started Apr 21 12:25:43 PM PDT 24
Finished Apr 21 12:25:48 PM PDT 24
Peak memory 214040 kb
Host smart-937b2fbb-ed75-44f1-b2bd-2ec39ebc33a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464903354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.464903354
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.4096256109
Short name T70
Test name
Test status
Simulation time 95278247 ps
CPU time 2.19 seconds
Started Apr 21 12:26:25 PM PDT 24
Finished Apr 21 12:26:27 PM PDT 24
Peak memory 209644 kb
Host smart-15380507-f6dc-48ea-aa0d-43b539ce7463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096256109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.4096256109
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.49555107
Short name T764
Test name
Test status
Simulation time 169648039 ps
CPU time 5.29 seconds
Started Apr 21 12:25:44 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 220440 kb
Host smart-02077dbb-c3cd-4806-8ee7-c9cdf5401c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49555107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.49555107
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2444527041
Short name T349
Test name
Test status
Simulation time 197904225 ps
CPU time 4.78 seconds
Started Apr 21 12:25:43 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 222260 kb
Host smart-552c723a-4053-4b73-b257-328bc5857f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444527041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2444527041
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2541847669
Short name T193
Test name
Test status
Simulation time 239108347 ps
CPU time 3.77 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 207496 kb
Host smart-c31b3954-ae77-44e6-97df-b37c366d176c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541847669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2541847669
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1220367404
Short name T338
Test name
Test status
Simulation time 234742683 ps
CPU time 5 seconds
Started Apr 21 12:25:52 PM PDT 24
Finished Apr 21 12:25:58 PM PDT 24
Peak memory 218084 kb
Host smart-7a43496b-7ac5-4f20-a65a-f79564b57e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220367404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1220367404
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2405758420
Short name T327
Test name
Test status
Simulation time 119217867 ps
CPU time 3.46 seconds
Started Apr 21 12:26:00 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 207640 kb
Host smart-44ee1284-2d70-4674-bb11-177e59bf5dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405758420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2405758420
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3800227384
Short name T446
Test name
Test status
Simulation time 49729646 ps
CPU time 2.13 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 208620 kb
Host smart-c3d72fba-972c-47ca-a191-8a8f132e96d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800227384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3800227384
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3836117245
Short name T352
Test name
Test status
Simulation time 263389860 ps
CPU time 2.96 seconds
Started Apr 21 12:25:59 PM PDT 24
Finished Apr 21 12:26:03 PM PDT 24
Peak memory 208848 kb
Host smart-9aad93a2-3e5b-4ad9-b3c1-5d2bc15030c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836117245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3836117245
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1056354978
Short name T333
Test name
Test status
Simulation time 92457569 ps
CPU time 2.01 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 208420 kb
Host smart-f28adefc-6ddd-447c-95be-d09ea3f54118
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056354978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1056354978
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1109885871
Short name T727
Test name
Test status
Simulation time 110358930 ps
CPU time 3.5 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 207332 kb
Host smart-643ca583-bfeb-4e87-a964-283a2a99b12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109885871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1109885871
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3083434910
Short name T770
Test name
Test status
Simulation time 732192423 ps
CPU time 2.72 seconds
Started Apr 21 12:25:36 PM PDT 24
Finished Apr 21 12:25:40 PM PDT 24
Peak memory 206712 kb
Host smart-10e04bc4-59fd-46e5-8819-a3c6c5ad7251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083434910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3083434910
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1646233948
Short name T72
Test name
Test status
Simulation time 223587194 ps
CPU time 6.18 seconds
Started Apr 21 12:25:45 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 215280 kb
Host smart-ad268312-9460-4569-a9da-26d9717108a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646233948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1646233948
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.689968875
Short name T710
Test name
Test status
Simulation time 584502479 ps
CPU time 10.76 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:59 PM PDT 24
Peak memory 209692 kb
Host smart-2061347c-c6af-437c-9308-b4d1687cfa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689968875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.689968875
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2094464644
Short name T692
Test name
Test status
Simulation time 76369861 ps
CPU time 0.73 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 205708 kb
Host smart-9c671e15-0e98-45f1-9955-f046ab808fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094464644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2094464644
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2620569209
Short name T29
Test name
Test status
Simulation time 84072112 ps
CPU time 1.58 seconds
Started Apr 21 12:24:28 PM PDT 24
Finished Apr 21 12:24:30 PM PDT 24
Peak memory 218176 kb
Host smart-dfd55402-e424-4b30-9d7a-1f871d31d0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620569209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2620569209
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3261886396
Short name T876
Test name
Test status
Simulation time 265902537 ps
CPU time 2.8 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:24:45 PM PDT 24
Peak memory 207484 kb
Host smart-3dced176-4472-46e2-bb78-ec70a585b17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261886396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3261886396
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3615669434
Short name T625
Test name
Test status
Simulation time 82318222 ps
CPU time 3.58 seconds
Started Apr 21 12:24:49 PM PDT 24
Finished Apr 21 12:24:53 PM PDT 24
Peak memory 209096 kb
Host smart-a9a1c190-a48d-40ef-a26d-2d6a279b1152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615669434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3615669434
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3117714239
Short name T86
Test name
Test status
Simulation time 2953063767 ps
CPU time 82.21 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 12:26:02 PM PDT 24
Peak memory 222580 kb
Host smart-6e18b848-c74d-46ad-a509-f43f6bae3387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117714239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3117714239
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1094964697
Short name T583
Test name
Test status
Simulation time 831782771 ps
CPU time 3.29 seconds
Started Apr 21 12:24:32 PM PDT 24
Finished Apr 21 12:24:35 PM PDT 24
Peak memory 219572 kb
Host smart-7a25bd4d-09a5-4bf8-a5a9-b6ad036968fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094964697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1094964697
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1232023056
Short name T856
Test name
Test status
Simulation time 35199081 ps
CPU time 2.48 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 214148 kb
Host smart-fd1c8231-2e7c-4110-bb14-c32fed15c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232023056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1232023056
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.901787028
Short name T231
Test name
Test status
Simulation time 358489832 ps
CPU time 6.97 seconds
Started Apr 21 12:24:55 PM PDT 24
Finished Apr 21 12:25:03 PM PDT 24
Peak memory 207488 kb
Host smart-da02e2e0-8aa5-4f5f-8dfc-cc4cda59c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901787028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.901787028
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1552199896
Short name T671
Test name
Test status
Simulation time 201400579 ps
CPU time 2.76 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 206520 kb
Host smart-3a7bda61-be51-4fb9-8ff9-d3920bad733f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552199896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1552199896
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.712918063
Short name T563
Test name
Test status
Simulation time 556308066 ps
CPU time 3.6 seconds
Started Apr 21 12:24:54 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 208312 kb
Host smart-a941f1e7-6316-4426-9243-c7c94112e53c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712918063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.712918063
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.135378463
Short name T515
Test name
Test status
Simulation time 34257618 ps
CPU time 2.29 seconds
Started Apr 21 12:24:35 PM PDT 24
Finished Apr 21 12:24:37 PM PDT 24
Peak memory 208456 kb
Host smart-45f9d407-d61a-4216-aac8-38db75faa686
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135378463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.135378463
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1688731854
Short name T713
Test name
Test status
Simulation time 207774132 ps
CPU time 3.81 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 208624 kb
Host smart-777a8e77-f2fa-48f2-908c-4ca55b549247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688731854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1688731854
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.105377696
Short name T604
Test name
Test status
Simulation time 548354142 ps
CPU time 3.89 seconds
Started Apr 21 12:24:54 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 206484 kb
Host smart-68f67308-154b-47fb-8e51-4342473708d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105377696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.105377696
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3156568902
Short name T364
Test name
Test status
Simulation time 1311390998 ps
CPU time 17.78 seconds
Started Apr 21 12:25:00 PM PDT 24
Finished Apr 21 12:25:19 PM PDT 24
Peak memory 215364 kb
Host smart-37934a98-9251-46bf-a910-02431ee7631c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156568902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3156568902
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2696435757
Short name T243
Test name
Test status
Simulation time 81051574 ps
CPU time 3.89 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:24:47 PM PDT 24
Peak memory 207088 kb
Host smart-22d4b79a-7462-4fcd-a891-9fbc72ccc5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696435757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2696435757
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3537392038
Short name T135
Test name
Test status
Simulation time 83042592 ps
CPU time 2.96 seconds
Started Apr 21 12:24:49 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 209632 kb
Host smart-fc7fab02-f72f-4ce3-b5d1-0c8d83f4e506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537392038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3537392038
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.184284461
Short name T435
Test name
Test status
Simulation time 44823211 ps
CPU time 0.71 seconds
Started Apr 21 12:25:53 PM PDT 24
Finished Apr 21 12:25:54 PM PDT 24
Peak memory 205872 kb
Host smart-f18ea84f-f529-4e6c-a399-67b52023b7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184284461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.184284461
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4214548059
Short name T153
Test name
Test status
Simulation time 106404789 ps
CPU time 3.9 seconds
Started Apr 21 12:26:05 PM PDT 24
Finished Apr 21 12:26:10 PM PDT 24
Peak memory 215448 kb
Host smart-d6a4067e-b93e-4e7d-9db9-5c5ed86cc8ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4214548059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4214548059
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2633624295
Short name T698
Test name
Test status
Simulation time 54257239 ps
CPU time 2.42 seconds
Started Apr 21 12:25:41 PM PDT 24
Finished Apr 21 12:25:45 PM PDT 24
Peak memory 207624 kb
Host smart-521e549b-e3a6-4da8-b2bf-2f2df348f4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633624295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2633624295
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2909836414
Short name T890
Test name
Test status
Simulation time 306474211 ps
CPU time 2.32 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 207180 kb
Host smart-3c5300f2-6eda-4ac2-a72d-fdcf57af58c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909836414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2909836414
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1658293117
Short name T335
Test name
Test status
Simulation time 637792033 ps
CPU time 7.24 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:58 PM PDT 24
Peak memory 209420 kb
Host smart-8a2d45fb-419a-4479-926d-06482823a816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658293117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1658293117
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3228384230
Short name T39
Test name
Test status
Simulation time 133922713 ps
CPU time 4.82 seconds
Started Apr 21 12:26:01 PM PDT 24
Finished Apr 21 12:26:06 PM PDT 24
Peak memory 209708 kb
Host smart-45937201-6a41-4942-9b96-b8a7478d6d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228384230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3228384230
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3273682981
Short name T40
Test name
Test status
Simulation time 452999982 ps
CPU time 3.56 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:25:45 PM PDT 24
Peak memory 209020 kb
Host smart-da173676-b2e9-4620-a82e-7b956fdda59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273682981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3273682981
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3311614749
Short name T500
Test name
Test status
Simulation time 610415745 ps
CPU time 11.9 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 209060 kb
Host smart-f50791f3-db07-4430-9644-0f2eddc4926d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311614749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3311614749
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.492635876
Short name T842
Test name
Test status
Simulation time 203598402 ps
CPU time 4.24 seconds
Started Apr 21 12:25:41 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 208392 kb
Host smart-01d2ab30-3763-4d7f-88b3-06ad0b65fc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492635876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.492635876
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1155229882
Short name T606
Test name
Test status
Simulation time 79430989 ps
CPU time 3.45 seconds
Started Apr 21 12:26:16 PM PDT 24
Finished Apr 21 12:26:20 PM PDT 24
Peak memory 207320 kb
Host smart-658dcf04-e9be-48ac-9d26-7b9a9b2a34d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155229882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1155229882
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1032448191
Short name T479
Test name
Test status
Simulation time 1199893422 ps
CPU time 7.11 seconds
Started Apr 21 12:25:43 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 208292 kb
Host smart-df62f72d-d589-46af-8ca8-c600cfc5504c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032448191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1032448191
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2875039337
Short name T855
Test name
Test status
Simulation time 1861487730 ps
CPU time 14.1 seconds
Started Apr 21 12:25:53 PM PDT 24
Finished Apr 21 12:26:08 PM PDT 24
Peak memory 207856 kb
Host smart-36bde6d7-52d0-44b5-8a7e-2609a2023d22
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875039337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2875039337
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.4063505558
Short name T831
Test name
Test status
Simulation time 125326713 ps
CPU time 3.83 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 215416 kb
Host smart-89ae4fe1-1858-4edd-9e03-18d5ee0e5ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063505558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4063505558
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2464239539
Short name T663
Test name
Test status
Simulation time 67915911 ps
CPU time 2.7 seconds
Started Apr 21 12:25:38 PM PDT 24
Finished Apr 21 12:25:56 PM PDT 24
Peak memory 207508 kb
Host smart-45a091fc-ae88-48be-9f67-4a4457c2d6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464239539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2464239539
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2517334521
Short name T98
Test name
Test status
Simulation time 846082607 ps
CPU time 25.01 seconds
Started Apr 21 12:26:04 PM PDT 24
Finished Apr 21 12:26:29 PM PDT 24
Peak memory 208356 kb
Host smart-cb3f1bde-4683-41b5-9b22-87c7204964ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517334521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2517334521
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1224833140
Short name T491
Test name
Test status
Simulation time 529457304 ps
CPU time 7.58 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 206948 kb
Host smart-c2f982ad-2d98-43fc-ad26-375ee4e9034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224833140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1224833140
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.285649470
Short name T600
Test name
Test status
Simulation time 235169457 ps
CPU time 4.01 seconds
Started Apr 21 12:25:45 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 209688 kb
Host smart-b2df1007-b124-483a-934f-20453223de6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285649470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.285649470
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.712031691
Short name T581
Test name
Test status
Simulation time 14391109 ps
CPU time 0.76 seconds
Started Apr 21 12:25:56 PM PDT 24
Finished Apr 21 12:25:57 PM PDT 24
Peak memory 205736 kb
Host smart-309fec8e-26cb-4399-a7a3-b94074d655cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712031691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.712031691
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.641237311
Short name T227
Test name
Test status
Simulation time 55672748 ps
CPU time 3.81 seconds
Started Apr 21 12:25:58 PM PDT 24
Finished Apr 21 12:26:02 PM PDT 24
Peak memory 214344 kb
Host smart-cee48261-9458-424f-942e-f03856b9320c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641237311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.641237311
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3939472906
Short name T50
Test name
Test status
Simulation time 24932248 ps
CPU time 1.84 seconds
Started Apr 21 12:26:06 PM PDT 24
Finished Apr 21 12:26:08 PM PDT 24
Peak memory 207156 kb
Host smart-08a174db-6a09-4ebc-8f37-3aa44350b7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939472906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3939472906
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2156755265
Short name T736
Test name
Test status
Simulation time 44942951 ps
CPU time 2.31 seconds
Started Apr 21 12:25:39 PM PDT 24
Finished Apr 21 12:25:43 PM PDT 24
Peak memory 214196 kb
Host smart-63e81c66-88f2-459d-b6b1-6787b214a2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156755265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2156755265
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.420360273
Short name T345
Test name
Test status
Simulation time 269108996 ps
CPU time 3.63 seconds
Started Apr 21 12:26:06 PM PDT 24
Finished Apr 21 12:26:10 PM PDT 24
Peak memory 208324 kb
Host smart-b470ce31-74ea-4710-bac5-e0fd6557c83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420360273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.420360273
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1029375944
Short name T847
Test name
Test status
Simulation time 17545913940 ps
CPU time 42.7 seconds
Started Apr 21 12:25:52 PM PDT 24
Finished Apr 21 12:26:36 PM PDT 24
Peak memory 208668 kb
Host smart-dcd5212b-2ffb-46cc-adc3-d11146835811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029375944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1029375944
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1068758216
Short name T776
Test name
Test status
Simulation time 230025710 ps
CPU time 3.12 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 208264 kb
Host smart-0b91e45a-d4ac-45f1-b15e-cddba4ee1c51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068758216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1068758216
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.303853234
Short name T875
Test name
Test status
Simulation time 298609438 ps
CPU time 3.7 seconds
Started Apr 21 12:26:08 PM PDT 24
Finished Apr 21 12:26:12 PM PDT 24
Peak memory 207720 kb
Host smart-4d78b1a4-9149-4ab5-9eff-5723c7ff1d8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303853234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.303853234
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2343161151
Short name T852
Test name
Test status
Simulation time 97336609 ps
CPU time 2.87 seconds
Started Apr 21 12:26:11 PM PDT 24
Finished Apr 21 12:26:15 PM PDT 24
Peak memory 206568 kb
Host smart-8dc032a4-0e14-4f47-9c25-f875356b8e01
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343161151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2343161151
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.40442437
Short name T633
Test name
Test status
Simulation time 28970023 ps
CPU time 1.83 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 209220 kb
Host smart-dd7219fb-7b0a-4c02-8cc4-2f67c2539b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40442437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.40442437
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2560929097
Short name T743
Test name
Test status
Simulation time 181779451 ps
CPU time 5.95 seconds
Started Apr 21 12:25:56 PM PDT 24
Finished Apr 21 12:26:02 PM PDT 24
Peak memory 207556 kb
Host smart-61051403-d9f9-4262-afce-63c4510558a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560929097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2560929097
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2061360665
Short name T734
Test name
Test status
Simulation time 5069521968 ps
CPU time 53.91 seconds
Started Apr 21 12:26:06 PM PDT 24
Finished Apr 21 12:27:00 PM PDT 24
Peak memory 208104 kb
Host smart-e499fdb5-069d-4d23-9581-c3242fa21676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061360665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2061360665
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1117431566
Short name T605
Test name
Test status
Simulation time 1066698995 ps
CPU time 11.87 seconds
Started Apr 21 12:26:01 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 221400 kb
Host smart-75dc7697-6e82-408b-a30e-6fd7e3ac5a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117431566 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1117431566
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1709171100
Short name T701
Test name
Test status
Simulation time 194682762 ps
CPU time 4.36 seconds
Started Apr 21 12:25:58 PM PDT 24
Finished Apr 21 12:26:03 PM PDT 24
Peak memory 214180 kb
Host smart-30b48611-1584-42c2-820f-2c76f9c109c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709171100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1709171100
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.670443065
Short name T141
Test name
Test status
Simulation time 122973836 ps
CPU time 2.73 seconds
Started Apr 21 12:26:14 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 209884 kb
Host smart-6cc28f71-5dc0-4ab0-8aca-ef0fe3f6e3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670443065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.670443065
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3547390135
Short name T439
Test name
Test status
Simulation time 8943745 ps
CPU time 0.74 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 205760 kb
Host smart-b900f016-0e07-4747-920d-74bb4bc47826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547390135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3547390135
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.4042370355
Short name T726
Test name
Test status
Simulation time 3709995016 ps
CPU time 49.94 seconds
Started Apr 21 12:26:55 PM PDT 24
Finished Apr 21 12:27:46 PM PDT 24
Peak memory 212652 kb
Host smart-95b5772e-68e8-4d1d-8208-cadc48da9891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4042370355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.4042370355
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.796865592
Short name T245
Test name
Test status
Simulation time 1157750436 ps
CPU time 6.84 seconds
Started Apr 21 12:26:00 PM PDT 24
Finished Apr 21 12:26:07 PM PDT 24
Peak memory 213616 kb
Host smart-971f3cf4-97e0-4b24-9921-d414a8af1ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796865592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.796865592
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1994388155
Short name T543
Test name
Test status
Simulation time 191954860 ps
CPU time 3.52 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 214308 kb
Host smart-6e563803-dbb7-41cf-a342-50f379db7b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994388155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1994388155
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2072713092
Short name T699
Test name
Test status
Simulation time 262374973 ps
CPU time 9.29 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:57 PM PDT 24
Peak memory 210880 kb
Host smart-18c03922-ec79-4897-945d-154d8432dbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072713092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2072713092
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1863571345
Short name T544
Test name
Test status
Simulation time 130735933 ps
CPU time 2.61 seconds
Started Apr 21 12:25:59 PM PDT 24
Finished Apr 21 12:26:02 PM PDT 24
Peak memory 208016 kb
Host smart-1ffb69c1-99e7-4582-b689-8ecc9388bb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863571345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1863571345
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2901955309
Short name T643
Test name
Test status
Simulation time 538218886 ps
CPU time 5.5 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 208520 kb
Host smart-1953e895-c68e-4f9a-87a2-cb32f55498f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901955309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2901955309
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.720803523
Short name T896
Test name
Test status
Simulation time 211365760 ps
CPU time 2.72 seconds
Started Apr 21 12:26:22 PM PDT 24
Finished Apr 21 12:26:25 PM PDT 24
Peak memory 207940 kb
Host smart-4d14de90-e3c1-4594-aadb-b1c0e5ad1a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720803523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.720803523
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3736427132
Short name T247
Test name
Test status
Simulation time 156576434 ps
CPU time 4.64 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 207700 kb
Host smart-5205d615-37c9-4e04-9bec-d6788bcea557
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736427132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3736427132
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2547440564
Short name T476
Test name
Test status
Simulation time 212400785 ps
CPU time 2.59 seconds
Started Apr 21 12:25:43 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 206596 kb
Host smart-0978f3ed-1587-4dff-9b00-a6c1b84869ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547440564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2547440564
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3187607552
Short name T562
Test name
Test status
Simulation time 118023645 ps
CPU time 3.61 seconds
Started Apr 21 12:25:57 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 206588 kb
Host smart-38e8b5dd-15dd-4ac1-a6a4-941eb5fa4baf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187607552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3187607552
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3180999634
Short name T498
Test name
Test status
Simulation time 186970823 ps
CPU time 2.58 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 215684 kb
Host smart-b7203f37-7639-400a-b343-d65ba5c534f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180999634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3180999634
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2207450190
Short name T488
Test name
Test status
Simulation time 328782143 ps
CPU time 3.19 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 208444 kb
Host smart-136c5d04-9f6d-4936-abb9-7c3fc91cfa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207450190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2207450190
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2347254634
Short name T269
Test name
Test status
Simulation time 13989089182 ps
CPU time 148.05 seconds
Started Apr 21 12:26:02 PM PDT 24
Finished Apr 21 12:28:31 PM PDT 24
Peak memory 216496 kb
Host smart-a4bfc437-d30e-4f0c-b011-d5d20fefb2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347254634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2347254634
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3388153101
Short name T137
Test name
Test status
Simulation time 77172487 ps
CPU time 3.62 seconds
Started Apr 21 12:25:48 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 209872 kb
Host smart-860c9a9d-71f8-4044-9f1b-5c0afb3256a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388153101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3388153101
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2979772288
Short name T882
Test name
Test status
Simulation time 336739842 ps
CPU time 2.2 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 209964 kb
Host smart-298a1c3d-17f0-4360-8b23-9ba6cb3347c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979772288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2979772288
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.4131532020
Short name T399
Test name
Test status
Simulation time 20722285 ps
CPU time 0.8 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 205712 kb
Host smart-72f08ab6-afa6-47f4-98b6-109b1ccbaae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131532020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4131532020
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2296353146
Short name T309
Test name
Test status
Simulation time 273047730 ps
CPU time 4.2 seconds
Started Apr 21 12:25:55 PM PDT 24
Finished Apr 21 12:26:00 PM PDT 24
Peak memory 214140 kb
Host smart-e500da4d-5f5c-4fbf-8423-bada7bb3902a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296353146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2296353146
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1974563860
Short name T209
Test name
Test status
Simulation time 348378575 ps
CPU time 5.11 seconds
Started Apr 21 12:27:10 PM PDT 24
Finished Apr 21 12:27:16 PM PDT 24
Peak memory 209332 kb
Host smart-105b279f-dc3c-41cd-bf5f-e9f9a21a510a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974563860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1974563860
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3885752466
Short name T815
Test name
Test status
Simulation time 847597773 ps
CPU time 2.88 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:49 PM PDT 24
Peak memory 207784 kb
Host smart-a9f87f33-e4c3-42b6-95d6-023295bf8e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885752466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3885752466
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3754816432
Short name T489
Test name
Test status
Simulation time 616614933 ps
CPU time 8.8 seconds
Started Apr 21 12:26:15 PM PDT 24
Finished Apr 21 12:26:25 PM PDT 24
Peak memory 218824 kb
Host smart-9fc013f5-e895-43df-8475-f6c51e6feaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754816432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3754816432
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1256736183
Short name T323
Test name
Test status
Simulation time 430683772 ps
CPU time 4.88 seconds
Started Apr 21 12:25:44 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 208368 kb
Host smart-5f3fa686-558f-4701-a2ee-0d8300ad62fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256736183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1256736183
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3953462542
Short name T482
Test name
Test status
Simulation time 374912249 ps
CPU time 4.2 seconds
Started Apr 21 12:25:55 PM PDT 24
Finished Apr 21 12:25:59 PM PDT 24
Peak memory 206388 kb
Host smart-06f2ebf9-2cae-4073-a3a8-584b9bebc82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953462542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3953462542
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2883457933
Short name T687
Test name
Test status
Simulation time 863801207 ps
CPU time 9.94 seconds
Started Apr 21 12:25:54 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 208192 kb
Host smart-6f6016b2-2494-4cc4-a601-7471150d643f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883457933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2883457933
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2772088957
Short name T200
Test name
Test status
Simulation time 265552207 ps
CPU time 1.98 seconds
Started Apr 21 12:26:55 PM PDT 24
Finished Apr 21 12:26:58 PM PDT 24
Peak memory 203696 kb
Host smart-128047c7-7705-4a96-9b6d-cdb944e78187
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772088957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2772088957
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1771847631
Short name T631
Test name
Test status
Simulation time 51694732 ps
CPU time 2.82 seconds
Started Apr 21 12:25:57 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 206240 kb
Host smart-a16f4c5b-45e2-4c14-bcdf-05dcd748f62a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771847631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1771847631
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2371863184
Short name T267
Test name
Test status
Simulation time 74070537 ps
CPU time 1.73 seconds
Started Apr 21 12:26:07 PM PDT 24
Finished Apr 21 12:26:09 PM PDT 24
Peak memory 215628 kb
Host smart-70ef04cc-7f8a-4e2e-ab26-cf78a76acc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371863184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2371863184
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3735632817
Short name T593
Test name
Test status
Simulation time 154163508 ps
CPU time 1.74 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:25:54 PM PDT 24
Peak memory 206784 kb
Host smart-c63e8ef4-ad72-4a3a-a2ec-01173741c009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735632817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3735632817
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1131027168
Short name T188
Test name
Test status
Simulation time 10502960814 ps
CPU time 54.15 seconds
Started Apr 21 12:26:04 PM PDT 24
Finished Apr 21 12:26:59 PM PDT 24
Peak memory 222444 kb
Host smart-d9e7bda1-74e9-4299-b007-b738078295bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131027168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1131027168
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1932700026
Short name T589
Test name
Test status
Simulation time 149984663 ps
CPU time 4.51 seconds
Started Apr 21 12:27:10 PM PDT 24
Finished Apr 21 12:27:15 PM PDT 24
Peak memory 222348 kb
Host smart-debc5782-c322-4f10-8a27-72e13de0a3b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932700026 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1932700026
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1608841354
Short name T837
Test name
Test status
Simulation time 348573982 ps
CPU time 4.04 seconds
Started Apr 21 12:25:59 PM PDT 24
Finished Apr 21 12:26:03 PM PDT 24
Peak memory 207672 kb
Host smart-28e9dab4-4363-4a4b-b812-f3f13a197770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608841354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1608841354
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2382030701
Short name T162
Test name
Test status
Simulation time 300948678 ps
CPU time 8.02 seconds
Started Apr 21 12:26:55 PM PDT 24
Finished Apr 21 12:27:04 PM PDT 24
Peak memory 207480 kb
Host smart-f147f084-cb57-47ad-86d6-b2c14250b4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382030701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2382030701
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3538062403
Short name T835
Test name
Test status
Simulation time 10072663 ps
CPU time 0.68 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:47 PM PDT 24
Peak memory 205836 kb
Host smart-c67558f2-9b66-4754-8575-9a8053031b61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538062403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3538062403
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.175107312
Short name T249
Test name
Test status
Simulation time 332490257 ps
CPU time 12.51 seconds
Started Apr 21 12:26:55 PM PDT 24
Finished Apr 21 12:27:09 PM PDT 24
Peak memory 214060 kb
Host smart-9e3f3c91-de55-4f97-9183-5b7bef065c5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175107312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.175107312
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2541868463
Short name T31
Test name
Test status
Simulation time 186992979 ps
CPU time 3.29 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:51 PM PDT 24
Peak memory 214476 kb
Host smart-e48aad79-8b85-4889-a5ca-2cb0c69baf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541868463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2541868463
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3062258516
Short name T60
Test name
Test status
Simulation time 604430282 ps
CPU time 3.9 seconds
Started Apr 21 12:26:09 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 209560 kb
Host smart-d085e34d-6445-46c6-886d-649be04429f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062258516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3062258516
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3034692776
Short name T657
Test name
Test status
Simulation time 386491931 ps
CPU time 5.52 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 208092 kb
Host smart-f9e2ca79-d944-4977-b65e-a0cdcb4a0160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034692776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3034692776
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3808255754
Short name T234
Test name
Test status
Simulation time 129988197 ps
CPU time 2.86 seconds
Started Apr 21 12:25:55 PM PDT 24
Finished Apr 21 12:25:58 PM PDT 24
Peak memory 210800 kb
Host smart-a81d33b3-aecf-4b06-bd44-f09e320a269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808255754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3808255754
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3217886409
Short name T775
Test name
Test status
Simulation time 325951700 ps
CPU time 4.67 seconds
Started Apr 21 12:26:07 PM PDT 24
Finished Apr 21 12:26:12 PM PDT 24
Peak memory 210204 kb
Host smart-76503053-dfdb-4809-8738-5b3e96f9aba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217886409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3217886409
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1825807945
Short name T845
Test name
Test status
Simulation time 591671427 ps
CPU time 3.79 seconds
Started Apr 21 12:26:55 PM PDT 24
Finished Apr 21 12:27:00 PM PDT 24
Peak memory 206088 kb
Host smart-ab21d897-13f4-4b05-95e0-a0e9d7d1b62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825807945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1825807945
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.195393995
Short name T549
Test name
Test status
Simulation time 237207061 ps
CPU time 8.02 seconds
Started Apr 21 12:26:55 PM PDT 24
Finished Apr 21 12:27:06 PM PDT 24
Peak memory 206940 kb
Host smart-7f8181dc-fa46-4353-a3a7-d0e02820c965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195393995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.195393995
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3619316453
Short name T594
Test name
Test status
Simulation time 495454156 ps
CPU time 4.18 seconds
Started Apr 21 12:26:05 PM PDT 24
Finished Apr 21 12:26:09 PM PDT 24
Peak memory 208508 kb
Host smart-f04b14ec-2495-44cc-9ca7-2e804e5a5c70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619316453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3619316453
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2053631265
Short name T411
Test name
Test status
Simulation time 653885050 ps
CPU time 7.04 seconds
Started Apr 21 12:25:48 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 206676 kb
Host smart-9f5e312c-f7f2-4d04-b259-635cb7cc8f89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053631265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2053631265
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.243363155
Short name T761
Test name
Test status
Simulation time 111346687 ps
CPU time 2.89 seconds
Started Apr 21 12:25:51 PM PDT 24
Finished Apr 21 12:25:54 PM PDT 24
Peak memory 208092 kb
Host smart-d46a04e8-4548-4d92-b730-6287b11d1824
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243363155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.243363155
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.758061363
Short name T270
Test name
Test status
Simulation time 41448506 ps
CPU time 1.72 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 209828 kb
Host smart-223d9d62-eb72-4bf4-aa00-cb0585d57f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758061363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.758061363
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3319025018
Short name T718
Test name
Test status
Simulation time 696769833 ps
CPU time 15.05 seconds
Started Apr 21 12:27:10 PM PDT 24
Finished Apr 21 12:27:26 PM PDT 24
Peak memory 207884 kb
Host smart-14e066bf-2e7a-435b-979c-3579e2e4411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319025018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3319025018
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.298392543
Short name T73
Test name
Test status
Simulation time 302572685 ps
CPU time 15.08 seconds
Started Apr 21 12:25:56 PM PDT 24
Finished Apr 21 12:26:12 PM PDT 24
Peak memory 215200 kb
Host smart-d4f0420d-30db-42e2-b49e-6f205d874091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298392543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.298392543
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2759055084
Short name T186
Test name
Test status
Simulation time 251733389 ps
CPU time 9.88 seconds
Started Apr 21 12:25:52 PM PDT 24
Finished Apr 21 12:26:03 PM PDT 24
Peak memory 219928 kb
Host smart-8d0aa946-94ad-4308-9e2f-36ce551a9f8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759055084 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2759055084
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2332647590
Short name T484
Test name
Test status
Simulation time 2289230842 ps
CPU time 25.95 seconds
Started Apr 21 12:26:55 PM PDT 24
Finished Apr 21 12:27:24 PM PDT 24
Peak memory 221972 kb
Host smart-b32a00e1-db65-4cfb-a752-d16fde70cf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332647590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2332647590
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3918386562
Short name T373
Test name
Test status
Simulation time 338420837 ps
CPU time 2.31 seconds
Started Apr 21 12:25:52 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 209256 kb
Host smart-1110dcb8-0471-48d8-b062-eb688ccd02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918386562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3918386562
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1839650517
Short name T453
Test name
Test status
Simulation time 21538236 ps
CPU time 0.75 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 205760 kb
Host smart-903a77e6-1c65-4e10-bf1d-cd5eb2be4f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839650517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1839650517
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2775551407
Short name T256
Test name
Test status
Simulation time 5392593797 ps
CPU time 49.95 seconds
Started Apr 21 12:25:44 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 214172 kb
Host smart-6b8b2920-3fa9-44d5-92b3-7d4698bf3d1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2775551407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2775551407
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.870787510
Short name T670
Test name
Test status
Simulation time 232476203 ps
CPU time 5.15 seconds
Started Apr 21 12:26:00 PM PDT 24
Finished Apr 21 12:26:06 PM PDT 24
Peak memory 214040 kb
Host smart-e3f3d32b-edff-4d8d-9da8-89dfdcea0f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870787510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.870787510
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.174446199
Short name T427
Test name
Test status
Simulation time 102444846 ps
CPU time 4.05 seconds
Started Apr 21 12:25:47 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 208488 kb
Host smart-98af3607-7dfc-4277-b01a-e59af6119683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174446199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.174446199
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.871149396
Short name T623
Test name
Test status
Simulation time 163050717 ps
CPU time 5.74 seconds
Started Apr 21 12:25:52 PM PDT 24
Finished Apr 21 12:25:59 PM PDT 24
Peak memory 209956 kb
Host smart-a4ebe7c2-e84a-48a2-bfdd-1362c0860897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871149396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.871149396
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2300666023
Short name T312
Test name
Test status
Simulation time 139443188 ps
CPU time 5.72 seconds
Started Apr 21 12:25:55 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 222136 kb
Host smart-4f5c1c83-bfb6-40f6-ad3b-3a1b2b0a79e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300666023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2300666023
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.31228673
Short name T44
Test name
Test status
Simulation time 104297864 ps
CPU time 3.71 seconds
Started Apr 21 12:25:56 PM PDT 24
Finished Apr 21 12:26:00 PM PDT 24
Peak memory 219744 kb
Host smart-41d6f451-2d13-42ea-8e3a-b057972f8e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31228673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.31228673
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2017161242
Short name T248
Test name
Test status
Simulation time 437016734 ps
CPU time 3.69 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 214124 kb
Host smart-692b87fe-542f-4af4-bb48-28b2d0eb148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017161242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2017161242
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2165766045
Short name T860
Test name
Test status
Simulation time 827734202 ps
CPU time 5.54 seconds
Started Apr 21 12:25:49 PM PDT 24
Finished Apr 21 12:25:55 PM PDT 24
Peak memory 207768 kb
Host smart-26707190-1485-4b93-b143-a651dd81dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165766045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2165766045
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1179198623
Short name T284
Test name
Test status
Simulation time 970820008 ps
CPU time 26.05 seconds
Started Apr 21 12:25:57 PM PDT 24
Finished Apr 21 12:26:24 PM PDT 24
Peak memory 207664 kb
Host smart-7a3cd237-f168-4213-a99e-7f53898e0cf7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179198623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1179198623
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2144230558
Short name T472
Test name
Test status
Simulation time 3044508323 ps
CPU time 7.49 seconds
Started Apr 21 12:25:40 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 208600 kb
Host smart-9b8d4e7e-d6b4-42ed-9973-7b7a3a66e798
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144230558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2144230558
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3771773286
Short name T532
Test name
Test status
Simulation time 36255435 ps
CPU time 2.51 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:54 PM PDT 24
Peak memory 206628 kb
Host smart-9534fd10-1a85-4ca8-87cc-a2a4e4d54e89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771773286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3771773286
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2161877377
Short name T812
Test name
Test status
Simulation time 164995090 ps
CPU time 2.57 seconds
Started Apr 21 12:25:57 PM PDT 24
Finished Apr 21 12:26:00 PM PDT 24
Peak memory 209336 kb
Host smart-91279333-da3c-4ff8-a567-73493c742acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161877377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2161877377
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.218723538
Short name T404
Test name
Test status
Simulation time 32860474 ps
CPU time 2.22 seconds
Started Apr 21 12:25:46 PM PDT 24
Finished Apr 21 12:25:50 PM PDT 24
Peak memory 208124 kb
Host smart-d2828d8d-ffba-4dcc-afad-29ec70624127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218723538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.218723538
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.22831340
Short name T210
Test name
Test status
Simulation time 16778108767 ps
CPU time 399.08 seconds
Started Apr 21 12:26:07 PM PDT 24
Finished Apr 21 12:32:46 PM PDT 24
Peak memory 222404 kb
Host smart-c6148d41-2a39-44d2-b612-6396315dd5b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22831340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.22831340
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.707001741
Short name T390
Test name
Test status
Simulation time 84522288 ps
CPU time 3.07 seconds
Started Apr 21 12:26:09 PM PDT 24
Finished Apr 21 12:26:13 PM PDT 24
Peak memory 207812 kb
Host smart-9fdb435d-15dc-4ba2-81b0-2a9f15ad3c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707001741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.707001741
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3983958130
Short name T773
Test name
Test status
Simulation time 116715294 ps
CPU time 2.06 seconds
Started Apr 21 12:25:37 PM PDT 24
Finished Apr 21 12:25:41 PM PDT 24
Peak memory 209904 kb
Host smart-b71cbc84-b126-4b1e-a909-2fe784adfedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983958130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3983958130
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3095112547
Short name T787
Test name
Test status
Simulation time 16496906 ps
CPU time 0.76 seconds
Started Apr 21 12:25:59 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 205796 kb
Host smart-8f0f9904-4d88-400c-af09-2fedcf5ce21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095112547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3095112547
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2623622323
Short name T144
Test name
Test status
Simulation time 730408084 ps
CPU time 10 seconds
Started Apr 21 12:26:13 PM PDT 24
Finished Apr 21 12:26:23 PM PDT 24
Peak memory 214040 kb
Host smart-4d17f0b0-25c2-4a48-842a-efc978b4f266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623622323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2623622323
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1099986232
Short name T841
Test name
Test status
Simulation time 7674254369 ps
CPU time 18.94 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:32 PM PDT 24
Peak memory 222664 kb
Host smart-8ce3b758-d78d-46e2-9d53-0b5774bb4a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099986232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1099986232
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2791873704
Short name T620
Test name
Test status
Simulation time 40601856 ps
CPU time 2.33 seconds
Started Apr 21 12:26:20 PM PDT 24
Finished Apr 21 12:26:23 PM PDT 24
Peak memory 209684 kb
Host smart-d1f47123-37bc-4662-b50b-24995eb2e66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791873704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2791873704
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3374235471
Short name T24
Test name
Test status
Simulation time 120322741 ps
CPU time 5.1 seconds
Started Apr 21 12:25:58 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 220720 kb
Host smart-1b4a040a-c400-49da-9253-c3b5f5f12602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374235471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3374235471
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3213139618
Short name T219
Test name
Test status
Simulation time 226550505 ps
CPU time 3.1 seconds
Started Apr 21 12:26:15 PM PDT 24
Finished Apr 21 12:26:19 PM PDT 24
Peak memory 220156 kb
Host smart-edb9f52c-e273-4085-b397-235f89239af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213139618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3213139618
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1306904456
Short name T539
Test name
Test status
Simulation time 123797352 ps
CPU time 3.64 seconds
Started Apr 21 12:26:01 PM PDT 24
Finished Apr 21 12:26:06 PM PDT 24
Peak memory 207252 kb
Host smart-9db0f970-c1b1-4b88-b3d0-79453b1b184a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306904456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1306904456
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2648279876
Short name T351
Test name
Test status
Simulation time 1626064033 ps
CPU time 4.87 seconds
Started Apr 21 12:25:53 PM PDT 24
Finished Apr 21 12:25:58 PM PDT 24
Peak memory 208228 kb
Host smart-40aaf355-ba47-40e6-b709-1acb1605bb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648279876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2648279876
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2445290081
Short name T103
Test name
Test status
Simulation time 114584852 ps
CPU time 1.83 seconds
Started Apr 21 12:25:42 PM PDT 24
Finished Apr 21 12:25:46 PM PDT 24
Peak memory 206552 kb
Host smart-8d36e0a2-9aaf-4aa8-a628-6d4f774d6384
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445290081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2445290081
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3641475064
Short name T866
Test name
Test status
Simulation time 552948310 ps
CPU time 4.82 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 206620 kb
Host smart-69df4fe6-2d97-43f8-8ef8-d6a5dfd363f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641475064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3641475064
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3484911455
Short name T550
Test name
Test status
Simulation time 581909896 ps
CPU time 6.29 seconds
Started Apr 21 12:26:01 PM PDT 24
Finished Apr 21 12:26:08 PM PDT 24
Peak memory 207688 kb
Host smart-37d044b3-b391-4e26-9b90-b67fb4d7c797
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484911455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3484911455
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.887676683
Short name T749
Test name
Test status
Simulation time 62903563 ps
CPU time 1.92 seconds
Started Apr 21 12:26:02 PM PDT 24
Finished Apr 21 12:26:05 PM PDT 24
Peak memory 207256 kb
Host smart-7ccbae45-4630-4c1c-a7cd-2fd42c784bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887676683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.887676683
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2079644778
Short name T194
Test name
Test status
Simulation time 420063788 ps
CPU time 2.81 seconds
Started Apr 21 12:25:59 PM PDT 24
Finished Apr 21 12:26:03 PM PDT 24
Peak memory 206472 kb
Host smart-91f35b5c-00fa-4254-9317-5b471e026385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079644778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2079644778
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.410020097
Short name T849
Test name
Test status
Simulation time 194187268 ps
CPU time 5.54 seconds
Started Apr 21 12:26:04 PM PDT 24
Finished Apr 21 12:26:10 PM PDT 24
Peak memory 209376 kb
Host smart-b5a5f788-f230-475a-a09d-e630e10836a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410020097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.410020097
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3694505565
Short name T371
Test name
Test status
Simulation time 372933688 ps
CPU time 2.69 seconds
Started Apr 21 12:26:11 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 210500 kb
Host smart-6df07141-fa4e-438f-af27-a122461bdd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694505565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3694505565
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.241500646
Short name T424
Test name
Test status
Simulation time 9902396 ps
CPU time 0.7 seconds
Started Apr 21 12:25:48 PM PDT 24
Finished Apr 21 12:25:52 PM PDT 24
Peak memory 205656 kb
Host smart-4cd689c3-c586-4b1f-b754-af0da2bc9431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241500646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.241500646
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3075088549
Short name T117
Test name
Test status
Simulation time 103826917 ps
CPU time 3.85 seconds
Started Apr 21 12:26:04 PM PDT 24
Finished Apr 21 12:26:08 PM PDT 24
Peak memory 214088 kb
Host smart-74831c34-6f96-48da-b7bf-92c5891a6c34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075088549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3075088549
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4922353
Short name T523
Test name
Test status
Simulation time 45210733 ps
CPU time 2.15 seconds
Started Apr 21 12:26:17 PM PDT 24
Finished Apr 21 12:26:19 PM PDT 24
Peak memory 218256 kb
Host smart-5ed91b43-429d-4962-9a06-35dec1d508c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4922353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4922353
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1600204727
Short name T503
Test name
Test status
Simulation time 162028946 ps
CPU time 3.71 seconds
Started Apr 21 12:26:10 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 218432 kb
Host smart-cfef3c13-3a48-47f9-a063-ef55af38ffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600204727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1600204727
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.276200845
Short name T870
Test name
Test status
Simulation time 622574482 ps
CPU time 9.6 seconds
Started Apr 21 12:26:05 PM PDT 24
Finished Apr 21 12:26:15 PM PDT 24
Peak memory 211384 kb
Host smart-01f771ab-9ef0-49af-a7de-f81864d6778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276200845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.276200845
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_random.374505802
Short name T755
Test name
Test status
Simulation time 247316850 ps
CPU time 6.87 seconds
Started Apr 21 12:26:17 PM PDT 24
Finished Apr 21 12:26:24 PM PDT 24
Peak memory 214108 kb
Host smart-ef673a8c-8cce-42b2-9b5a-58f9fd432f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374505802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.374505802
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2075744455
Short name T462
Test name
Test status
Simulation time 210855252 ps
CPU time 1.8 seconds
Started Apr 21 12:25:59 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 206548 kb
Host smart-ff64a0e1-bd12-4a0a-9972-681c0dcc819c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075744455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2075744455
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3074929338
Short name T813
Test name
Test status
Simulation time 23824401 ps
CPU time 2.01 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:19 PM PDT 24
Peak memory 207232 kb
Host smart-dec76b42-c71f-410e-9cb0-d24a5823f668
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074929338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3074929338
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.706824002
Short name T379
Test name
Test status
Simulation time 260540496 ps
CPU time 6.75 seconds
Started Apr 21 12:25:58 PM PDT 24
Finished Apr 21 12:26:05 PM PDT 24
Peak memory 207732 kb
Host smart-1640a72a-423a-49b3-b931-976329e3278a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706824002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.706824002
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1057840602
Short name T777
Test name
Test status
Simulation time 67387530 ps
CPU time 2.92 seconds
Started Apr 21 12:26:09 PM PDT 24
Finished Apr 21 12:26:13 PM PDT 24
Peak memory 208448 kb
Host smart-2953bcec-b6d1-4567-a7f7-4b4f204fa3ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057840602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1057840602
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.438994344
Short name T638
Test name
Test status
Simulation time 325636407 ps
CPU time 3.88 seconds
Started Apr 21 12:26:02 PM PDT 24
Finished Apr 21 12:26:07 PM PDT 24
Peak memory 208080 kb
Host smart-9fb283bd-a577-4d3d-b6de-df66b5b543ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438994344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.438994344
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.512437144
Short name T107
Test name
Test status
Simulation time 55314575 ps
CPU time 2.04 seconds
Started Apr 21 12:26:06 PM PDT 24
Finished Apr 21 12:26:08 PM PDT 24
Peak memory 206528 kb
Host smart-f2e6c4ba-2bfa-4b88-9170-fbeec4ed4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512437144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.512437144
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1579466716
Short name T675
Test name
Test status
Simulation time 209386983 ps
CPU time 8.01 seconds
Started Apr 21 12:25:57 PM PDT 24
Finished Apr 21 12:26:06 PM PDT 24
Peak memory 220212 kb
Host smart-800e0d3d-6737-4796-8d12-7dc1911788cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579466716 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1579466716
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3074971203
Short name T242
Test name
Test status
Simulation time 1233250886 ps
CPU time 3.37 seconds
Started Apr 21 12:26:15 PM PDT 24
Finished Apr 21 12:26:19 PM PDT 24
Peak memory 207516 kb
Host smart-42206cb2-7439-4b10-a34d-966d576e5054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074971203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3074971203
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2787437463
Short name T161
Test name
Test status
Simulation time 123839164 ps
CPU time 2.61 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:15 PM PDT 24
Peak memory 210100 kb
Host smart-d9b52fdd-d79e-4036-be04-24bbca3805b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787437463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2787437463
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1950883125
Short name T745
Test name
Test status
Simulation time 80718681 ps
CPU time 0.68 seconds
Started Apr 21 12:26:05 PM PDT 24
Finished Apr 21 12:26:06 PM PDT 24
Peak memory 205796 kb
Host smart-d2ac2920-f275-4973-b144-0941756c0465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950883125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1950883125
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4049120022
Short name T384
Test name
Test status
Simulation time 914878266 ps
CPU time 12.04 seconds
Started Apr 21 12:25:54 PM PDT 24
Finished Apr 21 12:26:07 PM PDT 24
Peak memory 214232 kb
Host smart-20261b58-a0c9-43df-b8ab-53357c06e7d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4049120022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4049120022
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2616254793
Short name T470
Test name
Test status
Simulation time 8185220875 ps
CPU time 97.43 seconds
Started Apr 21 12:26:36 PM PDT 24
Finished Apr 21 12:28:14 PM PDT 24
Peak memory 234104 kb
Host smart-2ab83060-ff4e-4037-b75a-c5ceca14af6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616254793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2616254793
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.369532456
Short name T765
Test name
Test status
Simulation time 85236591 ps
CPU time 3.97 seconds
Started Apr 21 12:26:30 PM PDT 24
Finished Apr 21 12:26:35 PM PDT 24
Peak memory 209256 kb
Host smart-0bb00288-2b71-4d79-8778-f04f788f9c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369532456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.369532456
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1654818308
Short name T90
Test name
Test status
Simulation time 54621990 ps
CPU time 3.13 seconds
Started Apr 21 12:26:15 PM PDT 24
Finished Apr 21 12:26:19 PM PDT 24
Peak memory 214264 kb
Host smart-824fc6a3-9d77-4c8e-afd4-be2a15e2a6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654818308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1654818308
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.740737394
Short name T313
Test name
Test status
Simulation time 274205997 ps
CPU time 5.01 seconds
Started Apr 21 12:26:10 PM PDT 24
Finished Apr 21 12:26:15 PM PDT 24
Peak memory 222292 kb
Host smart-1c7a1062-096b-4277-8d6f-bfc08dcf01fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740737394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.740737394
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1012825707
Short name T585
Test name
Test status
Simulation time 111751375 ps
CPU time 3.65 seconds
Started Apr 21 12:26:02 PM PDT 24
Finished Apr 21 12:26:06 PM PDT 24
Peak memory 208816 kb
Host smart-a8b30efe-0fa7-441c-b0d3-f4bdfc99406a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012825707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1012825707
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2192435669
Short name T457
Test name
Test status
Simulation time 4622304684 ps
CPU time 79.94 seconds
Started Apr 21 12:25:58 PM PDT 24
Finished Apr 21 12:27:18 PM PDT 24
Peak memory 208144 kb
Host smart-b96009f0-953e-4b81-9719-6d78dbfd384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192435669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2192435669
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2927529588
Short name T487
Test name
Test status
Simulation time 241141297 ps
CPU time 8.58 seconds
Started Apr 21 12:25:50 PM PDT 24
Finished Apr 21 12:25:59 PM PDT 24
Peak memory 208400 kb
Host smart-5b354e7f-9003-43c5-938e-757ad5d740a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927529588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2927529588
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2247526086
Short name T738
Test name
Test status
Simulation time 2543358102 ps
CPU time 6.31 seconds
Started Apr 21 12:25:55 PM PDT 24
Finished Apr 21 12:26:02 PM PDT 24
Peak memory 208448 kb
Host smart-d307d95f-3e74-45d8-be7f-bc31ab56ba71
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247526086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2247526086
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.610467470
Short name T337
Test name
Test status
Simulation time 258856590 ps
CPU time 5.11 seconds
Started Apr 21 12:26:09 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 208356 kb
Host smart-dc697d14-4302-4303-8039-d6c2787ca458
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610467470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.610467470
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.250451440
Short name T540
Test name
Test status
Simulation time 118760824 ps
CPU time 4.75 seconds
Started Apr 21 12:26:17 PM PDT 24
Finished Apr 21 12:26:22 PM PDT 24
Peak memory 206452 kb
Host smart-68a66560-b994-4cd3-9d77-fbc7d1003203
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250451440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.250451440
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2559552422
Short name T729
Test name
Test status
Simulation time 171841832 ps
CPU time 2.41 seconds
Started Apr 21 12:25:56 PM PDT 24
Finished Apr 21 12:25:59 PM PDT 24
Peak memory 209544 kb
Host smart-25842ac1-a4c2-4766-93e5-651d9353231f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559552422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2559552422
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2826501268
Short name T463
Test name
Test status
Simulation time 83597623 ps
CPU time 3.45 seconds
Started Apr 21 12:26:04 PM PDT 24
Finished Apr 21 12:26:08 PM PDT 24
Peak memory 208536 kb
Host smart-ec0068a1-d288-4597-b1f7-eacf6c16623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826501268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2826501268
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3546092031
Short name T322
Test name
Test status
Simulation time 2641861884 ps
CPU time 24.3 seconds
Started Apr 21 12:26:30 PM PDT 24
Finished Apr 21 12:26:54 PM PDT 24
Peak memory 221052 kb
Host smart-b24efe7a-16d7-42d8-ac78-193d526421e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546092031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3546092031
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.379700369
Short name T880
Test name
Test status
Simulation time 4128911338 ps
CPU time 66.86 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:27:38 PM PDT 24
Peak memory 214184 kb
Host smart-0c46cdd0-5d5e-425b-8f41-88f84c894855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379700369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.379700369
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2994542792
Short name T840
Test name
Test status
Simulation time 12588009 ps
CPU time 0.88 seconds
Started Apr 21 12:26:03 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 205752 kb
Host smart-0ab3f530-1ed0-4a96-b0b9-d3eb6cc96bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994542792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2994542792
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.792611061
Short name T888
Test name
Test status
Simulation time 699953226 ps
CPU time 18.39 seconds
Started Apr 21 12:26:00 PM PDT 24
Finished Apr 21 12:26:20 PM PDT 24
Peak memory 222228 kb
Host smart-c3262661-b867-42a3-ad65-be1802234c9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792611061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.792611061
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3883761910
Short name T1
Test name
Test status
Simulation time 21971777 ps
CPU time 1.75 seconds
Started Apr 21 12:26:04 PM PDT 24
Finished Apr 21 12:26:06 PM PDT 24
Peak memory 207684 kb
Host smart-a2a4eb6b-7a2d-473b-a8e5-eda23e6a3010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883761910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3883761910
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.863950026
Short name T874
Test name
Test status
Simulation time 683511977 ps
CPU time 8.71 seconds
Started Apr 21 12:26:09 PM PDT 24
Finished Apr 21 12:26:18 PM PDT 24
Peak memory 214120 kb
Host smart-2f29381f-84f0-4819-9b91-f6302626a0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863950026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.863950026
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2749689398
Short name T330
Test name
Test status
Simulation time 1129795780 ps
CPU time 8.41 seconds
Started Apr 21 12:26:07 PM PDT 24
Finished Apr 21 12:26:16 PM PDT 24
Peak memory 214384 kb
Host smart-61c3d812-f7cf-4532-b59f-3bb2c8ebbed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749689398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2749689398
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1473646572
Short name T223
Test name
Test status
Simulation time 507740373 ps
CPU time 4.39 seconds
Started Apr 21 12:25:56 PM PDT 24
Finished Apr 21 12:26:01 PM PDT 24
Peak memory 209980 kb
Host smart-776aa701-a776-443b-b0f3-701e0ad3799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473646572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1473646572
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2252791620
Short name T762
Test name
Test status
Simulation time 62222824 ps
CPU time 3.66 seconds
Started Apr 21 12:26:18 PM PDT 24
Finished Apr 21 12:26:27 PM PDT 24
Peak memory 214100 kb
Host smart-33410920-1150-4ff5-ae90-a247d9e53653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252791620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2252791620
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1506866069
Short name T676
Test name
Test status
Simulation time 1109477387 ps
CPU time 4.15 seconds
Started Apr 21 12:26:06 PM PDT 24
Finished Apr 21 12:26:11 PM PDT 24
Peak memory 208284 kb
Host smart-52f16a88-dbc5-4708-a0ae-796786298722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506866069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1506866069
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1912838874
Short name T271
Test name
Test status
Simulation time 421398759 ps
CPU time 2.55 seconds
Started Apr 21 12:26:15 PM PDT 24
Finished Apr 21 12:26:18 PM PDT 24
Peak memory 207168 kb
Host smart-99d73b6d-3690-4cc9-a707-30faa61aafda
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912838874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1912838874
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1493413933
Short name T132
Test name
Test status
Simulation time 544447201 ps
CPU time 7.19 seconds
Started Apr 21 12:26:02 PM PDT 24
Finished Apr 21 12:26:10 PM PDT 24
Peak memory 208256 kb
Host smart-99754d78-1c96-438b-9f79-a5ac0cc9825c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493413933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1493413933
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2213388232
Short name T611
Test name
Test status
Simulation time 56396763 ps
CPU time 3.05 seconds
Started Apr 21 12:26:16 PM PDT 24
Finished Apr 21 12:26:20 PM PDT 24
Peak memory 208460 kb
Host smart-9d6b1df0-e802-476f-8976-38dc552e54bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213388232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2213388232
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.24403212
Short name T430
Test name
Test status
Simulation time 239328213 ps
CPU time 4.93 seconds
Started Apr 21 12:25:55 PM PDT 24
Finished Apr 21 12:26:00 PM PDT 24
Peak memory 208712 kb
Host smart-44340584-587c-47aa-988f-02bbf1df3aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24403212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.24403212
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.28509373
Short name T781
Test name
Test status
Simulation time 788773648 ps
CPU time 4.95 seconds
Started Apr 21 12:26:00 PM PDT 24
Finished Apr 21 12:26:05 PM PDT 24
Peak memory 208540 kb
Host smart-1de62691-8909-4054-a4b3-0673c4b1bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28509373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.28509373
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.736298606
Short name T746
Test name
Test status
Simulation time 748691303 ps
CPU time 12.14 seconds
Started Apr 21 12:26:21 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 222472 kb
Host smart-cd9bc852-bb31-4d2a-ad4a-26c578c89d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736298606 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.736298606
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3245794288
Short name T632
Test name
Test status
Simulation time 175447809 ps
CPU time 4.32 seconds
Started Apr 21 12:26:08 PM PDT 24
Finished Apr 21 12:26:13 PM PDT 24
Peak memory 208632 kb
Host smart-d87133e6-b75a-40b4-8ede-64d3107889fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245794288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3245794288
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1122715770
Short name T728
Test name
Test status
Simulation time 102180846 ps
CPU time 2.45 seconds
Started Apr 21 12:26:24 PM PDT 24
Finished Apr 21 12:26:26 PM PDT 24
Peak memory 209892 kb
Host smart-91c51f2c-864e-40ce-b3bb-795e7a3d6208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122715770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1122715770
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.4104605160
Short name T634
Test name
Test status
Simulation time 18205135 ps
CPU time 0.77 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:24:46 PM PDT 24
Peak memory 205724 kb
Host smart-6de4cabc-649e-4926-bfc8-4cb81592b10d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104605160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.4104605160
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3083876175
Short name T397
Test name
Test status
Simulation time 28418579 ps
CPU time 2.41 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 214228 kb
Host smart-eebb0741-35ba-4cea-a122-18fb44388610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083876175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3083876175
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1929976229
Short name T486
Test name
Test status
Simulation time 78774062 ps
CPU time 3.02 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 209560 kb
Host smart-2521ae5c-8375-4c5a-81da-1379452686f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929976229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1929976229
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3869508778
Short name T850
Test name
Test status
Simulation time 48651070 ps
CPU time 1.88 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 208948 kb
Host smart-43042cf2-0a42-4a68-8f93-f4872025b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869508778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3869508778
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1483338182
Short name T751
Test name
Test status
Simulation time 128372163 ps
CPU time 4.9 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 218940 kb
Host smart-774e7928-a171-497f-acca-4c17d759cd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483338182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1483338182
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3705745392
Short name T514
Test name
Test status
Simulation time 2164243201 ps
CPU time 10.49 seconds
Started Apr 21 12:24:59 PM PDT 24
Finished Apr 21 12:25:11 PM PDT 24
Peak memory 209648 kb
Host smart-1ca2e30f-2129-49ab-87c6-34e0ba2c934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705745392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3705745392
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1511498019
Short name T12
Test name
Test status
Simulation time 4567350074 ps
CPU time 37.01 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:25:22 PM PDT 24
Peak memory 235864 kb
Host smart-c832bb20-eee5-4830-b979-261e27ffa483
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511498019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1511498019
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3941326524
Short name T553
Test name
Test status
Simulation time 52514994 ps
CPU time 2.66 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 206624 kb
Host smart-dced33cd-3acb-4385-b2be-493108a0abca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941326524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3941326524
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.950897245
Short name T422
Test name
Test status
Simulation time 1057812421 ps
CPU time 5.52 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:51 PM PDT 24
Peak memory 208088 kb
Host smart-d926bceb-8971-42ac-8430-f1ae5bf07528
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950897245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.950897245
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3278480680
Short name T654
Test name
Test status
Simulation time 154196126 ps
CPU time 2.93 seconds
Started Apr 21 12:25:06 PM PDT 24
Finished Apr 21 12:25:09 PM PDT 24
Peak memory 208544 kb
Host smart-5ce18349-972a-46b7-9d86-04a213055567
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278480680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3278480680
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.532543164
Short name T832
Test name
Test status
Simulation time 72293042 ps
CPU time 2.34 seconds
Started Apr 21 12:24:39 PM PDT 24
Finished Apr 21 12:24:42 PM PDT 24
Peak memory 206488 kb
Host smart-9827666e-7226-4bbf-9461-4728e85e510b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532543164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.532543164
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3999029058
Short name T666
Test name
Test status
Simulation time 166666068 ps
CPU time 4.28 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 209616 kb
Host smart-b3b90367-6a24-4673-bcd9-7d9004585f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999029058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3999029058
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3952251234
Short name T732
Test name
Test status
Simulation time 49342566 ps
CPU time 2.48 seconds
Started Apr 21 12:24:37 PM PDT 24
Finished Apr 21 12:24:41 PM PDT 24
Peak memory 208128 kb
Host smart-24a88a1f-9a0b-4f54-a342-f82b72841f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952251234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3952251234
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1033454305
Short name T814
Test name
Test status
Simulation time 5006214099 ps
CPU time 58.47 seconds
Started Apr 21 12:25:08 PM PDT 24
Finished Apr 21 12:26:07 PM PDT 24
Peak memory 215540 kb
Host smart-02c3c2ec-8e4b-4bcf-9765-1926e0e5ef61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033454305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1033454305
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3258476858
Short name T47
Test name
Test status
Simulation time 1357012322 ps
CPU time 13.66 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 219960 kb
Host smart-30c397b2-b89c-43d0-9d41-38d8b3aebc18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258476858 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3258476858
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.472621818
Short name T564
Test name
Test status
Simulation time 623103065 ps
CPU time 5.58 seconds
Started Apr 21 12:24:57 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 214248 kb
Host smart-5d304da9-f62d-4bba-8674-55a0bb03c0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472621818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.472621818
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3792256334
Short name T34
Test name
Test status
Simulation time 105130365 ps
CPU time 3.56 seconds
Started Apr 21 12:24:55 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 209624 kb
Host smart-2651b513-3e34-42d7-a72e-cead59cd0737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792256334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3792256334
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3870606462
Short name T708
Test name
Test status
Simulation time 20968010 ps
CPU time 1.04 seconds
Started Apr 21 12:25:52 PM PDT 24
Finished Apr 21 12:25:53 PM PDT 24
Peak memory 205972 kb
Host smart-11c0cd99-8285-4863-8c4d-fee986c0599d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870606462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3870606462
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.202522771
Short name T892
Test name
Test status
Simulation time 75233911 ps
CPU time 4.25 seconds
Started Apr 21 12:26:07 PM PDT 24
Finished Apr 21 12:26:12 PM PDT 24
Peak memory 214164 kb
Host smart-0978b44b-4481-49d2-b3f5-e4517bf1925c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202522771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.202522771
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.825788677
Short name T662
Test name
Test status
Simulation time 79777817 ps
CPU time 3.6 seconds
Started Apr 21 12:26:10 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 210332 kb
Host smart-45f989bb-2b9c-492a-b8d3-e7b129e66ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825788677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.825788677
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2206953930
Short name T647
Test name
Test status
Simulation time 149286775 ps
CPU time 4.83 seconds
Started Apr 21 12:26:08 PM PDT 24
Finished Apr 21 12:26:13 PM PDT 24
Peak memory 214120 kb
Host smart-4231d012-e6af-456d-9020-c876ca4f4fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206953930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2206953930
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.195137299
Short name T89
Test name
Test status
Simulation time 235693744 ps
CPU time 3.78 seconds
Started Apr 21 12:26:13 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 211028 kb
Host smart-082129b8-393a-4650-8f96-f99965dcb314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195137299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.195137299
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3596112730
Short name T628
Test name
Test status
Simulation time 51219477 ps
CPU time 2.41 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 214192 kb
Host smart-fea789ae-d668-452a-891e-696fcdceba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596112730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3596112730
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1859168907
Short name T356
Test name
Test status
Simulation time 1061320345 ps
CPU time 5.38 seconds
Started Apr 21 12:26:08 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 209692 kb
Host smart-01615fa5-bb92-4cc3-8e1c-1a816be078dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859168907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1859168907
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1377826282
Short name T501
Test name
Test status
Simulation time 254334318 ps
CPU time 4.11 seconds
Started Apr 21 12:26:19 PM PDT 24
Finished Apr 21 12:26:24 PM PDT 24
Peak memory 207980 kb
Host smart-56a534d9-9169-4754-a9c2-c2ccb385145c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377826282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1377826282
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4046269401
Short name T519
Test name
Test status
Simulation time 644227788 ps
CPU time 7.43 seconds
Started Apr 21 12:26:17 PM PDT 24
Finished Apr 21 12:26:24 PM PDT 24
Peak memory 207804 kb
Host smart-3cb11bca-d1e4-4c85-ae67-3c600fd83cd7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046269401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4046269401
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.361360477
Short name T494
Test name
Test status
Simulation time 66478289 ps
CPU time 2.38 seconds
Started Apr 21 12:25:58 PM PDT 24
Finished Apr 21 12:26:02 PM PDT 24
Peak memory 206844 kb
Host smart-a580a163-384c-4ce4-adb2-513cd30cdbcd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361360477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.361360477
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2308795871
Short name T646
Test name
Test status
Simulation time 32454240 ps
CPU time 2.33 seconds
Started Apr 21 12:26:08 PM PDT 24
Finished Apr 21 12:26:11 PM PDT 24
Peak memory 206420 kb
Host smart-74dc9076-d613-403c-b43c-94ee8e9cc9cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308795871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2308795871
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2041869397
Short name T469
Test name
Test status
Simulation time 355885863 ps
CPU time 2.75 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:15 PM PDT 24
Peak memory 209588 kb
Host smart-d0e8faa6-92af-46bc-8122-ca079d6043b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041869397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2041869397
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3375618318
Short name T421
Test name
Test status
Simulation time 210982895 ps
CPU time 2.77 seconds
Started Apr 21 12:26:07 PM PDT 24
Finished Apr 21 12:26:10 PM PDT 24
Peak memory 206508 kb
Host smart-efb18649-47b7-4dfd-a876-6a90d77340f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375618318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3375618318
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2199964468
Short name T858
Test name
Test status
Simulation time 628220313 ps
CPU time 23.83 seconds
Started Apr 21 12:26:11 PM PDT 24
Finished Apr 21 12:26:35 PM PDT 24
Peak memory 215916 kb
Host smart-b83fd432-36c4-4890-a244-87086bbf0658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199964468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2199964468
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2740970391
Short name T802
Test name
Test status
Simulation time 54205064 ps
CPU time 2.18 seconds
Started Apr 21 12:26:11 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 213960 kb
Host smart-06eacccf-2bef-41e5-b20c-b7fe33c57769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740970391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2740970391
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4176761409
Short name T191
Test name
Test status
Simulation time 72148258 ps
CPU time 2.2 seconds
Started Apr 21 12:26:07 PM PDT 24
Finished Apr 21 12:26:09 PM PDT 24
Peak memory 209568 kb
Host smart-11830c70-285f-499d-976d-8070654ec232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176761409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4176761409
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2949917753
Short name T806
Test name
Test status
Simulation time 40571661 ps
CPU time 0.87 seconds
Started Apr 21 12:26:25 PM PDT 24
Finished Apr 21 12:26:26 PM PDT 24
Peak memory 205764 kb
Host smart-b67cf0f7-c2ea-434b-bc3c-77deffaef84f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949917753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2949917753
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3045877607
Short name T19
Test name
Test status
Simulation time 72967279 ps
CPU time 2.73 seconds
Started Apr 21 12:26:08 PM PDT 24
Finished Apr 21 12:26:11 PM PDT 24
Peak memory 209788 kb
Host smart-5fa2ca61-001b-4212-88c5-84645390db61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045877607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3045877607
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.123289206
Short name T614
Test name
Test status
Simulation time 781572870 ps
CPU time 3.85 seconds
Started Apr 21 12:26:06 PM PDT 24
Finished Apr 21 12:26:10 PM PDT 24
Peak memory 208616 kb
Host smart-f22ec7e8-e85a-4bc5-9883-6c4b3c17621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123289206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.123289206
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1504130191
Short name T84
Test name
Test status
Simulation time 380830283 ps
CPU time 12.1 seconds
Started Apr 21 12:26:18 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 214112 kb
Host smart-63d746fb-65a1-4f57-970b-84be4641e44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504130191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1504130191
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3980487090
Short name T796
Test name
Test status
Simulation time 123894568 ps
CPU time 5.05 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 214232 kb
Host smart-0e7ca22b-420e-4255-8b73-cc512b068915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980487090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3980487090
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3058038906
Short name T723
Test name
Test status
Simulation time 40659404 ps
CPU time 2.73 seconds
Started Apr 21 12:26:11 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 207656 kb
Host smart-bfe0dfd7-e2df-4cab-84cf-aab4eed38fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058038906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3058038906
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.929948245
Short name T576
Test name
Test status
Simulation time 97456637 ps
CPU time 1.91 seconds
Started Apr 21 12:26:19 PM PDT 24
Finished Apr 21 12:26:22 PM PDT 24
Peak memory 206620 kb
Host smart-49c1bab5-a2c9-47b9-9c9b-e78b7e193ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929948245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.929948245
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.205822840
Short name T601
Test name
Test status
Simulation time 40267514 ps
CPU time 2.37 seconds
Started Apr 21 12:26:01 PM PDT 24
Finished Apr 21 12:26:04 PM PDT 24
Peak memory 206956 kb
Host smart-18f9c6b6-4e31-4e36-af82-39d21193adb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205822840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.205822840
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4132123600
Short name T768
Test name
Test status
Simulation time 269168835 ps
CPU time 3.77 seconds
Started Apr 21 12:26:03 PM PDT 24
Finished Apr 21 12:26:07 PM PDT 24
Peak memory 208368 kb
Host smart-db2842ee-e093-488b-bd7a-7176fc958e19
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132123600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4132123600
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.40897635
Short name T450
Test name
Test status
Simulation time 109585871 ps
CPU time 2.97 seconds
Started Apr 21 12:25:53 PM PDT 24
Finished Apr 21 12:25:56 PM PDT 24
Peak memory 206640 kb
Host smart-a9e1d194-04b5-49a3-8dde-667ae5efcacc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40897635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.40897635
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4210464658
Short name T14
Test name
Test status
Simulation time 464959355 ps
CPU time 8.15 seconds
Started Apr 21 12:26:22 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 208548 kb
Host smart-17f5b95d-9670-4ef1-9609-cf34416a737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210464658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4210464658
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2368061522
Short name T382
Test name
Test status
Simulation time 845158343 ps
CPU time 5.46 seconds
Started Apr 21 12:26:15 PM PDT 24
Finished Apr 21 12:26:21 PM PDT 24
Peak memory 208052 kb
Host smart-70ba7586-046a-4369-92af-9e8943ec488a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368061522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2368061522
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2668785446
Short name T4
Test name
Test status
Simulation time 3058735228 ps
CPU time 19.14 seconds
Started Apr 21 12:26:02 PM PDT 24
Finished Apr 21 12:26:22 PM PDT 24
Peak memory 207944 kb
Host smart-5bae1dec-bd3e-43c3-baae-a62e74eaad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668785446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2668785446
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1374504711
Short name T883
Test name
Test status
Simulation time 231536560 ps
CPU time 2.66 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 209944 kb
Host smart-8289da90-6896-452b-84b8-296573ca1221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374504711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1374504711
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3466763629
Short name T602
Test name
Test status
Simulation time 27074388 ps
CPU time 0.83 seconds
Started Apr 21 12:26:16 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 205836 kb
Host smart-df2f5ab9-7bcf-4031-a23f-1282418bc4cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466763629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3466763629
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.558856758
Short name T791
Test name
Test status
Simulation time 35387032 ps
CPU time 2.6 seconds
Started Apr 21 12:26:05 PM PDT 24
Finished Apr 21 12:26:08 PM PDT 24
Peak memory 215172 kb
Host smart-ef1235cd-eeab-4611-b05a-8b203151ef95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558856758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.558856758
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1128863047
Short name T429
Test name
Test status
Simulation time 151075032 ps
CPU time 2.09 seconds
Started Apr 21 12:26:25 PM PDT 24
Finished Apr 21 12:26:27 PM PDT 24
Peak memory 209688 kb
Host smart-17eb6b3d-36f2-49bb-b204-70ea1103882d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128863047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1128863047
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2698288997
Short name T143
Test name
Test status
Simulation time 98398990 ps
CPU time 1.52 seconds
Started Apr 21 12:26:19 PM PDT 24
Finished Apr 21 12:26:21 PM PDT 24
Peak memory 205932 kb
Host smart-fab3bd27-3b20-49da-a852-32b4842c5042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698288997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2698288997
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1131190226
Short name T826
Test name
Test status
Simulation time 330153482 ps
CPU time 11.11 seconds
Started Apr 21 12:26:24 PM PDT 24
Finished Apr 21 12:26:36 PM PDT 24
Peak memory 208704 kb
Host smart-7b2296eb-a401-4850-b93a-57f37f1c28a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131190226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1131190226
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2018653685
Short name T361
Test name
Test status
Simulation time 83378174 ps
CPU time 3.12 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 208320 kb
Host smart-3a5fdd2d-536e-428c-866e-21c7430e1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018653685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2018653685
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4176836874
Short name T805
Test name
Test status
Simulation time 3329677290 ps
CPU time 8.81 seconds
Started Apr 21 12:26:19 PM PDT 24
Finished Apr 21 12:26:28 PM PDT 24
Peak memory 208216 kb
Host smart-4dfd7c0f-de26-405c-80b5-215d068447cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176836874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4176836874
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.448716028
Short name T567
Test name
Test status
Simulation time 214836725 ps
CPU time 3.11 seconds
Started Apr 21 12:26:10 PM PDT 24
Finished Apr 21 12:26:14 PM PDT 24
Peak memory 208468 kb
Host smart-9a19cef4-fbd3-4a70-924f-309b881d5dae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448716028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.448716028
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3654719983
Short name T612
Test name
Test status
Simulation time 414805594 ps
CPU time 5.64 seconds
Started Apr 21 12:26:18 PM PDT 24
Finished Apr 21 12:26:24 PM PDT 24
Peak memory 208288 kb
Host smart-a1f77b70-0636-4d87-a83e-fa92f53fb2c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654719983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3654719983
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2074302170
Short name T296
Test name
Test status
Simulation time 267077025 ps
CPU time 2.32 seconds
Started Apr 21 12:26:16 PM PDT 24
Finished Apr 21 12:26:18 PM PDT 24
Peak memory 214164 kb
Host smart-61fa64f0-a380-4fd7-a171-7b1a20553c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074302170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2074302170
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3863599210
Short name T554
Test name
Test status
Simulation time 50997806 ps
CPU time 2.43 seconds
Started Apr 21 12:26:25 PM PDT 24
Finished Apr 21 12:26:27 PM PDT 24
Peak memory 206696 kb
Host smart-8fb23d15-14fb-4a14-a80e-f568e6b2c808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863599210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3863599210
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3624282456
Short name T716
Test name
Test status
Simulation time 1060156597 ps
CPU time 13.83 seconds
Started Apr 21 12:26:17 PM PDT 24
Finished Apr 21 12:26:32 PM PDT 24
Peak memory 215956 kb
Host smart-63a1ca10-239d-48f9-a9a7-af0c76bf260b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624282456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3624282456
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.939825818
Short name T387
Test name
Test status
Simulation time 423113701 ps
CPU time 4.96 seconds
Started Apr 21 12:26:12 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 209680 kb
Host smart-b55f77f2-d3a6-4428-b2d9-73f93f378b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939825818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.939825818
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1784004150
Short name T769
Test name
Test status
Simulation time 10788257 ps
CPU time 0.78 seconds
Started Apr 21 12:26:26 PM PDT 24
Finished Apr 21 12:26:28 PM PDT 24
Peak memory 205752 kb
Host smart-b28dfc6c-f9e3-4ced-88ff-a32fe157f654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784004150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1784004150
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2737864392
Short name T325
Test name
Test status
Simulation time 55417662 ps
CPU time 3.83 seconds
Started Apr 21 12:26:08 PM PDT 24
Finished Apr 21 12:26:13 PM PDT 24
Peak memory 214188 kb
Host smart-f85e4e78-72ce-4542-86ab-fd87943f8938
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737864392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2737864392
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.298428444
Short name T220
Test name
Test status
Simulation time 85542620 ps
CPU time 3.53 seconds
Started Apr 21 12:26:29 PM PDT 24
Finished Apr 21 12:26:33 PM PDT 24
Peak memory 209748 kb
Host smart-b552d5d6-737c-4010-995b-27df41391fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298428444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.298428444
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2875772175
Short name T320
Test name
Test status
Simulation time 849519576 ps
CPU time 22.54 seconds
Started Apr 21 12:26:19 PM PDT 24
Finished Apr 21 12:26:42 PM PDT 24
Peak memory 214084 kb
Host smart-3012c7ec-a906-43d1-8374-f7b43d4fc9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875772175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2875772175
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1106548888
Short name T703
Test name
Test status
Simulation time 142187573 ps
CPU time 2.54 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:31 PM PDT 24
Peak memory 209660 kb
Host smart-ff86ddeb-c249-4828-a93e-f53b4dde411e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106548888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1106548888
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1193224955
Short name T65
Test name
Test status
Simulation time 222593250 ps
CPU time 3.06 seconds
Started Apr 21 12:26:18 PM PDT 24
Finished Apr 21 12:26:22 PM PDT 24
Peak memory 208608 kb
Host smart-91072050-eda5-4fed-899e-67ce25eae540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193224955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1193224955
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3174735666
Short name T305
Test name
Test status
Simulation time 4425017150 ps
CPU time 11.34 seconds
Started Apr 21 12:26:14 PM PDT 24
Finished Apr 21 12:26:25 PM PDT 24
Peak memory 207856 kb
Host smart-2f1316f8-8028-4103-b290-ee6268c84347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174735666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3174735666
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1658200343
Short name T524
Test name
Test status
Simulation time 315579903 ps
CPU time 2.09 seconds
Started Apr 21 12:26:21 PM PDT 24
Finished Apr 21 12:26:24 PM PDT 24
Peak memory 207208 kb
Host smart-92baa080-1c4c-4cda-bdea-b094ea5c9d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658200343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1658200343
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2379408692
Short name T533
Test name
Test status
Simulation time 6844791326 ps
CPU time 23.21 seconds
Started Apr 21 12:26:20 PM PDT 24
Finished Apr 21 12:26:43 PM PDT 24
Peak memory 208368 kb
Host smart-9fec6583-6823-46c8-9625-f5e9566022e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379408692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2379408692
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1561618925
Short name T315
Test name
Test status
Simulation time 6202098324 ps
CPU time 71.12 seconds
Started Apr 21 12:26:16 PM PDT 24
Finished Apr 21 12:27:27 PM PDT 24
Peak memory 208692 kb
Host smart-3a01a694-0a87-4acf-b87f-fceb922945bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561618925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1561618925
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2582139563
Short name T648
Test name
Test status
Simulation time 888010368 ps
CPU time 6.65 seconds
Started Apr 21 12:26:11 PM PDT 24
Finished Apr 21 12:26:18 PM PDT 24
Peak memory 207752 kb
Host smart-b8007b52-a4ce-4f56-a920-e891d747c773
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582139563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2582139563
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2294958698
Short name T438
Test name
Test status
Simulation time 175680930 ps
CPU time 2.61 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 214148 kb
Host smart-09c2e8d6-681b-4480-a082-8acb94109668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294958698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2294958698
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2868019860
Short name T881
Test name
Test status
Simulation time 125211002 ps
CPU time 3.5 seconds
Started Apr 21 12:26:18 PM PDT 24
Finished Apr 21 12:26:22 PM PDT 24
Peak memory 208260 kb
Host smart-f326baf6-9e1b-4904-9946-f2ffb07acec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868019860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2868019860
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.941559139
Short name T719
Test name
Test status
Simulation time 168017398 ps
CPU time 3.71 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:33 PM PDT 24
Peak memory 208748 kb
Host smart-6552f58c-2a95-4804-8210-dec820ed16a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941559139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.941559139
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2550143824
Short name T859
Test name
Test status
Simulation time 336736145 ps
CPU time 6.12 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 210120 kb
Host smart-f5240bb4-554e-49ed-8d77-d7b6e7d40d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550143824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2550143824
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.870484708
Short name T477
Test name
Test status
Simulation time 15235648 ps
CPU time 0.77 seconds
Started Apr 21 12:26:24 PM PDT 24
Finished Apr 21 12:26:25 PM PDT 24
Peak memory 205716 kb
Host smart-3d3b5051-8760-4cf3-848b-1c29b94a1d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870484708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.870484708
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.4291467770
Short name T493
Test name
Test status
Simulation time 1350363393 ps
CPU time 30.12 seconds
Started Apr 21 12:26:56 PM PDT 24
Finished Apr 21 12:27:27 PM PDT 24
Peak memory 222216 kb
Host smart-7a41afad-2a8d-4137-bd1f-3cb26b676171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291467770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.4291467770
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1914690916
Short name T74
Test name
Test status
Simulation time 34851056 ps
CPU time 2.29 seconds
Started Apr 21 12:26:17 PM PDT 24
Finished Apr 21 12:26:20 PM PDT 24
Peak memory 214036 kb
Host smart-392e5924-d5ca-42a5-aff6-2fec7871127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914690916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1914690916
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3626747844
Short name T685
Test name
Test status
Simulation time 1014035198 ps
CPU time 7.15 seconds
Started Apr 21 12:26:33 PM PDT 24
Finished Apr 21 12:26:46 PM PDT 24
Peak memory 208888 kb
Host smart-6325161c-07eb-4144-81ea-21a4aac88c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626747844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3626747844
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3170080600
Short name T260
Test name
Test status
Simulation time 156973111 ps
CPU time 5.84 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 214052 kb
Host smart-5efce8d3-4feb-4327-8528-b8a79db2f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170080600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3170080600
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2043401199
Short name T59
Test name
Test status
Simulation time 48058671 ps
CPU time 3.22 seconds
Started Apr 21 12:26:32 PM PDT 24
Finished Apr 21 12:26:35 PM PDT 24
Peak memory 210180 kb
Host smart-1074f9c4-1677-44c6-a978-613db14d87f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043401199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2043401199
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2162512695
Short name T688
Test name
Test status
Simulation time 73958708 ps
CPU time 2.71 seconds
Started Apr 21 12:26:17 PM PDT 24
Finished Apr 21 12:26:21 PM PDT 24
Peak memory 208892 kb
Host smart-be0b7a3a-09b8-4cf9-a0cf-4abb2184d051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162512695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2162512695
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3852083892
Short name T417
Test name
Test status
Simulation time 735255134 ps
CPU time 8.78 seconds
Started Apr 21 12:26:24 PM PDT 24
Finished Apr 21 12:26:33 PM PDT 24
Peak memory 207504 kb
Host smart-e27d3af8-931c-4dd9-8846-b12617b91112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852083892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3852083892
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1287385318
Short name T80
Test name
Test status
Simulation time 106212429 ps
CPU time 3.54 seconds
Started Apr 21 12:26:16 PM PDT 24
Finished Apr 21 12:26:20 PM PDT 24
Peak memory 207964 kb
Host smart-d7899c70-0b98-4c3f-ad30-354d5ac3995f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287385318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1287385318
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1337451842
Short name T525
Test name
Test status
Simulation time 53199689 ps
CPU time 2.83 seconds
Started Apr 21 12:26:18 PM PDT 24
Finished Apr 21 12:26:21 PM PDT 24
Peak memory 206688 kb
Host smart-54a4a0d7-4ebe-4df7-9235-6769768d63d3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337451842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1337451842
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.719529734
Short name T511
Test name
Test status
Simulation time 79655776 ps
CPU time 1.69 seconds
Started Apr 21 12:26:15 PM PDT 24
Finished Apr 21 12:26:17 PM PDT 24
Peak memory 206532 kb
Host smart-e6895334-937f-4955-bf4a-3a182ff8be05
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719529734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.719529734
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2355586473
Short name T140
Test name
Test status
Simulation time 58983714 ps
CPU time 2.55 seconds
Started Apr 21 12:26:21 PM PDT 24
Finished Apr 21 12:26:24 PM PDT 24
Peak memory 215332 kb
Host smart-59de6db4-e5b4-4b31-8d23-4953dab736f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355586473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2355586473
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1061998469
Short name T557
Test name
Test status
Simulation time 2542150026 ps
CPU time 16.27 seconds
Started Apr 21 12:26:17 PM PDT 24
Finished Apr 21 12:26:33 PM PDT 24
Peak memory 207568 kb
Host smart-216c6406-4caf-477d-8bb0-f3bc3db9a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061998469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1061998469
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1318083712
Short name T596
Test name
Test status
Simulation time 304300773 ps
CPU time 11.78 seconds
Started Apr 21 12:26:18 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 219368 kb
Host smart-c957ee9d-3527-4ce2-983b-92f34bfd91e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318083712 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1318083712
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3905568559
Short name T297
Test name
Test status
Simulation time 888106342 ps
CPU time 9.06 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:26:37 PM PDT 24
Peak memory 209760 kb
Host smart-c2baf5ee-2deb-4125-a10f-35d1a259c878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905568559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3905568559
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3659726621
Short name T668
Test name
Test status
Simulation time 90691258 ps
CPU time 2.57 seconds
Started Apr 21 12:26:21 PM PDT 24
Finished Apr 21 12:26:24 PM PDT 24
Peak memory 209864 kb
Host smart-7778c470-29ff-46a8-93aa-c8ee8bbb5bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659726621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3659726621
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.674930869
Short name T621
Test name
Test status
Simulation time 12333354 ps
CPU time 0.75 seconds
Started Apr 21 12:26:30 PM PDT 24
Finished Apr 21 12:26:31 PM PDT 24
Peak memory 205776 kb
Host smart-8bb5b009-0ed5-4bd3-bc8d-07fb40282563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674930869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.674930869
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1688743346
Short name T316
Test name
Test status
Simulation time 209457659 ps
CPU time 3.81 seconds
Started Apr 21 12:26:29 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 214088 kb
Host smart-8bcdad8f-d515-487c-a179-f6d903874933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688743346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1688743346
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.633719615
Short name T21
Test name
Test status
Simulation time 63274080 ps
CPU time 2.95 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:26:35 PM PDT 24
Peak memory 218356 kb
Host smart-5e59432d-dcd5-4e47-b666-3b67c84dbc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633719615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.633719615
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2167197098
Short name T454
Test name
Test status
Simulation time 1305353944 ps
CPU time 8.33 seconds
Started Apr 21 12:26:21 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 209008 kb
Host smart-fd881e05-73ec-4149-99df-d44cf0ff0a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167197098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2167197098
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3884718609
Short name T891
Test name
Test status
Simulation time 1418815872 ps
CPU time 42.84 seconds
Started Apr 21 12:26:29 PM PDT 24
Finished Apr 21 12:27:18 PM PDT 24
Peak memory 214104 kb
Host smart-ae32b0ef-08a6-458c-82da-be4386e09556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884718609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3884718609
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3047618038
Short name T527
Test name
Test status
Simulation time 2028836177 ps
CPU time 54.85 seconds
Started Apr 21 12:26:26 PM PDT 24
Finished Apr 21 12:27:21 PM PDT 24
Peak memory 226508 kb
Host smart-9f5ab4e2-e5c4-4db6-be6c-0d34ecd530b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047618038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3047618038
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.791637261
Short name T206
Test name
Test status
Simulation time 414068711 ps
CPU time 6.3 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:35 PM PDT 24
Peak memory 220216 kb
Host smart-12cde62f-b9c7-4fcd-9ff1-f5438231ec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791637261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.791637261
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1749715237
Short name T714
Test name
Test status
Simulation time 861399157 ps
CPU time 9.77 seconds
Started Apr 21 12:26:30 PM PDT 24
Finished Apr 21 12:26:40 PM PDT 24
Peak memory 214224 kb
Host smart-dcbfe19a-3b42-4aca-9e85-41e070dd74b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749715237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1749715237
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1255687359
Short name T603
Test name
Test status
Simulation time 49179606 ps
CPU time 2.49 seconds
Started Apr 21 12:26:30 PM PDT 24
Finished Apr 21 12:26:33 PM PDT 24
Peak memory 207096 kb
Host smart-20daa2d4-a931-41b6-b0f5-0df64f2346f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255687359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1255687359
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.456367671
Short name T690
Test name
Test status
Simulation time 354929373 ps
CPU time 4.11 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:33 PM PDT 24
Peak memory 208440 kb
Host smart-9ad39621-f48f-4960-aabe-60ee37b4ff0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456367671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.456367671
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2772371396
Short name T266
Test name
Test status
Simulation time 1021766380 ps
CPU time 6.81 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:36 PM PDT 24
Peak memory 208580 kb
Host smart-931016ec-06a2-44f8-adf7-0979bd9f81f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772371396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2772371396
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4184782051
Short name T754
Test name
Test status
Simulation time 1915411975 ps
CPU time 8.32 seconds
Started Apr 21 12:26:33 PM PDT 24
Finished Apr 21 12:26:42 PM PDT 24
Peak memory 208384 kb
Host smart-e298abe4-aebf-4c3e-962c-5e40244ef386
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184782051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4184782051
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2481615984
Short name T283
Test name
Test status
Simulation time 669906902 ps
CPU time 7.53 seconds
Started Apr 21 12:26:20 PM PDT 24
Finished Apr 21 12:26:28 PM PDT 24
Peak memory 209932 kb
Host smart-4dd38a9b-2442-4f77-a754-3cbaa372db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481615984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2481615984
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.256161483
Short name T848
Test name
Test status
Simulation time 115984553 ps
CPU time 2.24 seconds
Started Apr 21 12:26:36 PM PDT 24
Finished Apr 21 12:26:38 PM PDT 24
Peak memory 206316 kb
Host smart-529c65bb-15be-4640-963e-a570d821c438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256161483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.256161483
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2742028609
Short name T363
Test name
Test status
Simulation time 693391423 ps
CPU time 12.56 seconds
Started Apr 21 12:26:26 PM PDT 24
Finished Apr 21 12:26:40 PM PDT 24
Peak memory 222184 kb
Host smart-d4c52fb4-2e6a-4767-ab04-051aac23f1e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742028609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2742028609
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2837554395
Short name T100
Test name
Test status
Simulation time 507480987 ps
CPU time 16.82 seconds
Started Apr 21 12:26:25 PM PDT 24
Finished Apr 21 12:26:42 PM PDT 24
Peak memory 222444 kb
Host smart-ab5bfca9-f816-4f26-b805-1fd0ece7a05c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837554395 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2837554395
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2021833793
Short name T789
Test name
Test status
Simulation time 53167462 ps
CPU time 2.66 seconds
Started Apr 21 12:26:36 PM PDT 24
Finished Apr 21 12:26:39 PM PDT 24
Peak memory 207412 kb
Host smart-6a1ea054-2048-4a41-abe1-36257199a628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021833793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2021833793
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1223866431
Short name T636
Test name
Test status
Simulation time 467257175 ps
CPU time 2.97 seconds
Started Apr 21 12:26:23 PM PDT 24
Finished Apr 21 12:26:26 PM PDT 24
Peak memory 210144 kb
Host smart-2d6c549a-cc3d-48d4-a26a-7cf34135194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223866431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1223866431
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1337179633
Short name T827
Test name
Test status
Simulation time 12759936 ps
CPU time 0.71 seconds
Started Apr 21 12:26:53 PM PDT 24
Finished Apr 21 12:26:54 PM PDT 24
Peak memory 205684 kb
Host smart-f7aa2ceb-7829-4abf-9145-142029e86136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337179633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1337179633
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3239249511
Short name T391
Test name
Test status
Simulation time 722924368 ps
CPU time 9.31 seconds
Started Apr 21 12:26:32 PM PDT 24
Finished Apr 21 12:26:42 PM PDT 24
Peak memory 214148 kb
Host smart-f9e2ed6f-7033-4257-b0af-543e3d497ad7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239249511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3239249511
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.4265557404
Short name T10
Test name
Test status
Simulation time 93461164 ps
CPU time 3.46 seconds
Started Apr 21 12:26:29 PM PDT 24
Finished Apr 21 12:26:33 PM PDT 24
Peak memory 214484 kb
Host smart-279b57f5-6a17-4f1b-9e19-d96b1ce87ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265557404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.4265557404
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.4045310521
Short name T68
Test name
Test status
Simulation time 93344298 ps
CPU time 1.58 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:26:29 PM PDT 24
Peak memory 206924 kb
Host smart-4f4f4ceb-47d3-420e-bbea-8f357d486ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045310521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4045310521
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.666818355
Short name T83
Test name
Test status
Simulation time 745987452 ps
CPU time 6.18 seconds
Started Apr 21 12:26:25 PM PDT 24
Finished Apr 21 12:26:32 PM PDT 24
Peak memory 222316 kb
Host smart-d2bfc95c-7277-47f7-97eb-577fcc9b2175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666818355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.666818355
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3946207021
Short name T237
Test name
Test status
Simulation time 447792506 ps
CPU time 2.81 seconds
Started Apr 21 12:26:33 PM PDT 24
Finished Apr 21 12:26:36 PM PDT 24
Peak memory 209180 kb
Host smart-d19924d0-804d-4fae-8906-49940fdfaa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946207021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3946207021
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3589296604
Short name T739
Test name
Test status
Simulation time 247388909 ps
CPU time 9.61 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:39 PM PDT 24
Peak memory 222600 kb
Host smart-6d1b4872-d5e6-4e95-84b9-f5bb6c58b497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589296604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3589296604
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.4287175664
Short name T580
Test name
Test status
Simulation time 361988752 ps
CPU time 9.39 seconds
Started Apr 21 12:26:22 PM PDT 24
Finished Apr 21 12:26:32 PM PDT 24
Peak memory 207860 kb
Host smart-3d0b5ef4-baec-41d8-a129-ce5a9a2db08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287175664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4287175664
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3718331041
Short name T680
Test name
Test status
Simulation time 776625270 ps
CPU time 18.85 seconds
Started Apr 21 12:26:40 PM PDT 24
Finished Apr 21 12:26:59 PM PDT 24
Peak memory 207608 kb
Host smart-097145b3-d30d-443b-b399-a805d917772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718331041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3718331041
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1674929353
Short name T584
Test name
Test status
Simulation time 253949066 ps
CPU time 6.19 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 207280 kb
Host smart-2b5b63ae-0904-49ef-ac38-1871c69128a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674929353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1674929353
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3866538405
Short name T801
Test name
Test status
Simulation time 3275108624 ps
CPU time 57.05 seconds
Started Apr 21 12:26:16 PM PDT 24
Finished Apr 21 12:27:14 PM PDT 24
Peak memory 208384 kb
Host smart-1b5153d8-ea50-4283-a7dc-827975de5c3c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866538405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3866538405
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1043513883
Short name T346
Test name
Test status
Simulation time 121165247 ps
CPU time 3.82 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:26:36 PM PDT 24
Peak memory 208120 kb
Host smart-dc92781d-dda6-43f7-9a06-046f0df354e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043513883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1043513883
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3834147166
Short name T819
Test name
Test status
Simulation time 1871452396 ps
CPU time 4.91 seconds
Started Apr 21 12:26:40 PM PDT 24
Finished Apr 21 12:26:46 PM PDT 24
Peak memory 209780 kb
Host smart-0d2e470c-7054-428e-a37c-7c5ac11f902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834147166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3834147166
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3633417172
Short name T733
Test name
Test status
Simulation time 32093172 ps
CPU time 2.22 seconds
Started Apr 21 12:26:41 PM PDT 24
Finished Apr 21 12:26:44 PM PDT 24
Peak memory 206412 kb
Host smart-10493c1c-ba19-4e5c-8b35-8de48154a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633417172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3633417172
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2938681640
Short name T321
Test name
Test status
Simulation time 12714623537 ps
CPU time 156.46 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:29:04 PM PDT 24
Peak memory 219632 kb
Host smart-02aef8e2-6e90-4eed-8f43-a9ee68efa359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938681640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2938681640
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.899245049
Short name T106
Test name
Test status
Simulation time 1936264192 ps
CPU time 40.32 seconds
Started Apr 21 12:26:29 PM PDT 24
Finished Apr 21 12:27:10 PM PDT 24
Peak memory 207768 kb
Host smart-94758545-7e4c-42ea-afc9-88224db260a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899245049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.899245049
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1137004348
Short name T664
Test name
Test status
Simulation time 509572558 ps
CPU time 2.34 seconds
Started Apr 21 12:26:58 PM PDT 24
Finished Apr 21 12:27:01 PM PDT 24
Peak memory 210032 kb
Host smart-3e1c218d-e810-4838-90e2-1d9b8cf6df75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137004348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1137004348
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.357344262
Short name T637
Test name
Test status
Simulation time 37638676 ps
CPU time 0.72 seconds
Started Apr 21 12:26:32 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 205760 kb
Host smart-e988d638-98ce-4540-83b6-9dd0dea2d7ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357344262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.357344262
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1859888756
Short name T27
Test name
Test status
Simulation time 2022650745 ps
CPU time 2.79 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 222548 kb
Host smart-42301ba5-a357-480c-b975-6594a885a72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859888756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1859888756
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3567930261
Short name T48
Test name
Test status
Simulation time 115164288 ps
CPU time 4.7 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:26:36 PM PDT 24
Peak memory 209660 kb
Host smart-61e2484c-0533-44cc-9710-21cb63e450f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567930261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3567930261
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.876427354
Short name T295
Test name
Test status
Simulation time 858075435 ps
CPU time 3.08 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:32 PM PDT 24
Peak memory 209536 kb
Host smart-81e653d8-0856-4e4c-8a2c-23e0f8afa9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876427354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.876427354
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3270572975
Short name T817
Test name
Test status
Simulation time 459092421 ps
CPU time 1.83 seconds
Started Apr 21 12:26:26 PM PDT 24
Finished Apr 21 12:26:28 PM PDT 24
Peak memory 219024 kb
Host smart-ba1c6dd0-5b2b-4387-b5c1-a614b00fd7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270572975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3270572975
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1882486099
Short name T280
Test name
Test status
Simulation time 296266774 ps
CPU time 8.89 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:38 PM PDT 24
Peak memory 209352 kb
Host smart-2bbbea39-4114-4dcc-8201-bc85ea7c3e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882486099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1882486099
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3460059022
Short name T709
Test name
Test status
Simulation time 65791256 ps
CPU time 2.88 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:38 PM PDT 24
Peak memory 207792 kb
Host smart-55cf856f-8806-4f8e-a48e-318de7f74578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460059022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3460059022
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2420566121
Short name T642
Test name
Test status
Simulation time 19133868 ps
CPU time 1.67 seconds
Started Apr 21 12:27:02 PM PDT 24
Finished Apr 21 12:27:04 PM PDT 24
Peak memory 206628 kb
Host smart-8406d5ff-d2b4-49d4-b97b-6ac3df906c26
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420566121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2420566121
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3890898400
Short name T843
Test name
Test status
Simulation time 784025641 ps
CPU time 2.68 seconds
Started Apr 21 12:26:19 PM PDT 24
Finished Apr 21 12:26:22 PM PDT 24
Peak memory 208272 kb
Host smart-e81b0d3f-7976-4346-9a8f-5b8a4fd7860c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890898400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3890898400
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2209291456
Short name T229
Test name
Test status
Simulation time 109301279 ps
CPU time 2.8 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:26:34 PM PDT 24
Peak memory 206516 kb
Host smart-d8809bcc-f8c0-4955-bf01-4c7201911653
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209291456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2209291456
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4291374917
Short name T202
Test name
Test status
Simulation time 38664507 ps
CPU time 2.61 seconds
Started Apr 21 12:27:04 PM PDT 24
Finished Apr 21 12:27:07 PM PDT 24
Peak memory 214224 kb
Host smart-bd31ddcb-0aee-4655-90bb-440e08e7245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291374917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4291374917
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2751774616
Short name T520
Test name
Test status
Simulation time 87738174 ps
CPU time 3.46 seconds
Started Apr 21 12:26:26 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 206584 kb
Host smart-a88c6e9b-e489-4c24-9979-c2fa60ef34d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751774616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2751774616
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.214719905
Short name T216
Test name
Test status
Simulation time 419247592 ps
CPU time 9.84 seconds
Started Apr 21 12:26:32 PM PDT 24
Finished Apr 21 12:26:43 PM PDT 24
Peak memory 220744 kb
Host smart-a2dd59fb-f3b7-437d-a4f4-9ca1ae79a729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214719905 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.214719905
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.140758584
Short name T753
Test name
Test status
Simulation time 235190040 ps
CPU time 4.14 seconds
Started Apr 21 12:26:32 PM PDT 24
Finished Apr 21 12:26:36 PM PDT 24
Peak memory 207272 kb
Host smart-341ae2a6-2b64-4be3-8ab8-2da7c62f40d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140758584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.140758584
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.122669843
Short name T613
Test name
Test status
Simulation time 135614322 ps
CPU time 1.93 seconds
Started Apr 21 12:26:27 PM PDT 24
Finished Apr 21 12:26:30 PM PDT 24
Peak memory 209396 kb
Host smart-d3c5af5e-c617-4ddf-be35-90fdb74b826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122669843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.122669843
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1123931310
Short name T502
Test name
Test status
Simulation time 17577685 ps
CPU time 0.69 seconds
Started Apr 21 12:26:35 PM PDT 24
Finished Apr 21 12:26:37 PM PDT 24
Peak memory 205884 kb
Host smart-22b094e5-2c7d-4a26-9891-fb0ab7c7a305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123931310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1123931310
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2719697817
Short name T799
Test name
Test status
Simulation time 141846216 ps
CPU time 4.92 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:40 PM PDT 24
Peak memory 214548 kb
Host smart-218fb339-dda6-4e88-a897-88ce9acdb8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719697817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2719697817
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4294416833
Short name T794
Test name
Test status
Simulation time 175707953 ps
CPU time 3.39 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:26:35 PM PDT 24
Peak memory 208160 kb
Host smart-b232074c-4086-4a51-a8ef-62c01acbf52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294416833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4294416833
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.508725830
Short name T661
Test name
Test status
Simulation time 1471956439 ps
CPU time 10.96 seconds
Started Apr 21 12:26:35 PM PDT 24
Finished Apr 21 12:26:47 PM PDT 24
Peak memory 208408 kb
Host smart-e2b766b0-41d8-4485-bc70-18eaf30589d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508725830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.508725830
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1223018244
Short name T275
Test name
Test status
Simulation time 280985487 ps
CPU time 7.4 seconds
Started Apr 21 12:26:31 PM PDT 24
Finished Apr 21 12:26:39 PM PDT 24
Peak memory 211616 kb
Host smart-1bfcb4b6-01f6-4a65-a820-edb3fa1c5118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223018244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1223018244
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.472364103
Short name T63
Test name
Test status
Simulation time 815721433 ps
CPU time 6.15 seconds
Started Apr 21 12:26:33 PM PDT 24
Finished Apr 21 12:26:40 PM PDT 24
Peak memory 220008 kb
Host smart-7bcbada9-8831-4add-8bd4-8c1c73e6f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472364103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.472364103
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2156133985
Short name T495
Test name
Test status
Simulation time 131044175 ps
CPU time 4.29 seconds
Started Apr 21 12:26:40 PM PDT 24
Finished Apr 21 12:26:45 PM PDT 24
Peak memory 209776 kb
Host smart-b634d7cd-9e59-423b-b4c5-ffee9b0f9f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156133985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2156133985
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1572985455
Short name T246
Test name
Test status
Simulation time 111977881 ps
CPU time 4.78 seconds
Started Apr 21 12:26:48 PM PDT 24
Finished Apr 21 12:26:53 PM PDT 24
Peak memory 208516 kb
Host smart-a4de70ef-bda8-4e0e-9e92-d70dcbb92aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572985455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1572985455
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3818526842
Short name T836
Test name
Test status
Simulation time 119148525 ps
CPU time 2.22 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:31 PM PDT 24
Peak memory 206600 kb
Host smart-843ff2f2-08fe-490d-b545-b63285e7c80a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818526842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3818526842
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3238644411
Short name T201
Test name
Test status
Simulation time 7256218758 ps
CPU time 23.09 seconds
Started Apr 21 12:26:35 PM PDT 24
Finished Apr 21 12:27:03 PM PDT 24
Peak memory 208468 kb
Host smart-668b9037-d58a-412d-af5f-33acec39dd7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238644411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3238644411
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3159846230
Short name T767
Test name
Test status
Simulation time 9451793693 ps
CPU time 50.18 seconds
Started Apr 21 12:26:42 PM PDT 24
Finished Apr 21 12:27:32 PM PDT 24
Peak memory 208960 kb
Host smart-01087fdb-c903-4cf8-97ae-c2b7437f04e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159846230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3159846230
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.362880739
Short name T506
Test name
Test status
Simulation time 247561535 ps
CPU time 2.98 seconds
Started Apr 21 12:26:41 PM PDT 24
Finished Apr 21 12:26:45 PM PDT 24
Peak memory 215552 kb
Host smart-e08711ed-61fc-499d-9560-74a75260da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362880739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.362880739
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.986413818
Short name T485
Test name
Test status
Simulation time 424878066 ps
CPU time 3.29 seconds
Started Apr 21 12:26:33 PM PDT 24
Finished Apr 21 12:26:37 PM PDT 24
Peak memory 206780 kb
Host smart-e416f590-b1d6-4014-b383-f4477ca01699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986413818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.986413818
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2307978704
Short name T126
Test name
Test status
Simulation time 274019454 ps
CPU time 10.58 seconds
Started Apr 21 12:26:57 PM PDT 24
Finished Apr 21 12:27:08 PM PDT 24
Peak memory 219396 kb
Host smart-86917154-5003-488d-a35a-a78dc4e59ed9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307978704 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2307978704
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.970617121
Short name T640
Test name
Test status
Simulation time 244040085 ps
CPU time 5.6 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:40 PM PDT 24
Peak memory 208532 kb
Host smart-38cec750-12f2-4e73-abc1-25e98ed5efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970617121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.970617121
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1769907876
Short name T785
Test name
Test status
Simulation time 33434250 ps
CPU time 2.08 seconds
Started Apr 21 12:26:39 PM PDT 24
Finished Apr 21 12:26:42 PM PDT 24
Peak memory 209596 kb
Host smart-280aa1f7-4c46-4080-9869-31b6ec1eda23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769907876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1769907876
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1611853636
Short name T595
Test name
Test status
Simulation time 98211529 ps
CPU time 0.85 seconds
Started Apr 21 12:26:36 PM PDT 24
Finished Apr 21 12:26:38 PM PDT 24
Peak memory 205836 kb
Host smart-34b55932-128b-4813-82f2-c6cc20310217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611853636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1611853636
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1509390228
Short name T889
Test name
Test status
Simulation time 615219355 ps
CPU time 2.69 seconds
Started Apr 21 12:26:33 PM PDT 24
Finished Apr 21 12:26:36 PM PDT 24
Peak memory 222568 kb
Host smart-b825755b-af73-4d36-942c-7d592a2183ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509390228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1509390228
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3344839762
Short name T233
Test name
Test status
Simulation time 256181201 ps
CPU time 3.23 seconds
Started Apr 21 12:26:35 PM PDT 24
Finished Apr 21 12:26:39 PM PDT 24
Peak memory 209592 kb
Host smart-5853d54f-2551-46a8-9811-fe9653bce8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344839762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3344839762
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2793972700
Short name T370
Test name
Test status
Simulation time 2654549346 ps
CPU time 14.38 seconds
Started Apr 21 12:26:36 PM PDT 24
Finished Apr 21 12:26:50 PM PDT 24
Peak memory 209476 kb
Host smart-ddfbe748-4dea-4807-a452-468e09f96bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793972700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2793972700
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3485674573
Short name T797
Test name
Test status
Simulation time 258050430 ps
CPU time 2.37 seconds
Started Apr 21 12:26:40 PM PDT 24
Finished Apr 21 12:26:43 PM PDT 24
Peak memory 209112 kb
Host smart-a5c141d1-1da1-4a51-bcbb-0754e8d728bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485674573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3485674573
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3369217380
Short name T54
Test name
Test status
Simulation time 858262101 ps
CPU time 3.78 seconds
Started Apr 21 12:26:44 PM PDT 24
Finished Apr 21 12:26:49 PM PDT 24
Peak memory 219988 kb
Host smart-df86b5cb-c13b-4857-b74e-016d3270a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369217380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3369217380
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.512123790
Short name T822
Test name
Test status
Simulation time 2218383996 ps
CPU time 27.05 seconds
Started Apr 21 12:26:33 PM PDT 24
Finished Apr 21 12:27:01 PM PDT 24
Peak memory 208324 kb
Host smart-4fd126e2-47b5-4f24-9755-eee1b361b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512123790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.512123790
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2501685021
Short name T721
Test name
Test status
Simulation time 141335354 ps
CPU time 1.97 seconds
Started Apr 21 12:26:40 PM PDT 24
Finished Apr 21 12:26:43 PM PDT 24
Peak memory 208276 kb
Host smart-4fc43510-ddf9-4669-9de7-25f304c07745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501685021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2501685021
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1324337860
Short name T674
Test name
Test status
Simulation time 40269597 ps
CPU time 2.72 seconds
Started Apr 21 12:26:30 PM PDT 24
Finished Apr 21 12:26:33 PM PDT 24
Peak memory 208756 kb
Host smart-b0172300-5fab-4c2e-b3a4-e8eff3238b71
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324337860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1324337860
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2404583683
Short name T684
Test name
Test status
Simulation time 314704792 ps
CPU time 2.76 seconds
Started Apr 21 12:26:38 PM PDT 24
Finished Apr 21 12:26:42 PM PDT 24
Peak memory 206604 kb
Host smart-5e4de150-629f-4c33-a399-73ce4dbf34c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404583683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2404583683
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2056178541
Short name T499
Test name
Test status
Simulation time 374096417 ps
CPU time 3.32 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:38 PM PDT 24
Peak memory 208552 kb
Host smart-6bc41b2c-dc39-4c1c-b10e-f4bc38eb73bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056178541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2056178541
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3779897940
Short name T641
Test name
Test status
Simulation time 37471510 ps
CPU time 1.93 seconds
Started Apr 21 12:26:34 PM PDT 24
Finished Apr 21 12:26:37 PM PDT 24
Peak memory 208516 kb
Host smart-3619e390-0ab9-43fa-a2bc-a3288c50aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779897940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3779897940
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3286598363
Short name T383
Test name
Test status
Simulation time 256517929 ps
CPU time 2.59 seconds
Started Apr 21 12:26:28 PM PDT 24
Finished Apr 21 12:26:31 PM PDT 24
Peak memory 208616 kb
Host smart-0eece435-0cde-4ba5-a2f0-00e3285a8734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286598363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3286598363
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.4239102826
Short name T190
Test name
Test status
Simulation time 2422695917 ps
CPU time 15.76 seconds
Started Apr 21 12:26:41 PM PDT 24
Finished Apr 21 12:26:57 PM PDT 24
Peak memory 221516 kb
Host smart-ba9af689-67e7-470c-a6eb-0f1cafe1087b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239102826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.4239102826
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1572971486
Short name T125
Test name
Test status
Simulation time 217260619 ps
CPU time 5.92 seconds
Started Apr 21 12:26:33 PM PDT 24
Finished Apr 21 12:26:40 PM PDT 24
Peak memory 220060 kb
Host smart-170a9303-77a9-4e12-b5ba-d1e433db375e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572971486 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1572971486
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3868283229
Short name T607
Test name
Test status
Simulation time 93431351 ps
CPU time 4.36 seconds
Started Apr 21 12:26:38 PM PDT 24
Finished Apr 21 12:26:44 PM PDT 24
Peak memory 208900 kb
Host smart-e708be54-2ac4-4f01-8901-4dea316b267f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868283229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3868283229
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3791769798
Short name T410
Test name
Test status
Simulation time 16811846 ps
CPU time 0.81 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:47 PM PDT 24
Peak memory 205784 kb
Host smart-a02011ac-2c4b-4870-9f73-6c3c79345e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791769798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3791769798
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1073291352
Short name T199
Test name
Test status
Simulation time 39637896 ps
CPU time 2.92 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:01 PM PDT 24
Peak memory 214116 kb
Host smart-a0afce6b-fc95-41fb-991b-7bdb3176fe70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073291352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1073291352
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.296323926
Short name T37
Test name
Test status
Simulation time 174631751 ps
CPU time 3.33 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 209344 kb
Host smart-53d4c11a-9d2c-4be0-ab64-3e1338287515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296323926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.296323926
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3384709148
Short name T522
Test name
Test status
Simulation time 1156327061 ps
CPU time 15.58 seconds
Started Apr 21 12:24:48 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 214108 kb
Host smart-d986f38b-cfa9-4013-a4ae-2602ca131ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384709148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3384709148
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3931289745
Short name T292
Test name
Test status
Simulation time 331678353 ps
CPU time 4.92 seconds
Started Apr 21 12:25:06 PM PDT 24
Finished Apr 21 12:25:12 PM PDT 24
Peak memory 220488 kb
Host smart-a333c78d-4eb1-40c4-b29f-287f085f91d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931289745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3931289745
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2615059202
Short name T780
Test name
Test status
Simulation time 860201440 ps
CPU time 10.35 seconds
Started Apr 21 12:24:54 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 222328 kb
Host smart-393e127a-8f90-4f80-b693-efe9fec9ae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615059202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2615059202
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3473527944
Short name T608
Test name
Test status
Simulation time 65910743 ps
CPU time 2.81 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:24:48 PM PDT 24
Peak memory 215340 kb
Host smart-c070dab3-9bc5-44c4-b863-a2bf3d6f8a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473527944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3473527944
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2606999723
Short name T820
Test name
Test status
Simulation time 6774256744 ps
CPU time 36.98 seconds
Started Apr 21 12:25:00 PM PDT 24
Finished Apr 21 12:25:38 PM PDT 24
Peak memory 208168 kb
Host smart-bceb6426-72dc-432c-8d3f-fdba0850cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606999723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2606999723
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4168790148
Short name T343
Test name
Test status
Simulation time 66741177 ps
CPU time 2.32 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:24:45 PM PDT 24
Peak memory 207136 kb
Host smart-ad2d4081-23d2-4d9b-8c78-03cf481d1b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168790148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4168790148
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3170701347
Short name T531
Test name
Test status
Simulation time 3380493231 ps
CPU time 6.9 seconds
Started Apr 21 12:24:41 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 208552 kb
Host smart-a8a7ee91-b4ca-491c-ae92-3c4885525bb6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170701347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3170701347
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.561259904
Short name T689
Test name
Test status
Simulation time 88317431 ps
CPU time 3.91 seconds
Started Apr 21 12:24:43 PM PDT 24
Finished Apr 21 12:24:47 PM PDT 24
Peak memory 208364 kb
Host smart-99a7a055-d122-4324-9226-4435ca6c3ca7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561259904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.561259904
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1415437104
Short name T483
Test name
Test status
Simulation time 4311596411 ps
CPU time 36.17 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:25:29 PM PDT 24
Peak memory 208784 kb
Host smart-944453ad-f9a9-4198-a5f2-4d7dfd9fe9fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415437104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1415437104
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1039336198
Short name T772
Test name
Test status
Simulation time 1431736225 ps
CPU time 4.32 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 214160 kb
Host smart-6f533922-2957-4b1e-a9c4-6878a5807cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039336198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1039336198
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1212473261
Short name T398
Test name
Test status
Simulation time 80313729 ps
CPU time 2.4 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 206352 kb
Host smart-ad836f9e-7da3-44be-808b-538e562d5d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212473261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1212473261
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1885052001
Short name T885
Test name
Test status
Simulation time 2130599373 ps
CPU time 24.69 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:25:18 PM PDT 24
Peak memory 219924 kb
Host smart-b26783ff-54cb-4877-8afb-5d780500f17c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885052001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1885052001
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.364707489
Short name T694
Test name
Test status
Simulation time 205448300 ps
CPU time 3.91 seconds
Started Apr 21 12:24:54 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 207796 kb
Host smart-712fa9b6-9443-439a-979c-6f74f1b00135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364707489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.364707489
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.501870964
Short name T747
Test name
Test status
Simulation time 2039778587 ps
CPU time 18.18 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 210160 kb
Host smart-325e984c-22e3-488d-a6cc-87bb58007e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501870964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.501870964
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2933145345
Short name T474
Test name
Test status
Simulation time 48163255 ps
CPU time 0.81 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:24:43 PM PDT 24
Peak memory 205804 kb
Host smart-457c6db9-fbee-429c-8bfa-96bfd3a14e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933145345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2933145345
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2663322697
Short name T610
Test name
Test status
Simulation time 100425201 ps
CPU time 3.72 seconds
Started Apr 21 12:24:58 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 214128 kb
Host smart-6997726e-ec99-4685-8cec-b353513792b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663322697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2663322697
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1679998026
Short name T547
Test name
Test status
Simulation time 210400227 ps
CPU time 3.08 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 208400 kb
Host smart-58febab8-ce37-4091-94f3-bad924e0e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679998026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1679998026
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3978821823
Short name T712
Test name
Test status
Simulation time 270982782 ps
CPU time 4.24 seconds
Started Apr 21 12:24:58 PM PDT 24
Finished Apr 21 12:25:03 PM PDT 24
Peak memory 214108 kb
Host smart-5be60e29-9b33-4fab-be28-9a2fa9c79892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978821823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3978821823
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3104692658
Short name T652
Test name
Test status
Simulation time 84689208 ps
CPU time 3.95 seconds
Started Apr 21 12:24:55 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 222364 kb
Host smart-608c1f6b-2471-49e0-9edb-75b0fcb26ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104692658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3104692658
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.35835475
Short name T760
Test name
Test status
Simulation time 231586227 ps
CPU time 3.51 seconds
Started Apr 21 12:25:00 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 207828 kb
Host smart-c78bf1c0-fb92-4827-931c-eeca76c94cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35835475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.35835475
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2957914759
Short name T534
Test name
Test status
Simulation time 209224843 ps
CPU time 2.87 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 208016 kb
Host smart-95ea3faa-f3d6-4ae5-a905-dfe5d8b03813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957914759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2957914759
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2457048630
Short name T678
Test name
Test status
Simulation time 912375373 ps
CPU time 6.56 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 207644 kb
Host smart-18ac3f3d-fa68-42a0-a40c-5b2b111e8dd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457048630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2457048630
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3929089138
Short name T409
Test name
Test status
Simulation time 3626434438 ps
CPU time 11.01 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 208172 kb
Host smart-0194344c-130b-4df7-a888-2f6432b32acc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929089138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3929089138
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3377863637
Short name T402
Test name
Test status
Simulation time 705289874 ps
CPU time 16.55 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:25:09 PM PDT 24
Peak memory 207700 kb
Host smart-18878806-19ff-464e-8680-76f9903c904c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377863637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3377863637
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.4038789655
Short name T240
Test name
Test status
Simulation time 266787166 ps
CPU time 3.2 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 210076 kb
Host smart-e8bc4b4d-a3dd-45e3-a8de-b7aea32ef04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038789655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4038789655
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.34385100
Short name T697
Test name
Test status
Simulation time 573650510 ps
CPU time 12.71 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 207712 kb
Host smart-501b5267-6d93-4db3-aedf-f6198ef5b407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34385100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.34385100
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3994001090
Short name T244
Test name
Test status
Simulation time 2923530993 ps
CPU time 14.94 seconds
Started Apr 21 12:24:47 PM PDT 24
Finished Apr 21 12:25:03 PM PDT 24
Peak memory 214932 kb
Host smart-96980f04-eb08-4d5e-b8eb-3dd84cb797d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994001090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3994001090
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1420832157
Short name T332
Test name
Test status
Simulation time 315202593 ps
CPU time 6.8 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:04 PM PDT 24
Peak memory 218000 kb
Host smart-88c868d9-06e6-4d78-91c1-4dbea775ac58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420832157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1420832157
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3010387170
Short name T552
Test name
Test status
Simulation time 72652964 ps
CPU time 3.02 seconds
Started Apr 21 12:24:41 PM PDT 24
Finished Apr 21 12:24:45 PM PDT 24
Peak memory 209824 kb
Host smart-fc705133-3d92-40ad-8919-f9eabc00d324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010387170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3010387170
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1243829169
Short name T97
Test name
Test status
Simulation time 13505578 ps
CPU time 0.73 seconds
Started Apr 21 12:25:14 PM PDT 24
Finished Apr 21 12:25:15 PM PDT 24
Peak memory 205784 kb
Host smart-1490d26f-d2ea-48e1-8f59-d14bfbea93d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243829169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1243829169
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.886886182
Short name T314
Test name
Test status
Simulation time 244583826 ps
CPU time 12.51 seconds
Started Apr 21 12:25:07 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 215660 kb
Host smart-098d21ea-1a16-4a75-b0b6-25dc1758c4d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=886886182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.886886182
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3098160936
Short name T20
Test name
Test status
Simulation time 143010508 ps
CPU time 1.94 seconds
Started Apr 21 12:25:13 PM PDT 24
Finished Apr 21 12:25:16 PM PDT 24
Peak memory 214316 kb
Host smart-2c145a5e-dfc6-4ae8-ada7-2adcaede23f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098160936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3098160936
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.354852420
Short name T69
Test name
Test status
Simulation time 666697733 ps
CPU time 3.89 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 208340 kb
Host smart-ad58e8fb-3f1b-40ef-a713-4627f98f5dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354852420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.354852420
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.4211785511
Short name T665
Test name
Test status
Simulation time 30312536 ps
CPU time 2.23 seconds
Started Apr 21 12:25:05 PM PDT 24
Finished Apr 21 12:25:08 PM PDT 24
Peak memory 208312 kb
Host smart-38fac3ef-4807-4b85-99ac-fb3b1351dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211785511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.4211785511
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.607589550
Short name T261
Test name
Test status
Simulation time 1969533079 ps
CPU time 54.41 seconds
Started Apr 21 12:24:44 PM PDT 24
Finished Apr 21 12:25:39 PM PDT 24
Peak memory 218948 kb
Host smart-db8c17df-7947-4ba3-ba0b-79e2b7e58941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607589550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.607589550
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2865693571
Short name T803
Test name
Test status
Simulation time 252076236 ps
CPU time 5.18 seconds
Started Apr 21 12:25:17 PM PDT 24
Finished Apr 21 12:25:23 PM PDT 24
Peak memory 220052 kb
Host smart-fbd78b64-512c-468c-bb33-88721d9041e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865693571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2865693571
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1902630066
Short name T367
Test name
Test status
Simulation time 362713941 ps
CPU time 5.36 seconds
Started Apr 21 12:24:45 PM PDT 24
Finished Apr 21 12:24:52 PM PDT 24
Peak memory 208108 kb
Host smart-9eb64afd-e729-4250-9b1c-79f7e3a98bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902630066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1902630066
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.951492336
Short name T707
Test name
Test status
Simulation time 140451888 ps
CPU time 2.32 seconds
Started Apr 21 12:24:57 PM PDT 24
Finished Apr 21 12:25:00 PM PDT 24
Peak memory 206604 kb
Host smart-1970107a-1768-4849-9c40-676a684c373c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951492336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.951492336
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.264904612
Short name T572
Test name
Test status
Simulation time 259969340 ps
CPU time 2.89 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 206604 kb
Host smart-3162225f-a0ed-4c87-9773-9d882fb408d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264904612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.264904612
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1021978935
Short name T578
Test name
Test status
Simulation time 124500321 ps
CPU time 4.16 seconds
Started Apr 21 12:25:02 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 206596 kb
Host smart-530679f1-3d00-4d9a-ae7e-f8c593960687
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021978935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1021978935
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2666710115
Short name T13
Test name
Test status
Simulation time 180390084 ps
CPU time 6.77 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 208268 kb
Host smart-64cfd04c-d8e4-42e3-82dd-97cc6362c601
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666710115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2666710115
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.520452025
Short name T336
Test name
Test status
Simulation time 160388331 ps
CPU time 4.26 seconds
Started Apr 21 12:25:04 PM PDT 24
Finished Apr 21 12:25:09 PM PDT 24
Peak memory 214148 kb
Host smart-95927af0-39b5-415f-a50e-00414b2f995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520452025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.520452025
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1704426959
Short name T380
Test name
Test status
Simulation time 230682659 ps
CPU time 4.96 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 207652 kb
Host smart-f3ee3dac-d2e8-45a0-9b4b-c4c2043d70e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704426959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1704426959
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3140829268
Short name T766
Test name
Test status
Simulation time 1303571200 ps
CPU time 43.97 seconds
Started Apr 21 12:24:58 PM PDT 24
Finished Apr 21 12:25:43 PM PDT 24
Peak memory 222344 kb
Host smart-eab6e1fe-fb80-41e5-9b83-6d205b2ce2e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140829268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3140829268
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1828074443
Short name T869
Test name
Test status
Simulation time 844132501 ps
CPU time 16.63 seconds
Started Apr 21 12:24:49 PM PDT 24
Finished Apr 21 12:25:06 PM PDT 24
Peak memory 221356 kb
Host smart-2c90174f-e48f-44e6-ae92-5191f8436685
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828074443 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1828074443
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1972829582
Short name T798
Test name
Test status
Simulation time 100525278 ps
CPU time 3.14 seconds
Started Apr 21 12:24:54 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 207772 kb
Host smart-19a6f0e6-2cba-4a0a-8fbd-2a9c670972ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972829582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1972829582
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1818539094
Short name T56
Test name
Test status
Simulation time 517074293 ps
CPU time 5.24 seconds
Started Apr 21 12:25:01 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 210096 kb
Host smart-4ea7023a-eabc-4af7-ad4e-528bbfacd9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818539094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1818539094
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.693328164
Short name T748
Test name
Test status
Simulation time 16213963 ps
CPU time 0.74 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 205720 kb
Host smart-54ea4561-b5dc-495d-96b4-2e6e86eb26fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693328164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.693328164
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2288634296
Short name T285
Test name
Test status
Simulation time 192643452 ps
CPU time 5.94 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:24:49 PM PDT 24
Peak memory 214204 kb
Host smart-af3021d2-6196-4362-8cbb-dae4224bf654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288634296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2288634296
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2500888751
Short name T731
Test name
Test status
Simulation time 406007455 ps
CPU time 8.21 seconds
Started Apr 21 12:24:50 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 209376 kb
Host smart-030d38d8-2368-4485-85ad-7f8e1e194f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500888751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2500888751
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3760813408
Short name T816
Test name
Test status
Simulation time 20173743 ps
CPU time 1.71 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 207892 kb
Host smart-11d415b1-c4cf-4649-9861-ea015f69ee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760813408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3760813408
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1176168123
Short name T239
Test name
Test status
Simulation time 69920771 ps
CPU time 3.92 seconds
Started Apr 21 12:25:12 PM PDT 24
Finished Apr 21 12:25:16 PM PDT 24
Peak memory 221824 kb
Host smart-c04a92f5-c8d2-420a-9b03-de99fe22e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176168123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1176168123
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.737528601
Short name T277
Test name
Test status
Simulation time 371180586 ps
CPU time 4.7 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:57 PM PDT 24
Peak memory 214044 kb
Host smart-8fbf3a52-ae00-4644-b852-dcbf8070b1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737528601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.737528601
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1209313756
Short name T224
Test name
Test status
Simulation time 337937399 ps
CPU time 4.45 seconds
Started Apr 21 12:25:19 PM PDT 24
Finished Apr 21 12:25:24 PM PDT 24
Peak memory 209524 kb
Host smart-5a9dfe88-baaf-4a9c-a78b-9dcf7ad05744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209313756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1209313756
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3982818974
Short name T287
Test name
Test status
Simulation time 2445695975 ps
CPU time 4.93 seconds
Started Apr 21 12:25:02 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 208536 kb
Host smart-fc3fade2-6a24-4737-999c-375a511d1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982818974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3982818974
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.87968643
Short name T530
Test name
Test status
Simulation time 973387546 ps
CPU time 29.13 seconds
Started Apr 21 12:25:03 PM PDT 24
Finished Apr 21 12:25:33 PM PDT 24
Peak memory 207884 kb
Host smart-ca9c6116-e551-4f61-8b30-6929459cf5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87968643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.87968643
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2903541342
Short name T413
Test name
Test status
Simulation time 53110469 ps
CPU time 2.46 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:55 PM PDT 24
Peak memory 208660 kb
Host smart-eb4eba53-ffb0-48b7-a2e0-804510a4db8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903541342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2903541342
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3986855530
Short name T293
Test name
Test status
Simulation time 1574174256 ps
CPU time 8.07 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 208584 kb
Host smart-ea84d19a-1c99-40a3-a721-a07800f3ab75
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986855530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3986855530
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1372090966
Short name T317
Test name
Test status
Simulation time 203827409 ps
CPU time 8.25 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 208468 kb
Host smart-12db7677-0a94-427f-8781-393f46933657
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372090966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1372090966
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.26249616
Short name T808
Test name
Test status
Simulation time 1716915364 ps
CPU time 7.48 seconds
Started Apr 21 12:25:18 PM PDT 24
Finished Apr 21 12:25:26 PM PDT 24
Peak memory 217612 kb
Host smart-048530cb-c1b4-44d3-baa5-62fa62d87310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26249616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.26249616
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.349128388
Short name T428
Test name
Test status
Simulation time 179237529 ps
CPU time 2.44 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 206588 kb
Host smart-1226ae94-9413-4d24-af6f-cd9f7dba761d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349128388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.349128388
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.440342740
Short name T213
Test name
Test status
Simulation time 879874396 ps
CPU time 25.9 seconds
Started Apr 21 12:25:01 PM PDT 24
Finished Apr 21 12:25:28 PM PDT 24
Peak memory 222436 kb
Host smart-f15e7084-e1c3-4849-8052-9d7131b549e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440342740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.440342740
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2094617442
Short name T185
Test name
Test status
Simulation time 465757550 ps
CPU time 16.5 seconds
Started Apr 21 12:24:42 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 222452 kb
Host smart-c2c395cd-36bd-476b-9ac2-450f9218f402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094617442 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2094617442
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1368324307
Short name T833
Test name
Test status
Simulation time 192304470 ps
CPU time 4.52 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:58 PM PDT 24
Peak memory 207264 kb
Host smart-2c90e2a5-b3ec-47d8-a0fa-87f47ce8e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368324307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1368324307
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3351078350
Short name T174
Test name
Test status
Simulation time 59582400 ps
CPU time 2.1 seconds
Started Apr 21 12:24:43 PM PDT 24
Finished Apr 21 12:24:45 PM PDT 24
Peak memory 209544 kb
Host smart-90c30fd7-608c-41d5-922b-5452880be078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351078350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3351078350
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.814581589
Short name T673
Test name
Test status
Simulation time 47417003 ps
CPU time 0.86 seconds
Started Apr 21 12:25:08 PM PDT 24
Finished Apr 21 12:25:10 PM PDT 24
Peak memory 205340 kb
Host smart-1d97f6e0-5a36-4bcb-b483-b334077a0a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814581589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.814581589
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1968669035
Short name T558
Test name
Test status
Simulation time 207240567 ps
CPU time 6.92 seconds
Started Apr 21 12:25:12 PM PDT 24
Finished Apr 21 12:25:20 PM PDT 24
Peak memory 221596 kb
Host smart-7932102c-a58e-4c43-9731-b2795ec3f149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968669035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1968669035
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4139927782
Short name T756
Test name
Test status
Simulation time 120425188 ps
CPU time 2.34 seconds
Started Apr 21 12:24:59 PM PDT 24
Finished Apr 21 12:25:03 PM PDT 24
Peak memory 207248 kb
Host smart-65bb2ce1-8945-4c3e-9086-de97b9abaec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139927782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4139927782
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2948346090
Short name T573
Test name
Test status
Simulation time 505840931 ps
CPU time 3.89 seconds
Started Apr 21 12:25:00 PM PDT 24
Finished Apr 21 12:25:05 PM PDT 24
Peak memory 214144 kb
Host smart-95e3aa8c-527d-40df-a174-90c7a46900e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948346090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2948346090
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2655925871
Short name T290
Test name
Test status
Simulation time 1124683996 ps
CPU time 9.84 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:07 PM PDT 24
Peak memory 210088 kb
Host smart-e23b4f60-3fbc-4f2a-a245-9c494af31014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655925871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2655925871
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.759334698
Short name T451
Test name
Test status
Simulation time 632405664 ps
CPU time 3.92 seconds
Started Apr 21 12:24:56 PM PDT 24
Finished Apr 21 12:25:02 PM PDT 24
Peak memory 222332 kb
Host smart-dee54cc0-27a5-4676-a808-1f8902af24b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759334698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.759334698
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.4198905931
Short name T626
Test name
Test status
Simulation time 3633389524 ps
CPU time 28.05 seconds
Started Apr 21 12:24:58 PM PDT 24
Finished Apr 21 12:25:27 PM PDT 24
Peak memory 218460 kb
Host smart-0d2230ee-f7f3-4ca2-b952-a96fae1fba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198905931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.4198905931
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2541373394
Short name T360
Test name
Test status
Simulation time 102892978 ps
CPU time 2.82 seconds
Started Apr 21 12:24:46 PM PDT 24
Finished Apr 21 12:24:50 PM PDT 24
Peak memory 206588 kb
Host smart-379854d8-2034-4543-9eee-f5f0a32a7a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541373394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2541373394
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4115634208
Short name T425
Test name
Test status
Simulation time 414091368 ps
CPU time 3.9 seconds
Started Apr 21 12:25:04 PM PDT 24
Finished Apr 21 12:25:09 PM PDT 24
Peak memory 208532 kb
Host smart-8fb16cba-1955-43de-9576-1e13ab75f6f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115634208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4115634208
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1311409820
Short name T460
Test name
Test status
Simulation time 255562474 ps
CPU time 5.21 seconds
Started Apr 21 12:25:09 PM PDT 24
Finished Apr 21 12:25:15 PM PDT 24
Peak memory 208576 kb
Host smart-2e8d20de-46c0-4205-b6a1-82789991cf86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311409820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1311409820
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1842646046
Short name T615
Test name
Test status
Simulation time 75065940 ps
CPU time 1.71 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:54 PM PDT 24
Peak memory 206588 kb
Host smart-97413a7f-a39e-4d27-a224-2949233338a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842646046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1842646046
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1086725741
Short name T355
Test name
Test status
Simulation time 730311676 ps
CPU time 7.6 seconds
Started Apr 21 12:25:21 PM PDT 24
Finished Apr 21 12:25:29 PM PDT 24
Peak memory 214156 kb
Host smart-93ae7705-41cc-48fa-92ee-7151d1bb0ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086725741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1086725741
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2393204050
Short name T899
Test name
Test status
Simulation time 156970130 ps
CPU time 2.39 seconds
Started Apr 21 12:25:20 PM PDT 24
Finished Apr 21 12:25:23 PM PDT 24
Peak memory 206460 kb
Host smart-1d2de7da-f465-47c2-8259-bed48dcc5ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393204050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2393204050
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.356941714
Short name T433
Test name
Test status
Simulation time 136460395 ps
CPU time 2.66 seconds
Started Apr 21 12:24:52 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 208288 kb
Host smart-67d9adff-deec-43a4-a689-d2215ee8b3db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356941714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.356941714
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.606695586
Short name T560
Test name
Test status
Simulation time 797218641 ps
CPU time 22.72 seconds
Started Apr 21 12:25:34 PM PDT 24
Finished Apr 21 12:25:58 PM PDT 24
Peak memory 222592 kb
Host smart-ae20adfa-2843-495b-90a0-90cde215498a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606695586 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.606695586
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1227407147
Short name T577
Test name
Test status
Simulation time 409370127 ps
CPU time 7.69 seconds
Started Apr 21 12:24:51 PM PDT 24
Finished Apr 21 12:24:59 PM PDT 24
Peak memory 209276 kb
Host smart-495ff5ed-c9fa-4a83-ab4d-e454716eda25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227407147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1227407147
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.423643868
Short name T655
Test name
Test status
Simulation time 64885368 ps
CPU time 1.7 seconds
Started Apr 21 12:24:53 PM PDT 24
Finished Apr 21 12:24:56 PM PDT 24
Peak memory 209368 kb
Host smart-8ba79c67-a712-4aaf-b00e-661a1bbbe4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423643868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.423643868
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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