SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 962 | 1 | T23 | 18 | T25 | 8 | T69 | 40 | ||||
auto[OtpRootKeyValidLow] | 195 | 1 | T23 | 2 | T25 | 1 | T69 | 7 | ||||
auto[LcStateInvalid] | 48 | 1 | T24 | 12 | T258 | 12 | T376 | 24 | ||||
auto[OtpDevIdInvalid] | 96 | 1 | T24 | 12 | T88 | 12 | T258 | 24 | ||||
auto[RomDigestInvalid] | 36 | 1 | T88 | 12 | T258 | 12 | T393 | 12 | ||||
auto[RomDigestValidLow] | 120 | 1 | T88 | 24 | T22 | 24 | T376 | 12 | ||||
auto[FlashCreatorSeedInvalid] | 12 | 1 | T366 | 12 | - | - | - | - | ||||
auto[FlashOwnerSeedInvalid] | 84 | 1 | T22 | 24 | T94 | 12 | T96 | 24 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |