Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11273

1

T1

5

T2

17

T3

10

auto[Attestation]

7826

1

T1

3

T2

3

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2819	1			T1	2		T3	2		T15	1
auto[Aes]	3399	1			T1	1		T3	4		T5	3
auto[Kmac]	3458	1			T1	1		T5	1		T15	1
auto[Otbn]	3431	1			T1	1		T2	20		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7740	1			T1	8		T2	8		T3	5
auto[OpGenId]	5992	1			T1	3		T3	8		T5	4
auto[OpGenSwOut]	5980	1			T1	5		T3	4		T5	6
auto[OpGenHwOut]	7127	1			T2	20		T3	3		T5	1
auto[OpDisable]	129	1			T26	1		T46	1		T47	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10124

1

T1

8

T2

8

T3

7

auto[OpDoneFail]

16844

1

T1

8

T2

20

T3

13

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5979	1			T1	1		T2	13		T3	8
auto[StInit]	4373	1			T1	2		T2	2		T3	6
auto[StCreatorRootKey]	3036	1			T1	2		T2	2		T3	1
auto[StOwnerIntKey]	2647	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2341	1			T1	2		T2	2		T3	2
auto[StDisabled]	7461	1			T1	7		T2	7		T3	1
auto[StInvalid]	1131	1			T39	32		T23	21		T25	18

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	297	1			T3	1		T36	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	122	1			T82	1		T47	1		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T49	1		T50	1		T67	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	81	1			T26	2		T51	1		T128	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	65	1			T36	1		T29	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	193	1			T18	2		T36	1		T27	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	29	1			T25	1		T90	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	340	1			T3	1		T5	3		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	131	1			T46	1		T82	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	89	1			T46	1		T189	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	63	1			T27	1		T51	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	68	1			T131	1		T50	2		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	188	1			T1	1		T27	3		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	24	1			T39	1		T197	1		T90	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	320	1			T36	1		T38	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T27	2		T82	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T27	1		T134	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	55	1			T49	1		T50	2		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	63	1			T27	1		T29	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	189	1			T1	1		T36	1		T27	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	41	1			T39	3		T23	1		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	308	1			T5	2		T18	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	119	1			T80	1		T20	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T15	1		T18	1		T193	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T15	1		T27	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	67	1			T27	1		T116	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	215	1			T1	1		T27	2		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	31	1			T39	1		T23	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	54	1			T36	1		T27	3		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	133	1			T3	1		T26	1		T27	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	94	1			T80	1		T59	1		T188	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	59	1			T1	1		T115	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	62	1			T36	1		T27	2		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	216	1			T1	1		T15	1		T27	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	36	1			T39	4		T23	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	47	1			T49	2		T50	2		T67	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	129	1			T15	1		T27	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	72	1			T83	1		T49	2		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	62	1			T51	1		T198	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	59	1			T18	1		T132	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	175	1			T36	1		T27	4		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	35	1			T23	1		T25	1		T95	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	54	1			T49	2		T50	2		T67	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	140	1			T27	2		T47	1		T132	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	71	1			T36	1		T27	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T18	1		T36	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	58	1			T27	1		T67	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	205	1			T15	1		T36	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	38	1			T39	2		T23	2		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T36	1		T49	5		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	104	1			T5	1		T37	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T37	1		T52	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T27	1		T115	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	53	1			T3	1		T80	1		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	212	1			T18	1		T37	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T23	1		T201	2		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	248	1			T28	2		T29	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T27	1		T49	2		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T115	1		T189	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	66	1			T27	1		T83	1		T116	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T82	1		T131	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	171	1			T27	1		T29	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	37	1			T39	1		T25	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	424	1			T3	1		T27	1		T42	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	133	1			T51	1		T127	1		T67	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	95	1			T27	1		T46	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	83	1			T3	1		T133	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T83	1		T133	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	271	1			T3	1		T27	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	34	1			T201	1		T196	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	442	1			T5	1		T27	1		T85	9
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	132	1			T26	1		T38	1		T49	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	109	1			T80	1		T84	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T85	1		T195	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T27	1		T80	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	270	1			T27	1		T29	2		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	32	1			T39	1		T25	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	447	1			T2	12		T27	5		T79	10
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	137	1			T2	1		T46	1		T115	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T2	1		T4	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	115	1			T2	1		T4	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	101	1			T4	1		T19	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	276	1			T2	2		T4	3		T19	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	36	1			T25	1		T201	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	45	1			T27	3		T49	2		T50	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	124	1			T27	2		T83	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T132	1		T189	1		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	55	1			T115	1		T50	1		T67	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	40	1			T50	1		T51	2		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	179	1			T27	3		T82	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	37	1			T23	1		T197	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	44	1			T27	1		T50	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	136	1			T26	1		T27	2		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	135	1			T133	1		T50	2		T127	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	102	1			T27	1		T46	1		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	81	1			T115	1		T50	1		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	253	1			T27	1		T133	1		T116	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	32	1			T25	1		T201	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T49	5		T50	7		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	158	1			T26	1		T27	3		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	99	1			T26	1		T27	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	106	1			T26	1		T82	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	79	1			T27	1		T131	2		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	274	1			T27	2		T84	3		T85	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	30	1			T39	2		T196	1		T87	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	47	1			T27	1		T49	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	144	1			T4	1		T19	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T19	1		T79	1		T51	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T19	1		T27	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	66	1			T2	1		T79	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	245	1			T2	2		T4	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	30	1			T39	1		T23	2		T95	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	197	1			T36	1		T26	2		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	661	1			T3	1		T18	2		T36	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	208	1			T27	1		T46	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	695	1			T1	1		T3	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	172	1			T27	2		T29	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	688	1			T1	1		T36	2		T27	5
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T15	2		T18	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	687	1			T1	1		T5	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	197	1			T1	1		T36	1		T27	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	457	1			T1	1		T3	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	174	1			T18	1		T132	1		T59	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	405	1			T15	1		T36	1		T27	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	179	1			T18	1		T36	2		T27	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	455	1			T15	1		T36	1		T27	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	178	1			T3	1		T37	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	430	1			T5	1		T18	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	180	1			T27	1		T82	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	570	1			T27	2		T28	2		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	261	1			T3	1		T27	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	873	1			T3	2		T27	2		T42	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T27	1		T80	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	893	1			T5	1		T26	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	314	1			T2	2		T4	3		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	909	1			T2	15		T4	3		T19	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	160	1			T132	1		T115	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	397	1			T27	8		T82	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	307	1			T27	1		T46	1		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	476	1			T26	1		T27	4		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	266	1			T26	2		T27	2		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	537	1			T26	1		T27	5		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	236	1			T2	1		T19	2		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	480	1			T2	2		T4	2		T19	2