Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30901

1

T1

21

T2

32

T3

22

auto[1]

281

1

T115

12

T116

2

T136

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30906	1			T1	21		T2	32		T3	22
auto[134217728:268435455]	7	1			T115	1		T255	1		T329	1
auto[268435456:402653183]	9	1			T137	1		T361	1		T275	1
auto[402653184:536870911]	9	1			T115	1		T136	1		T223	1
auto[536870912:671088639]	3	1			T293	1		T406	2		-	-
auto[671088640:805306367]	10	1			T139	1		T378	2		T223	2
auto[805306368:939524095]	7	1			T223	1		T288	1		T407	1
auto[939524096:1073741823]	11	1			T115	1		T136	1		T329	1
auto[1073741824:1207959551]	14	1			T137	1		T378	1		T223	1
auto[1207959552:1342177279]	9	1			T223	1		T288	1		T224	2
auto[1342177280:1476395007]	12	1			T256	1		T288	2		T408	1
auto[1476395008:1610612735]	9	1			T115	1		T256	1		T223	1
auto[1610612736:1744830463]	7	1			T137	1		T246	1		T244	1
auto[1744830464:1879048191]	5	1			T406	1		T409	1		T303	1
auto[1879048192:2013265919]	10	1			T137	1		T139	1		T256	2
auto[2013265920:2147483647]	7	1			T261	1		T392	1		T288	1
auto[2147483648:2281701375]	17	1			T136	1		T137	1		T256	1
auto[2281701376:2415919103]	7	1			T256	1		T239	1		T224	1
auto[2415919104:2550136831]	9	1			T288	1		T275	1		T244	1
auto[2550136832:2684354559]	6	1			T116	1		T136	1		T391	1
auto[2684354560:2818572287]	17	1			T115	1		T256	1		T378	1
auto[2818572288:2952790015]	17	1			T115	1		T139	1		T256	1
auto[2952790016:3087007743]	7	1			T378	1		T261	1		T410	1
auto[3087007744:3221225471]	6	1			T115	1		T116	1		T378	2
auto[3221225472:3355443199]	7	1			T246	1		T378	1		T288	1
auto[3355443200:3489660927]	9	1			T115	1		T378	1		T355	1
auto[3489660928:3623878655]	5	1			T115	1		T137	1		T223	1
auto[3623878656:3758096383]	9	1			T136	1		T378	1		T392	1
auto[3758096384:3892314111]	9	1			T115	1		T136	1		T223	1
auto[3892314112:4026531839]	9	1			T223	2		T261	1		T299	1
auto[4026531840:4160749567]	5	1			T139	1		T293	1		T244	1
auto[4160749568:4294967295]	8	1			T137	1		T223	1		T411	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30901	1			T1	21		T2	32		T3	22
auto[0:134217727]	auto[1]	5	1			T115	2		T261	1		T412	1
auto[134217728:268435455]	auto[1]	7	1			T115	1		T255	1		T329	1
auto[268435456:402653183]	auto[1]	9	1			T137	1		T361	1		T275	1
auto[402653184:536870911]	auto[1]	9	1			T115	1		T136	1		T223	1
auto[536870912:671088639]	auto[1]	3	1			T293	1		T406	2		-	-
auto[671088640:805306367]	auto[1]	10	1			T139	1		T378	2		T223	2
auto[805306368:939524095]	auto[1]	7	1			T223	1		T288	1		T407	1
auto[939524096:1073741823]	auto[1]	11	1			T115	1		T136	1		T329	1
auto[1073741824:1207959551]	auto[1]	14	1			T137	1		T378	1		T223	1
auto[1207959552:1342177279]	auto[1]	9	1			T223	1		T288	1		T224	2
auto[1342177280:1476395007]	auto[1]	12	1			T256	1		T288	2		T408	1
auto[1476395008:1610612735]	auto[1]	9	1			T115	1		T256	1		T223	1
auto[1610612736:1744830463]	auto[1]	7	1			T137	1		T246	1		T244	1
auto[1744830464:1879048191]	auto[1]	5	1			T406	1		T409	1		T303	1
auto[1879048192:2013265919]	auto[1]	10	1			T137	1		T139	1		T256	2
auto[2013265920:2147483647]	auto[1]	7	1			T261	1		T392	1		T288	1
auto[2147483648:2281701375]	auto[1]	17	1			T136	1		T137	1		T256	1
auto[2281701376:2415919103]	auto[1]	7	1			T256	1		T239	1		T224	1
auto[2415919104:2550136831]	auto[1]	9	1			T288	1		T275	1		T244	1
auto[2550136832:2684354559]	auto[1]	6	1			T116	1		T136	1		T391	1
auto[2684354560:2818572287]	auto[1]	17	1			T115	1		T256	1		T378	1
auto[2818572288:2952790015]	auto[1]	17	1			T115	1		T139	1		T256	1
auto[2952790016:3087007743]	auto[1]	7	1			T378	1		T261	1		T410	1
auto[3087007744:3221225471]	auto[1]	6	1			T115	1		T116	1		T378	2
auto[3221225472:3355443199]	auto[1]	7	1			T246	1		T378	1		T288	1
auto[3355443200:3489660927]	auto[1]	9	1			T115	1		T378	1		T355	1
auto[3489660928:3623878655]	auto[1]	5	1			T115	1		T137	1		T223	1
auto[3623878656:3758096383]	auto[1]	9	1			T136	1		T378	1		T392	1
auto[3758096384:3892314111]	auto[1]	9	1			T115	1		T136	1		T223	1
auto[3892314112:4026531839]	auto[1]	9	1			T223	2		T261	1		T299	1
auto[4026531840:4160749567]	auto[1]	5	1			T139	1		T293	1		T244	1
auto[4160749568:4294967295]	auto[1]	8	1			T137	1		T223	1		T411	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1446

1

T3

2

T36

3

T27

17

auto[1]

1655

1

T3

2

T36

1

T26

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	118	1			T27	6		T24	1		T49	1
auto[134217728:268435455]	85	1			T42	1		T116	1		T24	1
auto[268435456:402653183]	87	1			T27	1		T131	1		T24	1
auto[402653184:536870911]	108	1			T26	1		T49	1		T51	1
auto[536870912:671088639]	92	1			T36	1		T27	1		T49	1
auto[671088640:805306367]	89	1			T46	1		T80	1		T20	1
auto[805306368:939524095]	77	1			T27	2		T24	1		T49	1
auto[939524096:1073741823]	96	1			T29	1		T82	1		T131	1
auto[1073741824:1207959551]	111	1			T27	2		T28	1		T51	2
auto[1207959552:1342177279]	106	1			T27	1		T42	1		T23	2
auto[1342177280:1476395007]	90	1			T27	1		T42	1		T24	1
auto[1476395008:1610612735]	96	1			T36	1		T27	2		T29	1
auto[1610612736:1744830463]	111	1			T36	1		T26	1		T46	1
auto[1744830464:1879048191]	109	1			T27	1		T115	1		T189	1
auto[1879048192:2013265919]	90	1			T27	1		T63	1		T67	1
auto[2013265920:2147483647]	105	1			T27	2		T83	1		T67	1
auto[2147483648:2281701375]	94	1			T80	1		T195	1		T51	1
auto[2281701376:2415919103]	93	1			T3	2		T27	3		T82	1
auto[2415919104:2550136831]	88	1			T39	1		T49	1		T50	1
auto[2550136832:2684354559]	86	1			T36	1		T82	1		T83	1
auto[2684354560:2818572287]	111	1			T3	1		T20	1		T116	1
auto[2818572288:2952790015]	84	1			T27	1		T29	1		T80	1
auto[2952790016:3087007743]	85	1			T26	1		T82	1		T67	2
auto[3087007744:3221225471]	89	1			T131	1		T20	1		T24	1
auto[3221225472:3355443199]	97	1			T42	1		T50	1		T51	1
auto[3355443200:3489660927]	97	1			T27	2		T115	1		T39	1
auto[3489660928:3623878655]	109	1			T27	1		T42	1		T116	1
auto[3623878656:3758096383]	90	1			T29	1		T39	1		T49	1
auto[3758096384:3892314111]	97	1			T116	1		T49	1		T33	1
auto[3892314112:4026531839]	94	1			T27	2		T47	1		T50	1
auto[4026531840:4160749567]	111	1			T27	3		T115	1		T116	1
auto[4160749568:4294967295]	106	1			T3	1		T83	1		T39	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T27	2		T24	1		T49	1
auto[0:134217727]	auto[1]	62	1			T27	4		T136	1		T54	1
auto[134217728:268435455]	auto[0]	33	1			T42	1		T24	1		T67	1
auto[134217728:268435455]	auto[1]	52	1			T116	1		T67	1		T6	1
auto[268435456:402653183]	auto[0]	38	1			T27	1		T95	1		T55	1
auto[268435456:402653183]	auto[1]	49	1			T131	1		T24	1		T63	1
auto[402653184:536870911]	auto[0]	56	1			T51	1		T61	2		T122	1
auto[402653184:536870911]	auto[1]	52	1			T26	1		T49	1		T95	1
auto[536870912:671088639]	auto[0]	45	1			T36	1		T6	1		T255	1
auto[536870912:671088639]	auto[1]	47	1			T27	1		T49	1		T50	2
auto[671088640:805306367]	auto[0]	45	1			T80	1		T39	1		T67	1
auto[671088640:805306367]	auto[1]	44	1			T46	1		T20	1		T39	1
auto[805306368:939524095]	auto[0]	32	1			T27	1		T24	1		T51	1
auto[805306368:939524095]	auto[1]	45	1			T27	1		T49	1		T51	1
auto[939524096:1073741823]	auto[0]	42	1			T50	1		T67	1		T6	1
auto[939524096:1073741823]	auto[1]	54	1			T29	1		T82	1		T131	1
auto[1073741824:1207959551]	auto[0]	53	1			T27	2		T51	1		T55	1
auto[1073741824:1207959551]	auto[1]	58	1			T28	1		T51	1		T202	1
auto[1207959552:1342177279]	auto[0]	61	1			T27	1		T23	2		T49	1
auto[1207959552:1342177279]	auto[1]	45	1			T42	1		T50	1		T67	1
auto[1342177280:1476395007]	auto[0]	43	1			T27	1		T24	1		T51	1
auto[1342177280:1476395007]	auto[1]	47	1			T42	1		T67	1		T95	1
auto[1476395008:1610612735]	auto[0]	47	1			T27	1		T47	1		T24	1
auto[1476395008:1610612735]	auto[1]	49	1			T36	1		T27	1		T29	1
auto[1610612736:1744830463]	auto[0]	51	1			T36	1		T25	2		T95	1
auto[1610612736:1744830463]	auto[1]	60	1			T26	1		T46	1		T136	1
auto[1744830464:1879048191]	auto[0]	62	1			T189	1		T66	1		T95	1
auto[1744830464:1879048191]	auto[1]	47	1			T27	1		T115	1		T229	1
auto[1879048192:2013265919]	auto[0]	40	1			T27	1		T67	1		T69	1
auto[1879048192:2013265919]	auto[1]	50	1			T63	1		T198	1		T136	1
auto[2013265920:2147483647]	auto[0]	50	1			T27	1		T67	1		T43	1
auto[2013265920:2147483647]	auto[1]	55	1			T27	1		T83	1		T6	1
auto[2147483648:2281701375]	auto[0]	44	1			T195	1		T6	3		T122	1
auto[2147483648:2281701375]	auto[1]	50	1			T80	1		T51	1		T413	1
auto[2281701376:2415919103]	auto[0]	44	1			T3	2		T27	1		T24	1
auto[2281701376:2415919103]	auto[1]	49	1			T27	2		T82	1		T51	1
auto[2415919104:2550136831]	auto[0]	49	1			T39	1		T51	1		T66	1
auto[2415919104:2550136831]	auto[1]	39	1			T49	1		T50	1		T67	1
auto[2550136832:2684354559]	auto[0]	38	1			T36	1		T50	1		T25	1
auto[2550136832:2684354559]	auto[1]	48	1			T82	1		T83	1		T115	1
auto[2684354560:2818572287]	auto[0]	50	1			T23	2		T49	1		T51	2
auto[2684354560:2818572287]	auto[1]	61	1			T3	1		T20	1		T116	1
auto[2818572288:2952790015]	auto[0]	34	1			T80	1		T50	1		T67	2
auto[2818572288:2952790015]	auto[1]	50	1			T27	1		T29	1		T49	1
auto[2952790016:3087007743]	auto[0]	49	1			T82	1		T67	2		T95	1
auto[2952790016:3087007743]	auto[1]	36	1			T26	1		T6	1		T241	1
auto[3087007744:3221225471]	auto[0]	39	1			T51	1		T226	1		T6	1
auto[3087007744:3221225471]	auto[1]	50	1			T131	1		T20	1		T24	1
auto[3221225472:3355443199]	auto[0]	35	1			T55	1		T61	1		T22	1
auto[3221225472:3355443199]	auto[1]	62	1			T42	1		T50	1		T51	1
auto[3355443200:3489660927]	auto[0]	39	1			T27	1		T39	1		T50	1
auto[3355443200:3489660927]	auto[1]	58	1			T27	1		T115	1		T51	1
auto[3489660928:3623878655]	auto[0]	42	1			T67	1		T6	1		T201	1
auto[3489660928:3623878655]	auto[1]	67	1			T27	1		T42	1		T116	1
auto[3623878656:3758096383]	auto[0]	40	1			T39	1		T51	1		T128	1
auto[3623878656:3758096383]	auto[1]	50	1			T29	1		T49	1		T51	1
auto[3758096384:3892314111]	auto[0]	39	1			T67	1		T86	1		T64	2
auto[3758096384:3892314111]	auto[1]	58	1			T116	1		T49	1		T33	1
auto[3892314112:4026531839]	auto[0]	49	1			T27	2		T47	1		T67	1
auto[3892314112:4026531839]	auto[1]	45	1			T50	1		T247	1		T255	1
auto[4026531840:4160749567]	auto[0]	48	1			T27	2		T23	1		T54	1
auto[4026531840:4160749567]	auto[1]	63	1			T27	1		T115	1		T116	1
auto[4160749568:4294967295]	auto[0]	53	1			T33	1		T247	1		T6	1
auto[4160749568:4294967295]	auto[1]	53	1			T3	1		T83	1		T39	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1453

1

T3

2

T36

2

T27

18

auto[1]

1647

1

T3

2

T36

2

T26

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T36	1		T27	3		T46	1
auto[134217728:268435455]	95	1			T27	1		T131	1		T23	1
auto[268435456:402653183]	110	1			T26	1		T63	1		T198	1
auto[402653184:536870911]	84	1			T27	3		T49	1		T67	1
auto[536870912:671088639]	101	1			T29	1		T39	1		T23	1
auto[671088640:805306367]	95	1			T27	1		T42	1		T20	1
auto[805306368:939524095]	105	1			T50	1		T51	1		T33	1
auto[939524096:1073741823]	88	1			T36	1		T27	2		T83	1
auto[1073741824:1207959551]	97	1			T39	1		T24	1		T49	1
auto[1207959552:1342177279]	92	1			T27	3		T29	1		T50	1
auto[1342177280:1476395007]	112	1			T27	2		T82	2		T83	1
auto[1476395008:1610612735]	87	1			T26	1		T49	1		T51	1
auto[1610612736:1744830463]	110	1			T3	1		T42	1		T51	1
auto[1744830464:1879048191]	89	1			T27	2		T116	1		T49	1
auto[1879048192:2013265919]	99	1			T36	1		T27	1		T80	1
auto[2013265920:2147483647]	107	1			T46	1		T80	1		T39	2
auto[2147483648:2281701375]	85	1			T27	2		T6	2		T138	1
auto[2281701376:2415919103]	97	1			T27	1		T83	1		T115	1
auto[2415919104:2550136831]	91	1			T115	1		T39	1		T116	1
auto[2550136832:2684354559]	90	1			T27	1		T39	1		T51	1
auto[2684354560:2818572287]	105	1			T3	1		T27	1		T29	1
auto[2818572288:2952790015]	103	1			T82	1		T195	1		T24	1
auto[2952790016:3087007743]	105	1			T27	1		T47	1		T116	1
auto[3087007744:3221225471]	91	1			T27	2		T20	1		T49	3
auto[3221225472:3355443199]	105	1			T82	1		T24	1		T49	1
auto[3355443200:3489660927]	100	1			T3	1		T42	2		T80	1
auto[3489660928:3623878655]	83	1			T26	1		T27	1		T20	1
auto[3623878656:3758096383]	98	1			T46	1		T50	1		T95	1
auto[3758096384:3892314111]	87	1			T27	1		T42	1		T33	1
auto[3892314112:4026531839]	99	1			T27	2		T29	1		T131	1
auto[4026531840:4160749567]	107	1			T27	1		T23	1		T24	1
auto[4160749568:4294967295]	84	1			T3	1		T36	1		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T27	3		T46	1		T23	1
auto[0:134217727]	auto[1]	52	1			T36	1		T67	1		T54	1
auto[134217728:268435455]	auto[0]	39	1			T23	1		T51	1		T95	1
auto[134217728:268435455]	auto[1]	56	1			T27	1		T131	1		T24	1
auto[268435456:402653183]	auto[0]	54	1			T63	1		T264	1		T44	1
auto[268435456:402653183]	auto[1]	56	1			T26	1		T198	1		T88	1
auto[402653184:536870911]	auto[0]	41	1			T27	3		T67	1		T226	1
auto[402653184:536870911]	auto[1]	43	1			T49	1		T95	1		T394	1
auto[536870912:671088639]	auto[0]	39	1			T23	1		T51	2		T6	1
auto[536870912:671088639]	auto[1]	62	1			T29	1		T39	1		T49	2
auto[671088640:805306367]	auto[0]	47	1			T6	2		T61	1		T139	1
auto[671088640:805306367]	auto[1]	48	1			T27	1		T42	1		T20	1
auto[805306368:939524095]	auto[0]	42	1			T51	1		T33	1		T55	1
auto[805306368:939524095]	auto[1]	63	1			T50	1		T202	1		T89	1
auto[939524096:1073741823]	auto[0]	43	1			T27	2		T50	1		T51	1
auto[939524096:1073741823]	auto[1]	45	1			T36	1		T83	1		T51	1
auto[1073741824:1207959551]	auto[0]	39	1			T39	1		T50	1		T95	2
auto[1073741824:1207959551]	auto[1]	58	1			T24	1		T49	1		T6	1
auto[1207959552:1342177279]	auto[0]	33	1			T128	2		T54	2		T227	1
auto[1207959552:1342177279]	auto[1]	59	1			T27	3		T29	1		T50	1
auto[1342177280:1476395007]	auto[0]	55	1			T27	2		T67	1		T260	1
auto[1342177280:1476395007]	auto[1]	57	1			T82	2		T83	1		T47	1
auto[1476395008:1610612735]	auto[0]	42	1			T25	1		T6	1		T45	3
auto[1476395008:1610612735]	auto[1]	45	1			T26	1		T49	1		T51	1
auto[1610612736:1744830463]	auto[0]	46	1			T3	1		T42	1		T229	1
auto[1610612736:1744830463]	auto[1]	64	1			T51	1		T67	2		T136	1
auto[1744830464:1879048191]	auto[0]	43	1			T27	1		T67	1		T69	1
auto[1744830464:1879048191]	auto[1]	46	1			T27	1		T116	1		T49	1
auto[1879048192:2013265919]	auto[0]	41	1			T36	1		T49	1		T51	1
auto[1879048192:2013265919]	auto[1]	58	1			T27	1		T80	1		T49	2
auto[2013265920:2147483647]	auto[0]	56	1			T80	1		T39	1		T24	1
auto[2013265920:2147483647]	auto[1]	51	1			T46	1		T39	1		T50	1
auto[2147483648:2281701375]	auto[0]	46	1			T27	1		T6	1		T138	1
auto[2147483648:2281701375]	auto[1]	39	1			T27	1		T6	1		T61	2
auto[2281701376:2415919103]	auto[0]	52	1			T27	1		T33	1		T67	2
auto[2281701376:2415919103]	auto[1]	45	1			T83	1		T115	1		T116	1
auto[2415919104:2550136831]	auto[0]	48	1			T39	1		T116	1		T50	1
auto[2415919104:2550136831]	auto[1]	43	1			T115	1		T51	2		T6	1
auto[2550136832:2684354559]	auto[0]	38	1			T39	1		T66	1		T25	1
auto[2550136832:2684354559]	auto[1]	52	1			T27	1		T51	1		T397	1
auto[2684354560:2818572287]	auto[0]	53	1			T67	3		T61	1		T64	1
auto[2684354560:2818572287]	auto[1]	52	1			T3	1		T27	1		T29	1
auto[2818572288:2952790015]	auto[0]	52	1			T195	1		T49	1		T6	1
auto[2818572288:2952790015]	auto[1]	51	1			T82	1		T24	1		T50	1
auto[2952790016:3087007743]	auto[0]	44	1			T27	1		T47	1		T67	1
auto[2952790016:3087007743]	auto[1]	61	1			T116	1		T51	1		T128	1
auto[3087007744:3221225471]	auto[0]	44	1			T49	1		T50	1		T55	1
auto[3087007744:3221225471]	auto[1]	47	1			T27	2		T20	1		T49	2
auto[3221225472:3355443199]	auto[0]	45	1			T237	2		T61	1		T235	1
auto[3221225472:3355443199]	auto[1]	60	1			T82	1		T24	1		T49	1
auto[3355443200:3489660927]	auto[0]	42	1			T42	1		T80	1		T243	1
auto[3355443200:3489660927]	auto[1]	58	1			T3	1		T42	1		T131	1
auto[3489660928:3623878655]	auto[0]	39	1			T27	1		T189	1		T24	2
auto[3489660928:3623878655]	auto[1]	44	1			T26	1		T20	1		T136	1
auto[3623878656:3758096383]	auto[0]	53	1			T50	1		T95	1		T43	1
auto[3623878656:3758096383]	auto[1]	45	1			T46	1		T247	1		T201	1
auto[3758096384:3892314111]	auto[0]	42	1			T33	1		T25	1		T170	1
auto[3758096384:3892314111]	auto[1]	45	1			T27	1		T42	1		T67	1
auto[3892314112:4026531839]	auto[0]	48	1			T27	1		T23	1		T24	1
auto[3892314112:4026531839]	auto[1]	51	1			T27	1		T29	1		T131	1
auto[4026531840:4160749567]	auto[0]	57	1			T27	1		T23	1		T24	1
auto[4026531840:4160749567]	auto[1]	50	1			T67	1		T202	1		T6	2
auto[4160749568:4294967295]	auto[0]	43	1			T3	1		T36	1		T27	1
auto[4160749568:4294967295]	auto[1]	41	1			T28	1		T50	1		T34	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1458

1

T3

3

T36

3

T27

17

auto[1]

1643

1

T3

1

T36

1

T26

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T26	1		T20	1		T49	1
auto[134217728:268435455]	99	1			T27	1		T50	1		T67	1
auto[268435456:402653183]	93	1			T27	1		T51	2		T67	1
auto[402653184:536870911]	108	1			T27	1		T66	1		T54	1
auto[536870912:671088639]	85	1			T23	1		T50	1		T33	1
auto[671088640:805306367]	110	1			T3	1		T27	3		T82	1
auto[805306368:939524095]	85	1			T27	3		T51	1		T245	1
auto[939524096:1073741823]	83	1			T42	1		T29	1		T46	1
auto[1073741824:1207959551]	94	1			T27	1		T131	1		T39	1
auto[1207959552:1342177279]	90	1			T36	1		T29	1		T116	1
auto[1342177280:1476395007]	90	1			T3	1		T27	1		T49	2
auto[1476395008:1610612735]	97	1			T36	1		T27	1		T29	1
auto[1610612736:1744830463]	100	1			T26	1		T83	1		T39	1
auto[1744830464:1879048191]	97	1			T27	1		T82	1		T23	1
auto[1879048192:2013265919]	103	1			T3	1		T27	2		T42	1
auto[2013265920:2147483647]	101	1			T39	1		T128	2		T67	1
auto[2147483648:2281701375]	80	1			T42	1		T33	1		T198	1
auto[2281701376:2415919103]	88	1			T27	1		T46	1		T63	2
auto[2415919104:2550136831]	80	1			T27	1		T116	1		T50	1
auto[2550136832:2684354559]	92	1			T42	1		T24	1		T51	4
auto[2684354560:2818572287]	94	1			T36	1		T27	1		T23	1
auto[2818572288:2952790015]	108	1			T26	1		T82	1		T39	1
auto[2952790016:3087007743]	102	1			T27	2		T49	2		T50	1
auto[3087007744:3221225471]	108	1			T36	1		T27	1		T80	1
auto[3221225472:3355443199]	85	1			T27	3		T42	1		T49	1
auto[3355443200:3489660927]	101	1			T27	3		T46	1		T49	1
auto[3489660928:3623878655]	108	1			T115	1		T51	1		T67	1
auto[3623878656:3758096383]	100	1			T27	2		T23	1		T50	1
auto[3758096384:3892314111]	113	1			T27	1		T83	1		T131	1
auto[3892314112:4026531839]	107	1			T80	1		T47	1		T24	1
auto[4026531840:4160749567]	122	1			T82	1		T115	1		T20	1
auto[4160749568:4294967295]	85	1			T3	1		T27	2		T28	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T49	1		T54	1		T138	2
auto[0:134217727]	auto[1]	55	1			T26	1		T20	1		T128	1
auto[134217728:268435455]	auto[0]	46	1			T27	1		T50	1		T67	1
auto[134217728:268435455]	auto[1]	53	1			T88	1		T200	2		T202	1
auto[268435456:402653183]	auto[0]	52	1			T27	1		T51	1		T67	1
auto[268435456:402653183]	auto[1]	41	1			T51	1		T6	2		T280	1
auto[402653184:536870911]	auto[0]	52	1			T27	1		T66	1		T54	1
auto[402653184:536870911]	auto[1]	56	1			T6	1		T243	1		T137	1
auto[536870912:671088639]	auto[0]	30	1			T23	1		T33	1		T95	1
auto[536870912:671088639]	auto[1]	55	1			T50	1		T198	1		T229	1
auto[671088640:805306367]	auto[0]	50	1			T3	1		T27	2		T39	2
auto[671088640:805306367]	auto[1]	60	1			T27	1		T82	1		T83	1
auto[805306368:939524095]	auto[0]	34	1			T27	3		T51	1		T138	1
auto[805306368:939524095]	auto[1]	51	1			T245	1		T137	1		T246	1
auto[939524096:1073741823]	auto[0]	36	1			T46	1		T24	1		T69	2
auto[939524096:1073741823]	auto[1]	47	1			T42	1		T29	1		T80	1
auto[1073741824:1207959551]	auto[0]	43	1			T27	1		T116	1		T50	1
auto[1073741824:1207959551]	auto[1]	51	1			T131	1		T39	1		T49	1
auto[1207959552:1342177279]	auto[0]	36	1			T36	1		T55	1		T6	1
auto[1207959552:1342177279]	auto[1]	54	1			T29	1		T116	1		T49	1
auto[1342177280:1476395007]	auto[0]	36	1			T95	1		T69	1		T227	1
auto[1342177280:1476395007]	auto[1]	54	1			T3	1		T27	1		T49	2
auto[1476395008:1610612735]	auto[0]	52	1			T36	1		T27	1		T25	1
auto[1476395008:1610612735]	auto[1]	45	1			T29	1		T136	1		T243	1
auto[1610612736:1744830463]	auto[0]	44	1			T189	1		T24	1		T6	1
auto[1610612736:1744830463]	auto[1]	56	1			T26	1		T83	1		T39	1
auto[1744830464:1879048191]	auto[0]	53	1			T27	1		T23	1		T50	1
auto[1744830464:1879048191]	auto[1]	44	1			T82	1		T50	1		T67	3
auto[1879048192:2013265919]	auto[0]	45	1			T3	1		T24	1		T49	1
auto[1879048192:2013265919]	auto[1]	58	1			T27	2		T42	1		T29	1
auto[2013265920:2147483647]	auto[0]	49	1			T39	1		T128	1		T226	1
auto[2013265920:2147483647]	auto[1]	52	1			T128	1		T67	1		T260	2
auto[2147483648:2281701375]	auto[0]	46	1			T42	1		T33	1		T237	1
auto[2147483648:2281701375]	auto[1]	34	1			T198	1		T200	1		T201	1
auto[2281701376:2415919103]	auto[0]	44	1			T33	1		T6	2		T205	1
auto[2281701376:2415919103]	auto[1]	44	1			T27	1		T46	1		T63	2
auto[2415919104:2550136831]	auto[0]	39	1			T260	1		T44	1		T122	1
auto[2415919104:2550136831]	auto[1]	41	1			T27	1		T116	1		T50	1
auto[2550136832:2684354559]	auto[0]	38	1			T51	2		T67	1		T95	1
auto[2550136832:2684354559]	auto[1]	54	1			T42	1		T24	1		T51	2
auto[2684354560:2818572287]	auto[0]	44	1			T23	1		T67	1		T95	1
auto[2684354560:2818572287]	auto[1]	50	1			T36	1		T27	1		T49	1
auto[2818572288:2952790015]	auto[0]	60	1			T39	1		T51	3		T67	1
auto[2818572288:2952790015]	auto[1]	48	1			T26	1		T82	1		T6	1
auto[2952790016:3087007743]	auto[0]	53	1			T33	1		T56	1		T171	1
auto[2952790016:3087007743]	auto[1]	49	1			T27	2		T49	2		T50	1
auto[3087007744:3221225471]	auto[0]	58	1			T36	1		T80	1		T49	1
auto[3087007744:3221225471]	auto[1]	50	1			T27	1		T131	1		T24	1
auto[3221225472:3355443199]	auto[0]	39	1			T27	2		T25	1		T54	1
auto[3221225472:3355443199]	auto[1]	46	1			T27	1		T42	1		T49	1
auto[3355443200:3489660927]	auto[0]	45	1			T27	2		T67	1		T247	1
auto[3355443200:3489660927]	auto[1]	56	1			T27	1		T46	1		T49	1
auto[3489660928:3623878655]	auto[0]	54	1			T67	1		T54	1		T43	1
auto[3489660928:3623878655]	auto[1]	54	1			T115	1		T51	1		T54	1
auto[3623878656:3758096383]	auto[0]	38	1			T27	1		T23	1		T67	1
auto[3623878656:3758096383]	auto[1]	62	1			T27	1		T50	1		T67	1
auto[3758096384:3892314111]	auto[0]	56	1			T27	1		T83	1		T24	1
auto[3758096384:3892314111]	auto[1]	57	1			T131	1		T33	1		T95	1
auto[3892314112:4026531839]	auto[0]	55	1			T80	1		T47	1		T67	3
auto[3892314112:4026531839]	auto[1]	52	1			T24	1		T51	1		T67	2
auto[4026531840:4160749567]	auto[0]	60	1			T82	1		T23	1		T50	1
auto[4026531840:4160749567]	auto[1]	62	1			T115	1		T20	1		T51	1
auto[4160749568:4294967295]	auto[0]	33	1			T3	1		T25	1		T55	1
auto[4160749568:4294967295]	auto[1]	52	1			T27	2		T28	1		T115	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1427

1

T3

2

T36

3

T27

16

auto[1]

1673

1

T3

2

T36

1

T26

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T27	1		T50	1		T55	1
auto[134217728:268435455]	93	1			T49	1		T51	1		T33	1
auto[268435456:402653183]	90	1			T26	1		T27	1		T23	2
auto[402653184:536870911]	99	1			T36	1		T39	1		T50	2
auto[536870912:671088639]	95	1			T27	2		T82	1		T131	1
auto[671088640:805306367]	94	1			T27	2		T39	1		T49	1
auto[805306368:939524095]	87	1			T27	1		T42	1		T51	1
auto[939524096:1073741823]	98	1			T3	1		T27	1		T49	1
auto[1073741824:1207959551]	89	1			T27	2		T83	1		T131	1
auto[1207959552:1342177279]	102	1			T27	1		T80	1		T82	1
auto[1342177280:1476395007]	81	1			T27	2		T42	1		T116	1
auto[1476395008:1610612735]	95	1			T27	2		T24	1		T49	1
auto[1610612736:1744830463]	106	1			T27	1		T51	1		T67	2
auto[1744830464:1879048191]	95	1			T27	3		T83	1		T50	1
auto[1879048192:2013265919]	117	1			T3	1		T27	1		T82	1
auto[2013265920:2147483647]	97	1			T189	1		T51	1		T88	1
auto[2147483648:2281701375]	91	1			T23	1		T24	1		T49	1
auto[2281701376:2415919103]	92	1			T27	1		T42	1		T29	1
auto[2415919104:2550136831]	105	1			T80	1		T23	1		T24	1
auto[2550136832:2684354559]	93	1			T27	1		T50	1		T67	1
auto[2684354560:2818572287]	93	1			T26	1		T42	1		T47	1
auto[2818572288:2952790015]	101	1			T27	1		T46	1		T24	1
auto[2952790016:3087007743]	105	1			T46	1		T80	1		T24	1
auto[3087007744:3221225471]	109	1			T36	1		T47	1		T116	1
auto[3221225472:3355443199]	103	1			T36	1		T27	1		T29	2
auto[3355443200:3489660927]	98	1			T27	1		T42	1		T46	1
auto[3489660928:3623878655]	95	1			T26	1		T27	1		T28	1
auto[3623878656:3758096383]	112	1			T27	1		T29	1		T39	1
auto[3758096384:3892314111]	82	1			T36	1		T39	1		T49	1
auto[3892314112:4026531839]	85	1			T3	1		T27	1		T115	2
auto[4026531840:4160749567]	84	1			T3	1		T27	1		T24	1
auto[4160749568:4294967295]	109	1			T27	3		T131	1		T20	1