Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2699

1

T3

4

T36

1

T26

3

auto[1]

264

1

T115

8

T116

1

T136

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T3	1		T27	1		T29	1
auto[134217728:268435455]	105	1			T82	1		T20	1		T23	1
auto[268435456:402653183]	92	1			T3	1		T27	1		T82	1
auto[402653184:536870911]	76	1			T51	2		T66	1		T128	1
auto[536870912:671088639]	84	1			T51	1		T128	1		T67	1
auto[671088640:805306367]	87	1			T29	1		T115	1		T50	1
auto[805306368:939524095]	95	1			T3	1		T36	1		T115	1
auto[939524096:1073741823]	100	1			T27	2		T47	1		T39	1
auto[1073741824:1207959551]	92	1			T42	1		T83	1		T115	1
auto[1207959552:1342177279]	102	1			T27	2		T46	1		T115	1
auto[1342177280:1476395007]	87	1			T27	2		T67	2		T226	1
auto[1476395008:1610612735]	67	1			T3	1		T27	1		T24	1
auto[1610612736:1744830463]	105	1			T82	1		T23	1		T49	1
auto[1744830464:1879048191]	85	1			T27	1		T49	1		T51	1
auto[1879048192:2013265919]	124	1			T27	2		T46	1		T39	1
auto[2013265920:2147483647]	96	1			T27	3		T80	1		T39	1
auto[2147483648:2281701375]	89	1			T115	2		T23	1		T50	1
auto[2281701376:2415919103]	92	1			T27	1		T115	1		T67	2
auto[2415919104:2550136831]	106	1			T27	1		T116	1		T49	1
auto[2550136832:2684354559]	86	1			T26	1		T27	1		T47	1
auto[2684354560:2818572287]	98	1			T82	1		T83	1		T24	1
auto[2818572288:2952790015]	92	1			T26	1		T27	1		T83	1
auto[2952790016:3087007743]	87	1			T116	1		T51	2		T63	1
auto[3087007744:3221225471]	84	1			T115	1		T49	2		T67	2
auto[3221225472:3355443199]	83	1			T27	2		T131	2		T116	1
auto[3355443200:3489660927]	86	1			T26	1		T116	1		T24	1
auto[3489660928:3623878655]	96	1			T27	1		T50	1		T95	1
auto[3623878656:3758096383]	83	1			T27	1		T51	1		T95	1
auto[3758096384:3892314111]	108	1			T27	1		T29	1		T39	1
auto[3892314112:4026531839]	89	1			T28	1		T29	1		T80	1
auto[4026531840:4160749567]	97	1			T20	1		T50	2		T67	1
auto[4160749568:4294967295]	102	1			T27	2		T46	1		T131	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	80	1			T3	1		T27	1		T29	1
auto[0:134217727]	auto[1]	8	1			T136	1		T255	1		T139	1
auto[134217728:268435455]	auto[0]	94	1			T82	1		T20	1		T23	1
auto[134217728:268435455]	auto[1]	11	1			T255	1		T378	1		T261	1
auto[268435456:402653183]	auto[0]	85	1			T3	1		T27	1		T82	1
auto[268435456:402653183]	auto[1]	7	1			T116	1		T256	1		T378	1
auto[402653184:536870911]	auto[0]	70	1			T51	2		T66	1		T128	1
auto[402653184:536870911]	auto[1]	6	1			T391	1		T261	1		T288	1
auto[536870912:671088639]	auto[0]	72	1			T51	1		T128	1		T67	1
auto[536870912:671088639]	auto[1]	12	1			T137	1		T246	1		T378	1
auto[671088640:805306367]	auto[0]	82	1			T29	1		T115	1		T50	1
auto[671088640:805306367]	auto[1]	5	1			T256	1		T223	1		T259	1
auto[805306368:939524095]	auto[0]	87	1			T3	1		T36	1		T115	1
auto[805306368:939524095]	auto[1]	8	1			T361	1		T391	1		T329	1
auto[939524096:1073741823]	auto[0]	88	1			T27	2		T47	1		T39	1
auto[939524096:1073741823]	auto[1]	12	1			T139	1		T300	1		T288	1
auto[1073741824:1207959551]	auto[0]	84	1			T42	1		T83	1		T115	1
auto[1073741824:1207959551]	auto[1]	8	1			T139	1		T361	1		T300	1
auto[1207959552:1342177279]	auto[0]	93	1			T27	2		T46	1		T50	1
auto[1207959552:1342177279]	auto[1]	9	1			T115	1		T255	1		T223	1
auto[1342177280:1476395007]	auto[0]	82	1			T27	2		T67	2		T226	1
auto[1342177280:1476395007]	auto[1]	5	1			T139	1		T256	1		T261	1
auto[1476395008:1610612735]	auto[0]	60	1			T3	1		T27	1		T24	1
auto[1476395008:1610612735]	auto[1]	7	1			T136	1		T255	1		T137	1
auto[1610612736:1744830463]	auto[0]	97	1			T82	1		T23	1		T49	1
auto[1610612736:1744830463]	auto[1]	8	1			T256	1		T408	1		T359	2
auto[1744830464:1879048191]	auto[0]	78	1			T27	1		T49	1		T51	1
auto[1744830464:1879048191]	auto[1]	7	1			T261	1		T288	2		T224	1
auto[1879048192:2013265919]	auto[0]	116	1			T27	2		T46	1		T39	1
auto[1879048192:2013265919]	auto[1]	8	1			T246	1		T299	1		T288	1
auto[2013265920:2147483647]	auto[0]	89	1			T27	3		T80	1		T39	1
auto[2013265920:2147483647]	auto[1]	7	1			T392	1		T416	1		T244	1
auto[2147483648:2281701375]	auto[0]	79	1			T23	1		T50	1		T95	1
auto[2147483648:2281701375]	auto[1]	10	1			T115	2		T256	1		T223	1
auto[2281701376:2415919103]	auto[0]	85	1			T27	1		T67	2		T95	1
auto[2281701376:2415919103]	auto[1]	7	1			T115	1		T255	1		T223	1
auto[2415919104:2550136831]	auto[0]	98	1			T27	1		T116	1		T49	1
auto[2415919104:2550136831]	auto[1]	8	1			T392	1		T288	1		T293	1
auto[2550136832:2684354559]	auto[0]	78	1			T26	1		T27	1		T47	1
auto[2550136832:2684354559]	auto[1]	8	1			T115	3		T261	1		T299	1
auto[2684354560:2818572287]	auto[0]	88	1			T82	1		T83	1		T24	1
auto[2684354560:2818572287]	auto[1]	10	1			T378	1		T355	1		T299	1
auto[2818572288:2952790015]	auto[0]	80	1			T26	1		T27	1		T83	1
auto[2818572288:2952790015]	auto[1]	12	1			T255	1		T261	1		T392	1
auto[2952790016:3087007743]	auto[0]	84	1			T116	1		T51	2		T63	1
auto[2952790016:3087007743]	auto[1]	3	1			T139	1		T409	1		T422	1
auto[3087007744:3221225471]	auto[0]	73	1			T49	2		T67	2		T198	1
auto[3087007744:3221225471]	auto[1]	11	1			T115	1		T255	1		T139	1
auto[3221225472:3355443199]	auto[0]	78	1			T27	2		T131	2		T116	1
auto[3221225472:3355443199]	auto[1]	5	1			T299	1		T300	1		T417	1
auto[3355443200:3489660927]	auto[0]	78	1			T26	1		T116	1		T24	1
auto[3355443200:3489660927]	auto[1]	8	1			T255	1		T139	1		T256	1
auto[3489660928:3623878655]	auto[0]	88	1			T27	1		T50	1		T95	1
auto[3489660928:3623878655]	auto[1]	8	1			T255	1		T223	1		T261	1
auto[3623878656:3758096383]	auto[0]	72	1			T27	1		T51	1		T95	1
auto[3623878656:3758096383]	auto[1]	11	1			T223	1		T261	1		T299	1
auto[3758096384:3892314111]	auto[0]	99	1			T27	1		T29	1		T39	1
auto[3758096384:3892314111]	auto[1]	9	1			T136	1		T223	3		T408	1
auto[3892314112:4026531839]	auto[0]	82	1			T28	1		T29	1		T80	1
auto[3892314112:4026531839]	auto[1]	7	1			T223	1		T261	1		T239	1
auto[4026531840:4160749567]	auto[0]	86	1			T20	1		T50	2		T67	1
auto[4026531840:4160749567]	auto[1]	11	1			T378	1		T261	1		T239	1
auto[4160749568:4294967295]	auto[0]	94	1			T27	2		T46	1		T131	1
auto[4160749568:4294967295]	auto[1]	8	1			T246	1		T239	2		T406	1