Unified Coverage Report :: Group Instance : sealing_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1443

1

T3

3

T36

2

T27

17

auto[1]

1657

1

T3

1

T36

2

T26

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T27	3		T131	1		T24	1
auto[134217728:268435455]	87	1			T82	1		T20	1		T24	1
auto[268435456:402653183]	111	1			T36	1		T27	2		T46	1
auto[402653184:536870911]	97	1			T39	2		T49	2		T51	1
auto[536870912:671088639]	91	1			T51	3		T25	1		T95	1
auto[671088640:805306367]	99	1			T23	1		T24	1		T33	1
auto[805306368:939524095]	98	1			T27	1		T49	2		T50	2
auto[939524096:1073741823]	95	1			T36	1		T42	1		T131	1
auto[1073741824:1207959551]	108	1			T27	1		T115	1		T116	1
auto[1207959552:1342177279]	115	1			T26	1		T39	1		T67	1
auto[1342177280:1476395007]	88	1			T27	1		T80	1		T51	1
auto[1476395008:1610612735]	112	1			T27	3		T29	1		T39	1
auto[1610612736:1744830463]	94	1			T27	2		T83	1		T24	1
auto[1744830464:1879048191]	104	1			T26	1		T27	3		T115	1
auto[1879048192:2013265919]	88	1			T82	2		T67	2		T88	1
auto[2013265920:2147483647]	84	1			T29	1		T116	1		T24	1
auto[2147483648:2281701375]	90	1			T3	2		T27	3		T24	1
auto[2281701376:2415919103]	98	1			T26	1		T29	1		T20	1
auto[2415919104:2550136831]	100	1			T27	1		T42	1		T131	1
auto[2550136832:2684354559]	95	1			T47	1		T115	1		T49	1
auto[2684354560:2818572287]	100	1			T27	2		T24	1		T67	1
auto[2818572288:2952790015]	103	1			T27	3		T23	1		T24	1
auto[2952790016:3087007743]	102	1			T36	1		T27	1		T42	1
auto[3087007744:3221225471]	99	1			T115	1		T49	1		T67	1
auto[3221225472:3355443199]	90	1			T46	1		T82	1		T49	1
auto[3355443200:3489660927]	82	1			T28	1		T80	1		T50	2
auto[3489660928:3623878655]	97	1			T36	1		T42	2		T39	1
auto[3623878656:3758096383]	104	1			T27	1		T47	1		T189	1
auto[3758096384:3892314111]	98	1			T3	1		T46	1		T80	1
auto[3892314112:4026531839]	93	1			T29	1		T49	1		T51	2
auto[4026531840:4160749567]	95	1			T27	3		T23	1		T67	1
auto[4160749568:4294967295]	80	1			T3	1		T27	2		T83	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T27	1		T24	1		T33	1
auto[0:134217727]	auto[1]	58	1			T27	2		T131	1		T67	1
auto[134217728:268435455]	auto[0]	41	1			T24	1		T67	1		T205	1
auto[134217728:268435455]	auto[1]	46	1			T82	1		T20	1		T202	1
auto[268435456:402653183]	auto[0]	48	1			T36	1		T23	1		T95	1
auto[268435456:402653183]	auto[1]	63	1			T27	2		T46	1		T49	1
auto[402653184:536870911]	auto[0]	45	1			T39	1		T49	1		T51	1
auto[402653184:536870911]	auto[1]	52	1			T39	1		T49	1		T67	1
auto[536870912:671088639]	auto[0]	44	1			T25	1		T95	1		T229	1
auto[536870912:671088639]	auto[1]	47	1			T51	3		T247	1		T246	1
auto[671088640:805306367]	auto[0]	49	1			T23	1		T24	1		T33	1
auto[671088640:805306367]	auto[1]	50	1			T88	1		T89	1		T6	2
auto[805306368:939524095]	auto[0]	43	1			T49	1		T50	1		T67	1
auto[805306368:939524095]	auto[1]	55	1			T27	1		T49	1		T50	1
auto[939524096:1073741823]	auto[0]	33	1			T23	1		T69	1		T229	1
auto[939524096:1073741823]	auto[1]	62	1			T36	1		T42	1		T131	1
auto[1073741824:1207959551]	auto[0]	58	1			T27	1		T116	1		T67	1
auto[1073741824:1207959551]	auto[1]	50	1			T115	1		T50	1		T128	1
auto[1207959552:1342177279]	auto[0]	46	1			T39	1		T55	1		T6	1
auto[1207959552:1342177279]	auto[1]	69	1			T26	1		T67	1		T198	1
auto[1342177280:1476395007]	auto[0]	40	1			T27	1		T51	1		T67	1
auto[1342177280:1476395007]	auto[1]	48	1			T80	1		T67	1		T200	1
auto[1476395008:1610612735]	auto[0]	55	1			T27	2		T50	1		T55	1
auto[1476395008:1610612735]	auto[1]	57	1			T27	1		T29	1		T39	1
auto[1610612736:1744830463]	auto[0]	48	1			T27	2		T89	1		T6	1
auto[1610612736:1744830463]	auto[1]	46	1			T83	1		T24	1		T49	2
auto[1744830464:1879048191]	auto[0]	52	1			T27	2		T195	1		T49	1
auto[1744830464:1879048191]	auto[1]	52	1			T26	1		T27	1		T115	1
auto[1879048192:2013265919]	auto[0]	38	1			T67	1		T88	1		T6	1
auto[1879048192:2013265919]	auto[1]	50	1			T82	2		T67	1		T260	1
auto[2013265920:2147483647]	auto[0]	42	1			T24	1		T67	1		T394	1
auto[2013265920:2147483647]	auto[1]	42	1			T29	1		T116	1		T202	1
auto[2147483648:2281701375]	auto[0]	44	1			T3	2		T27	1		T24	1
auto[2147483648:2281701375]	auto[1]	46	1			T27	2		T50	1		T51	1
auto[2281701376:2415919103]	auto[0]	46	1			T51	2		T67	1		T25	1
auto[2281701376:2415919103]	auto[1]	52	1			T26	1		T29	1		T20	1
auto[2415919104:2550136831]	auto[0]	50	1			T33	1		T43	1		T69	1
auto[2415919104:2550136831]	auto[1]	50	1			T27	1		T42	1		T131	1
auto[2550136832:2684354559]	auto[0]	43	1			T88	1		T6	1		T138	1
auto[2550136832:2684354559]	auto[1]	52	1			T47	1		T115	1		T49	1
auto[2684354560:2818572287]	auto[0]	43	1			T67	1		T43	1		T247	1
auto[2684354560:2818572287]	auto[1]	57	1			T27	2		T24	1		T95	1
auto[2818572288:2952790015]	auto[0]	51	1			T27	3		T23	1		T24	1
auto[2818572288:2952790015]	auto[1]	52	1			T49	1		T50	1		T200	1
auto[2952790016:3087007743]	auto[0]	45	1			T42	1		T39	1		T51	1
auto[2952790016:3087007743]	auto[1]	57	1			T36	1		T27	1		T116	1
auto[3087007744:3221225471]	auto[0]	44	1			T49	1		T6	2		T264	1
auto[3087007744:3221225471]	auto[1]	55	1			T115	1		T67	1		T95	1
auto[3221225472:3355443199]	auto[0]	46	1			T50	2		T67	1		T25	1
auto[3221225472:3355443199]	auto[1]	44	1			T46	1		T82	1		T49	1
auto[3355443200:3489660927]	auto[0]	36	1			T80	1		T128	1		T55	1
auto[3355443200:3489660927]	auto[1]	46	1			T28	1		T50	2		T67	1
auto[3489660928:3623878655]	auto[0]	45	1			T36	1		T42	1		T39	1
auto[3489660928:3623878655]	auto[1]	52	1			T42	1		T55	1		T229	1
auto[3623878656:3758096383]	auto[0]	43	1			T27	1		T47	1		T189	1
auto[3623878656:3758096383]	auto[1]	61	1			T67	1		T54	1		T6	1
auto[3758096384:3892314111]	auto[0]	48	1			T3	1		T66	1		T90	1
auto[3758096384:3892314111]	auto[1]	50	1			T46	1		T80	1		T67	1
auto[3892314112:4026531839]	auto[0]	49	1			T51	1		T95	1		T237	1
auto[3892314112:4026531839]	auto[1]	44	1			T29	1		T49	1		T51	1
auto[4026531840:4160749567]	auto[0]	46	1			T27	2		T23	1		T67	1
auto[4026531840:4160749567]	auto[1]	49	1			T27	1		T6	2		T44	1
auto[4160749568:4294967295]	auto[0]	37	1			T27	1		T67	1		T95	1
auto[4160749568:4294967295]	auto[1]	43	1			T3	1		T27	1		T83	2