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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6424 1 T3 8 T36 2 T26 6
auto[1] 282 1 T115 14 T116 3 T136 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 2695 1 T3 4 T36 1 T26 2
auto[134217728:268435455] 136 1 T27 1 T115 1 T39 1
auto[268435456:402653183] 137 1 T27 1 T29 1 T80 1
auto[402653184:536870911] 135 1 T3 1 T27 2 T46 1
auto[536870912:671088639] 140 1 T26 1 T27 1 T46 1
auto[671088640:805306367] 146 1 T36 1 T27 1 T42 1
auto[805306368:939524095] 129 1 T26 1 T27 1 T115 2
auto[939524096:1073741823] 146 1 T82 1 T115 1 T39 1
auto[1073741824:1207959551] 120 1 T27 1 T29 1 T80 1
auto[1207959552:1342177279] 143 1 T26 1 T27 1 T115 1
auto[1342177280:1476395007] 137 1 T27 1 T29 1 T80 1
auto[1476395008:1610612735] 115 1 T28 1 T80 1 T83 1
auto[1610612736:1744830463] 130 1 T46 1 T115 1 T116 1
auto[1744830464:1879048191] 130 1 T3 1 T27 3 T82 2
auto[1879048192:2013265919] 114 1 T39 1 T67 1 T198 1
auto[2013265920:2147483647] 131 1 T27 1 T29 1 T116 2
auto[2147483648:2281701375] 120 1 T27 1 T46 1 T83 1
auto[2281701376:2415919103] 117 1 T27 1 T39 1 T67 1
auto[2415919104:2550136831] 135 1 T27 1 T83 1 T39 1
auto[2550136832:2684354559] 138 1 T27 2 T29 1 T80 1
auto[2684354560:2818572287] 103 1 T27 2 T29 1 T23 1
auto[2818572288:2952790015] 120 1 T27 3 T83 1 T20 1
auto[2952790016:3087007743] 116 1 T115 1 T39 1 T33 1
auto[3087007744:3221225471] 133 1 T3 1 T27 1 T131 1
auto[3221225472:3355443199] 98 1 T27 1 T80 1 T195 1
auto[3355443200:3489660927] 115 1 T47 1 T115 1 T39 1
auto[3489660928:3623878655] 141 1 T27 1 T29 1 T23 1
auto[3623878656:3758096383] 132 1 T27 1 T80 1 T82 1
auto[3758096384:3892314111] 133 1 T26 1 T27 2 T29 2
auto[3892314112:4026531839] 130 1 T27 1 T29 2 T83 1
auto[4026531840:4160749567] 146 1 T80 2 T47 1 T115 1
auto[4160749568:4294967295] 145 1 T3 1 T115 1 T49 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 2688 1 T3 4 T36 1 T26 2
auto[0:134217727] auto[1] 7 1 T115 1 T139 1 T259 1
auto[134217728:268435455] auto[0] 131 1 T27 1 T39 1 T24 2
auto[134217728:268435455] auto[1] 5 1 T115 1 T408 1 T412 2
auto[268435456:402653183] auto[0] 134 1 T27 1 T29 1 T80 1
auto[268435456:402653183] auto[1] 3 1 T355 1 T409 1 T415 1
auto[402653184:536870911] auto[0] 127 1 T3 1 T27 2 T46 1
auto[402653184:536870911] auto[1] 8 1 T378 1 T300 1 T275 1
auto[536870912:671088639] auto[0] 125 1 T26 1 T27 1 T46 1
auto[536870912:671088639] auto[1] 15 1 T115 2 T137 1 T378 1
auto[671088640:805306367] auto[0] 137 1 T36 1 T27 1 T42 1
auto[671088640:805306367] auto[1] 9 1 T261 1 T259 1 T299 1
auto[805306368:939524095] auto[0] 117 1 T26 1 T27 1 T39 1
auto[805306368:939524095] auto[1] 12 1 T115 2 T378 2 T223 1
auto[939524096:1073741823] auto[0] 134 1 T82 1 T39 1 T116 1
auto[939524096:1073741823] auto[1] 12 1 T115 1 T137 1 T256 2
auto[1073741824:1207959551] auto[0] 111 1 T27 1 T29 1 T80 1
auto[1073741824:1207959551] auto[1] 9 1 T115 1 T137 1 T223 2
auto[1207959552:1342177279] auto[0] 136 1 T26 1 T27 1 T116 1
auto[1207959552:1342177279] auto[1] 7 1 T115 1 T255 1 T223 1
auto[1342177280:1476395007] auto[0] 127 1 T27 1 T29 1 T80 1
auto[1342177280:1476395007] auto[1] 10 1 T299 1 T239 1 T275 1
auto[1476395008:1610612735] auto[0] 110 1 T28 1 T80 1 T83 1
auto[1476395008:1610612735] auto[1] 5 1 T256 1 T408 1 T411 1
auto[1610612736:1744830463] auto[0] 126 1 T46 1 T115 1 T116 1
auto[1610612736:1744830463] auto[1] 4 1 T406 1 T407 1 T225 1
auto[1744830464:1879048191] auto[0] 124 1 T3 1 T27 3 T82 2
auto[1744830464:1879048191] auto[1] 6 1 T115 1 T392 1 T300 1
auto[1879048192:2013265919] auto[0] 104 1 T39 1 T67 1 T198 1
auto[1879048192:2013265919] auto[1] 10 1 T246 1 T378 1 T239 1
auto[2013265920:2147483647] auto[0] 119 1 T27 1 T29 1 T49 1
auto[2013265920:2147483647] auto[1] 12 1 T116 2 T299 1 T239 1
auto[2147483648:2281701375] auto[0] 108 1 T27 1 T46 1 T83 1
auto[2147483648:2281701375] auto[1] 12 1 T246 1 T239 2 T409 2
auto[2281701376:2415919103] auto[0] 109 1 T27 1 T39 1 T67 1
auto[2281701376:2415919103] auto[1] 8 1 T378 1 T288 1 T408 1
auto[2415919104:2550136831] auto[0] 122 1 T27 1 T83 1 T39 1
auto[2415919104:2550136831] auto[1] 13 1 T256 1 T223 1 T300 1
auto[2550136832:2684354559] auto[0] 128 1 T27 2 T29 1 T80 1
auto[2550136832:2684354559] auto[1] 10 1 T115 1 T255 2 T137 1
auto[2684354560:2818572287] auto[0] 90 1 T27 2 T29 1 T23 1
auto[2684354560:2818572287] auto[1] 13 1 T139 1 T223 2 T391 1
auto[2818572288:2952790015] auto[0] 113 1 T27 3 T83 1 T20 1
auto[2818572288:2952790015] auto[1] 7 1 T137 1 T246 1 T378 1
auto[2952790016:3087007743] auto[0] 109 1 T39 1 T33 1 T202 1
auto[2952790016:3087007743] auto[1] 7 1 T115 1 T136 1 T361 1
auto[3087007744:3221225471] auto[0] 127 1 T3 1 T27 1 T131 1
auto[3087007744:3221225471] auto[1] 6 1 T137 1 T408 1 T239 1
auto[3221225472:3355443199] auto[0] 91 1 T27 1 T80 1 T195 1
auto[3221225472:3355443199] auto[1] 7 1 T411 1 T416 1 T417 1
auto[3355443200:3489660927] auto[0] 110 1 T47 1 T115 1 T39 1
auto[3355443200:3489660927] auto[1] 5 1 T255 1 T355 1 T391 1
auto[3489660928:3623878655] auto[0] 128 1 T27 1 T29 1 T23 1
auto[3489660928:3623878655] auto[1] 13 1 T223 1 T355 1 T392 1
auto[3623878656:3758096383] auto[0] 124 1 T27 1 T80 1 T82 1
auto[3623878656:3758096383] auto[1] 8 1 T329 1 T408 1 T275 1
auto[3758096384:3892314111] auto[0] 126 1 T26 1 T27 2 T29 2
auto[3758096384:3892314111] auto[1] 7 1 T136 1 T261 2 T406 1
auto[3892314112:4026531839] auto[0] 119 1 T27 1 T29 2 T83 1
auto[3892314112:4026531839] auto[1] 11 1 T255 1 T256 1 T378 1
auto[4026531840:4160749567] auto[0] 134 1 T80 2 T47 1 T116 1
auto[4026531840:4160749567] auto[1] 12 1 T115 1 T116 1 T137 1
auto[4160749568:4294967295] auto[0] 136 1 T3 1 T49 1 T67 2
auto[4160749568:4294967295] auto[1] 9 1 T115 1 T137 1 T246 1

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