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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4124 1 T3 4 T36 8 T26 4
auto[1] 2078 1 T3 4 T26 2 T27 20



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 222 1 T27 4 T23 2 T24 2
auto[134217728:268435455] 196 1 T3 2 T28 2 T42 2
auto[268435456:402653183] 164 1 T36 2 T80 2 T39 2
auto[402653184:536870911] 178 1 T39 2 T24 2 T51 4
auto[536870912:671088639] 184 1 T42 2 T50 2 T51 2
auto[671088640:805306367] 214 1 T36 2 T47 2 T39 2
auto[805306368:939524095] 166 1 T27 2 T29 2 T46 2
auto[939524096:1073741823] 178 1 T116 2 T195 2 T51 4
auto[1073741824:1207959551] 150 1 T36 2 T131 2 T24 2
auto[1207959552:1342177279] 178 1 T27 2 T115 2 T49 2
auto[1342177280:1476395007] 180 1 T83 2 T51 2 T67 4
auto[1476395008:1610612735] 182 1 T3 2 T27 6 T51 4
auto[1610612736:1744830463] 186 1 T27 2 T131 2 T189 2
auto[1744830464:1879048191] 178 1 T23 2 T49 2 T51 2
auto[1879048192:2013265919] 190 1 T46 2 T39 2 T116 2
auto[2013265920:2147483647] 212 1 T20 2 T24 2 T50 2
auto[2147483648:2281701375] 192 1 T27 2 T29 2 T46 2
auto[2281701376:2415919103] 202 1 T27 4 T116 4 T50 2
auto[2415919104:2550136831] 216 1 T26 2 T27 2 T47 2
auto[2550136832:2684354559] 194 1 T42 2 T24 2 T49 2
auto[2684354560:2818572287] 190 1 T36 2 T80 2 T50 2
auto[2818572288:2952790015] 240 1 T27 8 T42 2 T83 2
auto[2952790016:3087007743] 188 1 T3 2 T26 2 T27 6
auto[3087007744:3221225471] 220 1 T27 6 T80 2 T20 2
auto[3221225472:3355443199] 194 1 T27 4 T82 2 T115 2
auto[3355443200:3489660927] 194 1 T27 2 T20 2 T51 2
auto[3489660928:3623878655] 184 1 T27 2 T29 2 T82 2
auto[3623878656:3758096383] 214 1 T27 6 T131 2 T115 2
auto[3758096384:3892314111] 200 1 T26 2 T27 4 T82 2
auto[3892314112:4026531839] 232 1 T27 2 T49 2 T67 2
auto[4026531840:4160749567] 170 1 T29 2 T82 2 T24 2
auto[4160749568:4294967295] 214 1 T3 2 T115 2 T49 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 144 1 T27 2 T24 2 T49 2
auto[0:134217727] auto[1] 78 1 T27 2 T23 2 T67 2
auto[134217728:268435455] auto[0] 140 1 T3 2 T24 2 T54 2
auto[134217728:268435455] auto[1] 56 1 T28 2 T42 2 T39 2
auto[268435456:402653183] auto[0] 90 1 T36 2 T80 2 T6 2
auto[268435456:402653183] auto[1] 74 1 T39 2 T64 2 T60 2
auto[402653184:536870911] auto[0] 118 1 T39 2 T51 2 T247 2
auto[402653184:536870911] auto[1] 60 1 T24 2 T51 2 T55 2
auto[536870912:671088639] auto[0] 126 1 T51 2 T128 2 T25 2
auto[536870912:671088639] auto[1] 58 1 T42 2 T50 2 T6 4
auto[671088640:805306367] auto[0] 144 1 T36 2 T47 2 T39 2
auto[671088640:805306367] auto[1] 70 1 T6 2 T397 2 T122 2
auto[805306368:939524095] auto[0] 106 1 T27 2 T29 2 T226 2
auto[805306368:939524095] auto[1] 60 1 T46 2 T245 2 T203 2
auto[939524096:1073741823] auto[0] 118 1 T116 2 T195 2 T51 2
auto[939524096:1073741823] auto[1] 60 1 T51 2 T201 2 T44 2
auto[1073741824:1207959551] auto[0] 110 1 T36 2 T131 2 T24 2
auto[1073741824:1207959551] auto[1] 40 1 T6 4 T45 2 T203 2
auto[1207959552:1342177279] auto[0] 130 1 T27 2 T115 2 T49 2
auto[1207959552:1342177279] auto[1] 48 1 T51 2 T33 2 T198 2
auto[1342177280:1476395007] auto[0] 110 1 T83 2 T67 4 T88 2
auto[1342177280:1476395007] auto[1] 70 1 T51 2 T54 2 T243 2
auto[1476395008:1610612735] auto[0] 110 1 T27 4 T67 2 T413 2
auto[1476395008:1610612735] auto[1] 72 1 T3 2 T27 2 T51 4
auto[1610612736:1744830463] auto[0] 128 1 T24 2 T49 2 T51 2
auto[1610612736:1744830463] auto[1] 58 1 T27 2 T131 2 T189 2
auto[1744830464:1879048191] auto[0] 122 1 T23 2 T49 2 T51 2
auto[1744830464:1879048191] auto[1] 56 1 T67 4 T95 2 T260 2
auto[1879048192:2013265919] auto[0] 106 1 T39 2 T116 2 T23 2
auto[1879048192:2013265919] auto[1] 84 1 T46 2 T394 2 T122 4
auto[2013265920:2147483647] auto[0] 132 1 T20 2 T24 2 T67 2
auto[2013265920:2147483647] auto[1] 80 1 T50 2 T51 2 T67 2
auto[2147483648:2281701375] auto[0] 136 1 T27 2 T49 2 T33 2
auto[2147483648:2281701375] auto[1] 56 1 T29 2 T46 2 T6 2
auto[2281701376:2415919103] auto[0] 132 1 T27 2 T116 2 T51 2
auto[2281701376:2415919103] auto[1] 70 1 T27 2 T116 2 T50 2
auto[2415919104:2550136831] auto[0] 138 1 T26 2 T27 2 T47 2
auto[2415919104:2550136831] auto[1] 78 1 T198 2 T95 2 T229 2
auto[2550136832:2684354559] auto[0] 138 1 T42 2 T24 2 T49 2
auto[2550136832:2684354559] auto[1] 56 1 T6 2 T171 2 T173 2
auto[2684354560:2818572287] auto[0] 136 1 T36 2 T50 2 T128 2
auto[2684354560:2818572287] auto[1] 54 1 T80 2 T70 2 T292 2
auto[2818572288:2952790015] auto[0] 146 1 T27 4 T42 2 T83 2
auto[2818572288:2952790015] auto[1] 94 1 T27 4 T51 2 T88 2
auto[2952790016:3087007743] auto[0] 140 1 T3 2 T27 2 T42 2
auto[2952790016:3087007743] auto[1] 48 1 T26 2 T27 4 T54 2
auto[3087007744:3221225471] auto[0] 148 1 T27 6 T80 2 T20 2
auto[3087007744:3221225471] auto[1] 72 1 T23 2 T55 2 T202 2
auto[3221225472:3355443199] auto[0] 122 1 T27 2 T82 2 T115 2
auto[3221225472:3355443199] auto[1] 72 1 T27 2 T49 2 T50 2
auto[3355443200:3489660927] auto[0] 122 1 T20 2 T67 4 T43 2
auto[3355443200:3489660927] auto[1] 72 1 T27 2 T51 2 T67 2
auto[3489660928:3623878655] auto[0] 130 1 T27 2 T82 2 T67 2
auto[3489660928:3623878655] auto[1] 54 1 T29 2 T6 4 T44 2
auto[3623878656:3758096383] auto[0] 146 1 T27 6 T115 2 T24 2
auto[3623878656:3758096383] auto[1] 68 1 T131 2 T50 2 T67 2
auto[3758096384:3892314111] auto[0] 138 1 T26 2 T27 4 T82 2
auto[3758096384:3892314111] auto[1] 62 1 T50 4 T51 2 T89 2
auto[3892314112:4026531839] auto[0] 140 1 T27 2 T49 2 T25 2
auto[3892314112:4026531839] auto[1] 92 1 T67 2 T229 2 T243 2
auto[4026531840:4160749567] auto[0] 114 1 T29 2 T82 2 T24 2
auto[4026531840:4160749567] auto[1] 56 1 T50 2 T67 4 T6 2
auto[4160749568:4294967295] auto[0] 164 1 T115 2 T49 2 T237 2
auto[4160749568:4294967295] auto[1] 50 1 T3 2 T67 2 T202 2

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