Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.81 99.07 98.06 98.29 100.00 99.19 98.41 91.61


Total test records in report: 1077
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T1006 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1957416291 Apr 23 01:51:51 PM PDT 24 Apr 23 01:51:53 PM PDT 24 9773117 ps
T1007 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1035443940 Apr 23 01:51:48 PM PDT 24 Apr 23 01:52:17 PM PDT 24 1334428006 ps
T1008 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.468089926 Apr 23 01:51:42 PM PDT 24 Apr 23 01:51:46 PM PDT 24 262736373 ps
T1009 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4021444809 Apr 23 01:51:37 PM PDT 24 Apr 23 01:51:40 PM PDT 24 225741733 ps
T1010 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1056960782 Apr 23 01:51:57 PM PDT 24 Apr 23 01:51:59 PM PDT 24 60599310 ps
T154 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.339930350 Apr 23 01:51:47 PM PDT 24 Apr 23 01:51:58 PM PDT 24 908204633 ps
T1011 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1986313343 Apr 23 01:51:48 PM PDT 24 Apr 23 01:51:52 PM PDT 24 64499556 ps
T1012 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.696123444 Apr 23 01:51:57 PM PDT 24 Apr 23 01:52:11 PM PDT 24 393451390 ps
T1013 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2940508560 Apr 23 01:51:55 PM PDT 24 Apr 23 01:51:57 PM PDT 24 51228368 ps
T1014 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3651450809 Apr 23 01:51:40 PM PDT 24 Apr 23 01:51:45 PM PDT 24 104178715 ps
T1015 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4134901714 Apr 23 01:51:49 PM PDT 24 Apr 23 01:51:54 PM PDT 24 332577571 ps
T1016 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3583014493 Apr 23 01:51:47 PM PDT 24 Apr 23 01:52:02 PM PDT 24 745974259 ps
T1017 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2534656217 Apr 23 01:52:01 PM PDT 24 Apr 23 01:52:03 PM PDT 24 34763934 ps
T1018 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2775145068 Apr 23 01:51:51 PM PDT 24 Apr 23 01:51:54 PM PDT 24 16844664 ps
T1019 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3549361651 Apr 23 01:51:48 PM PDT 24 Apr 23 01:51:59 PM PDT 24 673185979 ps
T1020 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.790393296 Apr 23 01:51:41 PM PDT 24 Apr 23 01:51:44 PM PDT 24 15177607 ps
T1021 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2149610749 Apr 23 01:51:39 PM PDT 24 Apr 23 01:51:43 PM PDT 24 130883718 ps
T158 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.4070239350 Apr 23 01:51:49 PM PDT 24 Apr 23 01:51:55 PM PDT 24 141777092 ps
T1022 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3060086333 Apr 23 01:51:48 PM PDT 24 Apr 23 01:51:51 PM PDT 24 19811768 ps
T1023 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.585679598 Apr 23 01:51:56 PM PDT 24 Apr 23 01:51:58 PM PDT 24 11533635 ps
T1024 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3194367134 Apr 23 01:51:45 PM PDT 24 Apr 23 01:51:50 PM PDT 24 174172309 ps
T1025 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3374986083 Apr 23 01:51:56 PM PDT 24 Apr 23 01:52:06 PM PDT 24 153707807 ps
T1026 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.629946951 Apr 23 01:51:42 PM PDT 24 Apr 23 01:51:45 PM PDT 24 14201162 ps
T1027 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3858467262 Apr 23 01:51:43 PM PDT 24 Apr 23 01:51:52 PM PDT 24 1155914407 ps
T1028 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1840498717 Apr 23 01:51:50 PM PDT 24 Apr 23 01:51:55 PM PDT 24 84815477 ps
T161 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.383835065 Apr 23 01:51:35 PM PDT 24 Apr 23 01:51:39 PM PDT 24 110798168 ps
T1029 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1582323163 Apr 23 01:51:48 PM PDT 24 Apr 23 01:51:53 PM PDT 24 95080966 ps
T1030 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.880594083 Apr 23 01:51:58 PM PDT 24 Apr 23 01:52:01 PM PDT 24 722833685 ps
T1031 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1756523434 Apr 23 01:51:46 PM PDT 24 Apr 23 01:51:50 PM PDT 24 98871258 ps
T160 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.458090147 Apr 23 01:51:50 PM PDT 24 Apr 23 01:51:55 PM PDT 24 206054814 ps
T1032 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1161967712 Apr 23 01:51:39 PM PDT 24 Apr 23 01:51:42 PM PDT 24 17159780 ps
T1033 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2523232519 Apr 23 01:51:41 PM PDT 24 Apr 23 01:51:44 PM PDT 24 94234592 ps
T1034 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2109970546 Apr 23 01:51:36 PM PDT 24 Apr 23 01:51:38 PM PDT 24 402448884 ps
T1035 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.148663605 Apr 23 01:51:41 PM PDT 24 Apr 23 01:51:51 PM PDT 24 1660037655 ps
T1036 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1077916778 Apr 23 01:51:49 PM PDT 24 Apr 23 01:51:54 PM PDT 24 100968849 ps
T1037 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1360402263 Apr 23 01:51:52 PM PDT 24 Apr 23 01:51:56 PM PDT 24 121122641 ps
T1038 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1617955242 Apr 23 01:51:34 PM PDT 24 Apr 23 01:51:40 PM PDT 24 380827622 ps
T1039 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4110456349 Apr 23 01:51:47 PM PDT 24 Apr 23 01:51:51 PM PDT 24 541741323 ps
T1040 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2696877858 Apr 23 01:51:54 PM PDT 24 Apr 23 01:51:56 PM PDT 24 38718464 ps
T1041 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.431731692 Apr 23 01:51:46 PM PDT 24 Apr 23 01:51:59 PM PDT 24 268820792 ps
T1042 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.503885235 Apr 23 01:51:45 PM PDT 24 Apr 23 01:51:48 PM PDT 24 15476404 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3825183207 Apr 23 01:51:39 PM PDT 24 Apr 23 01:51:43 PM PDT 24 206526023 ps
T1044 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4127279511 Apr 23 01:51:48 PM PDT 24 Apr 23 01:51:50 PM PDT 24 49577782 ps
T1045 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1184855922 Apr 23 01:51:49 PM PDT 24 Apr 23 01:51:52 PM PDT 24 26919913 ps
T1046 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2234937824 Apr 23 01:51:45 PM PDT 24 Apr 23 01:51:49 PM PDT 24 108100103 ps
T1047 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2453386414 Apr 23 01:51:50 PM PDT 24 Apr 23 01:51:56 PM PDT 24 435134007 ps
T1048 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3781127013 Apr 23 01:52:04 PM PDT 24 Apr 23 01:52:10 PM PDT 24 12127124 ps
T1049 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2113842878 Apr 23 01:51:51 PM PDT 24 Apr 23 01:51:54 PM PDT 24 32494835 ps
T1050 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2314848875 Apr 23 01:51:50 PM PDT 24 Apr 23 01:51:56 PM PDT 24 153858359 ps
T1051 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3944326046 Apr 23 01:51:54 PM PDT 24 Apr 23 01:51:56 PM PDT 24 14564608 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2038053928 Apr 23 01:51:40 PM PDT 24 Apr 23 01:51:44 PM PDT 24 69083173 ps
T1053 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.517222720 Apr 23 01:52:01 PM PDT 24 Apr 23 01:52:03 PM PDT 24 31128860 ps
T152 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2027346720 Apr 23 01:51:34 PM PDT 24 Apr 23 01:51:41 PM PDT 24 118513791 ps
T1054 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.370961024 Apr 23 01:51:45 PM PDT 24 Apr 23 01:51:51 PM PDT 24 107896382 ps
T1055 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1101506907 Apr 23 01:51:44 PM PDT 24 Apr 23 01:51:47 PM PDT 24 33229766 ps
T1056 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3423570232 Apr 23 01:51:42 PM PDT 24 Apr 23 01:51:46 PM PDT 24 140146903 ps
T1057 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.519420493 Apr 23 01:52:07 PM PDT 24 Apr 23 01:52:08 PM PDT 24 61255100 ps
T1058 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.427816623 Apr 23 01:51:51 PM PDT 24 Apr 23 01:51:55 PM PDT 24 186097850 ps
T1059 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4280128088 Apr 23 01:51:45 PM PDT 24 Apr 23 01:51:49 PM PDT 24 15336723 ps
T1060 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1171537569 Apr 23 01:51:49 PM PDT 24 Apr 23 01:51:56 PM PDT 24 1598684878 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.334242700 Apr 23 01:51:47 PM PDT 24 Apr 23 01:51:59 PM PDT 24 705841181 ps
T1062 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3711372369 Apr 23 01:51:36 PM PDT 24 Apr 23 01:51:41 PM PDT 24 108746359 ps
T1063 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3326572559 Apr 23 01:51:57 PM PDT 24 Apr 23 01:51:59 PM PDT 24 127483918 ps
T1064 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4261347646 Apr 23 01:51:47 PM PDT 24 Apr 23 01:52:03 PM PDT 24 411525490 ps
T1065 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2697330521 Apr 23 01:51:48 PM PDT 24 Apr 23 01:51:51 PM PDT 24 44506801 ps
T1066 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.467623307 Apr 23 01:51:53 PM PDT 24 Apr 23 01:51:55 PM PDT 24 42909104 ps
T1067 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3149293443 Apr 23 01:51:42 PM PDT 24 Apr 23 01:51:55 PM PDT 24 3893597688 ps
T1068 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1766312907 Apr 23 01:51:53 PM PDT 24 Apr 23 01:51:55 PM PDT 24 30077446 ps
T1069 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.521311234 Apr 23 01:51:59 PM PDT 24 Apr 23 01:52:01 PM PDT 24 38635493 ps
T1070 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2989397879 Apr 23 01:51:40 PM PDT 24 Apr 23 01:51:42 PM PDT 24 19415022 ps
T1071 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.386094427 Apr 23 01:51:49 PM PDT 24 Apr 23 01:51:52 PM PDT 24 29783001 ps
T1072 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2796332447 Apr 23 01:51:51 PM PDT 24 Apr 23 01:51:57 PM PDT 24 697001941 ps
T1073 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4171103992 Apr 23 01:51:49 PM PDT 24 Apr 23 01:51:51 PM PDT 24 41907778 ps
T1074 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2533401845 Apr 23 01:51:57 PM PDT 24 Apr 23 01:52:00 PM PDT 24 77009498 ps
T1075 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1228429621 Apr 23 01:51:42 PM PDT 24 Apr 23 01:51:47 PM PDT 24 388174381 ps
T1076 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.215164012 Apr 23 01:51:41 PM PDT 24 Apr 23 01:51:47 PM PDT 24 396695165 ps
T1077 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.936374395 Apr 23 01:51:53 PM PDT 24 Apr 23 01:51:56 PM PDT 24 92841631 ps

Test location /workspace/coverage/default/30.keymgr_custom_cm.3808058390
Short name T3
Test name
Test status
Simulation time 109863207 ps
CPU time 3.62 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:56:43 PM PDT 24
Peak memory 218636 kb
Host smart-1c335193-9dac-451f-b7d4-2c789516e659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808058390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3808058390
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.569607816
Short name T6
Test name
Test status
Simulation time 13210111348 ps
CPU time 311.12 seconds
Started Apr 23 01:56:06 PM PDT 24
Finished Apr 23 02:01:17 PM PDT 24
Peak memory 222808 kb
Host smart-1bae7e4f-a1df-467c-964a-37fb2325e8c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569607816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.569607816
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4180503412
Short name T27
Test name
Test status
Simulation time 1964549251 ps
CPU time 22.39 seconds
Started Apr 23 01:57:27 PM PDT 24
Finished Apr 23 01:57:50 PM PDT 24
Peak memory 215260 kb
Host smart-de181a79-8fec-4e0e-a224-8d343a08a325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180503412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4180503412
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.832360279
Short name T67
Test name
Test status
Simulation time 758760175 ps
CPU time 23.28 seconds
Started Apr 23 01:54:49 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 222884 kb
Host smart-0b1ff288-1995-4a73-a268-b57615a29fea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832360279 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.832360279
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2170547340
Short name T41
Test name
Test status
Simulation time 1149426051 ps
CPU time 11.18 seconds
Started Apr 23 01:54:50 PM PDT 24
Finished Apr 23 01:55:02 PM PDT 24
Peak memory 239532 kb
Host smart-86d81280-18d0-43c7-95c8-5e24ee23b8b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170547340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2170547340
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2401070003
Short name T111
Test name
Test status
Simulation time 411288741 ps
CPU time 10.87 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 214600 kb
Host smart-b76d01da-e391-4576-ae08-4b335b394cb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401070003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2401070003
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1816660785
Short name T36
Test name
Test status
Simulation time 3739219090 ps
CPU time 12.7 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:57:23 PM PDT 24
Peak memory 216884 kb
Host smart-3596b7f6-51ba-488a-a35f-94e7221dbad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816660785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1816660785
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.309882530
Short name T45
Test name
Test status
Simulation time 1137633947 ps
CPU time 43.47 seconds
Started Apr 23 01:57:15 PM PDT 24
Finished Apr 23 01:57:59 PM PDT 24
Peak memory 216876 kb
Host smart-d36cc683-cc48-470e-b915-540ee1ff69f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309882530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.309882530
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2110802926
Short name T51
Test name
Test status
Simulation time 3206181661 ps
CPU time 25.55 seconds
Started Apr 23 01:56:31 PM PDT 24
Finished Apr 23 01:56:57 PM PDT 24
Peak memory 220264 kb
Host smart-c2b7062f-7f41-4845-82a8-0c6e1c76c635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110802926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2110802926
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.384198731
Short name T115
Test name
Test status
Simulation time 1666354586 ps
CPU time 13.75 seconds
Started Apr 23 01:56:32 PM PDT 24
Finished Apr 23 01:56:46 PM PDT 24
Peak memory 215696 kb
Host smart-5d5923e9-1f6e-4ade-89aa-9341afe7d129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=384198731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.384198731
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2067344461
Short name T9
Test name
Test status
Simulation time 202883835 ps
CPU time 1.77 seconds
Started Apr 23 01:57:33 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 217612 kb
Host smart-9512ddbb-8743-4040-8a86-81d666c3496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067344461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2067344461
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2550314905
Short name T48
Test name
Test status
Simulation time 70599719 ps
CPU time 2.6 seconds
Started Apr 23 01:54:41 PM PDT 24
Finished Apr 23 01:54:45 PM PDT 24
Peak memory 206392 kb
Host smart-a38a7bee-b8a7-4832-8919-b2227c2fbd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550314905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2550314905
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3876025705
Short name T239
Test name
Test status
Simulation time 1893567242 ps
CPU time 17.26 seconds
Started Apr 23 01:56:15 PM PDT 24
Finished Apr 23 01:56:33 PM PDT 24
Peak memory 215832 kb
Host smart-e25e230f-2532-4d57-a31b-028332dce114
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876025705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3876025705
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2171719994
Short name T95
Test name
Test status
Simulation time 866287908 ps
CPU time 10.41 seconds
Started Apr 23 01:55:07 PM PDT 24
Finished Apr 23 01:55:18 PM PDT 24
Peak memory 214796 kb
Host smart-5404c0dd-c936-49b4-8cf1-4fa8b94d5fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171719994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2171719994
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2908805323
Short name T288
Test name
Test status
Simulation time 3574296384 ps
CPU time 49.57 seconds
Started Apr 23 01:54:37 PM PDT 24
Finished Apr 23 01:55:28 PM PDT 24
Peak memory 215736 kb
Host smart-1277833a-ccb9-4f10-b0b1-bd522bb5a9f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908805323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2908805323
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2602881520
Short name T69
Test name
Test status
Simulation time 103863699 ps
CPU time 3.51 seconds
Started Apr 23 01:56:02 PM PDT 24
Finished Apr 23 01:56:06 PM PDT 24
Peak memory 214636 kb
Host smart-4b0e7e7e-66d4-4611-a565-1250b62b246f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602881520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2602881520
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2798419543
Short name T223
Test name
Test status
Simulation time 159625328 ps
CPU time 8.53 seconds
Started Apr 23 01:57:25 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 215544 kb
Host smart-648a1ac1-d921-40ab-bac2-fec9f980fc41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798419543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2798419543
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.4291518910
Short name T49
Test name
Test status
Simulation time 15363176405 ps
CPU time 95.11 seconds
Started Apr 23 01:56:46 PM PDT 24
Finished Apr 23 01:58:22 PM PDT 24
Peak memory 216652 kb
Host smart-47faeea1-8fec-48ad-a7ab-8e8bd4c9e5e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291518910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.4291518910
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.917100658
Short name T61
Test name
Test status
Simulation time 21052700441 ps
CPU time 46.26 seconds
Started Apr 23 01:55:08 PM PDT 24
Finished Apr 23 01:55:56 PM PDT 24
Peak memory 215920 kb
Host smart-18da1e85-d455-4222-a5f3-d4276fe3941d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917100658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.917100658
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4286615439
Short name T52
Test name
Test status
Simulation time 66861863 ps
CPU time 1.8 seconds
Started Apr 23 01:55:37 PM PDT 24
Finished Apr 23 01:55:41 PM PDT 24
Peak memory 209976 kb
Host smart-361bb4d5-c860-487f-8510-d94ff3e9acc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286615439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4286615439
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1004156879
Short name T293
Test name
Test status
Simulation time 766572397 ps
CPU time 10.74 seconds
Started Apr 23 01:56:57 PM PDT 24
Finished Apr 23 01:57:08 PM PDT 24
Peak memory 215944 kb
Host smart-39b546c6-d2d9-4015-a107-9c8485d938e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004156879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1004156879
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1189781088
Short name T35
Test name
Test status
Simulation time 78904106 ps
CPU time 3.23 seconds
Started Apr 23 01:55:55 PM PDT 24
Finished Apr 23 01:55:59 PM PDT 24
Peak memory 214864 kb
Host smart-9b498b57-1da7-4c72-8aaa-c3f2b08eaeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189781088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1189781088
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1336542601
Short name T24
Test name
Test status
Simulation time 283729337 ps
CPU time 6.38 seconds
Started Apr 23 01:55:10 PM PDT 24
Finished Apr 23 01:55:17 PM PDT 24
Peak memory 214620 kb
Host smart-c7c054a9-8ac5-424b-b360-f85084e9a08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336542601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1336542601
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3008618215
Short name T256
Test name
Test status
Simulation time 107826254 ps
CPU time 6.17 seconds
Started Apr 23 01:56:00 PM PDT 24
Finished Apr 23 01:56:07 PM PDT 24
Peak memory 215516 kb
Host smart-338edbd5-0e58-4f9a-8aa3-03a46365481c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008618215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3008618215
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.4210923935
Short name T421
Test name
Test status
Simulation time 1540591963 ps
CPU time 14.8 seconds
Started Apr 23 01:57:19 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 214476 kb
Host smart-aa6de64a-6d4a-4ad9-875b-df576a7eebed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4210923935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4210923935
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1764613130
Short name T266
Test name
Test status
Simulation time 78061941 ps
CPU time 3.26 seconds
Started Apr 23 01:56:14 PM PDT 24
Finished Apr 23 01:56:18 PM PDT 24
Peak memory 209836 kb
Host smart-a267efb4-73e0-4cf1-bc14-fde51f43fc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764613130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1764613130
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2259614205
Short name T76
Test name
Test status
Simulation time 25332111754 ps
CPU time 328.26 seconds
Started Apr 23 01:56:44 PM PDT 24
Finished Apr 23 02:02:14 PM PDT 24
Peak memory 222820 kb
Host smart-5d180c6e-64d4-4f29-a398-a3c781a56da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259614205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2259614205
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3442616468
Short name T120
Test name
Test status
Simulation time 472234716 ps
CPU time 4.05 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 214500 kb
Host smart-be578f92-9e14-455b-a766-328bc6df7cac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442616468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3442616468
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1631442336
Short name T22
Test name
Test status
Simulation time 25283371609 ps
CPU time 82.39 seconds
Started Apr 23 01:56:44 PM PDT 24
Finished Apr 23 01:58:08 PM PDT 24
Peak memory 209800 kb
Host smart-20372dc5-bef4-4a1b-bdbb-c27a19c667b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631442336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1631442336
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2651226260
Short name T562
Test name
Test status
Simulation time 77593718 ps
CPU time 3.82 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:55:25 PM PDT 24
Peak memory 209524 kb
Host smart-d9720776-6c88-4543-a304-5003dc9daeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651226260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2651226260
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1399320521
Short name T60
Test name
Test status
Simulation time 1063941658 ps
CPU time 15.12 seconds
Started Apr 23 01:57:33 PM PDT 24
Finished Apr 23 01:57:48 PM PDT 24
Peak memory 221280 kb
Host smart-194a23bd-91ad-4ece-acd9-9be475d4d217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399320521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1399320521
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1540286194
Short name T149
Test name
Test status
Simulation time 803049613 ps
CPU time 8.77 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:58 PM PDT 24
Peak memory 214372 kb
Host smart-2e423f8e-78bb-4cbb-af18-a3d6dd395720
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540286194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1540286194
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1080579993
Short name T406
Test name
Test status
Simulation time 5955113117 ps
CPU time 21.16 seconds
Started Apr 23 01:57:11 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 216300 kb
Host smart-9dd57d92-d836-419d-bc76-02dc96798441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080579993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1080579993
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1553725300
Short name T108
Test name
Test status
Simulation time 105529257 ps
CPU time 2.49 seconds
Started Apr 23 01:57:31 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 223032 kb
Host smart-5c81b941-a173-42ae-9ab0-9ef509a3deff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553725300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1553725300
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1885077453
Short name T126
Test name
Test status
Simulation time 563553861 ps
CPU time 22.29 seconds
Started Apr 23 01:55:57 PM PDT 24
Finished Apr 23 01:56:20 PM PDT 24
Peak memory 222944 kb
Host smart-72e5a510-1a56-4a1f-a5e7-55fbcd95d0ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885077453 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1885077453
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1016911621
Short name T216
Test name
Test status
Simulation time 2184385490 ps
CPU time 31.06 seconds
Started Apr 23 01:55:45 PM PDT 24
Finished Apr 23 01:56:16 PM PDT 24
Peak memory 222788 kb
Host smart-daf7b8e9-a22d-4053-a169-ada49b295feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016911621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1016911621
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1445992279
Short name T39
Test name
Test status
Simulation time 97472070 ps
CPU time 3.78 seconds
Started Apr 23 01:56:11 PM PDT 24
Finished Apr 23 01:56:15 PM PDT 24
Peak memory 214176 kb
Host smart-9452c6e2-5197-43d9-b5eb-885a46e33b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445992279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1445992279
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2765555332
Short name T191
Test name
Test status
Simulation time 28927450 ps
CPU time 0.73 seconds
Started Apr 23 01:55:29 PM PDT 24
Finished Apr 23 01:55:30 PM PDT 24
Peak memory 206044 kb
Host smart-dae6feb0-6e57-45b0-bdd8-91e539583a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765555332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2765555332
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3311683105
Short name T137
Test name
Test status
Simulation time 68483002 ps
CPU time 4.52 seconds
Started Apr 23 01:54:40 PM PDT 24
Finished Apr 23 01:54:45 PM PDT 24
Peak memory 214772 kb
Host smart-8b729a86-9402-445b-b786-6620e091af90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311683105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3311683105
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3787203855
Short name T337
Test name
Test status
Simulation time 4442495830 ps
CPU time 87.87 seconds
Started Apr 23 01:56:21 PM PDT 24
Finished Apr 23 01:57:49 PM PDT 24
Peak memory 216500 kb
Host smart-173cfcaa-234c-4583-bcfa-30bb1c3c304a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787203855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3787203855
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1984623264
Short name T422
Test name
Test status
Simulation time 309562310 ps
CPU time 12.49 seconds
Started Apr 23 01:56:24 PM PDT 24
Finished Apr 23 01:56:37 PM PDT 24
Peak memory 222680 kb
Host smart-1e0bdd75-cc24-4cef-b34a-513a5e9b18da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984623264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1984623264
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3973149343
Short name T20
Test name
Test status
Simulation time 383132119 ps
CPU time 4.46 seconds
Started Apr 23 01:54:57 PM PDT 24
Finished Apr 23 01:55:02 PM PDT 24
Peak memory 210284 kb
Host smart-2ee3271a-accd-4203-beb0-f82f96ebaafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973149343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3973149343
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1715401382
Short name T255
Test name
Test status
Simulation time 1222467903 ps
CPU time 5.15 seconds
Started Apr 23 01:56:28 PM PDT 24
Finished Apr 23 01:56:33 PM PDT 24
Peak memory 215656 kb
Host smart-0b3ff806-7239-456e-842e-e844ba643d6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715401382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1715401382
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.621891368
Short name T33
Test name
Test status
Simulation time 100710897 ps
CPU time 3.94 seconds
Started Apr 23 01:56:11 PM PDT 24
Finished Apr 23 01:56:15 PM PDT 24
Peak memory 210260 kb
Host smart-567c9bcb-31c1-4f83-a344-8c2fa0efc596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621891368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.621891368
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1926162015
Short name T62
Test name
Test status
Simulation time 556562504 ps
CPU time 8.74 seconds
Started Apr 23 01:56:24 PM PDT 24
Finished Apr 23 01:56:33 PM PDT 24
Peak memory 218612 kb
Host smart-e63aedb8-c372-46ed-861f-6f9c5ac06cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926162015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1926162015
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3239008544
Short name T262
Test name
Test status
Simulation time 6808910321 ps
CPU time 66.58 seconds
Started Apr 23 01:55:40 PM PDT 24
Finished Apr 23 01:56:47 PM PDT 24
Peak memory 216492 kb
Host smart-9b0b51f5-a9c2-4564-887a-e7368d24ebc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239008544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3239008544
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4043558186
Short name T220
Test name
Test status
Simulation time 3164072681 ps
CPU time 107.41 seconds
Started Apr 23 01:56:57 PM PDT 24
Finished Apr 23 01:58:45 PM PDT 24
Peak memory 216544 kb
Host smart-eece7d8a-b4b3-49a0-9aeb-23da47f9aaa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043558186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4043558186
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1374343560
Short name T267
Test name
Test status
Simulation time 15895520527 ps
CPU time 40.35 seconds
Started Apr 23 01:57:07 PM PDT 24
Finished Apr 23 01:57:48 PM PDT 24
Peak memory 222680 kb
Host smart-5ab9da87-5a4d-4864-a196-75cadaaed458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374343560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1374343560
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1748505122
Short name T244
Test name
Test status
Simulation time 126579040 ps
CPU time 4.38 seconds
Started Apr 23 01:57:15 PM PDT 24
Finished Apr 23 01:57:20 PM PDT 24
Peak memory 214520 kb
Host smart-1bd9302d-614c-4d0c-aeea-a3240ae839b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748505122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1748505122
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2914756930
Short name T310
Test name
Test status
Simulation time 2035322501 ps
CPU time 6.16 seconds
Started Apr 23 01:55:08 PM PDT 24
Finished Apr 23 01:55:15 PM PDT 24
Peak memory 210416 kb
Host smart-c2f2d3e9-4489-4c9d-872a-253e36b15b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914756930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2914756930
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2027346720
Short name T152
Test name
Test status
Simulation time 118513791 ps
CPU time 6.36 seconds
Started Apr 23 01:51:34 PM PDT 24
Finished Apr 23 01:51:41 PM PDT 24
Peak memory 209536 kb
Host smart-5fb57484-458c-4548-ac30-f7df56d07102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027346720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2027346720
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.339930350
Short name T154
Test name
Test status
Simulation time 908204633 ps
CPU time 8.85 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:51:58 PM PDT 24
Peak memory 209212 kb
Host smart-56b1dbb8-d690-4b97-9991-f25bebe582f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339930350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.339930350
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1848832478
Short name T383
Test name
Test status
Simulation time 462145127 ps
CPU time 3.37 seconds
Started Apr 23 01:55:49 PM PDT 24
Finished Apr 23 01:55:52 PM PDT 24
Peak memory 210528 kb
Host smart-cdaf086f-14eb-4b3d-b333-c6bc1535713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848832478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1848832478
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2422523872
Short name T253
Test name
Test status
Simulation time 111188450 ps
CPU time 4.22 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 210420 kb
Host smart-fdfcd546-80c9-4153-903a-794a8fa2598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422523872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2422523872
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3736240552
Short name T215
Test name
Test status
Simulation time 6859729264 ps
CPU time 66.67 seconds
Started Apr 23 01:56:04 PM PDT 24
Finished Apr 23 01:57:11 PM PDT 24
Peak memory 222800 kb
Host smart-1e2e05dc-d530-4965-9408-62b69506b2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736240552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3736240552
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.4070239350
Short name T158
Test name
Test status
Simulation time 141777092 ps
CPU time 4.64 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 209276 kb
Host smart-5204641e-15e7-408d-86ac-3d5fc89e057f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070239350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.4070239350
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4181700274
Short name T107
Test name
Test status
Simulation time 267117734 ps
CPU time 4 seconds
Started Apr 23 01:56:41 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 223040 kb
Host smart-c32b2034-772f-4ca1-bcf3-a10e79d74273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181700274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4181700274
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2586384740
Short name T358
Test name
Test status
Simulation time 2668995538 ps
CPU time 38.16 seconds
Started Apr 23 01:55:27 PM PDT 24
Finished Apr 23 01:56:06 PM PDT 24
Peak memory 222928 kb
Host smart-c2b858ee-8dfb-4b68-8d4b-5b1d100945c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586384740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2586384740
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.767603580
Short name T234
Test name
Test status
Simulation time 149778880 ps
CPU time 5.57 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:05 PM PDT 24
Peak memory 211296 kb
Host smart-622a5b46-efd3-444d-a57e-f647d41f39a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767603580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.767603580
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3329066427
Short name T378
Test name
Test status
Simulation time 2704627686 ps
CPU time 35.81 seconds
Started Apr 23 01:55:58 PM PDT 24
Finished Apr 23 01:56:35 PM PDT 24
Peak memory 222268 kb
Host smart-2185159e-eb0f-4a15-8bc7-4e1cc73cb55f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329066427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3329066427
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.68185789
Short name T77
Test name
Test status
Simulation time 15819175842 ps
CPU time 44.8 seconds
Started Apr 23 01:56:25 PM PDT 24
Finished Apr 23 01:57:10 PM PDT 24
Peak memory 216988 kb
Host smart-dcac9e23-fe16-47d3-8230-8af7a27887a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68185789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.68185789
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2050272564
Short name T347
Test name
Test status
Simulation time 902123759 ps
CPU time 18.31 seconds
Started Apr 23 01:57:39 PM PDT 24
Finished Apr 23 01:57:58 PM PDT 24
Peak memory 222668 kb
Host smart-37682f00-337f-4a3d-94aa-0c0023bc2c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050272564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2050272564
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2706543903
Short name T169
Test name
Test status
Simulation time 531976729 ps
CPU time 3.84 seconds
Started Apr 23 01:55:04 PM PDT 24
Finished Apr 23 01:55:08 PM PDT 24
Peak memory 207400 kb
Host smart-0f7531d2-7bab-44c6-b45f-84942ce033b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706543903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2706543903
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.458090147
Short name T160
Test name
Test status
Simulation time 206054814 ps
CPU time 3.16 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 214264 kb
Host smart-fd572101-8ff7-44e7-8a36-13c765eb1c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458090147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.458090147
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.136103531
Short name T109
Test name
Test status
Simulation time 192939020 ps
CPU time 4.61 seconds
Started Apr 23 01:55:36 PM PDT 24
Finished Apr 23 01:55:44 PM PDT 24
Peak memory 218388 kb
Host smart-1b34cbe3-48e6-4e15-b2af-87f41b8a54e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136103531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.136103531
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3965221284
Short name T88
Test name
Test status
Simulation time 99911927 ps
CPU time 4.6 seconds
Started Apr 23 01:54:39 PM PDT 24
Finished Apr 23 01:54:44 PM PDT 24
Peak memory 208544 kb
Host smart-9ed64ac7-f246-41e3-b2a4-245b691b75b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965221284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3965221284
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1942858383
Short name T340
Test name
Test status
Simulation time 3065350016 ps
CPU time 14.36 seconds
Started Apr 23 01:54:42 PM PDT 24
Finished Apr 23 01:54:57 PM PDT 24
Peak memory 214616 kb
Host smart-e0617509-e6dc-463e-9c85-3df67f8756b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942858383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1942858383
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1953471954
Short name T323
Test name
Test status
Simulation time 85382174 ps
CPU time 3.47 seconds
Started Apr 23 01:55:27 PM PDT 24
Finished Apr 23 01:55:30 PM PDT 24
Peak memory 208848 kb
Host smart-a8a4fbd7-997b-494b-8714-8908d893d681
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953471954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1953471954
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_random.3921150443
Short name T202
Test name
Test status
Simulation time 205178926 ps
CPU time 3.42 seconds
Started Apr 23 01:56:06 PM PDT 24
Finished Apr 23 01:56:10 PM PDT 24
Peak memory 207628 kb
Host smart-25ce20b9-5883-4914-be57-892f2fb27f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921150443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3921150443
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3763593160
Short name T241
Test name
Test status
Simulation time 460478714 ps
CPU time 11.8 seconds
Started Apr 23 01:56:16 PM PDT 24
Finished Apr 23 01:56:28 PM PDT 24
Peak memory 214432 kb
Host smart-fbbf93d3-db6c-47fd-96a4-bde7df9e793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763593160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3763593160
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3816484059
Short name T417
Test name
Test status
Simulation time 52347554 ps
CPU time 3.62 seconds
Started Apr 23 01:56:50 PM PDT 24
Finished Apr 23 01:56:54 PM PDT 24
Peak memory 215028 kb
Host smart-294eff65-8f10-4afa-bf4d-8cf3ce3e3f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816484059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3816484059
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2913584961
Short name T876
Test name
Test status
Simulation time 186145661 ps
CPU time 6.54 seconds
Started Apr 23 01:54:59 PM PDT 24
Finished Apr 23 01:55:06 PM PDT 24
Peak memory 214488 kb
Host smart-7cad6b8c-8738-4892-b0dc-9390e0fc83bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913584961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2913584961
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.383835065
Short name T161
Test name
Test status
Simulation time 110798168 ps
CPU time 3.56 seconds
Started Apr 23 01:51:35 PM PDT 24
Finished Apr 23 01:51:39 PM PDT 24
Peak memory 209848 kb
Host smart-8a7d6a31-4a20-4878-afea-e1fc183a92e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383835065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
383835065
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3714766103
Short name T162
Test name
Test status
Simulation time 100395252 ps
CPU time 3.3 seconds
Started Apr 23 01:51:52 PM PDT 24
Finished Apr 23 01:51:57 PM PDT 24
Peak memory 214296 kb
Host smart-809fcc8b-e8b9-49f0-ba83-e95ef377977b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714766103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3714766103
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.276738528
Short name T146
Test name
Test status
Simulation time 1430241479 ps
CPU time 13.93 seconds
Started Apr 23 01:51:58 PM PDT 24
Finished Apr 23 01:52:13 PM PDT 24
Peak memory 209808 kb
Host smart-d413166a-b3c1-4508-82c8-7a6b206baa86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276738528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.276738528
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3451598267
Short name T147
Test name
Test status
Simulation time 76413131 ps
CPU time 1.95 seconds
Started Apr 23 01:56:00 PM PDT 24
Finished Apr 23 01:56:03 PM PDT 24
Peak memory 210044 kb
Host smart-04e3cd5d-47be-44a4-90e1-ebbb01fa5665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451598267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3451598267
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.692241723
Short name T159
Test name
Test status
Simulation time 168274906 ps
CPU time 3.62 seconds
Started Apr 23 01:57:23 PM PDT 24
Finished Apr 23 01:57:28 PM PDT 24
Peak memory 210540 kb
Host smart-2c0428d6-88d8-4164-b4cb-ff5052643f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692241723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.692241723
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2713165356
Short name T110
Test name
Test status
Simulation time 147039595 ps
CPU time 3.48 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 217732 kb
Host smart-786f6f86-8ff9-4745-9100-013a5ce6e795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713165356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2713165356
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_random.769730474
Short name T774
Test name
Test status
Simulation time 354980193 ps
CPU time 3.54 seconds
Started Apr 23 01:54:36 PM PDT 24
Finished Apr 23 01:54:40 PM PDT 24
Peak memory 214524 kb
Host smart-01852943-8a28-4e1d-9fe2-e82f49614502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769730474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.769730474
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1332402658
Short name T127
Test name
Test status
Simulation time 49330681 ps
CPU time 2.74 seconds
Started Apr 23 01:54:36 PM PDT 24
Finished Apr 23 01:54:39 PM PDT 24
Peak memory 207656 kb
Host smart-b438daa0-3cf6-4fcd-99db-4a458c5c3c8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332402658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1332402658
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2642875636
Short name T350
Test name
Test status
Simulation time 83208719 ps
CPU time 2.54 seconds
Started Apr 23 01:54:42 PM PDT 24
Finished Apr 23 01:54:45 PM PDT 24
Peak memory 222776 kb
Host smart-68e0b7c5-0c01-48f2-ade1-ee41a93ca5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642875636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2642875636
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2135470584
Short name T390
Test name
Test status
Simulation time 176796230 ps
CPU time 3.6 seconds
Started Apr 23 01:54:44 PM PDT 24
Finished Apr 23 01:54:48 PM PDT 24
Peak memory 209996 kb
Host smart-e6c30cae-de57-4b5a-820b-27ca7efbabe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135470584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2135470584
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3130189090
Short name T409
Test name
Test status
Simulation time 70429684 ps
CPU time 4.38 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:55:25 PM PDT 24
Peak memory 214572 kb
Host smart-05b67fb6-3572-4b2a-ba86-4d957b517d77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130189090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3130189090
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2761206330
Short name T43
Test name
Test status
Simulation time 909223881 ps
CPU time 2.74 seconds
Started Apr 23 01:55:28 PM PDT 24
Finished Apr 23 01:55:31 PM PDT 24
Peak memory 218908 kb
Host smart-3d44081b-e35b-46fd-bcb3-6b5b68bd8a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761206330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2761206330
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3895735773
Short name T55
Test name
Test status
Simulation time 73964990 ps
CPU time 2.66 seconds
Started Apr 23 01:55:33 PM PDT 24
Finished Apr 23 01:55:37 PM PDT 24
Peak memory 208676 kb
Host smart-acbc0e73-eeb2-4230-9193-2452d84ae5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895735773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3895735773
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1063214867
Short name T354
Test name
Test status
Simulation time 364728745 ps
CPU time 14.55 seconds
Started Apr 23 01:55:36 PM PDT 24
Finished Apr 23 01:55:54 PM PDT 24
Peak memory 222880 kb
Host smart-4868d90d-26df-411b-89bd-e07c10da3778
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063214867 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1063214867
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3927487984
Short name T250
Test name
Test status
Simulation time 1615681462 ps
CPU time 23.93 seconds
Started Apr 23 01:55:48 PM PDT 24
Finished Apr 23 01:56:12 PM PDT 24
Peak memory 214532 kb
Host smart-1b2099cc-94c6-4833-b3ab-651fbb27f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927487984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3927487984
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1333212214
Short name T138
Test name
Test status
Simulation time 2046980755 ps
CPU time 13.96 seconds
Started Apr 23 01:55:44 PM PDT 24
Finished Apr 23 01:55:59 PM PDT 24
Peak memory 210016 kb
Host smart-595906a9-b274-440a-a27b-f5137cff5258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333212214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1333212214
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1025750809
Short name T485
Test name
Test status
Simulation time 173750723 ps
CPU time 2.24 seconds
Started Apr 23 01:55:57 PM PDT 24
Finished Apr 23 01:56:00 PM PDT 24
Peak memory 210328 kb
Host smart-d638029e-5d5a-47d9-a95f-729f853d92bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025750809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1025750809
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.245873580
Short name T136
Test name
Test status
Simulation time 177587936 ps
CPU time 3.85 seconds
Started Apr 23 01:54:46 PM PDT 24
Finished Apr 23 01:54:50 PM PDT 24
Peak memory 214624 kb
Host smart-f443f6c9-bf2e-4dd4-957f-0c2edacf4a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245873580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.245873580
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2651828789
Short name T204
Test name
Test status
Simulation time 131630213 ps
CPU time 5.8 seconds
Started Apr 23 01:56:03 PM PDT 24
Finished Apr 23 01:56:09 PM PDT 24
Peak memory 210528 kb
Host smart-674cf373-ebb6-4aa2-8600-d6d1a2218d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651828789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2651828789
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3779754240
Short name T106
Test name
Test status
Simulation time 345333858 ps
CPU time 4.45 seconds
Started Apr 23 01:56:31 PM PDT 24
Finished Apr 23 01:56:36 PM PDT 24
Peak memory 222564 kb
Host smart-f4a03738-a617-4668-89be-c72185ba03b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779754240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3779754240
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1307271823
Short name T209
Test name
Test status
Simulation time 183331337 ps
CPU time 3.67 seconds
Started Apr 23 01:56:30 PM PDT 24
Finished Apr 23 01:56:34 PM PDT 24
Peak memory 214564 kb
Host smart-a7b7b810-9918-41af-acf4-e72927645346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307271823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1307271823
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1669870993
Short name T352
Test name
Test status
Simulation time 324399658 ps
CPU time 4.75 seconds
Started Apr 23 01:56:27 PM PDT 24
Finished Apr 23 01:56:32 PM PDT 24
Peak memory 207260 kb
Host smart-aa1554ec-ecf5-4bca-bdfc-622934dfeace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669870993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1669870993
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.728339318
Short name T295
Test name
Test status
Simulation time 104784664 ps
CPU time 3.83 seconds
Started Apr 23 01:56:34 PM PDT 24
Finished Apr 23 01:56:39 PM PDT 24
Peak memory 210108 kb
Host smart-3367a2df-5149-4bb7-856a-3be838d81807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728339318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.728339318
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_sideload.270110591
Short name T306
Test name
Test status
Simulation time 45808607 ps
CPU time 2.55 seconds
Started Apr 23 01:56:51 PM PDT 24
Finished Apr 23 01:56:54 PM PDT 24
Peak memory 208760 kb
Host smart-727b7cb1-21d4-47f3-a929-dd80bc6fc686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270110591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.270110591
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.270166884
Short name T339
Test name
Test status
Simulation time 1060467267 ps
CPU time 32.92 seconds
Started Apr 23 01:54:58 PM PDT 24
Finished Apr 23 01:55:31 PM PDT 24
Peak memory 212828 kb
Host smart-c99877cb-2885-4729-8a96-f5d952d650b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270166884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.270166884
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3401351975
Short name T366
Test name
Test status
Simulation time 308315519 ps
CPU time 10.02 seconds
Started Apr 23 01:57:30 PM PDT 24
Finished Apr 23 01:57:41 PM PDT 24
Peak memory 222788 kb
Host smart-64fb1307-9f38-4859-ad32-21f4be7fca46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401351975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3401351975
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2434242322
Short name T63
Test name
Test status
Simulation time 166743845 ps
CPU time 4.17 seconds
Started Apr 23 01:57:36 PM PDT 24
Finished Apr 23 01:57:41 PM PDT 24
Peak memory 209256 kb
Host smart-a97af55d-1e5d-46c4-aa6d-7a4000f505b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434242322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2434242322
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1617955242
Short name T1038
Test name
Test status
Simulation time 380827622 ps
CPU time 5.37 seconds
Started Apr 23 01:51:34 PM PDT 24
Finished Apr 23 01:51:40 PM PDT 24
Peak memory 206036 kb
Host smart-96921d65-76d1-42f9-9131-4b88ebc92aba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617955242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
617955242
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3232044790
Short name T1001
Test name
Test status
Simulation time 2077100128 ps
CPU time 12.05 seconds
Started Apr 23 01:51:31 PM PDT 24
Finished Apr 23 01:51:43 PM PDT 24
Peak memory 206100 kb
Host smart-826eb2f8-ce0a-4617-b803-0626ed83dc03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232044790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
232044790
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.222885357
Short name T975
Test name
Test status
Simulation time 97935070 ps
CPU time 1.34 seconds
Started Apr 23 01:51:33 PM PDT 24
Finished Apr 23 01:51:36 PM PDT 24
Peak memory 206024 kb
Host smart-a6b1767c-4035-4b53-9d45-2abc128797d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222885357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.222885357
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1388438096
Short name T981
Test name
Test status
Simulation time 166243957 ps
CPU time 1.62 seconds
Started Apr 23 01:51:44 PM PDT 24
Finished Apr 23 01:51:48 PM PDT 24
Peak memory 214276 kb
Host smart-70ce2ce2-d5dd-4153-8ef9-f3e048e75b1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388438096 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1388438096
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.721419103
Short name T973
Test name
Test status
Simulation time 9543092 ps
CPU time 0.87 seconds
Started Apr 23 01:51:42 PM PDT 24
Finished Apr 23 01:51:45 PM PDT 24
Peak memory 205912 kb
Host smart-6d1d0f0b-527a-468a-9d42-748dcaf2e310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721419103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.721419103
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2850952107
Short name T927
Test name
Test status
Simulation time 11647350 ps
CPU time 0.7 seconds
Started Apr 23 01:51:26 PM PDT 24
Finished Apr 23 01:51:28 PM PDT 24
Peak memory 205684 kb
Host smart-44d3ab88-5ce7-412f-9dbd-0b722940ca2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850952107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2850952107
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3825183207
Short name T1043
Test name
Test status
Simulation time 206526023 ps
CPU time 1.96 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:43 PM PDT 24
Peak memory 206100 kb
Host smart-eb4b0707-0f8e-4c93-996a-c29cd8efd40d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825183207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3825183207
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4021444809
Short name T1009
Test name
Test status
Simulation time 225741733 ps
CPU time 2.27 seconds
Started Apr 23 01:51:37 PM PDT 24
Finished Apr 23 01:51:40 PM PDT 24
Peak memory 214596 kb
Host smart-d262c167-4386-4fab-b02c-65f67f7de369
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021444809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.4021444809
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1278879859
Short name T974
Test name
Test status
Simulation time 491454077 ps
CPU time 9.64 seconds
Started Apr 23 01:51:23 PM PDT 24
Finished Apr 23 01:51:33 PM PDT 24
Peak memory 214524 kb
Host smart-23f5010a-70c5-4117-aa7a-f7aefe3c9c83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278879859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1278879859
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.601766174
Short name T978
Test name
Test status
Simulation time 232513988 ps
CPU time 3.73 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:45 PM PDT 24
Peak memory 217008 kb
Host smart-3587c141-3f00-44d5-adcd-d1fd505da6dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601766174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.601766174
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2057647846
Short name T940
Test name
Test status
Simulation time 139388595 ps
CPU time 4.89 seconds
Started Apr 23 01:51:41 PM PDT 24
Finished Apr 23 01:51:48 PM PDT 24
Peak memory 206008 kb
Host smart-752a6f69-f3c1-43dd-b75c-39a36287ed37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057647846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
057647846
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.148663605
Short name T1035
Test name
Test status
Simulation time 1660037655 ps
CPU time 7.96 seconds
Started Apr 23 01:51:41 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 205996 kb
Host smart-c55c4839-1b52-454c-acb3-ece16f266e3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148663605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.148663605
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2523232519
Short name T1033
Test name
Test status
Simulation time 94234592 ps
CPU time 1.17 seconds
Started Apr 23 01:51:41 PM PDT 24
Finished Apr 23 01:51:44 PM PDT 24
Peak memory 206176 kb
Host smart-482213aa-5dd3-4374-957e-214d8b63a64a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523232519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
523232519
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3588216129
Short name T941
Test name
Test status
Simulation time 29874712 ps
CPU time 2.28 seconds
Started Apr 23 01:51:31 PM PDT 24
Finished Apr 23 01:51:34 PM PDT 24
Peak memory 214424 kb
Host smart-5fc46640-3f51-42ee-b0ac-b5ad93c35136
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588216129 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3588216129
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2109970546
Short name T1034
Test name
Test status
Simulation time 402448884 ps
CPU time 1.31 seconds
Started Apr 23 01:51:36 PM PDT 24
Finished Apr 23 01:51:38 PM PDT 24
Peak memory 205964 kb
Host smart-f5d5b4ed-e290-4165-b933-9b5df2cfdbf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109970546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2109970546
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4108687595
Short name T1005
Test name
Test status
Simulation time 64930921 ps
CPU time 0.72 seconds
Started Apr 23 01:51:28 PM PDT 24
Finished Apr 23 01:51:29 PM PDT 24
Peak memory 205736 kb
Host smart-e8d87ed7-ecb7-462c-b98b-55f399195007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108687595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4108687595
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2038053928
Short name T1052
Test name
Test status
Simulation time 69083173 ps
CPU time 2.21 seconds
Started Apr 23 01:51:40 PM PDT 24
Finished Apr 23 01:51:44 PM PDT 24
Peak memory 206092 kb
Host smart-c9723e79-dcdb-4e45-972e-4c5d6c922647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038053928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2038053928
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.188912496
Short name T953
Test name
Test status
Simulation time 149945166 ps
CPU time 3.88 seconds
Started Apr 23 01:51:44 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 214508 kb
Host smart-efcd3320-3f5f-4963-9ab6-bc46375f4608
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188912496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.188912496
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3711372369
Short name T1062
Test name
Test status
Simulation time 108746359 ps
CPU time 4.61 seconds
Started Apr 23 01:51:36 PM PDT 24
Finished Apr 23 01:51:41 PM PDT 24
Peak memory 214580 kb
Host smart-ba12a726-c893-4e35-9397-25cb4bebfe2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711372369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3711372369
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.765273581
Short name T909
Test name
Test status
Simulation time 88590943 ps
CPU time 3.01 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:51:52 PM PDT 24
Peak memory 217688 kb
Host smart-e7cc7e5f-5334-4616-9c2c-ca8a4b602772
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765273581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.765273581
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.29373920
Short name T960
Test name
Test status
Simulation time 27361223 ps
CPU time 1.46 seconds
Started Apr 23 01:51:42 PM PDT 24
Finished Apr 23 01:51:45 PM PDT 24
Peak memory 214340 kb
Host smart-b6e5a3d1-b8fe-4666-9472-0d555021a22c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29373920 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.29373920
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4280128088
Short name T1059
Test name
Test status
Simulation time 15336723 ps
CPU time 1.11 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:49 PM PDT 24
Peak memory 205908 kb
Host smart-17180370-830b-44a8-bdd5-116d2b295e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280128088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4280128088
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1676651560
Short name T920
Test name
Test status
Simulation time 25198266 ps
CPU time 0.82 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 205768 kb
Host smart-5bc11ef8-bca3-4b36-b6f6-11ca5fc24825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676651560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1676651560
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2149610749
Short name T1021
Test name
Test status
Simulation time 130883718 ps
CPU time 2.57 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:43 PM PDT 24
Peak memory 206028 kb
Host smart-51c2464c-d253-4164-9df2-55e9397d7369
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149610749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2149610749
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3301300708
Short name T922
Test name
Test status
Simulation time 142429879 ps
CPU time 4.25 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 214492 kb
Host smart-4f3281fd-7f48-4c22-b946-614f034d9d3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301300708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3301300708
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.705201109
Short name T112
Test name
Test status
Simulation time 78228840 ps
CPU time 3.65 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 214520 kb
Host smart-d2be3e0b-cdb2-4479-a3be-9d547b435dc4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705201109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.705201109
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3651450809
Short name T1014
Test name
Test status
Simulation time 104178715 ps
CPU time 2.88 seconds
Started Apr 23 01:51:40 PM PDT 24
Finished Apr 23 01:51:45 PM PDT 24
Peak memory 214240 kb
Host smart-437a561e-11eb-47fb-9938-ce4326f7a92e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651450809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3651450809
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.370961024
Short name T1054
Test name
Test status
Simulation time 107896382 ps
CPU time 3.2 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 209800 kb
Host smart-19db0e4c-9c3e-43e6-ba2b-2a09c405bfc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370961024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.370961024
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.137785957
Short name T929
Test name
Test status
Simulation time 125652196 ps
CPU time 1.55 seconds
Started Apr 23 01:51:37 PM PDT 24
Finished Apr 23 01:51:39 PM PDT 24
Peak memory 214336 kb
Host smart-10d865c9-eeae-4a5c-a434-c00c7ab172ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137785957 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.137785957
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2534656217
Short name T1017
Test name
Test status
Simulation time 34763934 ps
CPU time 0.9 seconds
Started Apr 23 01:52:01 PM PDT 24
Finished Apr 23 01:52:03 PM PDT 24
Peak memory 205848 kb
Host smart-c348dc68-4fc5-4803-a5a7-7f67b4fc7eec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534656217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2534656217
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4171103992
Short name T1073
Test name
Test status
Simulation time 41907778 ps
CPU time 0.85 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 205788 kb
Host smart-3b04b334-7ea6-4a0d-aa9b-6f2c4cc21a41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171103992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.4171103992
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.661834823
Short name T144
Test name
Test status
Simulation time 68041075 ps
CPU time 1.27 seconds
Started Apr 23 01:51:54 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 206144 kb
Host smart-593aaf53-0210-4d92-8e78-9649aefd5208
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661834823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.661834823
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2453386414
Short name T1047
Test name
Test status
Simulation time 435134007 ps
CPU time 4.68 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 219316 kb
Host smart-44158fa3-2b82-40f3-b751-3f78dbb08db7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453386414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2453386414
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3231251504
Short name T926
Test name
Test status
Simulation time 388407413 ps
CPU time 7.36 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 214536 kb
Host smart-05d0e581-8bef-47ab-abdc-f1de6d2150b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231251504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3231251504
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1192003787
Short name T902
Test name
Test status
Simulation time 21986265 ps
CPU time 1.73 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:48 PM PDT 24
Peak memory 214440 kb
Host smart-66a01371-21b2-4719-aa31-e677b919b89c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192003787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1192003787
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1766312907
Short name T1068
Test name
Test status
Simulation time 30077446 ps
CPU time 1.38 seconds
Started Apr 23 01:51:53 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 206136 kb
Host smart-1b495a3c-acf2-4e9d-a248-ea6db2e2b365
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766312907 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1766312907
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.503885235
Short name T1042
Test name
Test status
Simulation time 15476404 ps
CPU time 1.14 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:48 PM PDT 24
Peak memory 205964 kb
Host smart-fd85db1d-b7d3-4a4d-a052-580dbc64c345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503885235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.503885235
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2696877858
Short name T1040
Test name
Test status
Simulation time 38718464 ps
CPU time 0.87 seconds
Started Apr 23 01:51:54 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 205772 kb
Host smart-3307c6d0-0f5f-450d-8faf-1f48bbaddae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696877858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2696877858
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3060086333
Short name T1022
Test name
Test status
Simulation time 19811768 ps
CPU time 1.54 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 206044 kb
Host smart-75f72de3-f7c8-417a-acf0-49ec6532ceaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060086333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3060086333
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3149293443
Short name T1067
Test name
Test status
Simulation time 3893597688 ps
CPU time 11.24 seconds
Started Apr 23 01:51:42 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 214588 kb
Host smart-73ff934a-9ccd-4dc8-bd91-4f2f7fa23b43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149293443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3149293443
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2570485889
Short name T113
Test name
Test status
Simulation time 914093649 ps
CPU time 4.91 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 214616 kb
Host smart-da096968-b487-4fe5-8738-1b1bceccbbe7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570485889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2570485889
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.225530285
Short name T913
Test name
Test status
Simulation time 35610303 ps
CPU time 2.33 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 214236 kb
Host smart-1b9b11a5-70af-4cf4-9063-ef2478b655a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225530285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.225530285
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.485400159
Short name T943
Test name
Test status
Simulation time 52510991 ps
CPU time 1.76 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 214316 kb
Host smart-75484886-7933-4e30-8d65-43518ca1ec67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485400159 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.485400159
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2321748346
Short name T950
Test name
Test status
Simulation time 24693475 ps
CPU time 1.1 seconds
Started Apr 23 01:51:44 PM PDT 24
Finished Apr 23 01:51:47 PM PDT 24
Peak memory 205984 kb
Host smart-e24b819a-ef2a-4a4b-b618-beb78aed8dff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321748346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2321748346
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3615681493
Short name T962
Test name
Test status
Simulation time 23437676 ps
CPU time 0.71 seconds
Started Apr 23 01:51:53 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 205860 kb
Host smart-9bef208b-da3f-440e-8245-e3fabbf060fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615681493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3615681493
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3255905155
Short name T141
Test name
Test status
Simulation time 51784903 ps
CPU time 2.4 seconds
Started Apr 23 01:51:43 PM PDT 24
Finished Apr 23 01:51:47 PM PDT 24
Peak memory 206216 kb
Host smart-31df5015-447a-43a9-887b-2365b092bc6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255905155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3255905155
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2314848875
Short name T1050
Test name
Test status
Simulation time 153858359 ps
CPU time 4.62 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 214524 kb
Host smart-50948b43-07a6-407b-916c-67df209661d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314848875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2314848875
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2983141303
Short name T935
Test name
Test status
Simulation time 360686196 ps
CPU time 4.69 seconds
Started Apr 23 01:51:40 PM PDT 24
Finished Apr 23 01:51:46 PM PDT 24
Peak memory 214524 kb
Host smart-c3c6962d-6147-4891-946a-9998d89bae7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983141303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2983141303
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3921986625
Short name T989
Test name
Test status
Simulation time 64297767 ps
CPU time 2.73 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 216468 kb
Host smart-78f9686d-59f6-48f7-abb1-805e3af2d5dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921986625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3921986625
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2038621878
Short name T387
Test name
Test status
Simulation time 5861904470 ps
CPU time 36.1 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:52:28 PM PDT 24
Peak memory 213044 kb
Host smart-5067c6cb-872e-4307-ac01-78786e8c29ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038621878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2038621878
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3651673995
Short name T1002
Test name
Test status
Simulation time 42278690 ps
CPU time 2.11 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:49 PM PDT 24
Peak memory 214336 kb
Host smart-c61afde3-8654-480e-a4bb-91b31c6e825d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651673995 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3651673995
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2775145068
Short name T1018
Test name
Test status
Simulation time 16844664 ps
CPU time 1.38 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 206012 kb
Host smart-877628ee-2c4a-41d9-933c-cdd1fc5036a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775145068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2775145068
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3255859626
Short name T936
Test name
Test status
Simulation time 9920381 ps
CPU time 0.73 seconds
Started Apr 23 01:51:43 PM PDT 24
Finished Apr 23 01:51:46 PM PDT 24
Peak memory 205776 kb
Host smart-f082e8bb-207d-443e-8d07-ca5f001c0745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255859626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3255859626
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1322954495
Short name T934
Test name
Test status
Simulation time 39304988 ps
CPU time 2.01 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 206100 kb
Host smart-11012a12-0d63-476a-a73e-84e636aaa254
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322954495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1322954495
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.659042
Short name T114
Test name
Test status
Simulation time 226275796 ps
CPU time 5.43 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:05 PM PDT 24
Peak memory 214596 kb
Host smart-b1bb63fb-ddf6-45dc-94dc-2a56c785b229
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_r
eg_errors.659042
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3549361651
Short name T1019
Test name
Test status
Simulation time 673185979 ps
CPU time 9.25 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 214656 kb
Host smart-fe1e7e4f-8900-4a6b-a249-c22d223ebeec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549361651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3549361651
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1582323163
Short name T1029
Test name
Test status
Simulation time 95080966 ps
CPU time 2.3 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 214344 kb
Host smart-654e6f7c-d6ec-4510-b396-6b3fbd125e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582323163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1582323163
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1341269016
Short name T155
Test name
Test status
Simulation time 675365929 ps
CPU time 9.58 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 214224 kb
Host smart-63653873-a2e8-443c-b93e-18e1689a31bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341269016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1341269016
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1756523434
Short name T1031
Test name
Test status
Simulation time 98871258 ps
CPU time 1.69 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 206156 kb
Host smart-e43474cf-1588-4205-a2d3-70d44c29d80d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756523434 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1756523434
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3503989625
Short name T963
Test name
Test status
Simulation time 65430524 ps
CPU time 1.31 seconds
Started Apr 23 01:51:54 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 206016 kb
Host smart-9044c19f-7047-4e9e-8397-6124dd250b2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503989625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3503989625
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1032014465
Short name T907
Test name
Test status
Simulation time 15152183 ps
CPU time 0.91 seconds
Started Apr 23 01:51:52 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 205940 kb
Host smart-0d1108be-e147-417a-b7a9-e8e68679c79b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032014465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1032014465
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.597395144
Short name T939
Test name
Test status
Simulation time 126881899 ps
CPU time 2.43 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 206144 kb
Host smart-fbc582da-11f8-48b6-9b71-64188a59b32c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597395144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.597395144
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4134901714
Short name T1015
Test name
Test status
Simulation time 332577571 ps
CPU time 3.02 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 214480 kb
Host smart-8e7a2a0d-b4e2-4fbf-8be5-54a0ab9470f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134901714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4134901714
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4261347646
Short name T1064
Test name
Test status
Simulation time 411525490 ps
CPU time 13.86 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:52:03 PM PDT 24
Peak memory 214508 kb
Host smart-a7882073-24a6-4e2a-b865-00ca6e2ccd4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261347646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4261347646
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2363107793
Short name T903
Test name
Test status
Simulation time 222783200 ps
CPU time 3.4 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 214424 kb
Host smart-8915d853-a9fd-4cbd-bb81-5b09970418b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363107793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2363107793
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1360402263
Short name T1037
Test name
Test status
Simulation time 121122641 ps
CPU time 3.52 seconds
Started Apr 23 01:51:52 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 209716 kb
Host smart-c2236866-3263-4012-a55b-8e50207fef6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360402263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1360402263
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.4144820793
Short name T966
Test name
Test status
Simulation time 74121783 ps
CPU time 1.39 seconds
Started Apr 23 01:51:53 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 214368 kb
Host smart-c9bbd81b-66c9-424b-9b44-9329b6024c6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144820793 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.4144820793
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.90746902
Short name T142
Test name
Test status
Simulation time 74373142 ps
CPU time 1.29 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 206080 kb
Host smart-bfb464f9-9a90-4053-a51f-77bf40f14a17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90746902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.90746902
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1957416291
Short name T1006
Test name
Test status
Simulation time 9773117 ps
CPU time 0.77 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 205716 kb
Host smart-b84b6663-e762-429d-8f03-75e7f34cfb23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957416291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1957416291
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2508322971
Short name T143
Test name
Test status
Simulation time 60479105 ps
CPU time 1.77 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 206000 kb
Host smart-92f22616-3cb2-4e97-a91b-e24cd7d413d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508322971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2508322971
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3159330527
Short name T961
Test name
Test status
Simulation time 1494334436 ps
CPU time 13.5 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:52:04 PM PDT 24
Peak memory 222376 kb
Host smart-740d29d3-a82f-4f27-9541-01118103231d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159330527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3159330527
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1302733864
Short name T951
Test name
Test status
Simulation time 44957332 ps
CPU time 2.82 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 216600 kb
Host smart-b6cbf52a-b913-4a2d-b1cc-4324d83c7075
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302733864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1302733864
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.880594083
Short name T1030
Test name
Test status
Simulation time 722833685 ps
CPU time 1.95 seconds
Started Apr 23 01:51:58 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 214372 kb
Host smart-48568a6d-26af-4056-baa6-693df0b286d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880594083 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.880594083
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4110456349
Short name T1039
Test name
Test status
Simulation time 541741323 ps
CPU time 1.89 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 205948 kb
Host smart-98bed4f4-29ab-43bc-b0d8-583468cd2d9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110456349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4110456349
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.791703819
Short name T917
Test name
Test status
Simulation time 82534721 ps
CPU time 0.9 seconds
Started Apr 23 01:51:55 PM PDT 24
Finished Apr 23 01:51:57 PM PDT 24
Peak memory 205792 kb
Host smart-95eeff7c-832c-447f-9ddf-877023e4017a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791703819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.791703819
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.459623316
Short name T971
Test name
Test status
Simulation time 245545118 ps
CPU time 1.87 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 205896 kb
Host smart-e6059376-19ca-468b-9ba9-a1ba47115a60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459623316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.459623316
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.207489489
Short name T965
Test name
Test status
Simulation time 231680780 ps
CPU time 4.04 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 214584 kb
Host smart-52c9b43c-38c0-411d-8d66-b6d12068d27f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207489489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.207489489
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3583014493
Short name T1016
Test name
Test status
Simulation time 745974259 ps
CPU time 12.88 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:52:02 PM PDT 24
Peak memory 220564 kb
Host smart-dbed0bb0-e7b0-4ab3-917f-f8aace972001
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583014493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3583014493
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.299650821
Short name T985
Test name
Test status
Simulation time 44266507 ps
CPU time 2.04 seconds
Started Apr 23 01:51:53 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 214168 kb
Host smart-1f42a124-c5eb-40c1-95dc-84340b745e98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299650821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.299650821
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.982780043
Short name T952
Test name
Test status
Simulation time 473249203 ps
CPU time 1.69 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 214492 kb
Host smart-bd1cb0e2-78da-4c09-b76f-6e9f280bc7ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982780043 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.982780043
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1184855922
Short name T1045
Test name
Test status
Simulation time 26919913 ps
CPU time 1.53 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:52 PM PDT 24
Peak memory 206028 kb
Host smart-d65ddb1c-a440-4638-8d06-df304e01ba5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184855922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1184855922
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.94547283
Short name T905
Test name
Test status
Simulation time 32494053 ps
CPU time 0.75 seconds
Started Apr 23 01:52:05 PM PDT 24
Finished Apr 23 01:52:06 PM PDT 24
Peak memory 205744 kb
Host smart-cd04144c-6847-40e8-901d-4b40bd482597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94547283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.94547283
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2528411063
Short name T932
Test name
Test status
Simulation time 35346472 ps
CPU time 2.04 seconds
Started Apr 23 01:51:56 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 206068 kb
Host smart-f91a3c8b-8b2b-4039-a84d-d5f9fbaded5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528411063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2528411063
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.78886897
Short name T119
Test name
Test status
Simulation time 227984219 ps
CPU time 5.83 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:58 PM PDT 24
Peak memory 214592 kb
Host smart-1544d1c0-671d-4c15-bf09-9364cbe28761
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78886897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow
_reg_errors.78886897
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3374986083
Short name T1025
Test name
Test status
Simulation time 153707807 ps
CPU time 8.66 seconds
Started Apr 23 01:51:56 PM PDT 24
Finished Apr 23 01:52:06 PM PDT 24
Peak memory 214528 kb
Host smart-1c61a903-0712-456d-8f23-48b2bfcd6d83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374986083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3374986083
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.936374395
Short name T1077
Test name
Test status
Simulation time 92841631 ps
CPU time 1.88 seconds
Started Apr 23 01:51:53 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 215360 kb
Host smart-8db1abee-9621-4301-9acf-b1758a2a858b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936374395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.936374395
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1807039491
Short name T984
Test name
Test status
Simulation time 752620344 ps
CPU time 15.44 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:52:04 PM PDT 24
Peak memory 214336 kb
Host smart-e2644085-eb83-452c-9aaa-33a1b18ad3f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807039491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1807039491
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2211027553
Short name T938
Test name
Test status
Simulation time 31754322 ps
CPU time 2.16 seconds
Started Apr 23 01:51:52 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 214320 kb
Host smart-85309ad8-5e46-47b9-a6b6-3a9e053f9de1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211027553 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2211027553
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1984354812
Short name T992
Test name
Test status
Simulation time 35978847 ps
CPU time 1.04 seconds
Started Apr 23 01:51:53 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 205772 kb
Host smart-df3b6104-cad4-42e6-ac82-1676e8aac131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984354812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1984354812
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2369689413
Short name T1004
Test name
Test status
Simulation time 23974419 ps
CPU time 0.8 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 205788 kb
Host smart-4f32bb7f-f1e2-4270-90af-a6589a2f7ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369689413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2369689413
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2533401845
Short name T1074
Test name
Test status
Simulation time 77009498 ps
CPU time 1.37 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:52:00 PM PDT 24
Peak memory 205992 kb
Host smart-4e6e9d0d-cfb7-4bcb-bb6e-a9f2c2fc2743
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533401845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2533401845
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3453701493
Short name T121
Test name
Test status
Simulation time 94081785 ps
CPU time 3.6 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:03 PM PDT 24
Peak memory 214608 kb
Host smart-2b34b3dd-4a28-4a61-892c-221b9794d1fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453701493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3453701493
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.696123444
Short name T1012
Test name
Test status
Simulation time 393451390 ps
CPU time 13.8 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:52:11 PM PDT 24
Peak memory 214456 kb
Host smart-7c7e7c6a-1b28-4cf6-8061-3018ea3c10af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696123444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.696123444
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1141177330
Short name T949
Test name
Test status
Simulation time 197258053 ps
CPU time 3.7 seconds
Started Apr 23 01:52:01 PM PDT 24
Finished Apr 23 01:52:06 PM PDT 24
Peak memory 214268 kb
Host smart-8dda7409-6d64-4d11-a75f-6ca37103bf87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141177330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1141177330
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3984152183
Short name T925
Test name
Test status
Simulation time 260635805 ps
CPU time 4.03 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:44 PM PDT 24
Peak memory 206032 kb
Host smart-14553823-938f-44a2-be74-b3c5db0306cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984152183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
984152183
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1035443940
Short name T1007
Test name
Test status
Simulation time 1334428006 ps
CPU time 27.18 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:52:17 PM PDT 24
Peak memory 205948 kb
Host smart-e4a4e6f9-8eee-4d50-8b30-6d533b0b7595
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035443940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
035443940
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1161967712
Short name T1032
Test name
Test status
Simulation time 17159780 ps
CPU time 0.99 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:42 PM PDT 24
Peak memory 206028 kb
Host smart-5594a860-12df-45d9-a898-477be99bf24c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161967712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
161967712
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4037034542
Short name T956
Test name
Test status
Simulation time 61019085 ps
CPU time 1.19 seconds
Started Apr 23 01:51:43 PM PDT 24
Finished Apr 23 01:51:46 PM PDT 24
Peak memory 214436 kb
Host smart-56cc57ed-fc5e-4f67-bff8-9acd3751e010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037034542 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4037034542
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1075484268
Short name T998
Test name
Test status
Simulation time 21580127 ps
CPU time 1.18 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:52 PM PDT 24
Peak memory 206004 kb
Host smart-7144c2d1-8077-4b45-beb9-5977e77b3a24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075484268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1075484268
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2989397879
Short name T1070
Test name
Test status
Simulation time 19415022 ps
CPU time 0.72 seconds
Started Apr 23 01:51:40 PM PDT 24
Finished Apr 23 01:51:42 PM PDT 24
Peak memory 205772 kb
Host smart-61444c5b-49aa-4bb0-8688-a9d08a7391a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989397879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2989397879
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1241631773
Short name T1003
Test name
Test status
Simulation time 226481064 ps
CPU time 2.38 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 206168 kb
Host smart-cd6b1a99-e4fd-4766-9a78-bdd24acab326
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241631773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1241631773
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3306049061
Short name T954
Test name
Test status
Simulation time 806677541 ps
CPU time 4.5 seconds
Started Apr 23 01:51:43 PM PDT 24
Finished Apr 23 01:51:49 PM PDT 24
Peak memory 222780 kb
Host smart-72dce03c-8a74-4acc-888d-2fd2c6895c3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306049061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3306049061
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4087248249
Short name T117
Test name
Test status
Simulation time 207640636 ps
CPU time 9.2 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 214680 kb
Host smart-6571dc2d-f78a-4a1a-9f8c-fcf96a1b6165
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087248249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4087248249
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.215164012
Short name T1076
Test name
Test status
Simulation time 396695165 ps
CPU time 4.44 seconds
Started Apr 23 01:51:41 PM PDT 24
Finished Apr 23 01:51:47 PM PDT 24
Peak memory 216764 kb
Host smart-493e99dd-e810-490b-a3f3-a103da1c381c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215164012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.215164012
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3723130616
Short name T150
Test name
Test status
Simulation time 791865369 ps
CPU time 11.38 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 214356 kb
Host smart-e099d6c1-34e5-49f6-9b91-faeff8c8f116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723130616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3723130616
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1827104345
Short name T970
Test name
Test status
Simulation time 14442018 ps
CPU time 0.7 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 205636 kb
Host smart-89e14c90-f304-4607-8bd3-16914159febd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827104345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1827104345
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1948606808
Short name T997
Test name
Test status
Simulation time 13512482 ps
CPU time 0.87 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 205716 kb
Host smart-92138503-334e-4866-a3c0-a2f7b08ef80e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948606808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1948606808
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.569460410
Short name T910
Test name
Test status
Simulation time 10348122 ps
CPU time 0.72 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:00 PM PDT 24
Peak memory 205848 kb
Host smart-02c87138-4aaa-4aac-b3a1-eca039a72f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569460410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.569460410
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1190564821
Short name T906
Test name
Test status
Simulation time 34303901 ps
CPU time 0.72 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 205852 kb
Host smart-ab6fd468-4428-4cf3-8116-b748aa6dbd4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190564821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1190564821
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2838475031
Short name T979
Test name
Test status
Simulation time 24010463 ps
CPU time 0.83 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 205764 kb
Host smart-3da26548-5010-46d1-9d49-640ca8d660da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838475031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2838475031
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3682260398
Short name T957
Test name
Test status
Simulation time 12895565 ps
CPU time 0.9 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 205864 kb
Host smart-db4f41c4-e404-4e13-b3bb-492c413a413e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682260398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3682260398
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2351995368
Short name T942
Test name
Test status
Simulation time 34475987 ps
CPU time 0.74 seconds
Started Apr 23 01:51:52 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 205824 kb
Host smart-0586d135-5a89-49bd-a35d-87bc96b7f5d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351995368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2351995368
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3229350806
Short name T983
Test name
Test status
Simulation time 69729305 ps
CPU time 0.7 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 205792 kb
Host smart-5c8b44b3-7006-4c6b-b587-f94a0edb94c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229350806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3229350806
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.585679598
Short name T1023
Test name
Test status
Simulation time 11533635 ps
CPU time 0.71 seconds
Started Apr 23 01:51:56 PM PDT 24
Finished Apr 23 01:51:58 PM PDT 24
Peak memory 205816 kb
Host smart-95e65e55-103b-448b-8f88-5bb0ba331880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585679598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.585679598
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1005806198
Short name T914
Test name
Test status
Simulation time 8240301 ps
CPU time 0.71 seconds
Started Apr 23 01:51:55 PM PDT 24
Finished Apr 23 01:51:57 PM PDT 24
Peak memory 205744 kb
Host smart-795388cb-cec3-4867-86cb-06384fdeb60a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005806198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1005806198
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3858467262
Short name T1027
Test name
Test status
Simulation time 1155914407 ps
CPU time 6.9 seconds
Started Apr 23 01:51:43 PM PDT 24
Finished Apr 23 01:51:52 PM PDT 24
Peak memory 206160 kb
Host smart-47fd847a-f1ff-42e1-8ae8-e0c48d7d3cdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858467262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
858467262
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1210876086
Short name T923
Test name
Test status
Simulation time 558705386 ps
CPU time 6.72 seconds
Started Apr 23 01:51:38 PM PDT 24
Finished Apr 23 01:51:46 PM PDT 24
Peak memory 206088 kb
Host smart-08d45b9c-f467-484c-a359-a48338bd8a3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210876086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
210876086
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.386094427
Short name T1071
Test name
Test status
Simulation time 29783001 ps
CPU time 1.06 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:52 PM PDT 24
Peak memory 205984 kb
Host smart-fbf1e088-3427-4d24-ac44-9f368491fb1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386094427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.386094427
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.330929029
Short name T988
Test name
Test status
Simulation time 21237118 ps
CPU time 1.39 seconds
Started Apr 23 01:51:42 PM PDT 24
Finished Apr 23 01:51:46 PM PDT 24
Peak memory 206148 kb
Host smart-079312ed-d5ef-405e-9897-041a92f4767e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330929029 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.330929029
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.622173855
Short name T933
Test name
Test status
Simulation time 23335087 ps
CPU time 0.86 seconds
Started Apr 23 01:51:40 PM PDT 24
Finished Apr 23 01:51:48 PM PDT 24
Peak memory 205952 kb
Host smart-5762a9d0-aaa8-4070-a77b-8649184aa122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622173855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.622173855
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.722048108
Short name T904
Test name
Test status
Simulation time 7557389 ps
CPU time 0.85 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:42 PM PDT 24
Peak memory 205780 kb
Host smart-a5703f3b-7930-491c-a4e7-7d9fcbcb0677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722048108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.722048108
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3883005858
Short name T996
Test name
Test status
Simulation time 91776506 ps
CPU time 3.84 seconds
Started Apr 23 01:51:38 PM PDT 24
Finished Apr 23 01:51:43 PM PDT 24
Peak memory 206200 kb
Host smart-d934cf26-ef20-4911-a02f-16add7eafe04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883005858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3883005858
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1166742616
Short name T964
Test name
Test status
Simulation time 81534304 ps
CPU time 2.43 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:43 PM PDT 24
Peak memory 222712 kb
Host smart-c7065584-7d07-44c5-a534-78232df805e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166742616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1166742616
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2796332447
Short name T1072
Test name
Test status
Simulation time 697001941 ps
CPU time 4.84 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:51:57 PM PDT 24
Peak memory 214452 kb
Host smart-f47e4c8e-44a9-40e8-9c22-eba677b5bdef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796332447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2796332447
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1840498717
Short name T1028
Test name
Test status
Simulation time 84815477 ps
CPU time 3.31 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 217520 kb
Host smart-2b1be001-5a94-492d-b0dd-a6e4313ce69f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840498717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1840498717
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2387235063
Short name T153
Test name
Test status
Simulation time 3530206161 ps
CPU time 11.88 seconds
Started Apr 23 01:51:44 PM PDT 24
Finished Apr 23 01:51:58 PM PDT 24
Peak memory 214268 kb
Host smart-f62ee2d2-a544-4754-b2a7-906fa3193052
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387235063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2387235063
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3337017127
Short name T980
Test name
Test status
Simulation time 10162290 ps
CPU time 0.8 seconds
Started Apr 23 01:52:01 PM PDT 24
Finished Apr 23 01:52:03 PM PDT 24
Peak memory 205740 kb
Host smart-277f79a1-1b3d-427c-b5e9-4537f1ee725c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337017127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3337017127
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.517222720
Short name T1053
Test name
Test status
Simulation time 31128860 ps
CPU time 0.75 seconds
Started Apr 23 01:52:01 PM PDT 24
Finished Apr 23 01:52:03 PM PDT 24
Peak memory 205788 kb
Host smart-9260a473-de92-423a-b57c-fe9662a8b36b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517222720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.517222720
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3783442616
Short name T967
Test name
Test status
Simulation time 35242301 ps
CPU time 0.68 seconds
Started Apr 23 01:51:56 PM PDT 24
Finished Apr 23 01:51:58 PM PDT 24
Peak memory 205740 kb
Host smart-ff90afce-70bc-4f88-bb30-83865d762613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783442616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3783442616
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.113057583
Short name T1000
Test name
Test status
Simulation time 110631420 ps
CPU time 0.87 seconds
Started Apr 23 01:51:52 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 205820 kb
Host smart-b86719ed-0a87-4c8f-a828-2f4800888557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113057583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.113057583
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2988368854
Short name T995
Test name
Test status
Simulation time 23033400 ps
CPU time 0.86 seconds
Started Apr 23 01:51:58 PM PDT 24
Finished Apr 23 01:52:00 PM PDT 24
Peak memory 205740 kb
Host smart-3395a9a1-7995-4eec-90fb-d1c369283f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988368854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2988368854
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3781127013
Short name T1048
Test name
Test status
Simulation time 12127124 ps
CPU time 0.83 seconds
Started Apr 23 01:52:04 PM PDT 24
Finished Apr 23 01:52:10 PM PDT 24
Peak memory 205740 kb
Host smart-6e803ca3-099a-44e7-8761-7ca3e218b584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781127013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3781127013
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.521311234
Short name T1069
Test name
Test status
Simulation time 38635493 ps
CPU time 0.85 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 205848 kb
Host smart-606fcfe8-d7f6-46d9-9ebb-d7727abea870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521311234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.521311234
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2697330521
Short name T1065
Test name
Test status
Simulation time 44506801 ps
CPU time 0.97 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 205772 kb
Host smart-e07308b2-8d22-44ed-8216-242f1e74cd55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697330521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2697330521
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3382179566
Short name T969
Test name
Test status
Simulation time 15503498 ps
CPU time 0.86 seconds
Started Apr 23 01:52:02 PM PDT 24
Finished Apr 23 01:52:04 PM PDT 24
Peak memory 206012 kb
Host smart-930026b0-5fce-49cb-9a0e-e12dc25eb01d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382179566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3382179566
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2940508560
Short name T1013
Test name
Test status
Simulation time 51228368 ps
CPU time 0.86 seconds
Started Apr 23 01:51:55 PM PDT 24
Finished Apr 23 01:51:57 PM PDT 24
Peak memory 205780 kb
Host smart-ca5dd525-f0f8-465f-ac4b-ea391037eebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940508560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2940508560
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1360751875
Short name T915
Test name
Test status
Simulation time 474607505 ps
CPU time 10.47 seconds
Started Apr 23 01:51:38 PM PDT 24
Finished Apr 23 01:51:49 PM PDT 24
Peak memory 205984 kb
Host smart-91b3990c-d673-4bfc-9226-be424e738ad9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360751875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
360751875
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.936944283
Short name T944
Test name
Test status
Simulation time 439332594 ps
CPU time 7.92 seconds
Started Apr 23 01:51:40 PM PDT 24
Finished Apr 23 01:51:49 PM PDT 24
Peak memory 205492 kb
Host smart-386ef0bd-739e-49e9-9204-3f9c180e5365
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936944283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.936944283
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3973614465
Short name T987
Test name
Test status
Simulation time 113989726 ps
CPU time 1.4 seconds
Started Apr 23 01:51:44 PM PDT 24
Finished Apr 23 01:51:47 PM PDT 24
Peak memory 205948 kb
Host smart-0382fe4a-95bf-424a-9961-92b6a96fdb97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973614465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
973614465
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2234937824
Short name T1046
Test name
Test status
Simulation time 108100103 ps
CPU time 1.29 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:49 PM PDT 24
Peak memory 206104 kb
Host smart-cd282bc0-0d95-4ee5-8a8d-3ac35c8cb9ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234937824 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2234937824
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2851031811
Short name T972
Test name
Test status
Simulation time 112796508 ps
CPU time 1.49 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 205992 kb
Host smart-db581986-cfe0-4523-a334-1557967508ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851031811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2851031811
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3949703057
Short name T912
Test name
Test status
Simulation time 40629585 ps
CPU time 0.78 seconds
Started Apr 23 01:51:38 PM PDT 24
Finished Apr 23 01:51:39 PM PDT 24
Peak memory 205716 kb
Host smart-86cb08e5-2c50-458e-ad02-5628205912f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949703057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3949703057
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1986313343
Short name T1011
Test name
Test status
Simulation time 64499556 ps
CPU time 1.61 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:52 PM PDT 24
Peak memory 206164 kb
Host smart-714e0bd7-d6b2-4b43-b8c0-b88c841cf48c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986313343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1986313343
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3316842883
Short name T945
Test name
Test status
Simulation time 76742171 ps
CPU time 2 seconds
Started Apr 23 01:51:44 PM PDT 24
Finished Apr 23 01:51:48 PM PDT 24
Peak memory 214532 kb
Host smart-1749a644-98e1-42c3-ae7c-1d0e859d0561
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316842883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3316842883
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4292139457
Short name T994
Test name
Test status
Simulation time 231375773 ps
CPU time 7.03 seconds
Started Apr 23 01:51:41 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 214536 kb
Host smart-088db25e-8399-4a74-b2e4-cf013dd37d70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292139457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4292139457
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.63617875
Short name T991
Test name
Test status
Simulation time 57672543 ps
CPU time 2.29 seconds
Started Apr 23 01:51:44 PM PDT 24
Finished Apr 23 01:51:48 PM PDT 24
Peak memory 214352 kb
Host smart-8b752f63-80e4-411d-947d-cabe614cb7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63617875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.63617875
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1531366340
Short name T145
Test name
Test status
Simulation time 499510167 ps
CPU time 8.27 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:48 PM PDT 24
Peak memory 214272 kb
Host smart-3e8eb2ac-b773-4e4b-9da9-2c5a94c91e65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531366340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1531366340
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3808418933
Short name T937
Test name
Test status
Simulation time 8554440 ps
CPU time 0.86 seconds
Started Apr 23 01:52:02 PM PDT 24
Finished Apr 23 01:52:04 PM PDT 24
Peak memory 205824 kb
Host smart-d9441f50-6007-4f43-ac41-dfd9e1d2819e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808418933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3808418933
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.519420493
Short name T1057
Test name
Test status
Simulation time 61255100 ps
CPU time 0.71 seconds
Started Apr 23 01:52:07 PM PDT 24
Finished Apr 23 01:52:08 PM PDT 24
Peak memory 205740 kb
Host smart-29ecfaf1-f04e-4be9-9703-820d6352d830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519420493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.519420493
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3326572559
Short name T1063
Test name
Test status
Simulation time 127483918 ps
CPU time 0.82 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 205784 kb
Host smart-e8ea2e24-35bc-4ff2-8253-0bd2f1906f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326572559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3326572559
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1056960782
Short name T1010
Test name
Test status
Simulation time 60599310 ps
CPU time 0.85 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 205688 kb
Host smart-5d6e20d0-8312-4a11-a40f-8e3149300734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056960782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1056960782
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.467623307
Short name T1066
Test name
Test status
Simulation time 42909104 ps
CPU time 0.8 seconds
Started Apr 23 01:51:53 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 205788 kb
Host smart-788aff6e-65d3-497e-82fe-bf8490356e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467623307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.467623307
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1472999386
Short name T931
Test name
Test status
Simulation time 13890443 ps
CPU time 0.8 seconds
Started Apr 23 01:52:04 PM PDT 24
Finished Apr 23 01:52:05 PM PDT 24
Peak memory 205772 kb
Host smart-f1de56f4-d7d9-43ab-a816-07c39ced171d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472999386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1472999386
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3978509108
Short name T993
Test name
Test status
Simulation time 47458948 ps
CPU time 0.74 seconds
Started Apr 23 01:51:55 PM PDT 24
Finished Apr 23 01:51:57 PM PDT 24
Peak memory 205796 kb
Host smart-92ca2095-ebe4-4dc5-8111-c85961556530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978509108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3978509108
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3847043459
Short name T958
Test name
Test status
Simulation time 28020956 ps
CPU time 0.69 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 205740 kb
Host smart-dc9c4a6b-3b02-4b1e-8892-d11e94fc950a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847043459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3847043459
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3944326046
Short name T1051
Test name
Test status
Simulation time 14564608 ps
CPU time 0.79 seconds
Started Apr 23 01:51:54 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 205844 kb
Host smart-b320e3c3-5da5-40d4-9bad-f43aee62f8e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944326046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3944326046
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.637974992
Short name T911
Test name
Test status
Simulation time 13322813 ps
CPU time 0.7 seconds
Started Apr 23 01:51:55 PM PDT 24
Finished Apr 23 01:51:57 PM PDT 24
Peak memory 205796 kb
Host smart-383a6b87-8c89-4e60-a995-bea6788fecc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637974992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.637974992
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.697903058
Short name T977
Test name
Test status
Simulation time 182572196 ps
CPU time 2.77 seconds
Started Apr 23 01:51:43 PM PDT 24
Finished Apr 23 01:51:47 PM PDT 24
Peak memory 214388 kb
Host smart-c98e8b30-3a21-488c-8960-d0344056a319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697903058 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.697903058
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1101506907
Short name T1055
Test name
Test status
Simulation time 33229766 ps
CPU time 1.26 seconds
Started Apr 23 01:51:44 PM PDT 24
Finished Apr 23 01:51:47 PM PDT 24
Peak memory 206044 kb
Host smart-ea6b9b07-b0c5-4ab4-abfc-36a0d858c7c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101506907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1101506907
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.592182688
Short name T930
Test name
Test status
Simulation time 33334553 ps
CPU time 0.79 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:41 PM PDT 24
Peak memory 205812 kb
Host smart-fe6acc7c-4a20-49b8-874d-2b7b879ac378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592182688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.592182688
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3126973382
Short name T140
Test name
Test status
Simulation time 46680941 ps
CPU time 1.67 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 206008 kb
Host smart-6fc38d41-1566-452c-9745-8a3200c2e7b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126973382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3126973382
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4099175887
Short name T999
Test name
Test status
Simulation time 336126300 ps
CPU time 6.75 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 214552 kb
Host smart-60b2630c-76a7-43c3-a6ef-27c699d09df9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099175887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.4099175887
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2946952551
Short name T916
Test name
Test status
Simulation time 294254744 ps
CPU time 3.78 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 214716 kb
Host smart-9b652fdc-2f75-4a66-b741-a4513aaa83df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946952551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2946952551
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1171537569
Short name T1060
Test name
Test status
Simulation time 1598684878 ps
CPU time 4.66 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:56 PM PDT 24
Peak memory 217344 kb
Host smart-c7242973-7029-4ec5-96da-0e4abe37b2cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171537569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1171537569
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1744625125
Short name T982
Test name
Test status
Simulation time 280774365 ps
CPU time 5.73 seconds
Started Apr 23 01:51:36 PM PDT 24
Finished Apr 23 01:51:42 PM PDT 24
Peak memory 214324 kb
Host smart-56e05685-4333-423d-9f8d-0c886909b3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744625125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1744625125
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4201831912
Short name T959
Test name
Test status
Simulation time 209551580 ps
CPU time 1.52 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 214344 kb
Host smart-829105c6-db33-4f82-9978-35ed45b0d729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201831912 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4201831912
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4127279511
Short name T1044
Test name
Test status
Simulation time 49577782 ps
CPU time 0.92 seconds
Started Apr 23 01:51:48 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 205800 kb
Host smart-0df57e29-dd54-4a89-9855-f7284a666cb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127279511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4127279511
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3510695330
Short name T947
Test name
Test status
Simulation time 20128363 ps
CPU time 0.82 seconds
Started Apr 23 01:51:50 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 205780 kb
Host smart-e9106a5e-6af7-4324-9912-851f56f7f88b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510695330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3510695330
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3351790803
Short name T946
Test name
Test status
Simulation time 53846787 ps
CPU time 2.47 seconds
Started Apr 23 01:51:42 PM PDT 24
Finished Apr 23 01:51:47 PM PDT 24
Peak memory 206028 kb
Host smart-57090471-45ae-458c-b241-b67403ba633a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351790803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3351790803
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1228429621
Short name T1075
Test name
Test status
Simulation time 388174381 ps
CPU time 3.03 seconds
Started Apr 23 01:51:42 PM PDT 24
Finished Apr 23 01:51:47 PM PDT 24
Peak memory 222724 kb
Host smart-9548ad02-40e4-4d58-9d48-61d8ca798d84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228429621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1228429621
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.471158525
Short name T908
Test name
Test status
Simulation time 25998900 ps
CPU time 1.91 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 216276 kb
Host smart-550c4a6e-37b9-4a17-919b-61a4abaac1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471158525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.471158525
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.605835055
Short name T148
Test name
Test status
Simulation time 1886471874 ps
CPU time 17.68 seconds
Started Apr 23 01:51:41 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 209752 kb
Host smart-4c61b852-fb59-4ed6-8dd1-8388839e8deb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605835055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
605835055
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3010102398
Short name T928
Test name
Test status
Simulation time 97191481 ps
CPU time 1.36 seconds
Started Apr 23 01:51:38 PM PDT 24
Finished Apr 23 01:51:40 PM PDT 24
Peak memory 214432 kb
Host smart-6e17ddf7-fff8-4219-afc3-b72bbbe0ad5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010102398 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3010102398
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1441140875
Short name T919
Test name
Test status
Simulation time 43089086 ps
CPU time 1.07 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 205956 kb
Host smart-9ef2012a-2ea1-4d07-ad65-635eadc0d552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441140875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1441140875
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.629946951
Short name T1026
Test name
Test status
Simulation time 14201162 ps
CPU time 0.71 seconds
Started Apr 23 01:51:42 PM PDT 24
Finished Apr 23 01:51:45 PM PDT 24
Peak memory 205724 kb
Host smart-0b1da0c1-de3d-49d4-bb12-0df90ea81c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629946951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.629946951
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.252293140
Short name T955
Test name
Test status
Simulation time 27939180 ps
CPU time 1.55 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:48 PM PDT 24
Peak memory 206128 kb
Host smart-89f92979-5bfb-4521-aa89-b325d29f09c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252293140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.252293140
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1256706696
Short name T921
Test name
Test status
Simulation time 109462878 ps
CPU time 2.14 seconds
Started Apr 23 01:51:53 PM PDT 24
Finished Apr 23 01:51:57 PM PDT 24
Peak memory 214444 kb
Host smart-b5afc5ec-ff29-424c-a77a-f1e5c6862719
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256706696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1256706696
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1923757430
Short name T976
Test name
Test status
Simulation time 1373611424 ps
CPU time 9.38 seconds
Started Apr 23 01:51:40 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 214584 kb
Host smart-ee79c7db-d56e-4213-b42d-501700e755de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923757430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1923757430
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1302484138
Short name T990
Test name
Test status
Simulation time 595449643 ps
CPU time 4.97 seconds
Started Apr 23 01:51:44 PM PDT 24
Finished Apr 23 01:51:51 PM PDT 24
Peak memory 216464 kb
Host smart-957f0e96-806a-4194-8898-943015cea5b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302484138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1302484138
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1274227484
Short name T151
Test name
Test status
Simulation time 778361533 ps
CPU time 5.92 seconds
Started Apr 23 01:51:39 PM PDT 24
Finished Apr 23 01:51:47 PM PDT 24
Peak memory 213684 kb
Host smart-a4075a5d-7cdb-4df0-af69-86dc138ff416
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274227484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1274227484
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2855951270
Short name T986
Test name
Test status
Simulation time 59890608 ps
CPU time 1.73 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:49 PM PDT 24
Peak memory 214368 kb
Host smart-a170c744-4e5e-43f3-8558-8adca789b305
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855951270 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2855951270
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2113842878
Short name T1049
Test name
Test status
Simulation time 32494835 ps
CPU time 1.43 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 205984 kb
Host smart-dbc3a6aa-2396-416c-9b03-a1cee54b88ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113842878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2113842878
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.790393296
Short name T1020
Test name
Test status
Simulation time 15177607 ps
CPU time 0.77 seconds
Started Apr 23 01:51:41 PM PDT 24
Finished Apr 23 01:51:44 PM PDT 24
Peak memory 205744 kb
Host smart-8f907333-776c-423e-b6c4-1ca13c91615f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790393296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.790393296
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2380254014
Short name T924
Test name
Test status
Simulation time 338385046 ps
CPU time 1.86 seconds
Started Apr 23 01:51:40 PM PDT 24
Finished Apr 23 01:51:44 PM PDT 24
Peak memory 206024 kb
Host smart-1a41d955-8315-4614-9404-0270ca80cd78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380254014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2380254014
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1077916778
Short name T1036
Test name
Test status
Simulation time 100968849 ps
CPU time 3.3 seconds
Started Apr 23 01:51:49 PM PDT 24
Finished Apr 23 01:51:54 PM PDT 24
Peak memory 214608 kb
Host smart-284323df-3b94-4357-8ef1-b84bb8bdfbef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077916778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1077916778
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3777496234
Short name T948
Test name
Test status
Simulation time 1324182487 ps
CPU time 10.15 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:52:03 PM PDT 24
Peak memory 214488 kb
Host smart-fdcb7110-0eb9-4df1-a1b0-2a1abe86b3f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777496234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3777496234
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1137429551
Short name T918
Test name
Test status
Simulation time 31961916 ps
CPU time 2.31 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 214184 kb
Host smart-46bf3fbf-1c61-4d8c-b84a-b7fa7e1087b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137429551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1137429551
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.431731692
Short name T1041
Test name
Test status
Simulation time 268820792 ps
CPU time 10.6 seconds
Started Apr 23 01:51:46 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 209504 kb
Host smart-4d34f2ce-48f0-4500-9b63-46b651216b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431731692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
431731692
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.468089926
Short name T1008
Test name
Test status
Simulation time 262736373 ps
CPU time 2.19 seconds
Started Apr 23 01:51:42 PM PDT 24
Finished Apr 23 01:51:46 PM PDT 24
Peak memory 217544 kb
Host smart-d96e0811-9855-4bac-b36f-263ef9677f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468089926 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.468089926
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3423570232
Short name T1056
Test name
Test status
Simulation time 140146903 ps
CPU time 1.3 seconds
Started Apr 23 01:51:42 PM PDT 24
Finished Apr 23 01:51:46 PM PDT 24
Peak memory 206032 kb
Host smart-38c3caff-3a11-47c1-ae9d-691c61f4cc77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423570232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3423570232
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2195642038
Short name T968
Test name
Test status
Simulation time 32813911 ps
CPU time 0.81 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:51:53 PM PDT 24
Peak memory 205756 kb
Host smart-db75df85-9586-44f1-a01e-ee1bc6d13465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195642038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2195642038
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3194367134
Short name T1024
Test name
Test status
Simulation time 174172309 ps
CPU time 2.28 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:50 PM PDT 24
Peak memory 206184 kb
Host smart-6faf7680-7aa4-4eb7-8a25-0616c1e5b498
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194367134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3194367134
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.427816623
Short name T1058
Test name
Test status
Simulation time 186097850 ps
CPU time 2.44 seconds
Started Apr 23 01:51:51 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 222732 kb
Host smart-66dd1931-c837-4ede-a39e-31a00b1f11f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427816623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.427816623
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4231852762
Short name T118
Test name
Test status
Simulation time 924678421 ps
CPU time 8.58 seconds
Started Apr 23 01:51:45 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 220388 kb
Host smart-88cbb3ee-df43-4076-811c-785198d5b4ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231852762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.4231852762
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.334242700
Short name T1061
Test name
Test status
Simulation time 705841181 ps
CPU time 5.82 seconds
Started Apr 23 01:51:47 PM PDT 24
Finished Apr 23 01:51:59 PM PDT 24
Peak memory 217508 kb
Host smart-b487a392-ede2-40ed-a574-22ca0c124da4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334242700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.334242700
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3504430973
Short name T693
Test name
Test status
Simulation time 71692506 ps
CPU time 0.83 seconds
Started Apr 23 01:54:42 PM PDT 24
Finished Apr 23 01:54:44 PM PDT 24
Peak memory 206048 kb
Host smart-24d56c63-7188-4920-9278-e9be93c989a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504430973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3504430973
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.4038319571
Short name T278
Test name
Test status
Simulation time 55345848 ps
CPU time 3.27 seconds
Started Apr 23 01:54:37 PM PDT 24
Finished Apr 23 01:54:41 PM PDT 24
Peak memory 210064 kb
Host smart-2526b7af-c202-45fb-935d-7d373440aa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038319571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.4038319571
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2535196472
Short name T550
Test name
Test status
Simulation time 507467174 ps
CPU time 9.54 seconds
Started Apr 23 01:54:36 PM PDT 24
Finished Apr 23 01:54:46 PM PDT 24
Peak memory 208888 kb
Host smart-311d7e3e-3505-4355-b73c-0c3c759fec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535196472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2535196472
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.125829260
Short name T322
Test name
Test status
Simulation time 620132197 ps
CPU time 9.92 seconds
Started Apr 23 01:54:38 PM PDT 24
Finished Apr 23 01:54:49 PM PDT 24
Peak memory 214752 kb
Host smart-464b90c6-f373-4561-bb84-8a0d837fbbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125829260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.125829260
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.864375286
Short name T311
Test name
Test status
Simulation time 720286942 ps
CPU time 9.07 seconds
Started Apr 23 01:54:39 PM PDT 24
Finished Apr 23 01:54:48 PM PDT 24
Peak memory 214548 kb
Host smart-fd6e56bf-8b61-4c5c-8789-ff57f92ac69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864375286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.864375286
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3079789398
Short name T808
Test name
Test status
Simulation time 149249983 ps
CPU time 3.09 seconds
Started Apr 23 01:54:37 PM PDT 24
Finished Apr 23 01:54:40 PM PDT 24
Peak memory 209636 kb
Host smart-222b346c-7534-4f88-b010-e3c657e0b7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079789398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3079789398
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.24339409
Short name T14
Test name
Test status
Simulation time 3278684737 ps
CPU time 17.44 seconds
Started Apr 23 01:54:38 PM PDT 24
Finished Apr 23 01:54:56 PM PDT 24
Peak memory 241184 kb
Host smart-476a56c7-521c-41e2-9cd2-7f2fb396fde9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24339409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.24339409
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2212099812
Short name T887
Test name
Test status
Simulation time 69119554 ps
CPU time 2.93 seconds
Started Apr 23 01:54:37 PM PDT 24
Finished Apr 23 01:54:41 PM PDT 24
Peak memory 208904 kb
Host smart-f944f542-5aba-41db-9b4b-8299382c2c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212099812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2212099812
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.4018052794
Short name T370
Test name
Test status
Simulation time 109999325 ps
CPU time 2.9 seconds
Started Apr 23 01:54:37 PM PDT 24
Finished Apr 23 01:54:41 PM PDT 24
Peak memory 208956 kb
Host smart-73c5df87-941c-4eed-a37b-1ceeb3c265b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018052794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4018052794
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3250084214
Short name T242
Test name
Test status
Simulation time 1350528067 ps
CPU time 9.98 seconds
Started Apr 23 01:54:38 PM PDT 24
Finished Apr 23 01:54:48 PM PDT 24
Peak memory 208372 kb
Host smart-efcec410-5e92-4090-855c-39703df85211
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250084214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3250084214
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3111308881
Short name T697
Test name
Test status
Simulation time 162891777 ps
CPU time 2.5 seconds
Started Apr 23 01:54:39 PM PDT 24
Finished Apr 23 01:54:42 PM PDT 24
Peak memory 215784 kb
Host smart-287a4b2b-1f5a-4c39-8869-53fc44d09e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111308881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3111308881
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3161852612
Short name T836
Test name
Test status
Simulation time 152990488 ps
CPU time 2.23 seconds
Started Apr 23 01:54:37 PM PDT 24
Finished Apr 23 01:54:40 PM PDT 24
Peak memory 206960 kb
Host smart-0fba3fe3-37df-4b8b-a3c5-af4ad7118ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161852612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3161852612
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3128984582
Short name T75
Test name
Test status
Simulation time 3129892260 ps
CPU time 38.84 seconds
Started Apr 23 01:54:37 PM PDT 24
Finished Apr 23 01:55:17 PM PDT 24
Peak memory 215788 kb
Host smart-0d79afcb-0097-49d5-9a59-64ccc583e453
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128984582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3128984582
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.547431884
Short name T369
Test name
Test status
Simulation time 569616536 ps
CPU time 9.47 seconds
Started Apr 23 01:54:37 PM PDT 24
Finished Apr 23 01:54:47 PM PDT 24
Peak memory 214500 kb
Host smart-d7950dba-5f33-4c41-8b16-9678dcd101bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547431884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.547431884
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1094508692
Short name T620
Test name
Test status
Simulation time 558506243 ps
CPU time 2.92 seconds
Started Apr 23 01:54:37 PM PDT 24
Finished Apr 23 01:54:40 PM PDT 24
Peak memory 210272 kb
Host smart-2cf5db2f-1264-449e-a0f8-90b38b98a9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094508692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1094508692
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3335300212
Short name T874
Test name
Test status
Simulation time 24419345 ps
CPU time 0.79 seconds
Started Apr 23 01:54:46 PM PDT 24
Finished Apr 23 01:54:47 PM PDT 24
Peak memory 206212 kb
Host smart-741bdaf5-ec74-40c6-888b-268cddef6918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335300212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3335300212
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2839933045
Short name T32
Test name
Test status
Simulation time 405170027 ps
CPU time 4.59 seconds
Started Apr 23 01:54:43 PM PDT 24
Finished Apr 23 01:54:48 PM PDT 24
Peak memory 208424 kb
Host smart-ac7a98f6-f669-407c-a346-5fc94dec8724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839933045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2839933045
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.4002387974
Short name T883
Test name
Test status
Simulation time 1522433774 ps
CPU time 18.36 seconds
Started Apr 23 01:54:42 PM PDT 24
Finished Apr 23 01:55:01 PM PDT 24
Peak memory 218492 kb
Host smart-e211ca8d-07cb-4c8d-a780-da287fdfef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002387974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.4002387974
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_random.1630269723
Short name T782
Test name
Test status
Simulation time 1019223315 ps
CPU time 11.27 seconds
Started Apr 23 01:54:41 PM PDT 24
Finished Apr 23 01:54:53 PM PDT 24
Peak memory 214508 kb
Host smart-ea451518-9e6e-4368-8e4f-8b63bd8791e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630269723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1630269723
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.586502193
Short name T98
Test name
Test status
Simulation time 2732719434 ps
CPU time 36.84 seconds
Started Apr 23 01:54:43 PM PDT 24
Finished Apr 23 01:55:21 PM PDT 24
Peak memory 244616 kb
Host smart-3b24d38a-bf9a-4600-b26c-0ea746f6cfd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586502193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.586502193
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1027514350
Short name T479
Test name
Test status
Simulation time 656444974 ps
CPU time 2.86 seconds
Started Apr 23 01:54:43 PM PDT 24
Finished Apr 23 01:54:46 PM PDT 24
Peak memory 208628 kb
Host smart-cd53e497-80e1-47d8-9837-bd8d02a2d742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027514350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1027514350
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.27418335
Short name T823
Test name
Test status
Simulation time 228925262 ps
CPU time 5.96 seconds
Started Apr 23 01:54:41 PM PDT 24
Finished Apr 23 01:54:49 PM PDT 24
Peak memory 208116 kb
Host smart-f545a4c4-bb8b-4b7d-ad32-f2ea0c6bbfce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27418335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.27418335
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3754370032
Short name T584
Test name
Test status
Simulation time 223586151 ps
CPU time 3.42 seconds
Started Apr 23 01:54:41 PM PDT 24
Finished Apr 23 01:54:45 PM PDT 24
Peak memory 208788 kb
Host smart-1845cb48-495c-490f-8748-89555400afba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754370032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3754370032
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.546406960
Short name T466
Test name
Test status
Simulation time 31373432 ps
CPU time 2.28 seconds
Started Apr 23 01:54:39 PM PDT 24
Finished Apr 23 01:54:42 PM PDT 24
Peak memory 206908 kb
Host smart-3d2abb3a-131e-424c-a8c7-cf9ec3e58ba8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546406960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.546406960
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3463023540
Short name T614
Test name
Test status
Simulation time 5816356425 ps
CPU time 40.97 seconds
Started Apr 23 01:54:40 PM PDT 24
Finished Apr 23 01:55:21 PM PDT 24
Peak memory 208928 kb
Host smart-850e0467-9943-46bb-a6ea-caaa8495e22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463023540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3463023540
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1517044488
Short name T526
Test name
Test status
Simulation time 3747938175 ps
CPU time 94.33 seconds
Started Apr 23 01:54:41 PM PDT 24
Finished Apr 23 01:56:16 PM PDT 24
Peak memory 216256 kb
Host smart-90837a51-acc8-4f47-910a-e42264db2778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517044488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1517044488
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3846926074
Short name T226
Test name
Test status
Simulation time 150717868 ps
CPU time 4.94 seconds
Started Apr 23 01:54:43 PM PDT 24
Finished Apr 23 01:54:49 PM PDT 24
Peak memory 210624 kb
Host smart-524d5ba9-ceed-43a8-8253-aa341578a1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846926074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3846926074
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1203555761
Short name T755
Test name
Test status
Simulation time 103543420 ps
CPU time 0.81 seconds
Started Apr 23 01:55:24 PM PDT 24
Finished Apr 23 01:55:26 PM PDT 24
Peak memory 206180 kb
Host smart-4495707e-d28f-4f0e-8411-a62d8a86da90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203555761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1203555761
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.454212181
Short name T10
Test name
Test status
Simulation time 176461278 ps
CPU time 4.42 seconds
Started Apr 23 01:55:31 PM PDT 24
Finished Apr 23 01:55:36 PM PDT 24
Peak memory 211404 kb
Host smart-23a03a34-17c7-422a-b311-c0664dfcee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454212181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.454212181
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.686486825
Short name T46
Test name
Test status
Simulation time 64106457 ps
CPU time 3.09 seconds
Started Apr 23 01:55:22 PM PDT 24
Finished Apr 23 01:55:25 PM PDT 24
Peak memory 208920 kb
Host smart-a2b77772-ac0b-4246-b810-048a00617496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686486825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.686486825
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3068229855
Short name T554
Test name
Test status
Simulation time 654810837 ps
CPU time 5.87 seconds
Started Apr 23 01:55:36 PM PDT 24
Finished Apr 23 01:55:45 PM PDT 24
Peak memory 209504 kb
Host smart-71206d28-8b52-48f9-93ef-a211f0512145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068229855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3068229855
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1953025713
Short name T380
Test name
Test status
Simulation time 1275883170 ps
CPU time 43.98 seconds
Started Apr 23 01:55:25 PM PDT 24
Finished Apr 23 01:56:10 PM PDT 24
Peak memory 213104 kb
Host smart-01176a86-f566-4c04-b520-85898fb26d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953025713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1953025713
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.4013656295
Short name T899
Test name
Test status
Simulation time 5337230691 ps
CPU time 38.41 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:55:59 PM PDT 24
Peak memory 208232 kb
Host smart-f522dfac-d865-46d3-8d75-f2ae8a87f9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013656295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4013656295
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.99464745
Short name T263
Test name
Test status
Simulation time 40221546 ps
CPU time 1.69 seconds
Started Apr 23 01:55:28 PM PDT 24
Finished Apr 23 01:55:30 PM PDT 24
Peak memory 206956 kb
Host smart-a3bf12b3-5b7a-4785-9c1f-af3c263afb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99464745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.99464745
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1074471674
Short name T779
Test name
Test status
Simulation time 153161235 ps
CPU time 3.45 seconds
Started Apr 23 01:55:19 PM PDT 24
Finished Apr 23 01:55:23 PM PDT 24
Peak memory 208908 kb
Host smart-5e79be32-7a70-42f5-8e6e-03e8a4c5a0e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074471674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1074471674
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3154151949
Short name T703
Test name
Test status
Simulation time 41996705 ps
CPU time 2.6 seconds
Started Apr 23 01:55:22 PM PDT 24
Finished Apr 23 01:55:25 PM PDT 24
Peak memory 208768 kb
Host smart-6f8f5b3c-4071-45cc-b8f0-f899dcf5c5b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154151949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3154151949
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2825452558
Short name T775
Test name
Test status
Simulation time 28983542 ps
CPU time 2.09 seconds
Started Apr 23 01:55:21 PM PDT 24
Finished Apr 23 01:55:24 PM PDT 24
Peak memory 208188 kb
Host smart-3c76242b-23b9-45e8-8423-08d2950465dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825452558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2825452558
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.862395024
Short name T801
Test name
Test status
Simulation time 80772656 ps
CPU time 2.29 seconds
Started Apr 23 01:55:29 PM PDT 24
Finished Apr 23 01:55:32 PM PDT 24
Peak memory 209620 kb
Host smart-e0e893df-e1fc-4ae8-8ea1-d97b2b16ee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862395024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.862395024
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3488697908
Short name T443
Test name
Test status
Simulation time 293880450 ps
CPU time 4.36 seconds
Started Apr 23 01:55:22 PM PDT 24
Finished Apr 23 01:55:27 PM PDT 24
Peak memory 206912 kb
Host smart-72305f74-6b1d-4519-a777-007b885e0b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488697908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3488697908
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2830136197
Short name T373
Test name
Test status
Simulation time 297393073 ps
CPU time 11.84 seconds
Started Apr 23 01:55:35 PM PDT 24
Finished Apr 23 01:55:50 PM PDT 24
Peak memory 215308 kb
Host smart-0a32e53e-e9e9-46f4-9bea-3c1dd550ff70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830136197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2830136197
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.580478925
Short name T444
Test name
Test status
Simulation time 567887625 ps
CPU time 4.09 seconds
Started Apr 23 01:55:19 PM PDT 24
Finished Apr 23 01:55:24 PM PDT 24
Peak memory 214080 kb
Host smart-87ff21f6-2b14-415f-8302-c4c4d0eb76da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580478925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.580478925
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3332351752
Short name T537
Test name
Test status
Simulation time 74880900 ps
CPU time 1.48 seconds
Started Apr 23 01:55:26 PM PDT 24
Finished Apr 23 01:55:28 PM PDT 24
Peak memory 209708 kb
Host smart-14390f30-6c12-4ffe-aa3c-7baba3cfe124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332351752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3332351752
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4000427896
Short name T224
Test name
Test status
Simulation time 233042647 ps
CPU time 12.43 seconds
Started Apr 23 01:55:24 PM PDT 24
Finished Apr 23 01:55:37 PM PDT 24
Peak memory 214868 kb
Host smart-7554d74b-834d-4f68-bde1-537bfc122729
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4000427896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4000427896
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3226102063
Short name T212
Test name
Test status
Simulation time 867396153 ps
CPU time 5.64 seconds
Started Apr 23 01:55:27 PM PDT 24
Finished Apr 23 01:55:33 PM PDT 24
Peak memory 209772 kb
Host smart-5e285f79-a3b0-4772-a84d-7a32852b47ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226102063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3226102063
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2784290373
Short name T184
Test name
Test status
Simulation time 1558336788 ps
CPU time 3.14 seconds
Started Apr 23 01:55:25 PM PDT 24
Finished Apr 23 01:55:29 PM PDT 24
Peak memory 208808 kb
Host smart-bba9e25b-74ab-43d5-8bbc-06da0a003ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784290373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2784290373
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2768799094
Short name T889
Test name
Test status
Simulation time 168624439 ps
CPU time 4.78 seconds
Started Apr 23 01:55:28 PM PDT 24
Finished Apr 23 01:55:33 PM PDT 24
Peak memory 214620 kb
Host smart-79957711-48c2-4357-bd2a-a271a86de49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768799094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2768799094
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.111932844
Short name T197
Test name
Test status
Simulation time 226219943 ps
CPU time 6.45 seconds
Started Apr 23 01:55:27 PM PDT 24
Finished Apr 23 01:55:34 PM PDT 24
Peak memory 210288 kb
Host smart-abef36cb-f207-4e9b-b1e9-0f76c893b781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111932844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.111932844
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3101634100
Short name T757
Test name
Test status
Simulation time 381537756 ps
CPU time 4.63 seconds
Started Apr 23 01:55:24 PM PDT 24
Finished Apr 23 01:55:29 PM PDT 24
Peak memory 218700 kb
Host smart-5c1fbec3-db98-45ca-9d95-94fd647cb345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101634100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3101634100
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1592737991
Short name T372
Test name
Test status
Simulation time 2168199022 ps
CPU time 30.41 seconds
Started Apr 23 01:55:29 PM PDT 24
Finished Apr 23 01:56:00 PM PDT 24
Peak memory 208444 kb
Host smart-070c0761-4fb4-4cd0-a9a3-66db33bccd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592737991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1592737991
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1450896734
Short name T605
Test name
Test status
Simulation time 84520917 ps
CPU time 2.02 seconds
Started Apr 23 01:55:23 PM PDT 24
Finished Apr 23 01:55:26 PM PDT 24
Peak memory 208600 kb
Host smart-31183f4d-b38c-4006-b35e-c6c6aaea61d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450896734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1450896734
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2756728964
Short name T709
Test name
Test status
Simulation time 130831426 ps
CPU time 2.5 seconds
Started Apr 23 01:55:25 PM PDT 24
Finished Apr 23 01:55:28 PM PDT 24
Peak memory 207032 kb
Host smart-c78ca1ea-2ddd-4918-b64c-d76ab4396f3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756728964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2756728964
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1344297510
Short name T626
Test name
Test status
Simulation time 334728846 ps
CPU time 3.49 seconds
Started Apr 23 01:55:22 PM PDT 24
Finished Apr 23 01:55:26 PM PDT 24
Peak memory 207048 kb
Host smart-104e7ac3-581e-4654-8dbe-da3ea45facd9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344297510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1344297510
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.139057571
Short name T469
Test name
Test status
Simulation time 424402741 ps
CPU time 5.27 seconds
Started Apr 23 01:55:23 PM PDT 24
Finished Apr 23 01:55:29 PM PDT 24
Peak memory 208204 kb
Host smart-c5ada756-190b-4cf5-b0ce-9b5875eed866
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139057571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.139057571
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.44248739
Short name T464
Test name
Test status
Simulation time 41200991 ps
CPU time 2.18 seconds
Started Apr 23 01:55:28 PM PDT 24
Finished Apr 23 01:55:31 PM PDT 24
Peak memory 209976 kb
Host smart-9f660cec-8306-42b2-8dad-e26828d90e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44248739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.44248739
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.929770236
Short name T561
Test name
Test status
Simulation time 276631011 ps
CPU time 3.59 seconds
Started Apr 23 01:55:25 PM PDT 24
Finished Apr 23 01:55:29 PM PDT 24
Peak memory 206720 kb
Host smart-c6879691-002b-4bcc-ac04-75b38fdec91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929770236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.929770236
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.584283392
Short name T330
Test name
Test status
Simulation time 234278403 ps
CPU time 3.99 seconds
Started Apr 23 01:55:33 PM PDT 24
Finished Apr 23 01:55:38 PM PDT 24
Peak memory 208232 kb
Host smart-596904b9-4930-44c0-a027-13bb6f3c0efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584283392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.584283392
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2161319114
Short name T135
Test name
Test status
Simulation time 716681729 ps
CPU time 4.11 seconds
Started Apr 23 01:55:35 PM PDT 24
Finished Apr 23 01:55:42 PM PDT 24
Peak memory 210648 kb
Host smart-5f8971c7-b827-4b59-ab1d-4aca3c866996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161319114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2161319114
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2414049782
Short name T892
Test name
Test status
Simulation time 31947412 ps
CPU time 0.75 seconds
Started Apr 23 01:55:31 PM PDT 24
Finished Apr 23 01:55:32 PM PDT 24
Peak memory 206080 kb
Host smart-fc7fd424-b9c3-46fa-a7af-bffcf10f5c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414049782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2414049782
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3379266210
Short name T325
Test name
Test status
Simulation time 130830839 ps
CPU time 3.32 seconds
Started Apr 23 01:55:28 PM PDT 24
Finished Apr 23 01:55:32 PM PDT 24
Peak memory 215380 kb
Host smart-56cdbc31-4be9-406b-ba9d-26af9e27325a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3379266210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3379266210
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.290073733
Short name T818
Test name
Test status
Simulation time 317594224 ps
CPU time 2.79 seconds
Started Apr 23 01:55:29 PM PDT 24
Finished Apr 23 01:55:32 PM PDT 24
Peak memory 214796 kb
Host smart-c9dcc1ff-1c79-4a01-a080-8e57e70b048f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290073733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.290073733
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.959920261
Short name T621
Test name
Test status
Simulation time 870262875 ps
CPU time 16.09 seconds
Started Apr 23 01:55:32 PM PDT 24
Finished Apr 23 01:55:48 PM PDT 24
Peak memory 209588 kb
Host smart-d9e30bcd-f720-4723-bbd6-61d5d88e73b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959920261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.959920261
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2964719845
Short name T94
Test name
Test status
Simulation time 183842295 ps
CPU time 5.04 seconds
Started Apr 23 01:55:28 PM PDT 24
Finished Apr 23 01:55:34 PM PDT 24
Peak memory 208856 kb
Host smart-e6710f18-059e-4ab8-9f89-c6464d3ba9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964719845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2964719845
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3646399193
Short name T313
Test name
Test status
Simulation time 277349503 ps
CPU time 4.43 seconds
Started Apr 23 01:55:32 PM PDT 24
Finished Apr 23 01:55:37 PM PDT 24
Peak memory 210532 kb
Host smart-eea86f13-29d4-489d-8669-ad8844762644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646399193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3646399193
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.1920153479
Short name T642
Test name
Test status
Simulation time 410049917 ps
CPU time 5.49 seconds
Started Apr 23 01:55:36 PM PDT 24
Finished Apr 23 01:55:44 PM PDT 24
Peak memory 214588 kb
Host smart-94d113cc-31df-4b5e-960f-371b82f213c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920153479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1920153479
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.295567441
Short name T641
Test name
Test status
Simulation time 159140009 ps
CPU time 3.76 seconds
Started Apr 23 01:55:29 PM PDT 24
Finished Apr 23 01:55:33 PM PDT 24
Peak memory 208720 kb
Host smart-fd306849-9796-48b7-9dc1-67b1fee2414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295567441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.295567441
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3100362115
Short name T827
Test name
Test status
Simulation time 91432922 ps
CPU time 3.98 seconds
Started Apr 23 01:55:28 PM PDT 24
Finished Apr 23 01:55:33 PM PDT 24
Peak memory 208776 kb
Host smart-70cb651d-3e34-4892-bbad-6558f619c163
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100362115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3100362115
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.487035546
Short name T2
Test name
Test status
Simulation time 113935721 ps
CPU time 2.3 seconds
Started Apr 23 01:55:27 PM PDT 24
Finished Apr 23 01:55:30 PM PDT 24
Peak memory 209020 kb
Host smart-c580c981-382a-43cc-ad4d-e844704dd286
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487035546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.487035546
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.295651867
Short name T397
Test name
Test status
Simulation time 243721666 ps
CPU time 2.39 seconds
Started Apr 23 01:55:29 PM PDT 24
Finished Apr 23 01:55:32 PM PDT 24
Peak memory 215804 kb
Host smart-1583e49d-6ef3-47ec-8a2e-599d5d492eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295651867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.295651867
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2275864455
Short name T686
Test name
Test status
Simulation time 3728309734 ps
CPU time 66.44 seconds
Started Apr 23 01:55:26 PM PDT 24
Finished Apr 23 01:56:33 PM PDT 24
Peak memory 208280 kb
Host smart-1a40bbf7-54b8-434d-85cc-0555c3e44963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275864455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2275864455
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.114129141
Short name T296
Test name
Test status
Simulation time 2118163539 ps
CPU time 15.97 seconds
Started Apr 23 01:55:31 PM PDT 24
Finished Apr 23 01:55:48 PM PDT 24
Peak memory 222716 kb
Host smart-62146271-dd9e-494c-bc1a-18237ba5a342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114129141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.114129141
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1501506570
Short name T83
Test name
Test status
Simulation time 894926103 ps
CPU time 6.52 seconds
Started Apr 23 01:55:30 PM PDT 24
Finished Apr 23 01:55:37 PM PDT 24
Peak memory 208160 kb
Host smart-d6c96c96-e3b2-4437-96b4-386c4d729f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501506570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1501506570
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3825067430
Short name T820
Test name
Test status
Simulation time 286252571 ps
CPU time 3.17 seconds
Started Apr 23 01:55:34 PM PDT 24
Finished Apr 23 01:55:40 PM PDT 24
Peak memory 210104 kb
Host smart-e8124da7-d307-4095-be7b-9a9adc47941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825067430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3825067430
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2381111701
Short name T446
Test name
Test status
Simulation time 38723991 ps
CPU time 0.84 seconds
Started Apr 23 01:55:37 PM PDT 24
Finished Apr 23 01:55:40 PM PDT 24
Peak memory 206128 kb
Host smart-d2b9c36b-54ad-480a-9004-b4eb23995110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381111701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2381111701
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2984638339
Short name T855
Test name
Test status
Simulation time 37549313 ps
CPU time 2.98 seconds
Started Apr 23 01:55:37 PM PDT 24
Finished Apr 23 01:55:42 PM PDT 24
Peak memory 215636 kb
Host smart-b74849d3-9f47-4b23-97e5-6ad7c773cae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2984638339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2984638339
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.127333453
Short name T454
Test name
Test status
Simulation time 407525895 ps
CPU time 4.11 seconds
Started Apr 23 01:55:32 PM PDT 24
Finished Apr 23 01:55:37 PM PDT 24
Peak memory 208896 kb
Host smart-684e75ab-9b2c-43f5-a789-c84bd9bdd2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127333453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.127333453
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.499434837
Short name T270
Test name
Test status
Simulation time 62024786 ps
CPU time 2.39 seconds
Started Apr 23 01:55:34 PM PDT 24
Finished Apr 23 01:55:39 PM PDT 24
Peak memory 214472 kb
Host smart-28cf81dd-d6e4-41d7-8195-7b5206e1f72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499434837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.499434837
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2001856459
Short name T25
Test name
Test status
Simulation time 441433056 ps
CPU time 6.2 seconds
Started Apr 23 01:55:34 PM PDT 24
Finished Apr 23 01:55:41 PM PDT 24
Peak memory 214564 kb
Host smart-23ee59eb-68a7-48f6-b874-a6c333c37d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001856459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2001856459
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3783449177
Short name T56
Test name
Test status
Simulation time 231970790 ps
CPU time 3.83 seconds
Started Apr 23 01:55:33 PM PDT 24
Finished Apr 23 01:55:38 PM PDT 24
Peak memory 209744 kb
Host smart-e649306e-3c55-4538-b673-e4a72cf4d872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783449177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3783449177
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4010887160
Short name T683
Test name
Test status
Simulation time 32878650 ps
CPU time 2.61 seconds
Started Apr 23 01:55:34 PM PDT 24
Finished Apr 23 01:55:38 PM PDT 24
Peak memory 208176 kb
Host smart-c26ac915-3c5c-4081-9ce4-e8ba0cf9a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010887160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4010887160
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3731052662
Short name T806
Test name
Test status
Simulation time 3875917445 ps
CPU time 66.02 seconds
Started Apr 23 01:55:31 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 208136 kb
Host smart-c20b152e-3f1b-479e-814c-ad25dc73afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731052662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3731052662
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2888846226
Short name T436
Test name
Test status
Simulation time 357551727 ps
CPU time 3.36 seconds
Started Apr 23 01:55:33 PM PDT 24
Finished Apr 23 01:55:38 PM PDT 24
Peak memory 206996 kb
Host smart-da7fcd19-4042-4d05-96f4-0ca88cb537f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888846226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2888846226
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.541308838
Short name T853
Test name
Test status
Simulation time 37040537 ps
CPU time 2.69 seconds
Started Apr 23 01:55:31 PM PDT 24
Finished Apr 23 01:55:35 PM PDT 24
Peak memory 208808 kb
Host smart-3010aa94-b76f-48df-8791-4212439d5824
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541308838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.541308838
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.649807223
Short name T316
Test name
Test status
Simulation time 111125496 ps
CPU time 3.63 seconds
Started Apr 23 01:55:33 PM PDT 24
Finished Apr 23 01:55:38 PM PDT 24
Peak memory 208896 kb
Host smart-19a3603c-f4d3-4957-892e-939bd22c3961
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649807223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.649807223
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1526578452
Short name T276
Test name
Test status
Simulation time 377424224 ps
CPU time 2.95 seconds
Started Apr 23 01:55:34 PM PDT 24
Finished Apr 23 01:55:39 PM PDT 24
Peak memory 208676 kb
Host smart-53ef35ba-1cda-49a4-a8e3-563ffcae3ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526578452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1526578452
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.10869205
Short name T18
Test name
Test status
Simulation time 187052855 ps
CPU time 4.44 seconds
Started Apr 23 01:55:29 PM PDT 24
Finished Apr 23 01:55:34 PM PDT 24
Peak memory 207044 kb
Host smart-36fa6055-625a-4229-b015-2495fcbcfcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10869205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.10869205
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3290197853
Short name T177
Test name
Test status
Simulation time 4957993057 ps
CPU time 29.43 seconds
Started Apr 23 01:55:31 PM PDT 24
Finished Apr 23 01:56:02 PM PDT 24
Peak memory 221224 kb
Host smart-136d403d-73f4-48de-ab25-efdd01558b3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290197853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3290197853
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1955110610
Short name T238
Test name
Test status
Simulation time 894539577 ps
CPU time 28.65 seconds
Started Apr 23 01:55:34 PM PDT 24
Finished Apr 23 01:56:05 PM PDT 24
Peak memory 218808 kb
Host smart-69ed7d58-d7c6-48dc-81e6-abe9f346d449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955110610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1955110610
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1072733406
Short name T691
Test name
Test status
Simulation time 21979076 ps
CPU time 0.86 seconds
Started Apr 23 01:55:42 PM PDT 24
Finished Apr 23 01:55:43 PM PDT 24
Peak memory 206144 kb
Host smart-9908ca2e-8b08-4e5b-80e3-47aa17c205dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072733406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1072733406
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.4162246857
Short name T329
Test name
Test status
Simulation time 452081152 ps
CPU time 3.68 seconds
Started Apr 23 01:55:35 PM PDT 24
Finished Apr 23 01:55:42 PM PDT 24
Peak memory 214496 kb
Host smart-04fa56e6-7269-4d1d-879a-92df5f2c337b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162246857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.4162246857
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3863168154
Short name T634
Test name
Test status
Simulation time 97961265 ps
CPU time 1.98 seconds
Started Apr 23 01:55:38 PM PDT 24
Finished Apr 23 01:55:42 PM PDT 24
Peak memory 209476 kb
Host smart-e2a10c73-c7f9-435e-a886-902dfa37577a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863168154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3863168154
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2586435581
Short name T533
Test name
Test status
Simulation time 74711391 ps
CPU time 3.53 seconds
Started Apr 23 01:55:37 PM PDT 24
Finished Apr 23 01:55:43 PM PDT 24
Peak memory 208256 kb
Host smart-1b177bda-93c5-4a82-932c-63a907877577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586435581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2586435581
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.51695001
Short name T271
Test name
Test status
Simulation time 77440516 ps
CPU time 3.44 seconds
Started Apr 23 01:55:34 PM PDT 24
Finished Apr 23 01:55:39 PM PDT 24
Peak memory 209448 kb
Host smart-7345c601-035e-455f-ae88-df4de970019d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51695001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.51695001
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3990971480
Short name T87
Test name
Test status
Simulation time 252731084 ps
CPU time 8.1 seconds
Started Apr 23 01:55:39 PM PDT 24
Finished Apr 23 01:55:48 PM PDT 24
Peak memory 211308 kb
Host smart-a7a78e41-ddb3-47a7-9c8e-77a1a7eb02e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990971480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3990971480
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.963152660
Short name T211
Test name
Test status
Simulation time 113303605 ps
CPU time 5.09 seconds
Started Apr 23 01:55:34 PM PDT 24
Finished Apr 23 01:55:42 PM PDT 24
Peak memory 210644 kb
Host smart-a7286617-905d-45e0-bcc4-6642c720c7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963152660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.963152660
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3320041508
Short name T418
Test name
Test status
Simulation time 295447160 ps
CPU time 10.92 seconds
Started Apr 23 01:55:35 PM PDT 24
Finished Apr 23 01:55:49 PM PDT 24
Peak memory 208292 kb
Host smart-c4259c40-e44e-4156-a53c-88ef8d556853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320041508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3320041508
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4169610675
Short name T334
Test name
Test status
Simulation time 402422229 ps
CPU time 7.28 seconds
Started Apr 23 01:55:35 PM PDT 24
Finished Apr 23 01:55:46 PM PDT 24
Peak memory 207012 kb
Host smart-b5239a9e-121b-4e3a-af3b-8266bc3e09a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169610675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4169610675
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.4145413232
Short name T760
Test name
Test status
Simulation time 565578600 ps
CPU time 5.06 seconds
Started Apr 23 01:55:36 PM PDT 24
Finished Apr 23 01:55:44 PM PDT 24
Peak memory 208728 kb
Host smart-6fc12c1f-ddf7-4063-aa24-83e3dff107c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145413232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.4145413232
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.4182109123
Short name T307
Test name
Test status
Simulation time 91608259 ps
CPU time 2.65 seconds
Started Apr 23 01:55:35 PM PDT 24
Finished Apr 23 01:55:40 PM PDT 24
Peak memory 207336 kb
Host smart-ce7a32d0-6086-4482-8a9c-3dab0784c936
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182109123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4182109123
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1662388970
Short name T402
Test name
Test status
Simulation time 148097283 ps
CPU time 2.64 seconds
Started Apr 23 01:55:35 PM PDT 24
Finished Apr 23 01:55:41 PM PDT 24
Peak memory 208828 kb
Host smart-0f3ddf52-a668-49f9-8913-22fa9f513555
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662388970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1662388970
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.73363384
Short name T280
Test name
Test status
Simulation time 128191591 ps
CPU time 2.3 seconds
Started Apr 23 01:55:42 PM PDT 24
Finished Apr 23 01:55:44 PM PDT 24
Peak memory 208252 kb
Host smart-0f1d09f8-0f7f-4a5d-aa45-8e73e3d14df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73363384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.73363384
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2015843252
Short name T833
Test name
Test status
Simulation time 248863321 ps
CPU time 3.07 seconds
Started Apr 23 01:55:37 PM PDT 24
Finished Apr 23 01:55:42 PM PDT 24
Peak memory 206808 kb
Host smart-b076df81-78d3-4d14-ae93-32fb29e0e958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015843252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2015843252
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3841973056
Short name T869
Test name
Test status
Simulation time 3981488570 ps
CPU time 31.1 seconds
Started Apr 23 01:55:36 PM PDT 24
Finished Apr 23 01:56:10 PM PDT 24
Peak memory 218692 kb
Host smart-8bfbff70-4d70-4292-8e73-45d163592083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841973056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3841973056
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.917750988
Short name T130
Test name
Test status
Simulation time 53749036 ps
CPU time 1.87 seconds
Started Apr 23 01:55:40 PM PDT 24
Finished Apr 23 01:55:43 PM PDT 24
Peak memory 210272 kb
Host smart-e5fd5381-d683-45f0-a2c3-a0c4ed2c1508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917750988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.917750988
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1306873786
Short name T499
Test name
Test status
Simulation time 11411886 ps
CPU time 0.85 seconds
Started Apr 23 01:55:47 PM PDT 24
Finished Apr 23 01:55:48 PM PDT 24
Peak memory 206112 kb
Host smart-caf344ad-4f8a-4454-9bd2-8f653d822adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306873786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1306873786
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3724136895
Short name T416
Test name
Test status
Simulation time 160185059 ps
CPU time 3.74 seconds
Started Apr 23 01:55:43 PM PDT 24
Finished Apr 23 01:55:48 PM PDT 24
Peak memory 214504 kb
Host smart-ae168413-21f4-470a-999d-b1fb1997670c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3724136895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3724136895
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4205521251
Short name T381
Test name
Test status
Simulation time 558930708 ps
CPU time 20.22 seconds
Started Apr 23 01:55:48 PM PDT 24
Finished Apr 23 01:56:09 PM PDT 24
Peak memory 222816 kb
Host smart-74470bb1-4286-4e96-9728-75d352c943e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205521251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4205521251
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1180109390
Short name T750
Test name
Test status
Simulation time 87496866 ps
CPU time 2.44 seconds
Started Apr 23 01:55:42 PM PDT 24
Finished Apr 23 01:55:45 PM PDT 24
Peak memory 209896 kb
Host smart-1b0f9d42-f265-480c-ba64-3de8a430f4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180109390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1180109390
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.571033046
Short name T610
Test name
Test status
Simulation time 504341875 ps
CPU time 5.51 seconds
Started Apr 23 01:55:46 PM PDT 24
Finished Apr 23 01:55:52 PM PDT 24
Peak memory 214592 kb
Host smart-eadd41fa-6dca-4737-9076-3569cfaf8972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571033046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.571033046
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_random.1758430338
Short name T473
Test name
Test status
Simulation time 66747662 ps
CPU time 2.65 seconds
Started Apr 23 01:55:43 PM PDT 24
Finished Apr 23 01:55:46 PM PDT 24
Peak memory 208316 kb
Host smart-2beba511-69e6-4113-9756-d57dd0883264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758430338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1758430338
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3062261688
Short name T543
Test name
Test status
Simulation time 89213496 ps
CPU time 1.87 seconds
Started Apr 23 01:55:43 PM PDT 24
Finished Apr 23 01:55:45 PM PDT 24
Peak memory 207352 kb
Host smart-8af58463-a1d3-4ca1-a115-792ac57639f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062261688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3062261688
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.367242592
Short name T719
Test name
Test status
Simulation time 1977641283 ps
CPU time 10.01 seconds
Started Apr 23 01:55:44 PM PDT 24
Finished Apr 23 01:55:54 PM PDT 24
Peak memory 208120 kb
Host smart-cda27135-2434-4f37-b8c3-ca278fa853ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367242592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.367242592
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.733009152
Short name T794
Test name
Test status
Simulation time 1590017327 ps
CPU time 3.81 seconds
Started Apr 23 01:55:41 PM PDT 24
Finished Apr 23 01:55:45 PM PDT 24
Peak memory 208700 kb
Host smart-69442197-445f-4b49-9dfd-b4c5df16be88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733009152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.733009152
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2210463910
Short name T763
Test name
Test status
Simulation time 241791905 ps
CPU time 7.04 seconds
Started Apr 23 01:55:42 PM PDT 24
Finished Apr 23 01:55:50 PM PDT 24
Peak memory 208060 kb
Host smart-32bd0f28-d579-4845-888a-da1c0fcdc69b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210463910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2210463910
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.124373867
Short name T583
Test name
Test status
Simulation time 351547376 ps
CPU time 8.46 seconds
Started Apr 23 01:55:45 PM PDT 24
Finished Apr 23 01:55:54 PM PDT 24
Peak memory 214660 kb
Host smart-d41de4b2-d504-463e-a219-72b72b218777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124373867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.124373867
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.521209987
Short name T432
Test name
Test status
Simulation time 356400858 ps
CPU time 10.32 seconds
Started Apr 23 01:55:41 PM PDT 24
Finished Apr 23 01:55:52 PM PDT 24
Peak memory 208640 kb
Host smart-279b27e3-bc83-4fe9-aa9f-89d96623eb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521209987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.521209987
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3032180275
Short name T441
Test name
Test status
Simulation time 326077702 ps
CPU time 4.29 seconds
Started Apr 23 01:55:43 PM PDT 24
Finished Apr 23 01:55:47 PM PDT 24
Peak memory 214520 kb
Host smart-86ed4a97-7234-4b83-ad7d-dcb652a9f2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032180275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3032180275
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2282671391
Short name T129
Test name
Test status
Simulation time 90081424 ps
CPU time 0.74 seconds
Started Apr 23 01:55:49 PM PDT 24
Finished Apr 23 01:55:50 PM PDT 24
Peak memory 206144 kb
Host smart-f75b10bd-0615-4c65-96c0-10e3bd7cff78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282671391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2282671391
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2760504217
Short name T299
Test name
Test status
Simulation time 249252293 ps
CPU time 3.74 seconds
Started Apr 23 01:55:43 PM PDT 24
Finished Apr 23 01:55:47 PM PDT 24
Peak memory 214504 kb
Host smart-6e3c4d11-c2ad-4310-a6c1-5149f7bf403d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760504217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2760504217
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.4040239701
Short name T214
Test name
Test status
Simulation time 385960290 ps
CPU time 5.13 seconds
Started Apr 23 01:55:49 PM PDT 24
Finished Apr 23 01:55:54 PM PDT 24
Peak memory 222244 kb
Host smart-5633d064-9409-459f-b19c-aa7957da3e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040239701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4040239701
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3149595527
Short name T848
Test name
Test status
Simulation time 79807310 ps
CPU time 1.53 seconds
Started Apr 23 01:55:48 PM PDT 24
Finished Apr 23 01:55:50 PM PDT 24
Peak memory 207424 kb
Host smart-bf452f27-eba1-4959-add9-43fcb250464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149595527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3149595527
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1491948705
Short name T606
Test name
Test status
Simulation time 657262132 ps
CPU time 3.53 seconds
Started Apr 23 01:55:49 PM PDT 24
Finished Apr 23 01:55:53 PM PDT 24
Peak memory 214544 kb
Host smart-e6a1660d-5d15-4df2-b50d-c733e27646e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491948705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1491948705
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2480944071
Short name T312
Test name
Test status
Simulation time 128188254 ps
CPU time 3.88 seconds
Started Apr 23 01:55:48 PM PDT 24
Finished Apr 23 01:55:52 PM PDT 24
Peak memory 211432 kb
Host smart-e5495f58-703a-4f5d-a6b6-81fc1710f8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480944071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2480944071
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1670364197
Short name T878
Test name
Test status
Simulation time 89162625 ps
CPU time 3.11 seconds
Started Apr 23 01:55:48 PM PDT 24
Finished Apr 23 01:55:52 PM PDT 24
Peak memory 218728 kb
Host smart-fb278587-f9cd-49fa-b0de-05de67aaaf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670364197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1670364197
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3925282774
Short name T735
Test name
Test status
Simulation time 965011711 ps
CPU time 25.43 seconds
Started Apr 23 01:55:43 PM PDT 24
Finished Apr 23 01:56:09 PM PDT 24
Peak memory 214620 kb
Host smart-a0e6d177-ab48-44c2-92a7-3edde7309f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925282774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3925282774
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.484982812
Short name T731
Test name
Test status
Simulation time 103347717 ps
CPU time 4.28 seconds
Started Apr 23 01:55:51 PM PDT 24
Finished Apr 23 01:55:56 PM PDT 24
Peak memory 208688 kb
Host smart-e0917634-4b1d-49f5-8c6e-1bd3d906f466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484982812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.484982812
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3501574101
Short name T492
Test name
Test status
Simulation time 451187531 ps
CPU time 9.79 seconds
Started Apr 23 01:55:48 PM PDT 24
Finished Apr 23 01:55:58 PM PDT 24
Peak memory 208404 kb
Host smart-127de741-cb31-4a97-b34d-edf1a76c08d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501574101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3501574101
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3262367537
Short name T886
Test name
Test status
Simulation time 3193843955 ps
CPU time 30.02 seconds
Started Apr 23 01:55:44 PM PDT 24
Finished Apr 23 01:56:15 PM PDT 24
Peak memory 208888 kb
Host smart-47b22894-4f21-43b1-a745-74d28f13caaa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262367537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3262367537
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.330783425
Short name T580
Test name
Test status
Simulation time 104407360 ps
CPU time 3.93 seconds
Started Apr 23 01:55:45 PM PDT 24
Finished Apr 23 01:55:50 PM PDT 24
Peak memory 207696 kb
Host smart-6e9d678c-dd3c-49d2-a87b-71ae59dc59ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330783425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.330783425
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1030875547
Short name T572
Test name
Test status
Simulation time 29337931 ps
CPU time 1.75 seconds
Started Apr 23 01:55:49 PM PDT 24
Finished Apr 23 01:55:51 PM PDT 24
Peak memory 218440 kb
Host smart-b8a4d2cd-9893-49c0-b7eb-43a8e88abb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030875547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1030875547
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1896343800
Short name T190
Test name
Test status
Simulation time 61280858 ps
CPU time 2.35 seconds
Started Apr 23 01:55:48 PM PDT 24
Finished Apr 23 01:55:51 PM PDT 24
Peak memory 206756 kb
Host smart-fda8f01a-09d1-4a59-a98e-288134c8997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896343800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1896343800
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.579356355
Short name T279
Test name
Test status
Simulation time 27699095192 ps
CPU time 266.51 seconds
Started Apr 23 01:55:48 PM PDT 24
Finished Apr 23 02:00:15 PM PDT 24
Peak memory 222772 kb
Host smart-9ecb7b06-d1ea-402b-a090-296e38b898ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579356355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.579356355
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1222231053
Short name T800
Test name
Test status
Simulation time 187733096 ps
CPU time 4.47 seconds
Started Apr 23 01:55:45 PM PDT 24
Finished Apr 23 01:55:50 PM PDT 24
Peak memory 209628 kb
Host smart-3f1b586c-4023-49ab-a941-90bb06290c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222231053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1222231053
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2688248898
Short name T570
Test name
Test status
Simulation time 52266711 ps
CPU time 1.89 seconds
Started Apr 23 01:55:48 PM PDT 24
Finished Apr 23 01:55:50 PM PDT 24
Peak memory 210424 kb
Host smart-68dd91e3-390e-4989-9036-9e0c591c4688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688248898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2688248898
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.754332150
Short name T742
Test name
Test status
Simulation time 22194146 ps
CPU time 0.86 seconds
Started Apr 23 01:55:51 PM PDT 24
Finished Apr 23 01:55:52 PM PDT 24
Peak memory 206184 kb
Host smart-9266e64e-125f-4745-ae2b-9848d65d05b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754332150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.754332150
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2210626322
Short name T391
Test name
Test status
Simulation time 34483188 ps
CPU time 2.76 seconds
Started Apr 23 01:55:51 PM PDT 24
Finished Apr 23 01:55:54 PM PDT 24
Peak memory 214732 kb
Host smart-20f70ab7-24f0-409c-a71b-96c758cb8fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2210626322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2210626322
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1888226289
Short name T68
Test name
Test status
Simulation time 44383565 ps
CPU time 2.17 seconds
Started Apr 23 01:55:51 PM PDT 24
Finished Apr 23 01:55:54 PM PDT 24
Peak memory 220240 kb
Host smart-399cc32a-66e7-4e3a-bcdc-39cd884b9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888226289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1888226289
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1845797690
Short name T451
Test name
Test status
Simulation time 67421874 ps
CPU time 1.92 seconds
Started Apr 23 01:55:54 PM PDT 24
Finished Apr 23 01:55:56 PM PDT 24
Peak memory 209940 kb
Host smart-634c539b-e972-4556-8d43-df2b779aca3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845797690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1845797690
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1986381671
Short name T89
Test name
Test status
Simulation time 446269122 ps
CPU time 7.88 seconds
Started Apr 23 01:55:51 PM PDT 24
Finished Apr 23 01:55:59 PM PDT 24
Peak memory 214544 kb
Host smart-acd052c5-f409-426e-bcae-953cd01a186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986381671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1986381671
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.901732472
Short name T205
Test name
Test status
Simulation time 430332481 ps
CPU time 2.19 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:02 PM PDT 24
Peak memory 219376 kb
Host smart-d9d7d58e-1d35-4b77-ab52-0560a03d55e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901732472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.901732472
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.867990026
Short name T349
Test name
Test status
Simulation time 384439128 ps
CPU time 5.03 seconds
Started Apr 23 01:55:49 PM PDT 24
Finished Apr 23 01:55:55 PM PDT 24
Peak memory 208572 kb
Host smart-300235ce-67f7-4086-8aa8-981f4c2515b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867990026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.867990026
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2347277230
Short name T724
Test name
Test status
Simulation time 492560219 ps
CPU time 12.16 seconds
Started Apr 23 01:55:47 PM PDT 24
Finished Apr 23 01:56:00 PM PDT 24
Peak memory 207964 kb
Host smart-27a6f6e7-d1b3-47c4-921a-dff70e73322d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347277230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2347277230
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.628919531
Short name T365
Test name
Test status
Simulation time 270831822 ps
CPU time 4.69 seconds
Started Apr 23 01:55:58 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 209124 kb
Host smart-64de4d9a-2eca-4321-a00c-a37690702c71
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628919531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.628919531
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2328441579
Short name T274
Test name
Test status
Simulation time 97474266 ps
CPU time 2.23 seconds
Started Apr 23 01:55:49 PM PDT 24
Finished Apr 23 01:55:52 PM PDT 24
Peak memory 208752 kb
Host smart-6eefb2af-ffad-403e-8fa0-c2a7653b1d79
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328441579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2328441579
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1712770484
Short name T649
Test name
Test status
Simulation time 1158637020 ps
CPU time 28.87 seconds
Started Apr 23 01:55:47 PM PDT 24
Finished Apr 23 01:56:16 PM PDT 24
Peak memory 208272 kb
Host smart-9222fcb7-bf67-4198-a174-9176e51e40f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712770484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1712770484
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1627171746
Short name T587
Test name
Test status
Simulation time 18658521 ps
CPU time 1.61 seconds
Started Apr 23 01:55:53 PM PDT 24
Finished Apr 23 01:55:55 PM PDT 24
Peak memory 207932 kb
Host smart-7ffe404e-4689-4769-b9fd-43c52930d3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627171746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1627171746
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3057034470
Short name T635
Test name
Test status
Simulation time 639137751 ps
CPU time 4.85 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 208332 kb
Host smart-53817b10-92ba-43aa-a7c7-902fc7814223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057034470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3057034470
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3793577542
Short name T327
Test name
Test status
Simulation time 1547701137 ps
CPU time 40.46 seconds
Started Apr 23 01:55:54 PM PDT 24
Finished Apr 23 01:56:35 PM PDT 24
Peak memory 221520 kb
Host smart-35a48808-5b40-48d1-83eb-5652bbb22085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793577542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3793577542
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3168368355
Short name T785
Test name
Test status
Simulation time 414895254 ps
CPU time 8.33 seconds
Started Apr 23 01:55:51 PM PDT 24
Finished Apr 23 01:56:00 PM PDT 24
Peak memory 219220 kb
Host smart-b6ae7fcd-07d5-4120-bab6-e74363bdb04a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168368355 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3168368355
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1896693954
Short name T569
Test name
Test status
Simulation time 346320236 ps
CPU time 4.24 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 210480 kb
Host smart-f7a1cf14-c9ce-470f-8b18-d7ff19fe9a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896693954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1896693954
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3829574185
Short name T53
Test name
Test status
Simulation time 61849473 ps
CPU time 1.42 seconds
Started Apr 23 01:55:51 PM PDT 24
Finished Apr 23 01:55:53 PM PDT 24
Peak memory 210192 kb
Host smart-b1169df3-c7e6-4091-bbed-e36bf6524343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829574185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3829574185
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2001469238
Short name T705
Test name
Test status
Simulation time 17541452 ps
CPU time 0.75 seconds
Started Apr 23 01:55:55 PM PDT 24
Finished Apr 23 01:55:56 PM PDT 24
Peak memory 206080 kb
Host smart-a3d8042f-843b-4c92-9792-ccd862b84283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001469238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2001469238
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3919312819
Short name T275
Test name
Test status
Simulation time 232685097 ps
CPU time 4.58 seconds
Started Apr 23 01:55:52 PM PDT 24
Finished Apr 23 01:55:57 PM PDT 24
Peak memory 215576 kb
Host smart-7c112858-f2b0-4eb8-b7e4-b5e9f39fc190
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3919312819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3919312819
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.514747272
Short name T74
Test name
Test status
Simulation time 61906405 ps
CPU time 1.83 seconds
Started Apr 23 01:55:51 PM PDT 24
Finished Apr 23 01:55:54 PM PDT 24
Peak memory 207616 kb
Host smart-afb12a22-3389-4b1e-9708-81efada547c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514747272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.514747272
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2456043480
Short name T344
Test name
Test status
Simulation time 125140830 ps
CPU time 5.12 seconds
Started Apr 23 01:55:57 PM PDT 24
Finished Apr 23 01:56:03 PM PDT 24
Peak memory 209604 kb
Host smart-f1a7638f-0fa7-462f-8502-6c50387bd67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456043480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2456043480
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2482097294
Short name T265
Test name
Test status
Simulation time 205725599 ps
CPU time 5.22 seconds
Started Apr 23 01:55:57 PM PDT 24
Finished Apr 23 01:56:03 PM PDT 24
Peak memory 211092 kb
Host smart-a215e6c7-7641-4c29-9e85-bf13967d04bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482097294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2482097294
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4276347350
Short name T213
Test name
Test status
Simulation time 570057164 ps
CPU time 17.21 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:17 PM PDT 24
Peak memory 220596 kb
Host smart-73bd6f18-fa7d-43bf-a95a-6dfbde04f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276347350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4276347350
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1130209776
Short name T769
Test name
Test status
Simulation time 300767048 ps
CPU time 3.11 seconds
Started Apr 23 01:55:50 PM PDT 24
Finished Apr 23 01:55:54 PM PDT 24
Peak memory 207940 kb
Host smart-cb33540c-3617-4631-83e9-6e4540e7a08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130209776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1130209776
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.45958800
Short name T301
Test name
Test status
Simulation time 222197805 ps
CPU time 5.07 seconds
Started Apr 23 01:55:51 PM PDT 24
Finished Apr 23 01:55:56 PM PDT 24
Peak memory 207012 kb
Host smart-49837c79-6194-45d4-912f-e1b790ba3624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45958800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.45958800
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.931023175
Short name T767
Test name
Test status
Simulation time 33303817 ps
CPU time 2.28 seconds
Started Apr 23 01:55:54 PM PDT 24
Finished Apr 23 01:55:57 PM PDT 24
Peak memory 207008 kb
Host smart-32e895db-e430-4fcb-8c2a-0c3ac3d59be4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931023175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.931023175
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.427632437
Short name T545
Test name
Test status
Simulation time 79830267 ps
CPU time 3.61 seconds
Started Apr 23 01:55:53 PM PDT 24
Finished Apr 23 01:55:57 PM PDT 24
Peak memory 208420 kb
Host smart-ab1cdf82-44f1-4736-8e8d-c660df9f9dd4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427632437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.427632437
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3007648003
Short name T172
Test name
Test status
Simulation time 21179117 ps
CPU time 1.76 seconds
Started Apr 23 01:55:58 PM PDT 24
Finished Apr 23 01:56:01 PM PDT 24
Peak memory 207092 kb
Host smart-5c4038cf-aa3e-4cc1-b821-fb1652d080bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007648003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3007648003
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3862069294
Short name T524
Test name
Test status
Simulation time 192017137 ps
CPU time 2.73 seconds
Started Apr 23 01:55:53 PM PDT 24
Finished Apr 23 01:55:56 PM PDT 24
Peak memory 216236 kb
Host smart-80c03814-fb48-4acb-9e3c-a3a8c2a3beff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862069294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3862069294
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3248064119
Short name T528
Test name
Test status
Simulation time 1990955197 ps
CPU time 47.09 seconds
Started Apr 23 01:55:50 PM PDT 24
Finished Apr 23 01:56:37 PM PDT 24
Peak memory 208912 kb
Host smart-7e979a99-c9b5-4ba2-8a24-5d6584f68513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248064119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3248064119
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.216864113
Short name T64
Test name
Test status
Simulation time 504281270 ps
CPU time 10.2 seconds
Started Apr 23 01:55:57 PM PDT 24
Finished Apr 23 01:56:08 PM PDT 24
Peak memory 219912 kb
Host smart-e5e72432-f820-4175-9b7d-e9679bf6e1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216864113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.216864113
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1854676203
Short name T332
Test name
Test status
Simulation time 1024652556 ps
CPU time 10.91 seconds
Started Apr 23 01:55:53 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 214524 kb
Host smart-9bd778ab-72a6-4bbe-849e-c8457e464775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854676203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1854676203
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2356263464
Short name T826
Test name
Test status
Simulation time 199747473 ps
CPU time 5.45 seconds
Started Apr 23 01:55:55 PM PDT 24
Finished Apr 23 01:56:01 PM PDT 24
Peak memory 211068 kb
Host smart-cf2950b1-33e8-4157-b0ea-5d8f40f951e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356263464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2356263464
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3171657882
Short name T426
Test name
Test status
Simulation time 15267261 ps
CPU time 0.72 seconds
Started Apr 23 01:55:57 PM PDT 24
Finished Apr 23 01:55:58 PM PDT 24
Peak memory 206104 kb
Host smart-11ef589a-0d6b-44ac-b3f7-c986ce6e8b76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171657882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3171657882
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2109335035
Short name T509
Test name
Test status
Simulation time 27596839 ps
CPU time 1.65 seconds
Started Apr 23 01:55:58 PM PDT 24
Finished Apr 23 01:56:00 PM PDT 24
Peak memory 207552 kb
Host smart-39daf049-e65e-433d-90cb-b22050c21869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109335035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2109335035
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.188502138
Short name T258
Test name
Test status
Simulation time 2373687089 ps
CPU time 8.43 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:08 PM PDT 24
Peak memory 209532 kb
Host smart-a17d437d-fc3b-4303-ab10-aceb73f7de2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188502138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.188502138
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3345123218
Short name T468
Test name
Test status
Simulation time 43337252 ps
CPU time 2.9 seconds
Started Apr 23 01:55:57 PM PDT 24
Finished Apr 23 01:56:01 PM PDT 24
Peak memory 214532 kb
Host smart-f5a4a2c7-a8d8-45e3-bf17-dd4fbe8350f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345123218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3345123218
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.552602483
Short name T564
Test name
Test status
Simulation time 100161058 ps
CPU time 3.37 seconds
Started Apr 23 01:55:58 PM PDT 24
Finished Apr 23 01:56:02 PM PDT 24
Peak memory 208320 kb
Host smart-c5d3447e-316e-49af-8bf6-1e265217098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552602483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.552602483
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3094767786
Short name T132
Test name
Test status
Simulation time 344647493 ps
CPU time 9.62 seconds
Started Apr 23 01:55:56 PM PDT 24
Finished Apr 23 01:56:06 PM PDT 24
Peak memory 208544 kb
Host smart-4d7f1435-12ef-4f01-87a0-e50ca9c0a99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094767786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3094767786
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2078156281
Short name T462
Test name
Test status
Simulation time 345099834 ps
CPU time 5.49 seconds
Started Apr 23 01:55:54 PM PDT 24
Finished Apr 23 01:56:00 PM PDT 24
Peak memory 209052 kb
Host smart-32b1a918-f8f0-4e65-816d-62724ed5aba8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078156281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2078156281
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3106015588
Short name T291
Test name
Test status
Simulation time 230623566 ps
CPU time 5.03 seconds
Started Apr 23 01:55:54 PM PDT 24
Finished Apr 23 01:56:00 PM PDT 24
Peak memory 208816 kb
Host smart-826a70b7-05c3-4300-a2f0-d6d0b9615994
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106015588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3106015588
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.72502567
Short name T105
Test name
Test status
Simulation time 158160818 ps
CPU time 2.46 seconds
Started Apr 23 01:55:55 PM PDT 24
Finished Apr 23 01:55:58 PM PDT 24
Peak memory 207000 kb
Host smart-90d97248-a65e-4550-9b65-083e0746ad40
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72502567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.72502567
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1990224952
Short name T678
Test name
Test status
Simulation time 994375455 ps
CPU time 3.92 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 214588 kb
Host smart-cc92902b-bf24-4154-b7c5-d3ac57f1cc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990224952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1990224952
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3191709029
Short name T433
Test name
Test status
Simulation time 125483669 ps
CPU time 2.4 seconds
Started Apr 23 01:55:54 PM PDT 24
Finished Apr 23 01:55:57 PM PDT 24
Peak memory 207004 kb
Host smart-a0ae13e4-3733-48af-b313-73060df8a478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191709029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3191709029
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1448962200
Short name T488
Test name
Test status
Simulation time 296849314 ps
CPU time 4 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 216540 kb
Host smart-fccd2d66-caa9-430b-a5f3-9fc3f0e547db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448962200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1448962200
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3327878153
Short name T872
Test name
Test status
Simulation time 14341266 ps
CPU time 0.82 seconds
Started Apr 23 01:54:51 PM PDT 24
Finished Apr 23 01:54:52 PM PDT 24
Peak memory 206220 kb
Host smart-aa9ae96c-2006-4969-ade3-d2e5bfb7afc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327878153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3327878153
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.336718544
Short name T655
Test name
Test status
Simulation time 202057454 ps
CPU time 3.2 seconds
Started Apr 23 01:54:47 PM PDT 24
Finished Apr 23 01:54:50 PM PDT 24
Peak memory 209228 kb
Host smart-25189ebc-1c53-40f1-99c8-addbb07fae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336718544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.336718544
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.703431905
Short name T679
Test name
Test status
Simulation time 86795110 ps
CPU time 2.46 seconds
Started Apr 23 01:54:50 PM PDT 24
Finished Apr 23 01:54:53 PM PDT 24
Peak memory 210128 kb
Host smart-d07d4f37-807e-4e66-8b0c-67cb0c781281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703431905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.703431905
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1848024030
Short name T612
Test name
Test status
Simulation time 5703375760 ps
CPU time 39.82 seconds
Started Apr 23 01:54:46 PM PDT 24
Finished Apr 23 01:55:26 PM PDT 24
Peak memory 209828 kb
Host smart-50609449-285f-405a-92b3-534fcb22445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848024030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1848024030
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2417568841
Short name T546
Test name
Test status
Simulation time 95199565 ps
CPU time 2.76 seconds
Started Apr 23 01:54:44 PM PDT 24
Finished Apr 23 01:54:48 PM PDT 24
Peak memory 215536 kb
Host smart-3ee937f2-acc6-4af9-b974-a36bc8f2e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417568841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2417568841
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3087352188
Short name T628
Test name
Test status
Simulation time 587045347 ps
CPU time 7.99 seconds
Started Apr 23 01:54:48 PM PDT 24
Finished Apr 23 01:54:57 PM PDT 24
Peak memory 209964 kb
Host smart-c14bacce-4ee9-4a10-a206-dfc780219bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087352188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3087352188
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3263686468
Short name T790
Test name
Test status
Simulation time 592008931 ps
CPU time 8.62 seconds
Started Apr 23 01:54:43 PM PDT 24
Finished Apr 23 01:54:53 PM PDT 24
Peak memory 208664 kb
Host smart-c8fbd84f-0a8f-48a6-b6f4-98576cf23568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263686468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3263686468
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2723650136
Short name T181
Test name
Test status
Simulation time 63844271 ps
CPU time 2.37 seconds
Started Apr 23 01:54:42 PM PDT 24
Finished Apr 23 01:54:46 PM PDT 24
Peak memory 206912 kb
Host smart-7ecf7351-b120-40b8-8646-858345bdca3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723650136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2723650136
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.755180238
Short name T460
Test name
Test status
Simulation time 882740397 ps
CPU time 23.43 seconds
Started Apr 23 01:54:42 PM PDT 24
Finished Apr 23 01:55:07 PM PDT 24
Peak memory 208392 kb
Host smart-212cacbd-436b-4c60-b214-9fbb7818892f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755180238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.755180238
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.19918135
Short name T575
Test name
Test status
Simulation time 259630921 ps
CPU time 3.2 seconds
Started Apr 23 01:54:44 PM PDT 24
Finished Apr 23 01:54:47 PM PDT 24
Peak memory 208828 kb
Host smart-10198156-02ff-4e72-ad85-1c00018cc437
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19918135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.19918135
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.8694556
Short name T480
Test name
Test status
Simulation time 27432731 ps
CPU time 2.03 seconds
Started Apr 23 01:54:46 PM PDT 24
Finished Apr 23 01:54:49 PM PDT 24
Peak memory 209928 kb
Host smart-2eb370cb-478f-4a8b-9e99-1125a995fd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8694556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.8694556
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2394155414
Short name T711
Test name
Test status
Simulation time 256734881 ps
CPU time 3.99 seconds
Started Apr 23 01:54:46 PM PDT 24
Finished Apr 23 01:54:51 PM PDT 24
Peak memory 206932 kb
Host smart-4efaa87f-524a-4dfb-8fd3-05aa6c601046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394155414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2394155414
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.292452369
Short name T230
Test name
Test status
Simulation time 3922822114 ps
CPU time 120.53 seconds
Started Apr 23 01:54:46 PM PDT 24
Finished Apr 23 01:56:47 PM PDT 24
Peak memory 217416 kb
Host smart-fa791c6d-8bab-4373-bf73-e791638672d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292452369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.292452369
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2443448850
Short name T722
Test name
Test status
Simulation time 290183790 ps
CPU time 8.71 seconds
Started Apr 23 01:54:46 PM PDT 24
Finished Apr 23 01:54:55 PM PDT 24
Peak memory 209284 kb
Host smart-15d4df91-a526-4dbb-bea9-69f9dcb82d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443448850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2443448850
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1584965449
Short name T486
Test name
Test status
Simulation time 127827981 ps
CPU time 3.13 seconds
Started Apr 23 01:54:44 PM PDT 24
Finished Apr 23 01:54:48 PM PDT 24
Peak memory 210248 kb
Host smart-48a00f28-2f50-448c-aca9-d15d49ad2ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584965449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1584965449
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.880489554
Short name T784
Test name
Test status
Simulation time 61843017 ps
CPU time 0.71 seconds
Started Apr 23 01:56:01 PM PDT 24
Finished Apr 23 01:56:02 PM PDT 24
Peak memory 206140 kb
Host smart-7917a612-ab27-4a37-be2c-59540c44e736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880489554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.880489554
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1805143436
Short name T5
Test name
Test status
Simulation time 335850647 ps
CPU time 2.35 seconds
Started Apr 23 01:56:04 PM PDT 24
Finished Apr 23 01:56:07 PM PDT 24
Peak memory 219220 kb
Host smart-5373c748-d623-4d41-aca0-691ad3efce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805143436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1805143436
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1233718965
Short name T710
Test name
Test status
Simulation time 61017395 ps
CPU time 3.02 seconds
Started Apr 23 01:56:01 PM PDT 24
Finished Apr 23 01:56:05 PM PDT 24
Peak memory 210244 kb
Host smart-cbac44e4-03c6-47c0-8205-fde3c520b290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233718965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1233718965
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2400913613
Short name T235
Test name
Test status
Simulation time 245161859 ps
CPU time 4.02 seconds
Started Apr 23 01:56:01 PM PDT 24
Finished Apr 23 01:56:05 PM PDT 24
Peak memory 211468 kb
Host smart-9ceb21cd-f257-42c3-aeef-24fef3ead90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400913613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2400913613
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3951070464
Short name T721
Test name
Test status
Simulation time 37792493 ps
CPU time 2.61 seconds
Started Apr 23 01:56:02 PM PDT 24
Finished Apr 23 01:56:05 PM PDT 24
Peak memory 220496 kb
Host smart-592c798f-8914-48ae-aba2-aa079535d0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951070464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3951070464
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2040420320
Short name T594
Test name
Test status
Simulation time 219510049 ps
CPU time 5.08 seconds
Started Apr 23 01:56:00 PM PDT 24
Finished Apr 23 01:56:06 PM PDT 24
Peak memory 208972 kb
Host smart-6273b434-1d2e-408f-b3f1-1346dc9fb049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040420320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2040420320
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.148259003
Short name T814
Test name
Test status
Simulation time 177128064 ps
CPU time 3.82 seconds
Started Apr 23 01:56:00 PM PDT 24
Finished Apr 23 01:56:05 PM PDT 24
Peak memory 208912 kb
Host smart-a3f179c8-8f3e-462d-9461-027b6b84217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148259003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.148259003
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.36103884
Short name T698
Test name
Test status
Simulation time 76681140 ps
CPU time 2.82 seconds
Started Apr 23 01:55:59 PM PDT 24
Finished Apr 23 01:56:03 PM PDT 24
Peak memory 208672 kb
Host smart-c7e98a15-2dc2-44dc-bc5e-d0afda6bdd7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36103884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.36103884
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.740516879
Short name T506
Test name
Test status
Simulation time 687049050 ps
CPU time 5.88 seconds
Started Apr 23 01:55:58 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 208036 kb
Host smart-0f7fb8bf-32d6-46e5-9e6a-b5bbe78b9ecd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740516879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.740516879
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3928315683
Short name T803
Test name
Test status
Simulation time 501900734 ps
CPU time 6.88 seconds
Started Apr 23 01:56:00 PM PDT 24
Finished Apr 23 01:56:08 PM PDT 24
Peak memory 209020 kb
Host smart-955e724e-d2b7-405b-babc-a92d884614f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928315683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3928315683
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1074623637
Short name T573
Test name
Test status
Simulation time 514949985 ps
CPU time 4.26 seconds
Started Apr 23 01:56:00 PM PDT 24
Finished Apr 23 01:56:05 PM PDT 24
Peak memory 209412 kb
Host smart-546bc3cb-30f5-4ccb-ade3-527e4e276c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074623637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1074623637
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2473492567
Short name T837
Test name
Test status
Simulation time 145472222 ps
CPU time 4.95 seconds
Started Apr 23 01:56:05 PM PDT 24
Finished Apr 23 01:56:11 PM PDT 24
Peak memory 207972 kb
Host smart-010a6b6b-fdd9-4dc3-8e0e-a5a89803fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473492567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2473492567
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3705222792
Short name T50
Test name
Test status
Simulation time 2839780374 ps
CPU time 15.92 seconds
Started Apr 23 01:56:02 PM PDT 24
Finished Apr 23 01:56:19 PM PDT 24
Peak memory 222980 kb
Host smart-033efe03-4cdd-4fd7-99f6-58058d4d0e7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705222792 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3705222792
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.103839810
Short name T360
Test name
Test status
Simulation time 264088552 ps
CPU time 5.58 seconds
Started Apr 23 01:56:04 PM PDT 24
Finished Apr 23 01:56:11 PM PDT 24
Peak memory 214672 kb
Host smart-178d7ea5-f427-40be-8a61-2a0d77fe8fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103839810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.103839810
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2049380534
Short name T502
Test name
Test status
Simulation time 9911070 ps
CPU time 0.73 seconds
Started Apr 23 01:56:04 PM PDT 24
Finished Apr 23 01:56:05 PM PDT 24
Peak memory 206216 kb
Host smart-f55d2184-f94a-477b-863a-25dd6d8fd744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049380534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2049380534
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3027039427
Short name T300
Test name
Test status
Simulation time 744365498 ps
CPU time 10.97 seconds
Started Apr 23 01:56:02 PM PDT 24
Finished Apr 23 01:56:13 PM PDT 24
Peak memory 215540 kb
Host smart-15fac01e-de80-4266-a3d6-166aaa0720e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3027039427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3027039427
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2237901434
Short name T398
Test name
Test status
Simulation time 203292096 ps
CPU time 2.97 seconds
Started Apr 23 01:56:04 PM PDT 24
Finished Apr 23 01:56:08 PM PDT 24
Peak memory 208704 kb
Host smart-67d877de-7191-4665-a904-e89692ec0112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237901434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2237901434
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3791424626
Short name T376
Test name
Test status
Simulation time 294811324 ps
CPU time 6.05 seconds
Started Apr 23 01:56:04 PM PDT 24
Finished Apr 23 01:56:11 PM PDT 24
Peak memory 220868 kb
Host smart-eee1062a-05ff-45d7-bb41-95e345ac949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791424626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3791424626
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1769842397
Short name T286
Test name
Test status
Simulation time 49077052 ps
CPU time 3.56 seconds
Started Apr 23 01:56:08 PM PDT 24
Finished Apr 23 01:56:12 PM PDT 24
Peak memory 222600 kb
Host smart-3456dc2b-a06e-4b06-9b9a-8941c2987bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769842397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1769842397
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2136216027
Short name T707
Test name
Test status
Simulation time 440782224 ps
CPU time 3.16 seconds
Started Apr 23 01:56:04 PM PDT 24
Finished Apr 23 01:56:08 PM PDT 24
Peak memory 222776 kb
Host smart-ef635e19-bb18-4ff1-af04-8f5c0036dabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136216027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2136216027
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_sideload.923261
Short name T188
Test name
Test status
Simulation time 64214019 ps
CPU time 2.91 seconds
Started Apr 23 01:56:03 PM PDT 24
Finished Apr 23 01:56:06 PM PDT 24
Peak memory 208028 kb
Host smart-4b796b8d-dc96-4907-9e8e-425f0c39b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.923261
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3677919312
Short name T475
Test name
Test status
Simulation time 22856958 ps
CPU time 1.91 seconds
Started Apr 23 01:56:04 PM PDT 24
Finished Apr 23 01:56:07 PM PDT 24
Peak memory 206820 kb
Host smart-603e77e4-cd2f-4c51-a7bf-81938ade3098
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677919312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3677919312
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3582989612
Short name T450
Test name
Test status
Simulation time 786812015 ps
CPU time 9.35 seconds
Started Apr 23 01:56:05 PM PDT 24
Finished Apr 23 01:56:15 PM PDT 24
Peak memory 209236 kb
Host smart-f5dc3819-c770-4529-b289-c90f7ab84ddf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582989612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3582989612
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2669919216
Short name T677
Test name
Test status
Simulation time 2775682059 ps
CPU time 40.13 seconds
Started Apr 23 01:56:09 PM PDT 24
Finished Apr 23 01:56:50 PM PDT 24
Peak memory 208380 kb
Host smart-872c017d-4a6c-4053-9a07-0642df7880e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669919216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2669919216
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1005628230
Short name T718
Test name
Test status
Simulation time 285996630 ps
CPU time 2.26 seconds
Started Apr 23 01:56:06 PM PDT 24
Finished Apr 23 01:56:09 PM PDT 24
Peak memory 216176 kb
Host smart-181204e2-88db-4c83-88fa-5e32d76e9a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005628230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1005628230
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2825313745
Short name T630
Test name
Test status
Simulation time 129893793 ps
CPU time 2.81 seconds
Started Apr 23 01:56:01 PM PDT 24
Finished Apr 23 01:56:04 PM PDT 24
Peak memory 208408 kb
Host smart-ceb948a1-05fd-499f-bae7-87fc8949ea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825313745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2825313745
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2417366550
Short name T781
Test name
Test status
Simulation time 565987455 ps
CPU time 26.6 seconds
Started Apr 23 01:56:02 PM PDT 24
Finished Apr 23 01:56:29 PM PDT 24
Peak memory 216896 kb
Host smart-ed7ec35c-d3bc-4121-960f-8ada96e0fecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417366550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2417366550
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3072406823
Short name T520
Test name
Test status
Simulation time 246688870 ps
CPU time 3.58 seconds
Started Apr 23 01:56:06 PM PDT 24
Finished Apr 23 01:56:10 PM PDT 24
Peak memory 207416 kb
Host smart-373fd232-fa4f-4db6-945e-75cee84f1e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072406823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3072406823
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1696220261
Short name T591
Test name
Test status
Simulation time 23986560 ps
CPU time 1.48 seconds
Started Apr 23 01:56:04 PM PDT 24
Finished Apr 23 01:56:06 PM PDT 24
Peak memory 210108 kb
Host smart-78e49f29-dc45-458d-a2a2-f4221e981186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696220261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1696220261
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1558800405
Short name T434
Test name
Test status
Simulation time 32273430 ps
CPU time 0.74 seconds
Started Apr 23 01:56:11 PM PDT 24
Finished Apr 23 01:56:12 PM PDT 24
Peak memory 205860 kb
Host smart-ffecd4e7-f43e-44e6-8113-641d4a4baea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558800405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1558800405
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1168623294
Short name T139
Test name
Test status
Simulation time 86160303 ps
CPU time 4.57 seconds
Started Apr 23 01:56:06 PM PDT 24
Finished Apr 23 01:56:12 PM PDT 24
Peak memory 215792 kb
Host smart-8ce89046-d416-4c9b-8182-cd41a3eb079b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1168623294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1168623294
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1068972202
Short name T66
Test name
Test status
Simulation time 841071961 ps
CPU time 3.17 seconds
Started Apr 23 01:56:07 PM PDT 24
Finished Apr 23 01:56:11 PM PDT 24
Peak memory 214608 kb
Host smart-69383f11-d523-4030-a96a-79bd452d48f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068972202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1068972202
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.255975773
Short name T86
Test name
Test status
Simulation time 593180608 ps
CPU time 4 seconds
Started Apr 23 01:56:08 PM PDT 24
Finished Apr 23 01:56:13 PM PDT 24
Peak memory 209400 kb
Host smart-eb26a709-bfb0-40c8-a5c6-dec4c49a9534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255975773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.255975773
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3982143190
Short name T273
Test name
Test status
Simulation time 349041053 ps
CPU time 4.55 seconds
Started Apr 23 01:56:06 PM PDT 24
Finished Apr 23 01:56:11 PM PDT 24
Peak memory 220460 kb
Host smart-813d20d6-5de6-4630-b5eb-c2d0f24363dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982143190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3982143190
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1040138149
Short name T901
Test name
Test status
Simulation time 260001639 ps
CPU time 3.35 seconds
Started Apr 23 01:56:05 PM PDT 24
Finished Apr 23 01:56:09 PM PDT 24
Peak memory 214604 kb
Host smart-0e0933e9-b75b-4606-974a-4ba380fe84fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040138149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1040138149
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.595790627
Short name T523
Test name
Test status
Simulation time 252691947 ps
CPU time 5.6 seconds
Started Apr 23 01:56:06 PM PDT 24
Finished Apr 23 01:56:12 PM PDT 24
Peak memory 206712 kb
Host smart-3be1942d-5d78-4905-8101-d931b42d43ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595790627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.595790627
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1656162851
Short name T187
Test name
Test status
Simulation time 743794079 ps
CPU time 6.81 seconds
Started Apr 23 01:56:09 PM PDT 24
Finished Apr 23 01:56:16 PM PDT 24
Peak memory 208308 kb
Host smart-455ea6e0-b853-407d-9498-9c06fd694d8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656162851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1656162851
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2817961880
Short name T783
Test name
Test status
Simulation time 1504611297 ps
CPU time 9.46 seconds
Started Apr 23 01:56:06 PM PDT 24
Finished Apr 23 01:56:16 PM PDT 24
Peak memory 208812 kb
Host smart-b994b7d1-b112-4603-bb65-b7659d66473c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817961880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2817961880
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2634026470
Short name T497
Test name
Test status
Simulation time 130147135 ps
CPU time 4.36 seconds
Started Apr 23 01:56:06 PM PDT 24
Finished Apr 23 01:56:10 PM PDT 24
Peak memory 208836 kb
Host smart-c556feb1-6eb5-425e-8bd4-28a8cb4d3b27
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634026470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2634026470
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1318047615
Short name T394
Test name
Test status
Simulation time 49202344 ps
CPU time 3.1 seconds
Started Apr 23 01:56:09 PM PDT 24
Finished Apr 23 01:56:13 PM PDT 24
Peak memory 214644 kb
Host smart-93516209-9849-4acf-9891-bd0b5e80b979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318047615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1318047615
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2619082757
Short name T847
Test name
Test status
Simulation time 73154754 ps
CPU time 1.77 seconds
Started Apr 23 01:56:08 PM PDT 24
Finished Apr 23 01:56:10 PM PDT 24
Peak memory 206976 kb
Host smart-fe4e5b53-b6e6-49fa-9fc5-9337b6f7405c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619082757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2619082757
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2243083384
Short name T170
Test name
Test status
Simulation time 1224188272 ps
CPU time 27.89 seconds
Started Apr 23 01:56:10 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 208744 kb
Host smart-fe4a8875-c2dd-473f-9448-6b1f4a9c61d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243083384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2243083384
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3811537103
Short name T165
Test name
Test status
Simulation time 356301054 ps
CPU time 10.61 seconds
Started Apr 23 01:56:10 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 222920 kb
Host smart-805b09bf-ef1b-497a-a8c4-b4b1ce5af0eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811537103 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3811537103
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2774134742
Short name T29
Test name
Test status
Simulation time 1007937252 ps
CPU time 9.83 seconds
Started Apr 23 01:56:10 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 218440 kb
Host smart-477025a0-231d-4b92-95b7-ba2c5cdfb405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774134742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2774134742
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2814988778
Short name T103
Test name
Test status
Simulation time 3161490042 ps
CPU time 15.99 seconds
Started Apr 23 01:56:10 PM PDT 24
Finished Apr 23 01:56:26 PM PDT 24
Peak memory 211640 kb
Host smart-a6a963f7-6beb-4984-a493-09368d10c28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814988778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2814988778
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4221366831
Short name T99
Test name
Test status
Simulation time 41409185 ps
CPU time 0.82 seconds
Started Apr 23 01:56:14 PM PDT 24
Finished Apr 23 01:56:15 PM PDT 24
Peak memory 206144 kb
Host smart-dd9eb1bc-5938-458d-b329-deae42443467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221366831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4221366831
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1126490234
Short name T361
Test name
Test status
Simulation time 254228105 ps
CPU time 3.41 seconds
Started Apr 23 01:56:11 PM PDT 24
Finished Apr 23 01:56:15 PM PDT 24
Peak memory 215364 kb
Host smart-6fd3a8d6-b5e9-41a8-828e-a472cb5699be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126490234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1126490234
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2264215244
Short name T65
Test name
Test status
Simulation time 81795312 ps
CPU time 2.59 seconds
Started Apr 23 01:56:14 PM PDT 24
Finished Apr 23 01:56:17 PM PDT 24
Peak memory 208028 kb
Host smart-7c138db4-a094-4e9b-aba3-279333db2596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264215244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2264215244
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3374487262
Short name T379
Test name
Test status
Simulation time 79106501 ps
CPU time 2.78 seconds
Started Apr 23 01:56:11 PM PDT 24
Finished Apr 23 01:56:14 PM PDT 24
Peak memory 207756 kb
Host smart-d814f36c-e1b5-4bde-afee-cfb2e9a3af0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374487262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3374487262
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3789221655
Short name T777
Test name
Test status
Simulation time 606213257 ps
CPU time 13.11 seconds
Started Apr 23 01:56:14 PM PDT 24
Finished Apr 23 01:56:27 PM PDT 24
Peak memory 209740 kb
Host smart-4de5da93-7697-4e41-b1b5-91f5ae5aff08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789221655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3789221655
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1442038114
Short name T647
Test name
Test status
Simulation time 102562552 ps
CPU time 3.49 seconds
Started Apr 23 01:56:12 PM PDT 24
Finished Apr 23 01:56:16 PM PDT 24
Peak memory 220572 kb
Host smart-8f037954-594d-49c4-ad87-e01957a0288b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442038114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1442038114
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.991396368
Short name T643
Test name
Test status
Simulation time 9432339979 ps
CPU time 30.11 seconds
Started Apr 23 01:56:08 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 208784 kb
Host smart-a3d13b77-6d90-495a-9de2-d9a8ea2b2efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991396368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.991396368
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2264714653
Short name T447
Test name
Test status
Simulation time 37098921 ps
CPU time 2.39 seconds
Started Apr 23 01:56:10 PM PDT 24
Finished Apr 23 01:56:13 PM PDT 24
Peak memory 208668 kb
Host smart-ad973e38-084b-4fb2-805f-7998ab006009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264714653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2264714653
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1180510966
Short name T672
Test name
Test status
Simulation time 466141446 ps
CPU time 3.32 seconds
Started Apr 23 01:56:09 PM PDT 24
Finished Apr 23 01:56:13 PM PDT 24
Peak memory 206904 kb
Host smart-423fb68c-dfec-43e3-be8e-9ea548c5d38f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180510966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1180510966
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.270884982
Short name T758
Test name
Test status
Simulation time 121557356 ps
CPU time 2.37 seconds
Started Apr 23 01:56:09 PM PDT 24
Finished Apr 23 01:56:12 PM PDT 24
Peak memory 206828 kb
Host smart-21de73ac-7494-433c-a32f-f453f987be89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270884982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.270884982
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.598314705
Short name T586
Test name
Test status
Simulation time 619607937 ps
CPU time 8.19 seconds
Started Apr 23 01:56:13 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 208884 kb
Host smart-06127754-f073-4c63-8f81-86f084fa652a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598314705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.598314705
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2274201264
Short name T281
Test name
Test status
Simulation time 454172305 ps
CPU time 3.99 seconds
Started Apr 23 01:56:14 PM PDT 24
Finished Apr 23 01:56:18 PM PDT 24
Peak memory 210060 kb
Host smart-0853c7a5-a20e-4cdd-893c-076270e759c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274201264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2274201264
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1977292356
Short name T841
Test name
Test status
Simulation time 206432277 ps
CPU time 2.64 seconds
Started Apr 23 01:56:10 PM PDT 24
Finished Apr 23 01:56:13 PM PDT 24
Peak memory 206752 kb
Host smart-c06ff57b-32a9-4fe5-a2e3-08a4e3d06c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977292356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1977292356
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2162360509
Short name T302
Test name
Test status
Simulation time 3449704103 ps
CPU time 30.95 seconds
Started Apr 23 01:56:14 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 222740 kb
Host smart-1b7b62c5-accb-4258-ae5c-68d35000041c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162360509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2162360509
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3886401549
Short name T164
Test name
Test status
Simulation time 1026259854 ps
CPU time 22.47 seconds
Started Apr 23 01:56:13 PM PDT 24
Finished Apr 23 01:56:36 PM PDT 24
Peak memory 220576 kb
Host smart-3bed2254-d8f8-4339-81d3-d563206dcb10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886401549 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3886401549
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.985266418
Short name T513
Test name
Test status
Simulation time 143961242 ps
CPU time 6.49 seconds
Started Apr 23 01:56:13 PM PDT 24
Finished Apr 23 01:56:19 PM PDT 24
Peak memory 209968 kb
Host smart-aed5b601-e91f-4707-9e09-f4a690adbc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985266418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.985266418
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.147093908
Short name T512
Test name
Test status
Simulation time 832154863 ps
CPU time 9.31 seconds
Started Apr 23 01:56:11 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 210688 kb
Host smart-b27b3081-d259-45c1-97df-ca9006b2aec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147093908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.147093908
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3560858724
Short name T532
Test name
Test status
Simulation time 40231369 ps
CPU time 0.75 seconds
Started Apr 23 01:56:16 PM PDT 24
Finished Apr 23 01:56:17 PM PDT 24
Peak memory 206136 kb
Host smart-99d28485-b104-41ac-8317-d583a86c9a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560858724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3560858724
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3244415537
Short name T648
Test name
Test status
Simulation time 191509929 ps
CPU time 2.45 seconds
Started Apr 23 01:56:15 PM PDT 24
Finished Apr 23 01:56:18 PM PDT 24
Peak memory 219968 kb
Host smart-86685e1d-7ca7-4f0d-956a-534d395a072a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244415537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3244415537
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1683432864
Short name T442
Test name
Test status
Simulation time 84063408 ps
CPU time 2.49 seconds
Started Apr 23 01:56:18 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 209772 kb
Host smart-752a75c7-971d-4303-bfa4-f543f9622574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683432864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1683432864
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2333761521
Short name T682
Test name
Test status
Simulation time 321305746 ps
CPU time 4.81 seconds
Started Apr 23 01:56:18 PM PDT 24
Finished Apr 23 01:56:23 PM PDT 24
Peak memory 210996 kb
Host smart-32a9e4e1-b6b6-418d-9e53-97447197b92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333761521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2333761521
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1288677175
Short name T203
Test name
Test status
Simulation time 78307272 ps
CPU time 3.91 seconds
Started Apr 23 01:56:16 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 214480 kb
Host smart-80a0a2f9-ea9f-4a74-ab1a-a83ed7e2fcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288677175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1288677175
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1012909626
Short name T663
Test name
Test status
Simulation time 2034770751 ps
CPU time 51.61 seconds
Started Apr 23 01:56:15 PM PDT 24
Finished Apr 23 01:57:07 PM PDT 24
Peak memory 209128 kb
Host smart-f4020963-ad50-4066-b687-668eb06fd534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012909626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1012909626
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3126642675
Short name T810
Test name
Test status
Simulation time 1351780192 ps
CPU time 44.19 seconds
Started Apr 23 01:56:19 PM PDT 24
Finished Apr 23 01:57:04 PM PDT 24
Peak memory 208532 kb
Host smart-22a11a61-342b-4264-aad4-832c573eafd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126642675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3126642675
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3762454483
Short name T133
Test name
Test status
Simulation time 42888476 ps
CPU time 1.81 seconds
Started Apr 23 01:56:15 PM PDT 24
Finished Apr 23 01:56:17 PM PDT 24
Peak memory 206964 kb
Host smart-7a130dc8-98b3-4323-8292-9f7f272c4658
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762454483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3762454483
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3880982059
Short name T544
Test name
Test status
Simulation time 110348233 ps
CPU time 3.15 seconds
Started Apr 23 01:56:17 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 207132 kb
Host smart-295b6558-424a-4280-98c7-a33e8f6b4ee1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880982059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3880982059
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1354741000
Short name T180
Test name
Test status
Simulation time 535357175 ps
CPU time 7.67 seconds
Started Apr 23 01:56:15 PM PDT 24
Finished Apr 23 01:56:23 PM PDT 24
Peak memory 208164 kb
Host smart-a3b12465-23ad-4fd0-bc88-7e0c3ba3c4bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354741000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1354741000
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3605050305
Short name T633
Test name
Test status
Simulation time 28830111 ps
CPU time 2.11 seconds
Started Apr 23 01:56:15 PM PDT 24
Finished Apr 23 01:56:17 PM PDT 24
Peak memory 209720 kb
Host smart-e6d2ee05-70b4-4b9a-9491-22ba5ea58cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605050305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3605050305
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3156050729
Short name T623
Test name
Test status
Simulation time 419983378 ps
CPU time 4.87 seconds
Started Apr 23 01:56:15 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 208000 kb
Host smart-fea5b725-b3de-4b72-8c8f-b41044f998a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156050729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3156050729
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2861473121
Short name T166
Test name
Test status
Simulation time 2731616836 ps
CPU time 23.28 seconds
Started Apr 23 01:56:15 PM PDT 24
Finished Apr 23 01:56:39 PM PDT 24
Peak memory 223000 kb
Host smart-de46b930-1282-4933-baac-4904afe6c16c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861473121 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2861473121
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3725812730
Short name T82
Test name
Test status
Simulation time 577988947 ps
CPU time 6.81 seconds
Started Apr 23 01:56:16 PM PDT 24
Finished Apr 23 01:56:23 PM PDT 24
Peak memory 208372 kb
Host smart-720e2080-5d15-490f-98d4-970a9cb1706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725812730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3725812730
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3113955712
Short name T385
Test name
Test status
Simulation time 141062279 ps
CPU time 1.79 seconds
Started Apr 23 01:56:17 PM PDT 24
Finished Apr 23 01:56:19 PM PDT 24
Peak memory 210048 kb
Host smart-e95cfd9f-377e-4dc8-9fb9-94cfa69bd5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113955712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3113955712
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2522929920
Short name T637
Test name
Test status
Simulation time 46987727 ps
CPU time 0.87 seconds
Started Apr 23 01:56:23 PM PDT 24
Finished Apr 23 01:56:24 PM PDT 24
Peak memory 206212 kb
Host smart-7b78efd5-c32a-4545-8fae-1007b137ba3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522929920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2522929920
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.460311350
Short name T425
Test name
Test status
Simulation time 1002260599 ps
CPU time 53.26 seconds
Started Apr 23 01:56:23 PM PDT 24
Finished Apr 23 01:57:16 PM PDT 24
Peak memory 215108 kb
Host smart-54298b9f-2dcb-4c3e-baaf-0f8c3bac52c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460311350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.460311350
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.939594208
Short name T34
Test name
Test status
Simulation time 189672823 ps
CPU time 2.3 seconds
Started Apr 23 01:56:21 PM PDT 24
Finished Apr 23 01:56:24 PM PDT 24
Peak memory 221896 kb
Host smart-9367c2b1-0e69-4095-b96a-9d0a3cd080e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939594208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.939594208
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3836978013
Short name T247
Test name
Test status
Simulation time 41468967 ps
CPU time 2.67 seconds
Started Apr 23 01:56:17 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 210120 kb
Host smart-a70c3c94-44b3-440d-ba0e-baf675f74f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836978013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3836978013
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.4282827287
Short name T102
Test name
Test status
Simulation time 1959846913 ps
CPU time 43.68 seconds
Started Apr 23 01:56:19 PM PDT 24
Finished Apr 23 01:57:03 PM PDT 24
Peak memory 209744 kb
Host smart-c69ade63-f90d-4c3d-8db9-d5e65752f71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282827287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4282827287
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1785398116
Short name T196
Test name
Test status
Simulation time 220343952 ps
CPU time 7.64 seconds
Started Apr 23 01:56:21 PM PDT 24
Finished Apr 23 01:56:29 PM PDT 24
Peak memory 210608 kb
Host smart-54445482-a654-4c61-af84-dfb489a5f920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785398116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1785398116
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.183891720
Short name T897
Test name
Test status
Simulation time 111619618 ps
CPU time 3.57 seconds
Started Apr 23 01:56:17 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 222760 kb
Host smart-9a4adef4-9cc9-4918-b6d0-c56245c2b621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183891720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.183891720
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.71431508
Short name T624
Test name
Test status
Simulation time 86304162 ps
CPU time 3.08 seconds
Started Apr 23 01:56:19 PM PDT 24
Finished Apr 23 01:56:23 PM PDT 24
Peak memory 208032 kb
Host smart-9d1aa6cf-e6be-4968-a038-c81343cdd881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71431508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.71431508
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2400157909
Short name T517
Test name
Test status
Simulation time 1148011669 ps
CPU time 3.95 seconds
Started Apr 23 01:56:17 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 208844 kb
Host smart-6adaed13-1452-4463-bcb7-6aabfe3d0c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400157909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2400157909
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.820893411
Short name T752
Test name
Test status
Simulation time 32958927 ps
CPU time 2.36 seconds
Started Apr 23 01:56:18 PM PDT 24
Finished Apr 23 01:56:21 PM PDT 24
Peak memory 206972 kb
Host smart-0285e71d-52c6-42f8-a245-35116f8fc2af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820893411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.820893411
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3978251972
Short name T829
Test name
Test status
Simulation time 636187465 ps
CPU time 5.02 seconds
Started Apr 23 01:56:17 PM PDT 24
Finished Apr 23 01:56:23 PM PDT 24
Peak memory 206964 kb
Host smart-d313a038-22f5-4653-985b-08c7c3aa5ba6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978251972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3978251972
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2187073065
Short name T732
Test name
Test status
Simulation time 1356174152 ps
CPU time 44.13 seconds
Started Apr 23 01:56:17 PM PDT 24
Finished Apr 23 01:57:01 PM PDT 24
Peak memory 209184 kb
Host smart-09a615eb-f39a-4fca-a66e-d3410d7c8201
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187073065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2187073065
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2440504759
Short name T559
Test name
Test status
Simulation time 1197327428 ps
CPU time 18.51 seconds
Started Apr 23 01:56:22 PM PDT 24
Finished Apr 23 01:56:41 PM PDT 24
Peak memory 209444 kb
Host smart-528a8935-4cda-49a7-8f37-fdd28ff761dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440504759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2440504759
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1035777247
Short name T193
Test name
Test status
Simulation time 1011298178 ps
CPU time 26.07 seconds
Started Apr 23 01:56:18 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 208088 kb
Host smart-e7ff89c1-7716-436a-bcd7-3d4b93e9c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035777247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1035777247
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2758024512
Short name T80
Test name
Test status
Simulation time 6915987660 ps
CPU time 68.97 seconds
Started Apr 23 01:56:25 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 217016 kb
Host smart-4e8d360d-8e51-4d45-9ad9-8ff88c4fd920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758024512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2758024512
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2026195181
Short name T577
Test name
Test status
Simulation time 92548727 ps
CPU time 4.81 seconds
Started Apr 23 01:56:19 PM PDT 24
Finished Apr 23 01:56:24 PM PDT 24
Peak memory 214644 kb
Host smart-07991e8a-ab31-4ded-a64f-9f651a399599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026195181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2026195181
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.344439873
Short name T388
Test name
Test status
Simulation time 81309826 ps
CPU time 3.1 seconds
Started Apr 23 01:56:21 PM PDT 24
Finished Apr 23 01:56:25 PM PDT 24
Peak memory 210216 kb
Host smart-bc89c9d7-bc92-4b8c-a6bf-ea6183c39c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344439873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.344439873
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2818964435
Short name T534
Test name
Test status
Simulation time 72251446 ps
CPU time 0.87 seconds
Started Apr 23 01:56:26 PM PDT 24
Finished Apr 23 01:56:27 PM PDT 24
Peak memory 206124 kb
Host smart-2dcd4423-1330-481f-81d5-ec4a3dc79f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818964435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2818964435
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3622781667
Short name T565
Test name
Test status
Simulation time 297712125 ps
CPU time 3.47 seconds
Started Apr 23 01:56:21 PM PDT 24
Finished Apr 23 01:56:25 PM PDT 24
Peak memory 209208 kb
Host smart-85e4cf64-a817-4e1b-a1ca-c0854765e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622781667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3622781667
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.613777498
Short name T346
Test name
Test status
Simulation time 325023152 ps
CPU time 8.22 seconds
Started Apr 23 01:56:25 PM PDT 24
Finished Apr 23 01:56:33 PM PDT 24
Peak memory 214588 kb
Host smart-4f230afc-55ba-430f-b2cc-56d2fd93b8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613777498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.613777498
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3289530196
Short name T251
Test name
Test status
Simulation time 179739720 ps
CPU time 6.45 seconds
Started Apr 23 01:56:26 PM PDT 24
Finished Apr 23 01:56:33 PM PDT 24
Peak memory 210424 kb
Host smart-a1571b99-2755-4940-b16e-7ec9e5ee1c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289530196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3289530196
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2547930073
Short name T821
Test name
Test status
Simulation time 36499804 ps
CPU time 2.03 seconds
Started Apr 23 01:56:24 PM PDT 24
Finished Apr 23 01:56:26 PM PDT 24
Peak memory 214728 kb
Host smart-4332ddec-f68c-45e3-a32d-b244201c1f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547930073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2547930073
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.287324987
Short name T343
Test name
Test status
Simulation time 1019078543 ps
CPU time 8.41 seconds
Started Apr 23 01:56:23 PM PDT 24
Finished Apr 23 01:56:32 PM PDT 24
Peak memory 209908 kb
Host smart-28f54d71-cd6c-4329-b5a8-b0c402ce8498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287324987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.287324987
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3822727488
Short name T331
Test name
Test status
Simulation time 81755228 ps
CPU time 2.27 seconds
Started Apr 23 01:56:26 PM PDT 24
Finished Apr 23 01:56:29 PM PDT 24
Peak memory 207932 kb
Host smart-8ea4804f-d1f5-4e00-aaf6-cc06bc5c484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822727488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3822727488
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1773156210
Short name T795
Test name
Test status
Simulation time 108308911 ps
CPU time 3.81 seconds
Started Apr 23 01:56:22 PM PDT 24
Finished Apr 23 01:56:26 PM PDT 24
Peak memory 206872 kb
Host smart-a61192dc-c339-4b39-a02d-749464e41f30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773156210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1773156210
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2486268704
Short name T553
Test name
Test status
Simulation time 121111716 ps
CPU time 2.14 seconds
Started Apr 23 01:56:24 PM PDT 24
Finished Apr 23 01:56:27 PM PDT 24
Peak memory 208984 kb
Host smart-69561858-fb54-4c9b-8cb8-9fdf82fafc35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486268704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2486268704
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2963113552
Short name T377
Test name
Test status
Simulation time 67657556 ps
CPU time 3.15 seconds
Started Apr 23 01:56:22 PM PDT 24
Finished Apr 23 01:56:25 PM PDT 24
Peak memory 208152 kb
Host smart-7f7864d1-3749-46a2-9a95-0a0a44f72939
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963113552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2963113552
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.81577142
Short name T737
Test name
Test status
Simulation time 295576609 ps
CPU time 4.12 seconds
Started Apr 23 01:56:31 PM PDT 24
Finished Apr 23 01:56:36 PM PDT 24
Peak memory 210164 kb
Host smart-310bc589-b5ea-4bd0-a662-dde7ab9907ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81577142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.81577142
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.499831506
Short name T549
Test name
Test status
Simulation time 245645686 ps
CPU time 3.23 seconds
Started Apr 23 01:56:21 PM PDT 24
Finished Apr 23 01:56:25 PM PDT 24
Peak memory 206964 kb
Host smart-c1384c8b-7164-4f9d-b6c7-aa874a2959c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499831506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.499831506
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3835543873
Short name T123
Test name
Test status
Simulation time 874138226 ps
CPU time 12.73 seconds
Started Apr 23 01:56:25 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 222848 kb
Host smart-315a6bbe-31a1-42bc-bfe7-e0db0a30c687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835543873 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3835543873
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1951397064
Short name T260
Test name
Test status
Simulation time 76789721 ps
CPU time 3.88 seconds
Started Apr 23 01:56:21 PM PDT 24
Finished Apr 23 01:56:25 PM PDT 24
Peak memory 214520 kb
Host smart-be7424c4-388e-4049-ae35-94f601520557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951397064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1951397064
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.840357897
Short name T163
Test name
Test status
Simulation time 50182126 ps
CPU time 2.87 seconds
Started Apr 23 01:56:26 PM PDT 24
Finished Apr 23 01:56:30 PM PDT 24
Peak memory 210152 kb
Host smart-62991c0e-a232-48fd-b2b2-2e9d30935352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840357897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.840357897
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3372689068
Short name T789
Test name
Test status
Simulation time 25204869 ps
CPU time 0.82 seconds
Started Apr 23 01:56:32 PM PDT 24
Finished Apr 23 01:56:34 PM PDT 24
Peak memory 206184 kb
Host smart-1c2355b6-2719-4a00-a78e-bc30a0496efa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372689068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3372689068
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2170503557
Short name T314
Test name
Test status
Simulation time 3704067622 ps
CPU time 9.12 seconds
Started Apr 23 01:56:30 PM PDT 24
Finished Apr 23 01:56:40 PM PDT 24
Peak memory 209764 kb
Host smart-a94affbf-78b4-4252-b178-64265835ee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170503557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2170503557
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.782071393
Short name T566
Test name
Test status
Simulation time 52860023 ps
CPU time 1.97 seconds
Started Apr 23 01:56:30 PM PDT 24
Finished Apr 23 01:56:32 PM PDT 24
Peak memory 208320 kb
Host smart-cffe3a2d-172c-47dc-affb-0b6b9f68c17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782071393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.782071393
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.123620813
Short name T318
Test name
Test status
Simulation time 710199822 ps
CPU time 6.8 seconds
Started Apr 23 01:56:28 PM PDT 24
Finished Apr 23 01:56:35 PM PDT 24
Peak memory 214552 kb
Host smart-43a3f028-7f27-4e0f-b9c4-7ac1400da09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123620813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.123620813
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1513684002
Short name T811
Test name
Test status
Simulation time 1505233354 ps
CPU time 10.51 seconds
Started Apr 23 01:56:25 PM PDT 24
Finished Apr 23 01:56:36 PM PDT 24
Peak memory 208908 kb
Host smart-e21874b9-e3d7-4cc5-97c8-7366098e85e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513684002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1513684002
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2660681904
Short name T527
Test name
Test status
Simulation time 729428248 ps
CPU time 4.06 seconds
Started Apr 23 01:56:32 PM PDT 24
Finished Apr 23 01:56:36 PM PDT 24
Peak memory 208772 kb
Host smart-78860f4a-b495-4e0d-9105-03d96e2d2480
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660681904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2660681904
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.122132142
Short name T182
Test name
Test status
Simulation time 161675862 ps
CPU time 4.96 seconds
Started Apr 23 01:56:26 PM PDT 24
Finished Apr 23 01:56:32 PM PDT 24
Peak memory 208008 kb
Host smart-7751d1d1-5c1a-4c97-8b62-4a972a3cd64d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122132142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.122132142
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.925604055
Short name T770
Test name
Test status
Simulation time 303010319 ps
CPU time 2.52 seconds
Started Apr 23 01:56:27 PM PDT 24
Finished Apr 23 01:56:30 PM PDT 24
Peak memory 207052 kb
Host smart-b6d757cb-ecc8-4d9c-9759-d458cdcfa5dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925604055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.925604055
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3092723123
Short name T615
Test name
Test status
Simulation time 948914001 ps
CPU time 5.04 seconds
Started Apr 23 01:56:31 PM PDT 24
Finished Apr 23 01:56:37 PM PDT 24
Peak memory 214528 kb
Host smart-c7e2e9e8-8f84-4b0f-84eb-f79690699082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092723123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3092723123
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.272929453
Short name T616
Test name
Test status
Simulation time 136131318 ps
CPU time 3.06 seconds
Started Apr 23 01:56:32 PM PDT 24
Finished Apr 23 01:56:35 PM PDT 24
Peak memory 206324 kb
Host smart-5220885f-a8e5-4d56-ae9e-eeba7c249dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272929453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.272929453
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1253754276
Short name T125
Test name
Test status
Simulation time 1024244878 ps
CPU time 14.25 seconds
Started Apr 23 01:56:29 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 222940 kb
Host smart-8ef8d318-cc9b-42f4-b9a9-32381f0756f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253754276 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1253754276
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1664602360
Short name T824
Test name
Test status
Simulation time 111573949 ps
CPU time 3.07 seconds
Started Apr 23 01:56:28 PM PDT 24
Finished Apr 23 01:56:31 PM PDT 24
Peak memory 207796 kb
Host smart-91190f4d-948d-4bce-b8db-8ac76f3c506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664602360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1664602360
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3502493219
Short name T384
Test name
Test status
Simulation time 51000017 ps
CPU time 2.83 seconds
Started Apr 23 01:56:30 PM PDT 24
Finished Apr 23 01:56:33 PM PDT 24
Peak memory 210404 kb
Host smart-8191602b-dce1-4f08-ac9b-9553df6ea5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502493219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3502493219
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3244298938
Short name T448
Test name
Test status
Simulation time 10217218 ps
CPU time 0.83 seconds
Started Apr 23 01:56:32 PM PDT 24
Finished Apr 23 01:56:34 PM PDT 24
Peak memory 206096 kb
Host smart-27bf280f-c3ce-4b5b-80b8-303183312c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244298938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3244298938
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1019939377
Short name T261
Test name
Test status
Simulation time 321233905 ps
CPU time 7.38 seconds
Started Apr 23 01:56:29 PM PDT 24
Finished Apr 23 01:56:37 PM PDT 24
Peak memory 214516 kb
Host smart-d502e22a-7629-476a-b1b7-ea2d2d4bc99a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019939377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1019939377
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1241344435
Short name T859
Test name
Test status
Simulation time 814962754 ps
CPU time 15.36 seconds
Started Apr 23 01:56:28 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 209352 kb
Host smart-2b5bde4f-b029-403d-93f7-25bc22a75a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241344435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1241344435
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3915307322
Short name T463
Test name
Test status
Simulation time 51358222 ps
CPU time 1.86 seconds
Started Apr 23 01:56:30 PM PDT 24
Finished Apr 23 01:56:32 PM PDT 24
Peak memory 207728 kb
Host smart-e2866d9f-f865-4fda-8474-ec5f02bc7343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915307322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3915307322
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2687130586
Short name T92
Test name
Test status
Simulation time 343207752 ps
CPU time 9.99 seconds
Started Apr 23 01:56:30 PM PDT 24
Finished Apr 23 01:56:40 PM PDT 24
Peak memory 209068 kb
Host smart-5da594ae-f287-4c62-b954-7353b6d2ae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687130586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2687130586
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1176967505
Short name T363
Test name
Test status
Simulation time 41455312 ps
CPU time 2.87 seconds
Started Apr 23 01:56:31 PM PDT 24
Finished Apr 23 01:56:35 PM PDT 24
Peak memory 210564 kb
Host smart-dab307f3-593d-4053-af60-d4de59bc3c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176967505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1176967505
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3703768379
Short name T206
Test name
Test status
Simulation time 67068740 ps
CPU time 2.98 seconds
Started Apr 23 01:56:29 PM PDT 24
Finished Apr 23 01:56:32 PM PDT 24
Peak memory 220652 kb
Host smart-5fbcd40e-2eff-4144-b95b-3e977cf3a506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703768379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3703768379
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3020239409
Short name T456
Test name
Test status
Simulation time 570656631 ps
CPU time 10.96 seconds
Started Apr 23 01:56:30 PM PDT 24
Finished Apr 23 01:56:41 PM PDT 24
Peak memory 214560 kb
Host smart-25c9402d-1c33-418d-9a0f-71d5e3dbc78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020239409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3020239409
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1948677856
Short name T405
Test name
Test status
Simulation time 166861858 ps
CPU time 2.35 seconds
Started Apr 23 01:56:29 PM PDT 24
Finished Apr 23 01:56:32 PM PDT 24
Peak memory 206980 kb
Host smart-9e2d35d2-f88e-464c-ba01-df4259f85787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948677856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1948677856
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.410696786
Short name T401
Test name
Test status
Simulation time 76180405 ps
CPU time 3.78 seconds
Started Apr 23 01:56:34 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 208996 kb
Host smart-cc5029f5-e318-4808-a94c-481a1b2134b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410696786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.410696786
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3381984752
Short name T297
Test name
Test status
Simulation time 285234043 ps
CPU time 3.19 seconds
Started Apr 23 01:56:30 PM PDT 24
Finished Apr 23 01:56:34 PM PDT 24
Peak memory 206948 kb
Host smart-9fc699f2-2dc2-45ad-905e-54e471e0cb82
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381984752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3381984752
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.4153400549
Short name T551
Test name
Test status
Simulation time 300430752 ps
CPU time 3.16 seconds
Started Apr 23 01:56:29 PM PDT 24
Finished Apr 23 01:56:33 PM PDT 24
Peak memory 207480 kb
Host smart-b3e1e6d0-28e4-46ed-b259-2c348cc5e0e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153400549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4153400549
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1836303520
Short name T131
Test name
Test status
Simulation time 57838642 ps
CPU time 2.4 seconds
Started Apr 23 01:56:28 PM PDT 24
Finished Apr 23 01:56:31 PM PDT 24
Peak memory 218644 kb
Host smart-f60fe3e8-0e62-4c68-9541-6b08d11fd8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836303520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1836303520
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4273741470
Short name T429
Test name
Test status
Simulation time 151700217 ps
CPU time 3.58 seconds
Started Apr 23 01:56:28 PM PDT 24
Finished Apr 23 01:56:32 PM PDT 24
Peak memory 206896 kb
Host smart-9a9f95a2-7096-4051-b820-839731d830a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273741470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4273741470
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1350098606
Short name T813
Test name
Test status
Simulation time 748164860 ps
CPU time 5.39 seconds
Started Apr 23 01:56:34 PM PDT 24
Finished Apr 23 01:56:40 PM PDT 24
Peak memory 208080 kb
Host smart-54fe6668-ad69-4686-a5e0-8f10f6455a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350098606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1350098606
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3230919387
Short name T168
Test name
Test status
Simulation time 312510991 ps
CPU time 8.92 seconds
Started Apr 23 01:56:32 PM PDT 24
Finished Apr 23 01:56:42 PM PDT 24
Peak memory 223020 kb
Host smart-e9fcc3ef-84a2-4e5e-ad81-6f3a7ce21e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230919387 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3230919387
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1700709109
Short name T315
Test name
Test status
Simulation time 124820906 ps
CPU time 5.43 seconds
Started Apr 23 01:56:31 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 210340 kb
Host smart-84e44bb6-abcd-41f3-8386-a1b52ae6fcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700709109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1700709109
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1888089667
Short name T382
Test name
Test status
Simulation time 619554788 ps
CPU time 6.32 seconds
Started Apr 23 01:56:34 PM PDT 24
Finished Apr 23 01:56:41 PM PDT 24
Peak memory 219568 kb
Host smart-3c0a9856-b754-48eb-b4d7-a2451468dee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888089667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1888089667
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1137895101
Short name T17
Test name
Test status
Simulation time 29043359 ps
CPU time 0.77 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:56:40 PM PDT 24
Peak memory 206144 kb
Host smart-f82f9048-2702-46e0-b718-4beaee18b5a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137895101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1137895101
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2994188606
Short name T865
Test name
Test status
Simulation time 71616923 ps
CPU time 3.4 seconds
Started Apr 23 01:56:36 PM PDT 24
Finished Apr 23 01:56:40 PM PDT 24
Peak memory 218980 kb
Host smart-4ea18108-1a42-4be6-ad43-0e3bdf4313b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994188606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2994188606
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.7148552
Short name T880
Test name
Test status
Simulation time 1308436803 ps
CPU time 13.28 seconds
Started Apr 23 01:56:34 PM PDT 24
Finished Apr 23 01:56:48 PM PDT 24
Peak memory 220004 kb
Host smart-d95deea2-bafe-4b00-b163-3910989145cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7148552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.7148552
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3173052704
Short name T321
Test name
Test status
Simulation time 487551387 ps
CPU time 4.05 seconds
Started Apr 23 01:56:33 PM PDT 24
Finished Apr 23 01:56:37 PM PDT 24
Peak memory 209460 kb
Host smart-018de401-614b-4a30-9263-277d4a1eb354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173052704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3173052704
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.670781880
Short name T815
Test name
Test status
Simulation time 405165316 ps
CPU time 4.97 seconds
Started Apr 23 01:56:34 PM PDT 24
Finished Apr 23 01:56:39 PM PDT 24
Peak memory 208812 kb
Host smart-95aa4e5e-c872-4be1-8929-4ff625352201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670781880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.670781880
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2108422405
Short name T868
Test name
Test status
Simulation time 185768262 ps
CPU time 4.11 seconds
Started Apr 23 01:56:34 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 208784 kb
Host smart-60952248-e7ab-46b1-bdf0-dea0d628cd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108422405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2108422405
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.247801341
Short name T776
Test name
Test status
Simulation time 807532843 ps
CPU time 6 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 208072 kb
Host smart-e4b5ea37-6c1a-4e24-8196-125a3d146b5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247801341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.247801341
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2225126692
Short name T579
Test name
Test status
Simulation time 10379805049 ps
CPU time 48.69 seconds
Started Apr 23 01:56:34 PM PDT 24
Finished Apr 23 01:57:24 PM PDT 24
Peak memory 208844 kb
Host smart-d5f19ba9-fc39-4c52-94a6-53cb0d70e743
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225126692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2225126692
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3923240884
Short name T494
Test name
Test status
Simulation time 493842072 ps
CPU time 4.34 seconds
Started Apr 23 01:56:32 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 207100 kb
Host smart-5227880f-76f4-4aec-82cf-929359538da1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923240884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3923240884
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3338832679
Short name T374
Test name
Test status
Simulation time 39122815 ps
CPU time 2.2 seconds
Started Apr 23 01:56:33 PM PDT 24
Finished Apr 23 01:56:35 PM PDT 24
Peak memory 208248 kb
Host smart-a785b5ae-fe60-4d79-9709-c3b7b5c9bcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338832679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3338832679
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1391572853
Short name T890
Test name
Test status
Simulation time 51240152 ps
CPU time 2.75 seconds
Started Apr 23 01:56:31 PM PDT 24
Finished Apr 23 01:56:35 PM PDT 24
Peak memory 206972 kb
Host smart-c32c6749-cb24-42cd-8502-8349ec3d151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391572853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1391572853
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.798980544
Short name T221
Test name
Test status
Simulation time 406514919 ps
CPU time 5.71 seconds
Started Apr 23 01:56:37 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 219712 kb
Host smart-80611c55-2038-44a4-92e9-4a71478babcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798980544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.798980544
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3615081802
Short name T712
Test name
Test status
Simulation time 379509060 ps
CPU time 4.78 seconds
Started Apr 23 01:56:32 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 208444 kb
Host smart-27c8c8b7-52bd-4b9f-a8cd-757dd593ea5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615081802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3615081802
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3855463564
Short name T58
Test name
Test status
Simulation time 294098511 ps
CPU time 2.34 seconds
Started Apr 23 01:56:39 PM PDT 24
Finished Apr 23 01:56:42 PM PDT 24
Peak memory 210268 kb
Host smart-39589b30-3599-4b04-b914-481441860c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855463564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3855463564
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2559283004
Short name T427
Test name
Test status
Simulation time 22381897 ps
CPU time 0.72 seconds
Started Apr 23 01:54:50 PM PDT 24
Finished Apr 23 01:54:52 PM PDT 24
Peak memory 206168 kb
Host smart-685bc1e4-728c-4ecc-b60f-3224543e1b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559283004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2559283004
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1123527143
Short name T303
Test name
Test status
Simulation time 35782069 ps
CPU time 2.61 seconds
Started Apr 23 01:54:51 PM PDT 24
Finished Apr 23 01:54:54 PM PDT 24
Peak memory 214828 kb
Host smart-8f2482a8-bea2-4ad9-b546-eca94928cb32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123527143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1123527143
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.117302245
Short name T207
Test name
Test status
Simulation time 57213626 ps
CPU time 2.58 seconds
Started Apr 23 01:54:53 PM PDT 24
Finished Apr 23 01:54:56 PM PDT 24
Peak memory 216296 kb
Host smart-1ca0f95b-f681-4aa2-b4a2-30eddcb3311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117302245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.117302245
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.809739998
Short name T264
Test name
Test status
Simulation time 107510840 ps
CPU time 3.95 seconds
Started Apr 23 01:54:49 PM PDT 24
Finished Apr 23 01:54:54 PM PDT 24
Peak memory 208744 kb
Host smart-1ccce6b9-002c-4e85-b8bd-7fd7085997a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809739998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.809739998
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3270165305
Short name T272
Test name
Test status
Simulation time 225089485 ps
CPU time 2.98 seconds
Started Apr 23 01:54:48 PM PDT 24
Finished Apr 23 01:54:52 PM PDT 24
Peak memory 214468 kb
Host smart-24f03942-5682-4bf3-b3b4-110b4ab7ce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270165305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3270165305
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3250869283
Short name T364
Test name
Test status
Simulation time 1064478708 ps
CPU time 6.33 seconds
Started Apr 23 01:54:49 PM PDT 24
Finished Apr 23 01:54:55 PM PDT 24
Peak memory 214476 kb
Host smart-527e9e7a-2b25-47be-9afd-572c734368b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250869283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3250869283
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2428934317
Short name T171
Test name
Test status
Simulation time 46646970 ps
CPU time 2.04 seconds
Started Apr 23 01:54:47 PM PDT 24
Finished Apr 23 01:54:50 PM PDT 24
Peak memory 216256 kb
Host smart-fffb697a-4c15-4c78-bfd8-676fe7cb66da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428934317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2428934317
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2874033103
Short name T631
Test name
Test status
Simulation time 47814127 ps
CPU time 3.29 seconds
Started Apr 23 01:54:50 PM PDT 24
Finished Apr 23 01:54:54 PM PDT 24
Peak memory 208856 kb
Host smart-03d7a985-a520-43f6-bf4f-fa25934c85df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874033103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2874033103
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3834069127
Short name T12
Test name
Test status
Simulation time 556575406 ps
CPU time 8.94 seconds
Started Apr 23 01:54:51 PM PDT 24
Finished Apr 23 01:55:01 PM PDT 24
Peak memory 230056 kb
Host smart-c2f3f895-a125-480f-b13d-d7f35ca54031
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834069127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3834069127
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1958680098
Short name T496
Test name
Test status
Simulation time 195525541 ps
CPU time 5.67 seconds
Started Apr 23 01:54:49 PM PDT 24
Finished Apr 23 01:54:56 PM PDT 24
Peak memory 208576 kb
Host smart-d323a4d8-cc50-4e85-b834-a67d36c12575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958680098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1958680098
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3954263660
Short name T866
Test name
Test status
Simulation time 359321547 ps
CPU time 3.33 seconds
Started Apr 23 01:54:52 PM PDT 24
Finished Apr 23 01:54:56 PM PDT 24
Peak memory 207504 kb
Host smart-5af43811-c12a-46a0-874f-b3955431cd04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954263660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3954263660
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3647970634
Short name T747
Test name
Test status
Simulation time 67584485 ps
CPU time 3.16 seconds
Started Apr 23 01:54:49 PM PDT 24
Finished Apr 23 01:54:53 PM PDT 24
Peak memory 207056 kb
Host smart-0820fd6f-ee0a-457e-8ae3-65167398c8d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647970634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3647970634
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2358105418
Short name T541
Test name
Test status
Simulation time 79677602 ps
CPU time 1.78 seconds
Started Apr 23 01:54:48 PM PDT 24
Finished Apr 23 01:54:50 PM PDT 24
Peak memory 206976 kb
Host smart-96141d43-e972-445c-8ea0-2460197f2742
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358105418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2358105418
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1730046988
Short name T884
Test name
Test status
Simulation time 220091111 ps
CPU time 1.67 seconds
Started Apr 23 01:54:50 PM PDT 24
Finished Apr 23 01:54:52 PM PDT 24
Peak memory 209108 kb
Host smart-ff9d92e9-3d68-4bb9-af2f-fc8951d3e5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730046988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1730046988
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1264829248
Short name T37
Test name
Test status
Simulation time 53087230 ps
CPU time 2.57 seconds
Started Apr 23 01:54:48 PM PDT 24
Finished Apr 23 01:54:51 PM PDT 24
Peak memory 206720 kb
Host smart-1c6b95f0-71a0-4e43-b179-0fa3c01aa76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264829248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1264829248
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1146683275
Short name T336
Test name
Test status
Simulation time 1331099856 ps
CPU time 18.22 seconds
Started Apr 23 01:54:53 PM PDT 24
Finished Apr 23 01:55:11 PM PDT 24
Peak memory 222740 kb
Host smart-e5fd7159-3200-4865-90d7-841bcfeab25b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146683275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1146683275
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2877371562
Short name T743
Test name
Test status
Simulation time 293465337 ps
CPU time 8.78 seconds
Started Apr 23 01:54:50 PM PDT 24
Finished Apr 23 01:54:59 PM PDT 24
Peak memory 209660 kb
Host smart-b54918a4-c79b-42b1-a44b-d7b4e6b42af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877371562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2877371562
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2330083533
Short name T873
Test name
Test status
Simulation time 102464948 ps
CPU time 2.95 seconds
Started Apr 23 01:54:52 PM PDT 24
Finished Apr 23 01:54:56 PM PDT 24
Peak memory 210436 kb
Host smart-2930b87d-99df-47ab-b54f-40b4623f726e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330083533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2330083533
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1893503844
Short name T598
Test name
Test status
Simulation time 44315148 ps
CPU time 0.77 seconds
Started Apr 23 01:56:44 PM PDT 24
Finished Apr 23 01:56:46 PM PDT 24
Peak memory 206024 kb
Host smart-9c07ccc9-de1f-4c59-bac6-a6c4dac1ada6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893503844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1893503844
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.936778506
Short name T246
Test name
Test status
Simulation time 209309563 ps
CPU time 4.49 seconds
Started Apr 23 01:56:36 PM PDT 24
Finished Apr 23 01:56:41 PM PDT 24
Peak memory 214588 kb
Host smart-02b4586d-abc0-4e6b-9ea0-d5cf065f127b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936778506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.936778506
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1455368664
Short name T26
Test name
Test status
Simulation time 2484788751 ps
CPU time 24.08 seconds
Started Apr 23 01:56:39 PM PDT 24
Finished Apr 23 01:57:04 PM PDT 24
Peak memory 209532 kb
Host smart-256ad190-2c43-475b-8580-965458f32aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455368664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1455368664
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.496001017
Short name T870
Test name
Test status
Simulation time 1579111019 ps
CPU time 4.19 seconds
Started Apr 23 01:56:42 PM PDT 24
Finished Apr 23 01:56:47 PM PDT 24
Peak memory 222316 kb
Host smart-fa6188bd-3bb5-41c2-b5e5-bf81544445d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496001017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.496001017
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.81130505
Short name T342
Test name
Test status
Simulation time 565230835 ps
CPU time 4.89 seconds
Started Apr 23 01:56:35 PM PDT 24
Finished Apr 23 01:56:40 PM PDT 24
Peak memory 214524 kb
Host smart-43e8a550-71aa-4211-8d8d-3e1815e2ea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81130505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.81130505
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3573752809
Short name T602
Test name
Test status
Simulation time 64903015 ps
CPU time 2.16 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:56:41 PM PDT 24
Peak memory 206408 kb
Host smart-857aff19-d760-4857-a62b-2c1a82593be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573752809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3573752809
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.607922887
Short name T518
Test name
Test status
Simulation time 378421304 ps
CPU time 4.66 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 209608 kb
Host smart-a92356ab-630b-4f51-8c6a-9ec261cde9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607922887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.607922887
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.108972079
Short name T459
Test name
Test status
Simulation time 35957602 ps
CPU time 2.24 seconds
Started Apr 23 01:56:35 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 207004 kb
Host smart-fb188501-9291-40ee-83dc-d4e7c49c7872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108972079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.108972079
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3970634749
Short name T568
Test name
Test status
Simulation time 8058443504 ps
CPU time 53.99 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:57:33 PM PDT 24
Peak memory 208504 kb
Host smart-e453c7d2-2c47-4d6c-a59e-b77d2cc54356
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970634749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3970634749
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1831538245
Short name T104
Test name
Test status
Simulation time 126455977 ps
CPU time 2.41 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:56:42 PM PDT 24
Peak memory 207500 kb
Host smart-47801804-ac78-46d9-91be-90b5931d4d3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831538245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1831538245
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2375277456
Short name T19
Test name
Test status
Simulation time 361090882 ps
CPU time 3.18 seconds
Started Apr 23 01:56:35 PM PDT 24
Finished Apr 23 01:56:39 PM PDT 24
Peak memory 207092 kb
Host smart-f096ac8f-783e-4eff-aed0-b3e573c6613f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375277456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2375277456
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1515160458
Short name T840
Test name
Test status
Simulation time 38917490 ps
CPU time 2.42 seconds
Started Apr 23 01:56:41 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 210076 kb
Host smart-11f30635-4805-4b6e-b326-811ff74a05af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515160458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1515160458
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3738210575
Short name T608
Test name
Test status
Simulation time 517799276 ps
CPU time 3.24 seconds
Started Apr 23 01:56:37 PM PDT 24
Finished Apr 23 01:56:40 PM PDT 24
Peak memory 206856 kb
Host smart-d6e93e44-131c-4355-af19-0744422c2843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738210575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3738210575
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3751860125
Short name T844
Test name
Test status
Simulation time 12374602821 ps
CPU time 372.05 seconds
Started Apr 23 01:56:37 PM PDT 24
Finished Apr 23 02:02:50 PM PDT 24
Peak memory 222816 kb
Host smart-e407845e-f0cc-4c0a-ad91-ab89b709a722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751860125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3751860125
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3483731327
Short name T753
Test name
Test status
Simulation time 325834046 ps
CPU time 9.9 seconds
Started Apr 23 01:56:39 PM PDT 24
Finished Apr 23 01:56:49 PM PDT 24
Peak memory 207280 kb
Host smart-c54bd42f-5e92-474d-8751-a56cc9bc2617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483731327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3483731327
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1975659494
Short name T57
Test name
Test status
Simulation time 151666012 ps
CPU time 2.25 seconds
Started Apr 23 01:56:35 PM PDT 24
Finished Apr 23 01:56:38 PM PDT 24
Peak memory 210356 kb
Host smart-c1b2ccd5-8b92-4dff-a4ee-651f25641164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975659494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1975659494
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.640371334
Short name T16
Test name
Test status
Simulation time 18575194 ps
CPU time 0.71 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:56:40 PM PDT 24
Peak memory 206064 kb
Host smart-4f879326-df47-494b-9443-425ee9677595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640371334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.640371334
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1045776529
Short name T420
Test name
Test status
Simulation time 492380470 ps
CPU time 13.11 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:56 PM PDT 24
Peak memory 214552 kb
Host smart-d1a59fbe-5ce4-49c0-9c82-8de6308dd891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1045776529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1045776529
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2592910300
Short name T515
Test name
Test status
Simulation time 56378070 ps
CPU time 2.69 seconds
Started Apr 23 01:56:42 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 206924 kb
Host smart-3e84869c-3663-4fda-a0ac-e1085ec7d534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592910300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2592910300
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.572843409
Short name T317
Test name
Test status
Simulation time 74301242 ps
CPU time 3.79 seconds
Started Apr 23 01:56:39 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 209684 kb
Host smart-e3d24d84-d0aa-4627-95b2-9c1c4fb94e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572843409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.572843409
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3061304711
Short name T688
Test name
Test status
Simulation time 363929570 ps
CPU time 3.57 seconds
Started Apr 23 01:56:40 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 222588 kb
Host smart-f633f964-f5f2-45e2-ab73-dd2012350afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061304711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3061304711
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2173854859
Short name T738
Test name
Test status
Simulation time 99766529 ps
CPU time 3.15 seconds
Started Apr 23 01:56:39 PM PDT 24
Finished Apr 23 01:56:43 PM PDT 24
Peak memory 208624 kb
Host smart-b88a376c-17a2-4b98-ad88-26f1846485ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173854859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2173854859
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2903339828
Short name T875
Test name
Test status
Simulation time 94470262 ps
CPU time 2.12 seconds
Started Apr 23 01:56:36 PM PDT 24
Finished Apr 23 01:56:39 PM PDT 24
Peak memory 208216 kb
Host smart-fcf55d85-2dd4-423d-af14-c43008394c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903339828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2903339828
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4013988730
Short name T404
Test name
Test status
Simulation time 101603289 ps
CPU time 4.01 seconds
Started Apr 23 01:56:44 PM PDT 24
Finished Apr 23 01:56:49 PM PDT 24
Peak memory 208008 kb
Host smart-3d514356-a408-4adf-8069-47ff4b2ee058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013988730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4013988730
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1811644976
Short name T582
Test name
Test status
Simulation time 2042678221 ps
CPU time 44.12 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:57:23 PM PDT 24
Peak memory 208020 kb
Host smart-8b945a99-e6e0-4d5a-b057-0b2feb7fec20
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811644976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1811644976
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2205193656
Short name T521
Test name
Test status
Simulation time 267728222 ps
CPU time 4.49 seconds
Started Apr 23 01:56:39 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 207124 kb
Host smart-e5e7610a-5bcd-4a64-b143-1a61aebcb142
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205193656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2205193656
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3516669357
Short name T399
Test name
Test status
Simulation time 99093391 ps
CPU time 4.33 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 209056 kb
Host smart-7aaef6c9-1185-4a97-8a0e-2a29f74a8c0d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516669357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3516669357
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1996060764
Short name T650
Test name
Test status
Simulation time 737130099 ps
CPU time 1.93 seconds
Started Apr 23 01:56:38 PM PDT 24
Finished Apr 23 01:56:41 PM PDT 24
Peak memory 207632 kb
Host smart-6dd78dad-1b5d-4600-9392-444569075410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996060764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1996060764
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1173445230
Short name T455
Test name
Test status
Simulation time 1172283792 ps
CPU time 8.51 seconds
Started Apr 23 01:56:36 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 208732 kb
Host smart-c920bcf4-b6d7-411b-b75b-cf110be07836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173445230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1173445230
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2258585303
Short name T44
Test name
Test status
Simulation time 1690017027 ps
CPU time 20.01 seconds
Started Apr 23 01:56:44 PM PDT 24
Finished Apr 23 01:57:05 PM PDT 24
Peak memory 221396 kb
Host smart-e3849702-383e-4dda-875c-f0dfce6c9623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258585303 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2258585303
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2325804836
Short name T713
Test name
Test status
Simulation time 247294972 ps
CPU time 4.47 seconds
Started Apr 23 01:56:40 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 208232 kb
Host smart-0d222d82-f5a3-43b1-afac-5a2c3f0a39a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325804836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2325804836
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2366632509
Short name T879
Test name
Test status
Simulation time 43600308 ps
CPU time 2.1 seconds
Started Apr 23 01:56:41 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 209888 kb
Host smart-936d5b45-7fd5-4934-a28a-ef424dc7f73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366632509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2366632509
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1723777102
Short name T81
Test name
Test status
Simulation time 16288237 ps
CPU time 0.73 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 206112 kb
Host smart-460f0336-2751-4fa0-847a-8eb332799f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723777102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1723777102
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1268091697
Short name T423
Test name
Test status
Simulation time 107961621 ps
CPU time 4.23 seconds
Started Apr 23 01:56:46 PM PDT 24
Finished Apr 23 01:56:51 PM PDT 24
Peak memory 214596 kb
Host smart-8093343c-de16-45e6-935b-de0c7bb58304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268091697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1268091697
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.446058681
Short name T701
Test name
Test status
Simulation time 681586456 ps
CPU time 5.21 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:49 PM PDT 24
Peak memory 210300 kb
Host smart-793c5542-0ecd-457d-a82e-03de414c0bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446058681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.446058681
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1139622719
Short name T483
Test name
Test status
Simulation time 91202273 ps
CPU time 2.35 seconds
Started Apr 23 01:56:42 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 208176 kb
Host smart-2f9307f4-5128-4cdc-afe8-53cc179d522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139622719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1139622719
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1522660463
Short name T761
Test name
Test status
Simulation time 175846913 ps
CPU time 2.55 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:46 PM PDT 24
Peak memory 214560 kb
Host smart-6c050d02-bbce-4271-a875-c65367686eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522660463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1522660463
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.4171332492
Short name T687
Test name
Test status
Simulation time 1006848941 ps
CPU time 11.08 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:54 PM PDT 24
Peak memory 210504 kb
Host smart-889f8224-98ee-42ec-abb8-575bf23d6a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171332492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.4171332492
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1966809549
Short name T208
Test name
Test status
Simulation time 108458403 ps
CPU time 2.85 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:47 PM PDT 24
Peak memory 210112 kb
Host smart-eb2baec1-d1b3-46e8-b76b-96af3e50eb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966809549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1966809549
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.841530323
Short name T725
Test name
Test status
Simulation time 232193647 ps
CPU time 5.18 seconds
Started Apr 23 01:56:39 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 209260 kb
Host smart-8e0610c9-a172-4768-b7fb-63fbebf8c620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841530323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.841530323
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3531878969
Short name T809
Test name
Test status
Simulation time 109971831 ps
CPU time 3.1 seconds
Started Apr 23 01:56:41 PM PDT 24
Finished Apr 23 01:56:44 PM PDT 24
Peak memory 208576 kb
Host smart-b69f396e-d847-4f6e-93ea-91a6ce5cf4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531878969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3531878969
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3803914167
Short name T796
Test name
Test status
Simulation time 1659866286 ps
CPU time 19.24 seconds
Started Apr 23 01:56:41 PM PDT 24
Finished Apr 23 01:57:01 PM PDT 24
Peak memory 208332 kb
Host smart-e02f2c3b-3771-4b49-bec1-d9280b3b8c3f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803914167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3803914167
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.4056299973
Short name T435
Test name
Test status
Simulation time 127858163 ps
CPU time 2.82 seconds
Started Apr 23 01:56:42 PM PDT 24
Finished Apr 23 01:56:46 PM PDT 24
Peak memory 206960 kb
Host smart-2ce3fad0-0e1e-4e4f-8e0c-0e09ee9308ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056299973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.4056299973
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1652267950
Short name T867
Test name
Test status
Simulation time 398089690 ps
CPU time 8.1 seconds
Started Apr 23 01:56:41 PM PDT 24
Finished Apr 23 01:56:50 PM PDT 24
Peak memory 208012 kb
Host smart-23fff4ab-c6d1-4bd6-b61e-8f1fff96487c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652267950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1652267950
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.834212047
Short name T881
Test name
Test status
Simulation time 55032426 ps
CPU time 2.74 seconds
Started Apr 23 01:56:45 PM PDT 24
Finished Apr 23 01:56:48 PM PDT 24
Peak memory 216340 kb
Host smart-1768828f-2b54-4a8b-9963-be94a830d141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834212047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.834212047
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2958299994
Short name T458
Test name
Test status
Simulation time 65620240 ps
CPU time 3.04 seconds
Started Apr 23 01:56:39 PM PDT 24
Finished Apr 23 01:56:43 PM PDT 24
Peak memory 207968 kb
Host smart-f35f7923-9b96-4847-9ffe-cf850e6197e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958299994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2958299994
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3661518718
Short name T124
Test name
Test status
Simulation time 205513331 ps
CPU time 13.81 seconds
Started Apr 23 01:56:44 PM PDT 24
Finished Apr 23 01:56:58 PM PDT 24
Peak memory 222896 kb
Host smart-02add529-25d9-4465-8d19-946392dab061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661518718 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3661518718
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2813443314
Short name T195
Test name
Test status
Simulation time 555667176 ps
CPU time 6.89 seconds
Started Apr 23 01:56:44 PM PDT 24
Finished Apr 23 01:56:52 PM PDT 24
Peak memory 208804 kb
Host smart-006dade9-60a2-4c61-a46f-7bb76e0640c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813443314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2813443314
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3917162249
Short name T659
Test name
Test status
Simulation time 153619357 ps
CPU time 1.76 seconds
Started Apr 23 01:56:45 PM PDT 24
Finished Apr 23 01:56:48 PM PDT 24
Peak memory 209912 kb
Host smart-694e94c2-d893-49ed-970c-800a7eaf121d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917162249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3917162249
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2359468126
Short name T600
Test name
Test status
Simulation time 17560375 ps
CPU time 0.93 seconds
Started Apr 23 01:56:46 PM PDT 24
Finished Apr 23 01:56:47 PM PDT 24
Peak memory 206276 kb
Host smart-adcb9d11-3b6e-4eec-8e94-d6977a16dc7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359468126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2359468126
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.848227560
Short name T294
Test name
Test status
Simulation time 38146309 ps
CPU time 3.04 seconds
Started Apr 23 01:56:48 PM PDT 24
Finished Apr 23 01:56:52 PM PDT 24
Peak memory 214828 kb
Host smart-b33160c3-d57a-4bda-aca3-3c54f41b1be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848227560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.848227560
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1439171442
Short name T30
Test name
Test status
Simulation time 126869109 ps
CPU time 5.76 seconds
Started Apr 23 01:56:48 PM PDT 24
Finished Apr 23 01:56:54 PM PDT 24
Peak memory 209960 kb
Host smart-6ae688a3-f0f2-4e6c-b869-c6e11a742ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439171442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1439171442
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3108368149
Short name T100
Test name
Test status
Simulation time 2834390768 ps
CPU time 26.52 seconds
Started Apr 23 01:56:45 PM PDT 24
Finished Apr 23 01:57:13 PM PDT 24
Peak memory 218664 kb
Host smart-308c0d79-7de8-4a1b-83c7-c3079bf55599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108368149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3108368149
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1403887005
Short name T248
Test name
Test status
Simulation time 160707472 ps
CPU time 3.97 seconds
Started Apr 23 01:56:48 PM PDT 24
Finished Apr 23 01:56:53 PM PDT 24
Peak memory 210748 kb
Host smart-be64d1e2-eac6-420b-aff8-eb6de2e85391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403887005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1403887005
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.979977394
Short name T414
Test name
Test status
Simulation time 31300038 ps
CPU time 2.43 seconds
Started Apr 23 01:56:53 PM PDT 24
Finished Apr 23 01:56:56 PM PDT 24
Peak memory 209420 kb
Host smart-d611039a-4434-4bcc-b12c-f1ae4404b2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979977394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.979977394
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.608056151
Short name T356
Test name
Test status
Simulation time 1280582165 ps
CPU time 32.47 seconds
Started Apr 23 01:56:44 PM PDT 24
Finished Apr 23 01:57:17 PM PDT 24
Peak memory 210704 kb
Host smart-ff4b2b88-5983-47be-baea-657e1c6f4e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608056151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.608056151
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3165367033
Short name T734
Test name
Test status
Simulation time 208551730 ps
CPU time 4.72 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:48 PM PDT 24
Peak memory 206952 kb
Host smart-58eec464-4161-422d-a760-6eb51243c152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165367033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3165367033
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1244864015
Short name T516
Test name
Test status
Simulation time 27920552 ps
CPU time 2.08 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 208788 kb
Host smart-62590a0f-5332-4f36-a1a3-fbe1493610c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244864015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1244864015
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3232922906
Short name T452
Test name
Test status
Simulation time 90865999 ps
CPU time 2.45 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 206352 kb
Host smart-ca3b3066-b2da-4abe-b953-a6434d165f16
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232922906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3232922906
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1958316241
Short name T674
Test name
Test status
Simulation time 98531608 ps
CPU time 2 seconds
Started Apr 23 01:56:43 PM PDT 24
Finished Apr 23 01:56:45 PM PDT 24
Peak memory 207880 kb
Host smart-d8465068-e753-4c3e-b75f-7c25716a712a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958316241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1958316241
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.760510581
Short name T237
Test name
Test status
Simulation time 131179740 ps
CPU time 2.76 seconds
Started Apr 23 01:56:48 PM PDT 24
Finished Apr 23 01:56:52 PM PDT 24
Peak memory 210004 kb
Host smart-e7037833-a77b-43be-bd3f-3fa747655e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760510581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.760510581
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.4245663062
Short name T430
Test name
Test status
Simulation time 37802550 ps
CPU time 2.26 seconds
Started Apr 23 01:56:45 PM PDT 24
Finished Apr 23 01:56:48 PM PDT 24
Peak memory 207064 kb
Host smart-87e91cfc-2ebb-4b4b-8316-aa49379b4a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245663062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.4245663062
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.4258362973
Short name T283
Test name
Test status
Simulation time 16122183417 ps
CPU time 513.75 seconds
Started Apr 23 01:56:47 PM PDT 24
Finished Apr 23 02:05:21 PM PDT 24
Peak memory 220612 kb
Host smart-f50e23d2-38ca-4dbb-9ed9-cdd1590cb1e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258362973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4258362973
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1881970755
Short name T845
Test name
Test status
Simulation time 487758907 ps
CPU time 7.95 seconds
Started Apr 23 01:56:45 PM PDT 24
Finished Apr 23 01:56:54 PM PDT 24
Peak memory 222940 kb
Host smart-30abee86-50f1-4e9e-ae29-9b481fb4f754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881970755 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1881970755
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2019220705
Short name T696
Test name
Test status
Simulation time 192131407 ps
CPU time 3.46 seconds
Started Apr 23 01:56:47 PM PDT 24
Finished Apr 23 01:56:51 PM PDT 24
Peak memory 208120 kb
Host smart-db31c62b-dd0a-4022-876a-f15ad31c6a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019220705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2019220705
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1738201710
Short name T386
Test name
Test status
Simulation time 185972128 ps
CPU time 2.35 seconds
Started Apr 23 01:56:44 PM PDT 24
Finished Apr 23 01:56:47 PM PDT 24
Peak memory 210284 kb
Host smart-77fd2e75-6051-4918-afd2-e6edd0343cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738201710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1738201710
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3698688432
Short name T838
Test name
Test status
Simulation time 10741376 ps
CPU time 0.86 seconds
Started Apr 23 01:56:50 PM PDT 24
Finished Apr 23 01:56:51 PM PDT 24
Peak memory 206128 kb
Host smart-6003fc42-9dac-417d-8515-0de3193f4209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698688432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3698688432
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1287317119
Short name T636
Test name
Test status
Simulation time 237537162 ps
CPU time 5.75 seconds
Started Apr 23 01:56:50 PM PDT 24
Finished Apr 23 01:56:56 PM PDT 24
Peak memory 209984 kb
Host smart-7a99ed4c-fe60-4981-afaa-41c972b6d35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287317119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1287317119
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.118856171
Short name T857
Test name
Test status
Simulation time 169717609 ps
CPU time 4.39 seconds
Started Apr 23 01:56:52 PM PDT 24
Finished Apr 23 01:56:57 PM PDT 24
Peak memory 209800 kb
Host smart-679d95f9-de00-4659-82fe-0a3a9d6998da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118856171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.118856171
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3757043724
Short name T289
Test name
Test status
Simulation time 102017083 ps
CPU time 3.44 seconds
Started Apr 23 01:56:48 PM PDT 24
Finished Apr 23 01:56:52 PM PDT 24
Peak memory 214612 kb
Host smart-1a28a986-14c9-4091-a09e-f239f5a350d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757043724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3757043724
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3700873060
Short name T252
Test name
Test status
Simulation time 114136047 ps
CPU time 5.01 seconds
Started Apr 23 01:56:48 PM PDT 24
Finished Apr 23 01:56:53 PM PDT 24
Peak memory 211056 kb
Host smart-1c8f2428-92b2-4fab-95a7-c402e007066a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700873060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3700873060
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.612975576
Short name T793
Test name
Test status
Simulation time 708116721 ps
CPU time 4.1 seconds
Started Apr 23 01:56:49 PM PDT 24
Finished Apr 23 01:56:53 PM PDT 24
Peak memory 210224 kb
Host smart-eab73fb3-2c84-488f-9664-bd57e50bf79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612975576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.612975576
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.823981806
Short name T465
Test name
Test status
Simulation time 633111873 ps
CPU time 17.41 seconds
Started Apr 23 01:56:47 PM PDT 24
Finished Apr 23 01:57:05 PM PDT 24
Peak memory 214524 kb
Host smart-4cac98cc-2231-4283-a65d-1a4462e44356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823981806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.823981806
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1480427093
Short name T548
Test name
Test status
Simulation time 6360490375 ps
CPU time 70.64 seconds
Started Apr 23 01:56:47 PM PDT 24
Finished Apr 23 01:57:58 PM PDT 24
Peak memory 208704 kb
Host smart-d4eec095-9b83-4adb-bab0-d332852d5b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480427093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1480427093
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1933358782
Short name T478
Test name
Test status
Simulation time 175783188 ps
CPU time 2.57 seconds
Started Apr 23 01:56:49 PM PDT 24
Finished Apr 23 01:56:52 PM PDT 24
Peak memory 206988 kb
Host smart-f3d11bb6-a390-4d85-9b16-6eb43fdb39dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933358782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1933358782
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1036431806
Short name T335
Test name
Test status
Simulation time 1025476149 ps
CPU time 8.36 seconds
Started Apr 23 01:56:53 PM PDT 24
Finished Apr 23 01:57:02 PM PDT 24
Peak memory 207792 kb
Host smart-b788a29d-45ba-41b7-bcdd-534e42795028
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036431806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1036431806
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1186478247
Short name T771
Test name
Test status
Simulation time 105451820 ps
CPU time 2.7 seconds
Started Apr 23 01:56:49 PM PDT 24
Finished Apr 23 01:56:52 PM PDT 24
Peak memory 208416 kb
Host smart-80a9afbd-752e-48d6-b687-2bd51b62d19f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186478247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1186478247
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1743574405
Short name T603
Test name
Test status
Simulation time 1075580893 ps
CPU time 3.98 seconds
Started Apr 23 01:56:50 PM PDT 24
Finished Apr 23 01:56:54 PM PDT 24
Peak memory 214576 kb
Host smart-fca88f34-96f0-4674-8e6c-b1a9608574b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743574405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1743574405
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1091488350
Short name T1
Test name
Test status
Simulation time 178024037 ps
CPU time 6 seconds
Started Apr 23 01:56:48 PM PDT 24
Finished Apr 23 01:56:55 PM PDT 24
Peak memory 206916 kb
Host smart-06f3effb-77f5-490b-906a-e200da6a1ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091488350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1091488350
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1287760138
Short name T328
Test name
Test status
Simulation time 1264801961 ps
CPU time 38.9 seconds
Started Apr 23 01:56:47 PM PDT 24
Finished Apr 23 01:57:26 PM PDT 24
Peak memory 215640 kb
Host smart-3cf2ce02-630c-4dff-a800-e18492b3d991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287760138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1287760138
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3168433752
Short name T122
Test name
Test status
Simulation time 387864212 ps
CPU time 21.17 seconds
Started Apr 23 01:56:49 PM PDT 24
Finished Apr 23 01:57:11 PM PDT 24
Peak memory 221876 kb
Host smart-1bc68929-7b37-4785-9c68-d6e0f764434b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168433752 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3168433752
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.175140613
Short name T175
Test name
Test status
Simulation time 74845631 ps
CPU time 3.69 seconds
Started Apr 23 01:56:51 PM PDT 24
Finished Apr 23 01:56:55 PM PDT 24
Peak memory 208184 kb
Host smart-700ee7fb-3692-4208-9775-cf666a6e465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175140613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.175140613
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1846508333
Short name T846
Test name
Test status
Simulation time 19103000 ps
CPU time 0.77 seconds
Started Apr 23 01:56:59 PM PDT 24
Finished Apr 23 01:57:00 PM PDT 24
Peak memory 206216 kb
Host smart-e423298a-1c9c-4b89-8644-484075991cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846508333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1846508333
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1951021609
Short name T116
Test name
Test status
Simulation time 155050828 ps
CPU time 3.54 seconds
Started Apr 23 01:56:52 PM PDT 24
Finished Apr 23 01:56:56 PM PDT 24
Peak memory 215496 kb
Host smart-b6a10333-d0e8-45bd-ac58-b726bd900ffe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951021609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1951021609
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1340663187
Short name T839
Test name
Test status
Simulation time 240702585 ps
CPU time 2.62 seconds
Started Apr 23 01:56:51 PM PDT 24
Finished Apr 23 01:56:54 PM PDT 24
Peak memory 208312 kb
Host smart-c9326eff-d7ca-4065-8e84-34da4cfbec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340663187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1340663187
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3438306454
Short name T368
Test name
Test status
Simulation time 28126825 ps
CPU time 2.12 seconds
Started Apr 23 01:56:53 PM PDT 24
Finished Apr 23 01:56:55 PM PDT 24
Peak memory 214480 kb
Host smart-036d94b0-b581-4e5f-b12c-24f3d29d31ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438306454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3438306454
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.423366429
Short name T749
Test name
Test status
Simulation time 107323710 ps
CPU time 3.53 seconds
Started Apr 23 01:56:53 PM PDT 24
Finished Apr 23 01:56:57 PM PDT 24
Peak memory 214556 kb
Host smart-2b0e4a03-6ec6-4991-8770-85aae1221058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423366429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.423366429
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3051379607
Short name T249
Test name
Test status
Simulation time 180611358 ps
CPU time 3.53 seconds
Started Apr 23 01:56:53 PM PDT 24
Finished Apr 23 01:56:57 PM PDT 24
Peak memory 214624 kb
Host smart-8252a12f-2e92-48d9-a690-42fc58c0b13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051379607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3051379607
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2606803919
Short name T690
Test name
Test status
Simulation time 133002223 ps
CPU time 2.67 seconds
Started Apr 23 01:56:53 PM PDT 24
Finished Apr 23 01:56:57 PM PDT 24
Peak memory 220732 kb
Host smart-9b71ed1c-a19d-45c9-92bd-b40e27d88523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606803919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2606803919
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3596578954
Short name T413
Test name
Test status
Simulation time 463677190 ps
CPU time 5.18 seconds
Started Apr 23 01:56:53 PM PDT 24
Finished Apr 23 01:56:59 PM PDT 24
Peak memory 207712 kb
Host smart-2dcf3886-208f-4377-b512-90d6df9c783b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596578954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3596578954
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1963368515
Short name T531
Test name
Test status
Simulation time 62296267 ps
CPU time 3.2 seconds
Started Apr 23 01:56:52 PM PDT 24
Finished Apr 23 01:56:56 PM PDT 24
Peak memory 208552 kb
Host smart-9419bb33-c757-482f-8447-fd20fb1629e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963368515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1963368515
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.4209265810
Short name T84
Test name
Test status
Simulation time 76616057 ps
CPU time 2.41 seconds
Started Apr 23 01:56:49 PM PDT 24
Finished Apr 23 01:56:52 PM PDT 24
Peak memory 207024 kb
Host smart-886c6cc8-dca4-4cb0-b926-89d847599bb8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209265810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.4209265810
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2215433774
Short name T490
Test name
Test status
Simulation time 192538585 ps
CPU time 5.72 seconds
Started Apr 23 01:56:55 PM PDT 24
Finished Apr 23 01:57:01 PM PDT 24
Peak memory 208244 kb
Host smart-7be056b6-f14a-4b39-9351-08c53fff07cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215433774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2215433774
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3400249931
Short name T351
Test name
Test status
Simulation time 726516332 ps
CPU time 5.08 seconds
Started Apr 23 01:56:51 PM PDT 24
Finished Apr 23 01:56:57 PM PDT 24
Peak memory 209704 kb
Host smart-c79754ed-fe31-413c-9894-ada7e031b810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400249931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3400249931
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2230158504
Short name T593
Test name
Test status
Simulation time 374213496 ps
CPU time 8.18 seconds
Started Apr 23 01:56:53 PM PDT 24
Finished Apr 23 01:57:02 PM PDT 24
Peak memory 208616 kb
Host smart-d48d6642-4676-4147-9f89-8dbb2fb9cc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230158504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2230158504
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2225492568
Short name T804
Test name
Test status
Simulation time 2727830379 ps
CPU time 36.08 seconds
Started Apr 23 01:56:54 PM PDT 24
Finished Apr 23 01:57:30 PM PDT 24
Peak memory 217568 kb
Host smart-a07ad91e-5605-4564-8c21-c67e3ebb7a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225492568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2225492568
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1748971037
Short name T357
Test name
Test status
Simulation time 485663295 ps
CPU time 8.08 seconds
Started Apr 23 01:56:54 PM PDT 24
Finished Apr 23 01:57:03 PM PDT 24
Peak memory 214604 kb
Host smart-d6ed0777-3637-4c39-a74e-25a134c96122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748971037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1748971037
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1790162710
Short name T403
Test name
Test status
Simulation time 103131436 ps
CPU time 1.95 seconds
Started Apr 23 01:56:53 PM PDT 24
Finished Apr 23 01:56:55 PM PDT 24
Peak memory 210308 kb
Host smart-5896f09a-58f4-4d45-a555-a50fb6775362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790162710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1790162710
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2960974816
Short name T822
Test name
Test status
Simulation time 34833894 ps
CPU time 0.82 seconds
Started Apr 23 01:56:59 PM PDT 24
Finished Apr 23 01:57:01 PM PDT 24
Peak memory 206128 kb
Host smart-aa4d01df-7e66-4ac2-b611-2d0649b2b112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960974816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2960974816
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2532339645
Short name T31
Test name
Test status
Simulation time 277358903 ps
CPU time 6.17 seconds
Started Apr 23 01:57:01 PM PDT 24
Finished Apr 23 01:57:08 PM PDT 24
Peak memory 208704 kb
Host smart-eb474671-cc72-48bb-a977-9e71ecba49bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532339645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2532339645
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2627997161
Short name T629
Test name
Test status
Simulation time 63704767 ps
CPU time 1.35 seconds
Started Apr 23 01:56:54 PM PDT 24
Finished Apr 23 01:56:56 PM PDT 24
Peak memory 207192 kb
Host smart-88e90e9a-e85c-40dc-a1e8-34d24ad42cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627997161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2627997161
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2051739581
Short name T661
Test name
Test status
Simulation time 145202450 ps
CPU time 3.61 seconds
Started Apr 23 01:56:58 PM PDT 24
Finished Apr 23 01:57:02 PM PDT 24
Peak memory 214480 kb
Host smart-0d165d7c-8f0e-4a1f-9e44-db3898eb2bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051739581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2051739581
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1143671334
Short name T787
Test name
Test status
Simulation time 151346146 ps
CPU time 2.72 seconds
Started Apr 23 01:56:55 PM PDT 24
Finished Apr 23 01:56:58 PM PDT 24
Peak memory 222592 kb
Host smart-4ddfafee-fdf6-431e-b3de-55398391fda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143671334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1143671334
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2477234850
Short name T54
Test name
Test status
Simulation time 304584476 ps
CPU time 4.88 seconds
Started Apr 23 01:56:58 PM PDT 24
Finished Apr 23 01:57:03 PM PDT 24
Peak memory 222812 kb
Host smart-04a58c0f-4f65-4ee6-8092-5f7761a27110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477234850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2477234850
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1164895134
Short name T797
Test name
Test status
Simulation time 156027457 ps
CPU time 5.07 seconds
Started Apr 23 01:56:56 PM PDT 24
Finished Apr 23 01:57:02 PM PDT 24
Peak memory 214492 kb
Host smart-08a87da8-fb09-43e4-b535-88bc98689370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164895134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1164895134
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2452591584
Short name T571
Test name
Test status
Simulation time 52075647 ps
CPU time 2.63 seconds
Started Apr 23 01:56:55 PM PDT 24
Finished Apr 23 01:56:58 PM PDT 24
Peak memory 206992 kb
Host smart-57d3fbfc-0fc1-4e40-a299-c8c3cee9f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452591584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2452591584
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.823185122
Short name T439
Test name
Test status
Simulation time 72671848 ps
CPU time 3.23 seconds
Started Apr 23 01:56:54 PM PDT 24
Finished Apr 23 01:56:58 PM PDT 24
Peak memory 207380 kb
Host smart-5f835bf1-0452-4a4c-8f3b-14c3aa50add2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823185122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.823185122
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2639883213
Short name T891
Test name
Test status
Simulation time 387261864 ps
CPU time 2.49 seconds
Started Apr 23 01:56:54 PM PDT 24
Finished Apr 23 01:56:57 PM PDT 24
Peak memory 206952 kb
Host smart-86e80a65-f8f0-48b7-a84d-449642a8318b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639883213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2639883213
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3865368652
Short name T717
Test name
Test status
Simulation time 32634057 ps
CPU time 2.3 seconds
Started Apr 23 01:56:57 PM PDT 24
Finished Apr 23 01:57:00 PM PDT 24
Peak memory 206920 kb
Host smart-51ef4baa-7579-486e-b1b8-5dae59d71bce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865368652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3865368652
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.4254247466
Short name T652
Test name
Test status
Simulation time 448144529 ps
CPU time 3.57 seconds
Started Apr 23 01:56:56 PM PDT 24
Finished Apr 23 01:57:00 PM PDT 24
Peak memory 209336 kb
Host smart-2d87cdba-d7ab-483e-80b0-b50c7f5b6d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254247466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4254247466
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2922149275
Short name T199
Test name
Test status
Simulation time 761829648 ps
CPU time 8.88 seconds
Started Apr 23 01:56:57 PM PDT 24
Finished Apr 23 01:57:06 PM PDT 24
Peak memory 207980 kb
Host smart-539b5d30-3a5e-480e-bd9a-51d6b976be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922149275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2922149275
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2663364832
Short name T799
Test name
Test status
Simulation time 920045329 ps
CPU time 12.99 seconds
Started Apr 23 01:56:58 PM PDT 24
Finished Apr 23 01:57:11 PM PDT 24
Peak memory 222952 kb
Host smart-fce3f8a3-7c71-4664-afc8-b8ed4a6a57cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663364832 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2663364832
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.915392596
Short name T619
Test name
Test status
Simulation time 201314058 ps
CPU time 6.32 seconds
Started Apr 23 01:56:58 PM PDT 24
Finished Apr 23 01:57:04 PM PDT 24
Peak memory 207252 kb
Host smart-79152b4f-8d73-453d-817f-395e7570613b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915392596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.915392596
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1798019409
Short name T745
Test name
Test status
Simulation time 100270450 ps
CPU time 2.75 seconds
Started Apr 23 01:56:59 PM PDT 24
Finished Apr 23 01:57:02 PM PDT 24
Peak memory 210316 kb
Host smart-4ef07e72-a890-49fd-88fc-9de59b0b4411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798019409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1798019409
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1427937646
Short name T510
Test name
Test status
Simulation time 57578939 ps
CPU time 0.87 seconds
Started Apr 23 01:57:02 PM PDT 24
Finished Apr 23 01:57:03 PM PDT 24
Peak memory 206060 kb
Host smart-7f41e5ee-2cb5-4278-917b-2132de9b561b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427937646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1427937646
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2578835884
Short name T355
Test name
Test status
Simulation time 167192271 ps
CPU time 3.06 seconds
Started Apr 23 01:57:00 PM PDT 24
Finished Apr 23 01:57:03 PM PDT 24
Peak memory 214456 kb
Host smart-f8991260-f21b-416e-9339-6115ed9f0edf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578835884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2578835884
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.431806373
Short name T7
Test name
Test status
Simulation time 134561534 ps
CPU time 2.87 seconds
Started Apr 23 01:57:02 PM PDT 24
Finished Apr 23 01:57:05 PM PDT 24
Peak memory 217716 kb
Host smart-567926ff-1d2e-4401-b0ac-8447081d92c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431806373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.431806373
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1700232598
Short name T560
Test name
Test status
Simulation time 219261693 ps
CPU time 3.4 seconds
Started Apr 23 01:57:03 PM PDT 24
Finished Apr 23 01:57:07 PM PDT 24
Peak memory 209780 kb
Host smart-4bce816d-f604-4294-b78d-8ee122c15ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700232598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1700232598
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2449646545
Short name T746
Test name
Test status
Simulation time 1549196516 ps
CPU time 10.5 seconds
Started Apr 23 01:57:03 PM PDT 24
Finished Apr 23 01:57:14 PM PDT 24
Peak memory 221608 kb
Host smart-b63fdca4-d716-4141-95fe-bfece58cec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449646545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2449646545
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1657889697
Short name T254
Test name
Test status
Simulation time 1106052961 ps
CPU time 12.23 seconds
Started Apr 23 01:57:03 PM PDT 24
Finished Apr 23 01:57:16 PM PDT 24
Peak memory 211468 kb
Host smart-a4446493-1a93-45c2-8f1f-97f2ee589a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657889697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1657889697
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2780940408
Short name T835
Test name
Test status
Simulation time 253434306 ps
CPU time 3.64 seconds
Started Apr 23 01:57:02 PM PDT 24
Finished Apr 23 01:57:06 PM PDT 24
Peak memory 210024 kb
Host smart-b2022b9c-1326-4199-9652-0b5774514766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780940408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2780940408
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.755481707
Short name T482
Test name
Test status
Simulation time 260576015 ps
CPU time 3.94 seconds
Started Apr 23 01:57:01 PM PDT 24
Finished Apr 23 01:57:05 PM PDT 24
Peak memory 209536 kb
Host smart-563d1c2a-82c2-4f84-82d0-3ac45a5f1966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755481707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.755481707
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3047585505
Short name T298
Test name
Test status
Simulation time 2480781129 ps
CPU time 49.7 seconds
Started Apr 23 01:56:57 PM PDT 24
Finished Apr 23 01:57:47 PM PDT 24
Peak memory 208148 kb
Host smart-8034453a-9746-4efb-a148-d49f3fc7a7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047585505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3047585505
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1038045609
Short name T508
Test name
Test status
Simulation time 422362768 ps
CPU time 8.86 seconds
Started Apr 23 01:57:01 PM PDT 24
Finished Apr 23 01:57:11 PM PDT 24
Peak memory 208496 kb
Host smart-ff5f484c-1331-49ad-a258-bd4eac796796
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038045609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1038045609
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3702710363
Short name T501
Test name
Test status
Simulation time 259635984 ps
CPU time 3.45 seconds
Started Apr 23 01:57:00 PM PDT 24
Finished Apr 23 01:57:04 PM PDT 24
Peak memory 208124 kb
Host smart-450ee84c-c4a5-4881-bb26-277fcda71a1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702710363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3702710363
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2063783841
Short name T658
Test name
Test status
Simulation time 64521049 ps
CPU time 3.23 seconds
Started Apr 23 01:57:03 PM PDT 24
Finished Apr 23 01:57:07 PM PDT 24
Peak memory 208760 kb
Host smart-69a3d13e-4bde-4bc7-b3f2-0d2327aa4552
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063783841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2063783841
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3658296107
Short name T542
Test name
Test status
Simulation time 438974803 ps
CPU time 2.69 seconds
Started Apr 23 01:57:02 PM PDT 24
Finished Apr 23 01:57:06 PM PDT 24
Peak memory 209224 kb
Host smart-c5de251e-2bce-4ea9-a8dd-0c30a35d44d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658296107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3658296107
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3930562752
Short name T609
Test name
Test status
Simulation time 160511471 ps
CPU time 2.08 seconds
Started Apr 23 01:56:59 PM PDT 24
Finished Apr 23 01:57:01 PM PDT 24
Peak memory 208812 kb
Host smart-ca1f0539-ffb3-42f1-8537-7b4fd6653dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930562752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3930562752
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2939573973
Short name T895
Test name
Test status
Simulation time 493288707 ps
CPU time 13.41 seconds
Started Apr 23 01:57:03 PM PDT 24
Finished Apr 23 01:57:17 PM PDT 24
Peak memory 217148 kb
Host smart-61acb836-70d0-4252-82fb-8dcf5a86b68e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939573973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2939573973
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.13256113
Short name T128
Test name
Test status
Simulation time 593962498 ps
CPU time 2.72 seconds
Started Apr 23 01:57:04 PM PDT 24
Finished Apr 23 01:57:07 PM PDT 24
Peak memory 208348 kb
Host smart-40f8ef09-1144-4c66-ac72-83aeaaef165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13256113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.13256113
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3111241961
Short name T597
Test name
Test status
Simulation time 587283617 ps
CPU time 8.92 seconds
Started Apr 23 01:57:03 PM PDT 24
Finished Apr 23 01:57:12 PM PDT 24
Peak memory 211012 kb
Host smart-3a817b5b-a71c-42e9-9592-50780aea0fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111241961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3111241961
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2529301038
Short name T511
Test name
Test status
Simulation time 11528854 ps
CPU time 0.73 seconds
Started Apr 23 01:57:06 PM PDT 24
Finished Apr 23 01:57:07 PM PDT 24
Peak memory 206196 kb
Host smart-271c0aee-fb8d-42c0-9d49-e5f42fedf2be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529301038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2529301038
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1380706949
Short name T419
Test name
Test status
Simulation time 623638777 ps
CPU time 9.4 seconds
Started Apr 23 01:57:05 PM PDT 24
Finished Apr 23 01:57:15 PM PDT 24
Peak memory 215540 kb
Host smart-94303cce-ea42-42a5-92a2-c11d1b4b3e22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1380706949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1380706949
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.440512621
Short name T618
Test name
Test status
Simulation time 535104532 ps
CPU time 6.15 seconds
Started Apr 23 01:57:07 PM PDT 24
Finished Apr 23 01:57:13 PM PDT 24
Peak memory 210988 kb
Host smart-b42aee31-4fba-4aef-a0a7-06121acb71ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440512621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.440512621
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3730696014
Short name T70
Test name
Test status
Simulation time 69770968 ps
CPU time 2.77 seconds
Started Apr 23 01:57:02 PM PDT 24
Finished Apr 23 01:57:05 PM PDT 24
Peak memory 209680 kb
Host smart-bfa96df1-255a-4290-ad48-ddea72467e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730696014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3730696014
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1966061240
Short name T632
Test name
Test status
Simulation time 261076161 ps
CPU time 9.89 seconds
Started Apr 23 01:57:08 PM PDT 24
Finished Apr 23 01:57:19 PM PDT 24
Peak memory 221044 kb
Host smart-b27cd1a9-9924-4e81-b657-4da532e226a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966061240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1966061240
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1372809589
Short name T341
Test name
Test status
Simulation time 91633949 ps
CPU time 3.41 seconds
Started Apr 23 01:57:07 PM PDT 24
Finished Apr 23 01:57:10 PM PDT 24
Peak memory 222532 kb
Host smart-81948c32-07c4-49f2-a3f6-42fe2ae8a0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372809589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1372809589
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2859485380
Short name T702
Test name
Test status
Simulation time 209002042 ps
CPU time 3.85 seconds
Started Apr 23 01:57:05 PM PDT 24
Finished Apr 23 01:57:09 PM PDT 24
Peak memory 214572 kb
Host smart-a22aa75c-1366-469b-8b2b-0d54a747389b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859485380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2859485380
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3804908260
Short name T657
Test name
Test status
Simulation time 357662618 ps
CPU time 4.44 seconds
Started Apr 23 01:57:05 PM PDT 24
Finished Apr 23 01:57:10 PM PDT 24
Peak memory 218712 kb
Host smart-3df35134-76e0-4abd-9049-938f36b081f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804908260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3804908260
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.315906873
Short name T231
Test name
Test status
Simulation time 219689102 ps
CPU time 3.32 seconds
Started Apr 23 01:57:04 PM PDT 24
Finished Apr 23 01:57:08 PM PDT 24
Peak memory 206944 kb
Host smart-5a467c0c-479f-4730-8f1f-9fbd7e310c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315906873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.315906873
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2361894957
Short name T684
Test name
Test status
Simulation time 126904001 ps
CPU time 2.5 seconds
Started Apr 23 01:57:04 PM PDT 24
Finished Apr 23 01:57:07 PM PDT 24
Peak memory 208976 kb
Host smart-72ecc44d-68ff-47cb-800d-0dd107a23b46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361894957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2361894957
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.913231901
Short name T474
Test name
Test status
Simulation time 668446608 ps
CPU time 8.08 seconds
Started Apr 23 01:57:03 PM PDT 24
Finished Apr 23 01:57:12 PM PDT 24
Peak memory 209092 kb
Host smart-3c03c62b-2b12-4098-9e90-8328378a4d55
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913231901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.913231901
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.703544574
Short name T576
Test name
Test status
Simulation time 207400387 ps
CPU time 4.09 seconds
Started Apr 23 01:57:04 PM PDT 24
Finished Apr 23 01:57:08 PM PDT 24
Peak memory 206852 kb
Host smart-9fbad777-b36e-47e4-89fc-d9762252896b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703544574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.703544574
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3092693604
Short name T816
Test name
Test status
Simulation time 31266456 ps
CPU time 1.6 seconds
Started Apr 23 01:57:07 PM PDT 24
Finished Apr 23 01:57:10 PM PDT 24
Peak memory 208292 kb
Host smart-09d0449b-446d-4816-9bac-0ebf3e95157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092693604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3092693604
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.337199737
Short name T788
Test name
Test status
Simulation time 70188221 ps
CPU time 1.72 seconds
Started Apr 23 01:57:03 PM PDT 24
Finished Apr 23 01:57:06 PM PDT 24
Peak memory 206676 kb
Host smart-02b798c9-4c0d-4a81-bbbe-067f7c39be70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337199737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.337199737
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.355437293
Short name T320
Test name
Test status
Simulation time 12752293174 ps
CPU time 289.92 seconds
Started Apr 23 01:57:06 PM PDT 24
Finished Apr 23 02:01:56 PM PDT 24
Peak memory 219100 kb
Host smart-831c6aa2-dd84-430d-aa34-2bddefdbdeab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355437293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.355437293
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.808750049
Short name T666
Test name
Test status
Simulation time 48600143 ps
CPU time 2.91 seconds
Started Apr 23 01:57:03 PM PDT 24
Finished Apr 23 01:57:07 PM PDT 24
Peak memory 207416 kb
Host smart-20ffab24-11a7-460c-a184-d264bf10d5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808750049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.808750049
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.214420045
Short name T828
Test name
Test status
Simulation time 45964656 ps
CPU time 2.02 seconds
Started Apr 23 01:57:11 PM PDT 24
Finished Apr 23 01:57:14 PM PDT 24
Peak memory 210152 kb
Host smart-239e2eff-1705-40eb-8a4d-c38f2ca39030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214420045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.214420045
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1347736786
Short name T849
Test name
Test status
Simulation time 13685688 ps
CPU time 0.77 seconds
Started Apr 23 01:57:09 PM PDT 24
Finished Apr 23 01:57:10 PM PDT 24
Peak memory 206112 kb
Host smart-adcdbdc0-45b6-466a-8698-9a977f7aed36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347736786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1347736786
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3723167302
Short name T819
Test name
Test status
Simulation time 188191632 ps
CPU time 6.05 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:57:17 PM PDT 24
Peak memory 210580 kb
Host smart-1f6651b0-2890-4f62-9758-37573552a524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723167302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3723167302
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3346440048
Short name T72
Test name
Test status
Simulation time 11942790196 ps
CPU time 14.64 seconds
Started Apr 23 01:57:08 PM PDT 24
Finished Apr 23 01:57:24 PM PDT 24
Peak memory 209252 kb
Host smart-fc52ea64-da97-4110-80fc-81f52b20d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346440048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3346440048
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2825394485
Short name T780
Test name
Test status
Simulation time 686231483 ps
CPU time 4.56 seconds
Started Apr 23 01:57:09 PM PDT 24
Finished Apr 23 01:57:15 PM PDT 24
Peak memory 209608 kb
Host smart-a1521395-14f4-45a3-aa76-9a5af9223568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825394485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2825394485
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3439998909
Short name T590
Test name
Test status
Simulation time 3000616099 ps
CPU time 13.66 seconds
Started Apr 23 01:57:09 PM PDT 24
Finished Apr 23 01:57:23 PM PDT 24
Peak memory 216972 kb
Host smart-90267df2-296b-4496-a702-13b7bb3cd2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439998909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3439998909
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1551462444
Short name T791
Test name
Test status
Simulation time 1359449832 ps
CPU time 18.04 seconds
Started Apr 23 01:57:05 PM PDT 24
Finished Apr 23 01:57:24 PM PDT 24
Peak memory 210048 kb
Host smart-3704e3fe-e10e-4ff4-b39c-59d1d22041e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551462444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1551462444
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.959976912
Short name T877
Test name
Test status
Simulation time 90008782 ps
CPU time 4.24 seconds
Started Apr 23 01:57:11 PM PDT 24
Finished Apr 23 01:57:17 PM PDT 24
Peak memory 209120 kb
Host smart-a17a907a-e5e6-4c60-904b-29e9c11d5ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959976912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.959976912
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1309870218
Short name T525
Test name
Test status
Simulation time 60053844 ps
CPU time 3.16 seconds
Started Apr 23 01:57:11 PM PDT 24
Finished Apr 23 01:57:16 PM PDT 24
Peak memory 208828 kb
Host smart-e96e3b0f-e47d-4ca8-a2e5-59f0d88f717c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309870218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1309870218
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3074188874
Short name T192
Test name
Test status
Simulation time 36219106 ps
CPU time 2.33 seconds
Started Apr 23 01:57:04 PM PDT 24
Finished Apr 23 01:57:07 PM PDT 24
Peak memory 207052 kb
Host smart-fee8fe3c-bdc6-491c-af67-b0746b3de59c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074188874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3074188874
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.920003736
Short name T4
Test name
Test status
Simulation time 107357905 ps
CPU time 4.48 seconds
Started Apr 23 01:57:04 PM PDT 24
Finished Apr 23 01:57:09 PM PDT 24
Peak memory 206480 kb
Host smart-4f3f66ea-0ac0-401a-b509-1ad436a5b39a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920003736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.920003736
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.563949943
Short name T834
Test name
Test status
Simulation time 24884544 ps
CPU time 1.97 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:57:13 PM PDT 24
Peak memory 216012 kb
Host smart-836ad89a-069b-4008-939e-19c25e30ec31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563949943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.563949943
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1877937762
Short name T651
Test name
Test status
Simulation time 145417923 ps
CPU time 5.04 seconds
Started Apr 23 01:57:09 PM PDT 24
Finished Apr 23 01:57:15 PM PDT 24
Peak memory 208216 kb
Host smart-196890bd-b74e-4219-af9e-c5effb795ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877937762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1877937762
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2218395367
Short name T660
Test name
Test status
Simulation time 7174516793 ps
CPU time 48.45 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:58:00 PM PDT 24
Peak memory 208900 kb
Host smart-7eac73b7-1b72-4e1a-a804-fd019fd4f52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218395367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2218395367
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2333009587
Short name T585
Test name
Test status
Simulation time 89988180 ps
CPU time 1.68 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:57:13 PM PDT 24
Peak memory 210112 kb
Host smart-b9ab13ba-0869-4c61-86f2-a912e742ddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333009587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2333009587
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3307099186
Short name T498
Test name
Test status
Simulation time 40001059 ps
CPU time 0.78 seconds
Started Apr 23 01:54:56 PM PDT 24
Finished Apr 23 01:54:58 PM PDT 24
Peak memory 206144 kb
Host smart-fb1b66d6-fa13-4e6d-bd25-1e3b1ff761bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307099186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3307099186
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2280602515
Short name T411
Test name
Test status
Simulation time 181239255 ps
CPU time 3.56 seconds
Started Apr 23 01:54:56 PM PDT 24
Finished Apr 23 01:55:00 PM PDT 24
Peak memory 215484 kb
Host smart-3b3e79dd-8b4a-4be7-9395-5da9a5e864c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280602515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2280602515
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1229337744
Short name T362
Test name
Test status
Simulation time 103172952 ps
CPU time 2.65 seconds
Started Apr 23 01:54:55 PM PDT 24
Finished Apr 23 01:54:58 PM PDT 24
Peak memory 208804 kb
Host smart-00ec4c4f-1e8a-4980-98fe-9c5c9975b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229337744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1229337744
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3615025633
Short name T812
Test name
Test status
Simulation time 197594118 ps
CPU time 5.57 seconds
Started Apr 23 01:54:56 PM PDT 24
Finished Apr 23 01:55:02 PM PDT 24
Peak memory 208700 kb
Host smart-46684b1b-e13a-47f7-9e4e-982368d66374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615025633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3615025633
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2193361474
Short name T739
Test name
Test status
Simulation time 181302022 ps
CPU time 6 seconds
Started Apr 23 01:54:55 PM PDT 24
Finished Apr 23 01:55:01 PM PDT 24
Peak memory 208140 kb
Host smart-f8ad7d3e-d5db-47d8-a596-ca3b7de4483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193361474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2193361474
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1259654081
Short name T13
Test name
Test status
Simulation time 13458496099 ps
CPU time 27.63 seconds
Started Apr 23 01:54:57 PM PDT 24
Finished Apr 23 01:55:25 PM PDT 24
Peak memory 241132 kb
Host smart-6252de01-b541-4002-a0d4-3bbfd5f36232
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259654081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1259654081
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1394769974
Short name T888
Test name
Test status
Simulation time 124509357 ps
CPU time 2.41 seconds
Started Apr 23 01:54:55 PM PDT 24
Finished Apr 23 01:54:58 PM PDT 24
Peak memory 207432 kb
Host smart-633c28b6-b17c-468d-a352-a8af2a223554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394769974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1394769974
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1896385139
Short name T552
Test name
Test status
Simulation time 4225645108 ps
CPU time 18.57 seconds
Started Apr 23 01:54:54 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 208320 kb
Host smart-735b1d91-9414-45e3-b2d6-13cc6bf57acc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896385139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1896385139
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4198662904
Short name T667
Test name
Test status
Simulation time 218402257 ps
CPU time 4.08 seconds
Started Apr 23 01:54:55 PM PDT 24
Finished Apr 23 01:55:00 PM PDT 24
Peak memory 209024 kb
Host smart-5c1bcedb-0cd9-4159-837c-f51fb4f18703
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198662904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4198662904
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3485132093
Short name T640
Test name
Test status
Simulation time 318448081 ps
CPU time 2.83 seconds
Started Apr 23 01:54:54 PM PDT 24
Finished Apr 23 01:54:58 PM PDT 24
Peak memory 207520 kb
Host smart-6b781d7b-b5b9-4cbe-87c7-a3aea51b4981
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485132093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3485132093
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2250840
Short name T535
Test name
Test status
Simulation time 286731100 ps
CPU time 7.55 seconds
Started Apr 23 01:54:56 PM PDT 24
Finished Apr 23 01:55:04 PM PDT 24
Peak memory 209080 kb
Host smart-1c1af8f0-e694-4976-a352-d69fbf1b3edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2250840
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1256400466
Short name T445
Test name
Test status
Simulation time 1504540000 ps
CPU time 4.29 seconds
Started Apr 23 01:54:52 PM PDT 24
Finished Apr 23 01:54:57 PM PDT 24
Peak memory 208392 kb
Host smart-a3c26ee8-eee1-4ce2-8590-8080e8171c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256400466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1256400466
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1786181584
Short name T807
Test name
Test status
Simulation time 2132542492 ps
CPU time 48.94 seconds
Started Apr 23 01:54:56 PM PDT 24
Finished Apr 23 01:55:45 PM PDT 24
Peak memory 214648 kb
Host smart-e1927f5d-3213-4e29-8e90-7f1b566eb750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786181584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1786181584
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3391836302
Short name T8
Test name
Test status
Simulation time 1638982723 ps
CPU time 9.27 seconds
Started Apr 23 01:54:59 PM PDT 24
Finished Apr 23 01:55:09 PM PDT 24
Peak memory 220000 kb
Host smart-32095c64-8964-44e0-b851-3c00242be08c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391836302 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3391836302
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1025646982
Short name T759
Test name
Test status
Simulation time 1000718109 ps
CPU time 10.76 seconds
Started Apr 23 01:54:56 PM PDT 24
Finished Apr 23 01:55:07 PM PDT 24
Peak memory 214616 kb
Host smart-ad1e82fa-3e1d-49b2-95c5-7914fcfa9b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025646982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1025646982
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3604280062
Short name T720
Test name
Test status
Simulation time 156749961 ps
CPU time 3.18 seconds
Started Apr 23 01:54:56 PM PDT 24
Finished Apr 23 01:55:00 PM PDT 24
Peak memory 210616 kb
Host smart-eb26decd-1b38-4294-b4a1-2a85300268da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604280062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3604280062
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1613327428
Short name T728
Test name
Test status
Simulation time 25036339 ps
CPU time 0.89 seconds
Started Apr 23 01:57:18 PM PDT 24
Finished Apr 23 01:57:20 PM PDT 24
Peak memory 206120 kb
Host smart-5bc11314-3d47-4d9c-bc36-76c992b13eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613327428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1613327428
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4199548469
Short name T259
Test name
Test status
Simulation time 186576301 ps
CPU time 3.92 seconds
Started Apr 23 01:57:09 PM PDT 24
Finished Apr 23 01:57:13 PM PDT 24
Peak memory 215332 kb
Host smart-3a04e68a-239f-4e43-a9f2-8a64851592f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199548469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4199548469
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.551655311
Short name T218
Test name
Test status
Simulation time 286117402 ps
CPU time 6.04 seconds
Started Apr 23 01:57:12 PM PDT 24
Finished Apr 23 01:57:19 PM PDT 24
Peak memory 214804 kb
Host smart-20aeaf3f-8428-4292-9cb1-3281d4b53458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551655311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.551655311
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.87118335
Short name T644
Test name
Test status
Simulation time 187474748 ps
CPU time 5.26 seconds
Started Apr 23 01:57:11 PM PDT 24
Finished Apr 23 01:57:17 PM PDT 24
Peak memory 218432 kb
Host smart-4a1a46b8-0318-4ac3-aca1-08fb3e62c784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87118335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.87118335
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4259737192
Short name T670
Test name
Test status
Simulation time 9232845687 ps
CPU time 102.94 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:58:54 PM PDT 24
Peak memory 222780 kb
Host smart-3af27d48-da33-4ebe-bbf2-892f9b8438f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259737192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4259737192
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1180204849
Short name T233
Test name
Test status
Simulation time 239090943 ps
CPU time 5.77 seconds
Started Apr 23 01:57:18 PM PDT 24
Finished Apr 23 01:57:25 PM PDT 24
Peak memory 211068 kb
Host smart-fdef861b-5bd8-4f86-b3a3-c84359b15050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180204849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1180204849
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2956997489
Short name T495
Test name
Test status
Simulation time 307458345 ps
CPU time 4.16 seconds
Started Apr 23 01:57:07 PM PDT 24
Finished Apr 23 01:57:12 PM PDT 24
Peak memory 208704 kb
Host smart-417e8c2a-6a58-4024-8047-e2a6736ff9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956997489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2956997489
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3816634014
Short name T227
Test name
Test status
Simulation time 945647296 ps
CPU time 4 seconds
Started Apr 23 01:57:09 PM PDT 24
Finished Apr 23 01:57:14 PM PDT 24
Peak memory 208252 kb
Host smart-d428ffcf-cb15-47bc-88f9-7ef521286db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816634014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3816634014
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2194129304
Short name T893
Test name
Test status
Simulation time 134778757 ps
CPU time 2.46 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:57:14 PM PDT 24
Peak memory 206408 kb
Host smart-433033da-acf8-4936-8589-fc6fbe12f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194129304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2194129304
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2818030077
Short name T589
Test name
Test status
Simulation time 109082635 ps
CPU time 3.31 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:57:15 PM PDT 24
Peak memory 208728 kb
Host smart-1d39f937-8f6f-4579-836f-74ee3ddadb88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818030077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2818030077
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3022877985
Short name T864
Test name
Test status
Simulation time 105036411 ps
CPU time 2.82 seconds
Started Apr 23 01:57:07 PM PDT 24
Finished Apr 23 01:57:11 PM PDT 24
Peak memory 207056 kb
Host smart-21610a7e-de60-4e91-a09a-401e47c05ecf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022877985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3022877985
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1603976574
Short name T843
Test name
Test status
Simulation time 223499960 ps
CPU time 3.93 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:57:15 PM PDT 24
Peak memory 206932 kb
Host smart-5d05a2d0-f6c2-49ff-8aa4-e6b833b41a1e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603976574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1603976574
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3579209236
Short name T505
Test name
Test status
Simulation time 3608694007 ps
CPU time 17.79 seconds
Started Apr 23 01:57:12 PM PDT 24
Finished Apr 23 01:57:31 PM PDT 24
Peak memory 218040 kb
Host smart-63e02a8a-38c7-4b9a-b43f-80a9556d70e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579209236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3579209236
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.737753471
Short name T596
Test name
Test status
Simulation time 141622990 ps
CPU time 2.59 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:57:13 PM PDT 24
Peak memory 208752 kb
Host smart-03cdc86a-56cf-4c2f-90f0-b901994d0fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737753471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.737753471
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3655624076
Short name T210
Test name
Test status
Simulation time 1409816204 ps
CPU time 32.1 seconds
Started Apr 23 01:57:14 PM PDT 24
Finished Apr 23 01:57:47 PM PDT 24
Peak memory 222680 kb
Host smart-883897a4-0184-407d-a72a-63faee66a622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655624076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3655624076
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.4018318570
Short name T222
Test name
Test status
Simulation time 208719650 ps
CPU time 9.09 seconds
Started Apr 23 01:57:11 PM PDT 24
Finished Apr 23 01:57:21 PM PDT 24
Peak memory 222880 kb
Host smart-39e7acba-217f-4a3c-81bd-c7678ad3c812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018318570 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.4018318570
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.308134092
Short name T653
Test name
Test status
Simulation time 179687833 ps
CPU time 5.36 seconds
Started Apr 23 01:57:09 PM PDT 24
Finished Apr 23 01:57:15 PM PDT 24
Peak memory 210348 kb
Host smart-f9bde450-fc29-45e0-861e-3e9a2cb3e558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308134092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.308134092
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2625644456
Short name T802
Test name
Test status
Simulation time 291918269 ps
CPU time 2.83 seconds
Started Apr 23 01:57:12 PM PDT 24
Finished Apr 23 01:57:16 PM PDT 24
Peak memory 210320 kb
Host smart-dcf416ed-80a3-43d9-82c0-27e43f552274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625644456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2625644456
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3092366560
Short name T514
Test name
Test status
Simulation time 19123367 ps
CPU time 0.79 seconds
Started Apr 23 01:57:15 PM PDT 24
Finished Apr 23 01:57:16 PM PDT 24
Peak memory 206060 kb
Host smart-b48de3fc-1fce-401e-b28a-bbbaa3c73eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092366560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3092366560
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.494358075
Short name T424
Test name
Test status
Simulation time 179612320 ps
CPU time 5.55 seconds
Started Apr 23 01:57:12 PM PDT 24
Finished Apr 23 01:57:19 PM PDT 24
Peak memory 215004 kb
Host smart-6334faf6-9030-4acf-b53e-4cf9f720b90b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494358075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.494358075
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2924711244
Short name T11
Test name
Test status
Simulation time 48252948 ps
CPU time 2.63 seconds
Started Apr 23 01:57:13 PM PDT 24
Finished Apr 23 01:57:16 PM PDT 24
Peak memory 221956 kb
Host smart-d3531d05-cb07-4933-a663-72cd0cb4a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924711244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2924711244
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1162462033
Short name T700
Test name
Test status
Simulation time 123291452 ps
CPU time 3.33 seconds
Started Apr 23 01:57:12 PM PDT 24
Finished Apr 23 01:57:16 PM PDT 24
Peak memory 210100 kb
Host smart-2494912a-3363-4e00-800f-5595476a1732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162462033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1162462033
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3020048219
Short name T240
Test name
Test status
Simulation time 1381574531 ps
CPU time 6.78 seconds
Started Apr 23 01:57:13 PM PDT 24
Finished Apr 23 01:57:20 PM PDT 24
Peak memory 209712 kb
Host smart-22b89252-2f64-44ed-849c-9db2073eacc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020048219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3020048219
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3241152085
Short name T500
Test name
Test status
Simulation time 102597635 ps
CPU time 4.6 seconds
Started Apr 23 01:57:17 PM PDT 24
Finished Apr 23 01:57:22 PM PDT 24
Peak memory 211568 kb
Host smart-2fdaef71-a141-4c7f-9eda-d5c84402afae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241152085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3241152085
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.983425014
Short name T858
Test name
Test status
Simulation time 43900224 ps
CPU time 2.18 seconds
Started Apr 23 01:57:17 PM PDT 24
Finished Apr 23 01:57:20 PM PDT 24
Peak memory 222868 kb
Host smart-8de34da4-02bf-4185-b90f-ca516bd22b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983425014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.983425014
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.463965306
Short name T588
Test name
Test status
Simulation time 442488688 ps
CPU time 5.26 seconds
Started Apr 23 01:57:11 PM PDT 24
Finished Apr 23 01:57:17 PM PDT 24
Peak memory 207744 kb
Host smart-60ba7a7d-c282-417e-a3f1-026acbd26346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463965306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.463965306
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1661315731
Short name T595
Test name
Test status
Simulation time 259679789 ps
CPU time 2.92 seconds
Started Apr 23 01:57:10 PM PDT 24
Finished Apr 23 01:57:13 PM PDT 24
Peak memory 208768 kb
Host smart-78cf2801-1ce7-45b9-881d-9aa89086a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661315731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1661315731
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.41265392
Short name T723
Test name
Test status
Simulation time 627719834 ps
CPU time 7.23 seconds
Started Apr 23 01:57:12 PM PDT 24
Finished Apr 23 01:57:20 PM PDT 24
Peak memory 208740 kb
Host smart-a5ce2024-d665-4dd0-9344-bcdb6cdaa651
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41265392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.41265392
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4243392181
Short name T348
Test name
Test status
Simulation time 102399152 ps
CPU time 2.94 seconds
Started Apr 23 01:57:14 PM PDT 24
Finished Apr 23 01:57:18 PM PDT 24
Peak memory 208800 kb
Host smart-c666d1f7-b821-4cba-9023-c7d978847a13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243392181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4243392181
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1046296667
Short name T664
Test name
Test status
Simulation time 659202816 ps
CPU time 21.1 seconds
Started Apr 23 01:57:14 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 208328 kb
Host smart-1c4fb75e-50db-420c-8c4b-870ab4e80729
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046296667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1046296667
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.807911308
Short name T547
Test name
Test status
Simulation time 168205078 ps
CPU time 2.39 seconds
Started Apr 23 01:57:15 PM PDT 24
Finished Apr 23 01:57:18 PM PDT 24
Peak memory 207036 kb
Host smart-254bdfb1-1e2f-464e-a611-bc8f98e3c217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807911308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.807911308
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.687212005
Short name T438
Test name
Test status
Simulation time 44091113 ps
CPU time 2.41 seconds
Started Apr 23 01:57:12 PM PDT 24
Finished Apr 23 01:57:15 PM PDT 24
Peak memory 208448 kb
Host smart-b80e6efa-ed2a-4566-b942-6a1421a15bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687212005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.687212005
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2111254782
Short name T476
Test name
Test status
Simulation time 103612790 ps
CPU time 5.18 seconds
Started Apr 23 01:57:12 PM PDT 24
Finished Apr 23 01:57:18 PM PDT 24
Peak memory 208024 kb
Host smart-4a306ba5-5a84-44d5-9d32-7bb7c3c1f567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111254782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2111254782
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2891493751
Short name T592
Test name
Test status
Simulation time 97959659 ps
CPU time 3.52 seconds
Started Apr 23 01:57:18 PM PDT 24
Finished Apr 23 01:57:22 PM PDT 24
Peak memory 210568 kb
Host smart-6889aa91-acbf-427b-ac31-7caaa70c99d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891493751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2891493751
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1547434612
Short name T431
Test name
Test status
Simulation time 13122711 ps
CPU time 0.88 seconds
Started Apr 23 01:57:18 PM PDT 24
Finished Apr 23 01:57:20 PM PDT 24
Peak memory 206176 kb
Host smart-b7b92ef8-f7ee-4681-9c08-4346aa6618c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547434612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1547434612
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3013220243
Short name T28
Test name
Test status
Simulation time 462367644 ps
CPU time 6.08 seconds
Started Apr 23 01:57:16 PM PDT 24
Finished Apr 23 01:57:23 PM PDT 24
Peak memory 218668 kb
Host smart-8e0cb3b3-c8a8-48b1-adb9-e9c72cc8efcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013220243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3013220243
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2428880808
Short name T367
Test name
Test status
Simulation time 36950651 ps
CPU time 1.98 seconds
Started Apr 23 01:57:15 PM PDT 24
Finished Apr 23 01:57:18 PM PDT 24
Peak memory 209824 kb
Host smart-4ef49375-9472-4393-994c-4fafcd1d60db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428880808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2428880808
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3609753873
Short name T93
Test name
Test status
Simulation time 1287940540 ps
CPU time 34.27 seconds
Started Apr 23 01:57:18 PM PDT 24
Finished Apr 23 01:57:53 PM PDT 24
Peak memory 222688 kb
Host smart-f28f967d-4b84-44c3-913b-9564d8817919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609753873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3609753873
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.231828754
Short name T338
Test name
Test status
Simulation time 113010923 ps
CPU time 5.63 seconds
Started Apr 23 01:57:12 PM PDT 24
Finished Apr 23 01:57:18 PM PDT 24
Peak memory 214456 kb
Host smart-d02df936-6511-4fa4-ae78-56e59d106672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231828754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.231828754
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1211620593
Short name T268
Test name
Test status
Simulation time 124767511 ps
CPU time 3.8 seconds
Started Apr 23 01:57:14 PM PDT 24
Finished Apr 23 01:57:18 PM PDT 24
Peak memory 220376 kb
Host smart-01a8af77-0887-4810-bb27-0c1fb9ee0e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211620593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1211620593
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3796441909
Short name T832
Test name
Test status
Simulation time 412858105 ps
CPU time 5.13 seconds
Started Apr 23 01:57:22 PM PDT 24
Finished Apr 23 01:57:28 PM PDT 24
Peak memory 207964 kb
Host smart-7898ef80-feea-442a-9c90-a2b2391fc517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796441909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3796441909
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1386610729
Short name T733
Test name
Test status
Simulation time 392047239 ps
CPU time 2.57 seconds
Started Apr 23 01:57:15 PM PDT 24
Finished Apr 23 01:57:19 PM PDT 24
Peak memory 207028 kb
Host smart-c83be811-05b1-43b6-97de-9d9e16b90e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386610729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1386610729
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.37090129
Short name T716
Test name
Test status
Simulation time 207232424 ps
CPU time 3.53 seconds
Started Apr 23 01:57:14 PM PDT 24
Finished Apr 23 01:57:18 PM PDT 24
Peak memory 208548 kb
Host smart-1b8fdde4-c3e8-4391-855b-689b5332a1e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37090129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.37090129
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1567876523
Short name T581
Test name
Test status
Simulation time 745468978 ps
CPU time 4.96 seconds
Started Apr 23 01:57:17 PM PDT 24
Finished Apr 23 01:57:22 PM PDT 24
Peak memory 208856 kb
Host smart-7139dfb7-eb29-4f61-8f93-d19634a4d4d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567876523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1567876523
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3447197221
Short name T557
Test name
Test status
Simulation time 105127775 ps
CPU time 3.65 seconds
Started Apr 23 01:57:14 PM PDT 24
Finished Apr 23 01:57:18 PM PDT 24
Peak memory 207104 kb
Host smart-1ec1ea19-d807-4fd3-b51a-9e3ab45e280c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447197221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3447197221
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3973073807
Short name T189
Test name
Test status
Simulation time 59147132 ps
CPU time 2.92 seconds
Started Apr 23 01:57:18 PM PDT 24
Finished Apr 23 01:57:22 PM PDT 24
Peak memory 209104 kb
Host smart-d6e82d9d-95f7-4c58-beeb-5a77a82113b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973073807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3973073807
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4193912167
Short name T472
Test name
Test status
Simulation time 87717550 ps
CPU time 3.7 seconds
Started Apr 23 01:57:15 PM PDT 24
Finished Apr 23 01:57:20 PM PDT 24
Peak memory 208448 kb
Host smart-64699366-670e-4c5e-8487-306739cc50eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193912167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4193912167
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.200555718
Short name T685
Test name
Test status
Simulation time 79350771 ps
CPU time 2.56 seconds
Started Apr 23 01:57:21 PM PDT 24
Finished Apr 23 01:57:25 PM PDT 24
Peak memory 209740 kb
Host smart-98fdad22-6db8-4cca-a389-fa448f73245f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200555718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.200555718
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.758449552
Short name T277
Test name
Test status
Simulation time 1183198247 ps
CPU time 12.96 seconds
Started Apr 23 01:57:16 PM PDT 24
Finished Apr 23 01:57:29 PM PDT 24
Peak memory 209968 kb
Host smart-fa67946b-e141-42ed-994b-7665fd17b474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758449552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.758449552
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1347110716
Short name T59
Test name
Test status
Simulation time 281350473 ps
CPU time 3.47 seconds
Started Apr 23 01:57:21 PM PDT 24
Finished Apr 23 01:57:25 PM PDT 24
Peak memory 209836 kb
Host smart-5ccc3b2f-4c2c-494b-b318-c04fd7dd36ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347110716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1347110716
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4096496878
Short name T487
Test name
Test status
Simulation time 16091129 ps
CPU time 0.96 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:57:21 PM PDT 24
Peak memory 206344 kb
Host smart-82d175e9-c5be-40e5-bd9c-4daac137f7da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096496878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4096496878
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1541649834
Short name T601
Test name
Test status
Simulation time 695387677 ps
CPU time 6.14 seconds
Started Apr 23 01:57:19 PM PDT 24
Finished Apr 23 01:57:25 PM PDT 24
Peak memory 208916 kb
Host smart-f01bcaf6-3091-48dd-ba83-e04255dca6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541649834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1541649834
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2880690439
Short name T741
Test name
Test status
Simulation time 176611062 ps
CPU time 2.64 seconds
Started Apr 23 01:57:18 PM PDT 24
Finished Apr 23 01:57:21 PM PDT 24
Peak memory 207836 kb
Host smart-806056ad-d90f-4bd8-916e-8d4db902583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880690439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2880690439
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1247870643
Short name T97
Test name
Test status
Simulation time 102284144 ps
CPU time 2.86 seconds
Started Apr 23 01:57:21 PM PDT 24
Finished Apr 23 01:57:25 PM PDT 24
Peak memory 214612 kb
Host smart-ad5bc30e-bf77-45e5-b217-aa53618aa71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247870643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1247870643
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2531038970
Short name T284
Test name
Test status
Simulation time 132088625 ps
CPU time 2.78 seconds
Started Apr 23 01:57:19 PM PDT 24
Finished Apr 23 01:57:23 PM PDT 24
Peak memory 215292 kb
Host smart-525f4283-ff03-476d-bc37-f54f948fb344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531038970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2531038970
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2580487306
Short name T695
Test name
Test status
Simulation time 71054083 ps
CPU time 2.6 seconds
Started Apr 23 01:57:19 PM PDT 24
Finished Apr 23 01:57:22 PM PDT 24
Peak memory 208576 kb
Host smart-4c607d72-672b-4c61-83e8-53756a8539df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580487306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2580487306
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1493122447
Short name T862
Test name
Test status
Simulation time 665830963 ps
CPU time 10.86 seconds
Started Apr 23 01:57:18 PM PDT 24
Finished Apr 23 01:57:30 PM PDT 24
Peak memory 207160 kb
Host smart-9f4d19f2-1b90-4d02-a263-cd403cda4db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493122447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1493122447
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4272116353
Short name T282
Test name
Test status
Simulation time 212039236 ps
CPU time 2.83 seconds
Started Apr 23 01:57:18 PM PDT 24
Finished Apr 23 01:57:21 PM PDT 24
Peak memory 207072 kb
Host smart-608b08b4-181e-4fc2-977b-ba39daf960f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272116353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4272116353
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2909673355
Short name T805
Test name
Test status
Simulation time 487506939 ps
CPU time 5.46 seconds
Started Apr 23 01:57:16 PM PDT 24
Finished Apr 23 01:57:22 PM PDT 24
Peak memory 207024 kb
Host smart-97534008-a928-4b0d-a8b1-611a9a506803
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909673355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2909673355
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4143452413
Short name T842
Test name
Test status
Simulation time 1237015994 ps
CPU time 7.19 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:57:28 PM PDT 24
Peak memory 208076 kb
Host smart-d7c7d790-0d51-4e6d-9d10-38efba65b639
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143452413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4143452413
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.285880490
Short name T772
Test name
Test status
Simulation time 182413592 ps
CPU time 4.84 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:57:26 PM PDT 24
Peak memory 208688 kb
Host smart-62a883e5-e7bb-46a7-9fda-d60cfdbbdac9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285880490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.285880490
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1311256080
Short name T538
Test name
Test status
Simulation time 167157189 ps
CPU time 3.94 seconds
Started Apr 23 01:57:21 PM PDT 24
Finished Apr 23 01:57:26 PM PDT 24
Peak memory 208652 kb
Host smart-a821116d-0646-42e1-a0b2-e89fc50feab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311256080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1311256080
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.819313077
Short name T477
Test name
Test status
Simulation time 125372484 ps
CPU time 3.01 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:57:24 PM PDT 24
Peak memory 208496 kb
Host smart-fe6b9936-e7a6-4491-b697-a901c65ae996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819313077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.819313077
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.283878961
Short name T305
Test name
Test status
Simulation time 1747729176 ps
CPU time 17.76 seconds
Started Apr 23 01:57:21 PM PDT 24
Finished Apr 23 01:57:39 PM PDT 24
Peak memory 216768 kb
Host smart-e942aac2-1294-48ef-abfb-17096eda197a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283878961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.283878961
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1354806756
Short name T768
Test name
Test status
Simulation time 257163171 ps
CPU time 10.23 seconds
Started Apr 23 01:57:23 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 220164 kb
Host smart-a1359f3d-e738-4fbf-8462-40255f2be506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354806756 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1354806756
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.188812181
Short name T243
Test name
Test status
Simulation time 648922986 ps
CPU time 4.27 seconds
Started Apr 23 01:57:21 PM PDT 24
Finished Apr 23 01:57:26 PM PDT 24
Peak memory 214608 kb
Host smart-84175688-de29-43d9-aa9d-2c02febd74d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188812181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.188812181
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3341411175
Short name T38
Test name
Test status
Simulation time 153167932 ps
CPU time 2.41 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:57:23 PM PDT 24
Peak memory 210304 kb
Host smart-9095dd4f-51ca-48c2-8b3b-112ff6ad1658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341411175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3341411175
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.262327856
Short name T856
Test name
Test status
Simulation time 14057988 ps
CPU time 0.75 seconds
Started Apr 23 01:57:23 PM PDT 24
Finished Apr 23 01:57:25 PM PDT 24
Peak memory 206136 kb
Host smart-5764215c-32d2-43ae-98f9-deadbaf4fd4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262327856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.262327856
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1752580318
Short name T359
Test name
Test status
Simulation time 195070134 ps
CPU time 3.79 seconds
Started Apr 23 01:57:21 PM PDT 24
Finished Apr 23 01:57:25 PM PDT 24
Peak memory 215608 kb
Host smart-9ccb5d5d-ff96-412e-8f95-f81218f196fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1752580318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1752580318
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2455645411
Short name T622
Test name
Test status
Simulation time 50911634 ps
CPU time 2.13 seconds
Started Apr 23 01:57:19 PM PDT 24
Finished Apr 23 01:57:22 PM PDT 24
Peak memory 207224 kb
Host smart-0ac7c78b-7262-4c7b-aead-322a9c677e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455645411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2455645411
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3744015836
Short name T345
Test name
Test status
Simulation time 2614525736 ps
CPU time 58.68 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:58:19 PM PDT 24
Peak memory 222340 kb
Host smart-06e3a612-d003-4f1d-95d2-d7b4ee496aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744015836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3744015836
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4169455771
Short name T90
Test name
Test status
Simulation time 599869098 ps
CPU time 6.19 seconds
Started Apr 23 01:57:22 PM PDT 24
Finished Apr 23 01:57:29 PM PDT 24
Peak memory 214556 kb
Host smart-65e024a9-6f9e-437e-bf9a-6bb9e079de5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169455771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4169455771
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2406674206
Short name T219
Test name
Test status
Simulation time 848952759 ps
CPU time 45.23 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:58:06 PM PDT 24
Peak memory 222628 kb
Host smart-4287556a-5d8c-4ff5-9ab6-8155225583b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406674206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2406674206
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2029180331
Short name T699
Test name
Test status
Simulation time 399533234 ps
CPU time 4.81 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:57:25 PM PDT 24
Peak memory 207552 kb
Host smart-3265bf39-acf2-48f8-ba2d-083136c9769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029180331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2029180331
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1859687251
Short name T599
Test name
Test status
Simulation time 60448871 ps
CPU time 2.87 seconds
Started Apr 23 01:57:23 PM PDT 24
Finished Apr 23 01:57:26 PM PDT 24
Peak memory 208240 kb
Host smart-9b918738-0907-4a31-8407-62e8b40af991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859687251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1859687251
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1908729813
Short name T558
Test name
Test status
Simulation time 767101580 ps
CPU time 6.21 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:57:27 PM PDT 24
Peak memory 207916 kb
Host smart-9033dbd7-6b35-42de-adfc-92da9467ba6c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908729813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1908729813
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.840269032
Short name T481
Test name
Test status
Simulation time 68080533 ps
CPU time 3.49 seconds
Started Apr 23 01:57:23 PM PDT 24
Finished Apr 23 01:57:27 PM PDT 24
Peak memory 208420 kb
Host smart-c008134c-14a7-4690-bec8-c39391531840
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840269032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.840269032
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3810667200
Short name T79
Test name
Test status
Simulation time 253081472 ps
CPU time 3.58 seconds
Started Apr 23 01:57:19 PM PDT 24
Finished Apr 23 01:57:23 PM PDT 24
Peak memory 208964 kb
Host smart-30f249fb-bc92-4e6f-ba77-90a49f88ef73
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810667200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3810667200
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3385141853
Short name T174
Test name
Test status
Simulation time 163105813 ps
CPU time 2.31 seconds
Started Apr 23 01:57:24 PM PDT 24
Finished Apr 23 01:57:27 PM PDT 24
Peak memory 207648 kb
Host smart-a2bb43a7-801a-42e1-b2f1-3b41df4a890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385141853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3385141853
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1655876082
Short name T185
Test name
Test status
Simulation time 192417605 ps
CPU time 2.96 seconds
Started Apr 23 01:57:21 PM PDT 24
Finished Apr 23 01:57:24 PM PDT 24
Peak memory 207040 kb
Host smart-d1a6d343-a8ce-4a69-a20e-4fc876592149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655876082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1655876082
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1787693804
Short name T530
Test name
Test status
Simulation time 1017171464 ps
CPU time 4.64 seconds
Started Apr 23 01:57:20 PM PDT 24
Finished Apr 23 01:57:26 PM PDT 24
Peak memory 209152 kb
Host smart-178a6499-528d-4896-9527-f65add45f7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787693804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1787693804
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3856152544
Short name T762
Test name
Test status
Simulation time 21173695 ps
CPU time 0.74 seconds
Started Apr 23 01:57:27 PM PDT 24
Finished Apr 23 01:57:28 PM PDT 24
Peak memory 206148 kb
Host smart-ad2e5c04-e302-45d0-af26-22402c387c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856152544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3856152544
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.612420770
Short name T173
Test name
Test status
Simulation time 126312218 ps
CPU time 2.89 seconds
Started Apr 23 01:57:30 PM PDT 24
Finished Apr 23 01:57:33 PM PDT 24
Peak memory 210548 kb
Host smart-c93d6550-99a9-4bd1-8c3a-cdb3d6ff30a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612420770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.612420770
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2091841531
Short name T507
Test name
Test status
Simulation time 72641768 ps
CPU time 2.55 seconds
Started Apr 23 01:57:27 PM PDT 24
Finished Apr 23 01:57:30 PM PDT 24
Peak memory 214576 kb
Host smart-5d798063-b721-4a68-ad76-b0ec9665d6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091841531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2091841531
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3326411602
Short name T766
Test name
Test status
Simulation time 126517722 ps
CPU time 3.91 seconds
Started Apr 23 01:57:24 PM PDT 24
Finished Apr 23 01:57:29 PM PDT 24
Peak memory 209608 kb
Host smart-53b43d6a-a2f5-4e80-8f8b-22fc7e99d223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326411602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3326411602
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3022498380
Short name T287
Test name
Test status
Simulation time 967220168 ps
CPU time 9.01 seconds
Started Apr 23 01:57:31 PM PDT 24
Finished Apr 23 01:57:41 PM PDT 24
Peak memory 211992 kb
Host smart-10e63f09-69f0-4230-a035-9f630dbbd6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022498380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3022498380
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1887668104
Short name T457
Test name
Test status
Simulation time 150949783 ps
CPU time 3.21 seconds
Started Apr 23 01:57:27 PM PDT 24
Finished Apr 23 01:57:31 PM PDT 24
Peak memory 214504 kb
Host smart-77e4304e-b802-4ebb-a6be-aff92253a56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887668104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1887668104
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3531659859
Short name T245
Test name
Test status
Simulation time 385211243 ps
CPU time 9.43 seconds
Started Apr 23 01:57:23 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 208220 kb
Host smart-7441e44a-1ab8-41b5-91f5-08e2ba54e568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531659859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3531659859
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1047875088
Short name T604
Test name
Test status
Simulation time 169968149 ps
CPU time 2.54 seconds
Started Apr 23 01:57:26 PM PDT 24
Finished Apr 23 01:57:29 PM PDT 24
Peak memory 208672 kb
Host smart-965f169b-15fd-46b3-a5ad-db70afacca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047875088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1047875088
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3854932503
Short name T540
Test name
Test status
Simulation time 646713528 ps
CPU time 7.88 seconds
Started Apr 23 01:57:25 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 208936 kb
Host smart-65e4d299-7fd7-47cc-a0c0-bddf2d243db5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854932503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3854932503
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3918999273
Short name T665
Test name
Test status
Simulation time 1944830878 ps
CPU time 14.22 seconds
Started Apr 23 01:57:25 PM PDT 24
Finished Apr 23 01:57:39 PM PDT 24
Peak memory 208564 kb
Host smart-b46910ae-bb08-4e84-83ac-8abc0014d988
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918999273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3918999273
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1805829572
Short name T186
Test name
Test status
Simulation time 20697455 ps
CPU time 1.92 seconds
Started Apr 23 01:57:25 PM PDT 24
Finished Apr 23 01:57:27 PM PDT 24
Peak memory 206980 kb
Host smart-fa8b79db-53d7-448d-862e-b99e5b9e140e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805829572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1805829572
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3307389291
Short name T694
Test name
Test status
Simulation time 275240062 ps
CPU time 2.52 seconds
Started Apr 23 01:57:30 PM PDT 24
Finished Apr 23 01:57:33 PM PDT 24
Peak memory 214456 kb
Host smart-9884d7fb-8f20-470a-bcf9-35af9562204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307389291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3307389291
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.312160922
Short name T555
Test name
Test status
Simulation time 330734858 ps
CPU time 4.3 seconds
Started Apr 23 01:57:25 PM PDT 24
Finished Apr 23 01:57:30 PM PDT 24
Peak memory 208776 kb
Host smart-99899950-a540-4f04-9167-d19d84f17a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312160922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.312160922
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.843987149
Short name T178
Test name
Test status
Simulation time 341992476 ps
CPU time 13.52 seconds
Started Apr 23 01:57:28 PM PDT 24
Finished Apr 23 01:57:42 PM PDT 24
Peak memory 215300 kb
Host smart-3177b391-9c86-4b5f-a0b4-2efca3205c9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843987149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.843987149
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2001233589
Short name T681
Test name
Test status
Simulation time 336382370 ps
CPU time 2.45 seconds
Started Apr 23 01:57:31 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 207400 kb
Host smart-f2c16eb6-155b-4c9e-90c1-0b0469dafa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001233589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2001233589
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.432502780
Short name T871
Test name
Test status
Simulation time 68672776 ps
CPU time 2.57 seconds
Started Apr 23 01:57:31 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 210324 kb
Host smart-08b9c342-6fe6-4315-9019-37945332bc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432502780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.432502780
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2276937290
Short name T730
Test name
Test status
Simulation time 38829526 ps
CPU time 0.74 seconds
Started Apr 23 01:57:32 PM PDT 24
Finished Apr 23 01:57:33 PM PDT 24
Peak memory 206188 kb
Host smart-31ee82f1-c407-4146-b0c2-ea4690b6c83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276937290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2276937290
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3544668209
Short name T412
Test name
Test status
Simulation time 5324409643 ps
CPU time 67.81 seconds
Started Apr 23 01:57:29 PM PDT 24
Finished Apr 23 01:58:38 PM PDT 24
Peak memory 214640 kb
Host smart-ae46a8a3-7f43-4b06-81b6-8e44e4d8cd9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3544668209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3544668209
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1858201518
Short name T613
Test name
Test status
Simulation time 298695739 ps
CPU time 3.96 seconds
Started Apr 23 01:57:32 PM PDT 24
Finished Apr 23 01:57:36 PM PDT 24
Peak memory 208092 kb
Host smart-b5750fe9-193f-43a9-ae93-6b157e04dcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858201518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1858201518
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1906714224
Short name T778
Test name
Test status
Simulation time 275078224 ps
CPU time 3.13 seconds
Started Apr 23 01:57:28 PM PDT 24
Finished Apr 23 01:57:32 PM PDT 24
Peak memory 210352 kb
Host smart-0ae8d179-9a3a-472c-b941-f21538db1497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906714224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1906714224
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.4079009562
Short name T269
Test name
Test status
Simulation time 120938941 ps
CPU time 2.35 seconds
Started Apr 23 01:57:30 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 207224 kb
Host smart-5cb77b9e-584b-441d-9d4a-919e65439488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079009562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4079009562
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1174741218
Short name T395
Test name
Test status
Simulation time 107412687 ps
CPU time 4.53 seconds
Started Apr 23 01:57:29 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 208068 kb
Host smart-27a3648c-ef3b-40c2-a856-d1b71f93771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174741218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1174741218
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3010327702
Short name T689
Test name
Test status
Simulation time 432599624 ps
CPU time 4.21 seconds
Started Apr 23 01:57:30 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 206960 kb
Host smart-58a1076f-87b5-4143-b11a-8b4683414c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010327702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3010327702
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.839976917
Short name T503
Test name
Test status
Simulation time 224295319 ps
CPU time 3.05 seconds
Started Apr 23 01:57:28 PM PDT 24
Finished Apr 23 01:57:32 PM PDT 24
Peak memory 208968 kb
Host smart-354e0ee2-aeca-4493-90ff-1227a6e1d1e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839976917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.839976917
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1732700020
Short name T85
Test name
Test status
Simulation time 268938532 ps
CPU time 3.72 seconds
Started Apr 23 01:57:30 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 209092 kb
Host smart-da7bf02c-00b7-42a3-be96-a18f4b2cf3b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732700020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1732700020
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.809074053
Short name T194
Test name
Test status
Simulation time 183475823 ps
CPU time 2.88 seconds
Started Apr 23 01:57:32 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 206860 kb
Host smart-23cd47a1-d4cb-4001-9134-62c1101f6385
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809074053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.809074053
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3659433409
Short name T773
Test name
Test status
Simulation time 584083534 ps
CPU time 4.5 seconds
Started Apr 23 01:57:29 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 207536 kb
Host smart-4ab93e0b-fdda-4031-939f-153bb7ede0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659433409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3659433409
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.595068170
Short name T491
Test name
Test status
Simulation time 280899991 ps
CPU time 4.02 seconds
Started Apr 23 01:57:31 PM PDT 24
Finished Apr 23 01:57:36 PM PDT 24
Peak memory 208508 kb
Host smart-7cd2dc85-41a4-4407-973c-2a3fd398feec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595068170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.595068170
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.4104903024
Short name T727
Test name
Test status
Simulation time 354498973 ps
CPU time 15.59 seconds
Started Apr 23 01:57:28 PM PDT 24
Finished Apr 23 01:57:44 PM PDT 24
Peak memory 222876 kb
Host smart-52a3bef4-6aa8-44ec-b735-438f9a70603f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104903024 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.4104903024
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2252829702
Short name T706
Test name
Test status
Simulation time 2281114334 ps
CPU time 48.21 seconds
Started Apr 23 01:57:31 PM PDT 24
Finished Apr 23 01:58:20 PM PDT 24
Peak memory 218708 kb
Host smart-7d893b72-4045-405b-a071-cf93720d85eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252829702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2252829702
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3543140697
Short name T860
Test name
Test status
Simulation time 178674633 ps
CPU time 3.54 seconds
Started Apr 23 01:57:28 PM PDT 24
Finished Apr 23 01:57:32 PM PDT 24
Peak memory 209772 kb
Host smart-42d8b632-27ab-4020-aa2d-3f54fdcd0077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543140697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3543140697
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.407744638
Short name T453
Test name
Test status
Simulation time 200820914 ps
CPU time 0.84 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:57:39 PM PDT 24
Peak memory 206124 kb
Host smart-eb00a991-fa3c-4526-8b88-9c035beda961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407744638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.407744638
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.370688966
Short name T410
Test name
Test status
Simulation time 313846362 ps
CPU time 5.58 seconds
Started Apr 23 01:57:33 PM PDT 24
Finished Apr 23 01:57:39 PM PDT 24
Peak memory 214520 kb
Host smart-882e37b1-a777-4e89-87fc-336469e40afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370688966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.370688966
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1259533201
Short name T764
Test name
Test status
Simulation time 236312816 ps
CPU time 3.37 seconds
Started Apr 23 01:57:32 PM PDT 24
Finished Apr 23 01:57:36 PM PDT 24
Peak memory 218416 kb
Host smart-b348aa63-1995-47ef-97a4-a1da84713e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259533201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1259533201
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3181360217
Short name T467
Test name
Test status
Simulation time 29842734 ps
CPU time 2.42 seconds
Started Apr 23 01:57:31 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 209516 kb
Host smart-ba30ae53-baca-4b9e-9a3d-1a03f64742e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181360217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3181360217
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.12992015
Short name T201
Test name
Test status
Simulation time 328115972 ps
CPU time 8.42 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:57:46 PM PDT 24
Peak memory 214536 kb
Host smart-26216d76-35b7-4a3d-a76b-9f65f92a13fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12992015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.12992015
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3516707320
Short name T574
Test name
Test status
Simulation time 1439779724 ps
CPU time 4.18 seconds
Started Apr 23 01:57:32 PM PDT 24
Finished Apr 23 01:57:37 PM PDT 24
Peak memory 220580 kb
Host smart-7604fa19-f40d-4cd6-9540-a8d8aab8c803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516707320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3516707320
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1346252649
Short name T375
Test name
Test status
Simulation time 141300656 ps
CPU time 5.17 seconds
Started Apr 23 01:57:38 PM PDT 24
Finished Apr 23 01:57:43 PM PDT 24
Peak memory 214680 kb
Host smart-cd525688-1019-49a1-8cf8-400c20fcdd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346252649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1346252649
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1127036246
Short name T556
Test name
Test status
Simulation time 463628935 ps
CPU time 5.4 seconds
Started Apr 23 01:57:29 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 208132 kb
Host smart-3a122b50-f10f-491d-89a0-c87a855fcd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127036246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1127036246
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.888973196
Short name T740
Test name
Test status
Simulation time 65302898 ps
CPU time 2.43 seconds
Started Apr 23 01:57:35 PM PDT 24
Finished Apr 23 01:57:38 PM PDT 24
Peak memory 206904 kb
Host smart-2e4ff1da-c8c7-4572-9e2d-3a855a641fa7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888973196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.888973196
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2405002147
Short name T529
Test name
Test status
Simulation time 201828630 ps
CPU time 2.92 seconds
Started Apr 23 01:57:31 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 206972 kb
Host smart-485e9102-11a5-4fba-8b43-f8c8aaaaa52a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405002147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2405002147
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2839775009
Short name T680
Test name
Test status
Simulation time 63387957 ps
CPU time 2.48 seconds
Started Apr 23 01:57:32 PM PDT 24
Finished Apr 23 01:57:35 PM PDT 24
Peak memory 208880 kb
Host smart-f6847531-3796-4c61-a09e-63525dc07419
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839775009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2839775009
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2053704235
Short name T751
Test name
Test status
Simulation time 60719928 ps
CPU time 2.18 seconds
Started Apr 23 01:57:35 PM PDT 24
Finished Apr 23 01:57:38 PM PDT 24
Peak memory 214484 kb
Host smart-97ae1039-2ac2-4163-acfe-02ffb311e81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053704235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2053704235
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1080646509
Short name T449
Test name
Test status
Simulation time 50839975 ps
CPU time 2.58 seconds
Started Apr 23 01:57:31 PM PDT 24
Finished Apr 23 01:57:34 PM PDT 24
Peak memory 208688 kb
Host smart-1392341c-55cf-4c3f-bbdd-f60d13a06a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080646509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1080646509
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3269895512
Short name T217
Test name
Test status
Simulation time 599417913 ps
CPU time 20.4 seconds
Started Apr 23 01:57:35 PM PDT 24
Finished Apr 23 01:57:56 PM PDT 24
Peak memory 222776 kb
Host smart-b925419f-bdce-474a-b876-78ffe99af218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269895512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3269895512
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1465593850
Short name T704
Test name
Test status
Simulation time 1054078681 ps
CPU time 11.23 seconds
Started Apr 23 01:57:30 PM PDT 24
Finished Apr 23 01:57:42 PM PDT 24
Peak memory 209028 kb
Host smart-6b4e28b9-26ab-43bd-b0fa-a6cc243ac632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465593850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1465593850
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2567062039
Short name T567
Test name
Test status
Simulation time 479584357 ps
CPU time 9.76 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:57:47 PM PDT 24
Peak memory 210580 kb
Host smart-dc90168f-fd63-4d7b-b592-1d249f61d082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567062039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2567062039
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3882503820
Short name T669
Test name
Test status
Simulation time 18218266 ps
CPU time 0.95 seconds
Started Apr 23 01:57:41 PM PDT 24
Finished Apr 23 01:57:42 PM PDT 24
Peak memory 206284 kb
Host smart-da380d9f-db1e-4879-9ccd-5b979b36a5b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882503820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3882503820
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4123347398
Short name T408
Test name
Test status
Simulation time 50972062 ps
CPU time 3.84 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:57:42 PM PDT 24
Peak memory 215528 kb
Host smart-51a24b97-fe5a-420f-aaff-7109397b79a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123347398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4123347398
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4186996048
Short name T21
Test name
Test status
Simulation time 128952480 ps
CPU time 2.19 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:57:40 PM PDT 24
Peak memory 216924 kb
Host smart-9680dd15-fb7d-4e89-8eb8-6df248b36191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186996048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4186996048
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2099117683
Short name T440
Test name
Test status
Simulation time 47972492 ps
CPU time 1.83 seconds
Started Apr 23 01:57:36 PM PDT 24
Finished Apr 23 01:57:39 PM PDT 24
Peak memory 207380 kb
Host smart-24ec1c85-240d-412e-876a-f4267ba94f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099117683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2099117683
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.507177731
Short name T798
Test name
Test status
Simulation time 4290821287 ps
CPU time 46.86 seconds
Started Apr 23 01:57:40 PM PDT 24
Finished Apr 23 01:58:28 PM PDT 24
Peak memory 222872 kb
Host smart-2483f1c9-8562-432c-b744-469afc083afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507177731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.507177731
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_random.3544501595
Short name T371
Test name
Test status
Simulation time 117179315 ps
CPU time 4.19 seconds
Started Apr 23 01:57:36 PM PDT 24
Finished Apr 23 01:57:41 PM PDT 24
Peak memory 209084 kb
Host smart-63392574-07bc-42be-a0e4-9e43f36dfeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544501595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3544501595
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2593401621
Short name T400
Test name
Test status
Simulation time 2173961813 ps
CPU time 8.15 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:57:45 PM PDT 24
Peak memory 207476 kb
Host smart-8c8d8b2a-dd51-4420-8272-b72622cdba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593401621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2593401621
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3613531541
Short name T646
Test name
Test status
Simulation time 44976543 ps
CPU time 2.87 seconds
Started Apr 23 01:57:35 PM PDT 24
Finished Apr 23 01:57:39 PM PDT 24
Peak memory 208580 kb
Host smart-0bb1b111-24be-4ba4-b3dc-6611e5d87c25
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613531541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3613531541
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1160571240
Short name T638
Test name
Test status
Simulation time 600256217 ps
CPU time 5.03 seconds
Started Apr 23 01:57:34 PM PDT 24
Finished Apr 23 01:57:40 PM PDT 24
Peak memory 207976 kb
Host smart-ed7600a0-f1e6-4a1c-a978-4ec820fbdb14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160571240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1160571240
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3449046000
Short name T854
Test name
Test status
Simulation time 226907652 ps
CPU time 6.64 seconds
Started Apr 23 01:57:35 PM PDT 24
Finished Apr 23 01:57:42 PM PDT 24
Peak memory 208948 kb
Host smart-358bfdb7-9754-4c37-9043-523f16ca33ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449046000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3449046000
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2315291554
Short name T353
Test name
Test status
Simulation time 102736316 ps
CPU time 3.25 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:57:41 PM PDT 24
Peak memory 210272 kb
Host smart-5776825e-86be-4335-a148-886d2b4da238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315291554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2315291554
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1911359001
Short name T863
Test name
Test status
Simulation time 1332149893 ps
CPU time 13.82 seconds
Started Apr 23 01:57:36 PM PDT 24
Finished Apr 23 01:57:50 PM PDT 24
Peak memory 208504 kb
Host smart-def54b62-8601-42f6-b721-64645f991de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911359001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1911359001
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2147246130
Short name T236
Test name
Test status
Simulation time 9947824533 ps
CPU time 32.88 seconds
Started Apr 23 01:57:41 PM PDT 24
Finished Apr 23 01:58:15 PM PDT 24
Peak memory 216968 kb
Host smart-2e50eec3-9ba5-46dc-b1bd-11148da4acb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147246130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2147246130
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1444249909
Short name T319
Test name
Test status
Simulation time 2068194492 ps
CPU time 7.04 seconds
Started Apr 23 01:57:35 PM PDT 24
Finished Apr 23 01:57:42 PM PDT 24
Peak memory 214560 kb
Host smart-0d522419-c7b0-487f-9ae4-ea74a3a507dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444249909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1444249909
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1844943765
Short name T461
Test name
Test status
Simulation time 44015247 ps
CPU time 1.75 seconds
Started Apr 23 01:57:40 PM PDT 24
Finished Apr 23 01:57:43 PM PDT 24
Peak memory 210068 kb
Host smart-563820a2-9882-4db3-9fe8-df0ea93a6d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844943765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1844943765
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3523666648
Short name T519
Test name
Test status
Simulation time 80057336 ps
CPU time 0.83 seconds
Started Apr 23 01:57:41 PM PDT 24
Finished Apr 23 01:57:43 PM PDT 24
Peak memory 206068 kb
Host smart-2835bb10-2dd5-44e7-83db-79093d601b37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523666648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3523666648
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2265805120
Short name T225
Test name
Test status
Simulation time 154283161 ps
CPU time 2.61 seconds
Started Apr 23 01:57:38 PM PDT 24
Finished Apr 23 01:57:42 PM PDT 24
Peak memory 214536 kb
Host smart-ba799f50-0f11-434f-b9b3-95fc8bbea255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265805120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2265805120
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3849597216
Short name T825
Test name
Test status
Simulation time 778882043 ps
CPU time 6.18 seconds
Started Apr 23 01:57:40 PM PDT 24
Finished Apr 23 01:57:46 PM PDT 24
Peak memory 209312 kb
Host smart-10223e25-bb53-441d-ae56-1dd676218db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849597216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3849597216
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2470742588
Short name T756
Test name
Test status
Simulation time 139201470 ps
CPU time 2.05 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:57:40 PM PDT 24
Peak memory 207664 kb
Host smart-baedaff4-baaa-4f89-a767-72567e0d0904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470742588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2470742588
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1757257991
Short name T290
Test name
Test status
Simulation time 1373925639 ps
CPU time 13.72 seconds
Started Apr 23 01:57:40 PM PDT 24
Finished Apr 23 01:57:54 PM PDT 24
Peak memory 214552 kb
Host smart-6a249ad9-4780-43c3-8b2d-3ff5ebbf966e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757257991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1757257991
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3007320818
Short name T23
Test name
Test status
Simulation time 353678633 ps
CPU time 9.98 seconds
Started Apr 23 01:57:42 PM PDT 24
Finished Apr 23 01:57:52 PM PDT 24
Peak memory 211684 kb
Host smart-e69584b5-9d7f-4016-9682-3dab532fd047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007320818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3007320818
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.4144339874
Short name T851
Test name
Test status
Simulation time 35894818 ps
CPU time 2.23 seconds
Started Apr 23 01:57:42 PM PDT 24
Finished Apr 23 01:57:45 PM PDT 24
Peak memory 220612 kb
Host smart-ab08df3a-878f-4301-b2ac-e5538927304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144339874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.4144339874
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3615990570
Short name T200
Test name
Test status
Simulation time 1818113831 ps
CPU time 57.13 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:58:35 PM PDT 24
Peak memory 214556 kb
Host smart-e096b9bf-804d-4a46-afc2-89b30a36bd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615990570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3615990570
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3169925775
Short name T744
Test name
Test status
Simulation time 535386762 ps
CPU time 6.61 seconds
Started Apr 23 01:57:38 PM PDT 24
Finished Apr 23 01:57:45 PM PDT 24
Peak memory 208356 kb
Host smart-05fb9a44-923a-41d3-8a42-d52455ce5b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169925775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3169925775
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3490698759
Short name T257
Test name
Test status
Simulation time 228467409 ps
CPU time 6.61 seconds
Started Apr 23 01:57:37 PM PDT 24
Finished Apr 23 01:57:44 PM PDT 24
Peak memory 208484 kb
Host smart-3f546872-f8f7-4142-999c-45227950b1ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490698759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3490698759
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.47281396
Short name T736
Test name
Test status
Simulation time 583858634 ps
CPU time 20.03 seconds
Started Apr 23 01:57:38 PM PDT 24
Finished Apr 23 01:57:59 PM PDT 24
Peak memory 208012 kb
Host smart-8092a35d-dd2f-45f0-a49b-cd71743e79b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47281396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.47281396
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1365576766
Short name T493
Test name
Test status
Simulation time 252671819 ps
CPU time 3.01 seconds
Started Apr 23 01:57:40 PM PDT 24
Finished Apr 23 01:57:44 PM PDT 24
Peak memory 208180 kb
Host smart-9400062d-ece9-4c87-b51b-714f91dfc0fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365576766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1365576766
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3189187258
Short name T786
Test name
Test status
Simulation time 434483625 ps
CPU time 3.4 seconds
Started Apr 23 01:57:39 PM PDT 24
Finished Apr 23 01:57:43 PM PDT 24
Peak memory 218348 kb
Host smart-7494dfee-f635-4868-91fb-146b20de8cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189187258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3189187258
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1285964205
Short name T748
Test name
Test status
Simulation time 169864956 ps
CPU time 4.56 seconds
Started Apr 23 01:57:39 PM PDT 24
Finished Apr 23 01:57:44 PM PDT 24
Peak memory 208552 kb
Host smart-9669e9c3-c96c-4258-ac0e-8f3cc4b3a4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285964205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1285964205
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.72468088
Short name T167
Test name
Test status
Simulation time 282077560 ps
CPU time 9.8 seconds
Started Apr 23 01:57:38 PM PDT 24
Finished Apr 23 01:57:49 PM PDT 24
Peak memory 222808 kb
Host smart-249c9f1f-16df-40e3-8dec-cbcbbec83a27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72468088 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.72468088
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.692400090
Short name T333
Test name
Test status
Simulation time 1095525610 ps
CPU time 35.9 seconds
Started Apr 23 01:57:39 PM PDT 24
Finished Apr 23 01:58:15 PM PDT 24
Peak memory 217488 kb
Host smart-af3c11c7-fc15-4b56-ac8c-c59feb102a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692400090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.692400090
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2360387613
Short name T389
Test name
Test status
Simulation time 499822953 ps
CPU time 6.82 seconds
Started Apr 23 01:57:41 PM PDT 24
Finished Apr 23 01:57:48 PM PDT 24
Peak memory 210256 kb
Host smart-a133089c-29cc-4ae6-b4fd-e7a9e45ec58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360387613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2360387613
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4170824289
Short name T671
Test name
Test status
Simulation time 46644159 ps
CPU time 0.75 seconds
Started Apr 23 01:55:10 PM PDT 24
Finished Apr 23 01:55:12 PM PDT 24
Peak memory 206188 kb
Host smart-8dd239f9-c1ac-4671-8b8f-a702198c5d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170824289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4170824289
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1593440672
Short name T415
Test name
Test status
Simulation time 376477058 ps
CPU time 6.12 seconds
Started Apr 23 01:55:05 PM PDT 24
Finished Apr 23 01:55:11 PM PDT 24
Peak memory 214592 kb
Host smart-caa1349a-361b-423a-95a2-ab404d81227c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593440672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1593440672
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.4169275722
Short name T627
Test name
Test status
Simulation time 354478344 ps
CPU time 2.84 seconds
Started Apr 23 01:55:00 PM PDT 24
Finished Apr 23 01:55:04 PM PDT 24
Peak memory 217808 kb
Host smart-352a9b69-49db-4f9b-8747-6b7e0e58cb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169275722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.4169275722
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3532764112
Short name T47
Test name
Test status
Simulation time 31083770 ps
CPU time 1.69 seconds
Started Apr 23 01:55:01 PM PDT 24
Finished Apr 23 01:55:03 PM PDT 24
Peak memory 209600 kb
Host smart-f58dcdc5-3564-4fbd-9ec5-2c8ba25753fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532764112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3532764112
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4038773571
Short name T326
Test name
Test status
Simulation time 4849013866 ps
CPU time 47.61 seconds
Started Apr 23 01:55:02 PM PDT 24
Finished Apr 23 01:55:50 PM PDT 24
Peak memory 220168 kb
Host smart-3adf6c75-0304-4699-9124-0d066de36cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038773571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4038773571
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1434182020
Short name T101
Test name
Test status
Simulation time 557301433 ps
CPU time 4.28 seconds
Started Apr 23 01:54:59 PM PDT 24
Finished Apr 23 01:55:04 PM PDT 24
Peak memory 222764 kb
Host smart-cef7ca1f-3974-4a68-8ea6-fc2bb37fab19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434182020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1434182020
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2425613277
Short name T708
Test name
Test status
Simulation time 1211784454 ps
CPU time 13.64 seconds
Started Apr 23 01:55:01 PM PDT 24
Finished Apr 23 01:55:15 PM PDT 24
Peak memory 209960 kb
Host smart-cc02b0ff-80af-4e7e-8b1d-7866e4e5cdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425613277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2425613277
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2149223826
Short name T134
Test name
Test status
Simulation time 541458923 ps
CPU time 4.83 seconds
Started Apr 23 01:55:01 PM PDT 24
Finished Apr 23 01:55:06 PM PDT 24
Peak memory 208628 kb
Host smart-a6ff64e9-c463-4b39-9696-ac2e13118858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149223826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2149223826
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3045587854
Short name T675
Test name
Test status
Simulation time 962244134 ps
CPU time 6.71 seconds
Started Apr 23 01:55:02 PM PDT 24
Finished Apr 23 01:55:09 PM PDT 24
Peak memory 208132 kb
Host smart-f6ba90ba-77b0-44ad-ac32-d467c58f337f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045587854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3045587854
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.4040204330
Short name T817
Test name
Test status
Simulation time 112408476 ps
CPU time 3.74 seconds
Started Apr 23 01:55:00 PM PDT 24
Finished Apr 23 01:55:04 PM PDT 24
Peak memory 208912 kb
Host smart-9a3a9c12-add9-4e2f-9d9f-7128a60ad658
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040204330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.4040204330
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1138087058
Short name T852
Test name
Test status
Simulation time 153824204 ps
CPU time 4.63 seconds
Started Apr 23 01:55:01 PM PDT 24
Finished Apr 23 01:55:06 PM PDT 24
Peak memory 206864 kb
Host smart-af9a2541-a0a5-4886-a6f3-97b7eb73e872
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138087058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1138087058
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.524439886
Short name T504
Test name
Test status
Simulation time 52802016 ps
CPU time 1.66 seconds
Started Apr 23 01:55:00 PM PDT 24
Finished Apr 23 01:55:03 PM PDT 24
Peak memory 207692 kb
Host smart-9c182fd6-42f4-4120-aefa-acb786d6dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524439886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.524439886
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3155943236
Short name T898
Test name
Test status
Simulation time 86734944 ps
CPU time 3.75 seconds
Started Apr 23 01:54:58 PM PDT 24
Finished Apr 23 01:55:02 PM PDT 24
Peak memory 206920 kb
Host smart-5ba4e5c8-7ce5-4fc5-a43d-b46e4b3e6e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155943236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3155943236
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.700490175
Short name T198
Test name
Test status
Simulation time 73534666 ps
CPU time 4.06 seconds
Started Apr 23 01:55:00 PM PDT 24
Finished Apr 23 01:55:04 PM PDT 24
Peak memory 210124 kb
Host smart-fab2aec9-220d-4b24-bc14-d2b05ab557a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700490175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.700490175
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.26876694
Short name T157
Test name
Test status
Simulation time 2279323151 ps
CPU time 11.88 seconds
Started Apr 23 01:55:01 PM PDT 24
Finished Apr 23 01:55:14 PM PDT 24
Peak memory 211224 kb
Host smart-bfa7947c-543c-47b9-8772-f007b8618206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26876694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.26876694
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1486974552
Short name T617
Test name
Test status
Simulation time 13607935 ps
CPU time 0.74 seconds
Started Apr 23 01:55:07 PM PDT 24
Finished Apr 23 01:55:09 PM PDT 24
Peak memory 206020 kb
Host smart-fbbc2100-c467-4004-9080-93d98694aa57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486974552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1486974552
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2664414860
Short name T850
Test name
Test status
Simulation time 28879788 ps
CPU time 2.5 seconds
Started Apr 23 01:55:09 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 214660 kb
Host smart-afa22c2f-afbf-481f-bcb6-5025f90132d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664414860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2664414860
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2648910683
Short name T882
Test name
Test status
Simulation time 139795348 ps
CPU time 3.85 seconds
Started Apr 23 01:55:09 PM PDT 24
Finished Apr 23 01:55:15 PM PDT 24
Peak memory 209188 kb
Host smart-92756c4d-98c4-47c4-bba2-2e14990ca476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648910683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2648910683
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2256548476
Short name T662
Test name
Test status
Simulation time 383345226 ps
CPU time 2.59 seconds
Started Apr 23 01:55:07 PM PDT 24
Finished Apr 23 01:55:10 PM PDT 24
Peak memory 209840 kb
Host smart-4379c5b6-439e-407b-9aaf-22149b39fbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256548476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2256548476
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.635270745
Short name T96
Test name
Test status
Simulation time 2934745915 ps
CPU time 39.58 seconds
Started Apr 23 01:55:10 PM PDT 24
Finished Apr 23 01:55:51 PM PDT 24
Peak memory 218936 kb
Host smart-4814e39e-d8fd-42e4-98d9-a61f0eab29ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635270745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.635270745
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.528967094
Short name T673
Test name
Test status
Simulation time 67382760 ps
CPU time 1.47 seconds
Started Apr 23 01:55:03 PM PDT 24
Finished Apr 23 01:55:05 PM PDT 24
Peak memory 206244 kb
Host smart-5c8c8814-8325-4e08-b1bc-b11df2a93371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528967094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.528967094
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1000496430
Short name T611
Test name
Test status
Simulation time 86722674 ps
CPU time 3.29 seconds
Started Apr 23 01:55:08 PM PDT 24
Finished Apr 23 01:55:11 PM PDT 24
Peak memory 207264 kb
Host smart-5622bb30-b9bb-4811-bcae-c72b9607c67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000496430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1000496430
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1057834974
Short name T861
Test name
Test status
Simulation time 347857700 ps
CPU time 2.69 seconds
Started Apr 23 01:55:07 PM PDT 24
Finished Apr 23 01:55:10 PM PDT 24
Peak memory 206948 kb
Host smart-e048f2ac-401a-46ed-b4a6-57c765f59ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057834974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1057834974
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.64611914
Short name T539
Test name
Test status
Simulation time 394871160 ps
CPU time 5.29 seconds
Started Apr 23 01:55:03 PM PDT 24
Finished Apr 23 01:55:09 PM PDT 24
Peak memory 206776 kb
Host smart-327500e9-8058-4f9f-b3bc-a1d44c2813c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64611914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.64611914
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.312269691
Short name T471
Test name
Test status
Simulation time 1041164797 ps
CPU time 8.58 seconds
Started Apr 23 01:55:09 PM PDT 24
Finished Apr 23 01:55:19 PM PDT 24
Peak memory 208980 kb
Host smart-19c6defc-27a7-40f8-807c-c941c7519143
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312269691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.312269691
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.741979925
Short name T894
Test name
Test status
Simulation time 25641778 ps
CPU time 2.11 seconds
Started Apr 23 01:55:08 PM PDT 24
Finished Apr 23 01:55:12 PM PDT 24
Peak memory 209916 kb
Host smart-0a5dc6d9-a20a-4879-941c-a5f8847151ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741979925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.741979925
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3018817973
Short name T484
Test name
Test status
Simulation time 344307621 ps
CPU time 3.51 seconds
Started Apr 23 01:55:08 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 207072 kb
Host smart-e34125b3-686f-4214-a144-d3a54687a691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018817973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3018817973
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2590125709
Short name T71
Test name
Test status
Simulation time 221137194 ps
CPU time 6.83 seconds
Started Apr 23 01:55:09 PM PDT 24
Finished Apr 23 01:55:17 PM PDT 24
Peak memory 218532 kb
Host smart-f5ebccde-47c9-46df-83b1-c811d21cb6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590125709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2590125709
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.281565712
Short name T715
Test name
Test status
Simulation time 361049296 ps
CPU time 5.88 seconds
Started Apr 23 01:55:08 PM PDT 24
Finished Apr 23 01:55:16 PM PDT 24
Peak memory 218424 kb
Host smart-91a2058b-6196-4e5e-b319-12b44a03f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281565712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.281565712
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4174978521
Short name T156
Test name
Test status
Simulation time 52688497 ps
CPU time 2.75 seconds
Started Apr 23 01:55:09 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 210388 kb
Host smart-55f20c4d-8d0b-4e85-81dd-529dc70db007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174978521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4174978521
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3827916375
Short name T765
Test name
Test status
Simulation time 13048196 ps
CPU time 0.89 seconds
Started Apr 23 01:55:13 PM PDT 24
Finished Apr 23 01:55:15 PM PDT 24
Peak memory 206128 kb
Host smart-db1cc04b-10d6-4f08-bd9f-ca5314da2f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827916375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3827916375
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3931280967
Short name T407
Test name
Test status
Simulation time 49772234 ps
CPU time 3.47 seconds
Started Apr 23 01:55:08 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 214664 kb
Host smart-c9c6e95f-477c-4256-b89f-16b834a902f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931280967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3931280967
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.613124509
Short name T40
Test name
Test status
Simulation time 3308752434 ps
CPU time 4.61 seconds
Started Apr 23 01:55:10 PM PDT 24
Finished Apr 23 01:55:16 PM PDT 24
Peak memory 210048 kb
Host smart-8cc05e41-9002-42d7-94f8-c651f9c4fb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613124509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.613124509
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2270292795
Short name T900
Test name
Test status
Simulation time 106858766 ps
CPU time 2.37 seconds
Started Apr 23 01:55:11 PM PDT 24
Finished Apr 23 01:55:14 PM PDT 24
Peak memory 210608 kb
Host smart-bbeaf859-a52b-41c6-9e2a-5b0fb829e4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270292795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2270292795
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.715196979
Short name T232
Test name
Test status
Simulation time 553105688 ps
CPU time 5.29 seconds
Started Apr 23 01:55:15 PM PDT 24
Finished Apr 23 01:55:21 PM PDT 24
Peak memory 212072 kb
Host smart-f30decbd-4fee-4961-b832-ab05a69723b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715196979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.715196979
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.297822102
Short name T578
Test name
Test status
Simulation time 81209820 ps
CPU time 3.76 seconds
Started Apr 23 01:55:10 PM PDT 24
Finished Apr 23 01:55:15 PM PDT 24
Peak memory 209928 kb
Host smart-0e72766c-5141-492b-b59c-a3bfc970b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297822102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.297822102
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2475799278
Short name T676
Test name
Test status
Simulation time 146842060 ps
CPU time 3.6 seconds
Started Apr 23 01:55:15 PM PDT 24
Finished Apr 23 01:55:20 PM PDT 24
Peak memory 208252 kb
Host smart-d0507ae2-1e6c-43c4-ae39-8ab2406c84d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475799278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2475799278
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1267165120
Short name T885
Test name
Test status
Simulation time 234270080 ps
CPU time 3.92 seconds
Started Apr 23 01:55:08 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 208688 kb
Host smart-e8c9a182-987f-4547-a56d-8ad77c6058b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267165120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1267165120
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2161522741
Short name T668
Test name
Test status
Simulation time 247246000 ps
CPU time 6.84 seconds
Started Apr 23 01:55:09 PM PDT 24
Finished Apr 23 01:55:17 PM PDT 24
Peak memory 208464 kb
Host smart-2a681b09-2e25-4246-aa4c-febad90f5e95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161522741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2161522741
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3131361554
Short name T324
Test name
Test status
Simulation time 204160800 ps
CPU time 3.72 seconds
Started Apr 23 01:55:08 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 207668 kb
Host smart-542712fb-05dd-44ac-8a07-f7a732cbd4da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131361554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3131361554
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2528348648
Short name T489
Test name
Test status
Simulation time 320219537 ps
CPU time 3.63 seconds
Started Apr 23 01:55:15 PM PDT 24
Finished Apr 23 01:55:19 PM PDT 24
Peak memory 208908 kb
Host smart-185d2be7-5c6c-4141-8a1c-ea6133d3cc70
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528348648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2528348648
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3257909917
Short name T625
Test name
Test status
Simulation time 37376516 ps
CPU time 2.58 seconds
Started Apr 23 01:55:09 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 216168 kb
Host smart-f5aeaae1-d592-43aa-984c-cd3a2dcedeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257909917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3257909917
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1595889440
Short name T896
Test name
Test status
Simulation time 714535753 ps
CPU time 5.16 seconds
Started Apr 23 01:55:09 PM PDT 24
Finished Apr 23 01:55:15 PM PDT 24
Peak memory 207932 kb
Host smart-0cababff-d8d6-4a07-9687-5f0deb7548c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595889440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1595889440
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.4248759402
Short name T830
Test name
Test status
Simulation time 3792076883 ps
CPU time 24.88 seconds
Started Apr 23 01:55:10 PM PDT 24
Finished Apr 23 01:55:36 PM PDT 24
Peak memory 210128 kb
Host smart-3a771f60-ad20-4729-b420-026e1f1d69fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248759402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4248759402
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.516310480
Short name T229
Test name
Test status
Simulation time 1156831781 ps
CPU time 12.81 seconds
Started Apr 23 01:55:10 PM PDT 24
Finished Apr 23 01:55:24 PM PDT 24
Peak memory 210140 kb
Host smart-6d7135cb-0576-4db9-a3ab-4cfece377225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516310480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.516310480
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3320652401
Short name T437
Test name
Test status
Simulation time 46155111 ps
CPU time 1.64 seconds
Started Apr 23 01:55:10 PM PDT 24
Finished Apr 23 01:55:13 PM PDT 24
Peak memory 209852 kb
Host smart-5d7e093d-ce78-4692-aa38-f97c2b3790ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320652401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3320652401
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.939378173
Short name T428
Test name
Test status
Simulation time 28486181 ps
CPU time 0.91 seconds
Started Apr 23 01:55:18 PM PDT 24
Finished Apr 23 01:55:20 PM PDT 24
Peak memory 206184 kb
Host smart-a0ae8323-39b6-46f8-a336-22fdb7c2320f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939378173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.939378173
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3490703967
Short name T392
Test name
Test status
Simulation time 54604547 ps
CPU time 3.66 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:55:24 PM PDT 24
Peak memory 214656 kb
Host smart-e18447cc-4a28-4e71-b70e-65a115390730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490703967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3490703967
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2158724735
Short name T522
Test name
Test status
Simulation time 415404299 ps
CPU time 5.45 seconds
Started Apr 23 01:55:18 PM PDT 24
Finished Apr 23 01:55:24 PM PDT 24
Peak memory 210412 kb
Host smart-e7418ad3-3aee-470b-9784-5d2b16376532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158724735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2158724735
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2344087645
Short name T73
Test name
Test status
Simulation time 111518194 ps
CPU time 3 seconds
Started Apr 23 01:55:14 PM PDT 24
Finished Apr 23 01:55:17 PM PDT 24
Peak memory 207372 kb
Host smart-c8bb8061-4044-4264-976d-e6524c59c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344087645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2344087645
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.248120573
Short name T91
Test name
Test status
Simulation time 2940074975 ps
CPU time 80.92 seconds
Started Apr 23 01:55:17 PM PDT 24
Finished Apr 23 01:56:39 PM PDT 24
Peak memory 214536 kb
Host smart-5b816080-d243-4cbb-a36d-f9e7c45d8482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248120573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.248120573
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4204937470
Short name T792
Test name
Test status
Simulation time 106547600 ps
CPU time 2.87 seconds
Started Apr 23 01:55:17 PM PDT 24
Finished Apr 23 01:55:21 PM PDT 24
Peak memory 214480 kb
Host smart-7ec35054-6fe7-4f54-8e78-fb9e8aae92fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204937470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4204937470
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1537658481
Short name T42
Test name
Test status
Simulation time 123123227 ps
CPU time 1.95 seconds
Started Apr 23 01:55:17 PM PDT 24
Finished Apr 23 01:55:20 PM PDT 24
Peak memory 215540 kb
Host smart-7dab8e3b-4528-4974-82bd-bd0d8a6cea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537658481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1537658481
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2356969203
Short name T309
Test name
Test status
Simulation time 114565969 ps
CPU time 5.08 seconds
Started Apr 23 01:55:13 PM PDT 24
Finished Apr 23 01:55:19 PM PDT 24
Peak memory 207280 kb
Host smart-d99f1c74-5845-4215-b078-c4ab1801a293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356969203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2356969203
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2926732676
Short name T639
Test name
Test status
Simulation time 898764913 ps
CPU time 6.96 seconds
Started Apr 23 01:55:15 PM PDT 24
Finished Apr 23 01:55:22 PM PDT 24
Peak memory 207904 kb
Host smart-2eb9dc0e-cbd6-4c78-8808-641184cd2a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926732676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2926732676
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4086758599
Short name T563
Test name
Test status
Simulation time 159073971 ps
CPU time 4.08 seconds
Started Apr 23 01:55:16 PM PDT 24
Finished Apr 23 01:55:21 PM PDT 24
Peak memory 207000 kb
Host smart-6d2cc9b0-a42c-46b6-b069-8475d43d67da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086758599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4086758599
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.541849072
Short name T396
Test name
Test status
Simulation time 133494803 ps
CPU time 3.16 seconds
Started Apr 23 01:55:17 PM PDT 24
Finished Apr 23 01:55:21 PM PDT 24
Peak memory 206444 kb
Host smart-75350046-fc39-4753-b7cb-4ef8d084dbcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541849072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.541849072
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.4139274907
Short name T656
Test name
Test status
Simulation time 325382808 ps
CPU time 3.28 seconds
Started Apr 23 01:55:15 PM PDT 24
Finished Apr 23 01:55:19 PM PDT 24
Peak memory 206916 kb
Host smart-8ed316d8-e850-4295-896c-aeea080575d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139274907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.4139274907
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1197818070
Short name T714
Test name
Test status
Simulation time 74012749 ps
CPU time 1.61 seconds
Started Apr 23 01:55:15 PM PDT 24
Finished Apr 23 01:55:18 PM PDT 24
Peak memory 207536 kb
Host smart-2e132075-ef0f-4937-8f56-8f4965efbef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197818070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1197818070
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1086940430
Short name T726
Test name
Test status
Simulation time 1771710829 ps
CPU time 4.65 seconds
Started Apr 23 01:55:14 PM PDT 24
Finished Apr 23 01:55:19 PM PDT 24
Peak memory 208612 kb
Host smart-83acb4a6-5c6c-43e6-bcae-65adcb1f90df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086940430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1086940430
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1853480831
Short name T176
Test name
Test status
Simulation time 791088506 ps
CPU time 19.23 seconds
Started Apr 23 01:55:18 PM PDT 24
Finished Apr 23 01:55:37 PM PDT 24
Peak memory 215928 kb
Host smart-e5716cf8-c282-4703-87b8-95fb5ce1d2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853480831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1853480831
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.438050760
Short name T78
Test name
Test status
Simulation time 1026068836 ps
CPU time 9.22 seconds
Started Apr 23 01:55:21 PM PDT 24
Finished Apr 23 01:55:31 PM PDT 24
Peak memory 222856 kb
Host smart-8860d40a-8842-49e2-a4b9-7e0e50affa50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438050760 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.438050760
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2903957304
Short name T754
Test name
Test status
Simulation time 129453858 ps
CPU time 4.19 seconds
Started Apr 23 01:55:12 PM PDT 24
Finished Apr 23 01:55:17 PM PDT 24
Peak memory 209100 kb
Host smart-395dfc9a-ebd6-4577-b8e0-5c8c91fc1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903957304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2903957304
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1169240212
Short name T470
Test name
Test status
Simulation time 452550402 ps
CPU time 3.45 seconds
Started Apr 23 01:55:17 PM PDT 24
Finished Apr 23 01:55:21 PM PDT 24
Peak memory 210328 kb
Host smart-49e3bdb8-cc69-41a8-9a5b-77d2d92426f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169240212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1169240212
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2954236991
Short name T645
Test name
Test status
Simulation time 8962874 ps
CPU time 0.8 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:55:21 PM PDT 24
Peak memory 206176 kb
Host smart-6e9ad02f-1704-4153-aaff-cc70e89a8f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954236991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2954236991
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.4059112737
Short name T292
Test name
Test status
Simulation time 62201333 ps
CPU time 2.49 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:55:23 PM PDT 24
Peak memory 214568 kb
Host smart-2acb8ef4-b2dd-4128-b91f-5f1a8c9f5166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4059112737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.4059112737
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2852506377
Short name T536
Test name
Test status
Simulation time 211610463 ps
CPU time 2.84 seconds
Started Apr 23 01:55:21 PM PDT 24
Finished Apr 23 01:55:24 PM PDT 24
Peak memory 209084 kb
Host smart-54221410-77a1-4273-8027-748e280b980f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852506377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2852506377
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.657574801
Short name T393
Test name
Test status
Simulation time 1865469007 ps
CPU time 41.17 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:56:02 PM PDT 24
Peak memory 209184 kb
Host smart-742322ba-3660-4760-a570-5049881b5268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657574801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.657574801
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1826611404
Short name T285
Test name
Test status
Simulation time 467135854 ps
CPU time 6.02 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:55:27 PM PDT 24
Peak memory 214532 kb
Host smart-cb91bd2b-9b6f-42ef-8d25-da7a190203b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826611404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1826611404
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.825645151
Short name T692
Test name
Test status
Simulation time 403205588 ps
CPU time 3.26 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:55:24 PM PDT 24
Peak memory 216828 kb
Host smart-53b72c65-8435-4fc2-95a0-c7f2b591edfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825645151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.825645151
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3826414972
Short name T183
Test name
Test status
Simulation time 266019578 ps
CPU time 3.64 seconds
Started Apr 23 01:55:17 PM PDT 24
Finished Apr 23 01:55:22 PM PDT 24
Peak memory 209040 kb
Host smart-1127ba45-77af-4503-a82d-fa019abe9dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826414972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3826414972
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.551463713
Short name T304
Test name
Test status
Simulation time 402555813 ps
CPU time 8.4 seconds
Started Apr 23 01:55:19 PM PDT 24
Finished Apr 23 01:55:28 PM PDT 24
Peak memory 208732 kb
Host smart-f8099844-99aa-4210-930a-436dbd9a6a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551463713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.551463713
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1382851169
Short name T308
Test name
Test status
Simulation time 249292279 ps
CPU time 3.37 seconds
Started Apr 23 01:55:18 PM PDT 24
Finished Apr 23 01:55:22 PM PDT 24
Peak memory 208692 kb
Host smart-43222a92-36e5-49fb-8f8e-c078e0d076ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382851169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1382851169
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1807187138
Short name T831
Test name
Test status
Simulation time 1086582788 ps
CPU time 7.14 seconds
Started Apr 23 01:55:17 PM PDT 24
Finished Apr 23 01:55:25 PM PDT 24
Peak memory 207716 kb
Host smart-ba33cb5f-b056-4ebc-9d3c-80efe4637360
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807187138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1807187138
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1459800596
Short name T654
Test name
Test status
Simulation time 541712124 ps
CPU time 4.59 seconds
Started Apr 23 01:55:17 PM PDT 24
Finished Apr 23 01:55:23 PM PDT 24
Peak memory 208776 kb
Host smart-0f47cb8b-d457-46be-86f7-bcd6a470d2b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459800596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1459800596
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.249439510
Short name T228
Test name
Test status
Simulation time 107132587 ps
CPU time 3.09 seconds
Started Apr 23 01:55:20 PM PDT 24
Finished Apr 23 01:55:24 PM PDT 24
Peak memory 209360 kb
Host smart-1f286e72-0dde-4694-834f-8575593d83ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249439510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.249439510
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.394637201
Short name T15
Test name
Test status
Simulation time 84153288 ps
CPU time 2.94 seconds
Started Apr 23 01:55:18 PM PDT 24
Finished Apr 23 01:55:22 PM PDT 24
Peak memory 206908 kb
Host smart-6648d5ec-eeb0-4324-99b0-09a497c98829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394637201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.394637201
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3559362166
Short name T179
Test name
Test status
Simulation time 3039777536 ps
CPU time 21.74 seconds
Started Apr 23 01:55:27 PM PDT 24
Finished Apr 23 01:55:50 PM PDT 24
Peak memory 217384 kb
Host smart-f35d0549-8e99-44f9-9a52-cd006dddfed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559362166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3559362166
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.855820656
Short name T729
Test name
Test status
Simulation time 12768752349 ps
CPU time 52.87 seconds
Started Apr 23 01:55:19 PM PDT 24
Finished Apr 23 01:56:12 PM PDT 24
Peak memory 220992 kb
Host smart-52a52dba-cb57-41b9-9d2b-e592846aa7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855820656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.855820656
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.464177399
Short name T607
Test name
Test status
Simulation time 454440147 ps
CPU time 4.2 seconds
Started Apr 23 01:55:21 PM PDT 24
Finished Apr 23 01:55:26 PM PDT 24
Peak memory 210156 kb
Host smart-fdeb0b74-cb57-4457-a131-3a7a50f95b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464177399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.464177399
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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