Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11793

1

T1

4

T2

2

T3

3

auto[Attestation]

8573

1

T1

4

T2

2

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2966	1			T3	2		T4	12		T15	3
auto[Aes]	3722	1			T1	2		T2	1		T3	1
auto[Kmac]	3597	1			T1	2		T2	1		T4	8
auto[Otbn]	3673	1			T2	2		T3	1		T4	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8117	1			T1	8		T2	3		T3	8
auto[OpGenId]	6408	1			T1	4		T3	4		T4	19
auto[OpGenSwOut]	6534	1			T1	4		T3	4		T4	23
auto[OpGenHwOut]	7424	1			T2	4		T4	13		T5	8
auto[OpDisable]	148	1			T4	1		T15	1		T47	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10600

1

T1

8

T2

7

T3

8

auto[OpDoneFail]

18031

1

T1

8

T3

8

T4

54

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6428	1			T1	1		T2	1		T3	1
auto[StInit]	4592	1			T1	2		T2	1		T3	2
auto[StCreatorRootKey]	3114	1			T1	2		T2	1		T3	2
auto[StOwnerIntKey]	2856	1			T1	2		T2	4		T3	2
auto[StOwnerKey]	2422	1			T1	2		T3	2		T4	6
auto[StDisabled]	8126	1			T1	7		T3	7		T4	25
auto[StInvalid]	1093	1			T27	27		T36	17		T40	13

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	319	1			T4	2		T16	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	123	1			T41	1		T35	1		T56	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	83	1			T183	1		T63	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	61	1			T184	1		T183	1		T57	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	68	1			T184	1		T63	1		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	216	1			T3	1		T4	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	38	1			T27	1		T36	2		T55	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	318	1			T4	3		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	125	1			T4	1		T25	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	88	1			T1	1		T3	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	85	1			T1	1		T84	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	74	1			T16	1		T141	1		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	258	1			T4	2		T116	1		T124	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	33	1			T40	1		T55	1		T88	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	327	1			T4	3		T16	2		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	115	1			T187	1		T188	1		T92	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T4	1		T17	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	65	1			T45	1		T7	2		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	54	1			T71	1		T7	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	237	1			T4	1		T16	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	40	1			T27	1		T190	2		T191	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	325	1			T4	2		T17	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	122	1			T116	1		T26	1		T57	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T57	2		T71	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T35	1		T130	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	62	1			T71	1		T45	1		T179	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	217	1			T17	1		T85	1		T117	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	37	1			T27	2		T40	1		T55	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	78	1			T57	1		T190	1		T125	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	145	1			T4	1		T25	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T35	1		T124	1		T193	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	89	1			T3	1		T35	1		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	70	1			T186	1		T183	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	234	1			T4	1		T16	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	30	1			T36	1		T55	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	79	1			T36	3		T57	4		T99	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	149	1			T4	1		T41	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	91	1			T85	1		T187	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	88	1			T62	1		T186	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	56	1			T116	1		T141	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	221	1			T17	2		T193	1		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	23	1			T99	1		T194	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	84	1			T57	4		T93	1		T190	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	123	1			T15	1		T41	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	75	1			T44	1		T64	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	82	1			T17	1		T116	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	56	1			T35	1		T141	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	227	1			T1	2		T4	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	38	1			T36	1		T99	1		T93	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	99	1			T57	1		T99	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	124	1			T25	1		T62	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T85	1		T45	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	61	1			T193	1		T57	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	53	1			T193	1		T192	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	243	1			T3	1		T4	2		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	33	1			T27	1		T36	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	275	1			T4	3		T17	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	141	1			T25	1		T116	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T15	1		T35	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	53	1			T4	1		T182	1		T60	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T124	1		T45	1		T46	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	164	1			T16	1		T84	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	34	1			T27	3		T36	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	484	1			T18	7		T19	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	142	1			T4	1		T54	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	87	1			T41	1		T44	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	111	1			T2	1		T18	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	79	1			T5	1		T197	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	285	1			T17	1		T18	2		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	33	1			T27	1		T55	2		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	434	1			T16	2		T19	1		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	149	1			T43	1		T35	1		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	97	1			T43	1		T41	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T2	1		T85	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	85	1			T141	1		T199	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	284	1			T15	1		T16	1		T117	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	27	1			T88	1		T93	1		T191	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	463	1			T4	2		T16	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	139	1			T15	1		T25	3		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T4	1		T19	1		T41	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T184	1		T187	2		T183	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	82	1			T124	1		T86	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	305	1			T16	1		T17	1		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	26	1			T36	1		T55	1		T99	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T36	1		T57	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T47	1		T85	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	56	1			T4	1		T196	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	62	1			T15	2		T124	1		T71	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T16	1		T188	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	168	1			T4	1		T54	1		T117	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	29	1			T27	1		T55	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	63	1			T60	1		T190	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	149	1			T5	1		T18	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T5	1		T18	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	111	1			T5	1		T17	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	73	1			T16	1		T18	1		T116	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	275	1			T5	4		T18	2		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	35	1			T27	1		T88	2		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	59	1			T4	1		T45	1		T125	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	143	1			T16	1		T47	1		T85	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T41	1		T54	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T43	1		T117	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	83	1			T43	1		T85	1		T116	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	293	1			T4	1		T16	1		T43	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	36	1			T40	1		T99	2		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	55	1			T99	1		T60	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	164	1			T26	1		T67	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	124	1			T117	1		T188	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	102	1			T2	2		T187	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	93	1			T64	2		T57	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	278	1			T4	1		T117	1		T193	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	33	1			T36	1		T55	1		T88	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	195	1			T184	2		T183	2		T63	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	713	1			T3	1		T4	4		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	222	1			T1	2		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	759	1			T4	6		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	197	1			T4	1		T17	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	732	1			T4	4		T16	3		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	201	1			T35	1		T130	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	714	1			T4	2		T17	2		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	212	1			T3	1		T35	2		T117	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	512	1			T4	2		T16	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	218	1			T85	1		T116	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	489	1			T4	1		T17	2		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T17	1		T35	1		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	489	1			T1	2		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	173	1			T85	1		T193	2		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	512	1			T3	1		T4	2		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	180	1			T4	1		T15	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	622	1			T4	3		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	260	1			T2	1		T5	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	961	1			T4	1		T17	1		T18	9
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	264	1			T2	1		T43	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	903	1			T15	1		T16	3		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	281	1			T4	1		T19	1		T41	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	943	1			T4	2		T15	1		T16	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	147	1			T4	1		T15	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	385	1			T4	1		T47	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	277	1			T5	2		T17	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	536	1			T5	5		T16	1		T18	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	275	1			T43	2		T41	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	541	1			T4	2		T16	2		T43	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	295	1			T2	2		T117	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	554	1			T4	1		T117	1		T193	2